drivers/net/iavf/iavf_rxtx_vec_avx2.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2019 Intel Corporation
   3  */
   4
   5 #include "iavf_rxtx_vec_common.h"
   6
   7 #include <x86intrin.h>
   8
   9 #ifndef __INTEL_COMPILER
  10 #pragma GCC diagnostic ignored "-Wcast-qual"
  11 #endif
  12
  13 static inline void
  14 iavf_rxq_rearm(struct iavf_rx_queue *rxq)
  15 {
  16         int i;
  17         uint16_t rx_id;
  18         volatile union iavf_rx_desc *rxdp;
  19         struct rte_mbuf **rxp = &rxq->sw_ring[rxq->rxrearm_start];
  20
  21         rxdp = rxq->rx_ring + rxq->rxrearm_start;
  22
  23         /* Pull 'n' more MBUFs into the software ring */
  24         if (rte_mempool_get_bulk(rxq->mp,
  25                                  (void *)rxp,
  26                                  IAVF_RXQ_REARM_THRESH) < 0) {
  27                 if (rxq->rxrearm_nb + IAVF_RXQ_REARM_THRESH >=
  28                     rxq->nb_rx_desc) {
  29                         __m128i dma_addr0;
  30
  31                         dma_addr0 = _mm_setzero_si128();
  32                         for (i = 0; i < IAVF_VPMD_DESCS_PER_LOOP; i++) {
  33                                 rxp[i] = &rxq->fake_mbuf;
  34                                 _mm_store_si128((__m128i *)&rxdp[i].read,
  35                                                 dma_addr0);
  36                         }
  37                 }
  38                 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed +=
  39                         IAVF_RXQ_REARM_THRESH;
  40                 return;
  41         }
  42
  43 #ifndef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
  44         struct rte_mbuf *mb0, *mb1;
  45         __m128i dma_addr0, dma_addr1;
  46         __m128i hdr_room = _mm_set_epi64x(RTE_PKTMBUF_HEADROOM,
  47                         RTE_PKTMBUF_HEADROOM);
  48         /* Initialize the mbufs in vector, process 2 mbufs in one loop */
  49         for (i = 0; i < IAVF_RXQ_REARM_THRESH; i += 2, rxp += 2) {
  50                 __m128i vaddr0, vaddr1;
  51
  52                 mb0 = rxp[0];
  53                 mb1 = rxp[1];
  54
  55                 /* load buf_addr(lo 64bit) and buf_iova(hi 64bit) */
  56                 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, buf_iova) !=
  57                                 offsetof(struct rte_mbuf, buf_addr) + 8);
  58                 vaddr0 = _mm_loadu_si128((__m128i *)&mb0->buf_addr);
  59                 vaddr1 = _mm_loadu_si128((__m128i *)&mb1->buf_addr);
  60
  61                 /* convert pa to dma_addr hdr/data */
  62                 dma_addr0 = _mm_unpackhi_epi64(vaddr0, vaddr0);
  63                 dma_addr1 = _mm_unpackhi_epi64(vaddr1, vaddr1);
  64
  65                 /* add headroom to pa values */
  66                 dma_addr0 = _mm_add_epi64(dma_addr0, hdr_room);
  67                 dma_addr1 = _mm_add_epi64(dma_addr1, hdr_room);
  68
  69                 /* flush desc with pa dma_addr */
  70                 _mm_store_si128((__m128i *)&rxdp++->read, dma_addr0);
  71                 _mm_store_si128((__m128i *)&rxdp++->read, dma_addr1);
  72         }
  73 #else
  74         struct rte_mbuf *mb0, *mb1, *mb2, *mb3;
  75         __m256i dma_addr0_1, dma_addr2_3;
  76         __m256i hdr_room = _mm256_set1_epi64x(RTE_PKTMBUF_HEADROOM);
  77         /* Initialize the mbufs in vector, process 4 mbufs in one loop */
  78         for (i = 0; i < IAVF_RXQ_REARM_THRESH;
  79                         i += 4, rxp += 4, rxdp += 4) {
  80                 __m128i vaddr0, vaddr1, vaddr2, vaddr3;
  81                 __m256i vaddr0_1, vaddr2_3;
  82
  83                 mb0 = rxp[0];
  84                 mb1 = rxp[1];
  85                 mb2 = rxp[2];
  86                 mb3 = rxp[3];
  87
  88                 /* load buf_addr(lo 64bit) and buf_iova(hi 64bit) */
  89                 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, buf_iova) !=
  90                                 offsetof(struct rte_mbuf, buf_addr) + 8);
  91                 vaddr0 = _mm_loadu_si128((__m128i *)&mb0->buf_addr);
  92                 vaddr1 = _mm_loadu_si128((__m128i *)&mb1->buf_addr);
  93                 vaddr2 = _mm_loadu_si128((__m128i *)&mb2->buf_addr);
  94                 vaddr3 = _mm_loadu_si128((__m128i *)&mb3->buf_addr);
  95
  96                 /**
  97                  * merge 0 & 1, by casting 0 to 256-bit and inserting 1
  98                  * into the high lanes. Similarly for 2 & 3
  99                  */
 100                 vaddr0_1 =
 101                         _mm256_inserti128_si256(_mm256_castsi128_si256(vaddr0),
 102                                                 vaddr1, 1);
 103                 vaddr2_3 =
 104                         _mm256_inserti128_si256(_mm256_castsi128_si256(vaddr2),
 105                                                 vaddr3, 1);
 106
 107                 /* convert pa to dma_addr hdr/data */
 108                 dma_addr0_1 = _mm256_unpackhi_epi64(vaddr0_1, vaddr0_1);
 109                 dma_addr2_3 = _mm256_unpackhi_epi64(vaddr2_3, vaddr2_3);
 110
 111                 /* add headroom to pa values */
 112                 dma_addr0_1 = _mm256_add_epi64(dma_addr0_1, hdr_room);
 113                 dma_addr2_3 = _mm256_add_epi64(dma_addr2_3, hdr_room);
 114
 115                 /* flush desc with pa dma_addr */
 116                 _mm256_store_si256((__m256i *)&rxdp->read, dma_addr0_1);
 117                 _mm256_store_si256((__m256i *)&(rxdp + 2)->read, dma_addr2_3);
 118         }
 119
 120 #endif
 121
 122         rxq->rxrearm_start += IAVF_RXQ_REARM_THRESH;
 123         if (rxq->rxrearm_start >= rxq->nb_rx_desc)
 124                 rxq->rxrearm_start = 0;
 125
 126         rxq->rxrearm_nb -= IAVF_RXQ_REARM_THRESH;
 127
 128         rx_id = (uint16_t)((rxq->rxrearm_start == 0) ?
 129                              (rxq->nb_rx_desc - 1) : (rxq->rxrearm_start - 1));
 130
 131         /* Update the tail pointer on the NIC */
 132         IAVF_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
 133 }
 134
 135 #define PKTLEN_SHIFT     10
 136
 137 static inline uint16_t
 138 _iavf_recv_raw_pkts_vec_avx2(struct iavf_rx_queue *rxq,
 139                              struct rte_mbuf **rx_pkts,
 140                              uint16_t nb_pkts, uint8_t *split_packet)
 141 {
 142 #define IAVF_DESCS_PER_LOOP_AVX 8
 143
 144         /* const uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl; */
 145         const uint32_t *type_table = rxq->vsi->adapter->ptype_tbl;
 146
 147         const __m256i mbuf_init = _mm256_set_epi64x(0, 0,
 148                         0, rxq->mbuf_initializer);
 149         /* struct iavf_rx_entry *sw_ring = &rxq->sw_ring[rxq->rx_tail]; */
 150         struct rte_mbuf **sw_ring = &rxq->sw_ring[rxq->rx_tail];
 151         volatile union iavf_rx_desc *rxdp = rxq->rx_ring + rxq->rx_tail;
 152         const int avx_aligned = ((rxq->rx_tail & 1) == 0);
 153
 154         rte_prefetch0(rxdp);
 155
 156         /* nb_pkts has to be floor-aligned to IAVF_DESCS_PER_LOOP_AVX */
 157         nb_pkts = RTE_ALIGN_FLOOR(nb_pkts, IAVF_DESCS_PER_LOOP_AVX);
 158
 159         /* See if we need to rearm the RX queue - gives the prefetch a bit
 160          * of time to act
 161          */
 162         if (rxq->rxrearm_nb > IAVF_RXQ_REARM_THRESH)
 163                 iavf_rxq_rearm(rxq);
 164
 165         /* Before we start moving massive data around, check to see if
 166          * there is actually a packet available
 167          */
 168         if (!(rxdp->wb.qword1.status_error_len &
 169                         rte_cpu_to_le_32(1 << IAVF_RX_DESC_STATUS_DD_SHIFT)))
 170                 return 0;
 171
 172         /* constants used in processing loop */
 173         const __m256i crc_adjust =
 174                 _mm256_set_epi16
 175                         (/* first descriptor */
 176                          0, 0, 0,       /* ignore non-length fields */
 177                          -rxq->crc_len, /* sub crc on data_len */
 178                          0,             /* ignore high-16bits of pkt_len */
 179                          -rxq->crc_len, /* sub crc on pkt_len */
 180                          0, 0,          /* ignore pkt_type field */
 181                          /* second descriptor */
 182                          0, 0, 0,       /* ignore non-length fields */
 183                          -rxq->crc_len, /* sub crc on data_len */
 184                          0,             /* ignore high-16bits of pkt_len */
 185                          -rxq->crc_len, /* sub crc on pkt_len */
 186                          0, 0           /* ignore pkt_type field */
 187                         );
 188
 189         /* 8 packets DD mask, LSB in each 32-bit value */
 190         const __m256i dd_check = _mm256_set1_epi32(1);
 191
 192         /* 8 packets EOP mask, second-LSB in each 32-bit value */
 193         const __m256i eop_check = _mm256_slli_epi32(dd_check,
 194                         IAVF_RX_DESC_STATUS_EOF_SHIFT);
 195
 196         /* mask to shuffle from desc. to mbuf (2 descriptors)*/
 197         const __m256i shuf_msk =
 198                 _mm256_set_epi8
 199                         (/* first descriptor */
 200                          7, 6, 5, 4,  /* octet 4~7, 32bits rss */
 201                          3, 2,        /* octet 2~3, low 16 bits vlan_macip */
 202                          15, 14,      /* octet 15~14, 16 bits data_len */
 203                          0xFF, 0xFF,  /* skip high 16 bits pkt_len, zero out */
 204                          15, 14,      /* octet 15~14, low 16 bits pkt_len */
 205                          0xFF, 0xFF,  /* pkt_type set as unknown */
 206                          0xFF, 0xFF,  /*pkt_type set as unknown */
 207                          /* second descriptor */
 208                          7, 6, 5, 4,  /* octet 4~7, 32bits rss */
 209                          3, 2,        /* octet 2~3, low 16 bits vlan_macip */
 210                          15, 14,      /* octet 15~14, 16 bits data_len */
 211                          0xFF, 0xFF,  /* skip high 16 bits pkt_len, zero out */
 212                          15, 14,      /* octet 15~14, low 16 bits pkt_len */
 213                          0xFF, 0xFF,  /* pkt_type set as unknown */
 214                          0xFF, 0xFF   /*pkt_type set as unknown */
 215                         );
 216         /**
 217          * compile-time check the above crc and shuffle layout is correct.
 218          * NOTE: the first field (lowest address) is given last in set_epi
 219          * calls above.
 220          */
 221         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, pkt_len) !=
 222                         offsetof(struct rte_mbuf, rx_descriptor_fields1) + 4);
 223         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, data_len) !=
 224                         offsetof(struct rte_mbuf, rx_descriptor_fields1) + 8);
 225         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, vlan_tci) !=
 226                         offsetof(struct rte_mbuf, rx_descriptor_fields1) + 10);
 227         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, hash) !=
 228                         offsetof(struct rte_mbuf, rx_descriptor_fields1) + 12);
 229
 230         /* Status/Error flag masks */
 231         /**
 232          * mask everything except RSS, flow director and VLAN flags
 233          * bit2 is for VLAN tag, bit11 for flow director indication
 234          * bit13:12 for RSS indication. Bits 3-5 of error
 235          * field (bits 22-24) are for IP/L4 checksum errors
 236          */
 237         const __m256i flags_mask =
 238                  _mm256_set1_epi32((1 << 2) | (1 << 11) |
 239                                    (3 << 12) | (7 << 22));
 240         /**
 241          * data to be shuffled by result of flag mask. If VLAN bit is set,
 242          * (bit 2), then position 4 in this array will be used in the
 243          * destination
 244          */
 245         const __m256i vlan_flags_shuf =
 246                 _mm256_set_epi32(0, 0, PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED, 0,
 247                                  0, 0, PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED, 0);
 248         /**
 249          * data to be shuffled by result of flag mask, shifted down 11.
 250          * If RSS/FDIR bits are set, shuffle moves appropriate flags in
 251          * place.
 252          */
 253         const __m256i rss_flags_shuf =
 254                 _mm256_set_epi8(0, 0, 0, 0, 0, 0, 0, 0,
 255                                 PKT_RX_RSS_HASH | PKT_RX_FDIR, PKT_RX_RSS_HASH,
 256                                 0, 0, 0, 0, PKT_RX_FDIR, 0,/* end up 128-bits */
 257                                 0, 0, 0, 0, 0, 0, 0, 0,
 258                                 PKT_RX_RSS_HASH | PKT_RX_FDIR, PKT_RX_RSS_HASH,
 259                                 0, 0, 0, 0, PKT_RX_FDIR, 0);
 260
 261         /**
 262          * data to be shuffled by the result of the flags mask shifted by 22
 263          * bits.  This gives use the l3_l4 flags.
 264          */
 265         const __m256i l3_l4_flags_shuf = _mm256_set_epi8(0, 0, 0, 0, 0, 0, 0, 0,
 266                         /* shift right 1 bit to make sure it not exceed 255 */
 267                         (PKT_RX_EIP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD |
 268                          PKT_RX_IP_CKSUM_BAD) >> 1,
 269                         (PKT_RX_IP_CKSUM_GOOD | PKT_RX_EIP_CKSUM_BAD |
 270                          PKT_RX_L4_CKSUM_BAD) >> 1,
 271                         (PKT_RX_EIP_CKSUM_BAD | PKT_RX_IP_CKSUM_BAD) >> 1,
 272                         (PKT_RX_IP_CKSUM_GOOD | PKT_RX_EIP_CKSUM_BAD) >> 1,
 273                         (PKT_RX_L4_CKSUM_BAD | PKT_RX_IP_CKSUM_BAD) >> 1,
 274                         (PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_BAD) >> 1,
 275                         PKT_RX_IP_CKSUM_BAD >> 1,
 276                         (PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD) >> 1,
 277                         /* second 128-bits */
 278                         0, 0, 0, 0, 0, 0, 0, 0,
 279                         (PKT_RX_EIP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD |
 280                          PKT_RX_IP_CKSUM_BAD) >> 1,
 281                         (PKT_RX_IP_CKSUM_GOOD | PKT_RX_EIP_CKSUM_BAD |
 282                          PKT_RX_L4_CKSUM_BAD) >> 1,
 283                         (PKT_RX_EIP_CKSUM_BAD | PKT_RX_IP_CKSUM_BAD) >> 1,
 284                         (PKT_RX_IP_CKSUM_GOOD | PKT_RX_EIP_CKSUM_BAD) >> 1,
 285                         (PKT_RX_L4_CKSUM_BAD | PKT_RX_IP_CKSUM_BAD) >> 1,
 286                         (PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_BAD) >> 1,
 287                         PKT_RX_IP_CKSUM_BAD >> 1,
 288                         (PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD) >> 1);
 289
 290         const __m256i cksum_mask =
 291                  _mm256_set1_epi32(PKT_RX_IP_CKSUM_GOOD | PKT_RX_IP_CKSUM_BAD |
 292                                    PKT_RX_L4_CKSUM_GOOD | PKT_RX_L4_CKSUM_BAD |
 293                                    PKT_RX_EIP_CKSUM_BAD);
 294
 295         RTE_SET_USED(avx_aligned); /* for 32B descriptors we don't use this */
 296
 297         uint16_t i, received;
 298
 299         for (i = 0, received = 0; i < nb_pkts;
 300              i += IAVF_DESCS_PER_LOOP_AVX,
 301              rxdp += IAVF_DESCS_PER_LOOP_AVX) {
 302                 /* step 1, copy over 8 mbuf pointers to rx_pkts array */
 303                 _mm256_storeu_si256((void *)&rx_pkts[i],
 304                                     _mm256_loadu_si256((void *)&sw_ring[i]));
 305 #ifdef RTE_ARCH_X86_64
 306                 _mm256_storeu_si256
 307                         ((void *)&rx_pkts[i + 4],
 308                          _mm256_loadu_si256((void *)&sw_ring[i + 4]));
 309 #endif
 310
 311                 __m256i raw_desc0_1, raw_desc2_3, raw_desc4_5, raw_desc6_7;
 312 #ifdef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
 313                 /* for AVX we need alignment otherwise loads are not atomic */
 314                 if (avx_aligned) {
 315                         /* load in descriptors, 2 at a time, in reverse order */
 316                         raw_desc6_7 = _mm256_load_si256((void *)(rxdp + 6));
 317                         rte_compiler_barrier();
 318                         raw_desc4_5 = _mm256_load_si256((void *)(rxdp + 4));
 319                         rte_compiler_barrier();
 320                         raw_desc2_3 = _mm256_load_si256((void *)(rxdp + 2));
 321                         rte_compiler_barrier();
 322                         raw_desc0_1 = _mm256_load_si256((void *)(rxdp + 0));
 323                 } else
 324 #endif
 325                 {
 326                         const __m128i raw_desc7 =
 327                                 _mm_load_si128((void *)(rxdp + 7));
 328                         rte_compiler_barrier();
 329                         const __m128i raw_desc6 =
 330                                 _mm_load_si128((void *)(rxdp + 6));
 331                         rte_compiler_barrier();
 332                         const __m128i raw_desc5 =
 333                                 _mm_load_si128((void *)(rxdp + 5));
 334                         rte_compiler_barrier();
 335                         const __m128i raw_desc4 =
 336                                 _mm_load_si128((void *)(rxdp + 4));
 337                         rte_compiler_barrier();
 338                         const __m128i raw_desc3 =
 339                                 _mm_load_si128((void *)(rxdp + 3));
 340                         rte_compiler_barrier();
 341                         const __m128i raw_desc2 =
 342                                 _mm_load_si128((void *)(rxdp + 2));
 343                         rte_compiler_barrier();
 344                         const __m128i raw_desc1 =
 345                                 _mm_load_si128((void *)(rxdp + 1));
 346                         rte_compiler_barrier();
 347                         const __m128i raw_desc0 =
 348                                 _mm_load_si128((void *)(rxdp + 0));
 349
 350                         raw_desc6_7 =
 351                                 _mm256_inserti128_si256
 352                                         (_mm256_castsi128_si256(raw_desc6),
 353                                          raw_desc7, 1);
 354                         raw_desc4_5 =
 355                                 _mm256_inserti128_si256
 356                                         (_mm256_castsi128_si256(raw_desc4),
 357                                          raw_desc5, 1);
 358                         raw_desc2_3 =
 359                                 _mm256_inserti128_si256
 360                                         (_mm256_castsi128_si256(raw_desc2),
 361                                          raw_desc3, 1);
 362                         raw_desc0_1 =
 363                                 _mm256_inserti128_si256
 364                                         (_mm256_castsi128_si256(raw_desc0),
 365                                          raw_desc1, 1);
 366                 }
 367
 368                 if (split_packet) {
 369                         int j;
 370
 371                         for (j = 0; j < IAVF_DESCS_PER_LOOP_AVX; j++)
 372                                 rte_mbuf_prefetch_part2(rx_pkts[i + j]);
 373                 }
 374
 375                 /**
 376                  * convert descriptors 4-7 into mbufs, adjusting length and
 377                  * re-arranging fields. Then write into the mbuf
 378                  */
 379                 const __m256i len6_7 = _mm256_slli_epi32(raw_desc6_7,
 380                                                          PKTLEN_SHIFT);
 381                 const __m256i len4_5 = _mm256_slli_epi32(raw_desc4_5,
 382                                                          PKTLEN_SHIFT);
 383                 const __m256i desc6_7 = _mm256_blend_epi16(raw_desc6_7,
 384                                                            len6_7, 0x80);
 385                 const __m256i desc4_5 = _mm256_blend_epi16(raw_desc4_5,
 386                                                            len4_5, 0x80);
 387                 __m256i mb6_7 = _mm256_shuffle_epi8(desc6_7, shuf_msk);
 388                 __m256i mb4_5 = _mm256_shuffle_epi8(desc4_5, shuf_msk);
 389
 390                 mb6_7 = _mm256_add_epi16(mb6_7, crc_adjust);
 391                 mb4_5 = _mm256_add_epi16(mb4_5, crc_adjust);
 392                 /**
 393                  * to get packet types, shift 64-bit values down 30 bits
 394                  * and so ptype is in lower 8-bits in each
 395                  */
 396                 const __m256i ptypes6_7 = _mm256_srli_epi64(desc6_7, 30);
 397                 const __m256i ptypes4_5 = _mm256_srli_epi64(desc4_5, 30);
 398                 const uint8_t ptype7 = _mm256_extract_epi8(ptypes6_7, 24);
 399                 const uint8_t ptype6 = _mm256_extract_epi8(ptypes6_7, 8);
 400                 const uint8_t ptype5 = _mm256_extract_epi8(ptypes4_5, 24);
 401                 const uint8_t ptype4 = _mm256_extract_epi8(ptypes4_5, 8);
 402
 403                 mb6_7 = _mm256_insert_epi32(mb6_7, type_table[ptype7], 4);
 404                 mb6_7 = _mm256_insert_epi32(mb6_7, type_table[ptype6], 0);
 405                 mb4_5 = _mm256_insert_epi32(mb4_5, type_table[ptype5], 4);
 406                 mb4_5 = _mm256_insert_epi32(mb4_5, type_table[ptype4], 0);
 407                 /* merge the status bits into one register */
 408                 const __m256i status4_7 = _mm256_unpackhi_epi32(desc6_7,
 409                                 desc4_5);
 410
 411                 /**
 412                  * convert descriptors 0-3 into mbufs, adjusting length and
 413                  * re-arranging fields. Then write into the mbuf
 414                  */
 415                 const __m256i len2_3 = _mm256_slli_epi32(raw_desc2_3,
 416                                                          PKTLEN_SHIFT);
 417                 const __m256i len0_1 = _mm256_slli_epi32(raw_desc0_1,
 418                                                          PKTLEN_SHIFT);
 419                 const __m256i desc2_3 = _mm256_blend_epi16(raw_desc2_3,
 420                                                            len2_3, 0x80);
 421                 const __m256i desc0_1 = _mm256_blend_epi16(raw_desc0_1,
 422                                                            len0_1, 0x80);
 423                 __m256i mb2_3 = _mm256_shuffle_epi8(desc2_3, shuf_msk);
 424                 __m256i mb0_1 = _mm256_shuffle_epi8(desc0_1, shuf_msk);
 425
 426                 mb2_3 = _mm256_add_epi16(mb2_3, crc_adjust);
 427                 mb0_1 = _mm256_add_epi16(mb0_1, crc_adjust);
 428                 /* get the packet types */
 429                 const __m256i ptypes2_3 = _mm256_srli_epi64(desc2_3, 30);
 430                 const __m256i ptypes0_1 = _mm256_srli_epi64(desc0_1, 30);
 431                 const uint8_t ptype3 = _mm256_extract_epi8(ptypes2_3, 24);
 432                 const uint8_t ptype2 = _mm256_extract_epi8(ptypes2_3, 8);
 433                 const uint8_t ptype1 = _mm256_extract_epi8(ptypes0_1, 24);
 434                 const uint8_t ptype0 = _mm256_extract_epi8(ptypes0_1, 8);
 435
 436                 mb2_3 = _mm256_insert_epi32(mb2_3, type_table[ptype3], 4);
 437                 mb2_3 = _mm256_insert_epi32(mb2_3, type_table[ptype2], 0);
 438                 mb0_1 = _mm256_insert_epi32(mb0_1, type_table[ptype1], 4);
 439                 mb0_1 = _mm256_insert_epi32(mb0_1, type_table[ptype0], 0);
 440                 /* merge the status bits into one register */
 441                 const __m256i status0_3 = _mm256_unpackhi_epi32(desc2_3,
 442                                                                 desc0_1);
 443
 444                 /**
 445                  * take the two sets of status bits and merge to one
 446                  * After merge, the packets status flags are in the
 447                  * order (hi->lo): [1, 3, 5, 7, 0, 2, 4, 6]
 448                  */
 449                 __m256i status0_7 = _mm256_unpacklo_epi64(status4_7,
 450                                                           status0_3);
 451
 452                 /* now do flag manipulation */
 453
 454                 /* get only flag/error bits we want */
 455                 const __m256i flag_bits =
 456                         _mm256_and_si256(status0_7, flags_mask);
 457                 /* set vlan and rss flags */
 458                 const __m256i vlan_flags =
 459                         _mm256_shuffle_epi8(vlan_flags_shuf, flag_bits);
 460                 const __m256i rss_flags =
 461                         _mm256_shuffle_epi8(rss_flags_shuf,
 462                                             _mm256_srli_epi32(flag_bits, 11));
 463                 /**
 464                  * l3_l4_error flags, shuffle, then shift to correct adjustment
 465                  * of flags in flags_shuf, and finally mask out extra bits
 466                  */
 467                 __m256i l3_l4_flags = _mm256_shuffle_epi8(l3_l4_flags_shuf,
 468                                 _mm256_srli_epi32(flag_bits, 22));
 469                 l3_l4_flags = _mm256_slli_epi32(l3_l4_flags, 1);
 470                 l3_l4_flags = _mm256_and_si256(l3_l4_flags, cksum_mask);
 471
 472                 /* merge flags */
 473                 const __m256i mbuf_flags = _mm256_or_si256(l3_l4_flags,
 474                                 _mm256_or_si256(rss_flags, vlan_flags));
 475                 /**
 476                  * At this point, we have the 8 sets of flags in the low 16-bits
 477                  * of each 32-bit value in vlan0.
 478                  * We want to extract these, and merge them with the mbuf init
 479                  * data so we can do a single write to the mbuf to set the flags
 480                  * and all the other initialization fields. Extracting the
 481                  * appropriate flags means that we have to do a shift and blend
 482                  * for each mbuf before we do the write. However, we can also
 483                  * add in the previously computed rx_descriptor fields to
 484                  * make a single 256-bit write per mbuf
 485                  */
 486                 /* check the structure matches expectations */
 487                 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, ol_flags) !=
 488                                  offsetof(struct rte_mbuf, rearm_data) + 8);
 489                 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, rearm_data) !=
 490                                  RTE_ALIGN(offsetof(struct rte_mbuf,
 491                                                     rearm_data),
 492                                            16));
 493                 /* build up data and do writes */
 494                 __m256i rearm0, rearm1, rearm2, rearm3, rearm4, rearm5,
 495                         rearm6, rearm7;
 496                 rearm6 = _mm256_blend_epi32(mbuf_init,
 497                                             _mm256_slli_si256(mbuf_flags, 8),
 498                                             0x04);
 499                 rearm4 = _mm256_blend_epi32(mbuf_init,
 500                                             _mm256_slli_si256(mbuf_flags, 4),
 501                                             0x04);
 502                 rearm2 = _mm256_blend_epi32(mbuf_init, mbuf_flags, 0x04);
 503                 rearm0 = _mm256_blend_epi32(mbuf_init,
 504                                             _mm256_srli_si256(mbuf_flags, 4),
 505                                             0x04);
 506                 /* permute to add in the rx_descriptor e.g. rss fields */
 507                 rearm6 = _mm256_permute2f128_si256(rearm6, mb6_7, 0x20);
 508                 rearm4 = _mm256_permute2f128_si256(rearm4, mb4_5, 0x20);
 509                 rearm2 = _mm256_permute2f128_si256(rearm2, mb2_3, 0x20);
 510                 rearm0 = _mm256_permute2f128_si256(rearm0, mb0_1, 0x20);
 511                 /* write to mbuf */
 512                 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 6]->rearm_data,
 513                                     rearm6);
 514                 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 4]->rearm_data,
 515                                     rearm4);
 516                 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 2]->rearm_data,
 517                                     rearm2);
 518                 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 0]->rearm_data,
 519                                     rearm0);
 520
 521                 /* repeat for the odd mbufs */
 522                 const __m256i odd_flags =
 523                         _mm256_castsi128_si256
 524                                 (_mm256_extracti128_si256(mbuf_flags, 1));
 525                 rearm7 = _mm256_blend_epi32(mbuf_init,
 526                                             _mm256_slli_si256(odd_flags, 8),
 527                                             0x04);
 528                 rearm5 = _mm256_blend_epi32(mbuf_init,
 529                                             _mm256_slli_si256(odd_flags, 4),
 530                                             0x04);
 531                 rearm3 = _mm256_blend_epi32(mbuf_init, odd_flags, 0x04);
 532                 rearm1 = _mm256_blend_epi32(mbuf_init,
 533                                             _mm256_srli_si256(odd_flags, 4),
 534                                             0x04);
 535                 /* since odd mbufs are already in hi 128-bits use blend */
 536                 rearm7 = _mm256_blend_epi32(rearm7, mb6_7, 0xF0);
 537                 rearm5 = _mm256_blend_epi32(rearm5, mb4_5, 0xF0);
 538                 rearm3 = _mm256_blend_epi32(rearm3, mb2_3, 0xF0);
 539                 rearm1 = _mm256_blend_epi32(rearm1, mb0_1, 0xF0);
 540                 /* again write to mbufs */
 541                 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 7]->rearm_data,
 542                                     rearm7);
 543                 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 5]->rearm_data,
 544                                     rearm5);
 545                 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 3]->rearm_data,
 546                                     rearm3);
 547                 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 1]->rearm_data,
 548                                     rearm1);
 549
 550                 /* extract and record EOP bit */
 551                 if (split_packet) {
 552                         const __m128i eop_mask =
 553                                 _mm_set1_epi16(1 << IAVF_RX_DESC_STATUS_EOF_SHIFT);
 554                         const __m256i eop_bits256 = _mm256_and_si256(status0_7,
 555                                                                      eop_check);
 556                         /* pack status bits into a single 128-bit register */
 557                         const __m128i eop_bits =
 558                                 _mm_packus_epi32
 559                                         (_mm256_castsi256_si128(eop_bits256),
 560                                          _mm256_extractf128_si256(eop_bits256,
 561                                                                   1));
 562                         /**
 563                          * flip bits, and mask out the EOP bit, which is now
 564                          * a split-packet bit i.e. !EOP, rather than EOP one.
 565                          */
 566                         __m128i split_bits = _mm_andnot_si128(eop_bits,
 567                                         eop_mask);
 568                         /**
 569                          * eop bits are out of order, so we need to shuffle them
 570                          * back into order again. In doing so, only use low 8
 571                          * bits, which acts like another pack instruction
 572                          * The original order is (hi->lo): 1,3,5,7,0,2,4,6
 573                          * [Since we use epi8, the 16-bit positions are
 574                          * multiplied by 2 in the eop_shuffle value.]
 575                          */
 576                         __m128i eop_shuffle =
 577                                 _mm_set_epi8(/* zero hi 64b */
 578                                              0xFF, 0xFF, 0xFF, 0xFF,
 579                                              0xFF, 0xFF, 0xFF, 0xFF,
 580                                              /* move values to lo 64b */
 581                                              8, 0, 10, 2,
 582                                              12, 4, 14, 6);
 583                         split_bits = _mm_shuffle_epi8(split_bits, eop_shuffle);
 584                         *(uint64_t *)split_packet =
 585                                 _mm_cvtsi128_si64(split_bits);
 586                         split_packet += IAVF_DESCS_PER_LOOP_AVX;
 587                 }
 588
 589                 /* perform dd_check */
 590                 status0_7 = _mm256_and_si256(status0_7, dd_check);
 591                 status0_7 = _mm256_packs_epi32(status0_7,
 592                                                _mm256_setzero_si256());
 593
 594                 uint64_t burst = __builtin_popcountll
 595                                         (_mm_cvtsi128_si64
 596                                                 (_mm256_extracti128_si256
 597                                                         (status0_7, 1)));
 598                 burst += __builtin_popcountll
 599                                 (_mm_cvtsi128_si64
 600                                         (_mm256_castsi256_si128(status0_7)));
 601                 received += burst;
 602                 if (burst != IAVF_DESCS_PER_LOOP_AVX)
 603                         break;
 604         }
 605
 606         /* update tail pointers */
 607         rxq->rx_tail += received;
 608         rxq->rx_tail &= (rxq->nb_rx_desc - 1);
 609         if ((rxq->rx_tail & 1) == 1 && received > 1) { /* keep avx2 aligned */
 610                 rxq->rx_tail--;
 611                 received--;
 612         }
 613         rxq->rxrearm_nb += received;
 614         return received;
 615 }
 616
 617 static inline __m256i
 618 flex_rxd_to_fdir_flags_vec_avx2(const __m256i fdir_id0_7)
 619 {
 620 #define FDID_MIS_MAGIC 0xFFFFFFFF
 621         RTE_BUILD_BUG_ON(PKT_RX_FDIR != (1 << 2));
 622         RTE_BUILD_BUG_ON(PKT_RX_FDIR_ID != (1 << 13));
 623         const __m256i pkt_fdir_bit = _mm256_set1_epi32(PKT_RX_FDIR |
 624                         PKT_RX_FDIR_ID);
 625         /* desc->flow_id field == 0xFFFFFFFF means fdir mismatch */
 626         const __m256i fdir_mis_mask = _mm256_set1_epi32(FDID_MIS_MAGIC);
 627         __m256i fdir_mask = _mm256_cmpeq_epi32(fdir_id0_7,
 628                         fdir_mis_mask);
 629         /* this XOR op results to bit-reverse the fdir_mask */
 630         fdir_mask = _mm256_xor_si256(fdir_mask, fdir_mis_mask);
 631         const __m256i fdir_flags = _mm256_and_si256(fdir_mask, pkt_fdir_bit);
 632
 633         return fdir_flags;
 634 }
 635
 636 static inline uint16_t
 637 _iavf_recv_raw_pkts_vec_avx2_flex_rxd(struct iavf_rx_queue *rxq,
 638                                       struct rte_mbuf **rx_pkts,
 639                                       uint16_t nb_pkts, uint8_t *split_packet)
 640 {
 641 #define IAVF_DESCS_PER_LOOP_AVX 8
 642
 643         const uint32_t *type_table = rxq->vsi->adapter->ptype_tbl;
 644
 645         const __m256i mbuf_init = _mm256_set_epi64x(0, 0,
 646                         0, rxq->mbuf_initializer);
 647         struct rte_mbuf **sw_ring = &rxq->sw_ring[rxq->rx_tail];
 648         volatile union iavf_rx_flex_desc *rxdp =
 649                 (union iavf_rx_flex_desc *)rxq->rx_ring + rxq->rx_tail;
 650
 651         rte_prefetch0(rxdp);
 652
 653         /* nb_pkts has to be floor-aligned to IAVF_DESCS_PER_LOOP_AVX */
 654         nb_pkts = RTE_ALIGN_FLOOR(nb_pkts, IAVF_DESCS_PER_LOOP_AVX);
 655
 656         /* See if we need to rearm the RX queue - gives the prefetch a bit
 657          * of time to act
 658          */
 659         if (rxq->rxrearm_nb > IAVF_RXQ_REARM_THRESH)
 660                 iavf_rxq_rearm(rxq);
 661
 662         /* Before we start moving massive data around, check to see if
 663          * there is actually a packet available
 664          */
 665         if (!(rxdp->wb.status_error0 &
 666                         rte_cpu_to_le_32(1 << IAVF_RX_FLEX_DESC_STATUS0_DD_S)))
 667                 return 0;
 668
 669         /* constants used in processing loop */
 670         const __m256i crc_adjust =
 671                 _mm256_set_epi16
 672                         (/* first descriptor */
 673                          0, 0, 0,       /* ignore non-length fields */
 674                          -rxq->crc_len, /* sub crc on data_len */
 675                          0,             /* ignore high-16bits of pkt_len */
 676                          -rxq->crc_len, /* sub crc on pkt_len */
 677                          0, 0,          /* ignore pkt_type field */
 678                          /* second descriptor */
 679                          0, 0, 0,       /* ignore non-length fields */
 680                          -rxq->crc_len, /* sub crc on data_len */
 681                          0,             /* ignore high-16bits of pkt_len */
 682                          -rxq->crc_len, /* sub crc on pkt_len */
 683                          0, 0           /* ignore pkt_type field */
 684                         );
 685
 686         /* 8 packets DD mask, LSB in each 32-bit value */
 687         const __m256i dd_check = _mm256_set1_epi32(1);
 688
 689         /* 8 packets EOP mask, second-LSB in each 32-bit value */
 690         const __m256i eop_check = _mm256_slli_epi32(dd_check,
 691                         IAVF_RX_FLEX_DESC_STATUS0_EOF_S);
 692
 693         /* mask to shuffle from desc. to mbuf (2 descriptors)*/
 694         const __m256i shuf_msk =
 695                 _mm256_set_epi8
 696                         (/* first descriptor */
 697                          0xFF, 0xFF,
 698                          0xFF, 0xFF,    /* rss hash parsed separately */
 699                          11, 10,        /* octet 10~11, 16 bits vlan_macip */
 700                          5, 4,          /* octet 4~5, 16 bits data_len */
 701                          0xFF, 0xFF,    /* skip hi 16 bits pkt_len, zero out */
 702                          5, 4,          /* octet 4~5, 16 bits pkt_len */
 703                          0xFF, 0xFF,    /* pkt_type set as unknown */
 704                          0xFF, 0xFF,    /*pkt_type set as unknown */
 705                          /* second descriptor */
 706                          0xFF, 0xFF,
 707                          0xFF, 0xFF,    /* rss hash parsed separately */
 708                          11, 10,        /* octet 10~11, 16 bits vlan_macip */
 709                          5, 4,          /* octet 4~5, 16 bits data_len */
 710                          0xFF, 0xFF,    /* skip hi 16 bits pkt_len, zero out */
 711                          5, 4,          /* octet 4~5, 16 bits pkt_len */
 712                          0xFF, 0xFF,    /* pkt_type set as unknown */
 713                          0xFF, 0xFF     /*pkt_type set as unknown */
 714                         );
 715         /**
 716          * compile-time check the above crc and shuffle layout is correct.
 717          * NOTE: the first field (lowest address) is given last in set_epi
 718          * calls above.
 719          */
 720         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, pkt_len) !=
 721                         offsetof(struct rte_mbuf, rx_descriptor_fields1) + 4);
 722         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, data_len) !=
 723                         offsetof(struct rte_mbuf, rx_descriptor_fields1) + 8);
 724         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, vlan_tci) !=
 725                         offsetof(struct rte_mbuf, rx_descriptor_fields1) + 10);
 726         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, hash) !=
 727                         offsetof(struct rte_mbuf, rx_descriptor_fields1) + 12);
 728
 729         /* Status/Error flag masks */
 730         /**
 731          * mask everything except Checksum Reports, RSS indication
 732          * and VLAN indication.
 733          * bit6:4 for IP/L4 checksum errors.
 734          * bit12 is for RSS indication.
 735          * bit13 is for VLAN indication.
 736          */
 737         const __m256i flags_mask =
 738                  _mm256_set1_epi32((7 << 4) | (1 << 12) | (1 << 13));
 739         /**
 740          * data to be shuffled by the result of the flags mask shifted by 4
 741          * bits.  This gives use the l3_l4 flags.
 742          */
 743         const __m256i l3_l4_flags_shuf = _mm256_set_epi8(0, 0, 0, 0, 0, 0, 0, 0,
 744                         /* shift right 1 bit to make sure it not exceed 255 */
 745                         (PKT_RX_EIP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD |
 746                          PKT_RX_IP_CKSUM_BAD) >> 1,
 747                         (PKT_RX_EIP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD |
 748                          PKT_RX_IP_CKSUM_GOOD) >> 1,
 749                         (PKT_RX_EIP_CKSUM_BAD | PKT_RX_L4_CKSUM_GOOD |
 750                          PKT_RX_IP_CKSUM_BAD) >> 1,
 751                         (PKT_RX_EIP_CKSUM_BAD | PKT_RX_L4_CKSUM_GOOD |
 752                          PKT_RX_IP_CKSUM_GOOD) >> 1,
 753                         (PKT_RX_L4_CKSUM_BAD | PKT_RX_IP_CKSUM_BAD) >> 1,
 754                         (PKT_RX_L4_CKSUM_BAD | PKT_RX_IP_CKSUM_GOOD) >> 1,
 755                         (PKT_RX_L4_CKSUM_GOOD | PKT_RX_IP_CKSUM_BAD) >> 1,
 756                         (PKT_RX_L4_CKSUM_GOOD | PKT_RX_IP_CKSUM_GOOD) >> 1,
 757                         /* second 128-bits */
 758                         0, 0, 0, 0, 0, 0, 0, 0,
 759                         (PKT_RX_EIP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD |
 760                          PKT_RX_IP_CKSUM_BAD) >> 1,
 761                         (PKT_RX_EIP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD |
 762                          PKT_RX_IP_CKSUM_GOOD) >> 1,
 763                         (PKT_RX_EIP_CKSUM_BAD | PKT_RX_L4_CKSUM_GOOD |
 764                          PKT_RX_IP_CKSUM_BAD) >> 1,
 765                         (PKT_RX_EIP_CKSUM_BAD | PKT_RX_L4_CKSUM_GOOD |
 766                          PKT_RX_IP_CKSUM_GOOD) >> 1,
 767                         (PKT_RX_L4_CKSUM_BAD | PKT_RX_IP_CKSUM_BAD) >> 1,
 768                         (PKT_RX_L4_CKSUM_BAD | PKT_RX_IP_CKSUM_GOOD) >> 1,
 769                         (PKT_RX_L4_CKSUM_GOOD | PKT_RX_IP_CKSUM_BAD) >> 1,
 770                         (PKT_RX_L4_CKSUM_GOOD | PKT_RX_IP_CKSUM_GOOD) >> 1);
 771         const __m256i cksum_mask =
 772                  _mm256_set1_epi32(PKT_RX_IP_CKSUM_GOOD | PKT_RX_IP_CKSUM_BAD |
 773                                    PKT_RX_L4_CKSUM_GOOD | PKT_RX_L4_CKSUM_BAD |
 774                                    PKT_RX_EIP_CKSUM_BAD);
 775         /**
 776          * data to be shuffled by result of flag mask, shifted down 12.
 777          * If RSS(bit12)/VLAN(bit13) are set,
 778          * shuffle moves appropriate flags in place.
 779          */
 780         const __m256i rss_flags_shuf = _mm256_set_epi8(0, 0, 0, 0,
 781                         0, 0, 0, 0,
 782                         0, 0, 0, 0,
 783                         PKT_RX_RSS_HASH, 0,
 784                         PKT_RX_RSS_HASH, 0,
 785                         /* end up 128-bits */
 786                         0, 0, 0, 0,
 787                         0, 0, 0, 0,
 788                         0, 0, 0, 0,
 789                         PKT_RX_RSS_HASH, 0,
 790                         PKT_RX_RSS_HASH, 0);
 791
 792         const __m256i vlan_flags_shuf = _mm256_set_epi8(0, 0, 0, 0,
 793                         0, 0, 0, 0,
 794                         0, 0, 0, 0,
 795                         PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED,
 796                         PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED,
 797                         0, 0,
 798                         /* end up 128-bits */
 799                         0, 0, 0, 0,
 800                         0, 0, 0, 0,
 801                         0, 0, 0, 0,
 802                         PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED,
 803                         PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED,
 804                         0, 0);
 805
 806         uint16_t i, received;
 807
 808         for (i = 0, received = 0; i < nb_pkts;
 809              i += IAVF_DESCS_PER_LOOP_AVX,
 810              rxdp += IAVF_DESCS_PER_LOOP_AVX) {
 811                 /* step 1, copy over 8 mbuf pointers to rx_pkts array */
 812                 _mm256_storeu_si256((void *)&rx_pkts[i],
 813                                     _mm256_loadu_si256((void *)&sw_ring[i]));
 814 #ifdef RTE_ARCH_X86_64
 815                 _mm256_storeu_si256
 816                         ((void *)&rx_pkts[i + 4],
 817                          _mm256_loadu_si256((void *)&sw_ring[i + 4]));
 818 #endif
 819
 820                 __m256i raw_desc0_1, raw_desc2_3, raw_desc4_5, raw_desc6_7;
 821
 822                 const __m128i raw_desc7 =
 823                         _mm_load_si128((void *)(rxdp + 7));
 824                 rte_compiler_barrier();
 825                 const __m128i raw_desc6 =
 826                         _mm_load_si128((void *)(rxdp + 6));
 827                 rte_compiler_barrier();
 828                 const __m128i raw_desc5 =
 829                         _mm_load_si128((void *)(rxdp + 5));
 830                 rte_compiler_barrier();
 831                 const __m128i raw_desc4 =
 832                         _mm_load_si128((void *)(rxdp + 4));
 833                 rte_compiler_barrier();
 834                 const __m128i raw_desc3 =
 835                         _mm_load_si128((void *)(rxdp + 3));
 836                 rte_compiler_barrier();
 837                 const __m128i raw_desc2 =
 838                         _mm_load_si128((void *)(rxdp + 2));
 839                 rte_compiler_barrier();
 840                 const __m128i raw_desc1 =
 841                         _mm_load_si128((void *)(rxdp + 1));
 842                 rte_compiler_barrier();
 843                 const __m128i raw_desc0 =
 844                         _mm_load_si128((void *)(rxdp + 0));
 845
 846                 raw_desc6_7 =
 847                         _mm256_inserti128_si256
 848                                 (_mm256_castsi128_si256(raw_desc6),
 849                                  raw_desc7, 1);
 850                 raw_desc4_5 =
 851                         _mm256_inserti128_si256
 852                                 (_mm256_castsi128_si256(raw_desc4),
 853                                  raw_desc5, 1);
 854                 raw_desc2_3 =
 855                         _mm256_inserti128_si256
 856                                 (_mm256_castsi128_si256(raw_desc2),
 857                                  raw_desc3, 1);
 858                 raw_desc0_1 =
 859                         _mm256_inserti128_si256
 860                                 (_mm256_castsi128_si256(raw_desc0),
 861                                  raw_desc1, 1);
 862
 863                 if (split_packet) {
 864                         int j;
 865
 866                         for (j = 0; j < IAVF_DESCS_PER_LOOP_AVX; j++)
 867                                 rte_mbuf_prefetch_part2(rx_pkts[i + j]);
 868                 }
 869
 870                 /**
 871                  * convert descriptors 4-7 into mbufs, re-arrange fields.
 872                  * Then write into the mbuf.
 873                  */
 874                 __m256i mb6_7 = _mm256_shuffle_epi8(raw_desc6_7, shuf_msk);
 875                 __m256i mb4_5 = _mm256_shuffle_epi8(raw_desc4_5, shuf_msk);
 876
 877                 mb6_7 = _mm256_add_epi16(mb6_7, crc_adjust);
 878                 mb4_5 = _mm256_add_epi16(mb4_5, crc_adjust);
 879                 /**
 880                  * to get packet types, ptype is located in bit16-25
 881                  * of each 128bits
 882                  */
 883                 const __m256i ptype_mask =
 884                         _mm256_set1_epi16(IAVF_RX_FLEX_DESC_PTYPE_M);
 885                 const __m256i ptypes6_7 =
 886                         _mm256_and_si256(raw_desc6_7, ptype_mask);
 887                 const __m256i ptypes4_5 =
 888                         _mm256_and_si256(raw_desc4_5, ptype_mask);
 889                 const uint16_t ptype7 = _mm256_extract_epi16(ptypes6_7, 9);
 890                 const uint16_t ptype6 = _mm256_extract_epi16(ptypes6_7, 1);
 891                 const uint16_t ptype5 = _mm256_extract_epi16(ptypes4_5, 9);
 892                 const uint16_t ptype4 = _mm256_extract_epi16(ptypes4_5, 1);
 893
 894                 mb6_7 = _mm256_insert_epi32(mb6_7, type_table[ptype7], 4);
 895                 mb6_7 = _mm256_insert_epi32(mb6_7, type_table[ptype6], 0);
 896                 mb4_5 = _mm256_insert_epi32(mb4_5, type_table[ptype5], 4);
 897                 mb4_5 = _mm256_insert_epi32(mb4_5, type_table[ptype4], 0);
 898                 /* merge the status bits into one register */
 899                 const __m256i status4_7 = _mm256_unpackhi_epi32(raw_desc6_7,
 900                                 raw_desc4_5);
 901
 902                 /**
 903                  * convert descriptors 0-3 into mbufs, re-arrange fields.
 904                  * Then write into the mbuf.
 905                  */
 906                 __m256i mb2_3 = _mm256_shuffle_epi8(raw_desc2_3, shuf_msk);
 907                 __m256i mb0_1 = _mm256_shuffle_epi8(raw_desc0_1, shuf_msk);
 908
 909                 mb2_3 = _mm256_add_epi16(mb2_3, crc_adjust);
 910                 mb0_1 = _mm256_add_epi16(mb0_1, crc_adjust);
 911                 /**
 912                  * to get packet types, ptype is located in bit16-25
 913                  * of each 128bits
 914                  */
 915                 const __m256i ptypes2_3 =
 916                         _mm256_and_si256(raw_desc2_3, ptype_mask);
 917                 const __m256i ptypes0_1 =
 918                         _mm256_and_si256(raw_desc0_1, ptype_mask);
 919                 const uint16_t ptype3 = _mm256_extract_epi16(ptypes2_3, 9);
 920                 const uint16_t ptype2 = _mm256_extract_epi16(ptypes2_3, 1);
 921                 const uint16_t ptype1 = _mm256_extract_epi16(ptypes0_1, 9);
 922                 const uint16_t ptype0 = _mm256_extract_epi16(ptypes0_1, 1);
 923
 924                 mb2_3 = _mm256_insert_epi32(mb2_3, type_table[ptype3], 4);
 925                 mb2_3 = _mm256_insert_epi32(mb2_3, type_table[ptype2], 0);
 926                 mb0_1 = _mm256_insert_epi32(mb0_1, type_table[ptype1], 4);
 927                 mb0_1 = _mm256_insert_epi32(mb0_1, type_table[ptype0], 0);
 928                 /* merge the status bits into one register */
 929                 const __m256i status0_3 = _mm256_unpackhi_epi32(raw_desc2_3,
 930                                                                 raw_desc0_1);
 931
 932                 /**
 933                  * take the two sets of status bits and merge to one
 934                  * After merge, the packets status flags are in the
 935                  * order (hi->lo): [1, 3, 5, 7, 0, 2, 4, 6]
 936                  */
 937                 __m256i status0_7 = _mm256_unpacklo_epi64(status4_7,
 938                                                           status0_3);
 939
 940                 /* now do flag manipulation */
 941
 942                 /* get only flag/error bits we want */
 943                 const __m256i flag_bits =
 944                         _mm256_and_si256(status0_7, flags_mask);
 945                 /**
 946                  * l3_l4_error flags, shuffle, then shift to correct adjustment
 947                  * of flags in flags_shuf, and finally mask out extra bits
 948                  */
 949                 __m256i l3_l4_flags = _mm256_shuffle_epi8(l3_l4_flags_shuf,
 950                                 _mm256_srli_epi32(flag_bits, 4));
 951                 l3_l4_flags = _mm256_slli_epi32(l3_l4_flags, 1);
 952                 l3_l4_flags = _mm256_and_si256(l3_l4_flags, cksum_mask);
 953
 954                 /* set rss and vlan flags */
 955                 const __m256i rss_vlan_flag_bits =
 956                         _mm256_srli_epi32(flag_bits, 12);
 957                 const __m256i rss_flags =
 958                         _mm256_shuffle_epi8(rss_flags_shuf,
 959                                             rss_vlan_flag_bits);
 960
 961                 __m256i vlan_flags = _mm256_setzero_si256();
 962
 963                 if (rxq->rx_flags == IAVF_RX_FLAGS_VLAN_TAG_LOC_L2TAG1)
 964                         vlan_flags =
 965                                 _mm256_shuffle_epi8(vlan_flags_shuf,
 966                                                     rss_vlan_flag_bits);
 967
 968                 const __m256i rss_vlan_flags =
 969                         _mm256_or_si256(rss_flags, vlan_flags);
 970
 971                 /* merge flags */
 972                 __m256i mbuf_flags = _mm256_or_si256(l3_l4_flags,
 973                                 rss_vlan_flags);
 974
 975                 if (rxq->fdir_enabled) {
 976                         const __m256i fdir_id4_7 =
 977                                 _mm256_unpackhi_epi32(raw_desc6_7, raw_desc4_5);
 978
 979                         const __m256i fdir_id0_3 =
 980                                 _mm256_unpackhi_epi32(raw_desc2_3, raw_desc0_1);
 981
 982                         const __m256i fdir_id0_7 =
 983                                 _mm256_unpackhi_epi64(fdir_id4_7, fdir_id0_3);
 984
 985                         const __m256i fdir_flags =
 986                                 flex_rxd_to_fdir_flags_vec_avx2(fdir_id0_7);
 987
 988                         /* merge with fdir_flags */
 989                         mbuf_flags = _mm256_or_si256(mbuf_flags, fdir_flags);
 990
 991                         /* write to mbuf: have to use scalar store here */
 992                         rx_pkts[i + 0]->hash.fdir.hi =
 993                                 _mm256_extract_epi32(fdir_id0_7, 3);
 994
 995                         rx_pkts[i + 1]->hash.fdir.hi =
 996                                 _mm256_extract_epi32(fdir_id0_7, 7);
 997
 998                         rx_pkts[i + 2]->hash.fdir.hi =
 999                                 _mm256_extract_epi32(fdir_id0_7, 2);
1000
1001                         rx_pkts[i + 3]->hash.fdir.hi =
1002                                 _mm256_extract_epi32(fdir_id0_7, 6);
1003
1004                         rx_pkts[i + 4]->hash.fdir.hi =
1005                                 _mm256_extract_epi32(fdir_id0_7, 1);
1006
1007                         rx_pkts[i + 5]->hash.fdir.hi =
1008                                 _mm256_extract_epi32(fdir_id0_7, 5);
1009
1010                         rx_pkts[i + 6]->hash.fdir.hi =
1011                                 _mm256_extract_epi32(fdir_id0_7, 0);
1012
1013                         rx_pkts[i + 7]->hash.fdir.hi =
1014                                 _mm256_extract_epi32(fdir_id0_7, 4);
1015                 } /* if() on fdir_enabled */
1016
1017 #ifndef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
1018                 /**
1019                  * needs to load 2nd 16B of each desc for RSS hash parsing,
1020                  * will cause performance drop to get into this context.
1021                  */
1022                 if (rxq->vsi->adapter->eth_dev->data->dev_conf.rxmode.offloads &
1023                                 DEV_RX_OFFLOAD_RSS_HASH ||
1024                                 rxq->rx_flags & IAVF_RX_FLAGS_VLAN_TAG_LOC_L2TAG2_2) {
1025                         /* load bottom half of every 32B desc */
1026                         const __m128i raw_desc_bh7 =
1027                                 _mm_load_si128
1028                                         ((void *)(&rxdp[7].wb.status_error1));
1029                         rte_compiler_barrier();
1030                         const __m128i raw_desc_bh6 =
1031                                 _mm_load_si128
1032                                         ((void *)(&rxdp[6].wb.status_error1));
1033                         rte_compiler_barrier();
1034                         const __m128i raw_desc_bh5 =
1035                                 _mm_load_si128
1036                                         ((void *)(&rxdp[5].wb.status_error1));
1037                         rte_compiler_barrier();
1038                         const __m128i raw_desc_bh4 =
1039                                 _mm_load_si128
1040                                         ((void *)(&rxdp[4].wb.status_error1));
1041                         rte_compiler_barrier();
1042                         const __m128i raw_desc_bh3 =
1043                                 _mm_load_si128
1044                                         ((void *)(&rxdp[3].wb.status_error1));
1045                         rte_compiler_barrier();
1046                         const __m128i raw_desc_bh2 =
1047                                 _mm_load_si128
1048                                         ((void *)(&rxdp[2].wb.status_error1));
1049                         rte_compiler_barrier();
1050                         const __m128i raw_desc_bh1 =
1051                                 _mm_load_si128
1052                                         ((void *)(&rxdp[1].wb.status_error1));
1053                         rte_compiler_barrier();
1054                         const __m128i raw_desc_bh0 =
1055                                 _mm_load_si128
1056                                         ((void *)(&rxdp[0].wb.status_error1));
1057
1058                         __m256i raw_desc_bh6_7 =
1059                                 _mm256_inserti128_si256
1060                                         (_mm256_castsi128_si256(raw_desc_bh6),
1061                                         raw_desc_bh7, 1);
1062                         __m256i raw_desc_bh4_5 =
1063                                 _mm256_inserti128_si256
1064                                         (_mm256_castsi128_si256(raw_desc_bh4),
1065                                         raw_desc_bh5, 1);
1066                         __m256i raw_desc_bh2_3 =
1067                                 _mm256_inserti128_si256
1068                                         (_mm256_castsi128_si256(raw_desc_bh2),
1069                                         raw_desc_bh3, 1);
1070                         __m256i raw_desc_bh0_1 =
1071                                 _mm256_inserti128_si256
1072                                         (_mm256_castsi128_si256(raw_desc_bh0),
1073                                         raw_desc_bh1, 1);
1074
1075                         if (rxq->vsi->adapter->eth_dev->data->dev_conf.rxmode.offloads &
1076                                         DEV_RX_OFFLOAD_RSS_HASH) {
1077                                 /**
1078                                  * to shift the 32b RSS hash value to the
1079                                  * highest 32b of each 128b before mask
1080                                  */
1081                                 __m256i rss_hash6_7 =
1082                                         _mm256_slli_epi64(raw_desc_bh6_7, 32);
1083                                 __m256i rss_hash4_5 =
1084                                         _mm256_slli_epi64(raw_desc_bh4_5, 32);
1085                                 __m256i rss_hash2_3 =
1086                                         _mm256_slli_epi64(raw_desc_bh2_3, 32);
1087                                 __m256i rss_hash0_1 =
1088                                         _mm256_slli_epi64(raw_desc_bh0_1, 32);
1089
1090                                 const __m256i rss_hash_msk =
1091                                         _mm256_set_epi32(0xFFFFFFFF, 0, 0, 0,
1092                                                          0xFFFFFFFF, 0, 0, 0);
1093
1094                                 rss_hash6_7 = _mm256_and_si256
1095                                                 (rss_hash6_7, rss_hash_msk);
1096                                 rss_hash4_5 = _mm256_and_si256
1097                                                 (rss_hash4_5, rss_hash_msk);
1098                                 rss_hash2_3 = _mm256_and_si256
1099                                                 (rss_hash2_3, rss_hash_msk);
1100                                 rss_hash0_1 = _mm256_and_si256
1101                                                 (rss_hash0_1, rss_hash_msk);
1102
1103                                 mb6_7 = _mm256_or_si256(mb6_7, rss_hash6_7);
1104                                 mb4_5 = _mm256_or_si256(mb4_5, rss_hash4_5);
1105                                 mb2_3 = _mm256_or_si256(mb2_3, rss_hash2_3);
1106                                 mb0_1 = _mm256_or_si256(mb0_1, rss_hash0_1);
1107                         }
1108
1109                         if (rxq->rx_flags & IAVF_RX_FLAGS_VLAN_TAG_LOC_L2TAG2_2) {
1110                                 /* merge the status/error-1 bits into one register */
1111                                 const __m256i status1_4_7 =
1112                                         _mm256_unpacklo_epi32(raw_desc_bh6_7,
1113                                                               raw_desc_bh4_5);
1114                                 const __m256i status1_0_3 =
1115                                         _mm256_unpacklo_epi32(raw_desc_bh2_3,
1116                                                               raw_desc_bh0_1);
1117
1118                                 const __m256i status1_0_7 =
1119                                         _mm256_unpacklo_epi64(status1_4_7,
1120                                                               status1_0_3);
1121
1122                                 const __m256i l2tag2p_flag_mask =
1123                                         _mm256_set1_epi32
1124                                         (1 << IAVF_RX_FLEX_DESC_STATUS1_L2TAG2P_S);
1125
1126                                 __m256i l2tag2p_flag_bits =
1127                                         _mm256_and_si256
1128                                         (status1_0_7, l2tag2p_flag_mask);
1129
1130                                 l2tag2p_flag_bits =
1131                                         _mm256_srli_epi32(l2tag2p_flag_bits,
1132                                                 IAVF_RX_FLEX_DESC_STATUS1_L2TAG2P_S);
1133
1134                                 const __m256i l2tag2_flags_shuf =
1135                                         _mm256_set_epi8(0, 0, 0, 0,
1136                                                         0, 0, 0, 0,
1137                                                         0, 0, 0, 0,
1138                                                         0, 0, 0, 0,
1139                                                         /* end up 128-bits */
1140                                                         0, 0, 0, 0,
1141                                                         0, 0, 0, 0,
1142                                                         0, 0, 0, 0,
1143                                                         0, 0,
1144                                                         PKT_RX_VLAN |
1145                                                         PKT_RX_VLAN_STRIPPED,
1146                                                         0);
1147
1148                                 vlan_flags =
1149                                         _mm256_shuffle_epi8(l2tag2_flags_shuf,
1150                                                             l2tag2p_flag_bits);
1151
1152                                 /* merge with vlan_flags */
1153                                 mbuf_flags = _mm256_or_si256
1154                                                 (mbuf_flags, vlan_flags);
1155
1156                                 /* L2TAG2_2 */
1157                                 __m256i vlan_tci6_7 =
1158                                         _mm256_slli_si256(raw_desc_bh6_7, 4);
1159                                 __m256i vlan_tci4_5 =
1160                                         _mm256_slli_si256(raw_desc_bh4_5, 4);
1161                                 __m256i vlan_tci2_3 =
1162                                         _mm256_slli_si256(raw_desc_bh2_3, 4);
1163                                 __m256i vlan_tci0_1 =
1164                                         _mm256_slli_si256(raw_desc_bh0_1, 4);
1165
1166                                 const __m256i vlan_tci_msk =
1167                                         _mm256_set_epi32(0, 0xFFFF0000, 0, 0,
1168                                                          0, 0xFFFF0000, 0, 0);
1169
1170                                 vlan_tci6_7 = _mm256_and_si256
1171                                                 (vlan_tci6_7, vlan_tci_msk);
1172                                 vlan_tci4_5 = _mm256_and_si256
1173                                                 (vlan_tci4_5, vlan_tci_msk);
1174                                 vlan_tci2_3 = _mm256_and_si256
1175                                                 (vlan_tci2_3, vlan_tci_msk);
1176                                 vlan_tci0_1 = _mm256_and_si256
1177                                                 (vlan_tci0_1, vlan_tci_msk);
1178
1179                                 mb6_7 = _mm256_or_si256(mb6_7, vlan_tci6_7);
1180                                 mb4_5 = _mm256_or_si256(mb4_5, vlan_tci4_5);
1181                                 mb2_3 = _mm256_or_si256(mb2_3, vlan_tci2_3);
1182                                 mb0_1 = _mm256_or_si256(mb0_1, vlan_tci0_1);
1183                         }
1184                 } /* if() on RSS hash parsing */
1185 #endif
1186
1187                 /**
1188                  * At this point, we have the 8 sets of flags in the low 16-bits
1189                  * of each 32-bit value in vlan0.
1190                  * We want to extract these, and merge them with the mbuf init
1191                  * data so we can do a single write to the mbuf to set the flags
1192                  * and all the other initialization fields. Extracting the
1193                  * appropriate flags means that we have to do a shift and blend
1194                  * for each mbuf before we do the write. However, we can also
1195                  * add in the previously computed rx_descriptor fields to
1196                  * make a single 256-bit write per mbuf
1197                  */
1198                 /* check the structure matches expectations */
1199                 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, ol_flags) !=
1200                                  offsetof(struct rte_mbuf, rearm_data) + 8);
1201                 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, rearm_data) !=
1202                                  RTE_ALIGN(offsetof(struct rte_mbuf,
1203                                                     rearm_data),
1204                                            16));
1205                 /* build up data and do writes */
1206                 __m256i rearm0, rearm1, rearm2, rearm3, rearm4, rearm5,
1207                         rearm6, rearm7;
1208                 rearm6 = _mm256_blend_epi32(mbuf_init,
1209                                             _mm256_slli_si256(mbuf_flags, 8),
1210                                             0x04);
1211                 rearm4 = _mm256_blend_epi32(mbuf_init,
1212                                             _mm256_slli_si256(mbuf_flags, 4),
1213                                             0x04);
1214                 rearm2 = _mm256_blend_epi32(mbuf_init, mbuf_flags, 0x04);
1215                 rearm0 = _mm256_blend_epi32(mbuf_init,
1216                                             _mm256_srli_si256(mbuf_flags, 4),
1217                                             0x04);
1218                 /* permute to add in the rx_descriptor e.g. rss fields */
1219                 rearm6 = _mm256_permute2f128_si256(rearm6, mb6_7, 0x20);
1220                 rearm4 = _mm256_permute2f128_si256(rearm4, mb4_5, 0x20);
1221                 rearm2 = _mm256_permute2f128_si256(rearm2, mb2_3, 0x20);
1222                 rearm0 = _mm256_permute2f128_si256(rearm0, mb0_1, 0x20);
1223                 /* write to mbuf */
1224                 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 6]->rearm_data,
1225                                     rearm6);
1226                 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 4]->rearm_data,
1227                                     rearm4);
1228                 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 2]->rearm_data,
1229                                     rearm2);
1230                 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 0]->rearm_data,
1231                                     rearm0);
1232
1233                 /* repeat for the odd mbufs */
1234                 const __m256i odd_flags =
1235                         _mm256_castsi128_si256
1236                                 (_mm256_extracti128_si256(mbuf_flags, 1));
1237                 rearm7 = _mm256_blend_epi32(mbuf_init,
1238                                             _mm256_slli_si256(odd_flags, 8),
1239                                             0x04);
1240                 rearm5 = _mm256_blend_epi32(mbuf_init,
1241                                             _mm256_slli_si256(odd_flags, 4),
1242                                             0x04);
1243                 rearm3 = _mm256_blend_epi32(mbuf_init, odd_flags, 0x04);
1244                 rearm1 = _mm256_blend_epi32(mbuf_init,
1245                                             _mm256_srli_si256(odd_flags, 4),
1246                                             0x04);
1247                 /* since odd mbufs are already in hi 128-bits use blend */
1248                 rearm7 = _mm256_blend_epi32(rearm7, mb6_7, 0xF0);
1249                 rearm5 = _mm256_blend_epi32(rearm5, mb4_5, 0xF0);
1250                 rearm3 = _mm256_blend_epi32(rearm3, mb2_3, 0xF0);
1251                 rearm1 = _mm256_blend_epi32(rearm1, mb0_1, 0xF0);
1252                 /* again write to mbufs */
1253                 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 7]->rearm_data,
1254                                     rearm7);
1255                 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 5]->rearm_data,
1256                                     rearm5);
1257                 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 3]->rearm_data,
1258                                     rearm3);
1259                 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 1]->rearm_data,
1260                                     rearm1);
1261
1262                 /* extract and record EOP bit */
1263                 if (split_packet) {
1264                         const __m128i eop_mask =
1265                                 _mm_set1_epi16(1 <<
1266                                                IAVF_RX_FLEX_DESC_STATUS0_EOF_S);
1267                         const __m256i eop_bits256 = _mm256_and_si256(status0_7,
1268                                                                      eop_check);
1269                         /* pack status bits into a single 128-bit register */
1270                         const __m128i eop_bits =
1271                                 _mm_packus_epi32
1272                                         (_mm256_castsi256_si128(eop_bits256),
1273                                          _mm256_extractf128_si256(eop_bits256,
1274                                                                   1));
1275                         /**
1276                          * flip bits, and mask out the EOP bit, which is now
1277                          * a split-packet bit i.e. !EOP, rather than EOP one.
1278                          */
1279                         __m128i split_bits = _mm_andnot_si128(eop_bits,
1280                                         eop_mask);
1281                         /**
1282                          * eop bits are out of order, so we need to shuffle them
1283                          * back into order again. In doing so, only use low 8
1284                          * bits, which acts like another pack instruction
1285                          * The original order is (hi->lo): 1,3,5,7,0,2,4,6
1286                          * [Since we use epi8, the 16-bit positions are
1287                          * multiplied by 2 in the eop_shuffle value.]
1288                          */
1289                         __m128i eop_shuffle =
1290                                 _mm_set_epi8(/* zero hi 64b */
1291                                              0xFF, 0xFF, 0xFF, 0xFF,
1292                                              0xFF, 0xFF, 0xFF, 0xFF,
1293                                              /* move values to lo 64b */
1294                                              8, 0, 10, 2,
1295                                              12, 4, 14, 6);
1296                         split_bits = _mm_shuffle_epi8(split_bits, eop_shuffle);
1297                         *(uint64_t *)split_packet =
1298                                 _mm_cvtsi128_si64(split_bits);
1299                         split_packet += IAVF_DESCS_PER_LOOP_AVX;
1300                 }
1301
1302                 /* perform dd_check */
1303                 status0_7 = _mm256_and_si256(status0_7, dd_check);
1304                 status0_7 = _mm256_packs_epi32(status0_7,
1305                                                _mm256_setzero_si256());
1306
1307                 uint64_t burst = __builtin_popcountll
1308                                         (_mm_cvtsi128_si64
1309                                                 (_mm256_extracti128_si256
1310                                                         (status0_7, 1)));
1311                 burst += __builtin_popcountll
1312                                 (_mm_cvtsi128_si64
1313                                         (_mm256_castsi256_si128(status0_7)));
1314                 received += burst;
1315                 if (burst != IAVF_DESCS_PER_LOOP_AVX)
1316                         break;
1317         }
1318
1319         /* update tail pointers */
1320         rxq->rx_tail += received;
1321         rxq->rx_tail &= (rxq->nb_rx_desc - 1);
1322         if ((rxq->rx_tail & 1) == 1 && received > 1) { /* keep avx2 aligned */
1323                 rxq->rx_tail--;
1324                 received--;
1325         }
1326         rxq->rxrearm_nb += received;
1327         return received;
1328 }
1329
1330 /**
1331  * Notice:
1332  * - nb_pkts < IAVF_DESCS_PER_LOOP, just return no packet
1333  */
1334 uint16_t
1335 iavf_recv_pkts_vec_avx2(void *rx_queue, struct rte_mbuf **rx_pkts,
1336                         uint16_t nb_pkts)
1337 {
1338         return _iavf_recv_raw_pkts_vec_avx2(rx_queue, rx_pkts, nb_pkts, NULL);
1339 }
1340
1341 /**
1342  * Notice:
1343  * - nb_pkts < IAVF_DESCS_PER_LOOP, just return no packet
1344  */
1345 uint16_t
1346 iavf_recv_pkts_vec_avx2_flex_rxd(void *rx_queue, struct rte_mbuf **rx_pkts,
1347                                  uint16_t nb_pkts)
1348 {
1349         return _iavf_recv_raw_pkts_vec_avx2_flex_rxd(rx_queue, rx_pkts,
1350                                                      nb_pkts, NULL);
1351 }
1352
1353 /**
1354  * vPMD receive routine that reassembles single burst of 32 scattered packets
1355  * Notice:
1356  * - nb_pkts < IAVF_DESCS_PER_LOOP, just return no packet
1357  */
1358 static uint16_t
1359 iavf_recv_scattered_burst_vec_avx2(void *rx_queue, struct rte_mbuf **rx_pkts,
1360                                    uint16_t nb_pkts)
1361 {
1362         struct iavf_rx_queue *rxq = rx_queue;
1363         uint8_t split_flags[IAVF_VPMD_RX_MAX_BURST] = {0};
1364
1365         /* get some new buffers */
1366         uint16_t nb_bufs = _iavf_recv_raw_pkts_vec_avx2(rxq, rx_pkts, nb_pkts,
1367                                                        split_flags);
1368         if (nb_bufs == 0)
1369                 return 0;
1370
1371         /* happy day case, full burst + no packets to be joined */
1372         const uint64_t *split_fl64 = (uint64_t *)split_flags;
1373
1374         if (!rxq->pkt_first_seg &&
1375             split_fl64[0] == 0 && split_fl64[1] == 0 &&
1376             split_fl64[2] == 0 && split_fl64[3] == 0)
1377                 return nb_bufs;
1378
1379         /* reassemble any packets that need reassembly*/
1380         unsigned int i = 0;
1381
1382         if (!rxq->pkt_first_seg) {
1383                 /* find the first split flag, and only reassemble then*/
1384                 while (i < nb_bufs && !split_flags[i])
1385                         i++;
1386                 if (i == nb_bufs)
1387                         return nb_bufs;
1388                 rxq->pkt_first_seg = rx_pkts[i];
1389         }
1390         return i + reassemble_packets(rxq, &rx_pkts[i], nb_bufs - i,
1391                                              &split_flags[i]);
1392 }
1393
1394 /**
1395  * vPMD receive routine that reassembles scattered packets.
1396  * Main receive routine that can handle arbitrary burst sizes
1397  * Notice:
1398  * - nb_pkts < IAVF_DESCS_PER_LOOP, just return no packet
1399  */
1400 uint16_t
1401 iavf_recv_scattered_pkts_vec_avx2(void *rx_queue, struct rte_mbuf **rx_pkts,
1402                                   uint16_t nb_pkts)
1403 {
1404         uint16_t retval = 0;
1405
1406         while (nb_pkts > IAVF_VPMD_RX_MAX_BURST) {
1407                 uint16_t burst = iavf_recv_scattered_burst_vec_avx2(rx_queue,
1408                                 rx_pkts + retval, IAVF_VPMD_RX_MAX_BURST);
1409                 retval += burst;
1410                 nb_pkts -= burst;
1411                 if (burst < IAVF_VPMD_RX_MAX_BURST)
1412                         return retval;
1413         }
1414         return retval + iavf_recv_scattered_burst_vec_avx2(rx_queue,
1415                                 rx_pkts + retval, nb_pkts);
1416 }
1417
1418 /**
1419  * vPMD receive routine that reassembles single burst of
1420  * 32 scattered packets for flex RxD
1421  * Notice:
1422  * - nb_pkts < IAVF_DESCS_PER_LOOP, just return no packet
1423  */
1424 static uint16_t
1425 iavf_recv_scattered_burst_vec_avx2_flex_rxd(void *rx_queue,
1426                                             struct rte_mbuf **rx_pkts,
1427                                             uint16_t nb_pkts)
1428 {
1429         struct iavf_rx_queue *rxq = rx_queue;
1430         uint8_t split_flags[IAVF_VPMD_RX_MAX_BURST] = {0};
1431
1432         /* get some new buffers */
1433         uint16_t nb_bufs = _iavf_recv_raw_pkts_vec_avx2_flex_rxd(rxq,
1434                                         rx_pkts, nb_pkts, split_flags);
1435         if (nb_bufs == 0)
1436                 return 0;
1437
1438         /* happy day case, full burst + no packets to be joined */
1439         const uint64_t *split_fl64 = (uint64_t *)split_flags;
1440
1441         if (!rxq->pkt_first_seg &&
1442             split_fl64[0] == 0 && split_fl64[1] == 0 &&
1443             split_fl64[2] == 0 && split_fl64[3] == 0)
1444                 return nb_bufs;
1445
1446         /* reassemble any packets that need reassembly*/
1447         unsigned int i = 0;
1448
1449         if (!rxq->pkt_first_seg) {
1450                 /* find the first split flag, and only reassemble then*/
1451                 while (i < nb_bufs && !split_flags[i])
1452                         i++;
1453                 if (i == nb_bufs)
1454                         return nb_bufs;
1455                 rxq->pkt_first_seg = rx_pkts[i];
1456         }
1457         return i + reassemble_packets(rxq, &rx_pkts[i], nb_bufs - i,
1458                                              &split_flags[i]);
1459 }
1460
1461 /**
1462  * vPMD receive routine that reassembles scattered packets for flex RxD.
1463  * Main receive routine that can handle arbitrary burst sizes
1464  * Notice:
1465  * - nb_pkts < IAVF_DESCS_PER_LOOP, just return no packet
1466  */
1467 uint16_t
1468 iavf_recv_scattered_pkts_vec_avx2_flex_rxd(void *rx_queue,
1469                                            struct rte_mbuf **rx_pkts,
1470                                            uint16_t nb_pkts)
1471 {
1472         uint16_t retval = 0;
1473
1474         while (nb_pkts > IAVF_VPMD_RX_MAX_BURST) {
1475                 uint16_t burst =
1476                         iavf_recv_scattered_burst_vec_avx2_flex_rxd
1477                         (rx_queue, rx_pkts + retval, IAVF_VPMD_RX_MAX_BURST);
1478                 retval += burst;
1479                 nb_pkts -= burst;
1480                 if (burst < IAVF_VPMD_RX_MAX_BURST)
1481                         return retval;
1482         }
1483         return retval + iavf_recv_scattered_burst_vec_avx2_flex_rxd(rx_queue,
1484                                 rx_pkts + retval, nb_pkts);
1485 }
1486
1487 static inline void
1488 iavf_vtx1(volatile struct iavf_tx_desc *txdp,
1489           struct rte_mbuf *pkt, uint64_t flags)
1490 {
1491         uint64_t high_qw =
1492                 (IAVF_TX_DESC_DTYPE_DATA |
1493                  ((uint64_t)flags  << IAVF_TXD_QW1_CMD_SHIFT) |
1494                  ((uint64_t)pkt->data_len << IAVF_TXD_QW1_TX_BUF_SZ_SHIFT));
1495
1496         __m128i descriptor = _mm_set_epi64x(high_qw,
1497                                 pkt->buf_iova + pkt->data_off);
1498         _mm_store_si128((__m128i *)txdp, descriptor);
1499 }
1500
1501 static inline void
1502 iavf_vtx(volatile struct iavf_tx_desc *txdp,
1503          struct rte_mbuf **pkt, uint16_t nb_pkts,  uint64_t flags)
1504 {
1505         const uint64_t hi_qw_tmpl = (IAVF_TX_DESC_DTYPE_DATA |
1506                         ((uint64_t)flags  << IAVF_TXD_QW1_CMD_SHIFT));
1507
1508         /* if unaligned on 32-bit boundary, do one to align */
1509         if (((uintptr_t)txdp & 0x1F) != 0 && nb_pkts != 0) {
1510                 iavf_vtx1(txdp, *pkt, flags);
1511                 nb_pkts--, txdp++, pkt++;
1512         }
1513
1514         /* do two at a time while possible, in bursts */
1515         for (; nb_pkts > 3; txdp += 4, pkt += 4, nb_pkts -= 4) {
1516                 uint64_t hi_qw3 =
1517                         hi_qw_tmpl |
1518                         ((uint64_t)pkt[3]->data_len <<
1519                          IAVF_TXD_QW1_TX_BUF_SZ_SHIFT);
1520                 uint64_t hi_qw2 =
1521                         hi_qw_tmpl |
1522                         ((uint64_t)pkt[2]->data_len <<
1523                          IAVF_TXD_QW1_TX_BUF_SZ_SHIFT);
1524                 uint64_t hi_qw1 =
1525                         hi_qw_tmpl |
1526                         ((uint64_t)pkt[1]->data_len <<
1527                          IAVF_TXD_QW1_TX_BUF_SZ_SHIFT);
1528                 uint64_t hi_qw0 =
1529                         hi_qw_tmpl |
1530                         ((uint64_t)pkt[0]->data_len <<
1531                          IAVF_TXD_QW1_TX_BUF_SZ_SHIFT);
1532
1533                 __m256i desc2_3 =
1534                         _mm256_set_epi64x
1535                                 (hi_qw3,
1536                                  pkt[3]->buf_iova + pkt[3]->data_off,
1537                                  hi_qw2,
1538                                  pkt[2]->buf_iova + pkt[2]->data_off);
1539                 __m256i desc0_1 =
1540                         _mm256_set_epi64x
1541                                 (hi_qw1,
1542                                  pkt[1]->buf_iova + pkt[1]->data_off,
1543                                  hi_qw0,
1544                                  pkt[0]->buf_iova + pkt[0]->data_off);
1545                 _mm256_store_si256((void *)(txdp + 2), desc2_3);
1546                 _mm256_store_si256((void *)txdp, desc0_1);
1547         }
1548
1549         /* do any last ones */
1550         while (nb_pkts) {
1551                 iavf_vtx1(txdp, *pkt, flags);
1552                 txdp++, pkt++, nb_pkts--;
1553         }
1554 }
1555
1556 static inline uint16_t
1557 iavf_xmit_fixed_burst_vec_avx2(void *tx_queue, struct rte_mbuf **tx_pkts,
1558                                uint16_t nb_pkts)
1559 {
1560         struct iavf_tx_queue *txq = (struct iavf_tx_queue *)tx_queue;
1561         volatile struct iavf_tx_desc *txdp;
1562         struct iavf_tx_entry *txep;
1563         uint16_t n, nb_commit, tx_id;
1564         /* bit2 is reserved and must be set to 1 according to Spec */
1565         uint64_t flags = IAVF_TX_DESC_CMD_EOP | IAVF_TX_DESC_CMD_ICRC;
1566         uint64_t rs = IAVF_TX_DESC_CMD_RS | flags;
1567
1568         /* cross rx_thresh boundary is not allowed */
1569         nb_pkts = RTE_MIN(nb_pkts, txq->rs_thresh);
1570
1571         if (txq->nb_free < txq->free_thresh)
1572                 iavf_tx_free_bufs(txq);
1573
1574         nb_commit = nb_pkts = (uint16_t)RTE_MIN(txq->nb_free, nb_pkts);
1575         if (unlikely(nb_pkts == 0))
1576                 return 0;
1577
1578         tx_id = txq->tx_tail;
1579         txdp = &txq->tx_ring[tx_id];
1580         txep = &txq->sw_ring[tx_id];
1581
1582         txq->nb_free = (uint16_t)(txq->nb_free - nb_pkts);
1583
1584         n = (uint16_t)(txq->nb_tx_desc - tx_id);
1585         if (nb_commit >= n) {
1586                 tx_backlog_entry(txep, tx_pkts, n);
1587
1588                 iavf_vtx(txdp, tx_pkts, n - 1, flags);
1589                 tx_pkts += (n - 1);
1590                 txdp += (n - 1);
1591
1592                 iavf_vtx1(txdp, *tx_pkts++, rs);
1593
1594                 nb_commit = (uint16_t)(nb_commit - n);
1595
1596                 tx_id = 0;
1597                 txq->next_rs = (uint16_t)(txq->rs_thresh - 1);
1598
1599                 /* avoid reach the end of ring */
1600                 txdp = &txq->tx_ring[tx_id];
1601                 txep = &txq->sw_ring[tx_id];
1602         }
1603
1604         tx_backlog_entry(txep, tx_pkts, nb_commit);
1605
1606         iavf_vtx(txdp, tx_pkts, nb_commit, flags);
1607
1608         tx_id = (uint16_t)(tx_id + nb_commit);
1609         if (tx_id > txq->next_rs) {
1610                 txq->tx_ring[txq->next_rs].cmd_type_offset_bsz |=
1611                         rte_cpu_to_le_64(((uint64_t)IAVF_TX_DESC_CMD_RS) <<
1612                                          IAVF_TXD_QW1_CMD_SHIFT);
1613                 txq->next_rs =
1614                         (uint16_t)(txq->next_rs + txq->rs_thresh);
1615         }
1616
1617         txq->tx_tail = tx_id;
1618
1619         IAVF_PCI_REG_WRITE(txq->qtx_tail, txq->tx_tail);
1620
1621         return nb_pkts;
1622 }
1623
1624 uint16_t
1625 iavf_xmit_pkts_vec_avx2(void *tx_queue, struct rte_mbuf **tx_pkts,
1626                         uint16_t nb_pkts)
1627 {
1628         uint16_t nb_tx = 0;
1629         struct iavf_tx_queue *txq = (struct iavf_tx_queue *)tx_queue;
1630
1631         while (nb_pkts) {
1632                 uint16_t ret, num;
1633
1634                 num = (uint16_t)RTE_MIN(nb_pkts, txq->rs_thresh);
1635                 ret = iavf_xmit_fixed_burst_vec_avx2(tx_queue, &tx_pkts[nb_tx],
1636                                                      num);
1637                 nb_tx += ret;
1638                 nb_pkts -= ret;
1639                 if (ret < num)
1640                         break;
1641         }
1642
1643         return nb_tx;
1644 }