drivers/net/iavf/iavf_rxtx_vec_avx512.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2020 Intel Corporation
   3  */
   4
   5 #include "iavf_rxtx_vec_common.h"
   6
   7 #include <rte_vect.h>
   8
   9 #ifndef __INTEL_COMPILER
  10 #pragma GCC diagnostic ignored "-Wcast-qual"
  11 #endif
  12
  13 #define IAVF_DESCS_PER_LOOP_AVX 8
  14 #define PKTLEN_SHIFT 10
  15
  16 /******************************************************************************
  17  * If user knows a specific offload is not enabled by APP,
  18  * the macro can be commented to save the effort of fast path.
  19  * Currently below 2 features are supported in RX path,
  20  * 1, checksum offload
  21  * 2, VLAN/QINQ stripping
  22  * 3, RSS hash
  23  * 4, packet type analysis
  24  * 5, flow director ID report
  25  ******************************************************************************/
  26 #define IAVF_RX_CSUM_OFFLOAD
  27 #define IAVF_RX_VLAN_OFFLOAD
  28 #define IAVF_RX_RSS_OFFLOAD
  29 #define IAVF_RX_PTYPE_OFFLOAD
  30 #define IAVF_RX_FDIR_OFFLOAD
  31
  32 static __rte_always_inline void
  33 iavf_rxq_rearm(struct iavf_rx_queue *rxq)
  34 {
  35         int i;
  36         uint16_t rx_id;
  37         volatile union iavf_rx_desc *rxdp;
  38         struct rte_mempool_cache *cache =
  39                 rte_mempool_default_cache(rxq->mp, rte_lcore_id());
  40         struct rte_mbuf **rxp = &rxq->sw_ring[rxq->rxrearm_start];
  41
  42         rxdp = rxq->rx_ring + rxq->rxrearm_start;
  43
  44         if (unlikely(!cache))
  45                 return iavf_rxq_rearm_common(rxq, true);
  46
  47         /* We need to pull 'n' more MBUFs into the software ring from mempool
  48          * We inline the mempool function here, so we can vectorize the copy
  49          * from the cache into the shadow ring.
  50          */
  51
  52         /* Can this be satisfied from the cache? */
  53         if (cache->len < IAVF_RXQ_REARM_THRESH) {
  54                 /* No. Backfill the cache first, and then fill from it */
  55                 uint32_t req = IAVF_RXQ_REARM_THRESH + (cache->size -
  56                                                         cache->len);
  57
  58                 /* How many do we require i.e. number to fill the cache + the request */
  59                 int ret = rte_mempool_ops_dequeue_bulk
  60                                 (rxq->mp, &cache->objs[cache->len], req);
  61                 if (ret == 0) {
  62                         cache->len += req;
  63                 } else {
  64                         if (rxq->rxrearm_nb + IAVF_RXQ_REARM_THRESH >=
  65                             rxq->nb_rx_desc) {
  66                                 __m128i dma_addr0;
  67
  68                                 dma_addr0 = _mm_setzero_si128();
  69                                 for (i = 0; i < IAVF_VPMD_DESCS_PER_LOOP; i++) {
  70                                         rxp[i] = &rxq->fake_mbuf;
  71                                         _mm_storeu_si128((__m128i *)&rxdp[i].read,
  72                                                          dma_addr0);
  73                                 }
  74                         }
  75                         rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed +=
  76                                         IAVF_RXQ_REARM_THRESH;
  77                         return;
  78                 }
  79         }
  80
  81         const __m512i iova_offsets =  _mm512_set1_epi64(offsetof
  82                                                         (struct rte_mbuf, buf_iova));
  83         const __m512i headroom = _mm512_set1_epi64(RTE_PKTMBUF_HEADROOM);
  84
  85 #ifndef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
  86         /* to shuffle the addresses to correct slots. Values 4-7 will contain
  87          * zeros, so use 7 for a zero-value.
  88          */
  89         const __m512i permute_idx = _mm512_set_epi64(7, 7, 3, 1, 7, 7, 2, 0);
  90 #else
  91         const __m512i permute_idx = _mm512_set_epi64(7, 3, 6, 2, 5, 1, 4, 0);
  92 #endif
  93
  94         /* Initialize the mbufs in vector, process 8 mbufs in one loop, taking
  95          * from mempool cache and populating both shadow and HW rings
  96          */
  97         for (i = 0; i < IAVF_RXQ_REARM_THRESH / IAVF_DESCS_PER_LOOP_AVX; i++) {
  98                 const __m512i mbuf_ptrs = _mm512_loadu_si512
  99                         (&cache->objs[cache->len - IAVF_DESCS_PER_LOOP_AVX]);
 100                 _mm512_storeu_si512(rxp, mbuf_ptrs);
 101
 102                 const __m512i iova_base_addrs = _mm512_i64gather_epi64
 103                                 (_mm512_add_epi64(mbuf_ptrs, iova_offsets),
 104                                  0, /* base */
 105                                  1  /* scale */);
 106                 const __m512i iova_addrs = _mm512_add_epi64(iova_base_addrs,
 107                                 headroom);
 108 #ifndef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
 109                 const __m512i iovas0 = _mm512_castsi256_si512
 110                                 (_mm512_extracti64x4_epi64(iova_addrs, 0));
 111                 const __m512i iovas1 = _mm512_castsi256_si512
 112                                 (_mm512_extracti64x4_epi64(iova_addrs, 1));
 113
 114                 /* permute leaves desc 2-3 addresses in header address slots 0-1
 115                  * but these are ignored by driver since header split not
 116                  * enabled. Similarly for desc 6 & 7.
 117                  */
 118                 const __m512i desc0_1 = _mm512_permutexvar_epi64
 119                                 (permute_idx,
 120                                  iovas0);
 121                 const __m512i desc2_3 = _mm512_bsrli_epi128(desc0_1, 8);
 122
 123                 const __m512i desc4_5 = _mm512_permutexvar_epi64
 124                                 (permute_idx,
 125                                  iovas1);
 126                 const __m512i desc6_7 = _mm512_bsrli_epi128(desc4_5, 8);
 127
 128                 _mm512_storeu_si512((void *)rxdp, desc0_1);
 129                 _mm512_storeu_si512((void *)(rxdp + 2), desc2_3);
 130                 _mm512_storeu_si512((void *)(rxdp + 4), desc4_5);
 131                 _mm512_storeu_si512((void *)(rxdp + 6), desc6_7);
 132 #else
 133                 /* permute leaves desc 4-7 addresses in header address slots 0-3
 134                  * but these are ignored by driver since header split not
 135                  * enabled.
 136                  */
 137                 const __m512i desc0_3 = _mm512_permutexvar_epi64(permute_idx,
 138                                                                  iova_addrs);
 139                 const __m512i desc4_7 = _mm512_bsrli_epi128(desc0_3, 8);
 140
 141                 _mm512_storeu_si512((void *)rxdp, desc0_3);
 142                 _mm512_storeu_si512((void *)(rxdp + 4), desc4_7);
 143 #endif
 144                 rxp += IAVF_DESCS_PER_LOOP_AVX;
 145                 rxdp += IAVF_DESCS_PER_LOOP_AVX;
 146                 cache->len -= IAVF_DESCS_PER_LOOP_AVX;
 147         }
 148
 149         rxq->rxrearm_start += IAVF_RXQ_REARM_THRESH;
 150         if (rxq->rxrearm_start >= rxq->nb_rx_desc)
 151                 rxq->rxrearm_start = 0;
 152
 153         rxq->rxrearm_nb -= IAVF_RXQ_REARM_THRESH;
 154
 155         rx_id = (uint16_t)((rxq->rxrearm_start == 0) ?
 156                            (rxq->nb_rx_desc - 1) : (rxq->rxrearm_start - 1));
 157
 158         /* Update the tail pointer on the NIC */
 159         IAVF_PCI_REG_WC_WRITE(rxq->qrx_tail, rx_id);
 160 }
 161
 162 #define IAVF_RX_LEN_MASK 0x80808080
 163 static __rte_always_inline uint16_t
 164 _iavf_recv_raw_pkts_vec_avx512(struct iavf_rx_queue *rxq,
 165                                struct rte_mbuf **rx_pkts,
 166                                uint16_t nb_pkts, uint8_t *split_packet,
 167                                bool offload)
 168 {
 169 #ifdef IAVF_RX_PTYPE_OFFLOAD
 170         const uint32_t *type_table = rxq->vsi->adapter->ptype_tbl;
 171 #endif
 172
 173         const __m256i mbuf_init = _mm256_set_epi64x(0, 0, 0,
 174                                                     rxq->mbuf_initializer);
 175         struct rte_mbuf **sw_ring = &rxq->sw_ring[rxq->rx_tail];
 176         volatile union iavf_rx_desc *rxdp = rxq->rx_ring + rxq->rx_tail;
 177
 178         rte_prefetch0(rxdp);
 179
 180         /* nb_pkts has to be floor-aligned to IAVF_DESCS_PER_LOOP_AVX */
 181         nb_pkts = RTE_ALIGN_FLOOR(nb_pkts, IAVF_DESCS_PER_LOOP_AVX);
 182
 183         /* See if we need to rearm the RX queue - gives the prefetch a bit
 184          * of time to act
 185          */
 186         if (rxq->rxrearm_nb > IAVF_RXQ_REARM_THRESH)
 187                 iavf_rxq_rearm(rxq);
 188
 189         /* Before we start moving massive data around, check to see if
 190          * there is actually a packet available
 191          */
 192         if (!(rxdp->wb.qword1.status_error_len &
 193               rte_cpu_to_le_32(1 << IAVF_RX_DESC_STATUS_DD_SHIFT)))
 194                 return 0;
 195
 196         /* constants used in processing loop */
 197         const __m512i crc_adjust =
 198                 _mm512_set_epi32
 199                         (/* 1st descriptor */
 200                          0,             /* ignore non-length fields */
 201                          -rxq->crc_len, /* sub crc on data_len */
 202                          -rxq->crc_len, /* sub crc on pkt_len */
 203                          0,             /* ignore pkt_type field */
 204                          /* 2nd descriptor */
 205                          0,             /* ignore non-length fields */
 206                          -rxq->crc_len, /* sub crc on data_len */
 207                          -rxq->crc_len, /* sub crc on pkt_len */
 208                          0,             /* ignore pkt_type field */
 209                          /* 3rd descriptor */
 210                          0,             /* ignore non-length fields */
 211                          -rxq->crc_len, /* sub crc on data_len */
 212                          -rxq->crc_len, /* sub crc on pkt_len */
 213                          0,             /* ignore pkt_type field */
 214                          /* 4th descriptor */
 215                          0,             /* ignore non-length fields */
 216                          -rxq->crc_len, /* sub crc on data_len */
 217                          -rxq->crc_len, /* sub crc on pkt_len */
 218                          0              /* ignore pkt_type field */
 219                         );
 220
 221         /* 8 packets DD mask, LSB in each 32-bit value */
 222         const __m256i dd_check = _mm256_set1_epi32(1);
 223
 224         /* 8 packets EOP mask, second-LSB in each 32-bit value */
 225         const __m256i eop_check = _mm256_slli_epi32(dd_check,
 226                         IAVF_RX_DESC_STATUS_EOF_SHIFT);
 227
 228         /* mask to shuffle from desc. to mbuf (4 descriptors)*/
 229         const __m512i shuf_msk =
 230                 _mm512_set_epi32
 231                         (/* 1st descriptor */
 232                          0x07060504,    /* octet 4~7, 32bits rss */
 233                          0x03020F0E,    /* octet 2~3, low 16 bits vlan_macip */
 234                                         /* octet 15~14, 16 bits data_len */
 235                          0xFFFF0F0E,    /* skip high 16 bits pkt_len, zero out */
 236                                         /* octet 15~14, low 16 bits pkt_len */
 237                          0xFFFFFFFF,    /* pkt_type set as unknown */
 238                          /* 2nd descriptor */
 239                          0x07060504,    /* octet 4~7, 32bits rss */
 240                          0x03020F0E,    /* octet 2~3, low 16 bits vlan_macip */
 241                                         /* octet 15~14, 16 bits data_len */
 242                          0xFFFF0F0E,    /* skip high 16 bits pkt_len, zero out */
 243                                         /* octet 15~14, low 16 bits pkt_len */
 244                          0xFFFFFFFF,    /* pkt_type set as unknown */
 245                          /* 3rd descriptor */
 246                          0x07060504,    /* octet 4~7, 32bits rss */
 247                          0x03020F0E,    /* octet 2~3, low 16 bits vlan_macip */
 248                                         /* octet 15~14, 16 bits data_len */
 249                          0xFFFF0F0E,    /* skip high 16 bits pkt_len, zero out */
 250                                         /* octet 15~14, low 16 bits pkt_len */
 251                          0xFFFFFFFF,    /* pkt_type set as unknown */
 252                          /* 4th descriptor */
 253                          0x07060504,    /* octet 4~7, 32bits rss */
 254                          0x03020F0E,    /* octet 2~3, low 16 bits vlan_macip */
 255                                         /* octet 15~14, 16 bits data_len */
 256                          0xFFFF0F0E,    /* skip high 16 bits pkt_len, zero out */
 257                                         /* octet 15~14, low 16 bits pkt_len */
 258                          0xFFFFFFFF     /* pkt_type set as unknown */
 259                         );
 260         /**
 261          * compile-time check the above crc and shuffle layout is correct.
 262          * NOTE: the first field (lowest address) is given last in set_epi
 263          * calls above.
 264          */
 265         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, pkt_len) !=
 266                          offsetof(struct rte_mbuf, rx_descriptor_fields1) + 4);
 267         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, data_len) !=
 268                          offsetof(struct rte_mbuf, rx_descriptor_fields1) + 8);
 269         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, vlan_tci) !=
 270                          offsetof(struct rte_mbuf, rx_descriptor_fields1) + 10);
 271         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, hash) !=
 272                          offsetof(struct rte_mbuf, rx_descriptor_fields1) + 12);
 273
 274         uint16_t i, received;
 275
 276         for (i = 0, received = 0; i < nb_pkts;
 277              i += IAVF_DESCS_PER_LOOP_AVX,
 278              rxdp += IAVF_DESCS_PER_LOOP_AVX) {
 279                 /* step 1, copy over 8 mbuf pointers to rx_pkts array */
 280                 _mm256_storeu_si256((void *)&rx_pkts[i],
 281                                     _mm256_loadu_si256((void *)&sw_ring[i]));
 282 #ifdef RTE_ARCH_X86_64
 283                 _mm256_storeu_si256
 284                         ((void *)&rx_pkts[i + 4],
 285                          _mm256_loadu_si256((void *)&sw_ring[i + 4]));
 286 #endif
 287
 288                 __m512i raw_desc0_3, raw_desc4_7;
 289                 const __m128i raw_desc7 =
 290                         _mm_load_si128((void *)(rxdp + 7));
 291                 rte_compiler_barrier();
 292                 const __m128i raw_desc6 =
 293                         _mm_load_si128((void *)(rxdp + 6));
 294                 rte_compiler_barrier();
 295                 const __m128i raw_desc5 =
 296                         _mm_load_si128((void *)(rxdp + 5));
 297                 rte_compiler_barrier();
 298                 const __m128i raw_desc4 =
 299                         _mm_load_si128((void *)(rxdp + 4));
 300                 rte_compiler_barrier();
 301                 const __m128i raw_desc3 =
 302                         _mm_load_si128((void *)(rxdp + 3));
 303                 rte_compiler_barrier();
 304                 const __m128i raw_desc2 =
 305                         _mm_load_si128((void *)(rxdp + 2));
 306                 rte_compiler_barrier();
 307                 const __m128i raw_desc1 =
 308                         _mm_load_si128((void *)(rxdp + 1));
 309                 rte_compiler_barrier();
 310                 const __m128i raw_desc0 =
 311                         _mm_load_si128((void *)(rxdp + 0));
 312
 313                 raw_desc4_7 = _mm512_broadcast_i32x4(raw_desc4);
 314                 raw_desc4_7 = _mm512_inserti32x4(raw_desc4_7, raw_desc5, 1);
 315                 raw_desc4_7 = _mm512_inserti32x4(raw_desc4_7, raw_desc6, 2);
 316                 raw_desc4_7 = _mm512_inserti32x4(raw_desc4_7, raw_desc7, 3);
 317                 raw_desc0_3 = _mm512_broadcast_i32x4(raw_desc0);
 318                 raw_desc0_3 = _mm512_inserti32x4(raw_desc0_3, raw_desc1, 1);
 319                 raw_desc0_3 = _mm512_inserti32x4(raw_desc0_3, raw_desc2, 2);
 320                 raw_desc0_3 = _mm512_inserti32x4(raw_desc0_3, raw_desc3, 3);
 321
 322                 if (split_packet) {
 323                         int j;
 324
 325                         for (j = 0; j < IAVF_DESCS_PER_LOOP_AVX; j++)
 326                                 rte_mbuf_prefetch_part2(rx_pkts[i + j]);
 327                 }
 328
 329                 /**
 330                  * convert descriptors 4-7 into mbufs, adjusting length and
 331                  * re-arranging fields. Then write into the mbuf
 332                  */
 333                 const __m512i len4_7 = _mm512_slli_epi32(raw_desc4_7,
 334                                                          PKTLEN_SHIFT);
 335                 const __m512i desc4_7 = _mm512_mask_blend_epi16(IAVF_RX_LEN_MASK,
 336                                                                 raw_desc4_7,
 337                                                                 len4_7);
 338                 __m512i mb4_7 = _mm512_shuffle_epi8(desc4_7, shuf_msk);
 339
 340                 mb4_7 = _mm512_add_epi32(mb4_7, crc_adjust);
 341 #ifdef IAVF_RX_PTYPE_OFFLOAD
 342                 /**
 343                  * to get packet types, shift 64-bit values down 30 bits
 344                  * and so ptype is in lower 8-bits in each
 345                  */
 346                 const __m512i ptypes4_7 = _mm512_srli_epi64(desc4_7, 30);
 347                 const __m256i ptypes6_7 = _mm512_extracti64x4_epi64(ptypes4_7, 1);
 348                 const __m256i ptypes4_5 = _mm512_extracti64x4_epi64(ptypes4_7, 0);
 349                 const uint8_t ptype7 = _mm256_extract_epi8(ptypes6_7, 24);
 350                 const uint8_t ptype6 = _mm256_extract_epi8(ptypes6_7, 8);
 351                 const uint8_t ptype5 = _mm256_extract_epi8(ptypes4_5, 24);
 352                 const uint8_t ptype4 = _mm256_extract_epi8(ptypes4_5, 8);
 353
 354                 const __m512i ptype4_7 = _mm512_set_epi32
 355                         (0, 0, 0, type_table[ptype7],
 356                          0, 0, 0, type_table[ptype6],
 357                          0, 0, 0, type_table[ptype5],
 358                          0, 0, 0, type_table[ptype4]);
 359                 mb4_7 = _mm512_mask_blend_epi32(0x1111, mb4_7, ptype4_7);
 360 #endif
 361
 362                 /**
 363                  * convert descriptors 0-3 into mbufs, adjusting length and
 364                  * re-arranging fields. Then write into the mbuf
 365                  */
 366                 const __m512i len0_3 = _mm512_slli_epi32(raw_desc0_3,
 367                                                          PKTLEN_SHIFT);
 368                 const __m512i desc0_3 = _mm512_mask_blend_epi16(IAVF_RX_LEN_MASK,
 369                                                                 raw_desc0_3,
 370                                                                 len0_3);
 371                 __m512i mb0_3 = _mm512_shuffle_epi8(desc0_3, shuf_msk);
 372
 373                 mb0_3 = _mm512_add_epi32(mb0_3, crc_adjust);
 374 #ifdef IAVF_RX_PTYPE_OFFLOAD
 375                 /* get the packet types */
 376                 const __m512i ptypes0_3 = _mm512_srli_epi64(desc0_3, 30);
 377                 const __m256i ptypes2_3 = _mm512_extracti64x4_epi64(ptypes0_3, 1);
 378                 const __m256i ptypes0_1 = _mm512_extracti64x4_epi64(ptypes0_3, 0);
 379                 const uint8_t ptype3 = _mm256_extract_epi8(ptypes2_3, 24);
 380                 const uint8_t ptype2 = _mm256_extract_epi8(ptypes2_3, 8);
 381                 const uint8_t ptype1 = _mm256_extract_epi8(ptypes0_1, 24);
 382                 const uint8_t ptype0 = _mm256_extract_epi8(ptypes0_1, 8);
 383
 384                 const __m512i ptype0_3 = _mm512_set_epi32
 385                         (0, 0, 0, type_table[ptype3],
 386                          0, 0, 0, type_table[ptype2],
 387                          0, 0, 0, type_table[ptype1],
 388                          0, 0, 0, type_table[ptype0]);
 389                 mb0_3 = _mm512_mask_blend_epi32(0x1111, mb0_3, ptype0_3);
 390 #endif
 391
 392                 /**
 393                  * use permute/extract to get status content
 394                  * After the operations, the packets status flags are in the
 395                  * order (hi->lo): [1, 3, 5, 7, 0, 2, 4, 6]
 396                  */
 397                 /* merge the status bits into one register */
 398                 const __m512i status_permute_msk = _mm512_set_epi32
 399                         (0, 0, 0, 0,
 400                          0, 0, 0, 0,
 401                          22, 30, 6, 14,
 402                          18, 26, 2, 10);
 403                 const __m512i raw_status0_7 = _mm512_permutex2var_epi32
 404                         (raw_desc4_7, status_permute_msk, raw_desc0_3);
 405                 __m256i status0_7 = _mm512_extracti64x4_epi64
 406                         (raw_status0_7, 0);
 407
 408                 /* now do flag manipulation */
 409
 410                 /* merge flags */
 411                 __m256i mbuf_flags = _mm256_set1_epi32(0);
 412
 413                 if (offload) {
 414 #if defined(IAVF_RX_CSUM_OFFLOAD) || defined(IAVF_RX_VLAN_OFFLOAD) || defined(IAVF_RX_RSS_OFFLOAD)
 415                         /* Status/Error flag masks */
 416                         /**
 417                          * mask everything except RSS, flow director and VLAN flags
 418                          * bit2 is for VLAN tag, bit11 for flow director indication
 419                          * bit13:12 for RSS indication. Bits 3-5 of error
 420                          * field (bits 22-24) are for IP/L4 checksum errors
 421                          */
 422                         const __m256i flags_mask =
 423                                 _mm256_set1_epi32((1 << 2) | (1 << 11) |
 424                                                   (3 << 12) | (7 << 22));
 425 #endif
 426
 427 #ifdef IAVF_RX_VLAN_OFFLOAD
 428                         /**
 429                          * data to be shuffled by result of flag mask. If VLAN bit is set,
 430                          * (bit 2), then position 4 in this array will be used in the
 431                          * destination
 432                          */
 433                         const __m256i vlan_flags_shuf =
 434                                 _mm256_set_epi32(0, 0, RTE_MBUF_F_RX_VLAN | RTE_MBUF_F_RX_VLAN_STRIPPED, 0,
 435                                                  0, 0, RTE_MBUF_F_RX_VLAN | RTE_MBUF_F_RX_VLAN_STRIPPED, 0);
 436 #endif
 437
 438 #ifdef IAVF_RX_RSS_OFFLOAD
 439                         /**
 440                          * data to be shuffled by result of flag mask, shifted down 11.
 441                          * If RSS/FDIR bits are set, shuffle moves appropriate flags in
 442                          * place.
 443                          */
 444                         const __m256i rss_flags_shuf =
 445                                 _mm256_set_epi8(0, 0, 0, 0, 0, 0, 0, 0,
 446                                                 RTE_MBUF_F_RX_RSS_HASH | RTE_MBUF_F_RX_FDIR, RTE_MBUF_F_RX_RSS_HASH,
 447                                                 0, 0, 0, 0, RTE_MBUF_F_RX_FDIR, 0,/* end up 128-bits */
 448                                                 0, 0, 0, 0, 0, 0, 0, 0,
 449                                                 RTE_MBUF_F_RX_RSS_HASH | RTE_MBUF_F_RX_FDIR, RTE_MBUF_F_RX_RSS_HASH,
 450                                                 0, 0, 0, 0, RTE_MBUF_F_RX_FDIR, 0);
 451 #endif
 452
 453 #ifdef IAVF_RX_CSUM_OFFLOAD
 454                         /**
 455                          * data to be shuffled by the result of the flags mask shifted by 22
 456                          * bits.  This gives use the l3_l4 flags.
 457                          */
 458                         const __m256i l3_l4_flags_shuf = _mm256_set_epi8(0, 0, 0, 0, 0, 0, 0, 0,
 459                                         /* shift right 1 bit to make sure it not exceed 255 */
 460                                         (RTE_MBUF_F_RX_OUTER_IP_CKSUM_BAD | RTE_MBUF_F_RX_L4_CKSUM_BAD |
 461                                          RTE_MBUF_F_RX_IP_CKSUM_BAD) >> 1,
 462                                         (RTE_MBUF_F_RX_IP_CKSUM_GOOD | RTE_MBUF_F_RX_OUTER_IP_CKSUM_BAD |
 463                                          RTE_MBUF_F_RX_L4_CKSUM_BAD) >> 1,
 464                                         (RTE_MBUF_F_RX_OUTER_IP_CKSUM_BAD | RTE_MBUF_F_RX_IP_CKSUM_BAD) >> 1,
 465                                         (RTE_MBUF_F_RX_IP_CKSUM_GOOD | RTE_MBUF_F_RX_OUTER_IP_CKSUM_BAD) >> 1,
 466                                         (RTE_MBUF_F_RX_L4_CKSUM_BAD | RTE_MBUF_F_RX_IP_CKSUM_BAD) >> 1,
 467                                         (RTE_MBUF_F_RX_IP_CKSUM_GOOD | RTE_MBUF_F_RX_L4_CKSUM_BAD) >> 1,
 468                                         RTE_MBUF_F_RX_IP_CKSUM_BAD >> 1,
 469                                         (RTE_MBUF_F_RX_IP_CKSUM_GOOD | RTE_MBUF_F_RX_L4_CKSUM_GOOD) >> 1,
 470                                         /* second 128-bits */
 471                                         0, 0, 0, 0, 0, 0, 0, 0,
 472                                         (RTE_MBUF_F_RX_OUTER_IP_CKSUM_BAD | RTE_MBUF_F_RX_L4_CKSUM_BAD |
 473                                          RTE_MBUF_F_RX_IP_CKSUM_BAD) >> 1,
 474                                         (RTE_MBUF_F_RX_IP_CKSUM_GOOD | RTE_MBUF_F_RX_OUTER_IP_CKSUM_BAD |
 475                                          RTE_MBUF_F_RX_L4_CKSUM_BAD) >> 1,
 476                                         (RTE_MBUF_F_RX_OUTER_IP_CKSUM_BAD | RTE_MBUF_F_RX_IP_CKSUM_BAD) >> 1,
 477                                         (RTE_MBUF_F_RX_IP_CKSUM_GOOD | RTE_MBUF_F_RX_OUTER_IP_CKSUM_BAD) >> 1,
 478                                         (RTE_MBUF_F_RX_L4_CKSUM_BAD | RTE_MBUF_F_RX_IP_CKSUM_BAD) >> 1,
 479                                         (RTE_MBUF_F_RX_IP_CKSUM_GOOD | RTE_MBUF_F_RX_L4_CKSUM_BAD) >> 1,
 480                                         RTE_MBUF_F_RX_IP_CKSUM_BAD >> 1,
 481                                         (RTE_MBUF_F_RX_IP_CKSUM_GOOD | RTE_MBUF_F_RX_L4_CKSUM_GOOD) >> 1);
 482
 483                         const __m256i cksum_mask =
 484                                 _mm256_set1_epi32(RTE_MBUF_F_RX_IP_CKSUM_GOOD | RTE_MBUF_F_RX_IP_CKSUM_BAD |
 485                                                   RTE_MBUF_F_RX_L4_CKSUM_GOOD | RTE_MBUF_F_RX_L4_CKSUM_BAD |
 486                                                   RTE_MBUF_F_RX_OUTER_IP_CKSUM_BAD);
 487 #endif
 488
 489 #if defined(IAVF_RX_CSUM_OFFLOAD) || defined(IAVF_RX_VLAN_OFFLOAD) || defined(IAVF_RX_RSS_OFFLOAD)
 490                         /* get only flag/error bits we want */
 491                         const __m256i flag_bits =
 492                                 _mm256_and_si256(status0_7, flags_mask);
 493 #endif
 494                         /* set vlan and rss flags */
 495 #ifdef IAVF_RX_VLAN_OFFLOAD
 496                         const __m256i vlan_flags =
 497                                 _mm256_shuffle_epi8(vlan_flags_shuf, flag_bits);
 498 #endif
 499 #ifdef IAVF_RX_RSS_OFFLOAD
 500                         const __m256i rss_flags =
 501                                 _mm256_shuffle_epi8(rss_flags_shuf,
 502                                                     _mm256_srli_epi32(flag_bits, 11));
 503 #endif
 504 #ifdef IAVF_RX_CSUM_OFFLOAD
 505                         /**
 506                          * l3_l4_error flags, shuffle, then shift to correct adjustment
 507                          * of flags in flags_shuf, and finally mask out extra bits
 508                          */
 509                         __m256i l3_l4_flags = _mm256_shuffle_epi8(l3_l4_flags_shuf,
 510                                                         _mm256_srli_epi32(flag_bits, 22));
 511                         l3_l4_flags = _mm256_slli_epi32(l3_l4_flags, 1);
 512                         l3_l4_flags = _mm256_and_si256(l3_l4_flags, cksum_mask);
 513 #endif
 514
 515 #ifdef IAVF_RX_CSUM_OFFLOAD
 516                         mbuf_flags = _mm256_or_si256(mbuf_flags, l3_l4_flags);
 517 #endif
 518 #ifdef IAVF_RX_RSS_OFFLOAD
 519                         mbuf_flags = _mm256_or_si256(mbuf_flags, rss_flags);
 520 #endif
 521 #ifdef IAVF_RX_VLAN_OFFLOAD
 522                         mbuf_flags = _mm256_or_si256(mbuf_flags, vlan_flags);
 523 #endif
 524                 }
 525
 526                 /**
 527                  * At this point, we have the 8 sets of flags in the low 16-bits
 528                  * of each 32-bit value in vlan0.
 529                  * We want to extract these, and merge them with the mbuf init
 530                  * data so we can do a single write to the mbuf to set the flags
 531                  * and all the other initialization fields. Extracting the
 532                  * appropriate flags means that we have to do a shift and blend
 533                  * for each mbuf before we do the write. However, we can also
 534                  * add in the previously computed rx_descriptor fields to
 535                  * make a single 256-bit write per mbuf
 536                  */
 537                 /* check the structure matches expectations */
 538                 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, ol_flags) !=
 539                                  offsetof(struct rte_mbuf, rearm_data) + 8);
 540                 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, rearm_data) !=
 541                                  RTE_ALIGN(offsetof(struct rte_mbuf,
 542                                                     rearm_data),
 543                                                     16));
 544                 /* build up data and do writes */
 545                 __m256i rearm0, rearm1, rearm2, rearm3, rearm4, rearm5,
 546                         rearm6, rearm7;
 547                 const __m256i mb4_5 = _mm512_extracti64x4_epi64(mb4_7, 0);
 548                 const __m256i mb6_7 = _mm512_extracti64x4_epi64(mb4_7, 1);
 549                 const __m256i mb0_1 = _mm512_extracti64x4_epi64(mb0_3, 0);
 550                 const __m256i mb2_3 = _mm512_extracti64x4_epi64(mb0_3, 1);
 551
 552                 if (offload) {
 553                         rearm6 = _mm256_blend_epi32(mbuf_init,
 554                                                     _mm256_slli_si256(mbuf_flags, 8),
 555                                                     0x04);
 556                         rearm4 = _mm256_blend_epi32(mbuf_init,
 557                                                     _mm256_slli_si256(mbuf_flags, 4),
 558                                                     0x04);
 559                         rearm2 = _mm256_blend_epi32(mbuf_init, mbuf_flags, 0x04);
 560                         rearm0 = _mm256_blend_epi32(mbuf_init,
 561                                                     _mm256_srli_si256(mbuf_flags, 4),
 562                                                     0x04);
 563                         /* permute to add in the rx_descriptor e.g. rss fields */
 564                         rearm6 = _mm256_permute2f128_si256(rearm6, mb6_7, 0x20);
 565                         rearm4 = _mm256_permute2f128_si256(rearm4, mb4_5, 0x20);
 566                         rearm2 = _mm256_permute2f128_si256(rearm2, mb2_3, 0x20);
 567                         rearm0 = _mm256_permute2f128_si256(rearm0, mb0_1, 0x20);
 568                 } else {
 569                         rearm6 = _mm256_permute2f128_si256(mbuf_init, mb6_7, 0x20);
 570                         rearm4 = _mm256_permute2f128_si256(mbuf_init, mb4_5, 0x20);
 571                         rearm2 = _mm256_permute2f128_si256(mbuf_init, mb2_3, 0x20);
 572                         rearm0 = _mm256_permute2f128_si256(mbuf_init, mb0_1, 0x20);
 573                 }
 574                 /* write to mbuf */
 575                 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 6]->rearm_data,
 576                                     rearm6);
 577                 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 4]->rearm_data,
 578                                     rearm4);
 579                 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 2]->rearm_data,
 580                                     rearm2);
 581                 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 0]->rearm_data,
 582                                     rearm0);
 583
 584                 /* repeat for the odd mbufs */
 585                 if (offload) {
 586                         const __m256i odd_flags =
 587                                 _mm256_castsi128_si256
 588                                         (_mm256_extracti128_si256(mbuf_flags, 1));
 589                         rearm7 = _mm256_blend_epi32(mbuf_init,
 590                                                     _mm256_slli_si256(odd_flags, 8),
 591                                                     0x04);
 592                         rearm5 = _mm256_blend_epi32(mbuf_init,
 593                                                     _mm256_slli_si256(odd_flags, 4),
 594                                                     0x04);
 595                         rearm3 = _mm256_blend_epi32(mbuf_init, odd_flags, 0x04);
 596                         rearm1 = _mm256_blend_epi32(mbuf_init,
 597                                                     _mm256_srli_si256(odd_flags, 4),
 598                                                     0x04);
 599                         /* since odd mbufs are already in hi 128-bits use blend */
 600                         rearm7 = _mm256_blend_epi32(rearm7, mb6_7, 0xF0);
 601                         rearm5 = _mm256_blend_epi32(rearm5, mb4_5, 0xF0);
 602                         rearm3 = _mm256_blend_epi32(rearm3, mb2_3, 0xF0);
 603                         rearm1 = _mm256_blend_epi32(rearm1, mb0_1, 0xF0);
 604                 } else {
 605                         rearm7 = _mm256_blend_epi32(mbuf_init, mb6_7, 0xF0);
 606                         rearm5 = _mm256_blend_epi32(mbuf_init, mb4_5, 0xF0);
 607                         rearm3 = _mm256_blend_epi32(mbuf_init, mb2_3, 0xF0);
 608                         rearm1 = _mm256_blend_epi32(mbuf_init, mb0_1, 0xF0);
 609                 }
 610                 /* again write to mbufs */
 611                 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 7]->rearm_data,
 612                                     rearm7);
 613                 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 5]->rearm_data,
 614                                     rearm5);
 615                 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 3]->rearm_data,
 616                                     rearm3);
 617                 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 1]->rearm_data,
 618                                     rearm1);
 619
 620                 /* extract and record EOP bit */
 621                 if (split_packet) {
 622                         const __m128i eop_mask =
 623                                 _mm_set1_epi16(1 << IAVF_RX_DESC_STATUS_EOF_SHIFT);
 624                         const __m256i eop_bits256 = _mm256_and_si256(status0_7,
 625                                                                      eop_check);
 626                         /* pack status bits into a single 128-bit register */
 627                         const __m128i eop_bits =
 628                                 _mm_packus_epi32
 629                                         (_mm256_castsi256_si128(eop_bits256),
 630                                          _mm256_extractf128_si256(eop_bits256,
 631                                                                   1));
 632                         /**
 633                          * flip bits, and mask out the EOP bit, which is now
 634                          * a split-packet bit i.e. !EOP, rather than EOP one.
 635                          */
 636                         __m128i split_bits = _mm_andnot_si128(eop_bits,
 637                                                               eop_mask);
 638                         /**
 639                          * eop bits are out of order, so we need to shuffle them
 640                          * back into order again. In doing so, only use low 8
 641                          * bits, which acts like another pack instruction
 642                          * The original order is (hi->lo): 1,3,5,7,0,2,4,6
 643                          * [Since we use epi8, the 16-bit positions are
 644                          * multiplied by 2 in the eop_shuffle value.]
 645                          */
 646                         __m128i eop_shuffle =
 647                                 _mm_set_epi8(/* zero hi 64b */
 648                                              0xFF, 0xFF, 0xFF, 0xFF,
 649                                              0xFF, 0xFF, 0xFF, 0xFF,
 650                                              /* move values to lo 64b */
 651                                              8, 0, 10, 2,
 652                                              12, 4, 14, 6);
 653                         split_bits = _mm_shuffle_epi8(split_bits, eop_shuffle);
 654                         *(uint64_t *)split_packet =
 655                                 _mm_cvtsi128_si64(split_bits);
 656                         split_packet += IAVF_DESCS_PER_LOOP_AVX;
 657                 }
 658
 659                 /* perform dd_check */
 660                 status0_7 = _mm256_and_si256(status0_7, dd_check);
 661                 status0_7 = _mm256_packs_epi32(status0_7,
 662                                                _mm256_setzero_si256());
 663
 664                 uint64_t burst = __builtin_popcountll
 665                                         (_mm_cvtsi128_si64
 666                                                 (_mm256_extracti128_si256
 667                                                         (status0_7, 1)));
 668                 burst += __builtin_popcountll
 669                                 (_mm_cvtsi128_si64
 670                                         (_mm256_castsi256_si128(status0_7)));
 671                 received += burst;
 672                 if (burst != IAVF_DESCS_PER_LOOP_AVX)
 673                         break;
 674         }
 675
 676         /* update tail pointers */
 677         rxq->rx_tail += received;
 678         rxq->rx_tail &= (rxq->nb_rx_desc - 1);
 679         if ((rxq->rx_tail & 1) == 1 && received > 1) { /* keep aligned */
 680                 rxq->rx_tail--;
 681                 received--;
 682         }
 683         rxq->rxrearm_nb += received;
 684         return received;
 685 }
 686
 687 static __rte_always_inline __m256i
 688 flex_rxd_to_fdir_flags_vec_avx512(const __m256i fdir_id0_7)
 689 {
 690 #define FDID_MIS_MAGIC 0xFFFFFFFF
 691         RTE_BUILD_BUG_ON(RTE_MBUF_F_RX_FDIR != (1 << 2));
 692         RTE_BUILD_BUG_ON(RTE_MBUF_F_RX_FDIR_ID != (1 << 13));
 693         const __m256i pkt_fdir_bit = _mm256_set1_epi32(RTE_MBUF_F_RX_FDIR |
 694                                                        RTE_MBUF_F_RX_FDIR_ID);
 695         /* desc->flow_id field == 0xFFFFFFFF means fdir mismatch */
 696         const __m256i fdir_mis_mask = _mm256_set1_epi32(FDID_MIS_MAGIC);
 697         __m256i fdir_mask = _mm256_cmpeq_epi32(fdir_id0_7,
 698                                                fdir_mis_mask);
 699         /* this XOR op results to bit-reverse the fdir_mask */
 700         fdir_mask = _mm256_xor_si256(fdir_mask, fdir_mis_mask);
 701         const __m256i fdir_flags = _mm256_and_si256(fdir_mask, pkt_fdir_bit);
 702
 703         return fdir_flags;
 704 }
 705
 706 static __rte_always_inline uint16_t
 707 _iavf_recv_raw_pkts_vec_avx512_flex_rxd(struct iavf_rx_queue *rxq,
 708                                         struct rte_mbuf **rx_pkts,
 709                                         uint16_t nb_pkts,
 710                                         uint8_t *split_packet,
 711                                         bool offload)
 712 {
 713         struct iavf_adapter *adapter = rxq->vsi->adapter;
 714
 715         uint64_t offloads = adapter->dev_data->dev_conf.rxmode.offloads;
 716
 717 #ifdef IAVF_RX_PTYPE_OFFLOAD
 718         const uint32_t *type_table = adapter->ptype_tbl;
 719 #endif
 720
 721         const __m256i mbuf_init = _mm256_set_epi64x(0, 0, 0,
 722                                                     rxq->mbuf_initializer);
 723         struct rte_mbuf **sw_ring = &rxq->sw_ring[rxq->rx_tail];
 724         volatile union iavf_rx_flex_desc *rxdp =
 725                 (union iavf_rx_flex_desc *)rxq->rx_ring + rxq->rx_tail;
 726
 727         rte_prefetch0(rxdp);
 728
 729         /* nb_pkts has to be floor-aligned to IAVF_DESCS_PER_LOOP_AVX */
 730         nb_pkts = RTE_ALIGN_FLOOR(nb_pkts, IAVF_DESCS_PER_LOOP_AVX);
 731
 732         /* See if we need to rearm the RX queue - gives the prefetch a bit
 733          * of time to act
 734          */
 735         if (rxq->rxrearm_nb > IAVF_RXQ_REARM_THRESH)
 736                 iavf_rxq_rearm(rxq);
 737
 738         /* Before we start moving massive data around, check to see if
 739          * there is actually a packet available
 740          */
 741         if (!(rxdp->wb.status_error0 &
 742               rte_cpu_to_le_32(1 << IAVF_RX_FLEX_DESC_STATUS0_DD_S)))
 743                 return 0;
 744
 745         /* constants used in processing loop */
 746         const __m512i crc_adjust =
 747                 _mm512_set_epi32
 748                         (/* 1st descriptor */
 749                          0,             /* ignore non-length fields */
 750                          -rxq->crc_len, /* sub crc on data_len */
 751                          -rxq->crc_len, /* sub crc on pkt_len */
 752                          0,             /* ignore pkt_type field */
 753                          /* 2nd descriptor */
 754                          0,             /* ignore non-length fields */
 755                          -rxq->crc_len, /* sub crc on data_len */
 756                          -rxq->crc_len, /* sub crc on pkt_len */
 757                          0,             /* ignore pkt_type field */
 758                          /* 3rd descriptor */
 759                          0,             /* ignore non-length fields */
 760                          -rxq->crc_len, /* sub crc on data_len */
 761                          -rxq->crc_len, /* sub crc on pkt_len */
 762                          0,             /* ignore pkt_type field */
 763                          /* 4th descriptor */
 764                          0,             /* ignore non-length fields */
 765                          -rxq->crc_len, /* sub crc on data_len */
 766                          -rxq->crc_len, /* sub crc on pkt_len */
 767                          0              /* ignore pkt_type field */
 768                         );
 769
 770         /* 8 packets DD mask, LSB in each 32-bit value */
 771         const __m256i dd_check = _mm256_set1_epi32(1);
 772
 773         /* 8 packets EOP mask, second-LSB in each 32-bit value */
 774         const __m256i eop_check = _mm256_slli_epi32(dd_check,
 775                         IAVF_RX_FLEX_DESC_STATUS0_EOF_S);
 776
 777         /* mask to shuffle from desc. to mbuf (4 descriptors)*/
 778         const __m512i shuf_msk =
 779                 _mm512_set_epi32
 780                         (/* 1st descriptor */
 781                          0xFFFFFFFF,    /* rss hash parsed separately */
 782                          0x0B0A0504,    /* octet 10~11, 16 bits vlan_macip */
 783                                         /* octet 4~5, 16 bits data_len */
 784                          0xFFFF0504,    /* skip hi 16 bits pkt_len, zero out */
 785                                         /* octet 4~5, 16 bits pkt_len */
 786                          0xFFFFFFFF,    /* pkt_type set as unknown */
 787                          /* 2nd descriptor */
 788                          0xFFFFFFFF,    /* rss hash parsed separately */
 789                          0x0B0A0504,    /* octet 10~11, 16 bits vlan_macip */
 790                                         /* octet 4~5, 16 bits data_len */
 791                          0xFFFF0504,    /* skip hi 16 bits pkt_len, zero out */
 792                                         /* octet 4~5, 16 bits pkt_len */
 793                          0xFFFFFFFF,    /* pkt_type set as unknown */
 794                          /* 3rd descriptor */
 795                          0xFFFFFFFF,    /* rss hash parsed separately */
 796                          0x0B0A0504,    /* octet 10~11, 16 bits vlan_macip */
 797                                         /* octet 4~5, 16 bits data_len */
 798                          0xFFFF0504,    /* skip hi 16 bits pkt_len, zero out */
 799                                         /* octet 4~5, 16 bits pkt_len */
 800                          0xFFFFFFFF,    /* pkt_type set as unknown */
 801                          /* 4th descriptor */
 802                          0xFFFFFFFF,    /* rss hash parsed separately */
 803                          0x0B0A0504,    /* octet 10~11, 16 bits vlan_macip */
 804                                         /* octet 4~5, 16 bits data_len */
 805                          0xFFFF0504,    /* skip hi 16 bits pkt_len, zero out */
 806                                         /* octet 4~5, 16 bits pkt_len */
 807                          0xFFFFFFFF     /* pkt_type set as unknown */
 808                         );
 809         /**
 810          * compile-time check the above crc and shuffle layout is correct.
 811          * NOTE: the first field (lowest address) is given last in set_epi
 812          * calls above.
 813          */
 814         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, pkt_len) !=
 815                          offsetof(struct rte_mbuf, rx_descriptor_fields1) + 4);
 816         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, data_len) !=
 817                          offsetof(struct rte_mbuf, rx_descriptor_fields1) + 8);
 818         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, vlan_tci) !=
 819                          offsetof(struct rte_mbuf, rx_descriptor_fields1) + 10);
 820         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, hash) !=
 821                          offsetof(struct rte_mbuf, rx_descriptor_fields1) + 12);
 822
 823         uint16_t i, received;
 824
 825         for (i = 0, received = 0; i < nb_pkts;
 826              i += IAVF_DESCS_PER_LOOP_AVX,
 827              rxdp += IAVF_DESCS_PER_LOOP_AVX) {
 828                 /* step 1, copy over 8 mbuf pointers to rx_pkts array */
 829                 _mm256_storeu_si256((void *)&rx_pkts[i],
 830                                     _mm256_loadu_si256((void *)&sw_ring[i]));
 831 #ifdef RTE_ARCH_X86_64
 832                 _mm256_storeu_si256
 833                         ((void *)&rx_pkts[i + 4],
 834                          _mm256_loadu_si256((void *)&sw_ring[i + 4]));
 835 #endif
 836
 837                 __m512i raw_desc0_3, raw_desc4_7;
 838
 839                 const __m128i raw_desc7 =
 840                         _mm_load_si128((void *)(rxdp + 7));
 841                 rte_compiler_barrier();
 842                 const __m128i raw_desc6 =
 843                         _mm_load_si128((void *)(rxdp + 6));
 844                 rte_compiler_barrier();
 845                 const __m128i raw_desc5 =
 846                         _mm_load_si128((void *)(rxdp + 5));
 847                 rte_compiler_barrier();
 848                 const __m128i raw_desc4 =
 849                         _mm_load_si128((void *)(rxdp + 4));
 850                 rte_compiler_barrier();
 851                 const __m128i raw_desc3 =
 852                         _mm_load_si128((void *)(rxdp + 3));
 853                 rte_compiler_barrier();
 854                 const __m128i raw_desc2 =
 855                         _mm_load_si128((void *)(rxdp + 2));
 856                 rte_compiler_barrier();
 857                 const __m128i raw_desc1 =
 858                         _mm_load_si128((void *)(rxdp + 1));
 859                 rte_compiler_barrier();
 860                 const __m128i raw_desc0 =
 861                         _mm_load_si128((void *)(rxdp + 0));
 862
 863                 raw_desc4_7 = _mm512_broadcast_i32x4(raw_desc4);
 864                 raw_desc4_7 = _mm512_inserti32x4(raw_desc4_7, raw_desc5, 1);
 865                 raw_desc4_7 = _mm512_inserti32x4(raw_desc4_7, raw_desc6, 2);
 866                 raw_desc4_7 = _mm512_inserti32x4(raw_desc4_7, raw_desc7, 3);
 867                 raw_desc0_3 = _mm512_broadcast_i32x4(raw_desc0);
 868                 raw_desc0_3 = _mm512_inserti32x4(raw_desc0_3, raw_desc1, 1);
 869                 raw_desc0_3 = _mm512_inserti32x4(raw_desc0_3, raw_desc2, 2);
 870                 raw_desc0_3 = _mm512_inserti32x4(raw_desc0_3, raw_desc3, 3);
 871
 872                 if (split_packet) {
 873                         int j;
 874
 875                         for (j = 0; j < IAVF_DESCS_PER_LOOP_AVX; j++)
 876                                 rte_mbuf_prefetch_part2(rx_pkts[i + j]);
 877                 }
 878
 879                 /**
 880                  * convert descriptors 4-7 into mbufs, re-arrange fields.
 881                  * Then write into the mbuf.
 882                  */
 883                 __m512i mb4_7 = _mm512_shuffle_epi8(raw_desc4_7, shuf_msk);
 884
 885                 mb4_7 = _mm512_add_epi32(mb4_7, crc_adjust);
 886 #ifdef IAVF_RX_PTYPE_OFFLOAD
 887                 /**
 888                  * to get packet types, ptype is located in bit16-25
 889                  * of each 128bits
 890                  */
 891                 const __m512i ptype_mask =
 892                         _mm512_set1_epi16(IAVF_RX_FLEX_DESC_PTYPE_M);
 893                 const __m512i ptypes4_7 =
 894                         _mm512_and_si512(raw_desc4_7, ptype_mask);
 895                 const __m256i ptypes6_7 = _mm512_extracti64x4_epi64(ptypes4_7, 1);
 896                 const __m256i ptypes4_5 = _mm512_extracti64x4_epi64(ptypes4_7, 0);
 897                 const uint16_t ptype7 = _mm256_extract_epi16(ptypes6_7, 9);
 898                 const uint16_t ptype6 = _mm256_extract_epi16(ptypes6_7, 1);
 899                 const uint16_t ptype5 = _mm256_extract_epi16(ptypes4_5, 9);
 900                 const uint16_t ptype4 = _mm256_extract_epi16(ptypes4_5, 1);
 901
 902                 const __m512i ptype4_7 = _mm512_set_epi32
 903                         (0, 0, 0, type_table[ptype7],
 904                          0, 0, 0, type_table[ptype6],
 905                          0, 0, 0, type_table[ptype5],
 906                          0, 0, 0, type_table[ptype4]);
 907                 mb4_7 = _mm512_mask_blend_epi32(0x1111, mb4_7, ptype4_7);
 908 #endif
 909
 910                 /**
 911                  * convert descriptors 0-3 into mbufs, re-arrange fields.
 912                  * Then write into the mbuf.
 913                  */
 914                 __m512i mb0_3 = _mm512_shuffle_epi8(raw_desc0_3, shuf_msk);
 915
 916                 mb0_3 = _mm512_add_epi32(mb0_3, crc_adjust);
 917 #ifdef IAVF_RX_PTYPE_OFFLOAD
 918                 /**
 919                  * to get packet types, ptype is located in bit16-25
 920                  * of each 128bits
 921                  */
 922                 const __m512i ptypes0_3 =
 923                         _mm512_and_si512(raw_desc0_3, ptype_mask);
 924                 const __m256i ptypes2_3 = _mm512_extracti64x4_epi64(ptypes0_3, 1);
 925                 const __m256i ptypes0_1 = _mm512_extracti64x4_epi64(ptypes0_3, 0);
 926                 const uint16_t ptype3 = _mm256_extract_epi16(ptypes2_3, 9);
 927                 const uint16_t ptype2 = _mm256_extract_epi16(ptypes2_3, 1);
 928                 const uint16_t ptype1 = _mm256_extract_epi16(ptypes0_1, 9);
 929                 const uint16_t ptype0 = _mm256_extract_epi16(ptypes0_1, 1);
 930
 931                 const __m512i ptype0_3 = _mm512_set_epi32
 932                         (0, 0, 0, type_table[ptype3],
 933                          0, 0, 0, type_table[ptype2],
 934                          0, 0, 0, type_table[ptype1],
 935                          0, 0, 0, type_table[ptype0]);
 936                 mb0_3 = _mm512_mask_blend_epi32(0x1111, mb0_3, ptype0_3);
 937 #endif
 938
 939                 /**
 940                  * use permute/extract to get status content
 941                  * After the operations, the packets status flags are in the
 942                  * order (hi->lo): [1, 3, 5, 7, 0, 2, 4, 6]
 943                  */
 944                 /* merge the status bits into one register */
 945                 const __m512i status_permute_msk = _mm512_set_epi32
 946                         (0, 0, 0, 0,
 947                          0, 0, 0, 0,
 948                          22, 30, 6, 14,
 949                          18, 26, 2, 10);
 950                 const __m512i raw_status0_7 = _mm512_permutex2var_epi32
 951                         (raw_desc4_7, status_permute_msk, raw_desc0_3);
 952                 __m256i status0_7 = _mm512_extracti64x4_epi64
 953                         (raw_status0_7, 0);
 954
 955                 /* now do flag manipulation */
 956
 957                 /* merge flags */
 958                 __m256i mbuf_flags = _mm256_set1_epi32(0);
 959                 __m256i vlan_flags = _mm256_setzero_si256();
 960
 961                 if (offload) {
 962 #if defined(IAVF_RX_CSUM_OFFLOAD) || defined(IAVF_RX_VLAN_OFFLOAD) || defined(IAVF_RX_RSS_OFFLOAD)
 963                         /* Status/Error flag masks */
 964                         /**
 965                          * mask everything except Checksum Reports, RSS indication
 966                          * and VLAN indication.
 967                          * bit6:4 for IP/L4 checksum errors.
 968                          * bit12 is for RSS indication.
 969                          * bit13 is for VLAN indication.
 970                          */
 971                         const __m256i flags_mask =
 972                                 _mm256_set1_epi32((7 << 4) | (1 << 12) | (1 << 13));
 973 #endif
 974 #ifdef IAVF_RX_CSUM_OFFLOAD
 975                         /**
 976                          * data to be shuffled by the result of the flags mask shifted by 4
 977                          * bits.  This gives use the l3_l4 flags.
 978                          */
 979                         const __m256i l3_l4_flags_shuf = _mm256_set_epi8(0, 0, 0, 0, 0, 0, 0, 0,
 980                                         /* shift right 1 bit to make sure it not exceed 255 */
 981                                         (RTE_MBUF_F_RX_OUTER_IP_CKSUM_BAD | RTE_MBUF_F_RX_L4_CKSUM_BAD |
 982                                          RTE_MBUF_F_RX_IP_CKSUM_BAD) >> 1,
 983                                         (RTE_MBUF_F_RX_OUTER_IP_CKSUM_BAD | RTE_MBUF_F_RX_L4_CKSUM_BAD |
 984                                          RTE_MBUF_F_RX_IP_CKSUM_GOOD) >> 1,
 985                                         (RTE_MBUF_F_RX_OUTER_IP_CKSUM_BAD | RTE_MBUF_F_RX_L4_CKSUM_GOOD |
 986                                          RTE_MBUF_F_RX_IP_CKSUM_BAD) >> 1,
 987                                         (RTE_MBUF_F_RX_OUTER_IP_CKSUM_BAD | RTE_MBUF_F_RX_L4_CKSUM_GOOD |
 988                                          RTE_MBUF_F_RX_IP_CKSUM_GOOD) >> 1,
 989                                         (RTE_MBUF_F_RX_L4_CKSUM_BAD | RTE_MBUF_F_RX_IP_CKSUM_BAD) >> 1,
 990                                         (RTE_MBUF_F_RX_L4_CKSUM_BAD | RTE_MBUF_F_RX_IP_CKSUM_GOOD) >> 1,
 991                                         (RTE_MBUF_F_RX_L4_CKSUM_GOOD | RTE_MBUF_F_RX_IP_CKSUM_BAD) >> 1,
 992                                         (RTE_MBUF_F_RX_L4_CKSUM_GOOD | RTE_MBUF_F_RX_IP_CKSUM_GOOD) >> 1,
 993                                         /* second 128-bits */
 994                                         0, 0, 0, 0, 0, 0, 0, 0,
 995                                         (RTE_MBUF_F_RX_OUTER_IP_CKSUM_BAD | RTE_MBUF_F_RX_L4_CKSUM_BAD |
 996                                          RTE_MBUF_F_RX_IP_CKSUM_BAD) >> 1,
 997                                         (RTE_MBUF_F_RX_OUTER_IP_CKSUM_BAD | RTE_MBUF_F_RX_L4_CKSUM_BAD |
 998                                          RTE_MBUF_F_RX_IP_CKSUM_GOOD) >> 1,
 999                                         (RTE_MBUF_F_RX_OUTER_IP_CKSUM_BAD | RTE_MBUF_F_RX_L4_CKSUM_GOOD |
1000                                          RTE_MBUF_F_RX_IP_CKSUM_BAD) >> 1,
1001                                         (RTE_MBUF_F_RX_OUTER_IP_CKSUM_BAD | RTE_MBUF_F_RX_L4_CKSUM_GOOD |
1002                                          RTE_MBUF_F_RX_IP_CKSUM_GOOD) >> 1,
1003                                         (RTE_MBUF_F_RX_L4_CKSUM_BAD | RTE_MBUF_F_RX_IP_CKSUM_BAD) >> 1,
1004                                         (RTE_MBUF_F_RX_L4_CKSUM_BAD | RTE_MBUF_F_RX_IP_CKSUM_GOOD) >> 1,
1005                                         (RTE_MBUF_F_RX_L4_CKSUM_GOOD | RTE_MBUF_F_RX_IP_CKSUM_BAD) >> 1,
1006                                         (RTE_MBUF_F_RX_L4_CKSUM_GOOD | RTE_MBUF_F_RX_IP_CKSUM_GOOD) >> 1);
1007                         const __m256i cksum_mask =
1008                                 _mm256_set1_epi32(RTE_MBUF_F_RX_IP_CKSUM_GOOD | RTE_MBUF_F_RX_IP_CKSUM_BAD |
1009                                                   RTE_MBUF_F_RX_L4_CKSUM_GOOD | RTE_MBUF_F_RX_L4_CKSUM_BAD |
1010                                                   RTE_MBUF_F_RX_OUTER_IP_CKSUM_BAD);
1011 #endif
1012 #if defined(IAVF_RX_VLAN_OFFLOAD) || defined(IAVF_RX_RSS_OFFLOAD)
1013                         /**
1014                          * data to be shuffled by result of flag mask, shifted down 12.
1015                          * If RSS(bit12)/VLAN(bit13) are set,
1016                          * shuffle moves appropriate flags in place.
1017                          */
1018                         const __m256i rss_flags_shuf = _mm256_set_epi8
1019                                         (0, 0, 0, 0,
1020                                          0, 0, 0, 0,
1021                                          0, 0, 0, 0,
1022                                          RTE_MBUF_F_RX_RSS_HASH, 0,
1023                                          RTE_MBUF_F_RX_RSS_HASH, 0,
1024                                          /* end up 128-bits */
1025                                          0, 0, 0, 0,
1026                                          0, 0, 0, 0,
1027                                          0, 0, 0, 0,
1028                                          RTE_MBUF_F_RX_RSS_HASH, 0,
1029                                          RTE_MBUF_F_RX_RSS_HASH, 0);
1030
1031                         const __m256i vlan_flags_shuf = _mm256_set_epi8
1032                                         (0, 0, 0, 0,
1033                                          0, 0, 0, 0,
1034                                          0, 0, 0, 0,
1035                                          RTE_MBUF_F_RX_VLAN | RTE_MBUF_F_RX_VLAN_STRIPPED,
1036                                          RTE_MBUF_F_RX_VLAN | RTE_MBUF_F_RX_VLAN_STRIPPED,
1037                                          0, 0,
1038                                          /* end up 128-bits */
1039                                          0, 0, 0, 0,
1040                                          0, 0, 0, 0,
1041                                          0, 0, 0, 0,
1042                                          RTE_MBUF_F_RX_VLAN | RTE_MBUF_F_RX_VLAN_STRIPPED,
1043                                          RTE_MBUF_F_RX_VLAN | RTE_MBUF_F_RX_VLAN_STRIPPED,
1044                                          0, 0);
1045 #endif
1046
1047 #if defined(IAVF_RX_CSUM_OFFLOAD) || defined(IAVF_RX_VLAN_OFFLOAD) || defined(IAVF_RX_RSS_OFFLOAD)
1048                         /* get only flag/error bits we want */
1049                         const __m256i flag_bits =
1050                                 _mm256_and_si256(status0_7, flags_mask);
1051 #endif
1052 #ifdef IAVF_RX_CSUM_OFFLOAD
1053                         /**
1054                          * l3_l4_error flags, shuffle, then shift to correct adjustment
1055                          * of flags in flags_shuf, and finally mask out extra bits
1056                          */
1057                         __m256i l3_l4_flags = _mm256_shuffle_epi8(l3_l4_flags_shuf,
1058                                         _mm256_srli_epi32(flag_bits, 4));
1059                         l3_l4_flags = _mm256_slli_epi32(l3_l4_flags, 1);
1060                         l3_l4_flags = _mm256_and_si256(l3_l4_flags, cksum_mask);
1061 #endif
1062 #if defined(IAVF_RX_VLAN_OFFLOAD) || defined(IAVF_RX_RSS_OFFLOAD)
1063                         /* set rss and vlan flags */
1064                         const __m256i rss_vlan_flag_bits =
1065                                 _mm256_srli_epi32(flag_bits, 12);
1066                         const __m256i rss_flags =
1067                                 _mm256_shuffle_epi8(rss_flags_shuf,
1068                                                     rss_vlan_flag_bits);
1069
1070                         if (rxq->rx_flags == IAVF_RX_FLAGS_VLAN_TAG_LOC_L2TAG1)
1071                                 vlan_flags =
1072                                         _mm256_shuffle_epi8(vlan_flags_shuf,
1073                                                             rss_vlan_flag_bits);
1074
1075                         const __m256i rss_vlan_flags =
1076                                 _mm256_or_si256(rss_flags, vlan_flags);
1077
1078 #endif
1079
1080 #ifdef IAVF_RX_CSUM_OFFLOAD
1081                         mbuf_flags = _mm256_or_si256(mbuf_flags, l3_l4_flags);
1082 #endif
1083 #if defined(IAVF_RX_VLAN_OFFLOAD) || defined(IAVF_RX_RSS_OFFLOAD)
1084                         mbuf_flags = _mm256_or_si256(mbuf_flags, rss_vlan_flags);
1085 #endif
1086                 }
1087
1088 #ifdef IAVF_RX_FDIR_OFFLOAD
1089                 if (rxq->fdir_enabled) {
1090                         const __m512i fdir_permute_mask = _mm512_set_epi32
1091                                 (0, 0, 0, 0,
1092                                  0, 0, 0, 0,
1093                                  7, 15, 23, 31,
1094                                  3, 11, 19, 27);
1095                         __m512i fdir_tmp = _mm512_permutex2var_epi32
1096                                 (raw_desc0_3, fdir_permute_mask, raw_desc4_7);
1097                         const __m256i fdir_id0_7 = _mm512_extracti64x4_epi64
1098                                 (fdir_tmp, 0);
1099                         const __m256i fdir_flags =
1100                                 flex_rxd_to_fdir_flags_vec_avx512(fdir_id0_7);
1101
1102                         /* merge with fdir_flags */
1103                         mbuf_flags = _mm256_or_si256(mbuf_flags, fdir_flags);
1104
1105                         /* write to mbuf: have to use scalar store here */
1106                         rx_pkts[i + 0]->hash.fdir.hi =
1107                                 _mm256_extract_epi32(fdir_id0_7, 3);
1108
1109                         rx_pkts[i + 1]->hash.fdir.hi =
1110                                 _mm256_extract_epi32(fdir_id0_7, 7);
1111
1112                         rx_pkts[i + 2]->hash.fdir.hi =
1113                                 _mm256_extract_epi32(fdir_id0_7, 2);
1114
1115                         rx_pkts[i + 3]->hash.fdir.hi =
1116                                 _mm256_extract_epi32(fdir_id0_7, 6);
1117
1118                         rx_pkts[i + 4]->hash.fdir.hi =
1119                                 _mm256_extract_epi32(fdir_id0_7, 1);
1120
1121                         rx_pkts[i + 5]->hash.fdir.hi =
1122                                 _mm256_extract_epi32(fdir_id0_7, 5);
1123
1124                         rx_pkts[i + 6]->hash.fdir.hi =
1125                                 _mm256_extract_epi32(fdir_id0_7, 0);
1126
1127                         rx_pkts[i + 7]->hash.fdir.hi =
1128                                 _mm256_extract_epi32(fdir_id0_7, 4);
1129                 } /* if() on fdir_enabled */
1130 #endif
1131
1132                 __m256i mb4_5 = _mm512_extracti64x4_epi64(mb4_7, 0);
1133                 __m256i mb6_7 = _mm512_extracti64x4_epi64(mb4_7, 1);
1134                 __m256i mb0_1 = _mm512_extracti64x4_epi64(mb0_3, 0);
1135                 __m256i mb2_3 = _mm512_extracti64x4_epi64(mb0_3, 1);
1136
1137 #ifndef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
1138                 if (offload) {
1139 #ifdef IAVF_RX_RSS_OFFLOAD
1140                         /**
1141                          * needs to load 2nd 16B of each desc for RSS hash parsing,
1142                          * will cause performance drop to get into this context.
1143                          */
1144                         if (offloads & RTE_ETH_RX_OFFLOAD_RSS_HASH ||
1145                             rxq->rx_flags & IAVF_RX_FLAGS_VLAN_TAG_LOC_L2TAG2_2) {
1146                                 /* load bottom half of every 32B desc */
1147                                 const __m128i raw_desc_bh7 =
1148                                         _mm_load_si128
1149                                                 ((void *)(&rxdp[7].wb.status_error1));
1150                                 rte_compiler_barrier();
1151                                 const __m128i raw_desc_bh6 =
1152                                         _mm_load_si128
1153                                                 ((void *)(&rxdp[6].wb.status_error1));
1154                                 rte_compiler_barrier();
1155                                 const __m128i raw_desc_bh5 =
1156                                         _mm_load_si128
1157                                                 ((void *)(&rxdp[5].wb.status_error1));
1158                                 rte_compiler_barrier();
1159                                 const __m128i raw_desc_bh4 =
1160                                         _mm_load_si128
1161                                                 ((void *)(&rxdp[4].wb.status_error1));
1162                                 rte_compiler_barrier();
1163                                 const __m128i raw_desc_bh3 =
1164                                         _mm_load_si128
1165                                                 ((void *)(&rxdp[3].wb.status_error1));
1166                                 rte_compiler_barrier();
1167                                 const __m128i raw_desc_bh2 =
1168                                         _mm_load_si128
1169                                                 ((void *)(&rxdp[2].wb.status_error1));
1170                                 rte_compiler_barrier();
1171                                 const __m128i raw_desc_bh1 =
1172                                         _mm_load_si128
1173                                                 ((void *)(&rxdp[1].wb.status_error1));
1174                                 rte_compiler_barrier();
1175                                 const __m128i raw_desc_bh0 =
1176                                         _mm_load_si128
1177                                                 ((void *)(&rxdp[0].wb.status_error1));
1178
1179                                 __m256i raw_desc_bh6_7 =
1180                                         _mm256_inserti128_si256
1181                                                 (_mm256_castsi128_si256(raw_desc_bh6),
1182                                                  raw_desc_bh7, 1);
1183                                 __m256i raw_desc_bh4_5 =
1184                                         _mm256_inserti128_si256
1185                                                 (_mm256_castsi128_si256(raw_desc_bh4),
1186                                                  raw_desc_bh5, 1);
1187                                 __m256i raw_desc_bh2_3 =
1188                                         _mm256_inserti128_si256
1189                                                 (_mm256_castsi128_si256(raw_desc_bh2),
1190                                                  raw_desc_bh3, 1);
1191                                 __m256i raw_desc_bh0_1 =
1192                                         _mm256_inserti128_si256
1193                                                 (_mm256_castsi128_si256(raw_desc_bh0),
1194                                                  raw_desc_bh1, 1);
1195
1196                                 if (offloads & RTE_ETH_RX_OFFLOAD_RSS_HASH) {
1197                                         /**
1198                                          * to shift the 32b RSS hash value to the
1199                                          * highest 32b of each 128b before mask
1200                                          */
1201                                         __m256i rss_hash6_7 =
1202                                                 _mm256_slli_epi64
1203                                                 (raw_desc_bh6_7, 32);
1204                                         __m256i rss_hash4_5 =
1205                                                 _mm256_slli_epi64
1206                                                 (raw_desc_bh4_5, 32);
1207                                         __m256i rss_hash2_3 =
1208                                                 _mm256_slli_epi64
1209                                                 (raw_desc_bh2_3, 32);
1210                                         __m256i rss_hash0_1 =
1211                                                 _mm256_slli_epi64
1212                                                 (raw_desc_bh0_1, 32);
1213
1214                                         const __m256i rss_hash_msk =
1215                                                 _mm256_set_epi32
1216                                                 (0xFFFFFFFF, 0, 0, 0,
1217                                                  0xFFFFFFFF, 0, 0, 0);
1218
1219                                         rss_hash6_7 = _mm256_and_si256
1220                                                 (rss_hash6_7, rss_hash_msk);
1221                                         rss_hash4_5 = _mm256_and_si256
1222                                                 (rss_hash4_5, rss_hash_msk);
1223                                         rss_hash2_3 = _mm256_and_si256
1224                                                 (rss_hash2_3, rss_hash_msk);
1225                                         rss_hash0_1 = _mm256_and_si256
1226                                                 (rss_hash0_1, rss_hash_msk);
1227
1228                                         mb6_7 = _mm256_or_si256
1229                                                 (mb6_7, rss_hash6_7);
1230                                         mb4_5 = _mm256_or_si256
1231                                                 (mb4_5, rss_hash4_5);
1232                                         mb2_3 = _mm256_or_si256
1233                                                 (mb2_3, rss_hash2_3);
1234                                         mb0_1 = _mm256_or_si256
1235                                                 (mb0_1, rss_hash0_1);
1236                                 }
1237
1238                                 if (rxq->rx_flags & IAVF_RX_FLAGS_VLAN_TAG_LOC_L2TAG2_2) {
1239                                         /* merge the status/error-1 bits into one register */
1240                                         const __m256i status1_4_7 =
1241                                                 _mm256_unpacklo_epi32
1242                                                 (raw_desc_bh6_7,
1243                                                  raw_desc_bh4_5);
1244                                         const __m256i status1_0_3 =
1245                                                 _mm256_unpacklo_epi32
1246                                                 (raw_desc_bh2_3,
1247                                                  raw_desc_bh0_1);
1248
1249                                         const __m256i status1_0_7 =
1250                                                 _mm256_unpacklo_epi64
1251                                                 (status1_4_7, status1_0_3);
1252
1253                                         const __m256i l2tag2p_flag_mask =
1254                                                 _mm256_set1_epi32
1255                                                 (1 << IAVF_RX_FLEX_DESC_STATUS1_L2TAG2P_S);
1256
1257                                         __m256i l2tag2p_flag_bits =
1258                                                 _mm256_and_si256
1259                                                 (status1_0_7,
1260                                                  l2tag2p_flag_mask);
1261
1262                                         l2tag2p_flag_bits =
1263                                                 _mm256_srli_epi32
1264                                                 (l2tag2p_flag_bits,
1265                                                  IAVF_RX_FLEX_DESC_STATUS1_L2TAG2P_S);
1266
1267                                         const __m256i l2tag2_flags_shuf =
1268                                                 _mm256_set_epi8
1269                                                         (0, 0, 0, 0,
1270                                                          0, 0, 0, 0,
1271                                                          0, 0, 0, 0,
1272                                                          0, 0, 0, 0,
1273                                                          /* end up 128-bits */
1274                                                          0, 0, 0, 0,
1275                                                          0, 0, 0, 0,
1276                                                          0, 0, 0, 0,
1277                                                          0, 0,
1278                                                          RTE_MBUF_F_RX_VLAN |
1279                                                          RTE_MBUF_F_RX_VLAN_STRIPPED,
1280                                                          0);
1281
1282                                         vlan_flags =
1283                                                 _mm256_shuffle_epi8
1284                                                         (l2tag2_flags_shuf,
1285                                                          l2tag2p_flag_bits);
1286
1287                                         /* merge with vlan_flags */
1288                                         mbuf_flags = _mm256_or_si256
1289                                                         (mbuf_flags,
1290                                                          vlan_flags);
1291
1292                                         /* L2TAG2_2 */
1293                                         __m256i vlan_tci6_7 =
1294                                                 _mm256_slli_si256
1295                                                         (raw_desc_bh6_7, 4);
1296                                         __m256i vlan_tci4_5 =
1297                                                 _mm256_slli_si256
1298                                                         (raw_desc_bh4_5, 4);
1299                                         __m256i vlan_tci2_3 =
1300                                                 _mm256_slli_si256
1301                                                         (raw_desc_bh2_3, 4);
1302                                         __m256i vlan_tci0_1 =
1303                                                 _mm256_slli_si256
1304                                                         (raw_desc_bh0_1, 4);
1305
1306                                         const __m256i vlan_tci_msk =
1307                                                 _mm256_set_epi32
1308                                                 (0, 0xFFFF0000, 0, 0,
1309                                                  0, 0xFFFF0000, 0, 0);
1310
1311                                         vlan_tci6_7 = _mm256_and_si256
1312                                                         (vlan_tci6_7,
1313                                                          vlan_tci_msk);
1314                                         vlan_tci4_5 = _mm256_and_si256
1315                                                         (vlan_tci4_5,
1316                                                          vlan_tci_msk);
1317                                         vlan_tci2_3 = _mm256_and_si256
1318                                                         (vlan_tci2_3,
1319                                                          vlan_tci_msk);
1320                                         vlan_tci0_1 = _mm256_and_si256
1321                                                         (vlan_tci0_1,
1322                                                          vlan_tci_msk);
1323
1324                                         mb6_7 = _mm256_or_si256
1325                                                         (mb6_7, vlan_tci6_7);
1326                                         mb4_5 = _mm256_or_si256
1327                                                         (mb4_5, vlan_tci4_5);
1328                                         mb2_3 = _mm256_or_si256
1329                                                         (mb2_3, vlan_tci2_3);
1330                                         mb0_1 = _mm256_or_si256
1331                                                         (mb0_1, vlan_tci0_1);
1332                                 }
1333                         } /* if() on RSS hash parsing */
1334 #endif
1335                 }
1336 #endif
1337
1338                 /**
1339                  * At this point, we have the 8 sets of flags in the low 16-bits
1340                  * of each 32-bit value in vlan0.
1341                  * We want to extract these, and merge them with the mbuf init
1342                  * data so we can do a single write to the mbuf to set the flags
1343                  * and all the other initialization fields. Extracting the
1344                  * appropriate flags means that we have to do a shift and blend
1345                  * for each mbuf before we do the write. However, we can also
1346                  * add in the previously computed rx_descriptor fields to
1347                  * make a single 256-bit write per mbuf
1348                  */
1349                 /* check the structure matches expectations */
1350                 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, ol_flags) !=
1351                                  offsetof(struct rte_mbuf, rearm_data) + 8);
1352                 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, rearm_data) !=
1353                                  RTE_ALIGN(offsetof(struct rte_mbuf,
1354                                                     rearm_data),
1355                                                     16));
1356                 /* build up data and do writes */
1357                 __m256i rearm0, rearm1, rearm2, rearm3, rearm4, rearm5,
1358                         rearm6, rearm7;
1359                 rearm6 = _mm256_blend_epi32(mbuf_init,
1360                                             _mm256_slli_si256(mbuf_flags, 8),
1361                                             0x04);
1362                 rearm4 = _mm256_blend_epi32(mbuf_init,
1363                                             _mm256_slli_si256(mbuf_flags, 4),
1364                                             0x04);
1365                 rearm2 = _mm256_blend_epi32(mbuf_init, mbuf_flags, 0x04);
1366                 rearm0 = _mm256_blend_epi32(mbuf_init,
1367                                             _mm256_srli_si256(mbuf_flags, 4),
1368                                             0x04);
1369                 /* permute to add in the rx_descriptor e.g. rss fields */
1370                 rearm6 = _mm256_permute2f128_si256(rearm6, mb6_7, 0x20);
1371                 rearm4 = _mm256_permute2f128_si256(rearm4, mb4_5, 0x20);
1372                 rearm2 = _mm256_permute2f128_si256(rearm2, mb2_3, 0x20);
1373                 rearm0 = _mm256_permute2f128_si256(rearm0, mb0_1, 0x20);
1374                 /* write to mbuf */
1375                 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 6]->rearm_data,
1376                                     rearm6);
1377                 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 4]->rearm_data,
1378                                     rearm4);
1379                 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 2]->rearm_data,
1380                                     rearm2);
1381                 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 0]->rearm_data,
1382                                     rearm0);
1383
1384                 /* repeat for the odd mbufs */
1385                 const __m256i odd_flags =
1386                         _mm256_castsi128_si256
1387                                 (_mm256_extracti128_si256(mbuf_flags, 1));
1388                 rearm7 = _mm256_blend_epi32(mbuf_init,
1389                                             _mm256_slli_si256(odd_flags, 8),
1390                                             0x04);
1391                 rearm5 = _mm256_blend_epi32(mbuf_init,
1392                                             _mm256_slli_si256(odd_flags, 4),
1393                                             0x04);
1394                 rearm3 = _mm256_blend_epi32(mbuf_init, odd_flags, 0x04);
1395                 rearm1 = _mm256_blend_epi32(mbuf_init,
1396                                             _mm256_srli_si256(odd_flags, 4),
1397                                             0x04);
1398                 /* since odd mbufs are already in hi 128-bits use blend */
1399                 rearm7 = _mm256_blend_epi32(rearm7, mb6_7, 0xF0);
1400                 rearm5 = _mm256_blend_epi32(rearm5, mb4_5, 0xF0);
1401                 rearm3 = _mm256_blend_epi32(rearm3, mb2_3, 0xF0);
1402                 rearm1 = _mm256_blend_epi32(rearm1, mb0_1, 0xF0);
1403                 /* again write to mbufs */
1404                 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 7]->rearm_data,
1405                                     rearm7);
1406                 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 5]->rearm_data,
1407                                     rearm5);
1408                 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 3]->rearm_data,
1409                                     rearm3);
1410                 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 1]->rearm_data,
1411                                     rearm1);
1412
1413                 /* extract and record EOP bit */
1414                 if (split_packet) {
1415                         const __m128i eop_mask =
1416                                 _mm_set1_epi16(1 <<
1417                                                IAVF_RX_FLEX_DESC_STATUS0_EOF_S);
1418                         const __m256i eop_bits256 = _mm256_and_si256(status0_7,
1419                                                                      eop_check);
1420                         /* pack status bits into a single 128-bit register */
1421                         const __m128i eop_bits =
1422                                 _mm_packus_epi32
1423                                         (_mm256_castsi256_si128(eop_bits256),
1424                                          _mm256_extractf128_si256(eop_bits256,
1425                                                                   1));
1426                         /**
1427                          * flip bits, and mask out the EOP bit, which is now
1428                          * a split-packet bit i.e. !EOP, rather than EOP one.
1429                          */
1430                         __m128i split_bits = _mm_andnot_si128(eop_bits,
1431                                                               eop_mask);
1432                         /**
1433                          * eop bits are out of order, so we need to shuffle them
1434                          * back into order again. In doing so, only use low 8
1435                          * bits, which acts like another pack instruction
1436                          * The original order is (hi->lo): 1,3,5,7,0,2,4,6
1437                          * [Since we use epi8, the 16-bit positions are
1438                          * multiplied by 2 in the eop_shuffle value.]
1439                          */
1440                         __m128i eop_shuffle =
1441                                 _mm_set_epi8(/* zero hi 64b */
1442                                              0xFF, 0xFF, 0xFF, 0xFF,
1443                                              0xFF, 0xFF, 0xFF, 0xFF,
1444                                              /* move values to lo 64b */
1445                                              8, 0, 10, 2,
1446                                              12, 4, 14, 6);
1447                         split_bits = _mm_shuffle_epi8(split_bits, eop_shuffle);
1448                         *(uint64_t *)split_packet =
1449                                 _mm_cvtsi128_si64(split_bits);
1450                         split_packet += IAVF_DESCS_PER_LOOP_AVX;
1451                 }
1452
1453                 /* perform dd_check */
1454                 status0_7 = _mm256_and_si256(status0_7, dd_check);
1455                 status0_7 = _mm256_packs_epi32(status0_7,
1456                                                _mm256_setzero_si256());
1457
1458                 uint64_t burst = __builtin_popcountll
1459                                         (_mm_cvtsi128_si64
1460                                                 (_mm256_extracti128_si256
1461                                                         (status0_7, 1)));
1462                 burst += __builtin_popcountll
1463                                 (_mm_cvtsi128_si64
1464                                         (_mm256_castsi256_si128(status0_7)));
1465                 received += burst;
1466                 if (burst != IAVF_DESCS_PER_LOOP_AVX)
1467                         break;
1468         }
1469
1470         /* update tail pointers */
1471         rxq->rx_tail += received;
1472         rxq->rx_tail &= (rxq->nb_rx_desc - 1);
1473         if ((rxq->rx_tail & 1) == 1 && received > 1) { /* keep aligned */
1474                 rxq->rx_tail--;
1475                 received--;
1476         }
1477         rxq->rxrearm_nb += received;
1478         return received;
1479 }
1480
1481 /**
1482  * Notice:
1483  * - nb_pkts < IAVF_DESCS_PER_LOOP, just return no packet
1484  */
1485 uint16_t
1486 iavf_recv_pkts_vec_avx512(void *rx_queue, struct rte_mbuf **rx_pkts,
1487                           uint16_t nb_pkts)
1488 {
1489         return _iavf_recv_raw_pkts_vec_avx512(rx_queue, rx_pkts, nb_pkts,
1490                                               NULL, false);
1491 }
1492
1493 /**
1494  * Notice:
1495  * - nb_pkts < IAVF_DESCS_PER_LOOP, just return no packet
1496  */
1497 uint16_t
1498 iavf_recv_pkts_vec_avx512_flex_rxd(void *rx_queue, struct rte_mbuf **rx_pkts,
1499                                    uint16_t nb_pkts)
1500 {
1501         return _iavf_recv_raw_pkts_vec_avx512_flex_rxd(rx_queue, rx_pkts,
1502                                                        nb_pkts, NULL, false);
1503 }
1504
1505 /**
1506  * vPMD receive routine that reassembles single burst of 32 scattered packets
1507  * Notice:
1508  * - nb_pkts < IAVF_DESCS_PER_LOOP, just return no packet
1509  */
1510 static __rte_always_inline uint16_t
1511 iavf_recv_scattered_burst_vec_avx512(void *rx_queue, struct rte_mbuf **rx_pkts,
1512                                      uint16_t nb_pkts, bool offload)
1513 {
1514         struct iavf_rx_queue *rxq = rx_queue;
1515         uint8_t split_flags[IAVF_VPMD_RX_MAX_BURST] = {0};
1516
1517         /* get some new buffers */
1518         uint16_t nb_bufs = _iavf_recv_raw_pkts_vec_avx512(rxq, rx_pkts, nb_pkts,
1519                                                           split_flags, offload);
1520         if (nb_bufs == 0)
1521                 return 0;
1522
1523         /* happy day case, full burst + no packets to be joined */
1524         const uint64_t *split_fl64 = (uint64_t *)split_flags;
1525
1526         if (!rxq->pkt_first_seg &&
1527             split_fl64[0] == 0 && split_fl64[1] == 0 &&
1528             split_fl64[2] == 0 && split_fl64[3] == 0)
1529                 return nb_bufs;
1530
1531         /* reassemble any packets that need reassembly*/
1532         unsigned int i = 0;
1533
1534         if (!rxq->pkt_first_seg) {
1535                 /* find the first split flag, and only reassemble then*/
1536                 while (i < nb_bufs && !split_flags[i])
1537                         i++;
1538                 if (i == nb_bufs)
1539                         return nb_bufs;
1540                 rxq->pkt_first_seg = rx_pkts[i];
1541         }
1542         return i + reassemble_packets(rxq, &rx_pkts[i], nb_bufs - i,
1543                                       &split_flags[i]);
1544 }
1545
1546 /**
1547  * vPMD receive routine that reassembles scattered packets.
1548  * Main receive routine that can handle arbitrary burst sizes
1549  * Notice:
1550  * - nb_pkts < IAVF_DESCS_PER_LOOP, just return no packet
1551  */
1552 static __rte_always_inline uint16_t
1553 iavf_recv_scattered_pkts_vec_avx512_cmn(void *rx_queue, struct rte_mbuf **rx_pkts,
1554                                         uint16_t nb_pkts, bool offload)
1555 {
1556         uint16_t retval = 0;
1557
1558         while (nb_pkts > IAVF_VPMD_RX_MAX_BURST) {
1559                 uint16_t burst = iavf_recv_scattered_burst_vec_avx512(rx_queue,
1560                                 rx_pkts + retval, IAVF_VPMD_RX_MAX_BURST, offload);
1561                 retval += burst;
1562                 nb_pkts -= burst;
1563                 if (burst < IAVF_VPMD_RX_MAX_BURST)
1564                         return retval;
1565         }
1566         return retval + iavf_recv_scattered_burst_vec_avx512(rx_queue,
1567                                 rx_pkts + retval, nb_pkts, offload);
1568 }
1569
1570 uint16_t
1571 iavf_recv_scattered_pkts_vec_avx512(void *rx_queue, struct rte_mbuf **rx_pkts,
1572                                     uint16_t nb_pkts)
1573 {
1574         return iavf_recv_scattered_pkts_vec_avx512_cmn(rx_queue, rx_pkts,
1575                                                        nb_pkts, false);
1576 }
1577
1578 /**
1579  * vPMD receive routine that reassembles single burst of
1580  * 32 scattered packets for flex RxD
1581  * Notice:
1582  * - nb_pkts < IAVF_DESCS_PER_LOOP, just return no packet
1583  */
1584 static __rte_always_inline uint16_t
1585 iavf_recv_scattered_burst_vec_avx512_flex_rxd(void *rx_queue,
1586                                               struct rte_mbuf **rx_pkts,
1587                                               uint16_t nb_pkts,
1588                                               bool offload)
1589 {
1590         struct iavf_rx_queue *rxq = rx_queue;
1591         uint8_t split_flags[IAVF_VPMD_RX_MAX_BURST] = {0};
1592
1593         /* get some new buffers */
1594         uint16_t nb_bufs = _iavf_recv_raw_pkts_vec_avx512_flex_rxd(rxq,
1595                                         rx_pkts, nb_pkts, split_flags, offload);
1596         if (nb_bufs == 0)
1597                 return 0;
1598
1599         /* happy day case, full burst + no packets to be joined */
1600         const uint64_t *split_fl64 = (uint64_t *)split_flags;
1601
1602         if (!rxq->pkt_first_seg &&
1603             split_fl64[0] == 0 && split_fl64[1] == 0 &&
1604             split_fl64[2] == 0 && split_fl64[3] == 0)
1605                 return nb_bufs;
1606
1607         /* reassemble any packets that need reassembly*/
1608         unsigned int i = 0;
1609
1610         if (!rxq->pkt_first_seg) {
1611                 /* find the first split flag, and only reassemble then*/
1612                 while (i < nb_bufs && !split_flags[i])
1613                         i++;
1614                 if (i == nb_bufs)
1615                         return nb_bufs;
1616                 rxq->pkt_first_seg = rx_pkts[i];
1617         }
1618         return i + reassemble_packets(rxq, &rx_pkts[i], nb_bufs - i,
1619                                       &split_flags[i]);
1620 }
1621
1622 /**
1623  * vPMD receive routine that reassembles scattered packets for flex RxD.
1624  * Main receive routine that can handle arbitrary burst sizes
1625  * Notice:
1626  * - nb_pkts < IAVF_DESCS_PER_LOOP, just return no packet
1627  */
1628 static __rte_always_inline uint16_t
1629 iavf_recv_scattered_pkts_vec_avx512_flex_rxd_cmn(void *rx_queue,
1630                                                  struct rte_mbuf **rx_pkts,
1631                                                  uint16_t nb_pkts,
1632                                                  bool offload)
1633 {
1634         uint16_t retval = 0;
1635
1636         while (nb_pkts > IAVF_VPMD_RX_MAX_BURST) {
1637                 uint16_t burst =
1638                         iavf_recv_scattered_burst_vec_avx512_flex_rxd
1639                                 (rx_queue, rx_pkts + retval,
1640                                  IAVF_VPMD_RX_MAX_BURST, offload);
1641                 retval += burst;
1642                 nb_pkts -= burst;
1643                 if (burst < IAVF_VPMD_RX_MAX_BURST)
1644                         return retval;
1645         }
1646         return retval + iavf_recv_scattered_burst_vec_avx512_flex_rxd(rx_queue,
1647                                 rx_pkts + retval, nb_pkts, offload);
1648 }
1649
1650 uint16_t
1651 iavf_recv_scattered_pkts_vec_avx512_flex_rxd(void *rx_queue,
1652                                              struct rte_mbuf **rx_pkts,
1653                                              uint16_t nb_pkts)
1654 {
1655         return iavf_recv_scattered_pkts_vec_avx512_flex_rxd_cmn(rx_queue,
1656                                                                 rx_pkts,
1657                                                                 nb_pkts,
1658                                                                 false);
1659 }
1660
1661 uint16_t
1662 iavf_recv_pkts_vec_avx512_offload(void *rx_queue, struct rte_mbuf **rx_pkts,
1663                                   uint16_t nb_pkts)
1664 {
1665         return _iavf_recv_raw_pkts_vec_avx512(rx_queue, rx_pkts,
1666                                               nb_pkts, NULL, true);
1667 }
1668
1669 uint16_t
1670 iavf_recv_scattered_pkts_vec_avx512_offload(void *rx_queue,
1671                                             struct rte_mbuf **rx_pkts,
1672                                             uint16_t nb_pkts)
1673 {
1674         return iavf_recv_scattered_pkts_vec_avx512_cmn(rx_queue, rx_pkts,
1675                                                        nb_pkts, true);
1676 }
1677
1678 uint16_t
1679 iavf_recv_pkts_vec_avx512_flex_rxd_offload(void *rx_queue,
1680                                            struct rte_mbuf **rx_pkts,
1681                                            uint16_t nb_pkts)
1682 {
1683         return _iavf_recv_raw_pkts_vec_avx512_flex_rxd(rx_queue,
1684                                                        rx_pkts,
1685                                                        nb_pkts,
1686                                                        NULL,
1687                                                        true);
1688 }
1689
1690 uint16_t
1691 iavf_recv_scattered_pkts_vec_avx512_flex_rxd_offload(void *rx_queue,
1692                                                      struct rte_mbuf **rx_pkts,
1693                                                      uint16_t nb_pkts)
1694 {
1695         return iavf_recv_scattered_pkts_vec_avx512_flex_rxd_cmn(rx_queue,
1696                                                                 rx_pkts,
1697                                                                 nb_pkts,
1698                                                                 true);
1699 }
1700
1701 static __rte_always_inline int
1702 iavf_tx_free_bufs_avx512(struct iavf_tx_queue *txq)
1703 {
1704         struct iavf_tx_vec_entry *txep;
1705         uint32_t n;
1706         uint32_t i;
1707         int nb_free = 0;
1708         struct rte_mbuf *m, *free[IAVF_VPMD_TX_MAX_FREE_BUF];
1709
1710         /* check DD bits on threshold descriptor */
1711         if ((txq->tx_ring[txq->next_dd].cmd_type_offset_bsz &
1712              rte_cpu_to_le_64(IAVF_TXD_QW1_DTYPE_MASK)) !=
1713             rte_cpu_to_le_64(IAVF_TX_DESC_DTYPE_DESC_DONE))
1714                 return 0;
1715
1716         n = txq->rs_thresh;
1717
1718          /* first buffer to free from S/W ring is at index
1719           * tx_next_dd - (tx_rs_thresh-1)
1720           */
1721         txep = (void *)txq->sw_ring;
1722         txep += txq->next_dd - (n - 1);
1723
1724         if (txq->offloads & RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE && (n & 31) == 0) {
1725                 struct rte_mempool *mp = txep[0].mbuf->pool;
1726                 struct rte_mempool_cache *cache = rte_mempool_default_cache(mp,
1727                                                                 rte_lcore_id());
1728                 void **cache_objs;
1729
1730                 if (!cache || cache->len == 0)
1731                         goto normal;
1732
1733                 cache_objs = &cache->objs[cache->len];
1734
1735                 if (n > RTE_MEMPOOL_CACHE_MAX_SIZE) {
1736                         rte_mempool_ops_enqueue_bulk(mp, (void *)txep, n);
1737                         goto done;
1738                 }
1739
1740                 /* The cache follows the following algorithm
1741                  *   1. Add the objects to the cache
1742                  *   2. Anything greater than the cache min value (if it crosses the
1743                  *   cache flush threshold) is flushed to the ring.
1744                  */
1745                 /* Add elements back into the cache */
1746                 uint32_t copied = 0;
1747                 /* n is multiple of 32 */
1748                 while (copied < n) {
1749                         const __m512i a = _mm512_loadu_si512(&txep[copied]);
1750                         const __m512i b = _mm512_loadu_si512(&txep[copied + 8]);
1751                         const __m512i c = _mm512_loadu_si512(&txep[copied + 16]);
1752                         const __m512i d = _mm512_loadu_si512(&txep[copied + 24]);
1753
1754                         _mm512_storeu_si512(&cache_objs[copied], a);
1755                         _mm512_storeu_si512(&cache_objs[copied + 8], b);
1756                         _mm512_storeu_si512(&cache_objs[copied + 16], c);
1757                         _mm512_storeu_si512(&cache_objs[copied + 24], d);
1758                         copied += 32;
1759                 }
1760                 cache->len += n;
1761
1762                 if (cache->len >= cache->flushthresh) {
1763                         rte_mempool_ops_enqueue_bulk(mp,
1764                                                      &cache->objs[cache->size],
1765                                                      cache->len - cache->size);
1766                         cache->len = cache->size;
1767                 }
1768                 goto done;
1769         }
1770
1771 normal:
1772         m = rte_pktmbuf_prefree_seg(txep[0].mbuf);
1773         if (likely(m)) {
1774                 free[0] = m;
1775                 nb_free = 1;
1776                 for (i = 1; i < n; i++) {
1777                         m = rte_pktmbuf_prefree_seg(txep[i].mbuf);
1778                         if (likely(m)) {
1779                                 if (likely(m->pool == free[0]->pool)) {
1780                                         free[nb_free++] = m;
1781                                 } else {
1782                                         rte_mempool_put_bulk(free[0]->pool,
1783                                                              (void *)free,
1784                                                              nb_free);
1785                                         free[0] = m;
1786                                         nb_free = 1;
1787                                 }
1788                         }
1789                 }
1790                 rte_mempool_put_bulk(free[0]->pool, (void **)free, nb_free);
1791         } else {
1792                 for (i = 1; i < n; i++) {
1793                         m = rte_pktmbuf_prefree_seg(txep[i].mbuf);
1794                         if (m)
1795                                 rte_mempool_put(m->pool, m);
1796                 }
1797         }
1798
1799 done:
1800         /* buffers were freed, update counters */
1801         txq->nb_free = (uint16_t)(txq->nb_free + txq->rs_thresh);
1802         txq->next_dd = (uint16_t)(txq->next_dd + txq->rs_thresh);
1803         if (txq->next_dd >= txq->nb_tx_desc)
1804                 txq->next_dd = (uint16_t)(txq->rs_thresh - 1);
1805
1806         return txq->rs_thresh;
1807 }
1808
1809 static __rte_always_inline void
1810 tx_backlog_entry_avx512(struct iavf_tx_vec_entry *txep,
1811                         struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
1812 {
1813         int i;
1814
1815         for (i = 0; i < (int)nb_pkts; ++i)
1816                 txep[i].mbuf = tx_pkts[i];
1817 }
1818
1819 static __rte_always_inline void
1820 iavf_vtx1(volatile struct iavf_tx_desc *txdp,
1821           struct rte_mbuf *pkt, uint64_t flags, bool offload)
1822 {
1823         uint64_t high_qw =
1824                 (IAVF_TX_DESC_DTYPE_DATA |
1825                  ((uint64_t)flags  << IAVF_TXD_QW1_CMD_SHIFT) |
1826                  ((uint64_t)pkt->data_len << IAVF_TXD_QW1_TX_BUF_SZ_SHIFT));
1827         if (offload)
1828                 iavf_txd_enable_offload(pkt, &high_qw);
1829
1830         __m128i descriptor = _mm_set_epi64x(high_qw,
1831                                             pkt->buf_iova + pkt->data_off);
1832         _mm_storeu_si128((__m128i *)txdp, descriptor);
1833 }
1834
1835 #define IAVF_TX_LEN_MASK 0xAA
1836 #define IAVF_TX_OFF_MASK 0x55
1837 static __rte_always_inline void
1838 iavf_vtx(volatile struct iavf_tx_desc *txdp,
1839          struct rte_mbuf **pkt, uint16_t nb_pkts,  uint64_t flags,
1840          bool offload)
1841 {
1842         const uint64_t hi_qw_tmpl = (IAVF_TX_DESC_DTYPE_DATA |
1843                         ((uint64_t)flags  << IAVF_TXD_QW1_CMD_SHIFT));
1844
1845         /* if unaligned on 32-bit boundary, do one to align */
1846         if (((uintptr_t)txdp & 0x1F) != 0 && nb_pkts != 0) {
1847                 iavf_vtx1(txdp, *pkt, flags, offload);
1848                 nb_pkts--, txdp++, pkt++;
1849         }
1850
1851         /* do 4 at a time while possible, in bursts */
1852         for (; nb_pkts > 3; txdp += 4, pkt += 4, nb_pkts -= 4) {
1853                 uint64_t hi_qw3 =
1854                         hi_qw_tmpl |
1855                         ((uint64_t)pkt[3]->data_len <<
1856                          IAVF_TXD_QW1_TX_BUF_SZ_SHIFT);
1857                 if (offload)
1858                         iavf_txd_enable_offload(pkt[3], &hi_qw3);
1859                 uint64_t hi_qw2 =
1860                         hi_qw_tmpl |
1861                         ((uint64_t)pkt[2]->data_len <<
1862                          IAVF_TXD_QW1_TX_BUF_SZ_SHIFT);
1863                 if (offload)
1864                         iavf_txd_enable_offload(pkt[2], &hi_qw2);
1865                 uint64_t hi_qw1 =
1866                         hi_qw_tmpl |
1867                         ((uint64_t)pkt[1]->data_len <<
1868                          IAVF_TXD_QW1_TX_BUF_SZ_SHIFT);
1869                 if (offload)
1870                         iavf_txd_enable_offload(pkt[1], &hi_qw1);
1871                 uint64_t hi_qw0 =
1872                         hi_qw_tmpl |
1873                         ((uint64_t)pkt[0]->data_len <<
1874                          IAVF_TXD_QW1_TX_BUF_SZ_SHIFT);
1875                 if (offload)
1876                         iavf_txd_enable_offload(pkt[0], &hi_qw0);
1877
1878                 __m512i desc0_3 =
1879                         _mm512_set_epi64
1880                                 (hi_qw3,
1881                                  pkt[3]->buf_iova + pkt[3]->data_off,
1882                                  hi_qw2,
1883                                  pkt[2]->buf_iova + pkt[2]->data_off,
1884                                  hi_qw1,
1885                                  pkt[1]->buf_iova + pkt[1]->data_off,
1886                                  hi_qw0,
1887                                  pkt[0]->buf_iova + pkt[0]->data_off);
1888                 _mm512_storeu_si512((void *)txdp, desc0_3);
1889         }
1890
1891         /* do any last ones */
1892         while (nb_pkts) {
1893                 iavf_vtx1(txdp, *pkt, flags, offload);
1894                 txdp++, pkt++, nb_pkts--;
1895         }
1896 }
1897
1898 static __rte_always_inline uint16_t
1899 iavf_xmit_fixed_burst_vec_avx512(void *tx_queue, struct rte_mbuf **tx_pkts,
1900                                  uint16_t nb_pkts, bool offload)
1901 {
1902         struct iavf_tx_queue *txq = (struct iavf_tx_queue *)tx_queue;
1903         volatile struct iavf_tx_desc *txdp;
1904         struct iavf_tx_vec_entry *txep;
1905         uint16_t n, nb_commit, tx_id;
1906         /* bit2 is reserved and must be set to 1 according to Spec */
1907         uint64_t flags = IAVF_TX_DESC_CMD_EOP | IAVF_TX_DESC_CMD_ICRC;
1908         uint64_t rs = IAVF_TX_DESC_CMD_RS | flags;
1909
1910         /* cross rx_thresh boundary is not allowed */
1911         nb_pkts = RTE_MIN(nb_pkts, txq->rs_thresh);
1912
1913         if (txq->nb_free < txq->free_thresh)
1914                 iavf_tx_free_bufs_avx512(txq);
1915
1916         nb_commit = nb_pkts = (uint16_t)RTE_MIN(txq->nb_free, nb_pkts);
1917         if (unlikely(nb_pkts == 0))
1918                 return 0;
1919
1920         tx_id = txq->tx_tail;
1921         txdp = &txq->tx_ring[tx_id];
1922         txep = (void *)txq->sw_ring;
1923         txep += tx_id;
1924
1925         txq->nb_free = (uint16_t)(txq->nb_free - nb_pkts);
1926
1927         n = (uint16_t)(txq->nb_tx_desc - tx_id);
1928         if (nb_commit >= n) {
1929                 tx_backlog_entry_avx512(txep, tx_pkts, n);
1930
1931                 iavf_vtx(txdp, tx_pkts, n - 1, flags, offload);
1932                 tx_pkts += (n - 1);
1933                 txdp += (n - 1);
1934
1935                 iavf_vtx1(txdp, *tx_pkts++, rs, offload);
1936
1937                 nb_commit = (uint16_t)(nb_commit - n);
1938
1939                 tx_id = 0;
1940                 txq->next_rs = (uint16_t)(txq->rs_thresh - 1);
1941
1942                 /* avoid reach the end of ring */
1943                 txdp = &txq->tx_ring[tx_id];
1944                 txep = (void *)txq->sw_ring;
1945                 txep += tx_id;
1946         }
1947
1948         tx_backlog_entry_avx512(txep, tx_pkts, nb_commit);
1949
1950         iavf_vtx(txdp, tx_pkts, nb_commit, flags, offload);
1951
1952         tx_id = (uint16_t)(tx_id + nb_commit);
1953         if (tx_id > txq->next_rs) {
1954                 txq->tx_ring[txq->next_rs].cmd_type_offset_bsz |=
1955                         rte_cpu_to_le_64(((uint64_t)IAVF_TX_DESC_CMD_RS) <<
1956                                          IAVF_TXD_QW1_CMD_SHIFT);
1957                 txq->next_rs =
1958                         (uint16_t)(txq->next_rs + txq->rs_thresh);
1959         }
1960
1961         txq->tx_tail = tx_id;
1962
1963         IAVF_PCI_REG_WC_WRITE(txq->qtx_tail, txq->tx_tail);
1964
1965         return nb_pkts;
1966 }
1967
1968 static __rte_always_inline uint16_t
1969 iavf_xmit_pkts_vec_avx512_cmn(void *tx_queue, struct rte_mbuf **tx_pkts,
1970                               uint16_t nb_pkts, bool offload)
1971 {
1972         uint16_t nb_tx = 0;
1973         struct iavf_tx_queue *txq = (struct iavf_tx_queue *)tx_queue;
1974
1975         while (nb_pkts) {
1976                 uint16_t ret, num;
1977
1978                 num = (uint16_t)RTE_MIN(nb_pkts, txq->rs_thresh);
1979                 ret = iavf_xmit_fixed_burst_vec_avx512(tx_queue, &tx_pkts[nb_tx],
1980                                                        num, offload);
1981                 nb_tx += ret;
1982                 nb_pkts -= ret;
1983                 if (ret < num)
1984                         break;
1985         }
1986
1987         return nb_tx;
1988 }
1989
1990 uint16_t
1991 iavf_xmit_pkts_vec_avx512(void *tx_queue, struct rte_mbuf **tx_pkts,
1992                           uint16_t nb_pkts)
1993 {
1994         return iavf_xmit_pkts_vec_avx512_cmn(tx_queue, tx_pkts, nb_pkts, false);
1995 }
1996
1997 static inline void
1998 iavf_tx_queue_release_mbufs_avx512(struct iavf_tx_queue *txq)
1999 {
2000         unsigned int i;
2001         const uint16_t max_desc = (uint16_t)(txq->nb_tx_desc - 1);
2002         struct iavf_tx_vec_entry *swr = (void *)txq->sw_ring;
2003
2004         if (!txq->sw_ring || txq->nb_free == max_desc)
2005                 return;
2006
2007         i = txq->next_dd - txq->rs_thresh + 1;
2008         if (txq->tx_tail < i) {
2009                 for (; i < txq->nb_tx_desc; i++) {
2010                         rte_pktmbuf_free_seg(swr[i].mbuf);
2011                         swr[i].mbuf = NULL;
2012                 }
2013                 i = 0;
2014         }
2015 }
2016
2017 static const struct iavf_txq_ops avx512_vec_txq_ops = {
2018         .release_mbufs = iavf_tx_queue_release_mbufs_avx512,
2019 };
2020
2021 int __rte_cold
2022 iavf_txq_vec_setup_avx512(struct iavf_tx_queue *txq)
2023 {
2024         txq->ops = &avx512_vec_txq_ops;
2025         return 0;
2026 }
2027
2028 uint16_t
2029 iavf_xmit_pkts_vec_avx512_offload(void *tx_queue, struct rte_mbuf **tx_pkts,
2030                                   uint16_t nb_pkts)
2031 {
2032         return iavf_xmit_pkts_vec_avx512_cmn(tx_queue, tx_pkts, nb_pkts, true);
2033 }