drivers/net/iavf/iavf_rxtx_vec_avx512.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2020 Intel Corporation
   3  */
   4
   5 #include "iavf_rxtx_vec_common.h"
   6
   7 #include <x86intrin.h>
   8
   9 #ifndef __INTEL_COMPILER
  10 #pragma GCC diagnostic ignored "-Wcast-qual"
  11 #endif
  12
  13 #define IAVF_DESCS_PER_LOOP_AVX 8
  14 #define PKTLEN_SHIFT 10
  15
  16 /******************************************************************************
  17  * If user knows a specific offload is not enabled by APP,
  18  * the macro can be commented to save the effort of fast path.
  19  * Currently below 2 features are supported in RX path,
  20  * 1, checksum offload
  21  * 2, VLAN/QINQ stripping
  22  * 3, RSS hash
  23  * 4, packet type analysis
  24  * 5, flow director ID report
  25  ******************************************************************************/
  26 #define IAVF_RX_CSUM_OFFLOAD
  27 #define IAVF_RX_VLAN_OFFLOAD
  28 #define IAVF_RX_RSS_OFFLOAD
  29 #define IAVF_RX_PTYPE_OFFLOAD
  30 #define IAVF_RX_FDIR_OFFLOAD
  31
  32 static __rte_always_inline void
  33 iavf_rxq_rearm(struct iavf_rx_queue *rxq)
  34 {
  35         int i;
  36         uint16_t rx_id;
  37         volatile union iavf_rx_desc *rxdp;
  38         struct rte_mempool_cache *cache =
  39                 rte_mempool_default_cache(rxq->mp, rte_lcore_id());
  40         struct rte_mbuf **rxp = &rxq->sw_ring[rxq->rxrearm_start];
  41
  42         rxdp = rxq->rx_ring + rxq->rxrearm_start;
  43
  44         if (unlikely(!cache))
  45                 return iavf_rxq_rearm_common(rxq, true);
  46
  47         /* We need to pull 'n' more MBUFs into the software ring from mempool
  48          * We inline the mempool function here, so we can vectorize the copy
  49          * from the cache into the shadow ring.
  50          */
  51
  52         /* Can this be satisfied from the cache? */
  53         if (cache->len < IAVF_RXQ_REARM_THRESH) {
  54                 /* No. Backfill the cache first, and then fill from it */
  55                 uint32_t req = IAVF_RXQ_REARM_THRESH + (cache->size -
  56                                                         cache->len);
  57
  58                 /* How many do we require i.e. number to fill the cache + the request */
  59                 int ret = rte_mempool_ops_dequeue_bulk
  60                                 (rxq->mp, &cache->objs[cache->len], req);
  61                 if (ret == 0) {
  62                         cache->len += req;
  63                 } else {
  64                         if (rxq->rxrearm_nb + IAVF_RXQ_REARM_THRESH >=
  65                             rxq->nb_rx_desc) {
  66                                 __m128i dma_addr0;
  67
  68                                 dma_addr0 = _mm_setzero_si128();
  69                                 for (i = 0; i < IAVF_VPMD_DESCS_PER_LOOP; i++) {
  70                                         rxp[i] = &rxq->fake_mbuf;
  71                                         _mm_storeu_si128((__m128i *)&rxdp[i].read,
  72                                                          dma_addr0);
  73                                 }
  74                         }
  75                         rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed +=
  76                                         IAVF_RXQ_REARM_THRESH;
  77                         return;
  78                 }
  79         }
  80
  81         const __m512i iova_offsets =  _mm512_set1_epi64(offsetof
  82                                                         (struct rte_mbuf, buf_iova));
  83         const __m512i headroom = _mm512_set1_epi64(RTE_PKTMBUF_HEADROOM);
  84
  85 #ifndef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
  86         /* to shuffle the addresses to correct slots. Values 4-7 will contain
  87          * zeros, so use 7 for a zero-value.
  88          */
  89         const __m512i permute_idx = _mm512_set_epi64(7, 7, 3, 1, 7, 7, 2, 0);
  90 #else
  91         const __m512i permute_idx = _mm512_set_epi64(7, 3, 6, 2, 5, 1, 4, 0);
  92 #endif
  93
  94         /* Initialize the mbufs in vector, process 8 mbufs in one loop, taking
  95          * from mempool cache and populating both shadow and HW rings
  96          */
  97         for (i = 0; i < IAVF_RXQ_REARM_THRESH / IAVF_DESCS_PER_LOOP_AVX; i++) {
  98                 const __m512i mbuf_ptrs = _mm512_loadu_si512
  99                         (&cache->objs[cache->len - IAVF_DESCS_PER_LOOP_AVX]);
 100                 _mm512_storeu_si512(rxp, mbuf_ptrs);
 101
 102                 const __m512i iova_base_addrs = _mm512_i64gather_epi64
 103                                 (_mm512_add_epi64(mbuf_ptrs, iova_offsets),
 104                                  0, /* base */
 105                                  1  /* scale */);
 106                 const __m512i iova_addrs = _mm512_add_epi64(iova_base_addrs,
 107                                 headroom);
 108 #ifndef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
 109                 const __m512i iovas0 = _mm512_castsi256_si512
 110                                 (_mm512_extracti64x4_epi64(iova_addrs, 0));
 111                 const __m512i iovas1 = _mm512_castsi256_si512
 112                                 (_mm512_extracti64x4_epi64(iova_addrs, 1));
 113
 114                 /* permute leaves desc 2-3 addresses in header address slots 0-1
 115                  * but these are ignored by driver since header split not
 116                  * enabled. Similarly for desc 6 & 7.
 117                  */
 118                 const __m512i desc0_1 = _mm512_permutexvar_epi64
 119                                 (permute_idx,
 120                                  iovas0);
 121                 const __m512i desc2_3 = _mm512_bsrli_epi128(desc0_1, 8);
 122
 123                 const __m512i desc4_5 = _mm512_permutexvar_epi64
 124                                 (permute_idx,
 125                                  iovas1);
 126                 const __m512i desc6_7 = _mm512_bsrli_epi128(desc4_5, 8);
 127
 128                 _mm512_storeu_si512((void *)rxdp, desc0_1);
 129                 _mm512_storeu_si512((void *)(rxdp + 2), desc2_3);
 130                 _mm512_storeu_si512((void *)(rxdp + 4), desc4_5);
 131                 _mm512_storeu_si512((void *)(rxdp + 6), desc6_7);
 132 #else
 133                 /* permute leaves desc 4-7 addresses in header address slots 0-3
 134                  * but these are ignored by driver since header split not
 135                  * enabled.
 136                  */
 137                 const __m512i desc0_3 = _mm512_permutexvar_epi64(permute_idx,
 138                                                                  iova_addrs);
 139                 const __m512i desc4_7 = _mm512_bsrli_epi128(desc0_3, 8);
 140
 141                 _mm512_storeu_si512((void *)rxdp, desc0_3);
 142                 _mm512_storeu_si512((void *)(rxdp + 4), desc4_7);
 143 #endif
 144                 rxp += IAVF_DESCS_PER_LOOP_AVX;
 145                 rxdp += IAVF_DESCS_PER_LOOP_AVX;
 146                 cache->len -= IAVF_DESCS_PER_LOOP_AVX;
 147         }
 148
 149         rxq->rxrearm_start += IAVF_RXQ_REARM_THRESH;
 150         if (rxq->rxrearm_start >= rxq->nb_rx_desc)
 151                 rxq->rxrearm_start = 0;
 152
 153         rxq->rxrearm_nb -= IAVF_RXQ_REARM_THRESH;
 154
 155         rx_id = (uint16_t)((rxq->rxrearm_start == 0) ?
 156                            (rxq->nb_rx_desc - 1) : (rxq->rxrearm_start - 1));
 157
 158         /* Update the tail pointer on the NIC */
 159         IAVF_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
 160 }
 161
 162 #define IAVF_RX_LEN_MASK 0x80808080
 163 static __rte_always_inline uint16_t
 164 _iavf_recv_raw_pkts_vec_avx512(struct iavf_rx_queue *rxq,
 165                                struct rte_mbuf **rx_pkts,
 166                                uint16_t nb_pkts, uint8_t *split_packet,
 167                                bool offload)
 168 {
 169 #ifdef IAVF_RX_PTYPE_OFFLOAD
 170         const uint32_t *type_table = rxq->vsi->adapter->ptype_tbl;
 171 #endif
 172
 173         const __m256i mbuf_init = _mm256_set_epi64x(0, 0, 0,
 174                                                     rxq->mbuf_initializer);
 175         struct rte_mbuf **sw_ring = &rxq->sw_ring[rxq->rx_tail];
 176         volatile union iavf_rx_desc *rxdp = rxq->rx_ring + rxq->rx_tail;
 177
 178         rte_prefetch0(rxdp);
 179
 180         /* nb_pkts has to be floor-aligned to IAVF_DESCS_PER_LOOP_AVX */
 181         nb_pkts = RTE_ALIGN_FLOOR(nb_pkts, IAVF_DESCS_PER_LOOP_AVX);
 182
 183         /* See if we need to rearm the RX queue - gives the prefetch a bit
 184          * of time to act
 185          */
 186         if (rxq->rxrearm_nb > IAVF_RXQ_REARM_THRESH)
 187                 iavf_rxq_rearm(rxq);
 188
 189         /* Before we start moving massive data around, check to see if
 190          * there is actually a packet available
 191          */
 192         if (!(rxdp->wb.qword1.status_error_len &
 193               rte_cpu_to_le_32(1 << IAVF_RX_DESC_STATUS_DD_SHIFT)))
 194                 return 0;
 195
 196         /* constants used in processing loop */
 197         const __m512i crc_adjust =
 198                 _mm512_set_epi32
 199                         (/* 1st descriptor */
 200                          0,             /* ignore non-length fields */
 201                          -rxq->crc_len, /* sub crc on data_len */
 202                          -rxq->crc_len, /* sub crc on pkt_len */
 203                          0,             /* ignore pkt_type field */
 204                          /* 2nd descriptor */
 205                          0,             /* ignore non-length fields */
 206                          -rxq->crc_len, /* sub crc on data_len */
 207                          -rxq->crc_len, /* sub crc on pkt_len */
 208                          0,             /* ignore pkt_type field */
 209                          /* 3rd descriptor */
 210                          0,             /* ignore non-length fields */
 211                          -rxq->crc_len, /* sub crc on data_len */
 212                          -rxq->crc_len, /* sub crc on pkt_len */
 213                          0,             /* ignore pkt_type field */
 214                          /* 4th descriptor */
 215                          0,             /* ignore non-length fields */
 216                          -rxq->crc_len, /* sub crc on data_len */
 217                          -rxq->crc_len, /* sub crc on pkt_len */
 218                          0              /* ignore pkt_type field */
 219                         );
 220
 221         /* 8 packets DD mask, LSB in each 32-bit value */
 222         const __m256i dd_check = _mm256_set1_epi32(1);
 223
 224         /* 8 packets EOP mask, second-LSB in each 32-bit value */
 225         const __m256i eop_check = _mm256_slli_epi32(dd_check,
 226                         IAVF_RX_DESC_STATUS_EOF_SHIFT);
 227
 228         /* mask to shuffle from desc. to mbuf (4 descriptors)*/
 229         const __m512i shuf_msk =
 230                 _mm512_set_epi32
 231                         (/* 1st descriptor */
 232                          0x07060504,    /* octet 4~7, 32bits rss */
 233                          0x03020F0E,    /* octet 2~3, low 16 bits vlan_macip */
 234                                         /* octet 15~14, 16 bits data_len */
 235                          0xFFFF0F0E,    /* skip high 16 bits pkt_len, zero out */
 236                                         /* octet 15~14, low 16 bits pkt_len */
 237                          0xFFFFFFFF,    /* pkt_type set as unknown */
 238                          /* 2nd descriptor */
 239                          0x07060504,    /* octet 4~7, 32bits rss */
 240                          0x03020F0E,    /* octet 2~3, low 16 bits vlan_macip */
 241                                         /* octet 15~14, 16 bits data_len */
 242                          0xFFFF0F0E,    /* skip high 16 bits pkt_len, zero out */
 243                                         /* octet 15~14, low 16 bits pkt_len */
 244                          0xFFFFFFFF,    /* pkt_type set as unknown */
 245                          /* 3rd descriptor */
 246                          0x07060504,    /* octet 4~7, 32bits rss */
 247                          0x03020F0E,    /* octet 2~3, low 16 bits vlan_macip */
 248                                         /* octet 15~14, 16 bits data_len */
 249                          0xFFFF0F0E,    /* skip high 16 bits pkt_len, zero out */
 250                                         /* octet 15~14, low 16 bits pkt_len */
 251                          0xFFFFFFFF,    /* pkt_type set as unknown */
 252                          /* 4th descriptor */
 253                          0x07060504,    /* octet 4~7, 32bits rss */
 254                          0x03020F0E,    /* octet 2~3, low 16 bits vlan_macip */
 255                                         /* octet 15~14, 16 bits data_len */
 256                          0xFFFF0F0E,    /* skip high 16 bits pkt_len, zero out */
 257                                         /* octet 15~14, low 16 bits pkt_len */
 258                          0xFFFFFFFF     /* pkt_type set as unknown */
 259                         );
 260         /**
 261          * compile-time check the above crc and shuffle layout is correct.
 262          * NOTE: the first field (lowest address) is given last in set_epi
 263          * calls above.
 264          */
 265         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, pkt_len) !=
 266                          offsetof(struct rte_mbuf, rx_descriptor_fields1) + 4);
 267         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, data_len) !=
 268                          offsetof(struct rte_mbuf, rx_descriptor_fields1) + 8);
 269         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, vlan_tci) !=
 270                          offsetof(struct rte_mbuf, rx_descriptor_fields1) + 10);
 271         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, hash) !=
 272                          offsetof(struct rte_mbuf, rx_descriptor_fields1) + 12);
 273
 274         uint16_t i, received;
 275
 276         for (i = 0, received = 0; i < nb_pkts;
 277              i += IAVF_DESCS_PER_LOOP_AVX,
 278              rxdp += IAVF_DESCS_PER_LOOP_AVX) {
 279                 /* step 1, copy over 8 mbuf pointers to rx_pkts array */
 280                 _mm256_storeu_si256((void *)&rx_pkts[i],
 281                                     _mm256_loadu_si256((void *)&sw_ring[i]));
 282 #ifdef RTE_ARCH_X86_64
 283                 _mm256_storeu_si256
 284                         ((void *)&rx_pkts[i + 4],
 285                          _mm256_loadu_si256((void *)&sw_ring[i + 4]));
 286 #endif
 287
 288                 __m512i raw_desc0_3, raw_desc4_7;
 289                 const __m128i raw_desc7 =
 290                         _mm_load_si128((void *)(rxdp + 7));
 291                 rte_compiler_barrier();
 292                 const __m128i raw_desc6 =
 293                         _mm_load_si128((void *)(rxdp + 6));
 294                 rte_compiler_barrier();
 295                 const __m128i raw_desc5 =
 296                         _mm_load_si128((void *)(rxdp + 5));
 297                 rte_compiler_barrier();
 298                 const __m128i raw_desc4 =
 299                         _mm_load_si128((void *)(rxdp + 4));
 300                 rte_compiler_barrier();
 301                 const __m128i raw_desc3 =
 302                         _mm_load_si128((void *)(rxdp + 3));
 303                 rte_compiler_barrier();
 304                 const __m128i raw_desc2 =
 305                         _mm_load_si128((void *)(rxdp + 2));
 306                 rte_compiler_barrier();
 307                 const __m128i raw_desc1 =
 308                         _mm_load_si128((void *)(rxdp + 1));
 309                 rte_compiler_barrier();
 310                 const __m128i raw_desc0 =
 311                         _mm_load_si128((void *)(rxdp + 0));
 312
 313                 raw_desc4_7 = _mm512_broadcast_i32x4(raw_desc4);
 314                 raw_desc4_7 = _mm512_inserti32x4(raw_desc4_7, raw_desc5, 1);
 315                 raw_desc4_7 = _mm512_inserti32x4(raw_desc4_7, raw_desc6, 2);
 316                 raw_desc4_7 = _mm512_inserti32x4(raw_desc4_7, raw_desc7, 3);
 317                 raw_desc0_3 = _mm512_broadcast_i32x4(raw_desc0);
 318                 raw_desc0_3 = _mm512_inserti32x4(raw_desc0_3, raw_desc1, 1);
 319                 raw_desc0_3 = _mm512_inserti32x4(raw_desc0_3, raw_desc2, 2);
 320                 raw_desc0_3 = _mm512_inserti32x4(raw_desc0_3, raw_desc3, 3);
 321
 322                 if (split_packet) {
 323                         int j;
 324
 325                         for (j = 0; j < IAVF_DESCS_PER_LOOP_AVX; j++)
 326                                 rte_mbuf_prefetch_part2(rx_pkts[i + j]);
 327                 }
 328
 329                 /**
 330                  * convert descriptors 4-7 into mbufs, adjusting length and
 331                  * re-arranging fields. Then write into the mbuf
 332                  */
 333                 const __m512i len4_7 = _mm512_slli_epi32(raw_desc4_7,
 334                                                          PKTLEN_SHIFT);
 335                 const __m512i desc4_7 = _mm512_mask_blend_epi16(IAVF_RX_LEN_MASK,
 336                                                                 raw_desc4_7,
 337                                                                 len4_7);
 338                 __m512i mb4_7 = _mm512_shuffle_epi8(desc4_7, shuf_msk);
 339
 340                 mb4_7 = _mm512_add_epi32(mb4_7, crc_adjust);
 341 #ifdef IAVF_RX_PTYPE_OFFLOAD
 342                 /**
 343                  * to get packet types, shift 64-bit values down 30 bits
 344                  * and so ptype is in lower 8-bits in each
 345                  */
 346                 const __m512i ptypes4_7 = _mm512_srli_epi64(desc4_7, 30);
 347                 const __m256i ptypes6_7 = _mm512_extracti64x4_epi64(ptypes4_7, 1);
 348                 const __m256i ptypes4_5 = _mm512_extracti64x4_epi64(ptypes4_7, 0);
 349                 const uint8_t ptype7 = _mm256_extract_epi8(ptypes6_7, 24);
 350                 const uint8_t ptype6 = _mm256_extract_epi8(ptypes6_7, 8);
 351                 const uint8_t ptype5 = _mm256_extract_epi8(ptypes4_5, 24);
 352                 const uint8_t ptype4 = _mm256_extract_epi8(ptypes4_5, 8);
 353
 354                 const __m512i ptype4_7 = _mm512_set_epi32
 355                         (0, 0, 0, type_table[ptype7],
 356                          0, 0, 0, type_table[ptype6],
 357                          0, 0, 0, type_table[ptype5],
 358                          0, 0, 0, type_table[ptype4]);
 359                 mb4_7 = _mm512_mask_blend_epi32(0x1111, mb4_7, ptype4_7);
 360 #endif
 361
 362                 /**
 363                  * convert descriptors 0-3 into mbufs, adjusting length and
 364                  * re-arranging fields. Then write into the mbuf
 365                  */
 366                 const __m512i len0_3 = _mm512_slli_epi32(raw_desc0_3,
 367                                                          PKTLEN_SHIFT);
 368                 const __m512i desc0_3 = _mm512_mask_blend_epi16(IAVF_RX_LEN_MASK,
 369                                                                 raw_desc0_3,
 370                                                                 len0_3);
 371                 __m512i mb0_3 = _mm512_shuffle_epi8(desc0_3, shuf_msk);
 372
 373                 mb0_3 = _mm512_add_epi32(mb0_3, crc_adjust);
 374 #ifdef IAVF_RX_PTYPE_OFFLOAD
 375                 /* get the packet types */
 376                 const __m512i ptypes0_3 = _mm512_srli_epi64(desc0_3, 30);
 377                 const __m256i ptypes2_3 = _mm512_extracti64x4_epi64(ptypes0_3, 1);
 378                 const __m256i ptypes0_1 = _mm512_extracti64x4_epi64(ptypes0_3, 0);
 379                 const uint8_t ptype3 = _mm256_extract_epi8(ptypes2_3, 24);
 380                 const uint8_t ptype2 = _mm256_extract_epi8(ptypes2_3, 8);
 381                 const uint8_t ptype1 = _mm256_extract_epi8(ptypes0_1, 24);
 382                 const uint8_t ptype0 = _mm256_extract_epi8(ptypes0_1, 8);
 383
 384                 const __m512i ptype0_3 = _mm512_set_epi32
 385                         (0, 0, 0, type_table[ptype3],
 386                          0, 0, 0, type_table[ptype2],
 387                          0, 0, 0, type_table[ptype1],
 388                          0, 0, 0, type_table[ptype0]);
 389                 mb0_3 = _mm512_mask_blend_epi32(0x1111, mb0_3, ptype0_3);
 390 #endif
 391
 392                 /**
 393                  * use permute/extract to get status content
 394                  * After the operations, the packets status flags are in the
 395                  * order (hi->lo): [1, 3, 5, 7, 0, 2, 4, 6]
 396                  */
 397                 /* merge the status bits into one register */
 398                 const __m512i status_permute_msk = _mm512_set_epi32
 399                         (0, 0, 0, 0,
 400                          0, 0, 0, 0,
 401                          22, 30, 6, 14,
 402                          18, 26, 2, 10);
 403                 const __m512i raw_status0_7 = _mm512_permutex2var_epi32
 404                         (raw_desc4_7, status_permute_msk, raw_desc0_3);
 405                 __m256i status0_7 = _mm512_extracti64x4_epi64
 406                         (raw_status0_7, 0);
 407
 408                 /* now do flag manipulation */
 409
 410                 /* merge flags */
 411                 __m256i mbuf_flags = _mm256_set1_epi32(0);
 412
 413                 if (offload) {
 414 #if defined(IAVF_RX_CSUM_OFFLOAD) || defined(IAVF_RX_VLAN_OFFLOAD) || defined(IAVF_RX_RSS_OFFLOAD)
 415                         /* Status/Error flag masks */
 416                         /**
 417                          * mask everything except RSS, flow director and VLAN flags
 418                          * bit2 is for VLAN tag, bit11 for flow director indication
 419                          * bit13:12 for RSS indication. Bits 3-5 of error
 420                          * field (bits 22-24) are for IP/L4 checksum errors
 421                          */
 422                         const __m256i flags_mask =
 423                                 _mm256_set1_epi32((1 << 2) | (1 << 11) |
 424                                                   (3 << 12) | (7 << 22));
 425 #endif
 426
 427 #ifdef IAVF_RX_VLAN_OFFLOAD
 428                         /**
 429                          * data to be shuffled by result of flag mask. If VLAN bit is set,
 430                          * (bit 2), then position 4 in this array will be used in the
 431                          * destination
 432                          */
 433                         const __m256i vlan_flags_shuf =
 434                                 _mm256_set_epi32(0, 0, PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED, 0,
 435                                                  0, 0, PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED, 0);
 436 #endif
 437
 438 #ifdef IAVF_RX_RSS_OFFLOAD
 439                         /**
 440                          * data to be shuffled by result of flag mask, shifted down 11.
 441                          * If RSS/FDIR bits are set, shuffle moves appropriate flags in
 442                          * place.
 443                          */
 444                         const __m256i rss_flags_shuf =
 445                                 _mm256_set_epi8(0, 0, 0, 0, 0, 0, 0, 0,
 446                                                 PKT_RX_RSS_HASH | PKT_RX_FDIR, PKT_RX_RSS_HASH,
 447                                                 0, 0, 0, 0, PKT_RX_FDIR, 0,/* end up 128-bits */
 448                                                 0, 0, 0, 0, 0, 0, 0, 0,
 449                                                 PKT_RX_RSS_HASH | PKT_RX_FDIR, PKT_RX_RSS_HASH,
 450                                                 0, 0, 0, 0, PKT_RX_FDIR, 0);
 451 #endif
 452
 453 #ifdef IAVF_RX_CSUM_OFFLOAD
 454                         /**
 455                          * data to be shuffled by the result of the flags mask shifted by 22
 456                          * bits.  This gives use the l3_l4 flags.
 457                          */
 458                         const __m256i l3_l4_flags_shuf = _mm256_set_epi8(0, 0, 0, 0, 0, 0, 0, 0,
 459                                         /* shift right 1 bit to make sure it not exceed 255 */
 460                                         (PKT_RX_OUTER_IP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD |
 461                                          PKT_RX_IP_CKSUM_BAD) >> 1,
 462                                         (PKT_RX_IP_CKSUM_GOOD | PKT_RX_OUTER_IP_CKSUM_BAD |
 463                                          PKT_RX_L4_CKSUM_BAD) >> 1,
 464                                         (PKT_RX_OUTER_IP_CKSUM_BAD | PKT_RX_IP_CKSUM_BAD) >> 1,
 465                                         (PKT_RX_IP_CKSUM_GOOD | PKT_RX_OUTER_IP_CKSUM_BAD) >> 1,
 466                                         (PKT_RX_L4_CKSUM_BAD | PKT_RX_IP_CKSUM_BAD) >> 1,
 467                                         (PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_BAD) >> 1,
 468                                         PKT_RX_IP_CKSUM_BAD >> 1,
 469                                         (PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD) >> 1,
 470                                         /* second 128-bits */
 471                                         0, 0, 0, 0, 0, 0, 0, 0,
 472                                         (PKT_RX_OUTER_IP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD |
 473                                          PKT_RX_IP_CKSUM_BAD) >> 1,
 474                                         (PKT_RX_IP_CKSUM_GOOD | PKT_RX_OUTER_IP_CKSUM_BAD |
 475                                          PKT_RX_L4_CKSUM_BAD) >> 1,
 476                                         (PKT_RX_OUTER_IP_CKSUM_BAD | PKT_RX_IP_CKSUM_BAD) >> 1,
 477                                         (PKT_RX_IP_CKSUM_GOOD | PKT_RX_OUTER_IP_CKSUM_BAD) >> 1,
 478                                         (PKT_RX_L4_CKSUM_BAD | PKT_RX_IP_CKSUM_BAD) >> 1,
 479                                         (PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_BAD) >> 1,
 480                                         PKT_RX_IP_CKSUM_BAD >> 1,
 481                                         (PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD) >> 1);
 482
 483                         const __m256i cksum_mask =
 484                                 _mm256_set1_epi32(PKT_RX_IP_CKSUM_GOOD | PKT_RX_IP_CKSUM_BAD |
 485                                                   PKT_RX_L4_CKSUM_GOOD | PKT_RX_L4_CKSUM_BAD |
 486                                                   PKT_RX_OUTER_IP_CKSUM_BAD);
 487 #endif
 488
 489 #if defined(IAVF_RX_CSUM_OFFLOAD) || defined(IAVF_RX_VLAN_OFFLOAD) || defined(IAVF_RX_RSS_OFFLOAD)
 490                         /* get only flag/error bits we want */
 491                         const __m256i flag_bits =
 492                                 _mm256_and_si256(status0_7, flags_mask);
 493 #endif
 494                         /* set vlan and rss flags */
 495 #ifdef IAVF_RX_VLAN_OFFLOAD
 496                         const __m256i vlan_flags =
 497                                 _mm256_shuffle_epi8(vlan_flags_shuf, flag_bits);
 498 #endif
 499 #ifdef IAVF_RX_RSS_OFFLOAD
 500                         const __m256i rss_flags =
 501                                 _mm256_shuffle_epi8(rss_flags_shuf,
 502                                                     _mm256_srli_epi32(flag_bits, 11));
 503 #endif
 504 #ifdef IAVF_RX_CSUM_OFFLOAD
 505                         /**
 506                          * l3_l4_error flags, shuffle, then shift to correct adjustment
 507                          * of flags in flags_shuf, and finally mask out extra bits
 508                          */
 509                         __m256i l3_l4_flags = _mm256_shuffle_epi8(l3_l4_flags_shuf,
 510                                                         _mm256_srli_epi32(flag_bits, 22));
 511                         l3_l4_flags = _mm256_slli_epi32(l3_l4_flags, 1);
 512                         l3_l4_flags = _mm256_and_si256(l3_l4_flags, cksum_mask);
 513 #endif
 514
 515 #ifdef IAVF_RX_CSUM_OFFLOAD
 516                         mbuf_flags = _mm256_or_si256(mbuf_flags, l3_l4_flags);
 517 #endif
 518 #ifdef IAVF_RX_RSS_OFFLOAD
 519                         mbuf_flags = _mm256_or_si256(mbuf_flags, rss_flags);
 520 #endif
 521 #ifdef IAVF_RX_VLAN_OFFLOAD
 522                         mbuf_flags = _mm256_or_si256(mbuf_flags, vlan_flags);
 523 #endif
 524                 }
 525
 526                 /**
 527                  * At this point, we have the 8 sets of flags in the low 16-bits
 528                  * of each 32-bit value in vlan0.
 529                  * We want to extract these, and merge them with the mbuf init
 530                  * data so we can do a single write to the mbuf to set the flags
 531                  * and all the other initialization fields. Extracting the
 532                  * appropriate flags means that we have to do a shift and blend
 533                  * for each mbuf before we do the write. However, we can also
 534                  * add in the previously computed rx_descriptor fields to
 535                  * make a single 256-bit write per mbuf
 536                  */
 537                 /* check the structure matches expectations */
 538                 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, ol_flags) !=
 539                                  offsetof(struct rte_mbuf, rearm_data) + 8);
 540                 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, rearm_data) !=
 541                                  RTE_ALIGN(offsetof(struct rte_mbuf,
 542                                                     rearm_data),
 543                                                     16));
 544                 /* build up data and do writes */
 545                 __m256i rearm0, rearm1, rearm2, rearm3, rearm4, rearm5,
 546                         rearm6, rearm7;
 547                 const __m256i mb4_5 = _mm512_extracti64x4_epi64(mb4_7, 0);
 548                 const __m256i mb6_7 = _mm512_extracti64x4_epi64(mb4_7, 1);
 549                 const __m256i mb0_1 = _mm512_extracti64x4_epi64(mb0_3, 0);
 550                 const __m256i mb2_3 = _mm512_extracti64x4_epi64(mb0_3, 1);
 551
 552                 if (offload) {
 553                         rearm6 = _mm256_blend_epi32(mbuf_init,
 554                                                     _mm256_slli_si256(mbuf_flags, 8),
 555                                                     0x04);
 556                         rearm4 = _mm256_blend_epi32(mbuf_init,
 557                                                     _mm256_slli_si256(mbuf_flags, 4),
 558                                                     0x04);
 559                         rearm2 = _mm256_blend_epi32(mbuf_init, mbuf_flags, 0x04);
 560                         rearm0 = _mm256_blend_epi32(mbuf_init,
 561                                                     _mm256_srli_si256(mbuf_flags, 4),
 562                                                     0x04);
 563                         /* permute to add in the rx_descriptor e.g. rss fields */
 564                         rearm6 = _mm256_permute2f128_si256(rearm6, mb6_7, 0x20);
 565                         rearm4 = _mm256_permute2f128_si256(rearm4, mb4_5, 0x20);
 566                         rearm2 = _mm256_permute2f128_si256(rearm2, mb2_3, 0x20);
 567                         rearm0 = _mm256_permute2f128_si256(rearm0, mb0_1, 0x20);
 568                 } else {
 569                         rearm6 = _mm256_permute2f128_si256(mbuf_init, mb6_7, 0x20);
 570                         rearm4 = _mm256_permute2f128_si256(mbuf_init, mb4_5, 0x20);
 571                         rearm2 = _mm256_permute2f128_si256(mbuf_init, mb2_3, 0x20);
 572                         rearm0 = _mm256_permute2f128_si256(mbuf_init, mb0_1, 0x20);
 573                 }
 574                 /* write to mbuf */
 575                 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 6]->rearm_data,
 576                                     rearm6);
 577                 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 4]->rearm_data,
 578                                     rearm4);
 579                 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 2]->rearm_data,
 580                                     rearm2);
 581                 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 0]->rearm_data,
 582                                     rearm0);
 583
 584                 /* repeat for the odd mbufs */
 585                 if (offload) {
 586                         const __m256i odd_flags =
 587                                 _mm256_castsi128_si256
 588                                         (_mm256_extracti128_si256(mbuf_flags, 1));
 589                         rearm7 = _mm256_blend_epi32(mbuf_init,
 590                                                     _mm256_slli_si256(odd_flags, 8),
 591                                                     0x04);
 592                         rearm5 = _mm256_blend_epi32(mbuf_init,
 593                                                     _mm256_slli_si256(odd_flags, 4),
 594                                                     0x04);
 595                         rearm3 = _mm256_blend_epi32(mbuf_init, odd_flags, 0x04);
 596                         rearm1 = _mm256_blend_epi32(mbuf_init,
 597                                                     _mm256_srli_si256(odd_flags, 4),
 598                                                     0x04);
 599                         /* since odd mbufs are already in hi 128-bits use blend */
 600                         rearm7 = _mm256_blend_epi32(rearm7, mb6_7, 0xF0);
 601                         rearm5 = _mm256_blend_epi32(rearm5, mb4_5, 0xF0);
 602                         rearm3 = _mm256_blend_epi32(rearm3, mb2_3, 0xF0);
 603                         rearm1 = _mm256_blend_epi32(rearm1, mb0_1, 0xF0);
 604                 } else {
 605                         rearm7 = _mm256_blend_epi32(mbuf_init, mb6_7, 0xF0);
 606                         rearm5 = _mm256_blend_epi32(mbuf_init, mb4_5, 0xF0);
 607                         rearm3 = _mm256_blend_epi32(mbuf_init, mb2_3, 0xF0);
 608                         rearm1 = _mm256_blend_epi32(mbuf_init, mb0_1, 0xF0);
 609                 }
 610                 /* again write to mbufs */
 611                 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 7]->rearm_data,
 612                                     rearm7);
 613                 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 5]->rearm_data,
 614                                     rearm5);
 615                 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 3]->rearm_data,
 616                                     rearm3);
 617                 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 1]->rearm_data,
 618                                     rearm1);
 619
 620                 /* extract and record EOP bit */
 621                 if (split_packet) {
 622                         const __m128i eop_mask =
 623                                 _mm_set1_epi16(1 << IAVF_RX_DESC_STATUS_EOF_SHIFT);
 624                         const __m256i eop_bits256 = _mm256_and_si256(status0_7,
 625                                                                      eop_check);
 626                         /* pack status bits into a single 128-bit register */
 627                         const __m128i eop_bits =
 628                                 _mm_packus_epi32
 629                                         (_mm256_castsi256_si128(eop_bits256),
 630                                          _mm256_extractf128_si256(eop_bits256,
 631                                                                   1));
 632                         /**
 633                          * flip bits, and mask out the EOP bit, which is now
 634                          * a split-packet bit i.e. !EOP, rather than EOP one.
 635                          */
 636                         __m128i split_bits = _mm_andnot_si128(eop_bits,
 637                                                               eop_mask);
 638                         /**
 639                          * eop bits are out of order, so we need to shuffle them
 640                          * back into order again. In doing so, only use low 8
 641                          * bits, which acts like another pack instruction
 642                          * The original order is (hi->lo): 1,3,5,7,0,2,4,6
 643                          * [Since we use epi8, the 16-bit positions are
 644                          * multiplied by 2 in the eop_shuffle value.]
 645                          */
 646                         __m128i eop_shuffle =
 647                                 _mm_set_epi8(/* zero hi 64b */
 648                                              0xFF, 0xFF, 0xFF, 0xFF,
 649                                              0xFF, 0xFF, 0xFF, 0xFF,
 650                                              /* move values to lo 64b */
 651                                              8, 0, 10, 2,
 652                                              12, 4, 14, 6);
 653                         split_bits = _mm_shuffle_epi8(split_bits, eop_shuffle);
 654                         *(uint64_t *)split_packet =
 655                                 _mm_cvtsi128_si64(split_bits);
 656                         split_packet += IAVF_DESCS_PER_LOOP_AVX;
 657                 }
 658
 659                 /* perform dd_check */
 660                 status0_7 = _mm256_and_si256(status0_7, dd_check);
 661                 status0_7 = _mm256_packs_epi32(status0_7,
 662                                                _mm256_setzero_si256());
 663
 664                 uint64_t burst = __builtin_popcountll
 665                                         (_mm_cvtsi128_si64
 666                                                 (_mm256_extracti128_si256
 667                                                         (status0_7, 1)));
 668                 burst += __builtin_popcountll
 669                                 (_mm_cvtsi128_si64
 670                                         (_mm256_castsi256_si128(status0_7)));
 671                 received += burst;
 672                 if (burst != IAVF_DESCS_PER_LOOP_AVX)
 673                         break;
 674         }
 675
 676         /* update tail pointers */
 677         rxq->rx_tail += received;
 678         rxq->rx_tail &= (rxq->nb_rx_desc - 1);
 679         if ((rxq->rx_tail & 1) == 1 && received > 1) { /* keep aligned */
 680                 rxq->rx_tail--;
 681                 received--;
 682         }
 683         rxq->rxrearm_nb += received;
 684         return received;
 685 }
 686
 687 static __rte_always_inline __m256i
 688 flex_rxd_to_fdir_flags_vec_avx512(const __m256i fdir_id0_7)
 689 {
 690 #define FDID_MIS_MAGIC 0xFFFFFFFF
 691         RTE_BUILD_BUG_ON(PKT_RX_FDIR != (1 << 2));
 692         RTE_BUILD_BUG_ON(PKT_RX_FDIR_ID != (1 << 13));
 693         const __m256i pkt_fdir_bit = _mm256_set1_epi32(PKT_RX_FDIR |
 694                                                        PKT_RX_FDIR_ID);
 695         /* desc->flow_id field == 0xFFFFFFFF means fdir mismatch */
 696         const __m256i fdir_mis_mask = _mm256_set1_epi32(FDID_MIS_MAGIC);
 697         __m256i fdir_mask = _mm256_cmpeq_epi32(fdir_id0_7,
 698                                                fdir_mis_mask);
 699         /* this XOR op results to bit-reverse the fdir_mask */
 700         fdir_mask = _mm256_xor_si256(fdir_mask, fdir_mis_mask);
 701         const __m256i fdir_flags = _mm256_and_si256(fdir_mask, pkt_fdir_bit);
 702
 703         return fdir_flags;
 704 }
 705
 706 static __rte_always_inline uint16_t
 707 _iavf_recv_raw_pkts_vec_avx512_flex_rxd(struct iavf_rx_queue *rxq,
 708                                         struct rte_mbuf **rx_pkts,
 709                                         uint16_t nb_pkts,
 710                                         uint8_t *split_packet,
 711                                         bool offload)
 712 {
 713 #ifdef IAVF_RX_PTYPE_OFFLOAD
 714         const uint32_t *type_table = rxq->vsi->adapter->ptype_tbl;
 715 #endif
 716
 717         const __m256i mbuf_init = _mm256_set_epi64x(0, 0, 0,
 718                                                     rxq->mbuf_initializer);
 719         struct rte_mbuf **sw_ring = &rxq->sw_ring[rxq->rx_tail];
 720         volatile union iavf_rx_flex_desc *rxdp =
 721                 (union iavf_rx_flex_desc *)rxq->rx_ring + rxq->rx_tail;
 722
 723         rte_prefetch0(rxdp);
 724
 725         /* nb_pkts has to be floor-aligned to IAVF_DESCS_PER_LOOP_AVX */
 726         nb_pkts = RTE_ALIGN_FLOOR(nb_pkts, IAVF_DESCS_PER_LOOP_AVX);
 727
 728         /* See if we need to rearm the RX queue - gives the prefetch a bit
 729          * of time to act
 730          */
 731         if (rxq->rxrearm_nb > IAVF_RXQ_REARM_THRESH)
 732                 iavf_rxq_rearm(rxq);
 733
 734         /* Before we start moving massive data around, check to see if
 735          * there is actually a packet available
 736          */
 737         if (!(rxdp->wb.status_error0 &
 738               rte_cpu_to_le_32(1 << IAVF_RX_FLEX_DESC_STATUS0_DD_S)))
 739                 return 0;
 740
 741         /* constants used in processing loop */
 742         const __m512i crc_adjust =
 743                 _mm512_set_epi32
 744                         (/* 1st descriptor */
 745                          0,             /* ignore non-length fields */
 746                          -rxq->crc_len, /* sub crc on data_len */
 747                          -rxq->crc_len, /* sub crc on pkt_len */
 748                          0,             /* ignore pkt_type field */
 749                          /* 2nd descriptor */
 750                          0,             /* ignore non-length fields */
 751                          -rxq->crc_len, /* sub crc on data_len */
 752                          -rxq->crc_len, /* sub crc on pkt_len */
 753                          0,             /* ignore pkt_type field */
 754                          /* 3rd descriptor */
 755                          0,             /* ignore non-length fields */
 756                          -rxq->crc_len, /* sub crc on data_len */
 757                          -rxq->crc_len, /* sub crc on pkt_len */
 758                          0,             /* ignore pkt_type field */
 759                          /* 4th descriptor */
 760                          0,             /* ignore non-length fields */
 761                          -rxq->crc_len, /* sub crc on data_len */
 762                          -rxq->crc_len, /* sub crc on pkt_len */
 763                          0              /* ignore pkt_type field */
 764                         );
 765
 766         /* 8 packets DD mask, LSB in each 32-bit value */
 767         const __m256i dd_check = _mm256_set1_epi32(1);
 768
 769         /* 8 packets EOP mask, second-LSB in each 32-bit value */
 770         const __m256i eop_check = _mm256_slli_epi32(dd_check,
 771                         IAVF_RX_FLEX_DESC_STATUS0_EOF_S);
 772
 773         /* mask to shuffle from desc. to mbuf (4 descriptors)*/
 774         const __m512i shuf_msk =
 775                 _mm512_set_epi32
 776                         (/* 1st descriptor */
 777                          0xFFFFFFFF,    /* rss hash parsed separately */
 778                          0x0B0A0504,    /* octet 10~11, 16 bits vlan_macip */
 779                                         /* octet 4~5, 16 bits data_len */
 780                          0xFFFF0504,    /* skip hi 16 bits pkt_len, zero out */
 781                                         /* octet 4~5, 16 bits pkt_len */
 782                          0xFFFFFFFF,    /* pkt_type set as unknown */
 783                          /* 2nd descriptor */
 784                          0xFFFFFFFF,    /* rss hash parsed separately */
 785                          0x0B0A0504,    /* octet 10~11, 16 bits vlan_macip */
 786                                         /* octet 4~5, 16 bits data_len */
 787                          0xFFFF0504,    /* skip hi 16 bits pkt_len, zero out */
 788                                         /* octet 4~5, 16 bits pkt_len */
 789                          0xFFFFFFFF,    /* pkt_type set as unknown */
 790                          /* 3rd descriptor */
 791                          0xFFFFFFFF,    /* rss hash parsed separately */
 792                          0x0B0A0504,    /* octet 10~11, 16 bits vlan_macip */
 793                                         /* octet 4~5, 16 bits data_len */
 794                          0xFFFF0504,    /* skip hi 16 bits pkt_len, zero out */
 795                                         /* octet 4~5, 16 bits pkt_len */
 796                          0xFFFFFFFF,    /* pkt_type set as unknown */
 797                          /* 4th descriptor */
 798                          0xFFFFFFFF,    /* rss hash parsed separately */
 799                          0x0B0A0504,    /* octet 10~11, 16 bits vlan_macip */
 800                                         /* octet 4~5, 16 bits data_len */
 801                          0xFFFF0504,    /* skip hi 16 bits pkt_len, zero out */
 802                                         /* octet 4~5, 16 bits pkt_len */
 803                          0xFFFFFFFF     /* pkt_type set as unknown */
 804                         );
 805         /**
 806          * compile-time check the above crc and shuffle layout is correct.
 807          * NOTE: the first field (lowest address) is given last in set_epi
 808          * calls above.
 809          */
 810         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, pkt_len) !=
 811                          offsetof(struct rte_mbuf, rx_descriptor_fields1) + 4);
 812         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, data_len) !=
 813                          offsetof(struct rte_mbuf, rx_descriptor_fields1) + 8);
 814         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, vlan_tci) !=
 815                          offsetof(struct rte_mbuf, rx_descriptor_fields1) + 10);
 816         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, hash) !=
 817                          offsetof(struct rte_mbuf, rx_descriptor_fields1) + 12);
 818
 819         uint16_t i, received;
 820
 821         for (i = 0, received = 0; i < nb_pkts;
 822              i += IAVF_DESCS_PER_LOOP_AVX,
 823              rxdp += IAVF_DESCS_PER_LOOP_AVX) {
 824                 /* step 1, copy over 8 mbuf pointers to rx_pkts array */
 825                 _mm256_storeu_si256((void *)&rx_pkts[i],
 826                                     _mm256_loadu_si256((void *)&sw_ring[i]));
 827 #ifdef RTE_ARCH_X86_64
 828                 _mm256_storeu_si256
 829                         ((void *)&rx_pkts[i + 4],
 830                          _mm256_loadu_si256((void *)&sw_ring[i + 4]));
 831 #endif
 832
 833                 __m512i raw_desc0_3, raw_desc4_7;
 834
 835                 const __m128i raw_desc7 =
 836                         _mm_load_si128((void *)(rxdp + 7));
 837                 rte_compiler_barrier();
 838                 const __m128i raw_desc6 =
 839                         _mm_load_si128((void *)(rxdp + 6));
 840                 rte_compiler_barrier();
 841                 const __m128i raw_desc5 =
 842                         _mm_load_si128((void *)(rxdp + 5));
 843                 rte_compiler_barrier();
 844                 const __m128i raw_desc4 =
 845                         _mm_load_si128((void *)(rxdp + 4));
 846                 rte_compiler_barrier();
 847                 const __m128i raw_desc3 =
 848                         _mm_load_si128((void *)(rxdp + 3));
 849                 rte_compiler_barrier();
 850                 const __m128i raw_desc2 =
 851                         _mm_load_si128((void *)(rxdp + 2));
 852                 rte_compiler_barrier();
 853                 const __m128i raw_desc1 =
 854                         _mm_load_si128((void *)(rxdp + 1));
 855                 rte_compiler_barrier();
 856                 const __m128i raw_desc0 =
 857                         _mm_load_si128((void *)(rxdp + 0));
 858
 859                 raw_desc4_7 = _mm512_broadcast_i32x4(raw_desc4);
 860                 raw_desc4_7 = _mm512_inserti32x4(raw_desc4_7, raw_desc5, 1);
 861                 raw_desc4_7 = _mm512_inserti32x4(raw_desc4_7, raw_desc6, 2);
 862                 raw_desc4_7 = _mm512_inserti32x4(raw_desc4_7, raw_desc7, 3);
 863                 raw_desc0_3 = _mm512_broadcast_i32x4(raw_desc0);
 864                 raw_desc0_3 = _mm512_inserti32x4(raw_desc0_3, raw_desc1, 1);
 865                 raw_desc0_3 = _mm512_inserti32x4(raw_desc0_3, raw_desc2, 2);
 866                 raw_desc0_3 = _mm512_inserti32x4(raw_desc0_3, raw_desc3, 3);
 867
 868                 if (split_packet) {
 869                         int j;
 870
 871                         for (j = 0; j < IAVF_DESCS_PER_LOOP_AVX; j++)
 872                                 rte_mbuf_prefetch_part2(rx_pkts[i + j]);
 873                 }
 874
 875                 /**
 876                  * convert descriptors 4-7 into mbufs, re-arrange fields.
 877                  * Then write into the mbuf.
 878                  */
 879                 __m512i mb4_7 = _mm512_shuffle_epi8(raw_desc4_7, shuf_msk);
 880
 881                 mb4_7 = _mm512_add_epi32(mb4_7, crc_adjust);
 882 #ifdef IAVF_RX_PTYPE_OFFLOAD
 883                 /**
 884                  * to get packet types, ptype is located in bit16-25
 885                  * of each 128bits
 886                  */
 887                 const __m512i ptype_mask =
 888                         _mm512_set1_epi16(IAVF_RX_FLEX_DESC_PTYPE_M);
 889                 const __m512i ptypes4_7 =
 890                         _mm512_and_si512(raw_desc4_7, ptype_mask);
 891                 const __m256i ptypes6_7 = _mm512_extracti64x4_epi64(ptypes4_7, 1);
 892                 const __m256i ptypes4_5 = _mm512_extracti64x4_epi64(ptypes4_7, 0);
 893                 const uint16_t ptype7 = _mm256_extract_epi16(ptypes6_7, 9);
 894                 const uint16_t ptype6 = _mm256_extract_epi16(ptypes6_7, 1);
 895                 const uint16_t ptype5 = _mm256_extract_epi16(ptypes4_5, 9);
 896                 const uint16_t ptype4 = _mm256_extract_epi16(ptypes4_5, 1);
 897
 898                 const __m512i ptype4_7 = _mm512_set_epi32
 899                         (0, 0, 0, type_table[ptype7],
 900                          0, 0, 0, type_table[ptype6],
 901                          0, 0, 0, type_table[ptype5],
 902                          0, 0, 0, type_table[ptype4]);
 903                 mb4_7 = _mm512_mask_blend_epi32(0x1111, mb4_7, ptype4_7);
 904 #endif
 905
 906                 /**
 907                  * convert descriptors 0-3 into mbufs, re-arrange fields.
 908                  * Then write into the mbuf.
 909                  */
 910                 __m512i mb0_3 = _mm512_shuffle_epi8(raw_desc0_3, shuf_msk);
 911
 912                 mb0_3 = _mm512_add_epi32(mb0_3, crc_adjust);
 913 #ifdef IAVF_RX_PTYPE_OFFLOAD
 914                 /**
 915                  * to get packet types, ptype is located in bit16-25
 916                  * of each 128bits
 917                  */
 918                 const __m512i ptypes0_3 =
 919                         _mm512_and_si512(raw_desc0_3, ptype_mask);
 920                 const __m256i ptypes2_3 = _mm512_extracti64x4_epi64(ptypes0_3, 1);
 921                 const __m256i ptypes0_1 = _mm512_extracti64x4_epi64(ptypes0_3, 0);
 922                 const uint16_t ptype3 = _mm256_extract_epi16(ptypes2_3, 9);
 923                 const uint16_t ptype2 = _mm256_extract_epi16(ptypes2_3, 1);
 924                 const uint16_t ptype1 = _mm256_extract_epi16(ptypes0_1, 9);
 925                 const uint16_t ptype0 = _mm256_extract_epi16(ptypes0_1, 1);
 926
 927                 const __m512i ptype0_3 = _mm512_set_epi32
 928                         (0, 0, 0, type_table[ptype3],
 929                          0, 0, 0, type_table[ptype2],
 930                          0, 0, 0, type_table[ptype1],
 931                          0, 0, 0, type_table[ptype0]);
 932                 mb0_3 = _mm512_mask_blend_epi32(0x1111, mb0_3, ptype0_3);
 933 #endif
 934
 935                 /**
 936                  * use permute/extract to get status content
 937                  * After the operations, the packets status flags are in the
 938                  * order (hi->lo): [1, 3, 5, 7, 0, 2, 4, 6]
 939                  */
 940                 /* merge the status bits into one register */
 941                 const __m512i status_permute_msk = _mm512_set_epi32
 942                         (0, 0, 0, 0,
 943                          0, 0, 0, 0,
 944                          22, 30, 6, 14,
 945                          18, 26, 2, 10);
 946                 const __m512i raw_status0_7 = _mm512_permutex2var_epi32
 947                         (raw_desc4_7, status_permute_msk, raw_desc0_3);
 948                 __m256i status0_7 = _mm512_extracti64x4_epi64
 949                         (raw_status0_7, 0);
 950
 951                 /* now do flag manipulation */
 952
 953                 /* merge flags */
 954                 __m256i mbuf_flags = _mm256_set1_epi32(0);
 955
 956                 if (offload) {
 957 #if defined(IAVF_RX_CSUM_OFFLOAD) || defined(IAVF_RX_VLAN_OFFLOAD) || defined(IAVF_RX_RSS_OFFLOAD)
 958                         /* Status/Error flag masks */
 959                         /**
 960                          * mask everything except Checksum Reports, RSS indication
 961                          * and VLAN indication.
 962                          * bit6:4 for IP/L4 checksum errors.
 963                          * bit12 is for RSS indication.
 964                          * bit13 is for VLAN indication.
 965                          */
 966                         const __m256i flags_mask =
 967                                 _mm256_set1_epi32((7 << 4) | (1 << 12) | (1 << 13));
 968 #endif
 969 #ifdef IAVF_RX_CSUM_OFFLOAD
 970                         /**
 971                          * data to be shuffled by the result of the flags mask shifted by 4
 972                          * bits.  This gives use the l3_l4 flags.
 973                          */
 974                         const __m256i l3_l4_flags_shuf = _mm256_set_epi8(0, 0, 0, 0, 0, 0, 0, 0,
 975                                         /* shift right 1 bit to make sure it not exceed 255 */
 976                                         (PKT_RX_OUTER_IP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD |
 977                                          PKT_RX_IP_CKSUM_BAD) >> 1,
 978                                         (PKT_RX_OUTER_IP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD |
 979                                          PKT_RX_IP_CKSUM_GOOD) >> 1,
 980                                         (PKT_RX_OUTER_IP_CKSUM_BAD | PKT_RX_L4_CKSUM_GOOD |
 981                                          PKT_RX_IP_CKSUM_BAD) >> 1,
 982                                         (PKT_RX_OUTER_IP_CKSUM_BAD | PKT_RX_L4_CKSUM_GOOD |
 983                                          PKT_RX_IP_CKSUM_GOOD) >> 1,
 984                                         (PKT_RX_L4_CKSUM_BAD | PKT_RX_IP_CKSUM_BAD) >> 1,
 985                                         (PKT_RX_L4_CKSUM_BAD | PKT_RX_IP_CKSUM_GOOD) >> 1,
 986                                         (PKT_RX_L4_CKSUM_GOOD | PKT_RX_IP_CKSUM_BAD) >> 1,
 987                                         (PKT_RX_L4_CKSUM_GOOD | PKT_RX_IP_CKSUM_GOOD) >> 1,
 988                                         /* second 128-bits */
 989                                         0, 0, 0, 0, 0, 0, 0, 0,
 990                                         (PKT_RX_OUTER_IP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD |
 991                                          PKT_RX_IP_CKSUM_BAD) >> 1,
 992                                         (PKT_RX_OUTER_IP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD |
 993                                          PKT_RX_IP_CKSUM_GOOD) >> 1,
 994                                         (PKT_RX_OUTER_IP_CKSUM_BAD | PKT_RX_L4_CKSUM_GOOD |
 995                                          PKT_RX_IP_CKSUM_BAD) >> 1,
 996                                         (PKT_RX_OUTER_IP_CKSUM_BAD | PKT_RX_L4_CKSUM_GOOD |
 997                                          PKT_RX_IP_CKSUM_GOOD) >> 1,
 998                                         (PKT_RX_L4_CKSUM_BAD | PKT_RX_IP_CKSUM_BAD) >> 1,
 999                                         (PKT_RX_L4_CKSUM_BAD | PKT_RX_IP_CKSUM_GOOD) >> 1,
1000                                         (PKT_RX_L4_CKSUM_GOOD | PKT_RX_IP_CKSUM_BAD) >> 1,
1001                                         (PKT_RX_L4_CKSUM_GOOD | PKT_RX_IP_CKSUM_GOOD) >> 1);
1002                         const __m256i cksum_mask =
1003                                 _mm256_set1_epi32(PKT_RX_IP_CKSUM_GOOD | PKT_RX_IP_CKSUM_BAD |
1004                                                   PKT_RX_L4_CKSUM_GOOD | PKT_RX_L4_CKSUM_BAD |
1005                                                   PKT_RX_OUTER_IP_CKSUM_BAD);
1006 #endif
1007 #if defined(IAVF_RX_VLAN_OFFLOAD) || defined(IAVF_RX_RSS_OFFLOAD)
1008                         /**
1009                          * data to be shuffled by result of flag mask, shifted down 12.
1010                          * If RSS(bit12)/VLAN(bit13) are set,
1011                          * shuffle moves appropriate flags in place.
1012                          */
1013                         const __m256i rss_vlan_flags_shuf = _mm256_set_epi8(0, 0, 0, 0,
1014                                         0, 0, 0, 0,
1015                                         0, 0, 0, 0,
1016                                         PKT_RX_RSS_HASH | PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED,
1017                                         PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED,
1018                                         PKT_RX_RSS_HASH, 0,
1019                                         /* end up 128-bits */
1020                                         0, 0, 0, 0,
1021                                         0, 0, 0, 0,
1022                                         0, 0, 0, 0,
1023                                         PKT_RX_RSS_HASH | PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED,
1024                                         PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED,
1025                                         PKT_RX_RSS_HASH, 0);
1026 #endif
1027
1028 #if defined(IAVF_RX_CSUM_OFFLOAD) || defined(IAVF_RX_VLAN_OFFLOAD) || defined(IAVF_RX_RSS_OFFLOAD)
1029                         /* get only flag/error bits we want */
1030                         const __m256i flag_bits =
1031                                 _mm256_and_si256(status0_7, flags_mask);
1032 #endif
1033 #ifdef IAVF_RX_CSUM_OFFLOAD
1034                         /**
1035                          * l3_l4_error flags, shuffle, then shift to correct adjustment
1036                          * of flags in flags_shuf, and finally mask out extra bits
1037                          */
1038                         __m256i l3_l4_flags = _mm256_shuffle_epi8(l3_l4_flags_shuf,
1039                                         _mm256_srli_epi32(flag_bits, 4));
1040                         l3_l4_flags = _mm256_slli_epi32(l3_l4_flags, 1);
1041                         l3_l4_flags = _mm256_and_si256(l3_l4_flags, cksum_mask);
1042 #endif
1043 #if defined(IAVF_RX_VLAN_OFFLOAD) || defined(IAVF_RX_RSS_OFFLOAD)
1044                         /* set rss and vlan flags */
1045                         const __m256i rss_vlan_flag_bits =
1046                                 _mm256_srli_epi32(flag_bits, 12);
1047                         const __m256i rss_vlan_flags =
1048                                 _mm256_shuffle_epi8(rss_vlan_flags_shuf,
1049                                                     rss_vlan_flag_bits);
1050 #endif
1051
1052 #ifdef IAVF_RX_CSUM_OFFLOAD
1053                         mbuf_flags = _mm256_or_si256(mbuf_flags, l3_l4_flags);
1054 #endif
1055 #if defined(IAVF_RX_VLAN_OFFLOAD) || defined(IAVF_RX_RSS_OFFLOAD)
1056                         mbuf_flags = _mm256_or_si256(mbuf_flags, rss_vlan_flags);
1057 #endif
1058                 }
1059
1060 #ifdef IAVF_RX_FDIR_OFFLOAD
1061                 if (rxq->fdir_enabled) {
1062                         const __m512i fdir_permute_mask = _mm512_set_epi32
1063                                 (0, 0, 0, 0,
1064                                  0, 0, 0, 0,
1065                                  7, 15, 23, 31,
1066                                  3, 11, 19, 27);
1067                         __m512i fdir_tmp = _mm512_permutex2var_epi32
1068                                 (raw_desc0_3, fdir_permute_mask, raw_desc4_7);
1069                         const __m256i fdir_id0_7 = _mm512_extracti64x4_epi64
1070                                 (fdir_tmp, 0);
1071                         const __m256i fdir_flags =
1072                                 flex_rxd_to_fdir_flags_vec_avx512(fdir_id0_7);
1073
1074                         /* merge with fdir_flags */
1075                         mbuf_flags = _mm256_or_si256(mbuf_flags, fdir_flags);
1076
1077                         /* write to mbuf: have to use scalar store here */
1078                         rx_pkts[i + 0]->hash.fdir.hi =
1079                                 _mm256_extract_epi32(fdir_id0_7, 3);
1080
1081                         rx_pkts[i + 1]->hash.fdir.hi =
1082                                 _mm256_extract_epi32(fdir_id0_7, 7);
1083
1084                         rx_pkts[i + 2]->hash.fdir.hi =
1085                                 _mm256_extract_epi32(fdir_id0_7, 2);
1086
1087                         rx_pkts[i + 3]->hash.fdir.hi =
1088                                 _mm256_extract_epi32(fdir_id0_7, 6);
1089
1090                         rx_pkts[i + 4]->hash.fdir.hi =
1091                                 _mm256_extract_epi32(fdir_id0_7, 1);
1092
1093                         rx_pkts[i + 5]->hash.fdir.hi =
1094                                 _mm256_extract_epi32(fdir_id0_7, 5);
1095
1096                         rx_pkts[i + 6]->hash.fdir.hi =
1097                                 _mm256_extract_epi32(fdir_id0_7, 0);
1098
1099                         rx_pkts[i + 7]->hash.fdir.hi =
1100                                 _mm256_extract_epi32(fdir_id0_7, 4);
1101                 } /* if() on fdir_enabled */
1102 #endif
1103
1104                 __m256i mb4_5 = _mm512_extracti64x4_epi64(mb4_7, 0);
1105                 __m256i mb6_7 = _mm512_extracti64x4_epi64(mb4_7, 1);
1106                 __m256i mb0_1 = _mm512_extracti64x4_epi64(mb0_3, 0);
1107                 __m256i mb2_3 = _mm512_extracti64x4_epi64(mb0_3, 1);
1108
1109 #ifndef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
1110                 if (offload) {
1111 #ifdef IAVF_RX_RSS_OFFLOAD
1112                         /**
1113                          * needs to load 2nd 16B of each desc for RSS hash parsing,
1114                          * will cause performance drop to get into this context.
1115                          */
1116                         if (rxq->vsi->adapter->eth_dev->data->dev_conf.rxmode.offloads &
1117                             DEV_RX_OFFLOAD_RSS_HASH) {
1118                                 /* load bottom half of every 32B desc */
1119                                 const __m128i raw_desc_bh7 =
1120                                         _mm_load_si128
1121                                                 ((void *)(&rxdp[7].wb.status_error1));
1122                                 rte_compiler_barrier();
1123                                 const __m128i raw_desc_bh6 =
1124                                         _mm_load_si128
1125                                                 ((void *)(&rxdp[6].wb.status_error1));
1126                                 rte_compiler_barrier();
1127                                 const __m128i raw_desc_bh5 =
1128                                         _mm_load_si128
1129                                                 ((void *)(&rxdp[5].wb.status_error1));
1130                                 rte_compiler_barrier();
1131                                 const __m128i raw_desc_bh4 =
1132                                         _mm_load_si128
1133                                                 ((void *)(&rxdp[4].wb.status_error1));
1134                                 rte_compiler_barrier();
1135                                 const __m128i raw_desc_bh3 =
1136                                         _mm_load_si128
1137                                                 ((void *)(&rxdp[3].wb.status_error1));
1138                                 rte_compiler_barrier();
1139                                 const __m128i raw_desc_bh2 =
1140                                         _mm_load_si128
1141                                                 ((void *)(&rxdp[2].wb.status_error1));
1142                                 rte_compiler_barrier();
1143                                 const __m128i raw_desc_bh1 =
1144                                         _mm_load_si128
1145                                                 ((void *)(&rxdp[1].wb.status_error1));
1146                                 rte_compiler_barrier();
1147                                 const __m128i raw_desc_bh0 =
1148                                         _mm_load_si128
1149                                                 ((void *)(&rxdp[0].wb.status_error1));
1150
1151                                 __m256i raw_desc_bh6_7 =
1152                                         _mm256_inserti128_si256
1153                                                 (_mm256_castsi128_si256(raw_desc_bh6),
1154                                                  raw_desc_bh7, 1);
1155                                 __m256i raw_desc_bh4_5 =
1156                                         _mm256_inserti128_si256
1157                                                 (_mm256_castsi128_si256(raw_desc_bh4),
1158                                                  raw_desc_bh5, 1);
1159                                 __m256i raw_desc_bh2_3 =
1160                                         _mm256_inserti128_si256
1161                                                 (_mm256_castsi128_si256(raw_desc_bh2),
1162                                                  raw_desc_bh3, 1);
1163                                 __m256i raw_desc_bh0_1 =
1164                                         _mm256_inserti128_si256
1165                                                 (_mm256_castsi128_si256(raw_desc_bh0),
1166                                                  raw_desc_bh1, 1);
1167
1168                                 /**
1169                                  * to shift the 32b RSS hash value to the
1170                                  * highest 32b of each 128b before mask
1171                                  */
1172                                 __m256i rss_hash6_7 =
1173                                         _mm256_slli_epi64(raw_desc_bh6_7, 32);
1174                                 __m256i rss_hash4_5 =
1175                                         _mm256_slli_epi64(raw_desc_bh4_5, 32);
1176                                 __m256i rss_hash2_3 =
1177                                         _mm256_slli_epi64(raw_desc_bh2_3, 32);
1178                                 __m256i rss_hash0_1 =
1179                                         _mm256_slli_epi64(raw_desc_bh0_1, 32);
1180
1181                                 __m256i rss_hash_msk =
1182                                         _mm256_set_epi32(0xFFFFFFFF, 0, 0, 0,
1183                                                          0xFFFFFFFF, 0, 0, 0);
1184
1185                                 rss_hash6_7 = _mm256_and_si256
1186                                                 (rss_hash6_7, rss_hash_msk);
1187                                 rss_hash4_5 = _mm256_and_si256
1188                                                 (rss_hash4_5, rss_hash_msk);
1189                                 rss_hash2_3 = _mm256_and_si256
1190                                                 (rss_hash2_3, rss_hash_msk);
1191                                 rss_hash0_1 = _mm256_and_si256
1192                                                 (rss_hash0_1, rss_hash_msk);
1193
1194                                 mb6_7 = _mm256_or_si256(mb6_7, rss_hash6_7);
1195                                 mb4_5 = _mm256_or_si256(mb4_5, rss_hash4_5);
1196                                 mb2_3 = _mm256_or_si256(mb2_3, rss_hash2_3);
1197                                 mb0_1 = _mm256_or_si256(mb0_1, rss_hash0_1);
1198                         } /* if() on RSS hash parsing */
1199 #endif
1200                 }
1201 #endif
1202
1203                 /**
1204                  * At this point, we have the 8 sets of flags in the low 16-bits
1205                  * of each 32-bit value in vlan0.
1206                  * We want to extract these, and merge them with the mbuf init
1207                  * data so we can do a single write to the mbuf to set the flags
1208                  * and all the other initialization fields. Extracting the
1209                  * appropriate flags means that we have to do a shift and blend
1210                  * for each mbuf before we do the write. However, we can also
1211                  * add in the previously computed rx_descriptor fields to
1212                  * make a single 256-bit write per mbuf
1213                  */
1214                 /* check the structure matches expectations */
1215                 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, ol_flags) !=
1216                                  offsetof(struct rte_mbuf, rearm_data) + 8);
1217                 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, rearm_data) !=
1218                                  RTE_ALIGN(offsetof(struct rte_mbuf,
1219                                                     rearm_data),
1220                                                     16));
1221                 /* build up data and do writes */
1222                 __m256i rearm0, rearm1, rearm2, rearm3, rearm4, rearm5,
1223                         rearm6, rearm7;
1224                 rearm6 = _mm256_blend_epi32(mbuf_init,
1225                                             _mm256_slli_si256(mbuf_flags, 8),
1226                                             0x04);
1227                 rearm4 = _mm256_blend_epi32(mbuf_init,
1228                                             _mm256_slli_si256(mbuf_flags, 4),
1229                                             0x04);
1230                 rearm2 = _mm256_blend_epi32(mbuf_init, mbuf_flags, 0x04);
1231                 rearm0 = _mm256_blend_epi32(mbuf_init,
1232                                             _mm256_srli_si256(mbuf_flags, 4),
1233                                             0x04);
1234                 /* permute to add in the rx_descriptor e.g. rss fields */
1235                 rearm6 = _mm256_permute2f128_si256(rearm6, mb6_7, 0x20);
1236                 rearm4 = _mm256_permute2f128_si256(rearm4, mb4_5, 0x20);
1237                 rearm2 = _mm256_permute2f128_si256(rearm2, mb2_3, 0x20);
1238                 rearm0 = _mm256_permute2f128_si256(rearm0, mb0_1, 0x20);
1239                 /* write to mbuf */
1240                 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 6]->rearm_data,
1241                                     rearm6);
1242                 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 4]->rearm_data,
1243                                     rearm4);
1244                 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 2]->rearm_data,
1245                                     rearm2);
1246                 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 0]->rearm_data,
1247                                     rearm0);
1248
1249                 /* repeat for the odd mbufs */
1250                 const __m256i odd_flags =
1251                         _mm256_castsi128_si256
1252                                 (_mm256_extracti128_si256(mbuf_flags, 1));
1253                 rearm7 = _mm256_blend_epi32(mbuf_init,
1254                                             _mm256_slli_si256(odd_flags, 8),
1255                                             0x04);
1256                 rearm5 = _mm256_blend_epi32(mbuf_init,
1257                                             _mm256_slli_si256(odd_flags, 4),
1258                                             0x04);
1259                 rearm3 = _mm256_blend_epi32(mbuf_init, odd_flags, 0x04);
1260                 rearm1 = _mm256_blend_epi32(mbuf_init,
1261                                             _mm256_srli_si256(odd_flags, 4),
1262                                             0x04);
1263                 /* since odd mbufs are already in hi 128-bits use blend */
1264                 rearm7 = _mm256_blend_epi32(rearm7, mb6_7, 0xF0);
1265                 rearm5 = _mm256_blend_epi32(rearm5, mb4_5, 0xF0);
1266                 rearm3 = _mm256_blend_epi32(rearm3, mb2_3, 0xF0);
1267                 rearm1 = _mm256_blend_epi32(rearm1, mb0_1, 0xF0);
1268                 /* again write to mbufs */
1269                 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 7]->rearm_data,
1270                                     rearm7);
1271                 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 5]->rearm_data,
1272                                     rearm5);
1273                 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 3]->rearm_data,
1274                                     rearm3);
1275                 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 1]->rearm_data,
1276                                     rearm1);
1277
1278                 /* extract and record EOP bit */
1279                 if (split_packet) {
1280                         const __m128i eop_mask =
1281                                 _mm_set1_epi16(1 <<
1282                                                IAVF_RX_FLEX_DESC_STATUS0_EOF_S);
1283                         const __m256i eop_bits256 = _mm256_and_si256(status0_7,
1284                                                                      eop_check);
1285                         /* pack status bits into a single 128-bit register */
1286                         const __m128i eop_bits =
1287                                 _mm_packus_epi32
1288                                         (_mm256_castsi256_si128(eop_bits256),
1289                                          _mm256_extractf128_si256(eop_bits256,
1290                                                                   1));
1291                         /**
1292                          * flip bits, and mask out the EOP bit, which is now
1293                          * a split-packet bit i.e. !EOP, rather than EOP one.
1294                          */
1295                         __m128i split_bits = _mm_andnot_si128(eop_bits,
1296                                                               eop_mask);
1297                         /**
1298                          * eop bits are out of order, so we need to shuffle them
1299                          * back into order again. In doing so, only use low 8
1300                          * bits, which acts like another pack instruction
1301                          * The original order is (hi->lo): 1,3,5,7,0,2,4,6
1302                          * [Since we use epi8, the 16-bit positions are
1303                          * multiplied by 2 in the eop_shuffle value.]
1304                          */
1305                         __m128i eop_shuffle =
1306                                 _mm_set_epi8(/* zero hi 64b */
1307                                              0xFF, 0xFF, 0xFF, 0xFF,
1308                                              0xFF, 0xFF, 0xFF, 0xFF,
1309                                              /* move values to lo 64b */
1310                                              8, 0, 10, 2,
1311                                              12, 4, 14, 6);
1312                         split_bits = _mm_shuffle_epi8(split_bits, eop_shuffle);
1313                         *(uint64_t *)split_packet =
1314                                 _mm_cvtsi128_si64(split_bits);
1315                         split_packet += IAVF_DESCS_PER_LOOP_AVX;
1316                 }
1317
1318                 /* perform dd_check */
1319                 status0_7 = _mm256_and_si256(status0_7, dd_check);
1320                 status0_7 = _mm256_packs_epi32(status0_7,
1321                                                _mm256_setzero_si256());
1322
1323                 uint64_t burst = __builtin_popcountll
1324                                         (_mm_cvtsi128_si64
1325                                                 (_mm256_extracti128_si256
1326                                                         (status0_7, 1)));
1327                 burst += __builtin_popcountll
1328                                 (_mm_cvtsi128_si64
1329                                         (_mm256_castsi256_si128(status0_7)));
1330                 received += burst;
1331                 if (burst != IAVF_DESCS_PER_LOOP_AVX)
1332                         break;
1333         }
1334
1335         /* update tail pointers */
1336         rxq->rx_tail += received;
1337         rxq->rx_tail &= (rxq->nb_rx_desc - 1);
1338         if ((rxq->rx_tail & 1) == 1 && received > 1) { /* keep aligned */
1339                 rxq->rx_tail--;
1340                 received--;
1341         }
1342         rxq->rxrearm_nb += received;
1343         return received;
1344 }
1345
1346 /**
1347  * Notice:
1348  * - nb_pkts < IAVF_DESCS_PER_LOOP, just return no packet
1349  */
1350 uint16_t
1351 iavf_recv_pkts_vec_avx512(void *rx_queue, struct rte_mbuf **rx_pkts,
1352                           uint16_t nb_pkts)
1353 {
1354         return _iavf_recv_raw_pkts_vec_avx512(rx_queue, rx_pkts, nb_pkts,
1355                                               NULL, false);
1356 }
1357
1358 /**
1359  * Notice:
1360  * - nb_pkts < IAVF_DESCS_PER_LOOP, just return no packet
1361  */
1362 uint16_t
1363 iavf_recv_pkts_vec_avx512_flex_rxd(void *rx_queue, struct rte_mbuf **rx_pkts,
1364                                    uint16_t nb_pkts)
1365 {
1366         return _iavf_recv_raw_pkts_vec_avx512_flex_rxd(rx_queue, rx_pkts,
1367                                                        nb_pkts, NULL, false);
1368 }
1369
1370 /**
1371  * vPMD receive routine that reassembles single burst of 32 scattered packets
1372  * Notice:
1373  * - nb_pkts < IAVF_DESCS_PER_LOOP, just return no packet
1374  */
1375 static __rte_always_inline uint16_t
1376 iavf_recv_scattered_burst_vec_avx512(void *rx_queue, struct rte_mbuf **rx_pkts,
1377                                      uint16_t nb_pkts, bool offload)
1378 {
1379         struct iavf_rx_queue *rxq = rx_queue;
1380         uint8_t split_flags[IAVF_VPMD_RX_MAX_BURST] = {0};
1381
1382         /* get some new buffers */
1383         uint16_t nb_bufs = _iavf_recv_raw_pkts_vec_avx512(rxq, rx_pkts, nb_pkts,
1384                                                           split_flags, offload);
1385         if (nb_bufs == 0)
1386                 return 0;
1387
1388         /* happy day case, full burst + no packets to be joined */
1389         const uint64_t *split_fl64 = (uint64_t *)split_flags;
1390
1391         if (!rxq->pkt_first_seg &&
1392             split_fl64[0] == 0 && split_fl64[1] == 0 &&
1393             split_fl64[2] == 0 && split_fl64[3] == 0)
1394                 return nb_bufs;
1395
1396         /* reassemble any packets that need reassembly*/
1397         unsigned int i = 0;
1398
1399         if (!rxq->pkt_first_seg) {
1400                 /* find the first split flag, and only reassemble then*/
1401                 while (i < nb_bufs && !split_flags[i])
1402                         i++;
1403                 if (i == nb_bufs)
1404                         return nb_bufs;
1405                 rxq->pkt_first_seg = rx_pkts[i];
1406         }
1407         return i + reassemble_packets(rxq, &rx_pkts[i], nb_bufs - i,
1408                                       &split_flags[i]);
1409 }
1410
1411 /**
1412  * vPMD receive routine that reassembles scattered packets.
1413  * Main receive routine that can handle arbitrary burst sizes
1414  * Notice:
1415  * - nb_pkts < IAVF_DESCS_PER_LOOP, just return no packet
1416  */
1417 static __rte_always_inline uint16_t
1418 iavf_recv_scattered_pkts_vec_avx512_cmn(void *rx_queue, struct rte_mbuf **rx_pkts,
1419                                         uint16_t nb_pkts, bool offload)
1420 {
1421         uint16_t retval = 0;
1422
1423         while (nb_pkts > IAVF_VPMD_RX_MAX_BURST) {
1424                 uint16_t burst = iavf_recv_scattered_burst_vec_avx512(rx_queue,
1425                                 rx_pkts + retval, IAVF_VPMD_RX_MAX_BURST, offload);
1426                 retval += burst;
1427                 nb_pkts -= burst;
1428                 if (burst < IAVF_VPMD_RX_MAX_BURST)
1429                         return retval;
1430         }
1431         return retval + iavf_recv_scattered_burst_vec_avx512(rx_queue,
1432                                 rx_pkts + retval, nb_pkts, offload);
1433 }
1434
1435 uint16_t
1436 iavf_recv_scattered_pkts_vec_avx512(void *rx_queue, struct rte_mbuf **rx_pkts,
1437                                     uint16_t nb_pkts)
1438 {
1439         return iavf_recv_scattered_pkts_vec_avx512_cmn(rx_queue, rx_pkts,
1440                                                        nb_pkts, false);
1441 }
1442
1443 /**
1444  * vPMD receive routine that reassembles single burst of
1445  * 32 scattered packets for flex RxD
1446  * Notice:
1447  * - nb_pkts < IAVF_DESCS_PER_LOOP, just return no packet
1448  */
1449 static __rte_always_inline uint16_t
1450 iavf_recv_scattered_burst_vec_avx512_flex_rxd(void *rx_queue,
1451                                               struct rte_mbuf **rx_pkts,
1452                                               uint16_t nb_pkts,
1453                                               bool offload)
1454 {
1455         struct iavf_rx_queue *rxq = rx_queue;
1456         uint8_t split_flags[IAVF_VPMD_RX_MAX_BURST] = {0};
1457
1458         /* get some new buffers */
1459         uint16_t nb_bufs = _iavf_recv_raw_pkts_vec_avx512_flex_rxd(rxq,
1460                                         rx_pkts, nb_pkts, split_flags, offload);
1461         if (nb_bufs == 0)
1462                 return 0;
1463
1464         /* happy day case, full burst + no packets to be joined */
1465         const uint64_t *split_fl64 = (uint64_t *)split_flags;
1466
1467         if (!rxq->pkt_first_seg &&
1468             split_fl64[0] == 0 && split_fl64[1] == 0 &&
1469             split_fl64[2] == 0 && split_fl64[3] == 0)
1470                 return nb_bufs;
1471
1472         /* reassemble any packets that need reassembly*/
1473         unsigned int i = 0;
1474
1475         if (!rxq->pkt_first_seg) {
1476                 /* find the first split flag, and only reassemble then*/
1477                 while (i < nb_bufs && !split_flags[i])
1478                         i++;
1479                 if (i == nb_bufs)
1480                         return nb_bufs;
1481                 rxq->pkt_first_seg = rx_pkts[i];
1482         }
1483         return i + reassemble_packets(rxq, &rx_pkts[i], nb_bufs - i,
1484                                       &split_flags[i]);
1485 }
1486
1487 /**
1488  * vPMD receive routine that reassembles scattered packets for flex RxD.
1489  * Main receive routine that can handle arbitrary burst sizes
1490  * Notice:
1491  * - nb_pkts < IAVF_DESCS_PER_LOOP, just return no packet
1492  */
1493 static __rte_always_inline uint16_t
1494 iavf_recv_scattered_pkts_vec_avx512_flex_rxd_cmn(void *rx_queue,
1495                                                  struct rte_mbuf **rx_pkts,
1496                                                  uint16_t nb_pkts,
1497                                                  bool offload)
1498 {
1499         uint16_t retval = 0;
1500
1501         while (nb_pkts > IAVF_VPMD_RX_MAX_BURST) {
1502                 uint16_t burst =
1503                         iavf_recv_scattered_burst_vec_avx512_flex_rxd
1504                                 (rx_queue, rx_pkts + retval,
1505                                  IAVF_VPMD_RX_MAX_BURST, offload);
1506                 retval += burst;
1507                 nb_pkts -= burst;
1508                 if (burst < IAVF_VPMD_RX_MAX_BURST)
1509                         return retval;
1510         }
1511         return retval + iavf_recv_scattered_burst_vec_avx512_flex_rxd(rx_queue,
1512                                 rx_pkts + retval, nb_pkts, offload);
1513 }
1514
1515 uint16_t
1516 iavf_recv_scattered_pkts_vec_avx512_flex_rxd(void *rx_queue,
1517                                              struct rte_mbuf **rx_pkts,
1518                                              uint16_t nb_pkts)
1519 {
1520         return iavf_recv_scattered_pkts_vec_avx512_flex_rxd_cmn(rx_queue,
1521                                                                 rx_pkts,
1522                                                                 nb_pkts,
1523                                                                 false);
1524 }
1525
1526 uint16_t
1527 iavf_recv_pkts_vec_avx512_offload(void *rx_queue, struct rte_mbuf **rx_pkts,
1528                                   uint16_t nb_pkts)
1529 {
1530         return _iavf_recv_raw_pkts_vec_avx512(rx_queue, rx_pkts,
1531                                               nb_pkts, NULL, true);
1532 }
1533
1534 uint16_t
1535 iavf_recv_scattered_pkts_vec_avx512_offload(void *rx_queue,
1536                                             struct rte_mbuf **rx_pkts,
1537                                             uint16_t nb_pkts)
1538 {
1539         return iavf_recv_scattered_pkts_vec_avx512_cmn(rx_queue, rx_pkts,
1540                                                        nb_pkts, true);
1541 }
1542
1543 uint16_t
1544 iavf_recv_pkts_vec_avx512_flex_rxd_offload(void *rx_queue,
1545                                            struct rte_mbuf **rx_pkts,
1546                                            uint16_t nb_pkts)
1547 {
1548         return _iavf_recv_raw_pkts_vec_avx512_flex_rxd(rx_queue,
1549                                                        rx_pkts,
1550                                                        nb_pkts,
1551                                                        NULL,
1552                                                        true);
1553 }
1554
1555 uint16_t
1556 iavf_recv_scattered_pkts_vec_avx512_flex_rxd_offload(void *rx_queue,
1557                                                      struct rte_mbuf **rx_pkts,
1558                                                      uint16_t nb_pkts)
1559 {
1560         return iavf_recv_scattered_pkts_vec_avx512_flex_rxd_cmn(rx_queue,
1561                                                                 rx_pkts,
1562                                                                 nb_pkts,
1563                                                                 true);
1564 }
1565
1566 static __rte_always_inline int
1567 iavf_tx_free_bufs_avx512(struct iavf_tx_queue *txq)
1568 {
1569         struct iavf_tx_vec_entry *txep;
1570         uint32_t n;
1571         uint32_t i;
1572         int nb_free = 0;
1573         struct rte_mbuf *m, *free[IAVF_VPMD_TX_MAX_FREE_BUF];
1574
1575         /* check DD bits on threshold descriptor */
1576         if ((txq->tx_ring[txq->next_dd].cmd_type_offset_bsz &
1577              rte_cpu_to_le_64(IAVF_TXD_QW1_DTYPE_MASK)) !=
1578             rte_cpu_to_le_64(IAVF_TX_DESC_DTYPE_DESC_DONE))
1579                 return 0;
1580
1581         n = txq->rs_thresh;
1582
1583          /* first buffer to free from S/W ring is at index
1584           * tx_next_dd - (tx_rs_thresh-1)
1585           */
1586         txep = (void *)txq->sw_ring;
1587         txep += txq->next_dd - (n - 1);
1588
1589         if (txq->offloads & DEV_TX_OFFLOAD_MBUF_FAST_FREE && (n & 31) == 0) {
1590                 struct rte_mempool *mp = txep[0].mbuf->pool;
1591                 struct rte_mempool_cache *cache = rte_mempool_default_cache(mp,
1592                                                                 rte_lcore_id());
1593                 void **cache_objs;
1594
1595                 if (!cache || cache->len == 0)
1596                         goto normal;
1597
1598                 cache_objs = &cache->objs[cache->len];
1599
1600                 if (n > RTE_MEMPOOL_CACHE_MAX_SIZE) {
1601                         rte_mempool_ops_enqueue_bulk(mp, (void *)txep, n);
1602                         goto done;
1603                 }
1604
1605                 /* The cache follows the following algorithm
1606                  *   1. Add the objects to the cache
1607                  *   2. Anything greater than the cache min value (if it crosses the
1608                  *   cache flush threshold) is flushed to the ring.
1609                  */
1610                 /* Add elements back into the cache */
1611                 uint32_t copied = 0;
1612                 /* n is multiple of 32 */
1613                 while (copied < n) {
1614                         const __m512i a = _mm512_loadu_si512(&txep[copied]);
1615                         const __m512i b = _mm512_loadu_si512(&txep[copied + 8]);
1616                         const __m512i c = _mm512_loadu_si512(&txep[copied + 16]);
1617                         const __m512i d = _mm512_loadu_si512(&txep[copied + 24]);
1618
1619                         _mm512_storeu_si512(&cache_objs[copied], a);
1620                         _mm512_storeu_si512(&cache_objs[copied + 8], b);
1621                         _mm512_storeu_si512(&cache_objs[copied + 16], c);
1622                         _mm512_storeu_si512(&cache_objs[copied + 24], d);
1623                         copied += 32;
1624                 }
1625                 cache->len += n;
1626
1627                 if (cache->len >= cache->flushthresh) {
1628                         rte_mempool_ops_enqueue_bulk(mp,
1629                                                      &cache->objs[cache->size],
1630                                                      cache->len - cache->size);
1631                         cache->len = cache->size;
1632                 }
1633                 goto done;
1634         }
1635
1636 normal:
1637         m = rte_pktmbuf_prefree_seg(txep[0].mbuf);
1638         if (likely(m)) {
1639                 free[0] = m;
1640                 nb_free = 1;
1641                 for (i = 1; i < n; i++) {
1642                         m = rte_pktmbuf_prefree_seg(txep[i].mbuf);
1643                         if (likely(m)) {
1644                                 if (likely(m->pool == free[0]->pool)) {
1645                                         free[nb_free++] = m;
1646                                 } else {
1647                                         rte_mempool_put_bulk(free[0]->pool,
1648                                                              (void *)free,
1649                                                              nb_free);
1650                                         free[0] = m;
1651                                         nb_free = 1;
1652                                 }
1653                         }
1654                 }
1655                 rte_mempool_put_bulk(free[0]->pool, (void **)free, nb_free);
1656         } else {
1657                 for (i = 1; i < n; i++) {
1658                         m = rte_pktmbuf_prefree_seg(txep[i].mbuf);
1659                         if (m)
1660                                 rte_mempool_put(m->pool, m);
1661                 }
1662         }
1663
1664 done:
1665         /* buffers were freed, update counters */
1666         txq->nb_free = (uint16_t)(txq->nb_free + txq->rs_thresh);
1667         txq->next_dd = (uint16_t)(txq->next_dd + txq->rs_thresh);
1668         if (txq->next_dd >= txq->nb_tx_desc)
1669                 txq->next_dd = (uint16_t)(txq->rs_thresh - 1);
1670
1671         return txq->rs_thresh;
1672 }
1673
1674 static __rte_always_inline void
1675 tx_backlog_entry_avx512(struct iavf_tx_vec_entry *txep,
1676                         struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
1677 {
1678         int i;
1679
1680         for (i = 0; i < (int)nb_pkts; ++i)
1681                 txep[i].mbuf = tx_pkts[i];
1682 }
1683
1684 static __rte_always_inline void
1685 iavf_vtx1(volatile struct iavf_tx_desc *txdp,
1686           struct rte_mbuf *pkt, uint64_t flags, bool offload)
1687 {
1688         uint64_t high_qw =
1689                 (IAVF_TX_DESC_DTYPE_DATA |
1690                  ((uint64_t)flags  << IAVF_TXD_QW1_CMD_SHIFT) |
1691                  ((uint64_t)pkt->data_len << IAVF_TXD_QW1_TX_BUF_SZ_SHIFT));
1692         if (offload)
1693                 iavf_txd_enable_offload(pkt, &high_qw);
1694
1695         __m128i descriptor = _mm_set_epi64x(high_qw,
1696                                             pkt->buf_iova + pkt->data_off);
1697         _mm_storeu_si128((__m128i *)txdp, descriptor);
1698 }
1699
1700 #define IAVF_TX_LEN_MASK 0xAA
1701 #define IAVF_TX_OFF_MASK 0x55
1702 static __rte_always_inline void
1703 iavf_vtx(volatile struct iavf_tx_desc *txdp,
1704          struct rte_mbuf **pkt, uint16_t nb_pkts,  uint64_t flags,
1705          bool offload)
1706 {
1707         const uint64_t hi_qw_tmpl = (IAVF_TX_DESC_DTYPE_DATA |
1708                         ((uint64_t)flags  << IAVF_TXD_QW1_CMD_SHIFT));
1709
1710         /* if unaligned on 32-bit boundary, do one to align */
1711         if (((uintptr_t)txdp & 0x1F) != 0 && nb_pkts != 0) {
1712                 iavf_vtx1(txdp, *pkt, flags, offload);
1713                 nb_pkts--, txdp++, pkt++;
1714         }
1715
1716         /* do 4 at a time while possible, in bursts */
1717         for (; nb_pkts > 3; txdp += 4, pkt += 4, nb_pkts -= 4) {
1718                 uint64_t hi_qw3 =
1719                         hi_qw_tmpl |
1720                         ((uint64_t)pkt[3]->data_len <<
1721                          IAVF_TXD_QW1_TX_BUF_SZ_SHIFT);
1722                 if (offload)
1723                         iavf_txd_enable_offload(pkt[3], &hi_qw3);
1724                 uint64_t hi_qw2 =
1725                         hi_qw_tmpl |
1726                         ((uint64_t)pkt[2]->data_len <<
1727                          IAVF_TXD_QW1_TX_BUF_SZ_SHIFT);
1728                 if (offload)
1729                         iavf_txd_enable_offload(pkt[2], &hi_qw2);
1730                 uint64_t hi_qw1 =
1731                         hi_qw_tmpl |
1732                         ((uint64_t)pkt[1]->data_len <<
1733                          IAVF_TXD_QW1_TX_BUF_SZ_SHIFT);
1734                 if (offload)
1735                         iavf_txd_enable_offload(pkt[1], &hi_qw1);
1736                 uint64_t hi_qw0 =
1737                         hi_qw_tmpl |
1738                         ((uint64_t)pkt[0]->data_len <<
1739                          IAVF_TXD_QW1_TX_BUF_SZ_SHIFT);
1740                 if (offload)
1741                         iavf_txd_enable_offload(pkt[0], &hi_qw0);
1742
1743                 __m512i desc0_3 =
1744                         _mm512_set_epi64
1745                                 (hi_qw3,
1746                                  pkt[3]->buf_iova + pkt[3]->data_off,
1747                                  hi_qw2,
1748                                  pkt[2]->buf_iova + pkt[2]->data_off,
1749                                  hi_qw1,
1750                                  pkt[1]->buf_iova + pkt[1]->data_off,
1751                                  hi_qw0,
1752                                  pkt[0]->buf_iova + pkt[0]->data_off);
1753                 _mm512_storeu_si512((void *)txdp, desc0_3);
1754         }
1755
1756         /* do any last ones */
1757         while (nb_pkts) {
1758                 iavf_vtx1(txdp, *pkt, flags, offload);
1759                 txdp++, pkt++, nb_pkts--;
1760         }
1761 }
1762
1763 static __rte_always_inline uint16_t
1764 iavf_xmit_fixed_burst_vec_avx512(void *tx_queue, struct rte_mbuf **tx_pkts,
1765                                  uint16_t nb_pkts, bool offload)
1766 {
1767         struct iavf_tx_queue *txq = (struct iavf_tx_queue *)tx_queue;
1768         volatile struct iavf_tx_desc *txdp;
1769         struct iavf_tx_vec_entry *txep;
1770         uint16_t n, nb_commit, tx_id;
1771         /* bit2 is reserved and must be set to 1 according to Spec */
1772         uint64_t flags = IAVF_TX_DESC_CMD_EOP | IAVF_TX_DESC_CMD_ICRC;
1773         uint64_t rs = IAVF_TX_DESC_CMD_RS | flags;
1774
1775         /* cross rx_thresh boundary is not allowed */
1776         nb_pkts = RTE_MIN(nb_pkts, txq->rs_thresh);
1777
1778         if (txq->nb_free < txq->free_thresh)
1779                 iavf_tx_free_bufs_avx512(txq);
1780
1781         nb_commit = nb_pkts = (uint16_t)RTE_MIN(txq->nb_free, nb_pkts);
1782         if (unlikely(nb_pkts == 0))
1783                 return 0;
1784
1785         tx_id = txq->tx_tail;
1786         txdp = &txq->tx_ring[tx_id];
1787         txep = (void *)txq->sw_ring;
1788         txep += tx_id;
1789
1790         txq->nb_free = (uint16_t)(txq->nb_free - nb_pkts);
1791
1792         n = (uint16_t)(txq->nb_tx_desc - tx_id);
1793         if (nb_commit >= n) {
1794                 tx_backlog_entry_avx512(txep, tx_pkts, n);
1795
1796                 iavf_vtx(txdp, tx_pkts, n - 1, flags, offload);
1797                 tx_pkts += (n - 1);
1798                 txdp += (n - 1);
1799
1800                 iavf_vtx1(txdp, *tx_pkts++, rs, offload);
1801
1802                 nb_commit = (uint16_t)(nb_commit - n);
1803
1804                 tx_id = 0;
1805                 txq->next_rs = (uint16_t)(txq->rs_thresh - 1);
1806
1807                 /* avoid reach the end of ring */
1808                 txdp = &txq->tx_ring[tx_id];
1809                 txep = (void *)txq->sw_ring;
1810                 txep += tx_id;
1811         }
1812
1813         tx_backlog_entry_avx512(txep, tx_pkts, nb_commit);
1814
1815         iavf_vtx(txdp, tx_pkts, nb_commit, flags, offload);
1816
1817         tx_id = (uint16_t)(tx_id + nb_commit);
1818         if (tx_id > txq->next_rs) {
1819                 txq->tx_ring[txq->next_rs].cmd_type_offset_bsz |=
1820                         rte_cpu_to_le_64(((uint64_t)IAVF_TX_DESC_CMD_RS) <<
1821                                          IAVF_TXD_QW1_CMD_SHIFT);
1822                 txq->next_rs =
1823                         (uint16_t)(txq->next_rs + txq->rs_thresh);
1824         }
1825
1826         txq->tx_tail = tx_id;
1827
1828         IAVF_PCI_REG_WRITE(txq->qtx_tail, txq->tx_tail);
1829
1830         return nb_pkts;
1831 }
1832
1833 static __rte_always_inline uint16_t
1834 iavf_xmit_pkts_vec_avx512_cmn(void *tx_queue, struct rte_mbuf **tx_pkts,
1835                               uint16_t nb_pkts, bool offload)
1836 {
1837         uint16_t nb_tx = 0;
1838         struct iavf_tx_queue *txq = (struct iavf_tx_queue *)tx_queue;
1839
1840         while (nb_pkts) {
1841                 uint16_t ret, num;
1842
1843                 num = (uint16_t)RTE_MIN(nb_pkts, txq->rs_thresh);
1844                 ret = iavf_xmit_fixed_burst_vec_avx512(tx_queue, &tx_pkts[nb_tx],
1845                                                        num, offload);
1846                 nb_tx += ret;
1847                 nb_pkts -= ret;
1848                 if (ret < num)
1849                         break;
1850         }
1851
1852         return nb_tx;
1853 }
1854
1855 uint16_t
1856 iavf_xmit_pkts_vec_avx512(void *tx_queue, struct rte_mbuf **tx_pkts,
1857                           uint16_t nb_pkts)
1858 {
1859         return iavf_xmit_pkts_vec_avx512_cmn(tx_queue, tx_pkts, nb_pkts, false);
1860 }
1861
1862 static inline void
1863 iavf_tx_queue_release_mbufs_avx512(struct iavf_tx_queue *txq)
1864 {
1865         unsigned int i;
1866         const uint16_t max_desc = (uint16_t)(txq->nb_tx_desc - 1);
1867         struct iavf_tx_vec_entry *swr = (void *)txq->sw_ring;
1868
1869         if (!txq->sw_ring || txq->nb_free == max_desc)
1870                 return;
1871
1872         i = txq->next_dd - txq->rs_thresh + 1;
1873         if (txq->tx_tail < i) {
1874                 for (; i < txq->nb_tx_desc; i++) {
1875                         rte_pktmbuf_free_seg(swr[i].mbuf);
1876                         swr[i].mbuf = NULL;
1877                 }
1878                 i = 0;
1879         }
1880 }
1881
1882 static const struct iavf_txq_ops avx512_vec_txq_ops = {
1883         .release_mbufs = iavf_tx_queue_release_mbufs_avx512,
1884 };
1885
1886 int __rte_cold
1887 iavf_txq_vec_setup_avx512(struct iavf_tx_queue *txq)
1888 {
1889         txq->ops = &avx512_vec_txq_ops;
1890         return 0;
1891 }
1892
1893 uint16_t
1894 iavf_xmit_pkts_vec_avx512_offload(void *tx_queue, struct rte_mbuf **tx_pkts,
1895                                   uint16_t nb_pkts)
1896 {
1897         return iavf_xmit_pkts_vec_avx512_cmn(tx_queue, tx_pkts, nb_pkts, true);
1898 }