1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2020 Intel Corporation
5 #include "iavf_rxtx_vec_common.h"
9 #ifndef __INTEL_COMPILER
10 #pragma GCC diagnostic ignored "-Wcast-qual"
13 #define IAVF_DESCS_PER_LOOP_AVX 8
14 #define PKTLEN_SHIFT 10
16 /******************************************************************************
17 * If user knows a specific offload is not enabled by APP,
18 * the macro can be commented to save the effort of fast path.
19 * Currently below 2 features are supported in RX path,
21 * 2, VLAN/QINQ stripping
23 * 4, packet type analysis
24 * 5, flow director ID report
25 ******************************************************************************/
26 #define IAVF_RX_CSUM_OFFLOAD
27 #define IAVF_RX_VLAN_OFFLOAD
28 #define IAVF_RX_RSS_OFFLOAD
29 #define IAVF_RX_PTYPE_OFFLOAD
30 #define IAVF_RX_FDIR_OFFLOAD
32 static __rte_always_inline void
33 iavf_rxq_rearm(struct iavf_rx_queue *rxq)
37 volatile union iavf_rx_desc *rxdp;
38 struct rte_mempool_cache *cache =
39 rte_mempool_default_cache(rxq->mp, rte_lcore_id());
40 struct rte_mbuf **rxp = &rxq->sw_ring[rxq->rxrearm_start];
42 rxdp = rxq->rx_ring + rxq->rxrearm_start;
45 return iavf_rxq_rearm_common(rxq, true);
47 /* We need to pull 'n' more MBUFs into the software ring from mempool
48 * We inline the mempool function here, so we can vectorize the copy
49 * from the cache into the shadow ring.
52 /* Can this be satisfied from the cache? */
53 if (cache->len < IAVF_RXQ_REARM_THRESH) {
54 /* No. Backfill the cache first, and then fill from it */
55 uint32_t req = IAVF_RXQ_REARM_THRESH + (cache->size -
58 /* How many do we require i.e. number to fill the cache + the request */
59 int ret = rte_mempool_ops_dequeue_bulk
60 (rxq->mp, &cache->objs[cache->len], req);
64 if (rxq->rxrearm_nb + IAVF_RXQ_REARM_THRESH >=
68 dma_addr0 = _mm_setzero_si128();
69 for (i = 0; i < IAVF_VPMD_DESCS_PER_LOOP; i++) {
70 rxp[i] = &rxq->fake_mbuf;
71 _mm_storeu_si128((__m128i *)&rxdp[i].read,
75 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed +=
76 IAVF_RXQ_REARM_THRESH;
81 const __m512i iova_offsets = _mm512_set1_epi64(offsetof
82 (struct rte_mbuf, buf_iova));
83 const __m512i headroom = _mm512_set1_epi64(RTE_PKTMBUF_HEADROOM);
85 #ifndef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
86 /* to shuffle the addresses to correct slots. Values 4-7 will contain
87 * zeros, so use 7 for a zero-value.
89 const __m512i permute_idx = _mm512_set_epi64(7, 7, 3, 1, 7, 7, 2, 0);
91 const __m512i permute_idx = _mm512_set_epi64(7, 3, 6, 2, 5, 1, 4, 0);
94 /* Initialize the mbufs in vector, process 8 mbufs in one loop, taking
95 * from mempool cache and populating both shadow and HW rings
97 for (i = 0; i < IAVF_RXQ_REARM_THRESH / IAVF_DESCS_PER_LOOP_AVX; i++) {
98 const __m512i mbuf_ptrs = _mm512_loadu_si512
99 (&cache->objs[cache->len - IAVF_DESCS_PER_LOOP_AVX]);
100 _mm512_storeu_si512(rxp, mbuf_ptrs);
102 const __m512i iova_base_addrs = _mm512_i64gather_epi64
103 (_mm512_add_epi64(mbuf_ptrs, iova_offsets),
106 const __m512i iova_addrs = _mm512_add_epi64(iova_base_addrs,
108 #ifndef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
109 const __m512i iovas0 = _mm512_castsi256_si512
110 (_mm512_extracti64x4_epi64(iova_addrs, 0));
111 const __m512i iovas1 = _mm512_castsi256_si512
112 (_mm512_extracti64x4_epi64(iova_addrs, 1));
114 /* permute leaves desc 2-3 addresses in header address slots 0-1
115 * but these are ignored by driver since header split not
116 * enabled. Similarly for desc 6 & 7.
118 const __m512i desc0_1 = _mm512_permutexvar_epi64
121 const __m512i desc2_3 = _mm512_bsrli_epi128(desc0_1, 8);
123 const __m512i desc4_5 = _mm512_permutexvar_epi64
126 const __m512i desc6_7 = _mm512_bsrli_epi128(desc4_5, 8);
128 _mm512_storeu_si512((void *)rxdp, desc0_1);
129 _mm512_storeu_si512((void *)(rxdp + 2), desc2_3);
130 _mm512_storeu_si512((void *)(rxdp + 4), desc4_5);
131 _mm512_storeu_si512((void *)(rxdp + 6), desc6_7);
133 /* permute leaves desc 4-7 addresses in header address slots 0-3
134 * but these are ignored by driver since header split not
137 const __m512i desc0_3 = _mm512_permutexvar_epi64(permute_idx,
139 const __m512i desc4_7 = _mm512_bsrli_epi128(desc0_3, 8);
141 _mm512_storeu_si512((void *)rxdp, desc0_3);
142 _mm512_storeu_si512((void *)(rxdp + 4), desc4_7);
144 rxp += IAVF_DESCS_PER_LOOP_AVX;
145 rxdp += IAVF_DESCS_PER_LOOP_AVX;
146 cache->len -= IAVF_DESCS_PER_LOOP_AVX;
149 rxq->rxrearm_start += IAVF_RXQ_REARM_THRESH;
150 if (rxq->rxrearm_start >= rxq->nb_rx_desc)
151 rxq->rxrearm_start = 0;
153 rxq->rxrearm_nb -= IAVF_RXQ_REARM_THRESH;
155 rx_id = (uint16_t)((rxq->rxrearm_start == 0) ?
156 (rxq->nb_rx_desc - 1) : (rxq->rxrearm_start - 1));
158 /* Update the tail pointer on the NIC */
159 IAVF_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
162 #define IAVF_RX_LEN_MASK 0x80808080
163 static __rte_always_inline uint16_t
164 _iavf_recv_raw_pkts_vec_avx512(struct iavf_rx_queue *rxq,
165 struct rte_mbuf **rx_pkts,
166 uint16_t nb_pkts, uint8_t *split_packet,
169 #ifdef IAVF_RX_PTYPE_OFFLOAD
170 const uint32_t *type_table = rxq->vsi->adapter->ptype_tbl;
173 const __m256i mbuf_init = _mm256_set_epi64x(0, 0, 0,
174 rxq->mbuf_initializer);
175 struct rte_mbuf **sw_ring = &rxq->sw_ring[rxq->rx_tail];
176 volatile union iavf_rx_desc *rxdp = rxq->rx_ring + rxq->rx_tail;
180 /* nb_pkts has to be floor-aligned to IAVF_DESCS_PER_LOOP_AVX */
181 nb_pkts = RTE_ALIGN_FLOOR(nb_pkts, IAVF_DESCS_PER_LOOP_AVX);
183 /* See if we need to rearm the RX queue - gives the prefetch a bit
186 if (rxq->rxrearm_nb > IAVF_RXQ_REARM_THRESH)
189 /* Before we start moving massive data around, check to see if
190 * there is actually a packet available
192 if (!(rxdp->wb.qword1.status_error_len &
193 rte_cpu_to_le_32(1 << IAVF_RX_DESC_STATUS_DD_SHIFT)))
196 /* constants used in processing loop */
197 const __m512i crc_adjust =
199 (/* 1st descriptor */
200 0, /* ignore non-length fields */
201 -rxq->crc_len, /* sub crc on data_len */
202 -rxq->crc_len, /* sub crc on pkt_len */
203 0, /* ignore pkt_type field */
205 0, /* ignore non-length fields */
206 -rxq->crc_len, /* sub crc on data_len */
207 -rxq->crc_len, /* sub crc on pkt_len */
208 0, /* ignore pkt_type field */
210 0, /* ignore non-length fields */
211 -rxq->crc_len, /* sub crc on data_len */
212 -rxq->crc_len, /* sub crc on pkt_len */
213 0, /* ignore pkt_type field */
215 0, /* ignore non-length fields */
216 -rxq->crc_len, /* sub crc on data_len */
217 -rxq->crc_len, /* sub crc on pkt_len */
218 0 /* ignore pkt_type field */
221 /* 8 packets DD mask, LSB in each 32-bit value */
222 const __m256i dd_check = _mm256_set1_epi32(1);
224 /* 8 packets EOP mask, second-LSB in each 32-bit value */
225 const __m256i eop_check = _mm256_slli_epi32(dd_check,
226 IAVF_RX_DESC_STATUS_EOF_SHIFT);
228 /* mask to shuffle from desc. to mbuf (4 descriptors)*/
229 const __m512i shuf_msk =
231 (/* 1st descriptor */
232 0x07060504, /* octet 4~7, 32bits rss */
233 0x03020F0E, /* octet 2~3, low 16 bits vlan_macip */
234 /* octet 15~14, 16 bits data_len */
235 0xFFFF0F0E, /* skip high 16 bits pkt_len, zero out */
236 /* octet 15~14, low 16 bits pkt_len */
237 0xFFFFFFFF, /* pkt_type set as unknown */
239 0x07060504, /* octet 4~7, 32bits rss */
240 0x03020F0E, /* octet 2~3, low 16 bits vlan_macip */
241 /* octet 15~14, 16 bits data_len */
242 0xFFFF0F0E, /* skip high 16 bits pkt_len, zero out */
243 /* octet 15~14, low 16 bits pkt_len */
244 0xFFFFFFFF, /* pkt_type set as unknown */
246 0x07060504, /* octet 4~7, 32bits rss */
247 0x03020F0E, /* octet 2~3, low 16 bits vlan_macip */
248 /* octet 15~14, 16 bits data_len */
249 0xFFFF0F0E, /* skip high 16 bits pkt_len, zero out */
250 /* octet 15~14, low 16 bits pkt_len */
251 0xFFFFFFFF, /* pkt_type set as unknown */
253 0x07060504, /* octet 4~7, 32bits rss */
254 0x03020F0E, /* octet 2~3, low 16 bits vlan_macip */
255 /* octet 15~14, 16 bits data_len */
256 0xFFFF0F0E, /* skip high 16 bits pkt_len, zero out */
257 /* octet 15~14, low 16 bits pkt_len */
258 0xFFFFFFFF /* pkt_type set as unknown */
261 * compile-time check the above crc and shuffle layout is correct.
262 * NOTE: the first field (lowest address) is given last in set_epi
265 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, pkt_len) !=
266 offsetof(struct rte_mbuf, rx_descriptor_fields1) + 4);
267 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, data_len) !=
268 offsetof(struct rte_mbuf, rx_descriptor_fields1) + 8);
269 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, vlan_tci) !=
270 offsetof(struct rte_mbuf, rx_descriptor_fields1) + 10);
271 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, hash) !=
272 offsetof(struct rte_mbuf, rx_descriptor_fields1) + 12);
274 uint16_t i, received;
276 for (i = 0, received = 0; i < nb_pkts;
277 i += IAVF_DESCS_PER_LOOP_AVX,
278 rxdp += IAVF_DESCS_PER_LOOP_AVX) {
279 /* step 1, copy over 8 mbuf pointers to rx_pkts array */
280 _mm256_storeu_si256((void *)&rx_pkts[i],
281 _mm256_loadu_si256((void *)&sw_ring[i]));
282 #ifdef RTE_ARCH_X86_64
284 ((void *)&rx_pkts[i + 4],
285 _mm256_loadu_si256((void *)&sw_ring[i + 4]));
288 __m512i raw_desc0_3, raw_desc4_7;
289 const __m128i raw_desc7 =
290 _mm_load_si128((void *)(rxdp + 7));
291 rte_compiler_barrier();
292 const __m128i raw_desc6 =
293 _mm_load_si128((void *)(rxdp + 6));
294 rte_compiler_barrier();
295 const __m128i raw_desc5 =
296 _mm_load_si128((void *)(rxdp + 5));
297 rte_compiler_barrier();
298 const __m128i raw_desc4 =
299 _mm_load_si128((void *)(rxdp + 4));
300 rte_compiler_barrier();
301 const __m128i raw_desc3 =
302 _mm_load_si128((void *)(rxdp + 3));
303 rte_compiler_barrier();
304 const __m128i raw_desc2 =
305 _mm_load_si128((void *)(rxdp + 2));
306 rte_compiler_barrier();
307 const __m128i raw_desc1 =
308 _mm_load_si128((void *)(rxdp + 1));
309 rte_compiler_barrier();
310 const __m128i raw_desc0 =
311 _mm_load_si128((void *)(rxdp + 0));
313 raw_desc4_7 = _mm512_broadcast_i32x4(raw_desc4);
314 raw_desc4_7 = _mm512_inserti32x4(raw_desc4_7, raw_desc5, 1);
315 raw_desc4_7 = _mm512_inserti32x4(raw_desc4_7, raw_desc6, 2);
316 raw_desc4_7 = _mm512_inserti32x4(raw_desc4_7, raw_desc7, 3);
317 raw_desc0_3 = _mm512_broadcast_i32x4(raw_desc0);
318 raw_desc0_3 = _mm512_inserti32x4(raw_desc0_3, raw_desc1, 1);
319 raw_desc0_3 = _mm512_inserti32x4(raw_desc0_3, raw_desc2, 2);
320 raw_desc0_3 = _mm512_inserti32x4(raw_desc0_3, raw_desc3, 3);
325 for (j = 0; j < IAVF_DESCS_PER_LOOP_AVX; j++)
326 rte_mbuf_prefetch_part2(rx_pkts[i + j]);
330 * convert descriptors 4-7 into mbufs, adjusting length and
331 * re-arranging fields. Then write into the mbuf
333 const __m512i len4_7 = _mm512_slli_epi32(raw_desc4_7,
335 const __m512i desc4_7 = _mm512_mask_blend_epi16(IAVF_RX_LEN_MASK,
338 __m512i mb4_7 = _mm512_shuffle_epi8(desc4_7, shuf_msk);
340 mb4_7 = _mm512_add_epi32(mb4_7, crc_adjust);
341 #ifdef IAVF_RX_PTYPE_OFFLOAD
343 * to get packet types, shift 64-bit values down 30 bits
344 * and so ptype is in lower 8-bits in each
346 const __m512i ptypes4_7 = _mm512_srli_epi64(desc4_7, 30);
347 const __m256i ptypes6_7 = _mm512_extracti64x4_epi64(ptypes4_7, 1);
348 const __m256i ptypes4_5 = _mm512_extracti64x4_epi64(ptypes4_7, 0);
349 const uint8_t ptype7 = _mm256_extract_epi8(ptypes6_7, 24);
350 const uint8_t ptype6 = _mm256_extract_epi8(ptypes6_7, 8);
351 const uint8_t ptype5 = _mm256_extract_epi8(ptypes4_5, 24);
352 const uint8_t ptype4 = _mm256_extract_epi8(ptypes4_5, 8);
354 const __m512i ptype4_7 = _mm512_set_epi32
355 (0, 0, 0, type_table[ptype7],
356 0, 0, 0, type_table[ptype6],
357 0, 0, 0, type_table[ptype5],
358 0, 0, 0, type_table[ptype4]);
359 mb4_7 = _mm512_mask_blend_epi32(0x1111, mb4_7, ptype4_7);
363 * convert descriptors 0-3 into mbufs, adjusting length and
364 * re-arranging fields. Then write into the mbuf
366 const __m512i len0_3 = _mm512_slli_epi32(raw_desc0_3,
368 const __m512i desc0_3 = _mm512_mask_blend_epi16(IAVF_RX_LEN_MASK,
371 __m512i mb0_3 = _mm512_shuffle_epi8(desc0_3, shuf_msk);
373 mb0_3 = _mm512_add_epi32(mb0_3, crc_adjust);
374 #ifdef IAVF_RX_PTYPE_OFFLOAD
375 /* get the packet types */
376 const __m512i ptypes0_3 = _mm512_srli_epi64(desc0_3, 30);
377 const __m256i ptypes2_3 = _mm512_extracti64x4_epi64(ptypes0_3, 1);
378 const __m256i ptypes0_1 = _mm512_extracti64x4_epi64(ptypes0_3, 0);
379 const uint8_t ptype3 = _mm256_extract_epi8(ptypes2_3, 24);
380 const uint8_t ptype2 = _mm256_extract_epi8(ptypes2_3, 8);
381 const uint8_t ptype1 = _mm256_extract_epi8(ptypes0_1, 24);
382 const uint8_t ptype0 = _mm256_extract_epi8(ptypes0_1, 8);
384 const __m512i ptype0_3 = _mm512_set_epi32
385 (0, 0, 0, type_table[ptype3],
386 0, 0, 0, type_table[ptype2],
387 0, 0, 0, type_table[ptype1],
388 0, 0, 0, type_table[ptype0]);
389 mb0_3 = _mm512_mask_blend_epi32(0x1111, mb0_3, ptype0_3);
393 * use permute/extract to get status content
394 * After the operations, the packets status flags are in the
395 * order (hi->lo): [1, 3, 5, 7, 0, 2, 4, 6]
397 /* merge the status bits into one register */
398 const __m512i status_permute_msk = _mm512_set_epi32
403 const __m512i raw_status0_7 = _mm512_permutex2var_epi32
404 (raw_desc4_7, status_permute_msk, raw_desc0_3);
405 __m256i status0_7 = _mm512_extracti64x4_epi64
408 /* now do flag manipulation */
411 __m256i mbuf_flags = _mm256_set1_epi32(0);
414 #if defined(IAVF_RX_CSUM_OFFLOAD) || defined(IAVF_RX_VLAN_OFFLOAD) || defined(IAVF_RX_RSS_OFFLOAD)
415 /* Status/Error flag masks */
417 * mask everything except RSS, flow director and VLAN flags
418 * bit2 is for VLAN tag, bit11 for flow director indication
419 * bit13:12 for RSS indication. Bits 3-5 of error
420 * field (bits 22-24) are for IP/L4 checksum errors
422 const __m256i flags_mask =
423 _mm256_set1_epi32((1 << 2) | (1 << 11) |
424 (3 << 12) | (7 << 22));
427 #ifdef IAVF_RX_VLAN_OFFLOAD
429 * data to be shuffled by result of flag mask. If VLAN bit is set,
430 * (bit 2), then position 4 in this array will be used in the
433 const __m256i vlan_flags_shuf =
434 _mm256_set_epi32(0, 0, PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED, 0,
435 0, 0, PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED, 0);
438 #ifdef IAVF_RX_RSS_OFFLOAD
440 * data to be shuffled by result of flag mask, shifted down 11.
441 * If RSS/FDIR bits are set, shuffle moves appropriate flags in
444 const __m256i rss_flags_shuf =
445 _mm256_set_epi8(0, 0, 0, 0, 0, 0, 0, 0,
446 PKT_RX_RSS_HASH | PKT_RX_FDIR, PKT_RX_RSS_HASH,
447 0, 0, 0, 0, PKT_RX_FDIR, 0,/* end up 128-bits */
448 0, 0, 0, 0, 0, 0, 0, 0,
449 PKT_RX_RSS_HASH | PKT_RX_FDIR, PKT_RX_RSS_HASH,
450 0, 0, 0, 0, PKT_RX_FDIR, 0);
453 #ifdef IAVF_RX_CSUM_OFFLOAD
455 * data to be shuffled by the result of the flags mask shifted by 22
456 * bits. This gives use the l3_l4 flags.
458 const __m256i l3_l4_flags_shuf = _mm256_set_epi8(0, 0, 0, 0, 0, 0, 0, 0,
459 /* shift right 1 bit to make sure it not exceed 255 */
460 (PKT_RX_OUTER_IP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD |
461 PKT_RX_IP_CKSUM_BAD) >> 1,
462 (PKT_RX_IP_CKSUM_GOOD | PKT_RX_OUTER_IP_CKSUM_BAD |
463 PKT_RX_L4_CKSUM_BAD) >> 1,
464 (PKT_RX_OUTER_IP_CKSUM_BAD | PKT_RX_IP_CKSUM_BAD) >> 1,
465 (PKT_RX_IP_CKSUM_GOOD | PKT_RX_OUTER_IP_CKSUM_BAD) >> 1,
466 (PKT_RX_L4_CKSUM_BAD | PKT_RX_IP_CKSUM_BAD) >> 1,
467 (PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_BAD) >> 1,
468 PKT_RX_IP_CKSUM_BAD >> 1,
469 (PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD) >> 1,
470 /* second 128-bits */
471 0, 0, 0, 0, 0, 0, 0, 0,
472 (PKT_RX_OUTER_IP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD |
473 PKT_RX_IP_CKSUM_BAD) >> 1,
474 (PKT_RX_IP_CKSUM_GOOD | PKT_RX_OUTER_IP_CKSUM_BAD |
475 PKT_RX_L4_CKSUM_BAD) >> 1,
476 (PKT_RX_OUTER_IP_CKSUM_BAD | PKT_RX_IP_CKSUM_BAD) >> 1,
477 (PKT_RX_IP_CKSUM_GOOD | PKT_RX_OUTER_IP_CKSUM_BAD) >> 1,
478 (PKT_RX_L4_CKSUM_BAD | PKT_RX_IP_CKSUM_BAD) >> 1,
479 (PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_BAD) >> 1,
480 PKT_RX_IP_CKSUM_BAD >> 1,
481 (PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD) >> 1);
483 const __m256i cksum_mask =
484 _mm256_set1_epi32(PKT_RX_IP_CKSUM_GOOD | PKT_RX_IP_CKSUM_BAD |
485 PKT_RX_L4_CKSUM_GOOD | PKT_RX_L4_CKSUM_BAD |
486 PKT_RX_OUTER_IP_CKSUM_BAD);
489 #if defined(IAVF_RX_CSUM_OFFLOAD) || defined(IAVF_RX_VLAN_OFFLOAD) || defined(IAVF_RX_RSS_OFFLOAD)
490 /* get only flag/error bits we want */
491 const __m256i flag_bits =
492 _mm256_and_si256(status0_7, flags_mask);
494 /* set vlan and rss flags */
495 #ifdef IAVF_RX_VLAN_OFFLOAD
496 const __m256i vlan_flags =
497 _mm256_shuffle_epi8(vlan_flags_shuf, flag_bits);
499 #ifdef IAVF_RX_RSS_OFFLOAD
500 const __m256i rss_flags =
501 _mm256_shuffle_epi8(rss_flags_shuf,
502 _mm256_srli_epi32(flag_bits, 11));
504 #ifdef IAVF_RX_CSUM_OFFLOAD
506 * l3_l4_error flags, shuffle, then shift to correct adjustment
507 * of flags in flags_shuf, and finally mask out extra bits
509 __m256i l3_l4_flags = _mm256_shuffle_epi8(l3_l4_flags_shuf,
510 _mm256_srli_epi32(flag_bits, 22));
511 l3_l4_flags = _mm256_slli_epi32(l3_l4_flags, 1);
512 l3_l4_flags = _mm256_and_si256(l3_l4_flags, cksum_mask);
515 #ifdef IAVF_RX_CSUM_OFFLOAD
516 mbuf_flags = _mm256_or_si256(mbuf_flags, l3_l4_flags);
518 #ifdef IAVF_RX_RSS_OFFLOAD
519 mbuf_flags = _mm256_or_si256(mbuf_flags, rss_flags);
521 #ifdef IAVF_RX_VLAN_OFFLOAD
522 mbuf_flags = _mm256_or_si256(mbuf_flags, vlan_flags);
527 * At this point, we have the 8 sets of flags in the low 16-bits
528 * of each 32-bit value in vlan0.
529 * We want to extract these, and merge them with the mbuf init
530 * data so we can do a single write to the mbuf to set the flags
531 * and all the other initialization fields. Extracting the
532 * appropriate flags means that we have to do a shift and blend
533 * for each mbuf before we do the write. However, we can also
534 * add in the previously computed rx_descriptor fields to
535 * make a single 256-bit write per mbuf
537 /* check the structure matches expectations */
538 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, ol_flags) !=
539 offsetof(struct rte_mbuf, rearm_data) + 8);
540 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, rearm_data) !=
541 RTE_ALIGN(offsetof(struct rte_mbuf,
544 /* build up data and do writes */
545 __m256i rearm0, rearm1, rearm2, rearm3, rearm4, rearm5,
547 const __m256i mb4_5 = _mm512_extracti64x4_epi64(mb4_7, 0);
548 const __m256i mb6_7 = _mm512_extracti64x4_epi64(mb4_7, 1);
549 const __m256i mb0_1 = _mm512_extracti64x4_epi64(mb0_3, 0);
550 const __m256i mb2_3 = _mm512_extracti64x4_epi64(mb0_3, 1);
553 rearm6 = _mm256_blend_epi32(mbuf_init,
554 _mm256_slli_si256(mbuf_flags, 8),
556 rearm4 = _mm256_blend_epi32(mbuf_init,
557 _mm256_slli_si256(mbuf_flags, 4),
559 rearm2 = _mm256_blend_epi32(mbuf_init, mbuf_flags, 0x04);
560 rearm0 = _mm256_blend_epi32(mbuf_init,
561 _mm256_srli_si256(mbuf_flags, 4),
563 /* permute to add in the rx_descriptor e.g. rss fields */
564 rearm6 = _mm256_permute2f128_si256(rearm6, mb6_7, 0x20);
565 rearm4 = _mm256_permute2f128_si256(rearm4, mb4_5, 0x20);
566 rearm2 = _mm256_permute2f128_si256(rearm2, mb2_3, 0x20);
567 rearm0 = _mm256_permute2f128_si256(rearm0, mb0_1, 0x20);
569 rearm6 = _mm256_permute2f128_si256(mbuf_init, mb6_7, 0x20);
570 rearm4 = _mm256_permute2f128_si256(mbuf_init, mb4_5, 0x20);
571 rearm2 = _mm256_permute2f128_si256(mbuf_init, mb2_3, 0x20);
572 rearm0 = _mm256_permute2f128_si256(mbuf_init, mb0_1, 0x20);
575 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 6]->rearm_data,
577 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 4]->rearm_data,
579 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 2]->rearm_data,
581 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 0]->rearm_data,
584 /* repeat for the odd mbufs */
586 const __m256i odd_flags =
587 _mm256_castsi128_si256
588 (_mm256_extracti128_si256(mbuf_flags, 1));
589 rearm7 = _mm256_blend_epi32(mbuf_init,
590 _mm256_slli_si256(odd_flags, 8),
592 rearm5 = _mm256_blend_epi32(mbuf_init,
593 _mm256_slli_si256(odd_flags, 4),
595 rearm3 = _mm256_blend_epi32(mbuf_init, odd_flags, 0x04);
596 rearm1 = _mm256_blend_epi32(mbuf_init,
597 _mm256_srli_si256(odd_flags, 4),
599 /* since odd mbufs are already in hi 128-bits use blend */
600 rearm7 = _mm256_blend_epi32(rearm7, mb6_7, 0xF0);
601 rearm5 = _mm256_blend_epi32(rearm5, mb4_5, 0xF0);
602 rearm3 = _mm256_blend_epi32(rearm3, mb2_3, 0xF0);
603 rearm1 = _mm256_blend_epi32(rearm1, mb0_1, 0xF0);
605 rearm7 = _mm256_blend_epi32(mbuf_init, mb6_7, 0xF0);
606 rearm5 = _mm256_blend_epi32(mbuf_init, mb4_5, 0xF0);
607 rearm3 = _mm256_blend_epi32(mbuf_init, mb2_3, 0xF0);
608 rearm1 = _mm256_blend_epi32(mbuf_init, mb0_1, 0xF0);
610 /* again write to mbufs */
611 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 7]->rearm_data,
613 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 5]->rearm_data,
615 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 3]->rearm_data,
617 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 1]->rearm_data,
620 /* extract and record EOP bit */
622 const __m128i eop_mask =
623 _mm_set1_epi16(1 << IAVF_RX_DESC_STATUS_EOF_SHIFT);
624 const __m256i eop_bits256 = _mm256_and_si256(status0_7,
626 /* pack status bits into a single 128-bit register */
627 const __m128i eop_bits =
629 (_mm256_castsi256_si128(eop_bits256),
630 _mm256_extractf128_si256(eop_bits256,
633 * flip bits, and mask out the EOP bit, which is now
634 * a split-packet bit i.e. !EOP, rather than EOP one.
636 __m128i split_bits = _mm_andnot_si128(eop_bits,
639 * eop bits are out of order, so we need to shuffle them
640 * back into order again. In doing so, only use low 8
641 * bits, which acts like another pack instruction
642 * The original order is (hi->lo): 1,3,5,7,0,2,4,6
643 * [Since we use epi8, the 16-bit positions are
644 * multiplied by 2 in the eop_shuffle value.]
646 __m128i eop_shuffle =
647 _mm_set_epi8(/* zero hi 64b */
648 0xFF, 0xFF, 0xFF, 0xFF,
649 0xFF, 0xFF, 0xFF, 0xFF,
650 /* move values to lo 64b */
653 split_bits = _mm_shuffle_epi8(split_bits, eop_shuffle);
654 *(uint64_t *)split_packet =
655 _mm_cvtsi128_si64(split_bits);
656 split_packet += IAVF_DESCS_PER_LOOP_AVX;
659 /* perform dd_check */
660 status0_7 = _mm256_and_si256(status0_7, dd_check);
661 status0_7 = _mm256_packs_epi32(status0_7,
662 _mm256_setzero_si256());
664 uint64_t burst = __builtin_popcountll
666 (_mm256_extracti128_si256
668 burst += __builtin_popcountll
670 (_mm256_castsi256_si128(status0_7)));
672 if (burst != IAVF_DESCS_PER_LOOP_AVX)
676 /* update tail pointers */
677 rxq->rx_tail += received;
678 rxq->rx_tail &= (rxq->nb_rx_desc - 1);
679 if ((rxq->rx_tail & 1) == 1 && received > 1) { /* keep aligned */
683 rxq->rxrearm_nb += received;
687 static __rte_always_inline __m256i
688 flex_rxd_to_fdir_flags_vec_avx512(const __m256i fdir_id0_7)
690 #define FDID_MIS_MAGIC 0xFFFFFFFF
691 RTE_BUILD_BUG_ON(PKT_RX_FDIR != (1 << 2));
692 RTE_BUILD_BUG_ON(PKT_RX_FDIR_ID != (1 << 13));
693 const __m256i pkt_fdir_bit = _mm256_set1_epi32(PKT_RX_FDIR |
695 /* desc->flow_id field == 0xFFFFFFFF means fdir mismatch */
696 const __m256i fdir_mis_mask = _mm256_set1_epi32(FDID_MIS_MAGIC);
697 __m256i fdir_mask = _mm256_cmpeq_epi32(fdir_id0_7,
699 /* this XOR op results to bit-reverse the fdir_mask */
700 fdir_mask = _mm256_xor_si256(fdir_mask, fdir_mis_mask);
701 const __m256i fdir_flags = _mm256_and_si256(fdir_mask, pkt_fdir_bit);
706 static __rte_always_inline uint16_t
707 _iavf_recv_raw_pkts_vec_avx512_flex_rxd(struct iavf_rx_queue *rxq,
708 struct rte_mbuf **rx_pkts,
710 uint8_t *split_packet,
713 #ifdef IAVF_RX_PTYPE_OFFLOAD
714 const uint32_t *type_table = rxq->vsi->adapter->ptype_tbl;
717 const __m256i mbuf_init = _mm256_set_epi64x(0, 0, 0,
718 rxq->mbuf_initializer);
719 struct rte_mbuf **sw_ring = &rxq->sw_ring[rxq->rx_tail];
720 volatile union iavf_rx_flex_desc *rxdp =
721 (union iavf_rx_flex_desc *)rxq->rx_ring + rxq->rx_tail;
725 /* nb_pkts has to be floor-aligned to IAVF_DESCS_PER_LOOP_AVX */
726 nb_pkts = RTE_ALIGN_FLOOR(nb_pkts, IAVF_DESCS_PER_LOOP_AVX);
728 /* See if we need to rearm the RX queue - gives the prefetch a bit
731 if (rxq->rxrearm_nb > IAVF_RXQ_REARM_THRESH)
734 /* Before we start moving massive data around, check to see if
735 * there is actually a packet available
737 if (!(rxdp->wb.status_error0 &
738 rte_cpu_to_le_32(1 << IAVF_RX_FLEX_DESC_STATUS0_DD_S)))
741 /* constants used in processing loop */
742 const __m512i crc_adjust =
744 (/* 1st descriptor */
745 0, /* ignore non-length fields */
746 -rxq->crc_len, /* sub crc on data_len */
747 -rxq->crc_len, /* sub crc on pkt_len */
748 0, /* ignore pkt_type field */
750 0, /* ignore non-length fields */
751 -rxq->crc_len, /* sub crc on data_len */
752 -rxq->crc_len, /* sub crc on pkt_len */
753 0, /* ignore pkt_type field */
755 0, /* ignore non-length fields */
756 -rxq->crc_len, /* sub crc on data_len */
757 -rxq->crc_len, /* sub crc on pkt_len */
758 0, /* ignore pkt_type field */
760 0, /* ignore non-length fields */
761 -rxq->crc_len, /* sub crc on data_len */
762 -rxq->crc_len, /* sub crc on pkt_len */
763 0 /* ignore pkt_type field */
766 /* 8 packets DD mask, LSB in each 32-bit value */
767 const __m256i dd_check = _mm256_set1_epi32(1);
769 /* 8 packets EOP mask, second-LSB in each 32-bit value */
770 const __m256i eop_check = _mm256_slli_epi32(dd_check,
771 IAVF_RX_FLEX_DESC_STATUS0_EOF_S);
773 /* mask to shuffle from desc. to mbuf (4 descriptors)*/
774 const __m512i shuf_msk =
776 (/* 1st descriptor */
777 0xFFFFFFFF, /* rss hash parsed separately */
778 0x0B0A0504, /* octet 10~11, 16 bits vlan_macip */
779 /* octet 4~5, 16 bits data_len */
780 0xFFFF0504, /* skip hi 16 bits pkt_len, zero out */
781 /* octet 4~5, 16 bits pkt_len */
782 0xFFFFFFFF, /* pkt_type set as unknown */
784 0xFFFFFFFF, /* rss hash parsed separately */
785 0x0B0A0504, /* octet 10~11, 16 bits vlan_macip */
786 /* octet 4~5, 16 bits data_len */
787 0xFFFF0504, /* skip hi 16 bits pkt_len, zero out */
788 /* octet 4~5, 16 bits pkt_len */
789 0xFFFFFFFF, /* pkt_type set as unknown */
791 0xFFFFFFFF, /* rss hash parsed separately */
792 0x0B0A0504, /* octet 10~11, 16 bits vlan_macip */
793 /* octet 4~5, 16 bits data_len */
794 0xFFFF0504, /* skip hi 16 bits pkt_len, zero out */
795 /* octet 4~5, 16 bits pkt_len */
796 0xFFFFFFFF, /* pkt_type set as unknown */
798 0xFFFFFFFF, /* rss hash parsed separately */
799 0x0B0A0504, /* octet 10~11, 16 bits vlan_macip */
800 /* octet 4~5, 16 bits data_len */
801 0xFFFF0504, /* skip hi 16 bits pkt_len, zero out */
802 /* octet 4~5, 16 bits pkt_len */
803 0xFFFFFFFF /* pkt_type set as unknown */
806 * compile-time check the above crc and shuffle layout is correct.
807 * NOTE: the first field (lowest address) is given last in set_epi
810 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, pkt_len) !=
811 offsetof(struct rte_mbuf, rx_descriptor_fields1) + 4);
812 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, data_len) !=
813 offsetof(struct rte_mbuf, rx_descriptor_fields1) + 8);
814 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, vlan_tci) !=
815 offsetof(struct rte_mbuf, rx_descriptor_fields1) + 10);
816 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, hash) !=
817 offsetof(struct rte_mbuf, rx_descriptor_fields1) + 12);
819 uint16_t i, received;
821 for (i = 0, received = 0; i < nb_pkts;
822 i += IAVF_DESCS_PER_LOOP_AVX,
823 rxdp += IAVF_DESCS_PER_LOOP_AVX) {
824 /* step 1, copy over 8 mbuf pointers to rx_pkts array */
825 _mm256_storeu_si256((void *)&rx_pkts[i],
826 _mm256_loadu_si256((void *)&sw_ring[i]));
827 #ifdef RTE_ARCH_X86_64
829 ((void *)&rx_pkts[i + 4],
830 _mm256_loadu_si256((void *)&sw_ring[i + 4]));
833 __m512i raw_desc0_3, raw_desc4_7;
835 const __m128i raw_desc7 =
836 _mm_load_si128((void *)(rxdp + 7));
837 rte_compiler_barrier();
838 const __m128i raw_desc6 =
839 _mm_load_si128((void *)(rxdp + 6));
840 rte_compiler_barrier();
841 const __m128i raw_desc5 =
842 _mm_load_si128((void *)(rxdp + 5));
843 rte_compiler_barrier();
844 const __m128i raw_desc4 =
845 _mm_load_si128((void *)(rxdp + 4));
846 rte_compiler_barrier();
847 const __m128i raw_desc3 =
848 _mm_load_si128((void *)(rxdp + 3));
849 rte_compiler_barrier();
850 const __m128i raw_desc2 =
851 _mm_load_si128((void *)(rxdp + 2));
852 rte_compiler_barrier();
853 const __m128i raw_desc1 =
854 _mm_load_si128((void *)(rxdp + 1));
855 rte_compiler_barrier();
856 const __m128i raw_desc0 =
857 _mm_load_si128((void *)(rxdp + 0));
859 raw_desc4_7 = _mm512_broadcast_i32x4(raw_desc4);
860 raw_desc4_7 = _mm512_inserti32x4(raw_desc4_7, raw_desc5, 1);
861 raw_desc4_7 = _mm512_inserti32x4(raw_desc4_7, raw_desc6, 2);
862 raw_desc4_7 = _mm512_inserti32x4(raw_desc4_7, raw_desc7, 3);
863 raw_desc0_3 = _mm512_broadcast_i32x4(raw_desc0);
864 raw_desc0_3 = _mm512_inserti32x4(raw_desc0_3, raw_desc1, 1);
865 raw_desc0_3 = _mm512_inserti32x4(raw_desc0_3, raw_desc2, 2);
866 raw_desc0_3 = _mm512_inserti32x4(raw_desc0_3, raw_desc3, 3);
871 for (j = 0; j < IAVF_DESCS_PER_LOOP_AVX; j++)
872 rte_mbuf_prefetch_part2(rx_pkts[i + j]);
876 * convert descriptors 4-7 into mbufs, re-arrange fields.
877 * Then write into the mbuf.
879 __m512i mb4_7 = _mm512_shuffle_epi8(raw_desc4_7, shuf_msk);
881 mb4_7 = _mm512_add_epi32(mb4_7, crc_adjust);
882 #ifdef IAVF_RX_PTYPE_OFFLOAD
884 * to get packet types, ptype is located in bit16-25
887 const __m512i ptype_mask =
888 _mm512_set1_epi16(IAVF_RX_FLEX_DESC_PTYPE_M);
889 const __m512i ptypes4_7 =
890 _mm512_and_si512(raw_desc4_7, ptype_mask);
891 const __m256i ptypes6_7 = _mm512_extracti64x4_epi64(ptypes4_7, 1);
892 const __m256i ptypes4_5 = _mm512_extracti64x4_epi64(ptypes4_7, 0);
893 const uint16_t ptype7 = _mm256_extract_epi16(ptypes6_7, 9);
894 const uint16_t ptype6 = _mm256_extract_epi16(ptypes6_7, 1);
895 const uint16_t ptype5 = _mm256_extract_epi16(ptypes4_5, 9);
896 const uint16_t ptype4 = _mm256_extract_epi16(ptypes4_5, 1);
898 const __m512i ptype4_7 = _mm512_set_epi32
899 (0, 0, 0, type_table[ptype7],
900 0, 0, 0, type_table[ptype6],
901 0, 0, 0, type_table[ptype5],
902 0, 0, 0, type_table[ptype4]);
903 mb4_7 = _mm512_mask_blend_epi32(0x1111, mb4_7, ptype4_7);
907 * convert descriptors 0-3 into mbufs, re-arrange fields.
908 * Then write into the mbuf.
910 __m512i mb0_3 = _mm512_shuffle_epi8(raw_desc0_3, shuf_msk);
912 mb0_3 = _mm512_add_epi32(mb0_3, crc_adjust);
913 #ifdef IAVF_RX_PTYPE_OFFLOAD
915 * to get packet types, ptype is located in bit16-25
918 const __m512i ptypes0_3 =
919 _mm512_and_si512(raw_desc0_3, ptype_mask);
920 const __m256i ptypes2_3 = _mm512_extracti64x4_epi64(ptypes0_3, 1);
921 const __m256i ptypes0_1 = _mm512_extracti64x4_epi64(ptypes0_3, 0);
922 const uint16_t ptype3 = _mm256_extract_epi16(ptypes2_3, 9);
923 const uint16_t ptype2 = _mm256_extract_epi16(ptypes2_3, 1);
924 const uint16_t ptype1 = _mm256_extract_epi16(ptypes0_1, 9);
925 const uint16_t ptype0 = _mm256_extract_epi16(ptypes0_1, 1);
927 const __m512i ptype0_3 = _mm512_set_epi32
928 (0, 0, 0, type_table[ptype3],
929 0, 0, 0, type_table[ptype2],
930 0, 0, 0, type_table[ptype1],
931 0, 0, 0, type_table[ptype0]);
932 mb0_3 = _mm512_mask_blend_epi32(0x1111, mb0_3, ptype0_3);
936 * use permute/extract to get status content
937 * After the operations, the packets status flags are in the
938 * order (hi->lo): [1, 3, 5, 7, 0, 2, 4, 6]
940 /* merge the status bits into one register */
941 const __m512i status_permute_msk = _mm512_set_epi32
946 const __m512i raw_status0_7 = _mm512_permutex2var_epi32
947 (raw_desc4_7, status_permute_msk, raw_desc0_3);
948 __m256i status0_7 = _mm512_extracti64x4_epi64
951 /* now do flag manipulation */
954 __m256i mbuf_flags = _mm256_set1_epi32(0);
955 __m256i vlan_flags = _mm256_setzero_si256();
958 #if defined(IAVF_RX_CSUM_OFFLOAD) || defined(IAVF_RX_VLAN_OFFLOAD) || defined(IAVF_RX_RSS_OFFLOAD)
959 /* Status/Error flag masks */
961 * mask everything except Checksum Reports, RSS indication
962 * and VLAN indication.
963 * bit6:4 for IP/L4 checksum errors.
964 * bit12 is for RSS indication.
965 * bit13 is for VLAN indication.
967 const __m256i flags_mask =
968 _mm256_set1_epi32((7 << 4) | (1 << 12) | (1 << 13));
970 #ifdef IAVF_RX_CSUM_OFFLOAD
972 * data to be shuffled by the result of the flags mask shifted by 4
973 * bits. This gives use the l3_l4 flags.
975 const __m256i l3_l4_flags_shuf = _mm256_set_epi8(0, 0, 0, 0, 0, 0, 0, 0,
976 /* shift right 1 bit to make sure it not exceed 255 */
977 (PKT_RX_OUTER_IP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD |
978 PKT_RX_IP_CKSUM_BAD) >> 1,
979 (PKT_RX_OUTER_IP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD |
980 PKT_RX_IP_CKSUM_GOOD) >> 1,
981 (PKT_RX_OUTER_IP_CKSUM_BAD | PKT_RX_L4_CKSUM_GOOD |
982 PKT_RX_IP_CKSUM_BAD) >> 1,
983 (PKT_RX_OUTER_IP_CKSUM_BAD | PKT_RX_L4_CKSUM_GOOD |
984 PKT_RX_IP_CKSUM_GOOD) >> 1,
985 (PKT_RX_L4_CKSUM_BAD | PKT_RX_IP_CKSUM_BAD) >> 1,
986 (PKT_RX_L4_CKSUM_BAD | PKT_RX_IP_CKSUM_GOOD) >> 1,
987 (PKT_RX_L4_CKSUM_GOOD | PKT_RX_IP_CKSUM_BAD) >> 1,
988 (PKT_RX_L4_CKSUM_GOOD | PKT_RX_IP_CKSUM_GOOD) >> 1,
989 /* second 128-bits */
990 0, 0, 0, 0, 0, 0, 0, 0,
991 (PKT_RX_OUTER_IP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD |
992 PKT_RX_IP_CKSUM_BAD) >> 1,
993 (PKT_RX_OUTER_IP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD |
994 PKT_RX_IP_CKSUM_GOOD) >> 1,
995 (PKT_RX_OUTER_IP_CKSUM_BAD | PKT_RX_L4_CKSUM_GOOD |
996 PKT_RX_IP_CKSUM_BAD) >> 1,
997 (PKT_RX_OUTER_IP_CKSUM_BAD | PKT_RX_L4_CKSUM_GOOD |
998 PKT_RX_IP_CKSUM_GOOD) >> 1,
999 (PKT_RX_L4_CKSUM_BAD | PKT_RX_IP_CKSUM_BAD) >> 1,
1000 (PKT_RX_L4_CKSUM_BAD | PKT_RX_IP_CKSUM_GOOD) >> 1,
1001 (PKT_RX_L4_CKSUM_GOOD | PKT_RX_IP_CKSUM_BAD) >> 1,
1002 (PKT_RX_L4_CKSUM_GOOD | PKT_RX_IP_CKSUM_GOOD) >> 1);
1003 const __m256i cksum_mask =
1004 _mm256_set1_epi32(PKT_RX_IP_CKSUM_GOOD | PKT_RX_IP_CKSUM_BAD |
1005 PKT_RX_L4_CKSUM_GOOD | PKT_RX_L4_CKSUM_BAD |
1006 PKT_RX_OUTER_IP_CKSUM_BAD);
1008 #if defined(IAVF_RX_VLAN_OFFLOAD) || defined(IAVF_RX_RSS_OFFLOAD)
1010 * data to be shuffled by result of flag mask, shifted down 12.
1011 * If RSS(bit12)/VLAN(bit13) are set,
1012 * shuffle moves appropriate flags in place.
1014 const __m256i rss_flags_shuf = _mm256_set_epi8
1020 /* end up 128-bits */
1025 PKT_RX_RSS_HASH, 0);
1027 const __m256i vlan_flags_shuf = _mm256_set_epi8
1031 PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED,
1032 PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED,
1034 /* end up 128-bits */
1038 PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED,
1039 PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED,
1043 #if defined(IAVF_RX_CSUM_OFFLOAD) || defined(IAVF_RX_VLAN_OFFLOAD) || defined(IAVF_RX_RSS_OFFLOAD)
1044 /* get only flag/error bits we want */
1045 const __m256i flag_bits =
1046 _mm256_and_si256(status0_7, flags_mask);
1048 #ifdef IAVF_RX_CSUM_OFFLOAD
1050 * l3_l4_error flags, shuffle, then shift to correct adjustment
1051 * of flags in flags_shuf, and finally mask out extra bits
1053 __m256i l3_l4_flags = _mm256_shuffle_epi8(l3_l4_flags_shuf,
1054 _mm256_srli_epi32(flag_bits, 4));
1055 l3_l4_flags = _mm256_slli_epi32(l3_l4_flags, 1);
1056 l3_l4_flags = _mm256_and_si256(l3_l4_flags, cksum_mask);
1058 #if defined(IAVF_RX_VLAN_OFFLOAD) || defined(IAVF_RX_RSS_OFFLOAD)
1059 /* set rss and vlan flags */
1060 const __m256i rss_vlan_flag_bits =
1061 _mm256_srli_epi32(flag_bits, 12);
1062 const __m256i rss_flags =
1063 _mm256_shuffle_epi8(rss_flags_shuf,
1064 rss_vlan_flag_bits);
1066 if (rxq->rx_flags == IAVF_RX_FLAGS_VLAN_TAG_LOC_L2TAG1)
1068 _mm256_shuffle_epi8(vlan_flags_shuf,
1069 rss_vlan_flag_bits);
1071 const __m256i rss_vlan_flags =
1072 _mm256_or_si256(rss_flags, vlan_flags);
1076 #ifdef IAVF_RX_CSUM_OFFLOAD
1077 mbuf_flags = _mm256_or_si256(mbuf_flags, l3_l4_flags);
1079 #if defined(IAVF_RX_VLAN_OFFLOAD) || defined(IAVF_RX_RSS_OFFLOAD)
1080 mbuf_flags = _mm256_or_si256(mbuf_flags, rss_vlan_flags);
1084 #ifdef IAVF_RX_FDIR_OFFLOAD
1085 if (rxq->fdir_enabled) {
1086 const __m512i fdir_permute_mask = _mm512_set_epi32
1091 __m512i fdir_tmp = _mm512_permutex2var_epi32
1092 (raw_desc0_3, fdir_permute_mask, raw_desc4_7);
1093 const __m256i fdir_id0_7 = _mm512_extracti64x4_epi64
1095 const __m256i fdir_flags =
1096 flex_rxd_to_fdir_flags_vec_avx512(fdir_id0_7);
1098 /* merge with fdir_flags */
1099 mbuf_flags = _mm256_or_si256(mbuf_flags, fdir_flags);
1101 /* write to mbuf: have to use scalar store here */
1102 rx_pkts[i + 0]->hash.fdir.hi =
1103 _mm256_extract_epi32(fdir_id0_7, 3);
1105 rx_pkts[i + 1]->hash.fdir.hi =
1106 _mm256_extract_epi32(fdir_id0_7, 7);
1108 rx_pkts[i + 2]->hash.fdir.hi =
1109 _mm256_extract_epi32(fdir_id0_7, 2);
1111 rx_pkts[i + 3]->hash.fdir.hi =
1112 _mm256_extract_epi32(fdir_id0_7, 6);
1114 rx_pkts[i + 4]->hash.fdir.hi =
1115 _mm256_extract_epi32(fdir_id0_7, 1);
1117 rx_pkts[i + 5]->hash.fdir.hi =
1118 _mm256_extract_epi32(fdir_id0_7, 5);
1120 rx_pkts[i + 6]->hash.fdir.hi =
1121 _mm256_extract_epi32(fdir_id0_7, 0);
1123 rx_pkts[i + 7]->hash.fdir.hi =
1124 _mm256_extract_epi32(fdir_id0_7, 4);
1125 } /* if() on fdir_enabled */
1128 __m256i mb4_5 = _mm512_extracti64x4_epi64(mb4_7, 0);
1129 __m256i mb6_7 = _mm512_extracti64x4_epi64(mb4_7, 1);
1130 __m256i mb0_1 = _mm512_extracti64x4_epi64(mb0_3, 0);
1131 __m256i mb2_3 = _mm512_extracti64x4_epi64(mb0_3, 1);
1133 #ifndef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
1135 #ifdef IAVF_RX_RSS_OFFLOAD
1137 * needs to load 2nd 16B of each desc for RSS hash parsing,
1138 * will cause performance drop to get into this context.
1140 if (rxq->vsi->adapter->eth_dev->data->dev_conf.rxmode.offloads &
1141 DEV_RX_OFFLOAD_RSS_HASH ||
1142 rxq->rx_flags & IAVF_RX_FLAGS_VLAN_TAG_LOC_L2TAG2_2) {
1143 /* load bottom half of every 32B desc */
1144 const __m128i raw_desc_bh7 =
1146 ((void *)(&rxdp[7].wb.status_error1));
1147 rte_compiler_barrier();
1148 const __m128i raw_desc_bh6 =
1150 ((void *)(&rxdp[6].wb.status_error1));
1151 rte_compiler_barrier();
1152 const __m128i raw_desc_bh5 =
1154 ((void *)(&rxdp[5].wb.status_error1));
1155 rte_compiler_barrier();
1156 const __m128i raw_desc_bh4 =
1158 ((void *)(&rxdp[4].wb.status_error1));
1159 rte_compiler_barrier();
1160 const __m128i raw_desc_bh3 =
1162 ((void *)(&rxdp[3].wb.status_error1));
1163 rte_compiler_barrier();
1164 const __m128i raw_desc_bh2 =
1166 ((void *)(&rxdp[2].wb.status_error1));
1167 rte_compiler_barrier();
1168 const __m128i raw_desc_bh1 =
1170 ((void *)(&rxdp[1].wb.status_error1));
1171 rte_compiler_barrier();
1172 const __m128i raw_desc_bh0 =
1174 ((void *)(&rxdp[0].wb.status_error1));
1176 __m256i raw_desc_bh6_7 =
1177 _mm256_inserti128_si256
1178 (_mm256_castsi128_si256(raw_desc_bh6),
1180 __m256i raw_desc_bh4_5 =
1181 _mm256_inserti128_si256
1182 (_mm256_castsi128_si256(raw_desc_bh4),
1184 __m256i raw_desc_bh2_3 =
1185 _mm256_inserti128_si256
1186 (_mm256_castsi128_si256(raw_desc_bh2),
1188 __m256i raw_desc_bh0_1 =
1189 _mm256_inserti128_si256
1190 (_mm256_castsi128_si256(raw_desc_bh0),
1193 if (rxq->vsi->adapter->eth_dev->data->dev_conf.rxmode.offloads &
1194 DEV_RX_OFFLOAD_RSS_HASH) {
1196 * to shift the 32b RSS hash value to the
1197 * highest 32b of each 128b before mask
1199 __m256i rss_hash6_7 =
1201 (raw_desc_bh6_7, 32);
1202 __m256i rss_hash4_5 =
1204 (raw_desc_bh4_5, 32);
1205 __m256i rss_hash2_3 =
1207 (raw_desc_bh2_3, 32);
1208 __m256i rss_hash0_1 =
1210 (raw_desc_bh0_1, 32);
1212 const __m256i rss_hash_msk =
1214 (0xFFFFFFFF, 0, 0, 0,
1215 0xFFFFFFFF, 0, 0, 0);
1217 rss_hash6_7 = _mm256_and_si256
1218 (rss_hash6_7, rss_hash_msk);
1219 rss_hash4_5 = _mm256_and_si256
1220 (rss_hash4_5, rss_hash_msk);
1221 rss_hash2_3 = _mm256_and_si256
1222 (rss_hash2_3, rss_hash_msk);
1223 rss_hash0_1 = _mm256_and_si256
1224 (rss_hash0_1, rss_hash_msk);
1226 mb6_7 = _mm256_or_si256
1227 (mb6_7, rss_hash6_7);
1228 mb4_5 = _mm256_or_si256
1229 (mb4_5, rss_hash4_5);
1230 mb2_3 = _mm256_or_si256
1231 (mb2_3, rss_hash2_3);
1232 mb0_1 = _mm256_or_si256
1233 (mb0_1, rss_hash0_1);
1236 if (rxq->rx_flags & IAVF_RX_FLAGS_VLAN_TAG_LOC_L2TAG2_2) {
1237 /* merge the status/error-1 bits into one register */
1238 const __m256i status1_4_7 =
1239 _mm256_unpacklo_epi32
1242 const __m256i status1_0_3 =
1243 _mm256_unpacklo_epi32
1247 const __m256i status1_0_7 =
1248 _mm256_unpacklo_epi64
1249 (status1_4_7, status1_0_3);
1251 const __m256i l2tag2p_flag_mask =
1253 (1 << IAVF_RX_FLEX_DESC_STATUS1_L2TAG2P_S);
1255 __m256i l2tag2p_flag_bits =
1263 IAVF_RX_FLEX_DESC_STATUS1_L2TAG2P_S);
1265 const __m256i l2tag2_flags_shuf =
1271 /* end up 128-bits */
1277 PKT_RX_VLAN_STRIPPED,
1285 /* merge with vlan_flags */
1286 mbuf_flags = _mm256_or_si256
1291 __m256i vlan_tci6_7 =
1293 (raw_desc_bh6_7, 4);
1294 __m256i vlan_tci4_5 =
1296 (raw_desc_bh4_5, 4);
1297 __m256i vlan_tci2_3 =
1299 (raw_desc_bh2_3, 4);
1300 __m256i vlan_tci0_1 =
1302 (raw_desc_bh0_1, 4);
1304 const __m256i vlan_tci_msk =
1306 (0, 0xFFFF0000, 0, 0,
1307 0, 0xFFFF0000, 0, 0);
1309 vlan_tci6_7 = _mm256_and_si256
1312 vlan_tci4_5 = _mm256_and_si256
1315 vlan_tci2_3 = _mm256_and_si256
1318 vlan_tci0_1 = _mm256_and_si256
1322 mb6_7 = _mm256_or_si256
1323 (mb6_7, vlan_tci6_7);
1324 mb4_5 = _mm256_or_si256
1325 (mb4_5, vlan_tci4_5);
1326 mb2_3 = _mm256_or_si256
1327 (mb2_3, vlan_tci2_3);
1328 mb0_1 = _mm256_or_si256
1329 (mb0_1, vlan_tci0_1);
1331 } /* if() on RSS hash parsing */
1337 * At this point, we have the 8 sets of flags in the low 16-bits
1338 * of each 32-bit value in vlan0.
1339 * We want to extract these, and merge them with the mbuf init
1340 * data so we can do a single write to the mbuf to set the flags
1341 * and all the other initialization fields. Extracting the
1342 * appropriate flags means that we have to do a shift and blend
1343 * for each mbuf before we do the write. However, we can also
1344 * add in the previously computed rx_descriptor fields to
1345 * make a single 256-bit write per mbuf
1347 /* check the structure matches expectations */
1348 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, ol_flags) !=
1349 offsetof(struct rte_mbuf, rearm_data) + 8);
1350 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, rearm_data) !=
1351 RTE_ALIGN(offsetof(struct rte_mbuf,
1354 /* build up data and do writes */
1355 __m256i rearm0, rearm1, rearm2, rearm3, rearm4, rearm5,
1357 rearm6 = _mm256_blend_epi32(mbuf_init,
1358 _mm256_slli_si256(mbuf_flags, 8),
1360 rearm4 = _mm256_blend_epi32(mbuf_init,
1361 _mm256_slli_si256(mbuf_flags, 4),
1363 rearm2 = _mm256_blend_epi32(mbuf_init, mbuf_flags, 0x04);
1364 rearm0 = _mm256_blend_epi32(mbuf_init,
1365 _mm256_srli_si256(mbuf_flags, 4),
1367 /* permute to add in the rx_descriptor e.g. rss fields */
1368 rearm6 = _mm256_permute2f128_si256(rearm6, mb6_7, 0x20);
1369 rearm4 = _mm256_permute2f128_si256(rearm4, mb4_5, 0x20);
1370 rearm2 = _mm256_permute2f128_si256(rearm2, mb2_3, 0x20);
1371 rearm0 = _mm256_permute2f128_si256(rearm0, mb0_1, 0x20);
1373 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 6]->rearm_data,
1375 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 4]->rearm_data,
1377 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 2]->rearm_data,
1379 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 0]->rearm_data,
1382 /* repeat for the odd mbufs */
1383 const __m256i odd_flags =
1384 _mm256_castsi128_si256
1385 (_mm256_extracti128_si256(mbuf_flags, 1));
1386 rearm7 = _mm256_blend_epi32(mbuf_init,
1387 _mm256_slli_si256(odd_flags, 8),
1389 rearm5 = _mm256_blend_epi32(mbuf_init,
1390 _mm256_slli_si256(odd_flags, 4),
1392 rearm3 = _mm256_blend_epi32(mbuf_init, odd_flags, 0x04);
1393 rearm1 = _mm256_blend_epi32(mbuf_init,
1394 _mm256_srli_si256(odd_flags, 4),
1396 /* since odd mbufs are already in hi 128-bits use blend */
1397 rearm7 = _mm256_blend_epi32(rearm7, mb6_7, 0xF0);
1398 rearm5 = _mm256_blend_epi32(rearm5, mb4_5, 0xF0);
1399 rearm3 = _mm256_blend_epi32(rearm3, mb2_3, 0xF0);
1400 rearm1 = _mm256_blend_epi32(rearm1, mb0_1, 0xF0);
1401 /* again write to mbufs */
1402 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 7]->rearm_data,
1404 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 5]->rearm_data,
1406 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 3]->rearm_data,
1408 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 1]->rearm_data,
1411 /* extract and record EOP bit */
1413 const __m128i eop_mask =
1415 IAVF_RX_FLEX_DESC_STATUS0_EOF_S);
1416 const __m256i eop_bits256 = _mm256_and_si256(status0_7,
1418 /* pack status bits into a single 128-bit register */
1419 const __m128i eop_bits =
1421 (_mm256_castsi256_si128(eop_bits256),
1422 _mm256_extractf128_si256(eop_bits256,
1425 * flip bits, and mask out the EOP bit, which is now
1426 * a split-packet bit i.e. !EOP, rather than EOP one.
1428 __m128i split_bits = _mm_andnot_si128(eop_bits,
1431 * eop bits are out of order, so we need to shuffle them
1432 * back into order again. In doing so, only use low 8
1433 * bits, which acts like another pack instruction
1434 * The original order is (hi->lo): 1,3,5,7,0,2,4,6
1435 * [Since we use epi8, the 16-bit positions are
1436 * multiplied by 2 in the eop_shuffle value.]
1438 __m128i eop_shuffle =
1439 _mm_set_epi8(/* zero hi 64b */
1440 0xFF, 0xFF, 0xFF, 0xFF,
1441 0xFF, 0xFF, 0xFF, 0xFF,
1442 /* move values to lo 64b */
1445 split_bits = _mm_shuffle_epi8(split_bits, eop_shuffle);
1446 *(uint64_t *)split_packet =
1447 _mm_cvtsi128_si64(split_bits);
1448 split_packet += IAVF_DESCS_PER_LOOP_AVX;
1451 /* perform dd_check */
1452 status0_7 = _mm256_and_si256(status0_7, dd_check);
1453 status0_7 = _mm256_packs_epi32(status0_7,
1454 _mm256_setzero_si256());
1456 uint64_t burst = __builtin_popcountll
1458 (_mm256_extracti128_si256
1460 burst += __builtin_popcountll
1462 (_mm256_castsi256_si128(status0_7)));
1464 if (burst != IAVF_DESCS_PER_LOOP_AVX)
1468 /* update tail pointers */
1469 rxq->rx_tail += received;
1470 rxq->rx_tail &= (rxq->nb_rx_desc - 1);
1471 if ((rxq->rx_tail & 1) == 1 && received > 1) { /* keep aligned */
1475 rxq->rxrearm_nb += received;
1481 * - nb_pkts < IAVF_DESCS_PER_LOOP, just return no packet
1484 iavf_recv_pkts_vec_avx512(void *rx_queue, struct rte_mbuf **rx_pkts,
1487 return _iavf_recv_raw_pkts_vec_avx512(rx_queue, rx_pkts, nb_pkts,
1493 * - nb_pkts < IAVF_DESCS_PER_LOOP, just return no packet
1496 iavf_recv_pkts_vec_avx512_flex_rxd(void *rx_queue, struct rte_mbuf **rx_pkts,
1499 return _iavf_recv_raw_pkts_vec_avx512_flex_rxd(rx_queue, rx_pkts,
1500 nb_pkts, NULL, false);
1504 * vPMD receive routine that reassembles single burst of 32 scattered packets
1506 * - nb_pkts < IAVF_DESCS_PER_LOOP, just return no packet
1508 static __rte_always_inline uint16_t
1509 iavf_recv_scattered_burst_vec_avx512(void *rx_queue, struct rte_mbuf **rx_pkts,
1510 uint16_t nb_pkts, bool offload)
1512 struct iavf_rx_queue *rxq = rx_queue;
1513 uint8_t split_flags[IAVF_VPMD_RX_MAX_BURST] = {0};
1515 /* get some new buffers */
1516 uint16_t nb_bufs = _iavf_recv_raw_pkts_vec_avx512(rxq, rx_pkts, nb_pkts,
1517 split_flags, offload);
1521 /* happy day case, full burst + no packets to be joined */
1522 const uint64_t *split_fl64 = (uint64_t *)split_flags;
1524 if (!rxq->pkt_first_seg &&
1525 split_fl64[0] == 0 && split_fl64[1] == 0 &&
1526 split_fl64[2] == 0 && split_fl64[3] == 0)
1529 /* reassemble any packets that need reassembly*/
1532 if (!rxq->pkt_first_seg) {
1533 /* find the first split flag, and only reassemble then*/
1534 while (i < nb_bufs && !split_flags[i])
1538 rxq->pkt_first_seg = rx_pkts[i];
1540 return i + reassemble_packets(rxq, &rx_pkts[i], nb_bufs - i,
1545 * vPMD receive routine that reassembles scattered packets.
1546 * Main receive routine that can handle arbitrary burst sizes
1548 * - nb_pkts < IAVF_DESCS_PER_LOOP, just return no packet
1550 static __rte_always_inline uint16_t
1551 iavf_recv_scattered_pkts_vec_avx512_cmn(void *rx_queue, struct rte_mbuf **rx_pkts,
1552 uint16_t nb_pkts, bool offload)
1554 uint16_t retval = 0;
1556 while (nb_pkts > IAVF_VPMD_RX_MAX_BURST) {
1557 uint16_t burst = iavf_recv_scattered_burst_vec_avx512(rx_queue,
1558 rx_pkts + retval, IAVF_VPMD_RX_MAX_BURST, offload);
1561 if (burst < IAVF_VPMD_RX_MAX_BURST)
1564 return retval + iavf_recv_scattered_burst_vec_avx512(rx_queue,
1565 rx_pkts + retval, nb_pkts, offload);
1569 iavf_recv_scattered_pkts_vec_avx512(void *rx_queue, struct rte_mbuf **rx_pkts,
1572 return iavf_recv_scattered_pkts_vec_avx512_cmn(rx_queue, rx_pkts,
1577 * vPMD receive routine that reassembles single burst of
1578 * 32 scattered packets for flex RxD
1580 * - nb_pkts < IAVF_DESCS_PER_LOOP, just return no packet
1582 static __rte_always_inline uint16_t
1583 iavf_recv_scattered_burst_vec_avx512_flex_rxd(void *rx_queue,
1584 struct rte_mbuf **rx_pkts,
1588 struct iavf_rx_queue *rxq = rx_queue;
1589 uint8_t split_flags[IAVF_VPMD_RX_MAX_BURST] = {0};
1591 /* get some new buffers */
1592 uint16_t nb_bufs = _iavf_recv_raw_pkts_vec_avx512_flex_rxd(rxq,
1593 rx_pkts, nb_pkts, split_flags, offload);
1597 /* happy day case, full burst + no packets to be joined */
1598 const uint64_t *split_fl64 = (uint64_t *)split_flags;
1600 if (!rxq->pkt_first_seg &&
1601 split_fl64[0] == 0 && split_fl64[1] == 0 &&
1602 split_fl64[2] == 0 && split_fl64[3] == 0)
1605 /* reassemble any packets that need reassembly*/
1608 if (!rxq->pkt_first_seg) {
1609 /* find the first split flag, and only reassemble then*/
1610 while (i < nb_bufs && !split_flags[i])
1614 rxq->pkt_first_seg = rx_pkts[i];
1616 return i + reassemble_packets(rxq, &rx_pkts[i], nb_bufs - i,
1621 * vPMD receive routine that reassembles scattered packets for flex RxD.
1622 * Main receive routine that can handle arbitrary burst sizes
1624 * - nb_pkts < IAVF_DESCS_PER_LOOP, just return no packet
1626 static __rte_always_inline uint16_t
1627 iavf_recv_scattered_pkts_vec_avx512_flex_rxd_cmn(void *rx_queue,
1628 struct rte_mbuf **rx_pkts,
1632 uint16_t retval = 0;
1634 while (nb_pkts > IAVF_VPMD_RX_MAX_BURST) {
1636 iavf_recv_scattered_burst_vec_avx512_flex_rxd
1637 (rx_queue, rx_pkts + retval,
1638 IAVF_VPMD_RX_MAX_BURST, offload);
1641 if (burst < IAVF_VPMD_RX_MAX_BURST)
1644 return retval + iavf_recv_scattered_burst_vec_avx512_flex_rxd(rx_queue,
1645 rx_pkts + retval, nb_pkts, offload);
1649 iavf_recv_scattered_pkts_vec_avx512_flex_rxd(void *rx_queue,
1650 struct rte_mbuf **rx_pkts,
1653 return iavf_recv_scattered_pkts_vec_avx512_flex_rxd_cmn(rx_queue,
1660 iavf_recv_pkts_vec_avx512_offload(void *rx_queue, struct rte_mbuf **rx_pkts,
1663 return _iavf_recv_raw_pkts_vec_avx512(rx_queue, rx_pkts,
1664 nb_pkts, NULL, true);
1668 iavf_recv_scattered_pkts_vec_avx512_offload(void *rx_queue,
1669 struct rte_mbuf **rx_pkts,
1672 return iavf_recv_scattered_pkts_vec_avx512_cmn(rx_queue, rx_pkts,
1677 iavf_recv_pkts_vec_avx512_flex_rxd_offload(void *rx_queue,
1678 struct rte_mbuf **rx_pkts,
1681 return _iavf_recv_raw_pkts_vec_avx512_flex_rxd(rx_queue,
1689 iavf_recv_scattered_pkts_vec_avx512_flex_rxd_offload(void *rx_queue,
1690 struct rte_mbuf **rx_pkts,
1693 return iavf_recv_scattered_pkts_vec_avx512_flex_rxd_cmn(rx_queue,
1699 static __rte_always_inline int
1700 iavf_tx_free_bufs_avx512(struct iavf_tx_queue *txq)
1702 struct iavf_tx_vec_entry *txep;
1706 struct rte_mbuf *m, *free[IAVF_VPMD_TX_MAX_FREE_BUF];
1708 /* check DD bits on threshold descriptor */
1709 if ((txq->tx_ring[txq->next_dd].cmd_type_offset_bsz &
1710 rte_cpu_to_le_64(IAVF_TXD_QW1_DTYPE_MASK)) !=
1711 rte_cpu_to_le_64(IAVF_TX_DESC_DTYPE_DESC_DONE))
1716 /* first buffer to free from S/W ring is at index
1717 * tx_next_dd - (tx_rs_thresh-1)
1719 txep = (void *)txq->sw_ring;
1720 txep += txq->next_dd - (n - 1);
1722 if (txq->offloads & DEV_TX_OFFLOAD_MBUF_FAST_FREE && (n & 31) == 0) {
1723 struct rte_mempool *mp = txep[0].mbuf->pool;
1724 struct rte_mempool_cache *cache = rte_mempool_default_cache(mp,
1728 if (!cache || cache->len == 0)
1731 cache_objs = &cache->objs[cache->len];
1733 if (n > RTE_MEMPOOL_CACHE_MAX_SIZE) {
1734 rte_mempool_ops_enqueue_bulk(mp, (void *)txep, n);
1738 /* The cache follows the following algorithm
1739 * 1. Add the objects to the cache
1740 * 2. Anything greater than the cache min value (if it crosses the
1741 * cache flush threshold) is flushed to the ring.
1743 /* Add elements back into the cache */
1744 uint32_t copied = 0;
1745 /* n is multiple of 32 */
1746 while (copied < n) {
1747 const __m512i a = _mm512_loadu_si512(&txep[copied]);
1748 const __m512i b = _mm512_loadu_si512(&txep[copied + 8]);
1749 const __m512i c = _mm512_loadu_si512(&txep[copied + 16]);
1750 const __m512i d = _mm512_loadu_si512(&txep[copied + 24]);
1752 _mm512_storeu_si512(&cache_objs[copied], a);
1753 _mm512_storeu_si512(&cache_objs[copied + 8], b);
1754 _mm512_storeu_si512(&cache_objs[copied + 16], c);
1755 _mm512_storeu_si512(&cache_objs[copied + 24], d);
1760 if (cache->len >= cache->flushthresh) {
1761 rte_mempool_ops_enqueue_bulk(mp,
1762 &cache->objs[cache->size],
1763 cache->len - cache->size);
1764 cache->len = cache->size;
1770 m = rte_pktmbuf_prefree_seg(txep[0].mbuf);
1774 for (i = 1; i < n; i++) {
1775 m = rte_pktmbuf_prefree_seg(txep[i].mbuf);
1777 if (likely(m->pool == free[0]->pool)) {
1778 free[nb_free++] = m;
1780 rte_mempool_put_bulk(free[0]->pool,
1788 rte_mempool_put_bulk(free[0]->pool, (void **)free, nb_free);
1790 for (i = 1; i < n; i++) {
1791 m = rte_pktmbuf_prefree_seg(txep[i].mbuf);
1793 rte_mempool_put(m->pool, m);
1798 /* buffers were freed, update counters */
1799 txq->nb_free = (uint16_t)(txq->nb_free + txq->rs_thresh);
1800 txq->next_dd = (uint16_t)(txq->next_dd + txq->rs_thresh);
1801 if (txq->next_dd >= txq->nb_tx_desc)
1802 txq->next_dd = (uint16_t)(txq->rs_thresh - 1);
1804 return txq->rs_thresh;
1807 static __rte_always_inline void
1808 tx_backlog_entry_avx512(struct iavf_tx_vec_entry *txep,
1809 struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
1813 for (i = 0; i < (int)nb_pkts; ++i)
1814 txep[i].mbuf = tx_pkts[i];
1817 static __rte_always_inline void
1818 iavf_vtx1(volatile struct iavf_tx_desc *txdp,
1819 struct rte_mbuf *pkt, uint64_t flags, bool offload)
1822 (IAVF_TX_DESC_DTYPE_DATA |
1823 ((uint64_t)flags << IAVF_TXD_QW1_CMD_SHIFT) |
1824 ((uint64_t)pkt->data_len << IAVF_TXD_QW1_TX_BUF_SZ_SHIFT));
1826 iavf_txd_enable_offload(pkt, &high_qw);
1828 __m128i descriptor = _mm_set_epi64x(high_qw,
1829 pkt->buf_iova + pkt->data_off);
1830 _mm_storeu_si128((__m128i *)txdp, descriptor);
1833 #define IAVF_TX_LEN_MASK 0xAA
1834 #define IAVF_TX_OFF_MASK 0x55
1835 static __rte_always_inline void
1836 iavf_vtx(volatile struct iavf_tx_desc *txdp,
1837 struct rte_mbuf **pkt, uint16_t nb_pkts, uint64_t flags,
1840 const uint64_t hi_qw_tmpl = (IAVF_TX_DESC_DTYPE_DATA |
1841 ((uint64_t)flags << IAVF_TXD_QW1_CMD_SHIFT));
1843 /* if unaligned on 32-bit boundary, do one to align */
1844 if (((uintptr_t)txdp & 0x1F) != 0 && nb_pkts != 0) {
1845 iavf_vtx1(txdp, *pkt, flags, offload);
1846 nb_pkts--, txdp++, pkt++;
1849 /* do 4 at a time while possible, in bursts */
1850 for (; nb_pkts > 3; txdp += 4, pkt += 4, nb_pkts -= 4) {
1853 ((uint64_t)pkt[3]->data_len <<
1854 IAVF_TXD_QW1_TX_BUF_SZ_SHIFT);
1856 iavf_txd_enable_offload(pkt[3], &hi_qw3);
1859 ((uint64_t)pkt[2]->data_len <<
1860 IAVF_TXD_QW1_TX_BUF_SZ_SHIFT);
1862 iavf_txd_enable_offload(pkt[2], &hi_qw2);
1865 ((uint64_t)pkt[1]->data_len <<
1866 IAVF_TXD_QW1_TX_BUF_SZ_SHIFT);
1868 iavf_txd_enable_offload(pkt[1], &hi_qw1);
1871 ((uint64_t)pkt[0]->data_len <<
1872 IAVF_TXD_QW1_TX_BUF_SZ_SHIFT);
1874 iavf_txd_enable_offload(pkt[0], &hi_qw0);
1879 pkt[3]->buf_iova + pkt[3]->data_off,
1881 pkt[2]->buf_iova + pkt[2]->data_off,
1883 pkt[1]->buf_iova + pkt[1]->data_off,
1885 pkt[0]->buf_iova + pkt[0]->data_off);
1886 _mm512_storeu_si512((void *)txdp, desc0_3);
1889 /* do any last ones */
1891 iavf_vtx1(txdp, *pkt, flags, offload);
1892 txdp++, pkt++, nb_pkts--;
1896 static __rte_always_inline uint16_t
1897 iavf_xmit_fixed_burst_vec_avx512(void *tx_queue, struct rte_mbuf **tx_pkts,
1898 uint16_t nb_pkts, bool offload)
1900 struct iavf_tx_queue *txq = (struct iavf_tx_queue *)tx_queue;
1901 volatile struct iavf_tx_desc *txdp;
1902 struct iavf_tx_vec_entry *txep;
1903 uint16_t n, nb_commit, tx_id;
1904 /* bit2 is reserved and must be set to 1 according to Spec */
1905 uint64_t flags = IAVF_TX_DESC_CMD_EOP | IAVF_TX_DESC_CMD_ICRC;
1906 uint64_t rs = IAVF_TX_DESC_CMD_RS | flags;
1908 /* cross rx_thresh boundary is not allowed */
1909 nb_pkts = RTE_MIN(nb_pkts, txq->rs_thresh);
1911 if (txq->nb_free < txq->free_thresh)
1912 iavf_tx_free_bufs_avx512(txq);
1914 nb_commit = nb_pkts = (uint16_t)RTE_MIN(txq->nb_free, nb_pkts);
1915 if (unlikely(nb_pkts == 0))
1918 tx_id = txq->tx_tail;
1919 txdp = &txq->tx_ring[tx_id];
1920 txep = (void *)txq->sw_ring;
1923 txq->nb_free = (uint16_t)(txq->nb_free - nb_pkts);
1925 n = (uint16_t)(txq->nb_tx_desc - tx_id);
1926 if (nb_commit >= n) {
1927 tx_backlog_entry_avx512(txep, tx_pkts, n);
1929 iavf_vtx(txdp, tx_pkts, n - 1, flags, offload);
1933 iavf_vtx1(txdp, *tx_pkts++, rs, offload);
1935 nb_commit = (uint16_t)(nb_commit - n);
1938 txq->next_rs = (uint16_t)(txq->rs_thresh - 1);
1940 /* avoid reach the end of ring */
1941 txdp = &txq->tx_ring[tx_id];
1942 txep = (void *)txq->sw_ring;
1946 tx_backlog_entry_avx512(txep, tx_pkts, nb_commit);
1948 iavf_vtx(txdp, tx_pkts, nb_commit, flags, offload);
1950 tx_id = (uint16_t)(tx_id + nb_commit);
1951 if (tx_id > txq->next_rs) {
1952 txq->tx_ring[txq->next_rs].cmd_type_offset_bsz |=
1953 rte_cpu_to_le_64(((uint64_t)IAVF_TX_DESC_CMD_RS) <<
1954 IAVF_TXD_QW1_CMD_SHIFT);
1956 (uint16_t)(txq->next_rs + txq->rs_thresh);
1959 txq->tx_tail = tx_id;
1961 IAVF_PCI_REG_WRITE(txq->qtx_tail, txq->tx_tail);
1966 static __rte_always_inline uint16_t
1967 iavf_xmit_pkts_vec_avx512_cmn(void *tx_queue, struct rte_mbuf **tx_pkts,
1968 uint16_t nb_pkts, bool offload)
1971 struct iavf_tx_queue *txq = (struct iavf_tx_queue *)tx_queue;
1976 num = (uint16_t)RTE_MIN(nb_pkts, txq->rs_thresh);
1977 ret = iavf_xmit_fixed_burst_vec_avx512(tx_queue, &tx_pkts[nb_tx],
1989 iavf_xmit_pkts_vec_avx512(void *tx_queue, struct rte_mbuf **tx_pkts,
1992 return iavf_xmit_pkts_vec_avx512_cmn(tx_queue, tx_pkts, nb_pkts, false);
1996 iavf_tx_queue_release_mbufs_avx512(struct iavf_tx_queue *txq)
1999 const uint16_t max_desc = (uint16_t)(txq->nb_tx_desc - 1);
2000 struct iavf_tx_vec_entry *swr = (void *)txq->sw_ring;
2002 if (!txq->sw_ring || txq->nb_free == max_desc)
2005 i = txq->next_dd - txq->rs_thresh + 1;
2006 if (txq->tx_tail < i) {
2007 for (; i < txq->nb_tx_desc; i++) {
2008 rte_pktmbuf_free_seg(swr[i].mbuf);
2015 static const struct iavf_txq_ops avx512_vec_txq_ops = {
2016 .release_mbufs = iavf_tx_queue_release_mbufs_avx512,
2020 iavf_txq_vec_setup_avx512(struct iavf_tx_queue *txq)
2022 txq->ops = &avx512_vec_txq_ops;
2027 iavf_xmit_pkts_vec_avx512_offload(void *tx_queue, struct rte_mbuf **tx_pkts,
2030 return iavf_xmit_pkts_vec_avx512_cmn(tx_queue, tx_pkts, nb_pkts, true);