drivers/net/iavf/iavf_rxtx_vec_common.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2017 Intel Corporation
   3  */
   4
   5 #ifndef _IAVF_RXTX_VEC_COMMON_H_
   6 #define _IAVF_RXTX_VEC_COMMON_H_
   7 #include <stdint.h>
   8 #include <ethdev_driver.h>
   9 #include <rte_malloc.h>
  10
  11 #include "iavf.h"
  12 #include "iavf_rxtx.h"
  13
  14 #ifndef __INTEL_COMPILER
  15 #pragma GCC diagnostic ignored "-Wcast-qual"
  16 #endif
  17
  18 static __rte_always_inline uint16_t
  19 reassemble_packets(struct iavf_rx_queue *rxq, struct rte_mbuf **rx_bufs,
  20                    uint16_t nb_bufs, uint8_t *split_flags)
  21 {
  22         struct rte_mbuf *pkts[IAVF_VPMD_RX_MAX_BURST];
  23         struct rte_mbuf *start = rxq->pkt_first_seg;
  24         struct rte_mbuf *end =  rxq->pkt_last_seg;
  25         unsigned int pkt_idx, buf_idx;
  26
  27         for (buf_idx = 0, pkt_idx = 0; buf_idx < nb_bufs; buf_idx++) {
  28                 if (end) {
  29                         /* processing a split packet */
  30                         end->next = rx_bufs[buf_idx];
  31                         rx_bufs[buf_idx]->data_len += rxq->crc_len;
  32
  33                         start->nb_segs++;
  34                         start->pkt_len += rx_bufs[buf_idx]->data_len;
  35                         end = end->next;
  36
  37                         if (!split_flags[buf_idx]) {
  38                                 /* it's the last packet of the set */
  39                                 start->hash = end->hash;
  40                                 start->vlan_tci = end->vlan_tci;
  41                                 start->ol_flags = end->ol_flags;
  42                                 /* we need to strip crc for the whole packet */
  43                                 start->pkt_len -= rxq->crc_len;
  44                                 if (end->data_len > rxq->crc_len) {
  45                                         end->data_len -= rxq->crc_len;
  46                                 } else {
  47                                         /* free up last mbuf */
  48                                         struct rte_mbuf *secondlast = start;
  49
  50                                         start->nb_segs--;
  51                                         while (secondlast->next != end)
  52                                                 secondlast = secondlast->next;
  53                                         secondlast->data_len -= (rxq->crc_len -
  54                                                         end->data_len);
  55                                         secondlast->next = NULL;
  56                                         rte_pktmbuf_free_seg(end);
  57                                 }
  58                                 pkts[pkt_idx++] = start;
  59                                 start = NULL;
  60                                 end = NULL;
  61                         }
  62                 } else {
  63                         /* not processing a split packet */
  64                         if (!split_flags[buf_idx]) {
  65                                 /* not a split packet, save and skip */
  66                                 pkts[pkt_idx++] = rx_bufs[buf_idx];
  67                                 continue;
  68                         }
  69                         end = start = rx_bufs[buf_idx];
  70                         rx_bufs[buf_idx]->data_len += rxq->crc_len;
  71                         rx_bufs[buf_idx]->pkt_len += rxq->crc_len;
  72                 }
  73         }
  74
  75         /* save the partial packet for next time */
  76         rxq->pkt_first_seg = start;
  77         rxq->pkt_last_seg = end;
  78         memcpy(rx_bufs, pkts, pkt_idx * (sizeof(*pkts)));
  79         return pkt_idx;
  80 }
  81
  82 static __rte_always_inline int
  83 iavf_tx_free_bufs(struct iavf_tx_queue *txq)
  84 {
  85         struct iavf_tx_entry *txep;
  86         uint32_t n;
  87         uint32_t i;
  88         int nb_free = 0;
  89         struct rte_mbuf *m, *free[IAVF_VPMD_TX_MAX_FREE_BUF];
  90
  91         /* check DD bits on threshold descriptor */
  92         if ((txq->tx_ring[txq->next_dd].cmd_type_offset_bsz &
  93                         rte_cpu_to_le_64(IAVF_TXD_QW1_DTYPE_MASK)) !=
  94                         rte_cpu_to_le_64(IAVF_TX_DESC_DTYPE_DESC_DONE))
  95                 return 0;
  96
  97         n = txq->rs_thresh;
  98
  99          /* first buffer to free from S/W ring is at index
 100           * tx_next_dd - (tx_rs_thresh-1)
 101           */
 102         txep = &txq->sw_ring[txq->next_dd - (n - 1)];
 103         m = rte_pktmbuf_prefree_seg(txep[0].mbuf);
 104         if (likely(m != NULL)) {
 105                 free[0] = m;
 106                 nb_free = 1;
 107                 for (i = 1; i < n; i++) {
 108                         m = rte_pktmbuf_prefree_seg(txep[i].mbuf);
 109                         if (likely(m != NULL)) {
 110                                 if (likely(m->pool == free[0]->pool)) {
 111                                         free[nb_free++] = m;
 112                                 } else {
 113                                         rte_mempool_put_bulk(free[0]->pool,
 114                                                              (void *)free,
 115                                                              nb_free);
 116                                         free[0] = m;
 117                                         nb_free = 1;
 118                                 }
 119                         }
 120                 }
 121                 rte_mempool_put_bulk(free[0]->pool, (void **)free, nb_free);
 122         } else {
 123                 for (i = 1; i < n; i++) {
 124                         m = rte_pktmbuf_prefree_seg(txep[i].mbuf);
 125                         if (m)
 126                                 rte_mempool_put(m->pool, m);
 127                 }
 128         }
 129
 130         /* buffers were freed, update counters */
 131         txq->nb_free = (uint16_t)(txq->nb_free + txq->rs_thresh);
 132         txq->next_dd = (uint16_t)(txq->next_dd + txq->rs_thresh);
 133         if (txq->next_dd >= txq->nb_tx_desc)
 134                 txq->next_dd = (uint16_t)(txq->rs_thresh - 1);
 135
 136         return txq->rs_thresh;
 137 }
 138
 139 static __rte_always_inline void
 140 tx_backlog_entry(struct iavf_tx_entry *txep,
 141                  struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
 142 {
 143         int i;
 144
 145         for (i = 0; i < (int)nb_pkts; ++i)
 146                 txep[i].mbuf = tx_pkts[i];
 147 }
 148
 149 static inline void
 150 _iavf_rx_queue_release_mbufs_vec(struct iavf_rx_queue *rxq)
 151 {
 152         const unsigned int mask = rxq->nb_rx_desc - 1;
 153         unsigned int i;
 154
 155         if (!rxq->sw_ring || rxq->rxrearm_nb >= rxq->nb_rx_desc)
 156                 return;
 157
 158         /* free all mbufs that are valid in the ring */
 159         if (rxq->rxrearm_nb == 0) {
 160                 for (i = 0; i < rxq->nb_rx_desc; i++) {
 161                         if (rxq->sw_ring[i])
 162                                 rte_pktmbuf_free_seg(rxq->sw_ring[i]);
 163                 }
 164         } else {
 165                 for (i = rxq->rx_tail;
 166                      i != rxq->rxrearm_start;
 167                      i = (i + 1) & mask) {
 168                         if (rxq->sw_ring[i])
 169                                 rte_pktmbuf_free_seg(rxq->sw_ring[i]);
 170                 }
 171         }
 172
 173         rxq->rxrearm_nb = rxq->nb_rx_desc;
 174
 175         /* set all entries to NULL */
 176         memset(rxq->sw_ring, 0, sizeof(rxq->sw_ring[0]) * rxq->nb_rx_desc);
 177 }
 178
 179 static inline void
 180 _iavf_tx_queue_release_mbufs_vec(struct iavf_tx_queue *txq)
 181 {
 182         unsigned i;
 183         const uint16_t max_desc = (uint16_t)(txq->nb_tx_desc - 1);
 184
 185         if (!txq->sw_ring || txq->nb_free == max_desc)
 186                 return;
 187
 188         i = txq->next_dd - txq->rs_thresh + 1;
 189         if (txq->tx_tail < i) {
 190                 for (; i < txq->nb_tx_desc; i++) {
 191                         rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
 192                         txq->sw_ring[i].mbuf = NULL;
 193                 }
 194                 i = 0;
 195         }
 196 }
 197
 198 static inline int
 199 iavf_rxq_vec_setup_default(struct iavf_rx_queue *rxq)
 200 {
 201         uintptr_t p;
 202         struct rte_mbuf mb_def = { .buf_addr = 0 }; /* zeroed mbuf */
 203
 204         mb_def.nb_segs = 1;
 205         mb_def.data_off = RTE_PKTMBUF_HEADROOM;
 206         mb_def.port = rxq->port_id;
 207         rte_mbuf_refcnt_set(&mb_def, 1);
 208
 209         /* prevent compiler reordering: rearm_data covers previous fields */
 210         rte_compiler_barrier();
 211         p = (uintptr_t)&mb_def.rearm_data;
 212         rxq->mbuf_initializer = *(uint64_t *)p;
 213         return 0;
 214 }
 215
 216 static inline int
 217 iavf_rx_vec_queue_default(struct iavf_rx_queue *rxq)
 218 {
 219         if (!rxq)
 220                 return -1;
 221
 222         if (!rte_is_power_of_2(rxq->nb_rx_desc))
 223                 return -1;
 224
 225         if (rxq->rx_free_thresh < IAVF_VPMD_RX_MAX_BURST)
 226                 return -1;
 227
 228         if (rxq->nb_rx_desc % rxq->rx_free_thresh)
 229                 return -1;
 230
 231         if (rxq->proto_xtr != IAVF_PROTO_XTR_NONE)
 232                 return -1;
 233
 234         if (rxq->offloads & IAVF_RX_VECTOR_OFFLOAD)
 235                 return IAVF_VECTOR_OFFLOAD_PATH;
 236
 237         return IAVF_VECTOR_PATH;
 238 }
 239
 240 static inline int
 241 iavf_tx_vec_queue_default(struct iavf_tx_queue *txq)
 242 {
 243         if (!txq)
 244                 return -1;
 245
 246         if (txq->rs_thresh < IAVF_VPMD_TX_MAX_BURST ||
 247             txq->rs_thresh > IAVF_VPMD_TX_MAX_FREE_BUF)
 248                 return -1;
 249
 250         if (txq->offloads & IAVF_TX_NO_VECTOR_FLAGS)
 251                 return -1;
 252
 253         if (txq->offloads & IAVF_TX_VECTOR_OFFLOAD)
 254                 return IAVF_VECTOR_OFFLOAD_PATH;
 255
 256         return IAVF_VECTOR_PATH;
 257 }
 258
 259 static inline int
 260 iavf_rx_vec_dev_check_default(struct rte_eth_dev *dev)
 261 {
 262         int i;
 263         struct iavf_rx_queue *rxq;
 264         int ret;
 265         int result = 0;
 266
 267         for (i = 0; i < dev->data->nb_rx_queues; i++) {
 268                 rxq = dev->data->rx_queues[i];
 269                 ret = iavf_rx_vec_queue_default(rxq);
 270
 271                 if (ret < 0)
 272                         return -1;
 273                 if (ret > result)
 274                         result = ret;
 275         }
 276
 277         return result;
 278 }
 279
 280 static inline int
 281 iavf_tx_vec_dev_check_default(struct rte_eth_dev *dev)
 282 {
 283         int i;
 284         struct iavf_tx_queue *txq;
 285         int ret;
 286         int result = 0;
 287
 288         for (i = 0; i < dev->data->nb_tx_queues; i++) {
 289                 txq = dev->data->tx_queues[i];
 290                 ret = iavf_tx_vec_queue_default(txq);
 291
 292                 if (ret < 0)
 293                         return -1;
 294                 if (ret > result)
 295                         result = ret;
 296         }
 297
 298         return result;
 299 }
 300
 301 /******************************************************************************
 302  * If user knows a specific offload is not enabled by APP,
 303  * the macro can be commented to save the effort of fast path.
 304  * Currently below 2 features are supported in TX path,
 305  * 1, checksum offload
 306  * 2, VLAN/QINQ insertion
 307  ******************************************************************************/
 308 #define IAVF_TX_CSUM_OFFLOAD
 309 #define IAVF_TX_VLAN_QINQ_OFFLOAD
 310
 311 static __rte_always_inline void
 312 iavf_txd_enable_offload(__rte_unused struct rte_mbuf *tx_pkt,
 313                         uint64_t *txd_hi)
 314 {
 315 #if defined(IAVF_TX_CSUM_OFFLOAD) || defined(IAVF_TX_VLAN_QINQ_OFFLOAD)
 316         uint64_t ol_flags = tx_pkt->ol_flags;
 317 #endif
 318         uint32_t td_cmd = 0;
 319 #ifdef IAVF_TX_CSUM_OFFLOAD
 320         uint32_t td_offset = 0;
 321 #endif
 322
 323 #ifdef IAVF_TX_CSUM_OFFLOAD
 324         /* Set MACLEN */
 325         td_offset |= (tx_pkt->l2_len >> 1) <<
 326                      IAVF_TX_DESC_LENGTH_MACLEN_SHIFT;
 327
 328         /* Enable L3 checksum offloads */
 329         if (ol_flags & PKT_TX_IP_CKSUM) {
 330                 td_cmd |= IAVF_TX_DESC_CMD_IIPT_IPV4_CSUM;
 331                 td_offset |= (tx_pkt->l3_len >> 2) <<
 332                              IAVF_TX_DESC_LENGTH_IPLEN_SHIFT;
 333         } else if (ol_flags & PKT_TX_IPV4) {
 334                 td_cmd |= IAVF_TX_DESC_CMD_IIPT_IPV4;
 335                 td_offset |= (tx_pkt->l3_len >> 2) <<
 336                              IAVF_TX_DESC_LENGTH_IPLEN_SHIFT;
 337         } else if (ol_flags & PKT_TX_IPV6) {
 338                 td_cmd |= IAVF_TX_DESC_CMD_IIPT_IPV6;
 339                 td_offset |= (tx_pkt->l3_len >> 2) <<
 340                              IAVF_TX_DESC_LENGTH_IPLEN_SHIFT;
 341         }
 342
 343         /* Enable L4 checksum offloads */
 344         switch (ol_flags & PKT_TX_L4_MASK) {
 345         case PKT_TX_TCP_CKSUM:
 346                 td_cmd |= IAVF_TX_DESC_CMD_L4T_EOFT_TCP;
 347                 td_offset |= (sizeof(struct rte_tcp_hdr) >> 2) <<
 348                              IAVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
 349                 break;
 350         case PKT_TX_SCTP_CKSUM:
 351                 td_cmd |= IAVF_TX_DESC_CMD_L4T_EOFT_SCTP;
 352                 td_offset |= (sizeof(struct rte_sctp_hdr) >> 2) <<
 353                              IAVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
 354                 break;
 355         case PKT_TX_UDP_CKSUM:
 356                 td_cmd |= IAVF_TX_DESC_CMD_L4T_EOFT_UDP;
 357                 td_offset |= (sizeof(struct rte_udp_hdr) >> 2) <<
 358                              IAVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
 359                 break;
 360         default:
 361                 break;
 362         }
 363
 364         *txd_hi |= ((uint64_t)td_offset) << IAVF_TXD_QW1_OFFSET_SHIFT;
 365 #endif
 366
 367 #ifdef IAVF_TX_VLAN_QINQ_OFFLOAD
 368         if (ol_flags & (PKT_TX_VLAN | PKT_TX_QINQ)) {
 369                 td_cmd |= IAVF_TX_DESC_CMD_IL2TAG1;
 370                 *txd_hi |= ((uint64_t)tx_pkt->vlan_tci <<
 371                             IAVF_TXD_QW1_L2TAG1_SHIFT);
 372         }
 373 #endif
 374
 375         *txd_hi |= ((uint64_t)td_cmd) << IAVF_TXD_QW1_CMD_SHIFT;
 376 }
 377
 378 #ifdef CC_AVX2_SUPPORT
 379 static __rte_always_inline void
 380 iavf_rxq_rearm_common(struct iavf_rx_queue *rxq, __rte_unused bool avx512)
 381 {
 382         int i;
 383         uint16_t rx_id;
 384         volatile union iavf_rx_desc *rxdp;
 385         struct rte_mbuf **rxp = &rxq->sw_ring[rxq->rxrearm_start];
 386
 387         rxdp = rxq->rx_ring + rxq->rxrearm_start;
 388
 389         /* Pull 'n' more MBUFs into the software ring */
 390         if (rte_mempool_get_bulk(rxq->mp,
 391                                  (void *)rxp,
 392                                  IAVF_RXQ_REARM_THRESH) < 0) {
 393                 if (rxq->rxrearm_nb + IAVF_RXQ_REARM_THRESH >=
 394                     rxq->nb_rx_desc) {
 395                         __m128i dma_addr0;
 396
 397                         dma_addr0 = _mm_setzero_si128();
 398                         for (i = 0; i < IAVF_VPMD_DESCS_PER_LOOP; i++) {
 399                                 rxp[i] = &rxq->fake_mbuf;
 400                                 _mm_store_si128((__m128i *)&rxdp[i].read,
 401                                                 dma_addr0);
 402                         }
 403                 }
 404                 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed +=
 405                         IAVF_RXQ_REARM_THRESH;
 406                 return;
 407         }
 408
 409 #ifndef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
 410         struct rte_mbuf *mb0, *mb1;
 411         __m128i dma_addr0, dma_addr1;
 412         __m128i hdr_room = _mm_set_epi64x(RTE_PKTMBUF_HEADROOM,
 413                         RTE_PKTMBUF_HEADROOM);
 414         /* Initialize the mbufs in vector, process 2 mbufs in one loop */
 415         for (i = 0; i < IAVF_RXQ_REARM_THRESH; i += 2, rxp += 2) {
 416                 __m128i vaddr0, vaddr1;
 417
 418                 mb0 = rxp[0];
 419                 mb1 = rxp[1];
 420
 421                 /* load buf_addr(lo 64bit) and buf_iova(hi 64bit) */
 422                 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, buf_iova) !=
 423                                 offsetof(struct rte_mbuf, buf_addr) + 8);
 424                 vaddr0 = _mm_loadu_si128((__m128i *)&mb0->buf_addr);
 425                 vaddr1 = _mm_loadu_si128((__m128i *)&mb1->buf_addr);
 426
 427                 /* convert pa to dma_addr hdr/data */
 428                 dma_addr0 = _mm_unpackhi_epi64(vaddr0, vaddr0);
 429                 dma_addr1 = _mm_unpackhi_epi64(vaddr1, vaddr1);
 430
 431                 /* add headroom to pa values */
 432                 dma_addr0 = _mm_add_epi64(dma_addr0, hdr_room);
 433                 dma_addr1 = _mm_add_epi64(dma_addr1, hdr_room);
 434
 435                 /* flush desc with pa dma_addr */
 436                 _mm_store_si128((__m128i *)&rxdp++->read, dma_addr0);
 437                 _mm_store_si128((__m128i *)&rxdp++->read, dma_addr1);
 438         }
 439 #else
 440 #ifdef CC_AVX512_SUPPORT
 441         if (avx512) {
 442                 struct rte_mbuf *mb0, *mb1, *mb2, *mb3;
 443                 struct rte_mbuf *mb4, *mb5, *mb6, *mb7;
 444                 __m512i dma_addr0_3, dma_addr4_7;
 445                 __m512i hdr_room = _mm512_set1_epi64(RTE_PKTMBUF_HEADROOM);
 446                 /* Initialize the mbufs in vector, process 8 mbufs in one loop */
 447                 for (i = 0; i < IAVF_RXQ_REARM_THRESH;
 448                                 i += 8, rxp += 8, rxdp += 8) {
 449                         __m128i vaddr0, vaddr1, vaddr2, vaddr3;
 450                         __m128i vaddr4, vaddr5, vaddr6, vaddr7;
 451                         __m256i vaddr0_1, vaddr2_3;
 452                         __m256i vaddr4_5, vaddr6_7;
 453                         __m512i vaddr0_3, vaddr4_7;
 454
 455                         mb0 = rxp[0];
 456                         mb1 = rxp[1];
 457                         mb2 = rxp[2];
 458                         mb3 = rxp[3];
 459                         mb4 = rxp[4];
 460                         mb5 = rxp[5];
 461                         mb6 = rxp[6];
 462                         mb7 = rxp[7];
 463
 464                         /* load buf_addr(lo 64bit) and buf_iova(hi 64bit) */
 465                         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, buf_iova) !=
 466                                         offsetof(struct rte_mbuf, buf_addr) + 8);
 467                         vaddr0 = _mm_loadu_si128((__m128i *)&mb0->buf_addr);
 468                         vaddr1 = _mm_loadu_si128((__m128i *)&mb1->buf_addr);
 469                         vaddr2 = _mm_loadu_si128((__m128i *)&mb2->buf_addr);
 470                         vaddr3 = _mm_loadu_si128((__m128i *)&mb3->buf_addr);
 471                         vaddr4 = _mm_loadu_si128((__m128i *)&mb4->buf_addr);
 472                         vaddr5 = _mm_loadu_si128((__m128i *)&mb5->buf_addr);
 473                         vaddr6 = _mm_loadu_si128((__m128i *)&mb6->buf_addr);
 474                         vaddr7 = _mm_loadu_si128((__m128i *)&mb7->buf_addr);
 475
 476                         /**
 477                          * merge 0 & 1, by casting 0 to 256-bit and inserting 1
 478                          * into the high lanes. Similarly for 2 & 3, and so on.
 479                          */
 480                         vaddr0_1 =
 481                                 _mm256_inserti128_si256(_mm256_castsi128_si256(vaddr0),
 482                                                         vaddr1, 1);
 483                         vaddr2_3 =
 484                                 _mm256_inserti128_si256(_mm256_castsi128_si256(vaddr2),
 485                                                         vaddr3, 1);
 486                         vaddr4_5 =
 487                                 _mm256_inserti128_si256(_mm256_castsi128_si256(vaddr4),
 488                                                         vaddr5, 1);
 489                         vaddr6_7 =
 490                                 _mm256_inserti128_si256(_mm256_castsi128_si256(vaddr6),
 491                                                         vaddr7, 1);
 492                         vaddr0_3 =
 493                                 _mm512_inserti64x4(_mm512_castsi256_si512(vaddr0_1),
 494                                                         vaddr2_3, 1);
 495                         vaddr4_7 =
 496                                 _mm512_inserti64x4(_mm512_castsi256_si512(vaddr4_5),
 497                                                         vaddr6_7, 1);
 498
 499                         /* convert pa to dma_addr hdr/data */
 500                         dma_addr0_3 = _mm512_unpackhi_epi64(vaddr0_3, vaddr0_3);
 501                         dma_addr4_7 = _mm512_unpackhi_epi64(vaddr4_7, vaddr4_7);
 502
 503                         /* add headroom to pa values */
 504                         dma_addr0_3 = _mm512_add_epi64(dma_addr0_3, hdr_room);
 505                         dma_addr4_7 = _mm512_add_epi64(dma_addr4_7, hdr_room);
 506
 507                         /* flush desc with pa dma_addr */
 508                         _mm512_store_si512((__m512i *)&rxdp->read, dma_addr0_3);
 509                         _mm512_store_si512((__m512i *)&(rxdp + 4)->read, dma_addr4_7);
 510                 }
 511         } else
 512 #endif
 513         {
 514                 struct rte_mbuf *mb0, *mb1, *mb2, *mb3;
 515                 __m256i dma_addr0_1, dma_addr2_3;
 516                 __m256i hdr_room = _mm256_set1_epi64x(RTE_PKTMBUF_HEADROOM);
 517                 /* Initialize the mbufs in vector, process 4 mbufs in one loop */
 518                 for (i = 0; i < IAVF_RXQ_REARM_THRESH;
 519                                 i += 4, rxp += 4, rxdp += 4) {
 520                         __m128i vaddr0, vaddr1, vaddr2, vaddr3;
 521                         __m256i vaddr0_1, vaddr2_3;
 522
 523                         mb0 = rxp[0];
 524                         mb1 = rxp[1];
 525                         mb2 = rxp[2];
 526                         mb3 = rxp[3];
 527
 528                         /* load buf_addr(lo 64bit) and buf_iova(hi 64bit) */
 529                         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, buf_iova) !=
 530                                         offsetof(struct rte_mbuf, buf_addr) + 8);
 531                         vaddr0 = _mm_loadu_si128((__m128i *)&mb0->buf_addr);
 532                         vaddr1 = _mm_loadu_si128((__m128i *)&mb1->buf_addr);
 533                         vaddr2 = _mm_loadu_si128((__m128i *)&mb2->buf_addr);
 534                         vaddr3 = _mm_loadu_si128((__m128i *)&mb3->buf_addr);
 535
 536                         /**
 537                          * merge 0 & 1, by casting 0 to 256-bit and inserting 1
 538                          * into the high lanes. Similarly for 2 & 3
 539                          */
 540                         vaddr0_1 =
 541                                 _mm256_inserti128_si256(_mm256_castsi128_si256(vaddr0),
 542                                                         vaddr1, 1);
 543                         vaddr2_3 =
 544                                 _mm256_inserti128_si256(_mm256_castsi128_si256(vaddr2),
 545                                                         vaddr3, 1);
 546
 547                         /* convert pa to dma_addr hdr/data */
 548                         dma_addr0_1 = _mm256_unpackhi_epi64(vaddr0_1, vaddr0_1);
 549                         dma_addr2_3 = _mm256_unpackhi_epi64(vaddr2_3, vaddr2_3);
 550
 551                         /* add headroom to pa values */
 552                         dma_addr0_1 = _mm256_add_epi64(dma_addr0_1, hdr_room);
 553                         dma_addr2_3 = _mm256_add_epi64(dma_addr2_3, hdr_room);
 554
 555                         /* flush desc with pa dma_addr */
 556                         _mm256_store_si256((__m256i *)&rxdp->read, dma_addr0_1);
 557                         _mm256_store_si256((__m256i *)&(rxdp + 2)->read, dma_addr2_3);
 558                 }
 559         }
 560
 561 #endif
 562
 563         rxq->rxrearm_start += IAVF_RXQ_REARM_THRESH;
 564         if (rxq->rxrearm_start >= rxq->nb_rx_desc)
 565                 rxq->rxrearm_start = 0;
 566
 567         rxq->rxrearm_nb -= IAVF_RXQ_REARM_THRESH;
 568
 569         rx_id = (uint16_t)((rxq->rxrearm_start == 0) ?
 570                              (rxq->nb_rx_desc - 1) : (rxq->rxrearm_start - 1));
 571
 572         /* Update the tail pointer on the NIC */
 573         IAVF_PCI_REG_WC_WRITE(rxq->qrx_tail, rx_id);
 574 }
 575 #endif
 576
 577 #endif