1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2017 Intel Corporation
5 #ifndef _IAVF_RXTX_VEC_COMMON_H_
6 #define _IAVF_RXTX_VEC_COMMON_H_
8 #include <ethdev_driver.h>
9 #include <rte_malloc.h>
12 #include "iavf_rxtx.h"
14 #ifndef __INTEL_COMPILER
15 #pragma GCC diagnostic ignored "-Wcast-qual"
18 static inline uint16_t
19 reassemble_packets(struct iavf_rx_queue *rxq, struct rte_mbuf **rx_bufs,
20 uint16_t nb_bufs, uint8_t *split_flags)
22 struct rte_mbuf *pkts[IAVF_VPMD_RX_MAX_BURST];
23 struct rte_mbuf *start = rxq->pkt_first_seg;
24 struct rte_mbuf *end = rxq->pkt_last_seg;
25 unsigned int pkt_idx, buf_idx;
27 for (buf_idx = 0, pkt_idx = 0; buf_idx < nb_bufs; buf_idx++) {
29 /* processing a split packet */
30 end->next = rx_bufs[buf_idx];
31 rx_bufs[buf_idx]->data_len += rxq->crc_len;
34 start->pkt_len += rx_bufs[buf_idx]->data_len;
37 if (!split_flags[buf_idx]) {
38 /* it's the last packet of the set */
39 start->hash = end->hash;
40 start->vlan_tci = end->vlan_tci;
41 start->ol_flags = end->ol_flags;
42 /* we need to strip crc for the whole packet */
43 start->pkt_len -= rxq->crc_len;
44 if (end->data_len > rxq->crc_len) {
45 end->data_len -= rxq->crc_len;
47 /* free up last mbuf */
48 struct rte_mbuf *secondlast = start;
51 while (secondlast->next != end)
52 secondlast = secondlast->next;
53 secondlast->data_len -= (rxq->crc_len -
55 secondlast->next = NULL;
56 rte_pktmbuf_free_seg(end);
58 pkts[pkt_idx++] = start;
63 /* not processing a split packet */
64 if (!split_flags[buf_idx]) {
65 /* not a split packet, save and skip */
66 pkts[pkt_idx++] = rx_bufs[buf_idx];
69 end = start = rx_bufs[buf_idx];
70 rx_bufs[buf_idx]->data_len += rxq->crc_len;
71 rx_bufs[buf_idx]->pkt_len += rxq->crc_len;
75 /* save the partial packet for next time */
76 rxq->pkt_first_seg = start;
77 rxq->pkt_last_seg = end;
78 memcpy(rx_bufs, pkts, pkt_idx * (sizeof(*pkts)));
82 static __rte_always_inline int
83 iavf_tx_free_bufs(struct iavf_tx_queue *txq)
85 struct iavf_tx_entry *txep;
89 struct rte_mbuf *m, *free[IAVF_VPMD_TX_MAX_FREE_BUF];
91 /* check DD bits on threshold descriptor */
92 if ((txq->tx_ring[txq->next_dd].cmd_type_offset_bsz &
93 rte_cpu_to_le_64(IAVF_TXD_QW1_DTYPE_MASK)) !=
94 rte_cpu_to_le_64(IAVF_TX_DESC_DTYPE_DESC_DONE))
99 /* first buffer to free from S/W ring is at index
100 * tx_next_dd - (tx_rs_thresh-1)
102 txep = &txq->sw_ring[txq->next_dd - (n - 1)];
103 m = rte_pktmbuf_prefree_seg(txep[0].mbuf);
104 if (likely(m != NULL)) {
107 for (i = 1; i < n; i++) {
108 m = rte_pktmbuf_prefree_seg(txep[i].mbuf);
109 if (likely(m != NULL)) {
110 if (likely(m->pool == free[0]->pool)) {
113 rte_mempool_put_bulk(free[0]->pool,
121 rte_mempool_put_bulk(free[0]->pool, (void **)free, nb_free);
123 for (i = 1; i < n; i++) {
124 m = rte_pktmbuf_prefree_seg(txep[i].mbuf);
126 rte_mempool_put(m->pool, m);
130 /* buffers were freed, update counters */
131 txq->nb_free = (uint16_t)(txq->nb_free + txq->rs_thresh);
132 txq->next_dd = (uint16_t)(txq->next_dd + txq->rs_thresh);
133 if (txq->next_dd >= txq->nb_tx_desc)
134 txq->next_dd = (uint16_t)(txq->rs_thresh - 1);
136 return txq->rs_thresh;
139 static __rte_always_inline void
140 tx_backlog_entry(struct iavf_tx_entry *txep,
141 struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
145 for (i = 0; i < (int)nb_pkts; ++i)
146 txep[i].mbuf = tx_pkts[i];
150 _iavf_rx_queue_release_mbufs_vec(struct iavf_rx_queue *rxq)
152 const unsigned int mask = rxq->nb_rx_desc - 1;
155 if (!rxq->sw_ring || rxq->rxrearm_nb >= rxq->nb_rx_desc)
158 /* free all mbufs that are valid in the ring */
159 if (rxq->rxrearm_nb == 0) {
160 for (i = 0; i < rxq->nb_rx_desc; i++) {
162 rte_pktmbuf_free_seg(rxq->sw_ring[i]);
165 for (i = rxq->rx_tail;
166 i != rxq->rxrearm_start;
167 i = (i + 1) & mask) {
169 rte_pktmbuf_free_seg(rxq->sw_ring[i]);
173 rxq->rxrearm_nb = rxq->nb_rx_desc;
175 /* set all entries to NULL */
176 memset(rxq->sw_ring, 0, sizeof(rxq->sw_ring[0]) * rxq->nb_rx_desc);
180 _iavf_tx_queue_release_mbufs_vec(struct iavf_tx_queue *txq)
183 const uint16_t max_desc = (uint16_t)(txq->nb_tx_desc - 1);
185 if (!txq->sw_ring || txq->nb_free == max_desc)
188 i = txq->next_dd - txq->rs_thresh + 1;
189 if (txq->tx_tail < i) {
190 for (; i < txq->nb_tx_desc; i++) {
191 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
192 txq->sw_ring[i].mbuf = NULL;
199 iavf_rxq_vec_setup_default(struct iavf_rx_queue *rxq)
202 struct rte_mbuf mb_def = { .buf_addr = 0 }; /* zeroed mbuf */
205 mb_def.data_off = RTE_PKTMBUF_HEADROOM;
206 mb_def.port = rxq->port_id;
207 rte_mbuf_refcnt_set(&mb_def, 1);
209 /* prevent compiler reordering: rearm_data covers previous fields */
210 rte_compiler_barrier();
211 p = (uintptr_t)&mb_def.rearm_data;
212 rxq->mbuf_initializer = *(uint64_t *)p;
217 iavf_rx_vec_queue_default(struct iavf_rx_queue *rxq)
222 if (!rte_is_power_of_2(rxq->nb_rx_desc))
225 if (rxq->rx_free_thresh < IAVF_VPMD_RX_MAX_BURST)
228 if (rxq->nb_rx_desc % rxq->rx_free_thresh)
231 if (rxq->proto_xtr != IAVF_PROTO_XTR_NONE)
238 iavf_tx_vec_queue_default(struct iavf_tx_queue *txq)
243 if (txq->offloads & IAVF_NO_VECTOR_FLAGS)
246 if (txq->rs_thresh < IAVF_VPMD_TX_MAX_BURST ||
247 txq->rs_thresh > IAVF_VPMD_TX_MAX_FREE_BUF)
254 iavf_rx_vec_dev_check_default(struct rte_eth_dev *dev)
257 struct iavf_rx_queue *rxq;
259 for (i = 0; i < dev->data->nb_rx_queues; i++) {
260 rxq = dev->data->rx_queues[i];
261 if (iavf_rx_vec_queue_default(rxq))
269 iavf_tx_vec_dev_check_default(struct rte_eth_dev *dev)
272 struct iavf_tx_queue *txq;
274 for (i = 0; i < dev->data->nb_tx_queues; i++) {
275 txq = dev->data->tx_queues[i];
276 if (iavf_tx_vec_queue_default(txq))
283 #ifdef CC_AVX2_SUPPORT
284 static __rte_always_inline void
285 iavf_rxq_rearm_common(struct iavf_rx_queue *rxq, __rte_unused bool avx512)
289 volatile union iavf_rx_desc *rxdp;
290 struct rte_mbuf **rxp = &rxq->sw_ring[rxq->rxrearm_start];
292 rxdp = rxq->rx_ring + rxq->rxrearm_start;
294 /* Pull 'n' more MBUFs into the software ring */
295 if (rte_mempool_get_bulk(rxq->mp,
297 IAVF_RXQ_REARM_THRESH) < 0) {
298 if (rxq->rxrearm_nb + IAVF_RXQ_REARM_THRESH >=
302 dma_addr0 = _mm_setzero_si128();
303 for (i = 0; i < IAVF_VPMD_DESCS_PER_LOOP; i++) {
304 rxp[i] = &rxq->fake_mbuf;
305 _mm_store_si128((__m128i *)&rxdp[i].read,
309 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed +=
310 IAVF_RXQ_REARM_THRESH;
314 #ifndef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
315 struct rte_mbuf *mb0, *mb1;
316 __m128i dma_addr0, dma_addr1;
317 __m128i hdr_room = _mm_set_epi64x(RTE_PKTMBUF_HEADROOM,
318 RTE_PKTMBUF_HEADROOM);
319 /* Initialize the mbufs in vector, process 2 mbufs in one loop */
320 for (i = 0; i < IAVF_RXQ_REARM_THRESH; i += 2, rxp += 2) {
321 __m128i vaddr0, vaddr1;
326 /* load buf_addr(lo 64bit) and buf_iova(hi 64bit) */
327 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, buf_iova) !=
328 offsetof(struct rte_mbuf, buf_addr) + 8);
329 vaddr0 = _mm_loadu_si128((__m128i *)&mb0->buf_addr);
330 vaddr1 = _mm_loadu_si128((__m128i *)&mb1->buf_addr);
332 /* convert pa to dma_addr hdr/data */
333 dma_addr0 = _mm_unpackhi_epi64(vaddr0, vaddr0);
334 dma_addr1 = _mm_unpackhi_epi64(vaddr1, vaddr1);
336 /* add headroom to pa values */
337 dma_addr0 = _mm_add_epi64(dma_addr0, hdr_room);
338 dma_addr1 = _mm_add_epi64(dma_addr1, hdr_room);
340 /* flush desc with pa dma_addr */
341 _mm_store_si128((__m128i *)&rxdp++->read, dma_addr0);
342 _mm_store_si128((__m128i *)&rxdp++->read, dma_addr1);
345 #ifdef CC_AVX512_SUPPORT
347 struct rte_mbuf *mb0, *mb1, *mb2, *mb3;
348 struct rte_mbuf *mb4, *mb5, *mb6, *mb7;
349 __m512i dma_addr0_3, dma_addr4_7;
350 __m512i hdr_room = _mm512_set1_epi64(RTE_PKTMBUF_HEADROOM);
351 /* Initialize the mbufs in vector, process 8 mbufs in one loop */
352 for (i = 0; i < IAVF_RXQ_REARM_THRESH;
353 i += 8, rxp += 8, rxdp += 8) {
354 __m128i vaddr0, vaddr1, vaddr2, vaddr3;
355 __m128i vaddr4, vaddr5, vaddr6, vaddr7;
356 __m256i vaddr0_1, vaddr2_3;
357 __m256i vaddr4_5, vaddr6_7;
358 __m512i vaddr0_3, vaddr4_7;
369 /* load buf_addr(lo 64bit) and buf_iova(hi 64bit) */
370 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, buf_iova) !=
371 offsetof(struct rte_mbuf, buf_addr) + 8);
372 vaddr0 = _mm_loadu_si128((__m128i *)&mb0->buf_addr);
373 vaddr1 = _mm_loadu_si128((__m128i *)&mb1->buf_addr);
374 vaddr2 = _mm_loadu_si128((__m128i *)&mb2->buf_addr);
375 vaddr3 = _mm_loadu_si128((__m128i *)&mb3->buf_addr);
376 vaddr4 = _mm_loadu_si128((__m128i *)&mb4->buf_addr);
377 vaddr5 = _mm_loadu_si128((__m128i *)&mb5->buf_addr);
378 vaddr6 = _mm_loadu_si128((__m128i *)&mb6->buf_addr);
379 vaddr7 = _mm_loadu_si128((__m128i *)&mb7->buf_addr);
382 * merge 0 & 1, by casting 0 to 256-bit and inserting 1
383 * into the high lanes. Similarly for 2 & 3, and so on.
386 _mm256_inserti128_si256(_mm256_castsi128_si256(vaddr0),
389 _mm256_inserti128_si256(_mm256_castsi128_si256(vaddr2),
392 _mm256_inserti128_si256(_mm256_castsi128_si256(vaddr4),
395 _mm256_inserti128_si256(_mm256_castsi128_si256(vaddr6),
398 _mm512_inserti64x4(_mm512_castsi256_si512(vaddr0_1),
401 _mm512_inserti64x4(_mm512_castsi256_si512(vaddr4_5),
404 /* convert pa to dma_addr hdr/data */
405 dma_addr0_3 = _mm512_unpackhi_epi64(vaddr0_3, vaddr0_3);
406 dma_addr4_7 = _mm512_unpackhi_epi64(vaddr4_7, vaddr4_7);
408 /* add headroom to pa values */
409 dma_addr0_3 = _mm512_add_epi64(dma_addr0_3, hdr_room);
410 dma_addr4_7 = _mm512_add_epi64(dma_addr4_7, hdr_room);
412 /* flush desc with pa dma_addr */
413 _mm512_store_si512((__m512i *)&rxdp->read, dma_addr0_3);
414 _mm512_store_si512((__m512i *)&(rxdp + 4)->read, dma_addr4_7);
419 struct rte_mbuf *mb0, *mb1, *mb2, *mb3;
420 __m256i dma_addr0_1, dma_addr2_3;
421 __m256i hdr_room = _mm256_set1_epi64x(RTE_PKTMBUF_HEADROOM);
422 /* Initialize the mbufs in vector, process 4 mbufs in one loop */
423 for (i = 0; i < IAVF_RXQ_REARM_THRESH;
424 i += 4, rxp += 4, rxdp += 4) {
425 __m128i vaddr0, vaddr1, vaddr2, vaddr3;
426 __m256i vaddr0_1, vaddr2_3;
433 /* load buf_addr(lo 64bit) and buf_iova(hi 64bit) */
434 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, buf_iova) !=
435 offsetof(struct rte_mbuf, buf_addr) + 8);
436 vaddr0 = _mm_loadu_si128((__m128i *)&mb0->buf_addr);
437 vaddr1 = _mm_loadu_si128((__m128i *)&mb1->buf_addr);
438 vaddr2 = _mm_loadu_si128((__m128i *)&mb2->buf_addr);
439 vaddr3 = _mm_loadu_si128((__m128i *)&mb3->buf_addr);
442 * merge 0 & 1, by casting 0 to 256-bit and inserting 1
443 * into the high lanes. Similarly for 2 & 3
446 _mm256_inserti128_si256(_mm256_castsi128_si256(vaddr0),
449 _mm256_inserti128_si256(_mm256_castsi128_si256(vaddr2),
452 /* convert pa to dma_addr hdr/data */
453 dma_addr0_1 = _mm256_unpackhi_epi64(vaddr0_1, vaddr0_1);
454 dma_addr2_3 = _mm256_unpackhi_epi64(vaddr2_3, vaddr2_3);
456 /* add headroom to pa values */
457 dma_addr0_1 = _mm256_add_epi64(dma_addr0_1, hdr_room);
458 dma_addr2_3 = _mm256_add_epi64(dma_addr2_3, hdr_room);
460 /* flush desc with pa dma_addr */
461 _mm256_store_si256((__m256i *)&rxdp->read, dma_addr0_1);
462 _mm256_store_si256((__m256i *)&(rxdp + 2)->read, dma_addr2_3);
468 rxq->rxrearm_start += IAVF_RXQ_REARM_THRESH;
469 if (rxq->rxrearm_start >= rxq->nb_rx_desc)
470 rxq->rxrearm_start = 0;
472 rxq->rxrearm_nb -= IAVF_RXQ_REARM_THRESH;
474 rx_id = (uint16_t)((rxq->rxrearm_start == 0) ?
475 (rxq->nb_rx_desc - 1) : (rxq->rxrearm_start - 1));
477 /* Update the tail pointer on the NIC */
478 IAVF_PCI_REG_WRITE(rxq->qrx_tail, rx_id);