net/mlx5: fix errno typos in comments
[dpdk.git] / drivers / net / iavf / iavf_rxtx_vec_sse.c
1 /* SPDX-License-Identifier: BSD-3-Clause
2  * Copyright(c) 2017 Intel Corporation
3  */
4
5 #include <stdint.h>
6 #include <rte_ethdev_driver.h>
7 #include <rte_malloc.h>
8
9 #include "base/iavf_prototype.h"
10 #include "base/iavf_type.h"
11 #include "iavf.h"
12 #include "iavf_rxtx.h"
13 #include "iavf_rxtx_vec_common.h"
14
15 #include <tmmintrin.h>
16
17 #ifndef __INTEL_COMPILER
18 #pragma GCC diagnostic ignored "-Wcast-qual"
19 #endif
20
21 static inline void
22 iavf_rxq_rearm(struct iavf_rx_queue *rxq)
23 {
24         int i;
25         uint16_t rx_id;
26
27         volatile union iavf_rx_desc *rxdp;
28         struct rte_mbuf **rxp = &rxq->sw_ring[rxq->rxrearm_start];
29         struct rte_mbuf *mb0, *mb1;
30         __m128i hdr_room = _mm_set_epi64x(RTE_PKTMBUF_HEADROOM,
31                         RTE_PKTMBUF_HEADROOM);
32         __m128i dma_addr0, dma_addr1;
33
34         rxdp = rxq->rx_ring + rxq->rxrearm_start;
35
36         /* Pull 'n' more MBUFs into the software ring */
37         if (rte_mempool_get_bulk(rxq->mp, (void *)rxp,
38                                  rxq->rx_free_thresh) < 0) {
39                 if (rxq->rxrearm_nb + rxq->rx_free_thresh >= rxq->nb_rx_desc) {
40                         dma_addr0 = _mm_setzero_si128();
41                         for (i = 0; i < IAVF_VPMD_DESCS_PER_LOOP; i++) {
42                                 rxp[i] = &rxq->fake_mbuf;
43                                 _mm_store_si128((__m128i *)&rxdp[i].read,
44                                                 dma_addr0);
45                         }
46                 }
47                 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed +=
48                         rxq->rx_free_thresh;
49                 return;
50         }
51
52         /* Initialize the mbufs in vector, process 2 mbufs in one loop */
53         for (i = 0; i < rxq->rx_free_thresh; i += 2, rxp += 2) {
54                 __m128i vaddr0, vaddr1;
55
56                 mb0 = rxp[0];
57                 mb1 = rxp[1];
58
59                 /* load buf_addr(lo 64bit) and buf_iova(hi 64bit) */
60                 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, buf_iova) !=
61                                 offsetof(struct rte_mbuf, buf_addr) + 8);
62                 vaddr0 = _mm_loadu_si128((__m128i *)&mb0->buf_addr);
63                 vaddr1 = _mm_loadu_si128((__m128i *)&mb1->buf_addr);
64
65                 /* convert pa to dma_addr hdr/data */
66                 dma_addr0 = _mm_unpackhi_epi64(vaddr0, vaddr0);
67                 dma_addr1 = _mm_unpackhi_epi64(vaddr1, vaddr1);
68
69                 /* add headroom to pa values */
70                 dma_addr0 = _mm_add_epi64(dma_addr0, hdr_room);
71                 dma_addr1 = _mm_add_epi64(dma_addr1, hdr_room);
72
73                 /* flush desc with pa dma_addr */
74                 _mm_store_si128((__m128i *)&rxdp++->read, dma_addr0);
75                 _mm_store_si128((__m128i *)&rxdp++->read, dma_addr1);
76         }
77
78         rxq->rxrearm_start += rxq->rx_free_thresh;
79         if (rxq->rxrearm_start >= rxq->nb_rx_desc)
80                 rxq->rxrearm_start = 0;
81
82         rxq->rxrearm_nb -= rxq->rx_free_thresh;
83
84         rx_id = (uint16_t)((rxq->rxrearm_start == 0) ?
85                            (rxq->nb_rx_desc - 1) : (rxq->rxrearm_start - 1));
86
87         PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_tail=%u "
88                    "rearm_start=%u rearm_nb=%u",
89                    rxq->port_id, rxq->queue_id,
90                    rx_id, rxq->rxrearm_start, rxq->rxrearm_nb);
91
92         /* Update the tail pointer on the NIC */
93         IAVF_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
94 }
95
96 static inline void
97 desc_to_olflags_v(struct iavf_rx_queue *rxq, __m128i descs[4],
98                   struct rte_mbuf **rx_pkts)
99 {
100         const __m128i mbuf_init = _mm_set_epi64x(0, rxq->mbuf_initializer);
101         __m128i rearm0, rearm1, rearm2, rearm3;
102
103         __m128i vlan0, vlan1, rss, l3_l4e;
104
105         /* mask everything except RSS, flow director and VLAN flags
106          * bit2 is for VLAN tag, bit11 for flow director indication
107          * bit13:12 for RSS indication.
108          */
109         const __m128i rss_vlan_msk = _mm_set_epi32(
110                         0x1c03804, 0x1c03804, 0x1c03804, 0x1c03804);
111
112         const __m128i cksum_mask = _mm_set_epi32(
113                         PKT_RX_IP_CKSUM_GOOD | PKT_RX_IP_CKSUM_BAD |
114                         PKT_RX_L4_CKSUM_GOOD | PKT_RX_L4_CKSUM_BAD |
115                         PKT_RX_EIP_CKSUM_BAD,
116                         PKT_RX_IP_CKSUM_GOOD | PKT_RX_IP_CKSUM_BAD |
117                         PKT_RX_L4_CKSUM_GOOD | PKT_RX_L4_CKSUM_BAD |
118                         PKT_RX_EIP_CKSUM_BAD,
119                         PKT_RX_IP_CKSUM_GOOD | PKT_RX_IP_CKSUM_BAD |
120                         PKT_RX_L4_CKSUM_GOOD | PKT_RX_L4_CKSUM_BAD |
121                         PKT_RX_EIP_CKSUM_BAD,
122                         PKT_RX_IP_CKSUM_GOOD | PKT_RX_IP_CKSUM_BAD |
123                         PKT_RX_L4_CKSUM_GOOD | PKT_RX_L4_CKSUM_BAD |
124                         PKT_RX_EIP_CKSUM_BAD);
125
126         /* map rss and vlan type to rss hash and vlan flag */
127         const __m128i vlan_flags = _mm_set_epi8(0, 0, 0, 0,
128                         0, 0, 0, 0,
129                         0, 0, 0, PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED,
130                         0, 0, 0, 0);
131
132         const __m128i rss_flags = _mm_set_epi8(0, 0, 0, 0,
133                         0, 0, 0, 0,
134                         PKT_RX_RSS_HASH | PKT_RX_FDIR, PKT_RX_RSS_HASH, 0, 0,
135                         0, 0, PKT_RX_FDIR, 0);
136
137         const __m128i l3_l4e_flags = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0,
138                         /* shift right 1 bit to make sure it not exceed 255 */
139                         (PKT_RX_EIP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD |
140                          PKT_RX_IP_CKSUM_BAD) >> 1,
141                         (PKT_RX_IP_CKSUM_GOOD | PKT_RX_EIP_CKSUM_BAD |
142                          PKT_RX_L4_CKSUM_BAD) >> 1,
143                         (PKT_RX_EIP_CKSUM_BAD | PKT_RX_IP_CKSUM_BAD) >> 1,
144                         (PKT_RX_IP_CKSUM_GOOD | PKT_RX_EIP_CKSUM_BAD) >> 1,
145                         (PKT_RX_L4_CKSUM_BAD | PKT_RX_IP_CKSUM_BAD) >> 1,
146                         (PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_BAD) >> 1,
147                         PKT_RX_IP_CKSUM_BAD >> 1,
148                         (PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD) >> 1);
149
150         vlan0 = _mm_unpackhi_epi32(descs[0], descs[1]);
151         vlan1 = _mm_unpackhi_epi32(descs[2], descs[3]);
152         vlan0 = _mm_unpacklo_epi64(vlan0, vlan1);
153
154         vlan1 = _mm_and_si128(vlan0, rss_vlan_msk);
155         vlan0 = _mm_shuffle_epi8(vlan_flags, vlan1);
156
157         rss = _mm_srli_epi32(vlan1, 11);
158         rss = _mm_shuffle_epi8(rss_flags, rss);
159
160         l3_l4e = _mm_srli_epi32(vlan1, 22);
161         l3_l4e = _mm_shuffle_epi8(l3_l4e_flags, l3_l4e);
162         /* then we shift left 1 bit */
163         l3_l4e = _mm_slli_epi32(l3_l4e, 1);
164         /* we need to mask out the reduntant bits */
165         l3_l4e = _mm_and_si128(l3_l4e, cksum_mask);
166
167         vlan0 = _mm_or_si128(vlan0, rss);
168         vlan0 = _mm_or_si128(vlan0, l3_l4e);
169
170         /* At this point, we have the 4 sets of flags in the low 16-bits
171          * of each 32-bit value in vlan0.
172          * We want to extract these, and merge them with the mbuf init data
173          * so we can do a single 16-byte write to the mbuf to set the flags
174          * and all the other initialization fields. Extracting the
175          * appropriate flags means that we have to do a shift and blend for
176          * each mbuf before we do the write.
177          */
178         rearm0 = _mm_blend_epi16(mbuf_init, _mm_slli_si128(vlan0, 8), 0x10);
179         rearm1 = _mm_blend_epi16(mbuf_init, _mm_slli_si128(vlan0, 4), 0x10);
180         rearm2 = _mm_blend_epi16(mbuf_init, vlan0, 0x10);
181         rearm3 = _mm_blend_epi16(mbuf_init, _mm_srli_si128(vlan0, 4), 0x10);
182
183         /* write the rearm data and the olflags in one write */
184         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, ol_flags) !=
185                         offsetof(struct rte_mbuf, rearm_data) + 8);
186         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, rearm_data) !=
187                         RTE_ALIGN(offsetof(struct rte_mbuf, rearm_data), 16));
188         _mm_store_si128((__m128i *)&rx_pkts[0]->rearm_data, rearm0);
189         _mm_store_si128((__m128i *)&rx_pkts[1]->rearm_data, rearm1);
190         _mm_store_si128((__m128i *)&rx_pkts[2]->rearm_data, rearm2);
191         _mm_store_si128((__m128i *)&rx_pkts[3]->rearm_data, rearm3);
192 }
193
194 #define PKTLEN_SHIFT     10
195
196 static inline void
197 desc_to_ptype_v(__m128i descs[4], struct rte_mbuf **rx_pkts)
198 {
199         __m128i ptype0 = _mm_unpackhi_epi64(descs[0], descs[1]);
200         __m128i ptype1 = _mm_unpackhi_epi64(descs[2], descs[3]);
201         static const uint32_t type_table[UINT8_MAX + 1] __rte_cache_aligned = {
202                 /* [0] reserved */
203                 [1] = RTE_PTYPE_L2_ETHER,
204                 /* [2] - [21] reserved */
205                 [22] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
206                         RTE_PTYPE_L4_FRAG,
207                 [23] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
208                         RTE_PTYPE_L4_NONFRAG,
209                 [24] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
210                         RTE_PTYPE_L4_UDP,
211                 /* [25] reserved */
212                 [26] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
213                         RTE_PTYPE_L4_TCP,
214                 [27] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
215                         RTE_PTYPE_L4_SCTP,
216                 [28] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
217                         RTE_PTYPE_L4_ICMP,
218                 /* All others reserved */
219         };
220
221         ptype0 = _mm_srli_epi64(ptype0, 30);
222         ptype1 = _mm_srli_epi64(ptype1, 30);
223
224         rx_pkts[0]->packet_type = type_table[_mm_extract_epi8(ptype0, 0)];
225         rx_pkts[1]->packet_type = type_table[_mm_extract_epi8(ptype0, 8)];
226         rx_pkts[2]->packet_type = type_table[_mm_extract_epi8(ptype1, 0)];
227         rx_pkts[3]->packet_type = type_table[_mm_extract_epi8(ptype1, 8)];
228 }
229
230 /* Notice:
231  * - nb_pkts < IAVF_VPMD_DESCS_PER_LOOP, just return no packet
232  * - nb_pkts > IAVF_VPMD_RX_MAX_BURST, only scan IAVF_VPMD_RX_MAX_BURST
233  *   numbers of DD bits
234  */
235 static inline uint16_t
236 _recv_raw_pkts_vec(struct iavf_rx_queue *rxq, struct rte_mbuf **rx_pkts,
237                    uint16_t nb_pkts, uint8_t *split_packet)
238 {
239         volatile union iavf_rx_desc *rxdp;
240         struct rte_mbuf **sw_ring;
241         uint16_t nb_pkts_recd;
242         int pos;
243         uint64_t var;
244         __m128i shuf_msk;
245
246         __m128i crc_adjust = _mm_set_epi16(
247                                 0, 0, 0,    /* ignore non-length fields */
248                                 -rxq->crc_len, /* sub crc on data_len */
249                                 0,          /* ignore high-16bits of pkt_len */
250                                 -rxq->crc_len, /* sub crc on pkt_len */
251                                 0, 0            /* ignore pkt_type field */
252                         );
253         /* compile-time check the above crc_adjust layout is correct.
254          * NOTE: the first field (lowest address) is given last in set_epi16
255          * call above.
256          */
257         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, pkt_len) !=
258                         offsetof(struct rte_mbuf, rx_descriptor_fields1) + 4);
259         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, data_len) !=
260                         offsetof(struct rte_mbuf, rx_descriptor_fields1) + 8);
261         __m128i dd_check, eop_check;
262
263         /* nb_pkts shall be less equal than IAVF_VPMD_RX_MAX_BURST */
264         nb_pkts = RTE_MIN(nb_pkts, IAVF_VPMD_RX_MAX_BURST);
265
266         /* nb_pkts has to be floor-aligned to IAVF_VPMD_DESCS_PER_LOOP */
267         nb_pkts = RTE_ALIGN_FLOOR(nb_pkts, IAVF_VPMD_DESCS_PER_LOOP);
268
269         /* Just the act of getting into the function from the application is
270          * going to cost about 7 cycles
271          */
272         rxdp = rxq->rx_ring + rxq->rx_tail;
273
274         rte_prefetch0(rxdp);
275
276         /* See if we need to rearm the RX queue - gives the prefetch a bit
277          * of time to act
278          */
279         if (rxq->rxrearm_nb > rxq->rx_free_thresh)
280                 iavf_rxq_rearm(rxq);
281
282         /* Before we start moving massive data around, check to see if
283          * there is actually a packet available
284          */
285         if (!(rxdp->wb.qword1.status_error_len &
286               rte_cpu_to_le_32(1 << IAVF_RX_DESC_STATUS_DD_SHIFT)))
287                 return 0;
288
289         /* 4 packets DD mask */
290         dd_check = _mm_set_epi64x(0x0000000100000001LL, 0x0000000100000001LL);
291
292         /* 4 packets EOP mask */
293         eop_check = _mm_set_epi64x(0x0000000200000002LL, 0x0000000200000002LL);
294
295         /* mask to shuffle from desc. to mbuf */
296         shuf_msk = _mm_set_epi8(
297                 7, 6, 5, 4,  /* octet 4~7, 32bits rss */
298                 3, 2,        /* octet 2~3, low 16 bits vlan_macip */
299                 15, 14,      /* octet 15~14, 16 bits data_len */
300                 0xFF, 0xFF,  /* skip high 16 bits pkt_len, zero out */
301                 15, 14,      /* octet 15~14, low 16 bits pkt_len */
302                 0xFF, 0xFF, 0xFF, 0xFF /* pkt_type set as unknown */
303                 );
304         /* Compile-time verify the shuffle mask
305          * NOTE: some field positions already verified above, but duplicated
306          * here for completeness in case of future modifications.
307          */
308         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, pkt_len) !=
309                         offsetof(struct rte_mbuf, rx_descriptor_fields1) + 4);
310         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, data_len) !=
311                         offsetof(struct rte_mbuf, rx_descriptor_fields1) + 8);
312         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, vlan_tci) !=
313                         offsetof(struct rte_mbuf, rx_descriptor_fields1) + 10);
314         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, hash) !=
315                         offsetof(struct rte_mbuf, rx_descriptor_fields1) + 12);
316
317         /* Cache is empty -> need to scan the buffer rings, but first move
318          * the next 'n' mbufs into the cache
319          */
320         sw_ring = &rxq->sw_ring[rxq->rx_tail];
321
322         /* A. load 4 packet in one loop
323          * [A*. mask out 4 unused dirty field in desc]
324          * B. copy 4 mbuf point from swring to rx_pkts
325          * C. calc the number of DD bits among the 4 packets
326          * [C*. extract the end-of-packet bit, if requested]
327          * D. fill info. from desc to mbuf
328          */
329
330         for (pos = 0, nb_pkts_recd = 0; pos < nb_pkts;
331              pos += IAVF_VPMD_DESCS_PER_LOOP,
332              rxdp += IAVF_VPMD_DESCS_PER_LOOP) {
333                 __m128i descs[IAVF_VPMD_DESCS_PER_LOOP];
334                 __m128i pkt_mb1, pkt_mb2, pkt_mb3, pkt_mb4;
335                 __m128i zero, staterr, sterr_tmp1, sterr_tmp2;
336                 /* 2 64 bit or 4 32 bit mbuf pointers in one XMM reg. */
337                 __m128i mbp1;
338 #if defined(RTE_ARCH_X86_64)
339                 __m128i mbp2;
340 #endif
341
342                 /* B.1 load 2 (64 bit) or 4 (32 bit) mbuf points */
343                 mbp1 = _mm_loadu_si128((__m128i *)&sw_ring[pos]);
344                 /* Read desc statuses backwards to avoid race condition */
345                 /* A.1 load 4 pkts desc */
346                 descs[3] = _mm_loadu_si128((__m128i *)(rxdp + 3));
347                 rte_compiler_barrier();
348
349                 /* B.2 copy 2 64 bit or 4 32 bit mbuf point into rx_pkts */
350                 _mm_storeu_si128((__m128i *)&rx_pkts[pos], mbp1);
351
352 #if defined(RTE_ARCH_X86_64)
353                 /* B.1 load 2 64 bit mbuf points */
354                 mbp2 = _mm_loadu_si128((__m128i *)&sw_ring[pos + 2]);
355 #endif
356
357                 descs[2] = _mm_loadu_si128((__m128i *)(rxdp + 2));
358                 rte_compiler_barrier();
359                 /* B.1 load 2 mbuf point */
360                 descs[1] = _mm_loadu_si128((__m128i *)(rxdp + 1));
361                 rte_compiler_barrier();
362                 descs[0] = _mm_loadu_si128((__m128i *)(rxdp));
363
364 #if defined(RTE_ARCH_X86_64)
365                 /* B.2 copy 2 mbuf point into rx_pkts  */
366                 _mm_storeu_si128((__m128i *)&rx_pkts[pos + 2], mbp2);
367 #endif
368
369                 if (split_packet) {
370                         rte_mbuf_prefetch_part2(rx_pkts[pos]);
371                         rte_mbuf_prefetch_part2(rx_pkts[pos + 1]);
372                         rte_mbuf_prefetch_part2(rx_pkts[pos + 2]);
373                         rte_mbuf_prefetch_part2(rx_pkts[pos + 3]);
374                 }
375
376                 /* avoid compiler reorder optimization */
377                 rte_compiler_barrier();
378
379                 /* pkt 3,4 shift the pktlen field to be 16-bit aligned*/
380                 const __m128i len3 = _mm_slli_epi32(descs[3], PKTLEN_SHIFT);
381                 const __m128i len2 = _mm_slli_epi32(descs[2], PKTLEN_SHIFT);
382
383                 /* merge the now-aligned packet length fields back in */
384                 descs[3] = _mm_blend_epi16(descs[3], len3, 0x80);
385                 descs[2] = _mm_blend_epi16(descs[2], len2, 0x80);
386
387                 /* D.1 pkt 3,4 convert format from desc to pktmbuf */
388                 pkt_mb4 = _mm_shuffle_epi8(descs[3], shuf_msk);
389                 pkt_mb3 = _mm_shuffle_epi8(descs[2], shuf_msk);
390
391                 /* C.1 4=>2 status err info only */
392                 sterr_tmp2 = _mm_unpackhi_epi32(descs[3], descs[2]);
393                 sterr_tmp1 = _mm_unpackhi_epi32(descs[1], descs[0]);
394
395                 desc_to_olflags_v(rxq, descs, &rx_pkts[pos]);
396
397                 /* D.2 pkt 3,4 set in_port/nb_seg and remove crc */
398                 pkt_mb4 = _mm_add_epi16(pkt_mb4, crc_adjust);
399                 pkt_mb3 = _mm_add_epi16(pkt_mb3, crc_adjust);
400
401                 /* pkt 1,2 shift the pktlen field to be 16-bit aligned*/
402                 const __m128i len1 = _mm_slli_epi32(descs[1], PKTLEN_SHIFT);
403                 const __m128i len0 = _mm_slli_epi32(descs[0], PKTLEN_SHIFT);
404
405                 /* merge the now-aligned packet length fields back in */
406                 descs[1] = _mm_blend_epi16(descs[1], len1, 0x80);
407                 descs[0] = _mm_blend_epi16(descs[0], len0, 0x80);
408
409                 /* D.1 pkt 1,2 convert format from desc to pktmbuf */
410                 pkt_mb2 = _mm_shuffle_epi8(descs[1], shuf_msk);
411                 pkt_mb1 = _mm_shuffle_epi8(descs[0], shuf_msk);
412
413                 /* C.2 get 4 pkts status err value  */
414                 zero = _mm_xor_si128(dd_check, dd_check);
415                 staterr = _mm_unpacklo_epi32(sterr_tmp1, sterr_tmp2);
416
417                 /* D.3 copy final 3,4 data to rx_pkts */
418                 _mm_storeu_si128(
419                         (void *)&rx_pkts[pos + 3]->rx_descriptor_fields1,
420                         pkt_mb4);
421                 _mm_storeu_si128(
422                         (void *)&rx_pkts[pos + 2]->rx_descriptor_fields1,
423                         pkt_mb3);
424
425                 /* D.2 pkt 1,2 remove crc */
426                 pkt_mb2 = _mm_add_epi16(pkt_mb2, crc_adjust);
427                 pkt_mb1 = _mm_add_epi16(pkt_mb1, crc_adjust);
428
429                 /* C* extract and record EOP bit */
430                 if (split_packet) {
431                         __m128i eop_shuf_mask = _mm_set_epi8(
432                                         0xFF, 0xFF, 0xFF, 0xFF,
433                                         0xFF, 0xFF, 0xFF, 0xFF,
434                                         0xFF, 0xFF, 0xFF, 0xFF,
435                                         0x04, 0x0C, 0x00, 0x08
436                                         );
437
438                         /* and with mask to extract bits, flipping 1-0 */
439                         __m128i eop_bits = _mm_andnot_si128(staterr, eop_check);
440                         /* the staterr values are not in order, as the count
441                          * count of dd bits doesn't care. However, for end of
442                          * packet tracking, we do care, so shuffle. This also
443                          * compresses the 32-bit values to 8-bit
444                          */
445                         eop_bits = _mm_shuffle_epi8(eop_bits, eop_shuf_mask);
446                         /* store the resulting 32-bit value */
447                         *(int *)split_packet = _mm_cvtsi128_si32(eop_bits);
448                         split_packet += IAVF_VPMD_DESCS_PER_LOOP;
449                 }
450
451                 /* C.3 calc available number of desc */
452                 staterr = _mm_and_si128(staterr, dd_check);
453                 staterr = _mm_packs_epi32(staterr, zero);
454
455                 /* D.3 copy final 1,2 data to rx_pkts */
456                 _mm_storeu_si128(
457                         (void *)&rx_pkts[pos + 1]->rx_descriptor_fields1,
458                         pkt_mb2);
459                 _mm_storeu_si128((void *)&rx_pkts[pos]->rx_descriptor_fields1,
460                                  pkt_mb1);
461                 desc_to_ptype_v(descs, &rx_pkts[pos]);
462                 /* C.4 calc avaialbe number of desc */
463                 var = __builtin_popcountll(_mm_cvtsi128_si64(staterr));
464                 nb_pkts_recd += var;
465                 if (likely(var != IAVF_VPMD_DESCS_PER_LOOP))
466                         break;
467         }
468
469         /* Update our internal tail pointer */
470         rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_pkts_recd);
471         rxq->rx_tail = (uint16_t)(rxq->rx_tail & (rxq->nb_rx_desc - 1));
472         rxq->rxrearm_nb = (uint16_t)(rxq->rxrearm_nb + nb_pkts_recd);
473
474         return nb_pkts_recd;
475 }
476
477 /* Notice:
478  * - nb_pkts < IAVF_DESCS_PER_LOOP, just return no packet
479  * - nb_pkts > IAVF_VPMD_RX_MAX_BURST, only scan IAVF_VPMD_RX_MAX_BURST
480  *   numbers of DD bits
481  */
482 uint16_t
483 iavf_recv_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts,
484                   uint16_t nb_pkts)
485 {
486         return _recv_raw_pkts_vec(rx_queue, rx_pkts, nb_pkts, NULL);
487 }
488
489 /* vPMD receive routine that reassembles scattered packets
490  * Notice:
491  * - nb_pkts < IAVF_VPMD_DESCS_PER_LOOP, just return no packet
492  * - nb_pkts > VPMD_RX_MAX_BURST, only scan IAVF_VPMD_RX_MAX_BURST
493  *   numbers of DD bits
494  */
495 uint16_t
496 iavf_recv_scattered_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts,
497                             uint16_t nb_pkts)
498 {
499         struct iavf_rx_queue *rxq = rx_queue;
500         uint8_t split_flags[IAVF_VPMD_RX_MAX_BURST] = {0};
501         unsigned int i = 0;
502
503         /* get some new buffers */
504         uint16_t nb_bufs = _recv_raw_pkts_vec(rxq, rx_pkts, nb_pkts,
505                                               split_flags);
506         if (nb_bufs == 0)
507                 return 0;
508
509         /* happy day case, full burst + no packets to be joined */
510         const uint64_t *split_fl64 = (uint64_t *)split_flags;
511
512         if (!rxq->pkt_first_seg &&
513             split_fl64[0] == 0 && split_fl64[1] == 0 &&
514             split_fl64[2] == 0 && split_fl64[3] == 0)
515                 return nb_bufs;
516
517         /* reassemble any packets that need reassembly*/
518         if (!rxq->pkt_first_seg) {
519                 /* find the first split flag, and only reassemble then*/
520                 while (i < nb_bufs && !split_flags[i])
521                         i++;
522                 if (i == nb_bufs)
523                         return nb_bufs;
524         }
525         return i + reassemble_packets(rxq, &rx_pkts[i], nb_bufs - i,
526                 &split_flags[i]);
527 }
528
529 static inline void
530 vtx1(volatile struct iavf_tx_desc *txdp, struct rte_mbuf *pkt, uint64_t flags)
531 {
532         uint64_t high_qw =
533                         (IAVF_TX_DESC_DTYPE_DATA |
534                          ((uint64_t)flags  << IAVF_TXD_QW1_CMD_SHIFT) |
535                          ((uint64_t)pkt->data_len <<
536                           IAVF_TXD_QW1_TX_BUF_SZ_SHIFT));
537
538         __m128i descriptor = _mm_set_epi64x(high_qw,
539                                             pkt->buf_iova + pkt->data_off);
540         _mm_store_si128((__m128i *)txdp, descriptor);
541 }
542
543 static inline void
544 iavf_vtx(volatile struct iavf_tx_desc *txdp, struct rte_mbuf **pkt,
545         uint16_t nb_pkts,  uint64_t flags)
546 {
547         int i;
548
549         for (i = 0; i < nb_pkts; ++i, ++txdp, ++pkt)
550                 vtx1(txdp, *pkt, flags);
551 }
552
553 uint16_t
554 iavf_xmit_fixed_burst_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
555                          uint16_t nb_pkts)
556 {
557         struct iavf_tx_queue *txq = (struct iavf_tx_queue *)tx_queue;
558         volatile struct iavf_tx_desc *txdp;
559         struct iavf_tx_entry *txep;
560         uint16_t n, nb_commit, tx_id;
561         uint64_t flags = IAVF_TX_DESC_CMD_EOP | 0x04;  /* bit 2 must be set */
562         uint64_t rs = IAVF_TX_DESC_CMD_RS | flags;
563         int i;
564
565         /* cross rx_thresh boundary is not allowed */
566         nb_pkts = RTE_MIN(nb_pkts, txq->rs_thresh);
567
568         if (txq->nb_free < txq->free_thresh)
569                 iavf_tx_free_bufs(txq);
570
571         nb_pkts = (uint16_t)RTE_MIN(txq->nb_free, nb_pkts);
572         if (unlikely(nb_pkts == 0))
573                 return 0;
574         nb_commit = nb_pkts;
575
576         tx_id = txq->tx_tail;
577         txdp = &txq->tx_ring[tx_id];
578         txep = &txq->sw_ring[tx_id];
579
580         txq->nb_free = (uint16_t)(txq->nb_free - nb_pkts);
581
582         n = (uint16_t)(txq->nb_tx_desc - tx_id);
583         if (nb_commit >= n) {
584                 tx_backlog_entry(txep, tx_pkts, n);
585
586                 for (i = 0; i < n - 1; ++i, ++tx_pkts, ++txdp)
587                         vtx1(txdp, *tx_pkts, flags);
588
589                 vtx1(txdp, *tx_pkts++, rs);
590
591                 nb_commit = (uint16_t)(nb_commit - n);
592
593                 tx_id = 0;
594                 txq->next_rs = (uint16_t)(txq->rs_thresh - 1);
595
596                 /* avoid reach the end of ring */
597                 txdp = &txq->tx_ring[tx_id];
598                 txep = &txq->sw_ring[tx_id];
599         }
600
601         tx_backlog_entry(txep, tx_pkts, nb_commit);
602
603         iavf_vtx(txdp, tx_pkts, nb_commit, flags);
604
605         tx_id = (uint16_t)(tx_id + nb_commit);
606         if (tx_id > txq->next_rs) {
607                 txq->tx_ring[txq->next_rs].cmd_type_offset_bsz |=
608                         rte_cpu_to_le_64(((uint64_t)IAVF_TX_DESC_CMD_RS) <<
609                                          IAVF_TXD_QW1_CMD_SHIFT);
610                 txq->next_rs =
611                         (uint16_t)(txq->next_rs + txq->rs_thresh);
612         }
613
614         txq->tx_tail = tx_id;
615
616         PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u tx_tail=%u nb_pkts=%u",
617                    txq->port_id, txq->queue_id, tx_id, nb_pkts);
618
619         IAVF_PCI_REG_WRITE(txq->qtx_tail, txq->tx_tail);
620
621         return nb_pkts;
622 }
623
624 static void __attribute__((cold))
625 iavf_rx_queue_release_mbufs_sse(struct iavf_rx_queue *rxq)
626 {
627         _iavf_rx_queue_release_mbufs_vec(rxq);
628 }
629
630 static void __attribute__((cold))
631 iavf_tx_queue_release_mbufs_sse(struct iavf_tx_queue *txq)
632 {
633         _iavf_tx_queue_release_mbufs_vec(txq);
634 }
635
636 static const struct iavf_rxq_ops sse_vec_rxq_ops = {
637         .release_mbufs = iavf_rx_queue_release_mbufs_sse,
638 };
639
640 static const struct iavf_txq_ops sse_vec_txq_ops = {
641         .release_mbufs = iavf_tx_queue_release_mbufs_sse,
642 };
643
644 int __attribute__((cold))
645 iavf_txq_vec_setup(struct iavf_tx_queue *txq)
646 {
647         txq->ops = &sse_vec_txq_ops;
648         return 0;
649 }
650
651 int __attribute__((cold))
652 iavf_rxq_vec_setup(struct iavf_rx_queue *rxq)
653 {
654         rxq->ops = &sse_vec_rxq_ops;
655         return iavf_rxq_vec_setup_default(rxq);
656 }