drivers/net/iavf/iavf_rxtx_vec_sse.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2017 Intel Corporation
   3  */
   4
   5 #include <stdint.h>
   6 #include <rte_ethdev_driver.h>
   7 #include <rte_malloc.h>
   8
   9 #include "iavf.h"
  10 #include "iavf_rxtx.h"
  11 #include "iavf_rxtx_vec_common.h"
  12
  13 #include <tmmintrin.h>
  14
  15 #ifndef __INTEL_COMPILER
  16 #pragma GCC diagnostic ignored "-Wcast-qual"
  17 #endif
  18
  19 static inline void
  20 iavf_rxq_rearm(struct iavf_rx_queue *rxq)
  21 {
  22         int i;
  23         uint16_t rx_id;
  24
  25         volatile union iavf_rx_desc *rxdp;
  26         struct rte_mbuf **rxp = &rxq->sw_ring[rxq->rxrearm_start];
  27         struct rte_mbuf *mb0, *mb1;
  28         __m128i hdr_room = _mm_set_epi64x(RTE_PKTMBUF_HEADROOM,
  29                         RTE_PKTMBUF_HEADROOM);
  30         __m128i dma_addr0, dma_addr1;
  31
  32         rxdp = rxq->rx_ring + rxq->rxrearm_start;
  33
  34         /* Pull 'n' more MBUFs into the software ring */
  35         if (rte_mempool_get_bulk(rxq->mp, (void *)rxp,
  36                                  rxq->rx_free_thresh) < 0) {
  37                 if (rxq->rxrearm_nb + rxq->rx_free_thresh >= rxq->nb_rx_desc) {
  38                         dma_addr0 = _mm_setzero_si128();
  39                         for (i = 0; i < IAVF_VPMD_DESCS_PER_LOOP; i++) {
  40                                 rxp[i] = &rxq->fake_mbuf;
  41                                 _mm_store_si128((__m128i *)&rxdp[i].read,
  42                                                 dma_addr0);
  43                         }
  44                 }
  45                 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed +=
  46                         rxq->rx_free_thresh;
  47                 return;
  48         }
  49
  50         /* Initialize the mbufs in vector, process 2 mbufs in one loop */
  51         for (i = 0; i < rxq->rx_free_thresh; i += 2, rxp += 2) {
  52                 __m128i vaddr0, vaddr1;
  53
  54                 mb0 = rxp[0];
  55                 mb1 = rxp[1];
  56
  57                 /* load buf_addr(lo 64bit) and buf_iova(hi 64bit) */
  58                 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, buf_iova) !=
  59                                 offsetof(struct rte_mbuf, buf_addr) + 8);
  60                 vaddr0 = _mm_loadu_si128((__m128i *)&mb0->buf_addr);
  61                 vaddr1 = _mm_loadu_si128((__m128i *)&mb1->buf_addr);
  62
  63                 /* convert pa to dma_addr hdr/data */
  64                 dma_addr0 = _mm_unpackhi_epi64(vaddr0, vaddr0);
  65                 dma_addr1 = _mm_unpackhi_epi64(vaddr1, vaddr1);
  66
  67                 /* add headroom to pa values */
  68                 dma_addr0 = _mm_add_epi64(dma_addr0, hdr_room);
  69                 dma_addr1 = _mm_add_epi64(dma_addr1, hdr_room);
  70
  71                 /* flush desc with pa dma_addr */
  72                 _mm_store_si128((__m128i *)&rxdp++->read, dma_addr0);
  73                 _mm_store_si128((__m128i *)&rxdp++->read, dma_addr1);
  74         }
  75
  76         rxq->rxrearm_start += rxq->rx_free_thresh;
  77         if (rxq->rxrearm_start >= rxq->nb_rx_desc)
  78                 rxq->rxrearm_start = 0;
  79
  80         rxq->rxrearm_nb -= rxq->rx_free_thresh;
  81
  82         rx_id = (uint16_t)((rxq->rxrearm_start == 0) ?
  83                            (rxq->nb_rx_desc - 1) : (rxq->rxrearm_start - 1));
  84
  85         PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_tail=%u "
  86                    "rearm_start=%u rearm_nb=%u",
  87                    rxq->port_id, rxq->queue_id,
  88                    rx_id, rxq->rxrearm_start, rxq->rxrearm_nb);
  89
  90         /* Update the tail pointer on the NIC */
  91         IAVF_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
  92 }
  93
  94 static inline void
  95 desc_to_olflags_v(struct iavf_rx_queue *rxq, __m128i descs[4],
  96                   struct rte_mbuf **rx_pkts)
  97 {
  98         const __m128i mbuf_init = _mm_set_epi64x(0, rxq->mbuf_initializer);
  99         __m128i rearm0, rearm1, rearm2, rearm3;
 100
 101         __m128i vlan0, vlan1, rss, l3_l4e;
 102
 103         /* mask everything except RSS, flow director and VLAN flags
 104          * bit2 is for VLAN tag, bit11 for flow director indication
 105          * bit13:12 for RSS indication.
 106          */
 107         const __m128i rss_vlan_msk = _mm_set_epi32(
 108                         0x1c03804, 0x1c03804, 0x1c03804, 0x1c03804);
 109
 110         const __m128i cksum_mask = _mm_set_epi32(
 111                         PKT_RX_IP_CKSUM_GOOD | PKT_RX_IP_CKSUM_BAD |
 112                         PKT_RX_L4_CKSUM_GOOD | PKT_RX_L4_CKSUM_BAD |
 113                         PKT_RX_EIP_CKSUM_BAD,
 114                         PKT_RX_IP_CKSUM_GOOD | PKT_RX_IP_CKSUM_BAD |
 115                         PKT_RX_L4_CKSUM_GOOD | PKT_RX_L4_CKSUM_BAD |
 116                         PKT_RX_EIP_CKSUM_BAD,
 117                         PKT_RX_IP_CKSUM_GOOD | PKT_RX_IP_CKSUM_BAD |
 118                         PKT_RX_L4_CKSUM_GOOD | PKT_RX_L4_CKSUM_BAD |
 119                         PKT_RX_EIP_CKSUM_BAD,
 120                         PKT_RX_IP_CKSUM_GOOD | PKT_RX_IP_CKSUM_BAD |
 121                         PKT_RX_L4_CKSUM_GOOD | PKT_RX_L4_CKSUM_BAD |
 122                         PKT_RX_EIP_CKSUM_BAD);
 123
 124         /* map rss and vlan type to rss hash and vlan flag */
 125         const __m128i vlan_flags = _mm_set_epi8(0, 0, 0, 0,
 126                         0, 0, 0, 0,
 127                         0, 0, 0, PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED,
 128                         0, 0, 0, 0);
 129
 130         const __m128i rss_flags = _mm_set_epi8(0, 0, 0, 0,
 131                         0, 0, 0, 0,
 132                         PKT_RX_RSS_HASH | PKT_RX_FDIR, PKT_RX_RSS_HASH, 0, 0,
 133                         0, 0, PKT_RX_FDIR, 0);
 134
 135         const __m128i l3_l4e_flags = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0,
 136                         /* shift right 1 bit to make sure it not exceed 255 */
 137                         (PKT_RX_EIP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD |
 138                          PKT_RX_IP_CKSUM_BAD) >> 1,
 139                         (PKT_RX_IP_CKSUM_GOOD | PKT_RX_EIP_CKSUM_BAD |
 140                          PKT_RX_L4_CKSUM_BAD) >> 1,
 141                         (PKT_RX_EIP_CKSUM_BAD | PKT_RX_IP_CKSUM_BAD) >> 1,
 142                         (PKT_RX_IP_CKSUM_GOOD | PKT_RX_EIP_CKSUM_BAD) >> 1,
 143                         (PKT_RX_L4_CKSUM_BAD | PKT_RX_IP_CKSUM_BAD) >> 1,
 144                         (PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_BAD) >> 1,
 145                         PKT_RX_IP_CKSUM_BAD >> 1,
 146                         (PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD) >> 1);
 147
 148         vlan0 = _mm_unpackhi_epi32(descs[0], descs[1]);
 149         vlan1 = _mm_unpackhi_epi32(descs[2], descs[3]);
 150         vlan0 = _mm_unpacklo_epi64(vlan0, vlan1);
 151
 152         vlan1 = _mm_and_si128(vlan0, rss_vlan_msk);
 153         vlan0 = _mm_shuffle_epi8(vlan_flags, vlan1);
 154
 155         rss = _mm_srli_epi32(vlan1, 11);
 156         rss = _mm_shuffle_epi8(rss_flags, rss);
 157
 158         l3_l4e = _mm_srli_epi32(vlan1, 22);
 159         l3_l4e = _mm_shuffle_epi8(l3_l4e_flags, l3_l4e);
 160         /* then we shift left 1 bit */
 161         l3_l4e = _mm_slli_epi32(l3_l4e, 1);
 162         /* we need to mask out the reduntant bits */
 163         l3_l4e = _mm_and_si128(l3_l4e, cksum_mask);
 164
 165         vlan0 = _mm_or_si128(vlan0, rss);
 166         vlan0 = _mm_or_si128(vlan0, l3_l4e);
 167
 168         /* At this point, we have the 4 sets of flags in the low 16-bits
 169          * of each 32-bit value in vlan0.
 170          * We want to extract these, and merge them with the mbuf init data
 171          * so we can do a single 16-byte write to the mbuf to set the flags
 172          * and all the other initialization fields. Extracting the
 173          * appropriate flags means that we have to do a shift and blend for
 174          * each mbuf before we do the write.
 175          */
 176         rearm0 = _mm_blend_epi16(mbuf_init, _mm_slli_si128(vlan0, 8), 0x10);
 177         rearm1 = _mm_blend_epi16(mbuf_init, _mm_slli_si128(vlan0, 4), 0x10);
 178         rearm2 = _mm_blend_epi16(mbuf_init, vlan0, 0x10);
 179         rearm3 = _mm_blend_epi16(mbuf_init, _mm_srli_si128(vlan0, 4), 0x10);
 180
 181         /* write the rearm data and the olflags in one write */
 182         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, ol_flags) !=
 183                         offsetof(struct rte_mbuf, rearm_data) + 8);
 184         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, rearm_data) !=
 185                         RTE_ALIGN(offsetof(struct rte_mbuf, rearm_data), 16));
 186         _mm_store_si128((__m128i *)&rx_pkts[0]->rearm_data, rearm0);
 187         _mm_store_si128((__m128i *)&rx_pkts[1]->rearm_data, rearm1);
 188         _mm_store_si128((__m128i *)&rx_pkts[2]->rearm_data, rearm2);
 189         _mm_store_si128((__m128i *)&rx_pkts[3]->rearm_data, rearm3);
 190 }
 191
 192 #define PKTLEN_SHIFT     10
 193
 194 static inline void
 195 desc_to_ptype_v(__m128i descs[4], struct rte_mbuf **rx_pkts,
 196                 const uint32_t *type_table)
 197 {
 198         __m128i ptype0 = _mm_unpackhi_epi64(descs[0], descs[1]);
 199         __m128i ptype1 = _mm_unpackhi_epi64(descs[2], descs[3]);
 200
 201         ptype0 = _mm_srli_epi64(ptype0, 30);
 202         ptype1 = _mm_srli_epi64(ptype1, 30);
 203
 204         rx_pkts[0]->packet_type = type_table[_mm_extract_epi8(ptype0, 0)];
 205         rx_pkts[1]->packet_type = type_table[_mm_extract_epi8(ptype0, 8)];
 206         rx_pkts[2]->packet_type = type_table[_mm_extract_epi8(ptype1, 0)];
 207         rx_pkts[3]->packet_type = type_table[_mm_extract_epi8(ptype1, 8)];
 208 }
 209
 210 /* Notice:
 211  * - nb_pkts < IAVF_VPMD_DESCS_PER_LOOP, just return no packet
 212  * - nb_pkts > IAVF_VPMD_RX_MAX_BURST, only scan IAVF_VPMD_RX_MAX_BURST
 213  *   numbers of DD bits
 214  */
 215 static inline uint16_t
 216 _recv_raw_pkts_vec(struct iavf_rx_queue *rxq, struct rte_mbuf **rx_pkts,
 217                    uint16_t nb_pkts, uint8_t *split_packet)
 218 {
 219         volatile union iavf_rx_desc *rxdp;
 220         struct rte_mbuf **sw_ring;
 221         uint16_t nb_pkts_recd;
 222         int pos;
 223         uint64_t var;
 224         __m128i shuf_msk;
 225         const uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
 226
 227         __m128i crc_adjust = _mm_set_epi16(
 228                                 0, 0, 0,    /* ignore non-length fields */
 229                                 -rxq->crc_len, /* sub crc on data_len */
 230                                 0,          /* ignore high-16bits of pkt_len */
 231                                 -rxq->crc_len, /* sub crc on pkt_len */
 232                                 0, 0            /* ignore pkt_type field */
 233                         );
 234         /* compile-time check the above crc_adjust layout is correct.
 235          * NOTE: the first field (lowest address) is given last in set_epi16
 236          * call above.
 237          */
 238         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, pkt_len) !=
 239                         offsetof(struct rte_mbuf, rx_descriptor_fields1) + 4);
 240         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, data_len) !=
 241                         offsetof(struct rte_mbuf, rx_descriptor_fields1) + 8);
 242         __m128i dd_check, eop_check;
 243
 244         /* nb_pkts shall be less equal than IAVF_VPMD_RX_MAX_BURST */
 245         nb_pkts = RTE_MIN(nb_pkts, IAVF_VPMD_RX_MAX_BURST);
 246
 247         /* nb_pkts has to be floor-aligned to IAVF_VPMD_DESCS_PER_LOOP */
 248         nb_pkts = RTE_ALIGN_FLOOR(nb_pkts, IAVF_VPMD_DESCS_PER_LOOP);
 249
 250         /* Just the act of getting into the function from the application is
 251          * going to cost about 7 cycles
 252          */
 253         rxdp = rxq->rx_ring + rxq->rx_tail;
 254
 255         rte_prefetch0(rxdp);
 256
 257         /* See if we need to rearm the RX queue - gives the prefetch a bit
 258          * of time to act
 259          */
 260         if (rxq->rxrearm_nb > rxq->rx_free_thresh)
 261                 iavf_rxq_rearm(rxq);
 262
 263         /* Before we start moving massive data around, check to see if
 264          * there is actually a packet available
 265          */
 266         if (!(rxdp->wb.qword1.status_error_len &
 267               rte_cpu_to_le_32(1 << IAVF_RX_DESC_STATUS_DD_SHIFT)))
 268                 return 0;
 269
 270         /* 4 packets DD mask */
 271         dd_check = _mm_set_epi64x(0x0000000100000001LL, 0x0000000100000001LL);
 272
 273         /* 4 packets EOP mask */
 274         eop_check = _mm_set_epi64x(0x0000000200000002LL, 0x0000000200000002LL);
 275
 276         /* mask to shuffle from desc. to mbuf */
 277         shuf_msk = _mm_set_epi8(
 278                 7, 6, 5, 4,  /* octet 4~7, 32bits rss */
 279                 3, 2,        /* octet 2~3, low 16 bits vlan_macip */
 280                 15, 14,      /* octet 15~14, 16 bits data_len */
 281                 0xFF, 0xFF,  /* skip high 16 bits pkt_len, zero out */
 282                 15, 14,      /* octet 15~14, low 16 bits pkt_len */
 283                 0xFF, 0xFF, 0xFF, 0xFF /* pkt_type set as unknown */
 284                 );
 285         /* Compile-time verify the shuffle mask
 286          * NOTE: some field positions already verified above, but duplicated
 287          * here for completeness in case of future modifications.
 288          */
 289         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, pkt_len) !=
 290                         offsetof(struct rte_mbuf, rx_descriptor_fields1) + 4);
 291         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, data_len) !=
 292                         offsetof(struct rte_mbuf, rx_descriptor_fields1) + 8);
 293         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, vlan_tci) !=
 294                         offsetof(struct rte_mbuf, rx_descriptor_fields1) + 10);
 295         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, hash) !=
 296                         offsetof(struct rte_mbuf, rx_descriptor_fields1) + 12);
 297
 298         /* Cache is empty -> need to scan the buffer rings, but first move
 299          * the next 'n' mbufs into the cache
 300          */
 301         sw_ring = &rxq->sw_ring[rxq->rx_tail];
 302
 303         /* A. load 4 packet in one loop
 304          * [A*. mask out 4 unused dirty field in desc]
 305          * B. copy 4 mbuf point from swring to rx_pkts
 306          * C. calc the number of DD bits among the 4 packets
 307          * [C*. extract the end-of-packet bit, if requested]
 308          * D. fill info. from desc to mbuf
 309          */
 310
 311         for (pos = 0, nb_pkts_recd = 0; pos < nb_pkts;
 312              pos += IAVF_VPMD_DESCS_PER_LOOP,
 313              rxdp += IAVF_VPMD_DESCS_PER_LOOP) {
 314                 __m128i descs[IAVF_VPMD_DESCS_PER_LOOP];
 315                 __m128i pkt_mb1, pkt_mb2, pkt_mb3, pkt_mb4;
 316                 __m128i zero, staterr, sterr_tmp1, sterr_tmp2;
 317                 /* 2 64 bit or 4 32 bit mbuf pointers in one XMM reg. */
 318                 __m128i mbp1;
 319 #if defined(RTE_ARCH_X86_64)
 320                 __m128i mbp2;
 321 #endif
 322
 323                 /* B.1 load 2 (64 bit) or 4 (32 bit) mbuf points */
 324                 mbp1 = _mm_loadu_si128((__m128i *)&sw_ring[pos]);
 325                 /* Read desc statuses backwards to avoid race condition */
 326                 /* A.1 load 4 pkts desc */
 327                 descs[3] = _mm_loadu_si128((__m128i *)(rxdp + 3));
 328                 rte_compiler_barrier();
 329
 330                 /* B.2 copy 2 64 bit or 4 32 bit mbuf point into rx_pkts */
 331                 _mm_storeu_si128((__m128i *)&rx_pkts[pos], mbp1);
 332
 333 #if defined(RTE_ARCH_X86_64)
 334                 /* B.1 load 2 64 bit mbuf points */
 335                 mbp2 = _mm_loadu_si128((__m128i *)&sw_ring[pos + 2]);
 336 #endif
 337
 338                 descs[2] = _mm_loadu_si128((__m128i *)(rxdp + 2));
 339                 rte_compiler_barrier();
 340                 /* B.1 load 2 mbuf point */
 341                 descs[1] = _mm_loadu_si128((__m128i *)(rxdp + 1));
 342                 rte_compiler_barrier();
 343                 descs[0] = _mm_loadu_si128((__m128i *)(rxdp));
 344
 345 #if defined(RTE_ARCH_X86_64)
 346                 /* B.2 copy 2 mbuf point into rx_pkts  */
 347                 _mm_storeu_si128((__m128i *)&rx_pkts[pos + 2], mbp2);
 348 #endif
 349
 350                 if (split_packet) {
 351                         rte_mbuf_prefetch_part2(rx_pkts[pos]);
 352                         rte_mbuf_prefetch_part2(rx_pkts[pos + 1]);
 353                         rte_mbuf_prefetch_part2(rx_pkts[pos + 2]);
 354                         rte_mbuf_prefetch_part2(rx_pkts[pos + 3]);
 355                 }
 356
 357                 /* avoid compiler reorder optimization */
 358                 rte_compiler_barrier();
 359
 360                 /* pkt 3,4 shift the pktlen field to be 16-bit aligned*/
 361                 const __m128i len3 = _mm_slli_epi32(descs[3], PKTLEN_SHIFT);
 362                 const __m128i len2 = _mm_slli_epi32(descs[2], PKTLEN_SHIFT);
 363
 364                 /* merge the now-aligned packet length fields back in */
 365                 descs[3] = _mm_blend_epi16(descs[3], len3, 0x80);
 366                 descs[2] = _mm_blend_epi16(descs[2], len2, 0x80);
 367
 368                 /* D.1 pkt 3,4 convert format from desc to pktmbuf */
 369                 pkt_mb4 = _mm_shuffle_epi8(descs[3], shuf_msk);
 370                 pkt_mb3 = _mm_shuffle_epi8(descs[2], shuf_msk);
 371
 372                 /* C.1 4=>2 status err info only */
 373                 sterr_tmp2 = _mm_unpackhi_epi32(descs[3], descs[2]);
 374                 sterr_tmp1 = _mm_unpackhi_epi32(descs[1], descs[0]);
 375
 376                 desc_to_olflags_v(rxq, descs, &rx_pkts[pos]);
 377
 378                 /* D.2 pkt 3,4 set in_port/nb_seg and remove crc */
 379                 pkt_mb4 = _mm_add_epi16(pkt_mb4, crc_adjust);
 380                 pkt_mb3 = _mm_add_epi16(pkt_mb3, crc_adjust);
 381
 382                 /* pkt 1,2 shift the pktlen field to be 16-bit aligned*/
 383                 const __m128i len1 = _mm_slli_epi32(descs[1], PKTLEN_SHIFT);
 384                 const __m128i len0 = _mm_slli_epi32(descs[0], PKTLEN_SHIFT);
 385
 386                 /* merge the now-aligned packet length fields back in */
 387                 descs[1] = _mm_blend_epi16(descs[1], len1, 0x80);
 388                 descs[0] = _mm_blend_epi16(descs[0], len0, 0x80);
 389
 390                 /* D.1 pkt 1,2 convert format from desc to pktmbuf */
 391                 pkt_mb2 = _mm_shuffle_epi8(descs[1], shuf_msk);
 392                 pkt_mb1 = _mm_shuffle_epi8(descs[0], shuf_msk);
 393
 394                 /* C.2 get 4 pkts status err value  */
 395                 zero = _mm_xor_si128(dd_check, dd_check);
 396                 staterr = _mm_unpacklo_epi32(sterr_tmp1, sterr_tmp2);
 397
 398                 /* D.3 copy final 3,4 data to rx_pkts */
 399                 _mm_storeu_si128(
 400                         (void *)&rx_pkts[pos + 3]->rx_descriptor_fields1,
 401                         pkt_mb4);
 402                 _mm_storeu_si128(
 403                         (void *)&rx_pkts[pos + 2]->rx_descriptor_fields1,
 404                         pkt_mb3);
 405
 406                 /* D.2 pkt 1,2 remove crc */
 407                 pkt_mb2 = _mm_add_epi16(pkt_mb2, crc_adjust);
 408                 pkt_mb1 = _mm_add_epi16(pkt_mb1, crc_adjust);
 409
 410                 /* C* extract and record EOP bit */
 411                 if (split_packet) {
 412                         __m128i eop_shuf_mask = _mm_set_epi8(
 413                                         0xFF, 0xFF, 0xFF, 0xFF,
 414                                         0xFF, 0xFF, 0xFF, 0xFF,
 415                                         0xFF, 0xFF, 0xFF, 0xFF,
 416                                         0x04, 0x0C, 0x00, 0x08
 417                                         );
 418
 419                         /* and with mask to extract bits, flipping 1-0 */
 420                         __m128i eop_bits = _mm_andnot_si128(staterr, eop_check);
 421                         /* the staterr values are not in order, as the count
 422                          * count of dd bits doesn't care. However, for end of
 423                          * packet tracking, we do care, so shuffle. This also
 424                          * compresses the 32-bit values to 8-bit
 425                          */
 426                         eop_bits = _mm_shuffle_epi8(eop_bits, eop_shuf_mask);
 427                         /* store the resulting 32-bit value */
 428                         *(int *)split_packet = _mm_cvtsi128_si32(eop_bits);
 429                         split_packet += IAVF_VPMD_DESCS_PER_LOOP;
 430                 }
 431
 432                 /* C.3 calc available number of desc */
 433                 staterr = _mm_and_si128(staterr, dd_check);
 434                 staterr = _mm_packs_epi32(staterr, zero);
 435
 436                 /* D.3 copy final 1,2 data to rx_pkts */
 437                 _mm_storeu_si128(
 438                         (void *)&rx_pkts[pos + 1]->rx_descriptor_fields1,
 439                         pkt_mb2);
 440                 _mm_storeu_si128((void *)&rx_pkts[pos]->rx_descriptor_fields1,
 441                                  pkt_mb1);
 442                 desc_to_ptype_v(descs, &rx_pkts[pos], ptype_tbl);
 443                 /* C.4 calc avaialbe number of desc */
 444                 var = __builtin_popcountll(_mm_cvtsi128_si64(staterr));
 445                 nb_pkts_recd += var;
 446                 if (likely(var != IAVF_VPMD_DESCS_PER_LOOP))
 447                         break;
 448         }
 449
 450         /* Update our internal tail pointer */
 451         rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_pkts_recd);
 452         rxq->rx_tail = (uint16_t)(rxq->rx_tail & (rxq->nb_rx_desc - 1));
 453         rxq->rxrearm_nb = (uint16_t)(rxq->rxrearm_nb + nb_pkts_recd);
 454
 455         return nb_pkts_recd;
 456 }
 457
 458 /* Notice:
 459  * - nb_pkts < IAVF_DESCS_PER_LOOP, just return no packet
 460  * - nb_pkts > IAVF_VPMD_RX_MAX_BURST, only scan IAVF_VPMD_RX_MAX_BURST
 461  *   numbers of DD bits
 462  */
 463 uint16_t
 464 iavf_recv_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts,
 465                   uint16_t nb_pkts)
 466 {
 467         return _recv_raw_pkts_vec(rx_queue, rx_pkts, nb_pkts, NULL);
 468 }
 469
 470 /* vPMD receive routine that reassembles scattered packets
 471  * Notice:
 472  * - nb_pkts < IAVF_VPMD_DESCS_PER_LOOP, just return no packet
 473  * - nb_pkts > VPMD_RX_MAX_BURST, only scan IAVF_VPMD_RX_MAX_BURST
 474  *   numbers of DD bits
 475  */
 476 uint16_t
 477 iavf_recv_scattered_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts,
 478                             uint16_t nb_pkts)
 479 {
 480         struct iavf_rx_queue *rxq = rx_queue;
 481         uint8_t split_flags[IAVF_VPMD_RX_MAX_BURST] = {0};
 482         unsigned int i = 0;
 483
 484         /* get some new buffers */
 485         uint16_t nb_bufs = _recv_raw_pkts_vec(rxq, rx_pkts, nb_pkts,
 486                                               split_flags);
 487         if (nb_bufs == 0)
 488                 return 0;
 489
 490         /* happy day case, full burst + no packets to be joined */
 491         const uint64_t *split_fl64 = (uint64_t *)split_flags;
 492
 493         if (!rxq->pkt_first_seg &&
 494             split_fl64[0] == 0 && split_fl64[1] == 0 &&
 495             split_fl64[2] == 0 && split_fl64[3] == 0)
 496                 return nb_bufs;
 497
 498         /* reassemble any packets that need reassembly*/
 499         if (!rxq->pkt_first_seg) {
 500                 /* find the first split flag, and only reassemble then*/
 501                 while (i < nb_bufs && !split_flags[i])
 502                         i++;
 503                 if (i == nb_bufs)
 504                         return nb_bufs;
 505                 rxq->pkt_first_seg = rx_pkts[i];
 506         }
 507         return i + reassemble_packets(rxq, &rx_pkts[i], nb_bufs - i,
 508                 &split_flags[i]);
 509 }
 510
 511 static inline void
 512 vtx1(volatile struct iavf_tx_desc *txdp, struct rte_mbuf *pkt, uint64_t flags)
 513 {
 514         uint64_t high_qw =
 515                         (IAVF_TX_DESC_DTYPE_DATA |
 516                          ((uint64_t)flags  << IAVF_TXD_QW1_CMD_SHIFT) |
 517                          ((uint64_t)pkt->data_len <<
 518                           IAVF_TXD_QW1_TX_BUF_SZ_SHIFT));
 519
 520         __m128i descriptor = _mm_set_epi64x(high_qw,
 521                                             pkt->buf_iova + pkt->data_off);
 522         _mm_store_si128((__m128i *)txdp, descriptor);
 523 }
 524
 525 static inline void
 526 iavf_vtx(volatile struct iavf_tx_desc *txdp, struct rte_mbuf **pkt,
 527         uint16_t nb_pkts,  uint64_t flags)
 528 {
 529         int i;
 530
 531         for (i = 0; i < nb_pkts; ++i, ++txdp, ++pkt)
 532                 vtx1(txdp, *pkt, flags);
 533 }
 534
 535 uint16_t
 536 iavf_xmit_fixed_burst_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
 537                          uint16_t nb_pkts)
 538 {
 539         struct iavf_tx_queue *txq = (struct iavf_tx_queue *)tx_queue;
 540         volatile struct iavf_tx_desc *txdp;
 541         struct iavf_tx_entry *txep;
 542         uint16_t n, nb_commit, tx_id;
 543         uint64_t flags = IAVF_TX_DESC_CMD_EOP | 0x04;  /* bit 2 must be set */
 544         uint64_t rs = IAVF_TX_DESC_CMD_RS | flags;
 545         int i;
 546
 547         /* cross rx_thresh boundary is not allowed */
 548         nb_pkts = RTE_MIN(nb_pkts, txq->rs_thresh);
 549
 550         if (txq->nb_free < txq->free_thresh)
 551                 iavf_tx_free_bufs(txq);
 552
 553         nb_pkts = (uint16_t)RTE_MIN(txq->nb_free, nb_pkts);
 554         if (unlikely(nb_pkts == 0))
 555                 return 0;
 556         nb_commit = nb_pkts;
 557
 558         tx_id = txq->tx_tail;
 559         txdp = &txq->tx_ring[tx_id];
 560         txep = &txq->sw_ring[tx_id];
 561
 562         txq->nb_free = (uint16_t)(txq->nb_free - nb_pkts);
 563
 564         n = (uint16_t)(txq->nb_tx_desc - tx_id);
 565         if (nb_commit >= n) {
 566                 tx_backlog_entry(txep, tx_pkts, n);
 567
 568                 for (i = 0; i < n - 1; ++i, ++tx_pkts, ++txdp)
 569                         vtx1(txdp, *tx_pkts, flags);
 570
 571                 vtx1(txdp, *tx_pkts++, rs);
 572
 573                 nb_commit = (uint16_t)(nb_commit - n);
 574
 575                 tx_id = 0;
 576                 txq->next_rs = (uint16_t)(txq->rs_thresh - 1);
 577
 578                 /* avoid reach the end of ring */
 579                 txdp = &txq->tx_ring[tx_id];
 580                 txep = &txq->sw_ring[tx_id];
 581         }
 582
 583         tx_backlog_entry(txep, tx_pkts, nb_commit);
 584
 585         iavf_vtx(txdp, tx_pkts, nb_commit, flags);
 586
 587         tx_id = (uint16_t)(tx_id + nb_commit);
 588         if (tx_id > txq->next_rs) {
 589                 txq->tx_ring[txq->next_rs].cmd_type_offset_bsz |=
 590                         rte_cpu_to_le_64(((uint64_t)IAVF_TX_DESC_CMD_RS) <<
 591                                          IAVF_TXD_QW1_CMD_SHIFT);
 592                 txq->next_rs =
 593                         (uint16_t)(txq->next_rs + txq->rs_thresh);
 594         }
 595
 596         txq->tx_tail = tx_id;
 597
 598         PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u tx_tail=%u nb_pkts=%u",
 599                    txq->port_id, txq->queue_id, tx_id, nb_pkts);
 600
 601         IAVF_PCI_REG_WRITE(txq->qtx_tail, txq->tx_tail);
 602
 603         return nb_pkts;
 604 }
 605
 606 uint16_t
 607 iavf_xmit_pkts_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
 608                    uint16_t nb_pkts)
 609 {
 610         uint16_t nb_tx = 0;
 611         struct iavf_tx_queue *txq = (struct iavf_tx_queue *)tx_queue;
 612
 613         while (nb_pkts) {
 614                 uint16_t ret, num;
 615
 616                 num = (uint16_t)RTE_MIN(nb_pkts, txq->rs_thresh);
 617                 ret = iavf_xmit_fixed_burst_vec(tx_queue, &tx_pkts[nb_tx], num);
 618                 nb_tx += ret;
 619                 nb_pkts -= ret;
 620                 if (ret < num)
 621                         break;
 622         }
 623
 624         return nb_tx;
 625 }
 626
 627 static void __rte_cold
 628 iavf_rx_queue_release_mbufs_sse(struct iavf_rx_queue *rxq)
 629 {
 630         _iavf_rx_queue_release_mbufs_vec(rxq);
 631 }
 632
 633 static void __rte_cold
 634 iavf_tx_queue_release_mbufs_sse(struct iavf_tx_queue *txq)
 635 {
 636         _iavf_tx_queue_release_mbufs_vec(txq);
 637 }
 638
 639 static const struct iavf_rxq_ops sse_vec_rxq_ops = {
 640         .release_mbufs = iavf_rx_queue_release_mbufs_sse,
 641 };
 642
 643 static const struct iavf_txq_ops sse_vec_txq_ops = {
 644         .release_mbufs = iavf_tx_queue_release_mbufs_sse,
 645 };
 646
 647 int __rte_cold
 648 iavf_txq_vec_setup(struct iavf_tx_queue *txq)
 649 {
 650         txq->ops = &sse_vec_txq_ops;
 651         return 0;
 652 }
 653
 654 int __rte_cold
 655 iavf_rxq_vec_setup(struct iavf_rx_queue *rxq)
 656 {
 657         rxq->ops = &sse_vec_rxq_ops;
 658         return iavf_rxq_vec_setup_default(rxq);
 659 }
 660
 661 int __rte_cold
 662 iavf_rx_vec_dev_check(struct rte_eth_dev *dev)
 663 {
 664         return iavf_rx_vec_dev_check_default(dev);
 665 }
 666
 667 int __rte_cold
 668 iavf_tx_vec_dev_check(struct rte_eth_dev *dev)
 669 {
 670         return iavf_tx_vec_dev_check_default(dev);
 671 }