drivers/net/iavf/iavf_rxtx_vec_sse.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2017 Intel Corporation
   3  */
   4
   5 #include <stdint.h>
   6 #include <rte_ethdev_driver.h>
   7 #include <rte_malloc.h>
   8
   9 #include "iavf.h"
  10 #include "iavf_rxtx.h"
  11 #include "iavf_rxtx_vec_common.h"
  12
  13 #include <tmmintrin.h>
  14
  15 #ifndef __INTEL_COMPILER
  16 #pragma GCC diagnostic ignored "-Wcast-qual"
  17 #endif
  18
  19 static inline void
  20 iavf_rxq_rearm(struct iavf_rx_queue *rxq)
  21 {
  22         int i;
  23         uint16_t rx_id;
  24
  25         volatile union iavf_rx_desc *rxdp;
  26         struct rte_mbuf **rxp = &rxq->sw_ring[rxq->rxrearm_start];
  27         struct rte_mbuf *mb0, *mb1;
  28         __m128i hdr_room = _mm_set_epi64x(RTE_PKTMBUF_HEADROOM,
  29                         RTE_PKTMBUF_HEADROOM);
  30         __m128i dma_addr0, dma_addr1;
  31
  32         rxdp = rxq->rx_ring + rxq->rxrearm_start;
  33
  34         /* Pull 'n' more MBUFs into the software ring */
  35         if (rte_mempool_get_bulk(rxq->mp, (void *)rxp,
  36                                  rxq->rx_free_thresh) < 0) {
  37                 if (rxq->rxrearm_nb + rxq->rx_free_thresh >= rxq->nb_rx_desc) {
  38                         dma_addr0 = _mm_setzero_si128();
  39                         for (i = 0; i < IAVF_VPMD_DESCS_PER_LOOP; i++) {
  40                                 rxp[i] = &rxq->fake_mbuf;
  41                                 _mm_store_si128((__m128i *)&rxdp[i].read,
  42                                                 dma_addr0);
  43                         }
  44                 }
  45                 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed +=
  46                         rxq->rx_free_thresh;
  47                 return;
  48         }
  49
  50         /* Initialize the mbufs in vector, process 2 mbufs in one loop */
  51         for (i = 0; i < rxq->rx_free_thresh; i += 2, rxp += 2) {
  52                 __m128i vaddr0, vaddr1;
  53
  54                 mb0 = rxp[0];
  55                 mb1 = rxp[1];
  56
  57                 /* load buf_addr(lo 64bit) and buf_iova(hi 64bit) */
  58                 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, buf_iova) !=
  59                                 offsetof(struct rte_mbuf, buf_addr) + 8);
  60                 vaddr0 = _mm_loadu_si128((__m128i *)&mb0->buf_addr);
  61                 vaddr1 = _mm_loadu_si128((__m128i *)&mb1->buf_addr);
  62
  63                 /* convert pa to dma_addr hdr/data */
  64                 dma_addr0 = _mm_unpackhi_epi64(vaddr0, vaddr0);
  65                 dma_addr1 = _mm_unpackhi_epi64(vaddr1, vaddr1);
  66
  67                 /* add headroom to pa values */
  68                 dma_addr0 = _mm_add_epi64(dma_addr0, hdr_room);
  69                 dma_addr1 = _mm_add_epi64(dma_addr1, hdr_room);
  70
  71                 /* flush desc with pa dma_addr */
  72                 _mm_store_si128((__m128i *)&rxdp++->read, dma_addr0);
  73                 _mm_store_si128((__m128i *)&rxdp++->read, dma_addr1);
  74         }
  75
  76         rxq->rxrearm_start += rxq->rx_free_thresh;
  77         if (rxq->rxrearm_start >= rxq->nb_rx_desc)
  78                 rxq->rxrearm_start = 0;
  79
  80         rxq->rxrearm_nb -= rxq->rx_free_thresh;
  81
  82         rx_id = (uint16_t)((rxq->rxrearm_start == 0) ?
  83                            (rxq->nb_rx_desc - 1) : (rxq->rxrearm_start - 1));
  84
  85         PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_tail=%u "
  86                    "rearm_start=%u rearm_nb=%u",
  87                    rxq->port_id, rxq->queue_id,
  88                    rx_id, rxq->rxrearm_start, rxq->rxrearm_nb);
  89
  90         /* Update the tail pointer on the NIC */
  91         IAVF_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
  92 }
  93
  94 static inline void
  95 desc_to_olflags_v(struct iavf_rx_queue *rxq, __m128i descs[4],
  96                   struct rte_mbuf **rx_pkts)
  97 {
  98         const __m128i mbuf_init = _mm_set_epi64x(0, rxq->mbuf_initializer);
  99         __m128i rearm0, rearm1, rearm2, rearm3;
 100
 101         __m128i vlan0, vlan1, rss, l3_l4e;
 102
 103         /* mask everything except RSS, flow director and VLAN flags
 104          * bit2 is for VLAN tag, bit11 for flow director indication
 105          * bit13:12 for RSS indication.
 106          */
 107         const __m128i rss_vlan_msk = _mm_set_epi32(
 108                         0x1c03804, 0x1c03804, 0x1c03804, 0x1c03804);
 109
 110         const __m128i cksum_mask = _mm_set_epi32(
 111                         PKT_RX_IP_CKSUM_GOOD | PKT_RX_IP_CKSUM_BAD |
 112                         PKT_RX_L4_CKSUM_GOOD | PKT_RX_L4_CKSUM_BAD |
 113                         PKT_RX_EIP_CKSUM_BAD,
 114                         PKT_RX_IP_CKSUM_GOOD | PKT_RX_IP_CKSUM_BAD |
 115                         PKT_RX_L4_CKSUM_GOOD | PKT_RX_L4_CKSUM_BAD |
 116                         PKT_RX_EIP_CKSUM_BAD,
 117                         PKT_RX_IP_CKSUM_GOOD | PKT_RX_IP_CKSUM_BAD |
 118                         PKT_RX_L4_CKSUM_GOOD | PKT_RX_L4_CKSUM_BAD |
 119                         PKT_RX_EIP_CKSUM_BAD,
 120                         PKT_RX_IP_CKSUM_GOOD | PKT_RX_IP_CKSUM_BAD |
 121                         PKT_RX_L4_CKSUM_GOOD | PKT_RX_L4_CKSUM_BAD |
 122                         PKT_RX_EIP_CKSUM_BAD);
 123
 124         /* map rss and vlan type to rss hash and vlan flag */
 125         const __m128i vlan_flags = _mm_set_epi8(0, 0, 0, 0,
 126                         0, 0, 0, 0,
 127                         0, 0, 0, PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED,
 128                         0, 0, 0, 0);
 129
 130         const __m128i rss_flags = _mm_set_epi8(0, 0, 0, 0,
 131                         0, 0, 0, 0,
 132                         PKT_RX_RSS_HASH | PKT_RX_FDIR, PKT_RX_RSS_HASH, 0, 0,
 133                         0, 0, PKT_RX_FDIR, 0);
 134
 135         const __m128i l3_l4e_flags = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0,
 136                         /* shift right 1 bit to make sure it not exceed 255 */
 137                         (PKT_RX_EIP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD |
 138                          PKT_RX_IP_CKSUM_BAD) >> 1,
 139                         (PKT_RX_IP_CKSUM_GOOD | PKT_RX_EIP_CKSUM_BAD |
 140                          PKT_RX_L4_CKSUM_BAD) >> 1,
 141                         (PKT_RX_EIP_CKSUM_BAD | PKT_RX_IP_CKSUM_BAD) >> 1,
 142                         (PKT_RX_IP_CKSUM_GOOD | PKT_RX_EIP_CKSUM_BAD) >> 1,
 143                         (PKT_RX_L4_CKSUM_BAD | PKT_RX_IP_CKSUM_BAD) >> 1,
 144                         (PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_BAD) >> 1,
 145                         PKT_RX_IP_CKSUM_BAD >> 1,
 146                         (PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD) >> 1);
 147
 148         vlan0 = _mm_unpackhi_epi32(descs[0], descs[1]);
 149         vlan1 = _mm_unpackhi_epi32(descs[2], descs[3]);
 150         vlan0 = _mm_unpacklo_epi64(vlan0, vlan1);
 151
 152         vlan1 = _mm_and_si128(vlan0, rss_vlan_msk);
 153         vlan0 = _mm_shuffle_epi8(vlan_flags, vlan1);
 154
 155         rss = _mm_srli_epi32(vlan1, 11);
 156         rss = _mm_shuffle_epi8(rss_flags, rss);
 157
 158         l3_l4e = _mm_srli_epi32(vlan1, 22);
 159         l3_l4e = _mm_shuffle_epi8(l3_l4e_flags, l3_l4e);
 160         /* then we shift left 1 bit */
 161         l3_l4e = _mm_slli_epi32(l3_l4e, 1);
 162         /* we need to mask out the reduntant bits */
 163         l3_l4e = _mm_and_si128(l3_l4e, cksum_mask);
 164
 165         vlan0 = _mm_or_si128(vlan0, rss);
 166         vlan0 = _mm_or_si128(vlan0, l3_l4e);
 167
 168         /* At this point, we have the 4 sets of flags in the low 16-bits
 169          * of each 32-bit value in vlan0.
 170          * We want to extract these, and merge them with the mbuf init data
 171          * so we can do a single 16-byte write to the mbuf to set the flags
 172          * and all the other initialization fields. Extracting the
 173          * appropriate flags means that we have to do a shift and blend for
 174          * each mbuf before we do the write.
 175          */
 176         rearm0 = _mm_blend_epi16(mbuf_init, _mm_slli_si128(vlan0, 8), 0x10);
 177         rearm1 = _mm_blend_epi16(mbuf_init, _mm_slli_si128(vlan0, 4), 0x10);
 178         rearm2 = _mm_blend_epi16(mbuf_init, vlan0, 0x10);
 179         rearm3 = _mm_blend_epi16(mbuf_init, _mm_srli_si128(vlan0, 4), 0x10);
 180
 181         /* write the rearm data and the olflags in one write */
 182         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, ol_flags) !=
 183                         offsetof(struct rte_mbuf, rearm_data) + 8);
 184         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, rearm_data) !=
 185                         RTE_ALIGN(offsetof(struct rte_mbuf, rearm_data), 16));
 186         _mm_store_si128((__m128i *)&rx_pkts[0]->rearm_data, rearm0);
 187         _mm_store_si128((__m128i *)&rx_pkts[1]->rearm_data, rearm1);
 188         _mm_store_si128((__m128i *)&rx_pkts[2]->rearm_data, rearm2);
 189         _mm_store_si128((__m128i *)&rx_pkts[3]->rearm_data, rearm3);
 190 }
 191
 192 static inline void
 193 flex_desc_to_olflags_v(struct iavf_rx_queue *rxq, __m128i descs[4],
 194                        struct rte_mbuf **rx_pkts)
 195 {
 196         const __m128i mbuf_init = _mm_set_epi64x(0, rxq->mbuf_initializer);
 197         __m128i rearm0, rearm1, rearm2, rearm3;
 198
 199         __m128i tmp_desc, flags, rss_vlan;
 200
 201         /* mask everything except checksum, RSS and VLAN flags.
 202          * bit6:4 for checksum.
 203          * bit12 for RSS indication.
 204          * bit13 for VLAN indication.
 205          */
 206         const __m128i desc_mask = _mm_set_epi32(0x3070, 0x3070,
 207                                                 0x3070, 0x3070);
 208
 209         const __m128i cksum_mask = _mm_set_epi32(PKT_RX_IP_CKSUM_MASK |
 210                                                  PKT_RX_L4_CKSUM_MASK |
 211                                                  PKT_RX_EIP_CKSUM_BAD,
 212                                                  PKT_RX_IP_CKSUM_MASK |
 213                                                  PKT_RX_L4_CKSUM_MASK |
 214                                                  PKT_RX_EIP_CKSUM_BAD,
 215                                                  PKT_RX_IP_CKSUM_MASK |
 216                                                  PKT_RX_L4_CKSUM_MASK |
 217                                                  PKT_RX_EIP_CKSUM_BAD,
 218                                                  PKT_RX_IP_CKSUM_MASK |
 219                                                  PKT_RX_L4_CKSUM_MASK |
 220                                                  PKT_RX_EIP_CKSUM_BAD);
 221
 222         /* map the checksum, rss and vlan fields to the checksum, rss
 223          * and vlan flag
 224          */
 225         const __m128i cksum_flags = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0,
 226                         /* shift right 1 bit to make sure it not exceed 255 */
 227                         (PKT_RX_EIP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD |
 228                          PKT_RX_IP_CKSUM_BAD) >> 1,
 229                         (PKT_RX_EIP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD |
 230                          PKT_RX_IP_CKSUM_GOOD) >> 1,
 231                         (PKT_RX_EIP_CKSUM_BAD | PKT_RX_L4_CKSUM_GOOD |
 232                          PKT_RX_IP_CKSUM_BAD) >> 1,
 233                         (PKT_RX_EIP_CKSUM_BAD | PKT_RX_L4_CKSUM_GOOD |
 234                          PKT_RX_IP_CKSUM_GOOD) >> 1,
 235                         (PKT_RX_L4_CKSUM_BAD | PKT_RX_IP_CKSUM_BAD) >> 1,
 236                         (PKT_RX_L4_CKSUM_BAD | PKT_RX_IP_CKSUM_GOOD) >> 1,
 237                         (PKT_RX_L4_CKSUM_GOOD | PKT_RX_IP_CKSUM_BAD) >> 1,
 238                         (PKT_RX_L4_CKSUM_GOOD | PKT_RX_IP_CKSUM_GOOD) >> 1);
 239
 240         const __m128i rss_vlan_flags = _mm_set_epi8(0, 0, 0, 0,
 241                         0, 0, 0, 0,
 242                         0, 0, 0, 0,
 243                         PKT_RX_RSS_HASH | PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED,
 244                         PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED,
 245                         PKT_RX_RSS_HASH, 0);
 246
 247         /* merge 4 descriptors */
 248         flags = _mm_unpackhi_epi32(descs[0], descs[1]);
 249         tmp_desc = _mm_unpackhi_epi32(descs[2], descs[3]);
 250         tmp_desc = _mm_unpacklo_epi64(flags, tmp_desc);
 251         tmp_desc = _mm_and_si128(flags, desc_mask);
 252
 253         /* checksum flags */
 254         tmp_desc = _mm_srli_epi32(tmp_desc, 4);
 255         flags = _mm_shuffle_epi8(cksum_flags, tmp_desc);
 256         /* then we shift left 1 bit */
 257         flags = _mm_slli_epi32(flags, 1);
 258         /* we need to mask out the redundant bits introduced by RSS or
 259          * VLAN fields.
 260          */
 261         flags = _mm_and_si128(flags, cksum_mask);
 262
 263         /* RSS, VLAN flag */
 264         tmp_desc = _mm_srli_epi32(tmp_desc, 8);
 265         rss_vlan = _mm_shuffle_epi8(rss_vlan_flags, tmp_desc);
 266
 267         /* merge the flags */
 268         flags = _mm_or_si128(flags, rss_vlan);
 269
 270         /**
 271          * At this point, we have the 4 sets of flags in the low 16-bits
 272          * of each 32-bit value in flags.
 273          * We want to extract these, and merge them with the mbuf init data
 274          * so we can do a single 16-byte write to the mbuf to set the flags
 275          * and all the other initialization fields. Extracting the
 276          * appropriate flags means that we have to do a shift and blend for
 277          * each mbuf before we do the write.
 278          */
 279         rearm0 = _mm_blend_epi16(mbuf_init, _mm_slli_si128(flags, 8), 0x10);
 280         rearm1 = _mm_blend_epi16(mbuf_init, _mm_slli_si128(flags, 4), 0x10);
 281         rearm2 = _mm_blend_epi16(mbuf_init, flags, 0x10);
 282         rearm3 = _mm_blend_epi16(mbuf_init, _mm_srli_si128(flags, 4), 0x10);
 283
 284         /* write the rearm data and the olflags in one write */
 285         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, ol_flags) !=
 286                          offsetof(struct rte_mbuf, rearm_data) + 8);
 287         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, rearm_data) !=
 288                          RTE_ALIGN(offsetof(struct rte_mbuf, rearm_data), 16));
 289         _mm_store_si128((__m128i *)&rx_pkts[0]->rearm_data, rearm0);
 290         _mm_store_si128((__m128i *)&rx_pkts[1]->rearm_data, rearm1);
 291         _mm_store_si128((__m128i *)&rx_pkts[2]->rearm_data, rearm2);
 292         _mm_store_si128((__m128i *)&rx_pkts[3]->rearm_data, rearm3);
 293 }
 294
 295 #define PKTLEN_SHIFT     10
 296
 297 static inline void
 298 desc_to_ptype_v(__m128i descs[4], struct rte_mbuf **rx_pkts,
 299                 const uint32_t *type_table)
 300 {
 301         __m128i ptype0 = _mm_unpackhi_epi64(descs[0], descs[1]);
 302         __m128i ptype1 = _mm_unpackhi_epi64(descs[2], descs[3]);
 303
 304         ptype0 = _mm_srli_epi64(ptype0, 30);
 305         ptype1 = _mm_srli_epi64(ptype1, 30);
 306
 307         rx_pkts[0]->packet_type = type_table[_mm_extract_epi8(ptype0, 0)];
 308         rx_pkts[1]->packet_type = type_table[_mm_extract_epi8(ptype0, 8)];
 309         rx_pkts[2]->packet_type = type_table[_mm_extract_epi8(ptype1, 0)];
 310         rx_pkts[3]->packet_type = type_table[_mm_extract_epi8(ptype1, 8)];
 311 }
 312
 313 static inline void
 314 flex_desc_to_ptype_v(__m128i descs[4], struct rte_mbuf **rx_pkts,
 315                      const uint32_t *type_table)
 316 {
 317         const __m128i ptype_mask = _mm_set_epi16(0, IAVF_RX_FLEX_DESC_PTYPE_M,
 318                                                  0, IAVF_RX_FLEX_DESC_PTYPE_M,
 319                                                  0, IAVF_RX_FLEX_DESC_PTYPE_M,
 320                                                  0, IAVF_RX_FLEX_DESC_PTYPE_M);
 321         __m128i ptype_01 = _mm_unpacklo_epi32(descs[0], descs[1]);
 322         __m128i ptype_23 = _mm_unpacklo_epi32(descs[2], descs[3]);
 323         __m128i ptype_all = _mm_unpacklo_epi64(ptype_01, ptype_23);
 324
 325         ptype_all = _mm_and_si128(ptype_all, ptype_mask);
 326
 327         rx_pkts[0]->packet_type = type_table[_mm_extract_epi16(ptype_all, 1)];
 328         rx_pkts[1]->packet_type = type_table[_mm_extract_epi16(ptype_all, 3)];
 329         rx_pkts[2]->packet_type = type_table[_mm_extract_epi16(ptype_all, 5)];
 330         rx_pkts[3]->packet_type = type_table[_mm_extract_epi16(ptype_all, 7)];
 331 }
 332
 333 /* Notice:
 334  * - nb_pkts < IAVF_VPMD_DESCS_PER_LOOP, just return no packet
 335  * - nb_pkts > IAVF_VPMD_RX_MAX_BURST, only scan IAVF_VPMD_RX_MAX_BURST
 336  *   numbers of DD bits
 337  */
 338 static inline uint16_t
 339 _recv_raw_pkts_vec(struct iavf_rx_queue *rxq, struct rte_mbuf **rx_pkts,
 340                    uint16_t nb_pkts, uint8_t *split_packet)
 341 {
 342         volatile union iavf_rx_desc *rxdp;
 343         struct rte_mbuf **sw_ring;
 344         uint16_t nb_pkts_recd;
 345         int pos;
 346         uint64_t var;
 347         __m128i shuf_msk;
 348         const uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
 349
 350         __m128i crc_adjust = _mm_set_epi16(
 351                                 0, 0, 0,    /* ignore non-length fields */
 352                                 -rxq->crc_len, /* sub crc on data_len */
 353                                 0,          /* ignore high-16bits of pkt_len */
 354                                 -rxq->crc_len, /* sub crc on pkt_len */
 355                                 0, 0            /* ignore pkt_type field */
 356                         );
 357         /* compile-time check the above crc_adjust layout is correct.
 358          * NOTE: the first field (lowest address) is given last in set_epi16
 359          * call above.
 360          */
 361         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, pkt_len) !=
 362                         offsetof(struct rte_mbuf, rx_descriptor_fields1) + 4);
 363         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, data_len) !=
 364                         offsetof(struct rte_mbuf, rx_descriptor_fields1) + 8);
 365         __m128i dd_check, eop_check;
 366
 367         /* nb_pkts shall be less equal than IAVF_VPMD_RX_MAX_BURST */
 368         nb_pkts = RTE_MIN(nb_pkts, IAVF_VPMD_RX_MAX_BURST);
 369
 370         /* nb_pkts has to be floor-aligned to IAVF_VPMD_DESCS_PER_LOOP */
 371         nb_pkts = RTE_ALIGN_FLOOR(nb_pkts, IAVF_VPMD_DESCS_PER_LOOP);
 372
 373         /* Just the act of getting into the function from the application is
 374          * going to cost about 7 cycles
 375          */
 376         rxdp = rxq->rx_ring + rxq->rx_tail;
 377
 378         rte_prefetch0(rxdp);
 379
 380         /* See if we need to rearm the RX queue - gives the prefetch a bit
 381          * of time to act
 382          */
 383         if (rxq->rxrearm_nb > rxq->rx_free_thresh)
 384                 iavf_rxq_rearm(rxq);
 385
 386         /* Before we start moving massive data around, check to see if
 387          * there is actually a packet available
 388          */
 389         if (!(rxdp->wb.qword1.status_error_len &
 390               rte_cpu_to_le_32(1 << IAVF_RX_DESC_STATUS_DD_SHIFT)))
 391                 return 0;
 392
 393         /* 4 packets DD mask */
 394         dd_check = _mm_set_epi64x(0x0000000100000001LL, 0x0000000100000001LL);
 395
 396         /* 4 packets EOP mask */
 397         eop_check = _mm_set_epi64x(0x0000000200000002LL, 0x0000000200000002LL);
 398
 399         /* mask to shuffle from desc. to mbuf */
 400         shuf_msk = _mm_set_epi8(
 401                 7, 6, 5, 4,  /* octet 4~7, 32bits rss */
 402                 3, 2,        /* octet 2~3, low 16 bits vlan_macip */
 403                 15, 14,      /* octet 15~14, 16 bits data_len */
 404                 0xFF, 0xFF,  /* skip high 16 bits pkt_len, zero out */
 405                 15, 14,      /* octet 15~14, low 16 bits pkt_len */
 406                 0xFF, 0xFF, 0xFF, 0xFF /* pkt_type set as unknown */
 407                 );
 408         /* Compile-time verify the shuffle mask
 409          * NOTE: some field positions already verified above, but duplicated
 410          * here for completeness in case of future modifications.
 411          */
 412         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, pkt_len) !=
 413                         offsetof(struct rte_mbuf, rx_descriptor_fields1) + 4);
 414         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, data_len) !=
 415                         offsetof(struct rte_mbuf, rx_descriptor_fields1) + 8);
 416         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, vlan_tci) !=
 417                         offsetof(struct rte_mbuf, rx_descriptor_fields1) + 10);
 418         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, hash) !=
 419                         offsetof(struct rte_mbuf, rx_descriptor_fields1) + 12);
 420
 421         /* Cache is empty -> need to scan the buffer rings, but first move
 422          * the next 'n' mbufs into the cache
 423          */
 424         sw_ring = &rxq->sw_ring[rxq->rx_tail];
 425
 426         /* A. load 4 packet in one loop
 427          * [A*. mask out 4 unused dirty field in desc]
 428          * B. copy 4 mbuf point from swring to rx_pkts
 429          * C. calc the number of DD bits among the 4 packets
 430          * [C*. extract the end-of-packet bit, if requested]
 431          * D. fill info. from desc to mbuf
 432          */
 433
 434         for (pos = 0, nb_pkts_recd = 0; pos < nb_pkts;
 435              pos += IAVF_VPMD_DESCS_PER_LOOP,
 436              rxdp += IAVF_VPMD_DESCS_PER_LOOP) {
 437                 __m128i descs[IAVF_VPMD_DESCS_PER_LOOP];
 438                 __m128i pkt_mb1, pkt_mb2, pkt_mb3, pkt_mb4;
 439                 __m128i zero, staterr, sterr_tmp1, sterr_tmp2;
 440                 /* 2 64 bit or 4 32 bit mbuf pointers in one XMM reg. */
 441                 __m128i mbp1;
 442 #if defined(RTE_ARCH_X86_64)
 443                 __m128i mbp2;
 444 #endif
 445
 446                 /* B.1 load 2 (64 bit) or 4 (32 bit) mbuf points */
 447                 mbp1 = _mm_loadu_si128((__m128i *)&sw_ring[pos]);
 448                 /* Read desc statuses backwards to avoid race condition */
 449                 /* A.1 load 4 pkts desc */
 450                 descs[3] = _mm_loadu_si128((__m128i *)(rxdp + 3));
 451                 rte_compiler_barrier();
 452
 453                 /* B.2 copy 2 64 bit or 4 32 bit mbuf point into rx_pkts */
 454                 _mm_storeu_si128((__m128i *)&rx_pkts[pos], mbp1);
 455
 456 #if defined(RTE_ARCH_X86_64)
 457                 /* B.1 load 2 64 bit mbuf points */
 458                 mbp2 = _mm_loadu_si128((__m128i *)&sw_ring[pos + 2]);
 459 #endif
 460
 461                 descs[2] = _mm_loadu_si128((__m128i *)(rxdp + 2));
 462                 rte_compiler_barrier();
 463                 /* B.1 load 2 mbuf point */
 464                 descs[1] = _mm_loadu_si128((__m128i *)(rxdp + 1));
 465                 rte_compiler_barrier();
 466                 descs[0] = _mm_loadu_si128((__m128i *)(rxdp));
 467
 468 #if defined(RTE_ARCH_X86_64)
 469                 /* B.2 copy 2 mbuf point into rx_pkts  */
 470                 _mm_storeu_si128((__m128i *)&rx_pkts[pos + 2], mbp2);
 471 #endif
 472
 473                 if (split_packet) {
 474                         rte_mbuf_prefetch_part2(rx_pkts[pos]);
 475                         rte_mbuf_prefetch_part2(rx_pkts[pos + 1]);
 476                         rte_mbuf_prefetch_part2(rx_pkts[pos + 2]);
 477                         rte_mbuf_prefetch_part2(rx_pkts[pos + 3]);
 478                 }
 479
 480                 /* avoid compiler reorder optimization */
 481                 rte_compiler_barrier();
 482
 483                 /* pkt 3,4 shift the pktlen field to be 16-bit aligned*/
 484                 const __m128i len3 = _mm_slli_epi32(descs[3], PKTLEN_SHIFT);
 485                 const __m128i len2 = _mm_slli_epi32(descs[2], PKTLEN_SHIFT);
 486
 487                 /* merge the now-aligned packet length fields back in */
 488                 descs[3] = _mm_blend_epi16(descs[3], len3, 0x80);
 489                 descs[2] = _mm_blend_epi16(descs[2], len2, 0x80);
 490
 491                 /* D.1 pkt 3,4 convert format from desc to pktmbuf */
 492                 pkt_mb4 = _mm_shuffle_epi8(descs[3], shuf_msk);
 493                 pkt_mb3 = _mm_shuffle_epi8(descs[2], shuf_msk);
 494
 495                 /* C.1 4=>2 status err info only */
 496                 sterr_tmp2 = _mm_unpackhi_epi32(descs[3], descs[2]);
 497                 sterr_tmp1 = _mm_unpackhi_epi32(descs[1], descs[0]);
 498
 499                 desc_to_olflags_v(rxq, descs, &rx_pkts[pos]);
 500
 501                 /* D.2 pkt 3,4 set in_port/nb_seg and remove crc */
 502                 pkt_mb4 = _mm_add_epi16(pkt_mb4, crc_adjust);
 503                 pkt_mb3 = _mm_add_epi16(pkt_mb3, crc_adjust);
 504
 505                 /* pkt 1,2 shift the pktlen field to be 16-bit aligned*/
 506                 const __m128i len1 = _mm_slli_epi32(descs[1], PKTLEN_SHIFT);
 507                 const __m128i len0 = _mm_slli_epi32(descs[0], PKTLEN_SHIFT);
 508
 509                 /* merge the now-aligned packet length fields back in */
 510                 descs[1] = _mm_blend_epi16(descs[1], len1, 0x80);
 511                 descs[0] = _mm_blend_epi16(descs[0], len0, 0x80);
 512
 513                 /* D.1 pkt 1,2 convert format from desc to pktmbuf */
 514                 pkt_mb2 = _mm_shuffle_epi8(descs[1], shuf_msk);
 515                 pkt_mb1 = _mm_shuffle_epi8(descs[0], shuf_msk);
 516
 517                 /* C.2 get 4 pkts status err value  */
 518                 zero = _mm_xor_si128(dd_check, dd_check);
 519                 staterr = _mm_unpacklo_epi32(sterr_tmp1, sterr_tmp2);
 520
 521                 /* D.3 copy final 3,4 data to rx_pkts */
 522                 _mm_storeu_si128(
 523                         (void *)&rx_pkts[pos + 3]->rx_descriptor_fields1,
 524                         pkt_mb4);
 525                 _mm_storeu_si128(
 526                         (void *)&rx_pkts[pos + 2]->rx_descriptor_fields1,
 527                         pkt_mb3);
 528
 529                 /* D.2 pkt 1,2 remove crc */
 530                 pkt_mb2 = _mm_add_epi16(pkt_mb2, crc_adjust);
 531                 pkt_mb1 = _mm_add_epi16(pkt_mb1, crc_adjust);
 532
 533                 /* C* extract and record EOP bit */
 534                 if (split_packet) {
 535                         __m128i eop_shuf_mask = _mm_set_epi8(
 536                                         0xFF, 0xFF, 0xFF, 0xFF,
 537                                         0xFF, 0xFF, 0xFF, 0xFF,
 538                                         0xFF, 0xFF, 0xFF, 0xFF,
 539                                         0x04, 0x0C, 0x00, 0x08
 540                                         );
 541
 542                         /* and with mask to extract bits, flipping 1-0 */
 543                         __m128i eop_bits = _mm_andnot_si128(staterr, eop_check);
 544                         /* the staterr values are not in order, as the count
 545                          * count of dd bits doesn't care. However, for end of
 546                          * packet tracking, we do care, so shuffle. This also
 547                          * compresses the 32-bit values to 8-bit
 548                          */
 549                         eop_bits = _mm_shuffle_epi8(eop_bits, eop_shuf_mask);
 550                         /* store the resulting 32-bit value */
 551                         *(int *)split_packet = _mm_cvtsi128_si32(eop_bits);
 552                         split_packet += IAVF_VPMD_DESCS_PER_LOOP;
 553                 }
 554
 555                 /* C.3 calc available number of desc */
 556                 staterr = _mm_and_si128(staterr, dd_check);
 557                 staterr = _mm_packs_epi32(staterr, zero);
 558
 559                 /* D.3 copy final 1,2 data to rx_pkts */
 560                 _mm_storeu_si128(
 561                         (void *)&rx_pkts[pos + 1]->rx_descriptor_fields1,
 562                         pkt_mb2);
 563                 _mm_storeu_si128((void *)&rx_pkts[pos]->rx_descriptor_fields1,
 564                                  pkt_mb1);
 565                 desc_to_ptype_v(descs, &rx_pkts[pos], ptype_tbl);
 566                 /* C.4 calc avaialbe number of desc */
 567                 var = __builtin_popcountll(_mm_cvtsi128_si64(staterr));
 568                 nb_pkts_recd += var;
 569                 if (likely(var != IAVF_VPMD_DESCS_PER_LOOP))
 570                         break;
 571         }
 572
 573         /* Update our internal tail pointer */
 574         rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_pkts_recd);
 575         rxq->rx_tail = (uint16_t)(rxq->rx_tail & (rxq->nb_rx_desc - 1));
 576         rxq->rxrearm_nb = (uint16_t)(rxq->rxrearm_nb + nb_pkts_recd);
 577
 578         return nb_pkts_recd;
 579 }
 580
 581 /* Notice:
 582  * - nb_pkts < IAVF_VPMD_DESCS_PER_LOOP, just return no packet
 583  * - nb_pkts > IAVF_VPMD_RX_MAX_BURST, only scan IAVF_VPMD_RX_MAX_BURST
 584  *   numbers of DD bits
 585  */
 586 static inline uint16_t
 587 _recv_raw_pkts_vec_flex_rxd(struct iavf_rx_queue *rxq,
 588                             struct rte_mbuf **rx_pkts,
 589                             uint16_t nb_pkts, uint8_t *split_packet)
 590 {
 591         volatile union iavf_rx_flex_desc *rxdp;
 592         struct rte_mbuf **sw_ring;
 593         uint16_t nb_pkts_recd;
 594         int pos;
 595         uint64_t var;
 596         const uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
 597         __m128i crc_adjust = _mm_set_epi16
 598                                 (0, 0, 0,       /* ignore non-length fields */
 599                                  -rxq->crc_len, /* sub crc on data_len */
 600                                  0,          /* ignore high-16bits of pkt_len */
 601                                  -rxq->crc_len, /* sub crc on pkt_len */
 602                                  0, 0           /* ignore pkt_type field */
 603                                 );
 604         const __m128i zero = _mm_setzero_si128();
 605         /* mask to shuffle from desc. to mbuf */
 606         const __m128i shuf_msk = _mm_set_epi8
 607                         (15, 14, 13, 12,  /* octet 12~15, 32 bits rss */
 608                          11, 10,      /* octet 10~11, 16 bits vlan_macip */
 609                          5, 4,        /* octet 4~5, 16 bits data_len */
 610                          0xFF, 0xFF,  /* skip high 16 bits pkt_len, zero out */
 611                          5, 4,        /* octet 4~5, low 16 bits pkt_len */
 612                          0xFF, 0xFF,  /* pkt_type set as unknown */
 613                          0xFF, 0xFF   /* pkt_type set as unknown */
 614                         );
 615         const __m128i eop_shuf_mask = _mm_set_epi8(0xFF, 0xFF,
 616                                                    0xFF, 0xFF,
 617                                                    0xFF, 0xFF,
 618                                                    0xFF, 0xFF,
 619                                                    0xFF, 0xFF,
 620                                                    0xFF, 0xFF,
 621                                                    0x04, 0x0C,
 622                                                    0x00, 0x08);
 623
 624         /**
 625          * compile-time check the above crc_adjust layout is correct.
 626          * NOTE: the first field (lowest address) is given last in set_epi16
 627          * call above.
 628          */
 629         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, pkt_len) !=
 630                          offsetof(struct rte_mbuf, rx_descriptor_fields1) + 4);
 631         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, data_len) !=
 632                          offsetof(struct rte_mbuf, rx_descriptor_fields1) + 8);
 633
 634         /* 4 packets DD mask */
 635         const __m128i dd_check = _mm_set_epi64x(0x0000000100000001LL,
 636                                                 0x0000000100000001LL);
 637         /* 4 packets EOP mask */
 638         const __m128i eop_check = _mm_set_epi64x(0x0000000200000002LL,
 639                                                  0x0000000200000002LL);
 640
 641         /* nb_pkts shall be less equal than IAVF_VPMD_RX_MAX_BURST */
 642         nb_pkts = RTE_MIN(nb_pkts, IAVF_VPMD_RX_MAX_BURST);
 643
 644         /* nb_pkts has to be floor-aligned to IAVF_VPMD_DESCS_PER_LOOP */
 645         nb_pkts = RTE_ALIGN_FLOOR(nb_pkts, IAVF_VPMD_DESCS_PER_LOOP);
 646
 647         /* Just the act of getting into the function from the application is
 648          * going to cost about 7 cycles
 649          */
 650         rxdp = (union iavf_rx_flex_desc *)rxq->rx_ring + rxq->rx_tail;
 651
 652         rte_prefetch0(rxdp);
 653
 654         /* See if we need to rearm the RX queue - gives the prefetch a bit
 655          * of time to act
 656          */
 657         if (rxq->rxrearm_nb > rxq->rx_free_thresh)
 658                 iavf_rxq_rearm(rxq);
 659
 660         /* Before we start moving massive data around, check to see if
 661          * there is actually a packet available
 662          */
 663         if (!(rxdp->wb.status_error0 &
 664               rte_cpu_to_le_32(1 << IAVF_RX_FLEX_DESC_STATUS0_DD_S)))
 665                 return 0;
 666
 667         /**
 668          * Compile-time verify the shuffle mask
 669          * NOTE: some field positions already verified above, but duplicated
 670          * here for completeness in case of future modifications.
 671          */
 672         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, pkt_len) !=
 673                          offsetof(struct rte_mbuf, rx_descriptor_fields1) + 4);
 674         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, data_len) !=
 675                          offsetof(struct rte_mbuf, rx_descriptor_fields1) + 8);
 676         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, vlan_tci) !=
 677                          offsetof(struct rte_mbuf, rx_descriptor_fields1) + 10);
 678         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, hash) !=
 679                          offsetof(struct rte_mbuf, rx_descriptor_fields1) + 12);
 680
 681         /* Cache is empty -> need to scan the buffer rings, but first move
 682          * the next 'n' mbufs into the cache
 683          */
 684         sw_ring = &rxq->sw_ring[rxq->rx_tail];
 685
 686         /* A. load 4 packet in one loop
 687          * [A*. mask out 4 unused dirty field in desc]
 688          * B. copy 4 mbuf point from swring to rx_pkts
 689          * C. calc the number of DD bits among the 4 packets
 690          * [C*. extract the end-of-packet bit, if requested]
 691          * D. fill info. from desc to mbuf
 692          */
 693
 694         for (pos = 0, nb_pkts_recd = 0; pos < nb_pkts;
 695              pos += IAVF_VPMD_DESCS_PER_LOOP,
 696              rxdp += IAVF_VPMD_DESCS_PER_LOOP) {
 697                 __m128i descs[IAVF_VPMD_DESCS_PER_LOOP];
 698                 __m128i pkt_mb1, pkt_mb2, pkt_mb3, pkt_mb4;
 699                 __m128i staterr, sterr_tmp1, sterr_tmp2;
 700                 /* 2 64 bit or 4 32 bit mbuf pointers in one XMM reg. */
 701                 __m128i mbp1;
 702 #if defined(RTE_ARCH_X86_64)
 703                 __m128i mbp2;
 704 #endif
 705
 706                 /* B.1 load 2 (64 bit) or 4 (32 bit) mbuf points */
 707                 mbp1 = _mm_loadu_si128((__m128i *)&sw_ring[pos]);
 708                 /* Read desc statuses backwards to avoid race condition */
 709                 /* A.1 load 4 pkts desc */
 710                 descs[3] = _mm_loadu_si128((__m128i *)(rxdp + 3));
 711                 rte_compiler_barrier();
 712
 713                 /* B.2 copy 2 64 bit or 4 32 bit mbuf point into rx_pkts */
 714                 _mm_storeu_si128((__m128i *)&rx_pkts[pos], mbp1);
 715
 716 #if defined(RTE_ARCH_X86_64)
 717                 /* B.1 load 2 64 bit mbuf points */
 718                 mbp2 = _mm_loadu_si128((__m128i *)&sw_ring[pos + 2]);
 719 #endif
 720
 721                 descs[2] = _mm_loadu_si128((__m128i *)(rxdp + 2));
 722                 rte_compiler_barrier();
 723                 /* B.1 load 2 mbuf point */
 724                 descs[1] = _mm_loadu_si128((__m128i *)(rxdp + 1));
 725                 rte_compiler_barrier();
 726                 descs[0] = _mm_loadu_si128((__m128i *)(rxdp));
 727
 728 #if defined(RTE_ARCH_X86_64)
 729                 /* B.2 copy 2 mbuf point into rx_pkts  */
 730                 _mm_storeu_si128((__m128i *)&rx_pkts[pos + 2], mbp2);
 731 #endif
 732
 733                 if (split_packet) {
 734                         rte_mbuf_prefetch_part2(rx_pkts[pos]);
 735                         rte_mbuf_prefetch_part2(rx_pkts[pos + 1]);
 736                         rte_mbuf_prefetch_part2(rx_pkts[pos + 2]);
 737                         rte_mbuf_prefetch_part2(rx_pkts[pos + 3]);
 738                 }
 739
 740                 /* avoid compiler reorder optimization */
 741                 rte_compiler_barrier();
 742
 743                 /* D.1 pkt 3,4 convert format from desc to pktmbuf */
 744                 pkt_mb4 = _mm_shuffle_epi8(descs[3], shuf_msk);
 745                 pkt_mb3 = _mm_shuffle_epi8(descs[2], shuf_msk);
 746
 747                 /* C.1 4=>2 filter staterr info only */
 748                 sterr_tmp2 = _mm_unpackhi_epi32(descs[3], descs[2]);
 749                 /* C.1 4=>2 filter staterr info only */
 750                 sterr_tmp1 = _mm_unpackhi_epi32(descs[1], descs[0]);
 751
 752                 flex_desc_to_olflags_v(rxq, descs, &rx_pkts[pos]);
 753
 754                 /* D.2 pkt 3,4 set in_port/nb_seg and remove crc */
 755                 pkt_mb4 = _mm_add_epi16(pkt_mb4, crc_adjust);
 756                 pkt_mb3 = _mm_add_epi16(pkt_mb3, crc_adjust);
 757
 758                 /* D.1 pkt 1,2 convert format from desc to pktmbuf */
 759                 pkt_mb2 = _mm_shuffle_epi8(descs[1], shuf_msk);
 760                 pkt_mb1 = _mm_shuffle_epi8(descs[0], shuf_msk);
 761
 762                 /* C.2 get 4 pkts staterr value  */
 763                 staterr = _mm_unpacklo_epi32(sterr_tmp1, sterr_tmp2);
 764
 765                 /* D.3 copy final 3,4 data to rx_pkts */
 766                 _mm_storeu_si128
 767                         ((void *)&rx_pkts[pos + 3]->rx_descriptor_fields1,
 768                          pkt_mb4);
 769                 _mm_storeu_si128
 770                         ((void *)&rx_pkts[pos + 2]->rx_descriptor_fields1,
 771                          pkt_mb3);
 772
 773                 /* D.2 pkt 1,2 set in_port/nb_seg and remove crc */
 774                 pkt_mb2 = _mm_add_epi16(pkt_mb2, crc_adjust);
 775                 pkt_mb1 = _mm_add_epi16(pkt_mb1, crc_adjust);
 776
 777                 /* C* extract and record EOP bit */
 778                 if (split_packet) {
 779                         /* and with mask to extract bits, flipping 1-0 */
 780                         __m128i eop_bits = _mm_andnot_si128(staterr, eop_check);
 781                         /* the staterr values are not in order, as the count
 782                          * count of dd bits doesn't care. However, for end of
 783                          * packet tracking, we do care, so shuffle. This also
 784                          * compresses the 32-bit values to 8-bit
 785                          */
 786                         eop_bits = _mm_shuffle_epi8(eop_bits, eop_shuf_mask);
 787                         /* store the resulting 32-bit value */
 788                         *(int *)split_packet = _mm_cvtsi128_si32(eop_bits);
 789                         split_packet += IAVF_VPMD_DESCS_PER_LOOP;
 790                 }
 791
 792                 /* C.3 calc available number of desc */
 793                 staterr = _mm_and_si128(staterr, dd_check);
 794                 staterr = _mm_packs_epi32(staterr, zero);
 795
 796                 /* D.3 copy final 1,2 data to rx_pkts */
 797                 _mm_storeu_si128
 798                         ((void *)&rx_pkts[pos + 1]->rx_descriptor_fields1,
 799                          pkt_mb2);
 800                 _mm_storeu_si128((void *)&rx_pkts[pos]->rx_descriptor_fields1,
 801                                  pkt_mb1);
 802                 flex_desc_to_ptype_v(descs, &rx_pkts[pos], ptype_tbl);
 803                 /* C.4 calc available number of desc */
 804                 var = __builtin_popcountll(_mm_cvtsi128_si64(staterr));
 805                 nb_pkts_recd += var;
 806                 if (likely(var != IAVF_VPMD_DESCS_PER_LOOP))
 807                         break;
 808         }
 809
 810         /* Update our internal tail pointer */
 811         rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_pkts_recd);
 812         rxq->rx_tail = (uint16_t)(rxq->rx_tail & (rxq->nb_rx_desc - 1));
 813         rxq->rxrearm_nb = (uint16_t)(rxq->rxrearm_nb + nb_pkts_recd);
 814
 815         return nb_pkts_recd;
 816 }
 817
 818 /* Notice:
 819  * - nb_pkts < IAVF_DESCS_PER_LOOP, just return no packet
 820  * - nb_pkts > IAVF_VPMD_RX_MAX_BURST, only scan IAVF_VPMD_RX_MAX_BURST
 821  *   numbers of DD bits
 822  */
 823 uint16_t
 824 iavf_recv_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts,
 825                   uint16_t nb_pkts)
 826 {
 827         return _recv_raw_pkts_vec(rx_queue, rx_pkts, nb_pkts, NULL);
 828 }
 829
 830 /* Notice:
 831  * - nb_pkts < IAVF_DESCS_PER_LOOP, just return no packet
 832  * - nb_pkts > IAVF_VPMD_RX_MAX_BURST, only scan IAVF_VPMD_RX_MAX_BURST
 833  *   numbers of DD bits
 834  */
 835 uint16_t
 836 iavf_recv_pkts_vec_flex_rxd(void *rx_queue, struct rte_mbuf **rx_pkts,
 837                             uint16_t nb_pkts)
 838 {
 839         return _recv_raw_pkts_vec_flex_rxd(rx_queue, rx_pkts, nb_pkts, NULL);
 840 }
 841
 842 /* vPMD receive routine that reassembles scattered packets
 843  * Notice:
 844  * - nb_pkts < IAVF_VPMD_DESCS_PER_LOOP, just return no packet
 845  * - nb_pkts > VPMD_RX_MAX_BURST, only scan IAVF_VPMD_RX_MAX_BURST
 846  *   numbers of DD bits
 847  */
 848 uint16_t
 849 iavf_recv_scattered_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts,
 850                             uint16_t nb_pkts)
 851 {
 852         struct iavf_rx_queue *rxq = rx_queue;
 853         uint8_t split_flags[IAVF_VPMD_RX_MAX_BURST] = {0};
 854         unsigned int i = 0;
 855
 856         /* get some new buffers */
 857         uint16_t nb_bufs = _recv_raw_pkts_vec(rxq, rx_pkts, nb_pkts,
 858                                               split_flags);
 859         if (nb_bufs == 0)
 860                 return 0;
 861
 862         /* happy day case, full burst + no packets to be joined */
 863         const uint64_t *split_fl64 = (uint64_t *)split_flags;
 864
 865         if (!rxq->pkt_first_seg &&
 866             split_fl64[0] == 0 && split_fl64[1] == 0 &&
 867             split_fl64[2] == 0 && split_fl64[3] == 0)
 868                 return nb_bufs;
 869
 870         /* reassemble any packets that need reassembly*/
 871         if (!rxq->pkt_first_seg) {
 872                 /* find the first split flag, and only reassemble then*/
 873                 while (i < nb_bufs && !split_flags[i])
 874                         i++;
 875                 if (i == nb_bufs)
 876                         return nb_bufs;
 877                 rxq->pkt_first_seg = rx_pkts[i];
 878         }
 879         return i + reassemble_packets(rxq, &rx_pkts[i], nb_bufs - i,
 880                 &split_flags[i]);
 881 }
 882
 883 /* vPMD receive routine that reassembles scattered packets for flex RxD
 884  * Notice:
 885  * - nb_pkts < IAVF_VPMD_DESCS_PER_LOOP, just return no packet
 886  * - nb_pkts > VPMD_RX_MAX_BURST, only scan IAVF_VPMD_RX_MAX_BURST
 887  *   numbers of DD bits
 888  */
 889 uint16_t
 890 iavf_recv_scattered_pkts_vec_flex_rxd(void *rx_queue,
 891                                       struct rte_mbuf **rx_pkts,
 892                                       uint16_t nb_pkts)
 893 {
 894         struct iavf_rx_queue *rxq = rx_queue;
 895         uint8_t split_flags[IAVF_VPMD_RX_MAX_BURST] = {0};
 896         unsigned int i = 0;
 897
 898         /* get some new buffers */
 899         uint16_t nb_bufs = _recv_raw_pkts_vec_flex_rxd(rxq, rx_pkts, nb_pkts,
 900                                               split_flags);
 901         if (nb_bufs == 0)
 902                 return 0;
 903
 904         /* happy day case, full burst + no packets to be joined */
 905         const uint64_t *split_fl64 = (uint64_t *)split_flags;
 906
 907         if (!rxq->pkt_first_seg &&
 908             split_fl64[0] == 0 && split_fl64[1] == 0 &&
 909             split_fl64[2] == 0 && split_fl64[3] == 0)
 910                 return nb_bufs;
 911
 912         /* reassemble any packets that need reassembly*/
 913         if (!rxq->pkt_first_seg) {
 914                 /* find the first split flag, and only reassemble then*/
 915                 while (i < nb_bufs && !split_flags[i])
 916                         i++;
 917                 if (i == nb_bufs)
 918                         return nb_bufs;
 919                 rxq->pkt_first_seg = rx_pkts[i];
 920         }
 921         return i + reassemble_packets(rxq, &rx_pkts[i], nb_bufs - i,
 922                 &split_flags[i]);
 923 }
 924
 925 static inline void
 926 vtx1(volatile struct iavf_tx_desc *txdp, struct rte_mbuf *pkt, uint64_t flags)
 927 {
 928         uint64_t high_qw =
 929                         (IAVF_TX_DESC_DTYPE_DATA |
 930                          ((uint64_t)flags  << IAVF_TXD_QW1_CMD_SHIFT) |
 931                          ((uint64_t)pkt->data_len <<
 932                           IAVF_TXD_QW1_TX_BUF_SZ_SHIFT));
 933
 934         __m128i descriptor = _mm_set_epi64x(high_qw,
 935                                             pkt->buf_iova + pkt->data_off);
 936         _mm_store_si128((__m128i *)txdp, descriptor);
 937 }
 938
 939 static inline void
 940 iavf_vtx(volatile struct iavf_tx_desc *txdp, struct rte_mbuf **pkt,
 941         uint16_t nb_pkts,  uint64_t flags)
 942 {
 943         int i;
 944
 945         for (i = 0; i < nb_pkts; ++i, ++txdp, ++pkt)
 946                 vtx1(txdp, *pkt, flags);
 947 }
 948
 949 uint16_t
 950 iavf_xmit_fixed_burst_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
 951                          uint16_t nb_pkts)
 952 {
 953         struct iavf_tx_queue *txq = (struct iavf_tx_queue *)tx_queue;
 954         volatile struct iavf_tx_desc *txdp;
 955         struct iavf_tx_entry *txep;
 956         uint16_t n, nb_commit, tx_id;
 957         uint64_t flags = IAVF_TX_DESC_CMD_EOP | 0x04;  /* bit 2 must be set */
 958         uint64_t rs = IAVF_TX_DESC_CMD_RS | flags;
 959         int i;
 960
 961         /* cross rx_thresh boundary is not allowed */
 962         nb_pkts = RTE_MIN(nb_pkts, txq->rs_thresh);
 963
 964         if (txq->nb_free < txq->free_thresh)
 965                 iavf_tx_free_bufs(txq);
 966
 967         nb_pkts = (uint16_t)RTE_MIN(txq->nb_free, nb_pkts);
 968         if (unlikely(nb_pkts == 0))
 969                 return 0;
 970         nb_commit = nb_pkts;
 971
 972         tx_id = txq->tx_tail;
 973         txdp = &txq->tx_ring[tx_id];
 974         txep = &txq->sw_ring[tx_id];
 975
 976         txq->nb_free = (uint16_t)(txq->nb_free - nb_pkts);
 977
 978         n = (uint16_t)(txq->nb_tx_desc - tx_id);
 979         if (nb_commit >= n) {
 980                 tx_backlog_entry(txep, tx_pkts, n);
 981
 982                 for (i = 0; i < n - 1; ++i, ++tx_pkts, ++txdp)
 983                         vtx1(txdp, *tx_pkts, flags);
 984
 985                 vtx1(txdp, *tx_pkts++, rs);
 986
 987                 nb_commit = (uint16_t)(nb_commit - n);
 988
 989                 tx_id = 0;
 990                 txq->next_rs = (uint16_t)(txq->rs_thresh - 1);
 991
 992                 /* avoid reach the end of ring */
 993                 txdp = &txq->tx_ring[tx_id];
 994                 txep = &txq->sw_ring[tx_id];
 995         }
 996
 997         tx_backlog_entry(txep, tx_pkts, nb_commit);
 998
 999         iavf_vtx(txdp, tx_pkts, nb_commit, flags);
1000
1001         tx_id = (uint16_t)(tx_id + nb_commit);
1002         if (tx_id > txq->next_rs) {
1003                 txq->tx_ring[txq->next_rs].cmd_type_offset_bsz |=
1004                         rte_cpu_to_le_64(((uint64_t)IAVF_TX_DESC_CMD_RS) <<
1005                                          IAVF_TXD_QW1_CMD_SHIFT);
1006                 txq->next_rs =
1007                         (uint16_t)(txq->next_rs + txq->rs_thresh);
1008         }
1009
1010         txq->tx_tail = tx_id;
1011
1012         PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u tx_tail=%u nb_pkts=%u",
1013                    txq->port_id, txq->queue_id, tx_id, nb_pkts);
1014
1015         IAVF_PCI_REG_WRITE(txq->qtx_tail, txq->tx_tail);
1016
1017         return nb_pkts;
1018 }
1019
1020 uint16_t
1021 iavf_xmit_pkts_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
1022                    uint16_t nb_pkts)
1023 {
1024         uint16_t nb_tx = 0;
1025         struct iavf_tx_queue *txq = (struct iavf_tx_queue *)tx_queue;
1026
1027         while (nb_pkts) {
1028                 uint16_t ret, num;
1029
1030                 num = (uint16_t)RTE_MIN(nb_pkts, txq->rs_thresh);
1031                 ret = iavf_xmit_fixed_burst_vec(tx_queue, &tx_pkts[nb_tx], num);
1032                 nb_tx += ret;
1033                 nb_pkts -= ret;
1034                 if (ret < num)
1035                         break;
1036         }
1037
1038         return nb_tx;
1039 }
1040
1041 static void __rte_cold
1042 iavf_rx_queue_release_mbufs_sse(struct iavf_rx_queue *rxq)
1043 {
1044         _iavf_rx_queue_release_mbufs_vec(rxq);
1045 }
1046
1047 static void __rte_cold
1048 iavf_tx_queue_release_mbufs_sse(struct iavf_tx_queue *txq)
1049 {
1050         _iavf_tx_queue_release_mbufs_vec(txq);
1051 }
1052
1053 static const struct iavf_rxq_ops sse_vec_rxq_ops = {
1054         .release_mbufs = iavf_rx_queue_release_mbufs_sse,
1055 };
1056
1057 static const struct iavf_txq_ops sse_vec_txq_ops = {
1058         .release_mbufs = iavf_tx_queue_release_mbufs_sse,
1059 };
1060
1061 int __rte_cold
1062 iavf_txq_vec_setup(struct iavf_tx_queue *txq)
1063 {
1064         txq->ops = &sse_vec_txq_ops;
1065         return 0;
1066 }
1067
1068 int __rte_cold
1069 iavf_rxq_vec_setup(struct iavf_rx_queue *rxq)
1070 {
1071         rxq->ops = &sse_vec_rxq_ops;
1072         return iavf_rxq_vec_setup_default(rxq);
1073 }
1074
1075 int __rte_cold
1076 iavf_rx_vec_dev_check(struct rte_eth_dev *dev)
1077 {
1078         return iavf_rx_vec_dev_check_default(dev);
1079 }
1080
1081 int __rte_cold
1082 iavf_tx_vec_dev_check(struct rte_eth_dev *dev)
1083 {
1084         return iavf_tx_vec_dev_check_default(dev);
1085 }