1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2001-2020 Intel Corporation
8 /* Determine the TCAM index of entry 'e' within the ACL table */
9 #define ICE_ACL_TBL_TCAM_IDX(e) ((e) / ICE_AQC_ACL_TCAM_DEPTH)
11 /* Determine the entry index within the TCAM */
12 #define ICE_ACL_TBL_TCAM_ENTRY_IDX(e) ((e) % ICE_AQC_ACL_TCAM_DEPTH)
14 #define ICE_ACL_SCEN_ENTRY_INVAL 0xFFFF
18 * @scen: pointer to the scenario struct
20 * Initialize the scenario control structure.
22 static void ice_acl_init_entry(struct ice_acl_scen *scen)
24 /* low priority: start from the highest index, 25% of total entries
25 * normal priority: start from the highest index, 50% of total entries
26 * high priority: start from the lowest index, 25% of total entries
28 scen->first_idx[ICE_LOW] = scen->num_entry - 1;
29 scen->first_idx[ICE_NORMAL] = scen->num_entry - scen->num_entry / 4 - 1;
30 scen->first_idx[ICE_HIGH] = 0;
32 scen->last_idx[ICE_LOW] = scen->num_entry - scen->num_entry / 4;
33 scen->last_idx[ICE_NORMAL] = scen->num_entry / 4;
34 scen->last_idx[ICE_HIGH] = scen->num_entry / 4 - 1;
38 * ice_acl_scen_assign_entry_idx
39 * @scen: pointer to the scenario struct
40 * @prior: the priority of the flow entry being allocated
42 * To find the index of an available entry in scenario
44 * Returns ICE_ACL_SCEN_ENTRY_INVAL if fails
45 * Returns index on success
48 ice_acl_scen_assign_entry_idx(struct ice_acl_scen *scen,
49 enum ice_acl_entry_prior prior)
51 u16 first_idx, last_idx, i;
54 if (prior >= ICE_MAX_PRIOR)
55 return ICE_ACL_SCEN_ENTRY_INVAL;
57 first_idx = scen->first_idx[prior];
58 last_idx = scen->last_idx[prior];
59 step = first_idx <= last_idx ? 1 : -1;
61 for (i = first_idx; i != last_idx + step; i += step)
62 if (!ice_test_and_set_bit(i, scen->entry_bitmap))
65 return ICE_ACL_SCEN_ENTRY_INVAL;
69 * ice_acl_scen_free_entry_idx
70 * @scen: pointer to the scenario struct
71 * @idx: the index of the flow entry being de-allocated
73 * To mark an entry available in scenario
75 static enum ice_status
76 ice_acl_scen_free_entry_idx(struct ice_acl_scen *scen, u16 idx)
78 if (idx >= scen->num_entry)
79 return ICE_ERR_MAX_LIMIT;
81 if (!ice_test_and_clear_bit(idx, scen->entry_bitmap))
82 return ICE_ERR_DOES_NOT_EXIST;
88 * ice_acl_tbl_calc_end_idx
89 * @start: start index of the TCAM entry of this partition
90 * @num_entries: number of entries in this partition
91 * @width: width of a partition in number of TCAMs
93 * Calculate the end entry index for a partition with starting entry index
94 * 'start', entries 'num_entries', and width 'width'.
96 static u16 ice_acl_tbl_calc_end_idx(u16 start, u16 num_entries, u16 width)
98 u16 end_idx, add_entries = 0;
100 end_idx = start + (num_entries - 1);
102 /* In case that our ACL partition requires cascading TCAMs */
106 /* Figure out the TCAM stacked level in this ACL scenario */
107 num_stack_level = (start % ICE_AQC_ACL_TCAM_DEPTH) +
109 num_stack_level = DIVIDE_AND_ROUND_UP(num_stack_level,
110 ICE_AQC_ACL_TCAM_DEPTH);
112 /* In this case, each entries in our ACL partition span
113 * multiple TCAMs. Thus, we will need to add
114 * ((width - 1) * num_stack_level) TCAM's entries to
117 * For example : In our case, our scenario is 2x2:
120 * Assuming that a TCAM will have 512 entries. If "start"
121 * is 500, "num_entries" is 3 and "width" = 2, then end_idx
122 * should be 1024 (belongs to TCAM 2).
123 * Before going to this if statement, end_idx will have the
124 * value of 512. If "width" is 1, then the final value of
125 * end_idx is 512. However, in our case, width is 2, then we
126 * will need add (2 - 1) * 1 * 512. As result, end_idx will
127 * have the value of 1024.
129 add_entries = (width - 1) * num_stack_level *
130 ICE_AQC_ACL_TCAM_DEPTH;
133 return end_idx + add_entries;
138 * @hw: pointer to the hardware structure
140 * Initialize the ACL table by invalidating TCAM entries and action pairs.
142 static enum ice_status ice_acl_init_tbl(struct ice_hw *hw)
144 struct ice_aqc_actpair act_buf;
145 struct ice_aqc_acl_data buf;
146 enum ice_status status = ICE_SUCCESS;
147 struct ice_acl_tbl *tbl;
153 status = ICE_ERR_CFG;
157 ice_memset(&buf, 0, sizeof(buf), ICE_NONDMA_MEM);
158 ice_memset(&act_buf, 0, sizeof(act_buf), ICE_NONDMA_MEM);
160 tcam_idx = tbl->first_tcam;
161 idx = tbl->first_entry;
162 while (tcam_idx < tbl->last_tcam ||
163 (tcam_idx == tbl->last_tcam && idx <= tbl->last_entry)) {
164 /* Use the same value for entry_key and entry_key_inv since
165 * we are initializing the fields to 0
167 status = ice_aq_program_acl_entry(hw, tcam_idx, idx, &buf,
172 if (++idx > tbl->last_entry) {
174 idx = tbl->first_entry;
178 for (i = 0; i < ICE_AQC_MAX_ACTION_MEMORIES; i++) {
179 u16 act_entry_idx, start, end;
181 if (tbl->act_mems[i].act_mem == ICE_ACL_ACT_PAIR_MEM_INVAL)
184 start = tbl->first_entry;
185 end = tbl->last_entry;
187 for (act_entry_idx = start; act_entry_idx <= end;
189 /* Invalidate all allocated action pairs */
190 status = ice_aq_program_actpair(hw, i, act_entry_idx,
201 * ice_acl_assign_act_mems_to_tcam
202 * @tbl: pointer to ACL table structure
203 * @cur_tcam: Index of current TCAM. Value = 0 to (ICE_AQC_ACL_SLICES - 1)
204 * @cur_mem_idx: Index of current action memory bank. Value = 0 to
205 * (ICE_AQC_MAX_ACTION_MEMORIES - 1)
206 * @num_mem: Number of action memory banks for this TCAM
208 * Assign "num_mem" valid action memory banks from "curr_mem_idx" to
212 ice_acl_assign_act_mems_to_tcam(struct ice_acl_tbl *tbl, u8 cur_tcam,
213 u8 *cur_mem_idx, u8 num_mem)
218 *cur_mem_idx < ICE_AQC_MAX_ACTION_MEMORIES && mem_cnt < num_mem;
220 struct ice_acl_act_mem *p_mem = &tbl->act_mems[*cur_mem_idx];
222 if (p_mem->act_mem == ICE_ACL_ACT_PAIR_MEM_INVAL)
225 p_mem->member_of_tcam = cur_tcam;
232 * ice_acl_divide_act_mems_to_tcams
233 * @tbl: pointer to ACL table structure
235 * Figure out how to divide given action memory banks to given TCAMs. This
236 * division is for SW book keeping. In the time when scenario is created,
237 * an action memory bank can be used for different TCAM.
239 * For example, given that we have 2x2 ACL table with each table entry has
240 * 2 action memory pairs. As the result, we will have 4 TCAMs (T1,T2,T3,T4)
241 * and 4 action memory banks (A1,A2,A3,A4)
242 * [T1 - T2] { A1 - A2 }
243 * [T3 - T4] { A3 - A4 }
244 * In the time when we need to create a scenario, for example, 2x1 scenario,
245 * we will use [T3,T4] in a cascaded layout. As it is a requirement that all
246 * action memory banks in a cascaded TCAM's row will need to associate with
247 * the last TCAM. Thus, we will associate action memory banks [A3] and [A4]
249 * For SW book-keeping purpose, we will keep theoretical maps between TCAM
250 * [Tn] to action memory bank [An].
252 static void ice_acl_divide_act_mems_to_tcams(struct ice_acl_tbl *tbl)
254 u16 num_cscd, stack_level, stack_idx, min_act_mem;
255 u8 tcam_idx = tbl->first_tcam;
256 u16 max_idx_to_get_extra;
259 /* Determine number of stacked TCAMs */
260 stack_level = DIVIDE_AND_ROUND_UP(tbl->info.depth,
261 ICE_AQC_ACL_TCAM_DEPTH);
263 /* Determine number of cascaded TCAMs */
264 num_cscd = DIVIDE_AND_ROUND_UP(tbl->info.width,
265 ICE_AQC_ACL_KEY_WIDTH_BYTES);
267 /* In a line of cascaded TCAM, given the number of action memory
268 * banks per ACL table entry, we want to fairly divide these action
269 * memory banks between these TCAMs.
271 * For example, there are 3 TCAMs (TCAM 3,4,5) in a line of
272 * cascaded TCAM, and there are 7 act_mems for each ACL table entry.
274 * [TCAM_3 will have 3 act_mems]
275 * [TCAM_4 will have 2 act_mems]
276 * [TCAM_5 will have 2 act_mems]
278 min_act_mem = tbl->info.entry_act_pairs / num_cscd;
279 max_idx_to_get_extra = tbl->info.entry_act_pairs % num_cscd;
281 for (stack_idx = 0; stack_idx < stack_level; stack_idx++) {
284 for (i = 0; i < num_cscd; i++) {
285 u8 total_act_mem = min_act_mem;
287 if (i < max_idx_to_get_extra)
290 ice_acl_assign_act_mems_to_tcam(tbl, tcam_idx,
301 * @hw: pointer to the HW struct
302 * @params: parameters for the table to be created
304 * Create a LEM table for ACL usage. We are currently starting with some fixed
305 * values for the size of the table, but this will need to grow as more flow
306 * entries are added by the user level.
309 ice_acl_create_tbl(struct ice_hw *hw, struct ice_acl_tbl_params *params)
311 u16 width, depth, first_e, last_e, i;
312 struct ice_aqc_acl_generic *resp_buf;
313 struct ice_acl_alloc_tbl tbl_alloc;
314 struct ice_acl_tbl *tbl;
315 enum ice_status status;
318 return ICE_ERR_ALREADY_EXISTS;
321 return ICE_ERR_PARAM;
323 /* round up the width to the next TCAM width boundary. */
324 width = ROUND_UP(params->width, (u16)ICE_AQC_ACL_KEY_WIDTH_BYTES);
325 /* depth should be provided in chunk (64 entry) increments */
326 depth = ICE_ALIGN(params->depth, ICE_ACL_ENTRY_ALLOC_UNIT);
328 if (params->entry_act_pairs < width / ICE_AQC_ACL_KEY_WIDTH_BYTES) {
329 params->entry_act_pairs = width / ICE_AQC_ACL_KEY_WIDTH_BYTES;
331 if (params->entry_act_pairs > ICE_AQC_TBL_MAX_ACTION_PAIRS)
332 params->entry_act_pairs = ICE_AQC_TBL_MAX_ACTION_PAIRS;
335 /* Validate that width*depth will not exceed the TCAM limit */
336 if ((DIVIDE_AND_ROUND_UP(depth, ICE_AQC_ACL_TCAM_DEPTH) *
337 (width / ICE_AQC_ACL_KEY_WIDTH_BYTES)) > ICE_AQC_ACL_SLICES)
338 return ICE_ERR_MAX_LIMIT;
340 ice_memset(&tbl_alloc, 0, sizeof(tbl_alloc), ICE_NONDMA_MEM);
341 tbl_alloc.width = width;
342 tbl_alloc.depth = depth;
343 tbl_alloc.act_pairs_per_entry = params->entry_act_pairs;
344 tbl_alloc.concurr = params->concurr;
345 /* Set dependent_alloc_id only for concurrent table type */
346 if (params->concurr) {
347 tbl_alloc.num_dependent_alloc_ids =
348 ICE_AQC_MAX_CONCURRENT_ACL_TBL;
350 for (i = 0; i < ICE_AQC_MAX_CONCURRENT_ACL_TBL; i++)
351 tbl_alloc.buf.data_buf.alloc_ids[i] =
352 CPU_TO_LE16(params->dep_tbls[i]);
355 /* call the AQ command to create the ACL table with these values */
356 status = ice_aq_alloc_acl_tbl(hw, &tbl_alloc, NULL);
358 if (LE16_TO_CPU(tbl_alloc.buf.resp_buf.alloc_id) <
359 ICE_AQC_ALLOC_ID_LESS_THAN_4K)
360 ice_debug(hw, ICE_DBG_ACL, "Alloc ACL table failed. Unavailable resource.\n");
362 ice_debug(hw, ICE_DBG_ACL, "AQ allocation of ACL failed with error. status: %d\n",
367 tbl = (struct ice_acl_tbl *)ice_malloc(hw, sizeof(*tbl));
369 status = ICE_ERR_NO_MEMORY;
374 resp_buf = &tbl_alloc.buf.resp_buf;
376 /* Retrieve information of the allocated table */
377 tbl->id = LE16_TO_CPU(resp_buf->alloc_id);
378 tbl->first_tcam = resp_buf->ops.table.first_tcam;
379 tbl->last_tcam = resp_buf->ops.table.last_tcam;
380 tbl->first_entry = LE16_TO_CPU(resp_buf->first_entry);
381 tbl->last_entry = LE16_TO_CPU(resp_buf->last_entry);
384 tbl->info.width = width;
385 tbl->info.depth = depth;
388 for (i = 0; i < ICE_AQC_MAX_ACTION_MEMORIES; i++)
389 tbl->act_mems[i].act_mem = resp_buf->act_mem[i];
391 /* Figure out which TCAMs that these newly allocated action memories
394 ice_acl_divide_act_mems_to_tcams(tbl);
396 /* Initialize the resources allocated by invalidating all TCAM entries
397 * and all the action pairs
399 status = ice_acl_init_tbl(hw);
403 ice_debug(hw, ICE_DBG_ACL, "Initialization of TCAM entries failed. status: %d\n",
408 first_e = (tbl->first_tcam * ICE_AQC_MAX_TCAM_ALLOC_UNITS) +
409 (tbl->first_entry / ICE_ACL_ENTRY_ALLOC_UNIT);
410 last_e = (tbl->last_tcam * ICE_AQC_MAX_TCAM_ALLOC_UNITS) +
411 (tbl->last_entry / ICE_ACL_ENTRY_ALLOC_UNIT);
413 /* Indicate available entries in the table */
414 ice_bitmap_set(tbl->avail, first_e, last_e - first_e + 1);
416 INIT_LIST_HEAD(&tbl->scens);
423 * ice_acl_alloc_partition - Allocate a partition from the ACL table
424 * @hw: pointer to the hardware structure
425 * @req: info of partition being allocated
427 static enum ice_status
428 ice_acl_alloc_partition(struct ice_hw *hw, struct ice_acl_scen *req)
430 u16 start = 0, cnt = 0, off = 0;
431 u16 width, r_entries, row;
435 /* Determine the number of TCAMs each entry overlaps */
436 width = DIVIDE_AND_ROUND_UP(req->width, ICE_AQC_ACL_KEY_WIDTH_BYTES);
438 /* Check if we have enough TCAMs to accommodate the width */
439 if (width > hw->acl_tbl->last_tcam - hw->acl_tbl->first_tcam + 1)
440 return ICE_ERR_MAX_LIMIT;
442 /* Number of entries must be multiple of ICE_ACL_ENTRY_ALLOC_UNIT's */
443 r_entries = ICE_ALIGN(req->num_entry, ICE_ACL_ENTRY_ALLOC_UNIT);
445 /* To look for an available partition that can accommodate the request,
446 * the process first logically arranges available TCAMs in rows such
447 * that each row produces entries with the requested width. It then
448 * scans the TCAMs' available bitmap, one bit at a time, and
449 * accumulates contiguous available 64-entry chunks until there are
450 * enough of them or when all TCAM configurations have been checked.
452 * For width of 1 TCAM, the scanning process starts from the top most
453 * TCAM, and goes downward. Available bitmaps are examined from LSB
456 * For width of multiple TCAMs, the process starts from the bottom-most
457 * row of TCAMs, and goes upward. Available bitmaps are examined from
458 * the MSB to the LSB.
460 * To make sure that adjacent TCAMs can be logically arranged in the
461 * same row, the scanning process may have multiple passes. In each
462 * pass, the first TCAM of the bottom-most row is displaced by one
463 * additional TCAM. The width of the row and the number of the TCAMs
464 * available determine the number of passes. When the displacement is
465 * more than the size of width, the TCAM row configurations will
466 * repeat. The process will terminate when the configurations repeat.
468 * Available partitions can span more than one row of TCAMs.
471 row = hw->acl_tbl->first_tcam;
474 /* Start with the bottom-most row, and scan for available
477 row = hw->acl_tbl->last_tcam + 1 - width;
484 /* Scan all 64-entry chunks, one chunk at a time, in the
488 i < ICE_AQC_MAX_TCAM_ALLOC_UNITS && cnt < r_entries;
493 /* Compute the cumulative available mask across the
494 * TCAM row to determine if the current 64-entry chunk
497 p = dir > 0 ? i : ICE_AQC_MAX_TCAM_ALLOC_UNITS - i - 1;
498 for (w = row; w < row + width && avail; w++) {
501 b = (w * ICE_AQC_MAX_TCAM_ALLOC_UNITS) + p;
502 avail &= ice_is_bit_set(hw->acl_tbl->avail, b);
508 /* Compute the starting index of the newly
509 * found partition. When 'dir' is negative, the
510 * scan processes is going upward. If so, the
511 * starting index needs to be updated for every
512 * available 64-entry chunk found.
515 start = (row * ICE_AQC_ACL_TCAM_DEPTH) +
516 (p * ICE_ACL_ENTRY_ALLOC_UNIT);
517 cnt += ICE_ACL_ENTRY_ALLOC_UNIT;
521 if (cnt >= r_entries) {
523 req->num_entry = r_entries;
524 req->end = ice_acl_tbl_calc_end_idx(start, r_entries,
529 row = (dir > 0) ? (row + width) : (row - width);
530 if (row > hw->acl_tbl->last_tcam ||
531 row < hw->acl_tbl->first_tcam) {
532 /* All rows have been checked. Increment 'off' that
533 * will help yield a different TCAM configuration in
534 * which adjacent TCAMs can be alternatively in the
539 /* However, if the new 'off' value yields previously
540 * checked configurations, then exit.
545 row = dir > 0 ? off :
546 hw->acl_tbl->last_tcam + 1 - off -
551 return cnt >= r_entries ? ICE_SUCCESS : ICE_ERR_MAX_LIMIT;
555 * ice_acl_fill_tcam_select
556 * @scen_buf: Pointer to the scenario buffer that needs to be populated
557 * @scen: Pointer to the available space for the scenario
558 * @tcam_idx: Index of the TCAM used for this scenario
559 * @tcam_idx_in_cascade : Local index of the TCAM in the cascade scenario
561 * For all TCAM that participate in this scenario, fill out the tcam_select
565 ice_acl_fill_tcam_select(struct ice_aqc_acl_scen *scen_buf,
566 struct ice_acl_scen *scen, u16 tcam_idx,
567 u16 tcam_idx_in_cascade)
569 u16 cascade_cnt, idx;
572 idx = tcam_idx_in_cascade * ICE_AQC_ACL_KEY_WIDTH_BYTES;
573 cascade_cnt = DIVIDE_AND_ROUND_UP(scen->width,
574 ICE_AQC_ACL_KEY_WIDTH_BYTES);
576 /* For each scenario, we reserved last three bytes of scenario width for
577 * profile ID, range checker, and packet direction. Thus, the last three
578 * bytes of the last cascaded TCAMs will have value of 1st, 31st and
579 * 32nd byte location of BYTE selection base.
581 * For other bytes in the TCAMs:
582 * For non-cascade mode (1 TCAM wide) scenario, TCAM[x]'s Select {0-1}
583 * select indices 0-1 of the Byte Selection Base
584 * For cascade mode, the leftmost TCAM of the first cascade row selects
585 * indices 0-4 of the Byte Selection Base; the second TCAM in the
586 * cascade row selects indices starting with 5-n
588 for (j = 0; j < ICE_AQC_ACL_KEY_WIDTH_BYTES; j++) {
589 /* PKT DIR uses the 1st location of Byte Selection Base: + 1 */
590 u8 val = ICE_AQC_ACL_BYTE_SEL_BASE + 1 + idx;
592 if (tcam_idx_in_cascade == cascade_cnt - 1) {
593 if (j == ICE_ACL_SCEN_RNG_CHK_IDX_IN_TCAM)
594 val = ICE_AQC_ACL_BYTE_SEL_BASE_RNG_CHK;
595 else if (j == ICE_ACL_SCEN_PID_IDX_IN_TCAM)
596 val = ICE_AQC_ACL_BYTE_SEL_BASE_PID;
597 else if (j == ICE_ACL_SCEN_PKT_DIR_IDX_IN_TCAM)
598 val = ICE_AQC_ACL_BYTE_SEL_BASE_PKT_DIR;
601 /* In case that scenario's width is greater than the width of
602 * the Byte selection base, we will not assign a value to the
603 * tcam_select[j]. As a result, the tcam_select[j] will have
604 * default value which is zero.
606 if (val > ICE_AQC_ACL_BYTE_SEL_BASE_RNG_CHK)
609 scen_buf->tcam_cfg[tcam_idx].tcam_select[j] = val;
616 * ice_acl_set_scen_chnk_msk
617 * @scen_buf: Pointer to the scenario buffer that needs to be populated
618 * @scen: pointer to the available space for the scenario
620 * Set the chunk mask for the entries that will be used by this scenario
623 ice_acl_set_scen_chnk_msk(struct ice_aqc_acl_scen *scen_buf,
624 struct ice_acl_scen *scen)
626 u16 tcam_idx, num_cscd, units, cnt;
629 /* Determine the starting TCAM index and offset of the start entry */
630 tcam_idx = ICE_ACL_TBL_TCAM_IDX(scen->start);
631 chnk_offst = (u8)((scen->start % ICE_AQC_ACL_TCAM_DEPTH) /
632 ICE_ACL_ENTRY_ALLOC_UNIT);
634 /* Entries are allocated and tracked in multiple of 64's */
635 units = scen->num_entry / ICE_ACL_ENTRY_ALLOC_UNIT;
637 /* Determine number of cascaded TCAMs */
638 num_cscd = scen->width / ICE_AQC_ACL_KEY_WIDTH_BYTES;
640 for (cnt = 0; cnt < units; cnt++) {
643 /* Set the corresponding bitmap of individual 64-entry
644 * chunk spans across a cascade of 1 or more TCAMs
645 * For each TCAM, there will be (ICE_AQC_ACL_TCAM_DEPTH
646 * / ICE_ACL_ENTRY_ALLOC_UNIT) or 8 chunks.
648 for (i = tcam_idx; i < tcam_idx + num_cscd; i++)
649 scen_buf->tcam_cfg[i].chnk_msk |= BIT(chnk_offst);
651 chnk_offst = (chnk_offst + 1) % ICE_AQC_MAX_TCAM_ALLOC_UNITS;
653 tcam_idx += num_cscd;
658 * ice_acl_assign_act_mem_for_scen
659 * @tbl: pointer to ACL table structure
660 * @scen: pointer to the scenario struct
661 * @scen_buf: pointer to the available space for the scenario
662 * @current_tcam_idx: theoretical index of the TCAM that we associated those
663 * action memory banks with, at the table creation time.
664 * @target_tcam_idx: index of the TCAM that we want to associate those action
668 ice_acl_assign_act_mem_for_scen(struct ice_acl_tbl *tbl,
669 struct ice_acl_scen *scen,
670 struct ice_aqc_acl_scen *scen_buf,
676 for (i = 0; i < ICE_AQC_MAX_ACTION_MEMORIES; i++) {
677 struct ice_acl_act_mem *p_mem = &tbl->act_mems[i];
679 if (p_mem->act_mem == ICE_ACL_ACT_PAIR_MEM_INVAL ||
680 p_mem->member_of_tcam != current_tcam_idx)
683 scen_buf->act_mem_cfg[i] = target_tcam_idx;
684 scen_buf->act_mem_cfg[i] |= ICE_AQC_ACL_SCE_ACT_MEM_EN;
685 ice_set_bit(i, scen->act_mem_bitmap);
690 * ice_acl_commit_partition - Indicate if the specified partition is active
691 * @hw: pointer to the hardware structure
692 * @scen: pointer to the scenario struct
693 * @commit: true if the partition is being commit
696 ice_acl_commit_partition(struct ice_hw *hw, struct ice_acl_scen *scen,
699 u16 tcam_idx, off, num_cscd, units, cnt;
701 /* Determine the starting TCAM index and offset of the start entry */
702 tcam_idx = ICE_ACL_TBL_TCAM_IDX(scen->start);
703 off = (scen->start % ICE_AQC_ACL_TCAM_DEPTH) /
704 ICE_ACL_ENTRY_ALLOC_UNIT;
706 /* Entries are allocated and tracked in multiple of 64's */
707 units = scen->num_entry / ICE_ACL_ENTRY_ALLOC_UNIT;
709 /* Determine number of cascaded TCAM */
710 num_cscd = scen->width / ICE_AQC_ACL_KEY_WIDTH_BYTES;
712 for (cnt = 0; cnt < units; cnt++) {
715 /* Set/clear the corresponding bitmap of individual 64-entry
716 * chunk spans across a row of 1 or more TCAMs
718 for (w = 0; w < num_cscd; w++) {
721 b = ((tcam_idx + w) * ICE_AQC_MAX_TCAM_ALLOC_UNITS) +
724 ice_set_bit(b, hw->acl_tbl->avail);
726 ice_clear_bit(b, hw->acl_tbl->avail);
729 off = (off + 1) % ICE_AQC_MAX_TCAM_ALLOC_UNITS;
731 tcam_idx += num_cscd;
736 * ice_acl_create_scen
737 * @hw: pointer to the hardware structure
738 * @match_width: number of bytes to be matched in this scenario
739 * @num_entries: number of entries to be allocated for the scenario
740 * @scen_id: holds returned scenario ID if successful
743 ice_acl_create_scen(struct ice_hw *hw, u16 match_width, u16 num_entries,
746 u8 cascade_cnt, first_tcam, last_tcam, i, k;
747 struct ice_aqc_acl_scen scen_buf;
748 struct ice_acl_scen *scen;
749 enum ice_status status;
752 return ICE_ERR_DOES_NOT_EXIST;
754 scen = (struct ice_acl_scen *)ice_malloc(hw, sizeof(*scen));
756 return ICE_ERR_NO_MEMORY;
758 scen->start = hw->acl_tbl->first_entry;
759 scen->width = ICE_AQC_ACL_KEY_WIDTH_BYTES *
760 DIVIDE_AND_ROUND_UP(match_width, ICE_AQC_ACL_KEY_WIDTH_BYTES);
761 scen->num_entry = num_entries;
763 status = ice_acl_alloc_partition(hw, scen);
769 ice_memset(&scen_buf, 0, sizeof(scen_buf), ICE_NONDMA_MEM);
771 /* Determine the number of cascade TCAMs, given the scenario's width */
772 cascade_cnt = DIVIDE_AND_ROUND_UP(scen->width,
773 ICE_AQC_ACL_KEY_WIDTH_BYTES);
774 first_tcam = ICE_ACL_TBL_TCAM_IDX(scen->start);
775 last_tcam = ICE_ACL_TBL_TCAM_IDX(scen->end);
777 /* For each scenario, we reserved last three bytes of scenario width for
778 * packet direction flag, profile ID and range checker. Thus, we want to
779 * return back to the caller the eff_width, pkt_dir_idx, rng_chk_idx and
782 scen->eff_width = cascade_cnt * ICE_AQC_ACL_KEY_WIDTH_BYTES -
783 ICE_ACL_SCEN_MIN_WIDTH;
784 scen->rng_chk_idx = (cascade_cnt - 1) * ICE_AQC_ACL_KEY_WIDTH_BYTES +
785 ICE_ACL_SCEN_RNG_CHK_IDX_IN_TCAM;
786 scen->pid_idx = (cascade_cnt - 1) * ICE_AQC_ACL_KEY_WIDTH_BYTES +
787 ICE_ACL_SCEN_PID_IDX_IN_TCAM;
788 scen->pkt_dir_idx = (cascade_cnt - 1) * ICE_AQC_ACL_KEY_WIDTH_BYTES +
789 ICE_ACL_SCEN_PKT_DIR_IDX_IN_TCAM;
791 /* set the chunk mask for the tcams */
792 ice_acl_set_scen_chnk_msk(&scen_buf, scen);
794 /* set the TCAM select and start_cmp and start_set bits */
796 /* set the START_SET bit at the beginning of the stack */
797 scen_buf.tcam_cfg[k].start_cmp_set |= ICE_AQC_ACL_ALLOC_SCE_START_SET;
798 while (k <= last_tcam) {
799 u8 last_tcam_idx_cascade = cascade_cnt + k - 1;
801 /* set start_cmp for the first cascaded TCAM */
802 scen_buf.tcam_cfg[k].start_cmp_set |=
803 ICE_AQC_ACL_ALLOC_SCE_START_CMP;
805 /* cascade TCAMs up to the width of the scenario */
806 for (i = k; i < cascade_cnt + k; i++) {
807 ice_acl_fill_tcam_select(&scen_buf, scen, i, i - k);
808 ice_acl_assign_act_mem_for_scen(hw->acl_tbl, scen,
811 last_tcam_idx_cascade);
817 /* We need to set the start_cmp bit for the unused TCAMs. */
819 while (i < first_tcam)
820 scen_buf.tcam_cfg[i++].start_cmp_set =
821 ICE_AQC_ACL_ALLOC_SCE_START_CMP;
824 while (i < ICE_AQC_ACL_SLICES)
825 scen_buf.tcam_cfg[i++].start_cmp_set =
826 ICE_AQC_ACL_ALLOC_SCE_START_CMP;
828 status = ice_aq_alloc_acl_scen(hw, scen_id, &scen_buf, NULL);
830 ice_debug(hw, ICE_DBG_ACL, "AQ allocation of ACL scenario failed. status: %d\n",
837 ice_acl_commit_partition(hw, scen, false);
838 ice_acl_init_entry(scen);
839 LIST_ADD(&scen->list_entry, &hw->acl_tbl->scens);
845 * ice_acl_destroy_tbl - Destroy a previously created LEM table for ACL
846 * @hw: pointer to the HW struct
848 enum ice_status ice_acl_destroy_tbl(struct ice_hw *hw)
850 struct ice_acl_scen *pos_scen, *tmp_scen;
851 struct ice_aqc_acl_generic resp_buf;
852 struct ice_aqc_acl_scen buf;
853 enum ice_status status;
857 return ICE_ERR_DOES_NOT_EXIST;
859 /* Mark all the created scenario's TCAM to stop the packet lookup and
860 * delete them afterward
862 LIST_FOR_EACH_ENTRY_SAFE(pos_scen, tmp_scen, &hw->acl_tbl->scens,
863 ice_acl_scen, list_entry) {
864 status = ice_aq_query_acl_scen(hw, pos_scen->id, &buf, NULL);
866 ice_debug(hw, ICE_DBG_ACL, "ice_aq_query_acl_scen() failed. status: %d\n",
871 for (i = 0; i < ICE_AQC_ACL_SLICES; i++) {
872 buf.tcam_cfg[i].chnk_msk = 0;
873 buf.tcam_cfg[i].start_cmp_set =
874 ICE_AQC_ACL_ALLOC_SCE_START_CMP;
877 for (i = 0; i < ICE_AQC_MAX_ACTION_MEMORIES; i++)
878 buf.act_mem_cfg[i] = 0;
880 status = ice_aq_update_acl_scen(hw, pos_scen->id, &buf, NULL);
882 ice_debug(hw, ICE_DBG_ACL, "ice_aq_update_acl_scen() failed. status: %d\n",
887 status = ice_acl_destroy_scen(hw, pos_scen->id);
889 ice_debug(hw, ICE_DBG_ACL, "deletion of scenario failed. status: %d\n",
895 /* call the AQ command to destroy the ACL table */
896 status = ice_aq_dealloc_acl_tbl(hw, hw->acl_tbl->id, &resp_buf, NULL);
898 ice_debug(hw, ICE_DBG_ACL, "AQ de-allocation of ACL failed. status: %d\n",
903 ice_free(hw, hw->acl_tbl);
910 * ice_acl_add_entry - Add a flow entry to an ACL scenario
911 * @hw: pointer to the HW struct
912 * @scen: scenario to add the entry to
913 * @prior: priority level of the entry being added
914 * @keys: buffer of the value of the key to be programmed to the ACL entry
915 * @inverts: buffer of the value of the key inverts to be programmed
916 * @acts: pointer to a buffer containing formatted actions
917 * @acts_cnt: indicates the number of actions stored in "acts"
918 * @entry_idx: returned scenario relative index of the added flow entry
920 * Given an ACL table and a scenario, to add the specified key and key invert
921 * to an available entry in the specified scenario.
922 * The "keys" and "inverts" buffers must be of the size which is the same as
923 * the scenario's width
926 ice_acl_add_entry(struct ice_hw *hw, struct ice_acl_scen *scen,
927 enum ice_acl_entry_prior prior, u8 *keys, u8 *inverts,
928 struct ice_acl_act_entry *acts, u8 acts_cnt, u16 *entry_idx)
930 u8 i, entry_tcam, num_cscd, offset;
931 struct ice_aqc_acl_data buf;
932 enum ice_status status = ICE_SUCCESS;
936 return ICE_ERR_DOES_NOT_EXIST;
938 *entry_idx = ice_acl_scen_assign_entry_idx(scen, prior);
939 if (*entry_idx >= scen->num_entry) {
941 return ICE_ERR_MAX_LIMIT;
944 /* Determine number of cascaded TCAMs */
945 num_cscd = DIVIDE_AND_ROUND_UP(scen->width,
946 ICE_AQC_ACL_KEY_WIDTH_BYTES);
948 entry_tcam = ICE_ACL_TBL_TCAM_IDX(scen->start);
949 idx = ICE_ACL_TBL_TCAM_ENTRY_IDX(scen->start + *entry_idx);
951 ice_memset(&buf, 0, sizeof(buf), ICE_NONDMA_MEM);
952 for (i = 0; i < num_cscd; i++) {
953 /* If the key spans more than one TCAM in the case of cascaded
954 * TCAMs, the key and key inverts need to be properly split
955 * among TCAMs.E.g.bytes 0 - 4 go to an index in the first TCAM
956 * and bytes 5 - 9 go to the same index in the next TCAM, etc.
957 * If the entry spans more than one TCAM in a cascaded TCAM
958 * mode, the programming of the entries in the TCAMs must be in
959 * reversed order - the TCAM entry of the rightmost TCAM should
960 * be programmed first; the TCAM entry of the leftmost TCAM
961 * should be programmed last.
963 offset = num_cscd - i - 1;
964 ice_memcpy(&buf.entry_key.val,
965 &keys[offset * sizeof(buf.entry_key.val)],
966 sizeof(buf.entry_key.val), ICE_NONDMA_TO_NONDMA);
967 ice_memcpy(&buf.entry_key_invert.val,
968 &inverts[offset * sizeof(buf.entry_key_invert.val)],
969 sizeof(buf.entry_key_invert.val),
970 ICE_NONDMA_TO_NONDMA);
971 status = ice_aq_program_acl_entry(hw, entry_tcam + offset, idx,
974 ice_debug(hw, ICE_DBG_ACL, "aq program acl entry failed status: %d\n",
980 /* Program the action memory */
981 status = ice_acl_prog_act(hw, scen, acts, acts_cnt, *entry_idx);
985 ice_acl_rem_entry(hw, scen, *entry_idx);
993 * ice_acl_prog_act - Program a scenario's action memory
994 * @hw: pointer to the HW struct
995 * @scen: scenario to add the entry to
996 * @acts: pointer to a buffer containing formatted actions
997 * @acts_cnt: indicates the number of actions stored in "acts"
998 * @entry_idx: scenario relative index of the added flow entry
1000 * Program a scenario's action memory
1003 ice_acl_prog_act(struct ice_hw *hw, struct ice_acl_scen *scen,
1004 struct ice_acl_act_entry *acts, u8 acts_cnt,
1007 u8 entry_tcam, num_cscd, i, actx_idx = 0;
1008 struct ice_aqc_actpair act_buf;
1009 enum ice_status status = ICE_SUCCESS;
1012 if (entry_idx >= scen->num_entry)
1013 return ICE_ERR_MAX_LIMIT;
1015 ice_memset(&act_buf, 0, sizeof(act_buf), ICE_NONDMA_MEM);
1017 /* Determine number of cascaded TCAMs */
1018 num_cscd = DIVIDE_AND_ROUND_UP(scen->width,
1019 ICE_AQC_ACL_KEY_WIDTH_BYTES);
1021 entry_tcam = ICE_ACL_TBL_TCAM_IDX(scen->start);
1022 idx = ICE_ACL_TBL_TCAM_ENTRY_IDX(scen->start + entry_idx);
1024 ice_for_each_set_bit(i, scen->act_mem_bitmap,
1025 ICE_AQC_MAX_ACTION_MEMORIES) {
1026 struct ice_acl_act_mem *mem = &hw->acl_tbl->act_mems[i];
1028 if (actx_idx >= acts_cnt)
1030 if (mem->member_of_tcam >= entry_tcam &&
1031 mem->member_of_tcam < entry_tcam + num_cscd) {
1032 ice_memcpy(&act_buf.act[0], &acts[actx_idx],
1033 sizeof(struct ice_acl_act_entry),
1034 ICE_NONDMA_TO_NONDMA);
1036 if (++actx_idx < acts_cnt) {
1037 ice_memcpy(&act_buf.act[1], &acts[actx_idx],
1038 sizeof(struct ice_acl_act_entry),
1039 ICE_NONDMA_TO_NONDMA);
1042 status = ice_aq_program_actpair(hw, i, idx, &act_buf,
1045 ice_debug(hw, ICE_DBG_ACL, "program actpair failed status: %d\n",
1053 if (!status && actx_idx < acts_cnt)
1054 status = ICE_ERR_MAX_LIMIT;
1060 * ice_acl_rem_entry - Remove a flow entry from an ACL scenario
1061 * @hw: pointer to the HW struct
1062 * @scen: scenario to remove the entry from
1063 * @entry_idx: the scenario-relative index of the flow entry being removed
1066 ice_acl_rem_entry(struct ice_hw *hw, struct ice_acl_scen *scen, u16 entry_idx)
1068 struct ice_aqc_actpair act_buf;
1069 struct ice_aqc_acl_data buf;
1070 u8 entry_tcam, num_cscd, i;
1071 enum ice_status status = ICE_SUCCESS;
1075 return ICE_ERR_DOES_NOT_EXIST;
1077 if (entry_idx >= scen->num_entry)
1078 return ICE_ERR_MAX_LIMIT;
1080 if (!ice_is_bit_set(scen->entry_bitmap, entry_idx))
1081 return ICE_ERR_DOES_NOT_EXIST;
1083 /* Determine number of cascaded TCAMs */
1084 num_cscd = DIVIDE_AND_ROUND_UP(scen->width,
1085 ICE_AQC_ACL_KEY_WIDTH_BYTES);
1087 entry_tcam = ICE_ACL_TBL_TCAM_IDX(scen->start);
1088 idx = ICE_ACL_TBL_TCAM_ENTRY_IDX(scen->start + entry_idx);
1090 /* invalidate the flow entry */
1091 ice_memset(&buf, 0, sizeof(buf), ICE_NONDMA_MEM);
1092 for (i = 0; i < num_cscd; i++) {
1093 status = ice_aq_program_acl_entry(hw, entry_tcam + i, idx, &buf,
1096 ice_debug(hw, ICE_DBG_ACL, "AQ program ACL entry failed status: %d\n",
1100 ice_memset(&act_buf, 0, sizeof(act_buf), ICE_NONDMA_MEM);
1102 ice_for_each_set_bit(i, scen->act_mem_bitmap,
1103 ICE_AQC_MAX_ACTION_MEMORIES) {
1104 struct ice_acl_act_mem *mem = &hw->acl_tbl->act_mems[i];
1106 if (mem->member_of_tcam >= entry_tcam &&
1107 mem->member_of_tcam < entry_tcam + num_cscd) {
1108 /* Invalidate allocated action pairs */
1109 status = ice_aq_program_actpair(hw, i, idx, &act_buf,
1112 ice_debug(hw, ICE_DBG_ACL, "program actpair failed status: %d\n",
1117 ice_acl_scen_free_entry_idx(scen, entry_idx);
1123 * ice_acl_destroy_scen - Destroy an ACL scenario
1124 * @hw: pointer to the HW struct
1125 * @scen_id: ID of the remove scenario
1127 enum ice_status ice_acl_destroy_scen(struct ice_hw *hw, u16 scen_id)
1129 struct ice_acl_scen *scen, *tmp_scen;
1130 struct ice_flow_prof *p, *tmp;
1131 enum ice_status status;
1134 return ICE_ERR_DOES_NOT_EXIST;
1136 /* Remove profiles that use "scen_id" scenario */
1137 LIST_FOR_EACH_ENTRY_SAFE(p, tmp, &hw->fl_profs[ICE_BLK_ACL],
1138 ice_flow_prof, l_entry)
1139 if (p->cfg.scen && p->cfg.scen->id == scen_id) {
1140 status = ice_flow_rem_prof(hw, ICE_BLK_ACL, p->id);
1142 ice_debug(hw, ICE_DBG_ACL,
1143 "ice_flow_rem_prof failed. status: %d\n",
1149 /* Call the AQ command to destroy the targeted scenario */
1150 status = ice_aq_dealloc_acl_scen(hw, scen_id, NULL);
1153 ice_debug(hw, ICE_DBG_ACL,
1154 "AQ de-allocation of scenario failed. status: %d\n",
1159 /* Remove scenario from hw->acl_tbl->scens */
1160 LIST_FOR_EACH_ENTRY_SAFE(scen, tmp_scen, &hw->acl_tbl->scens,
1161 ice_acl_scen, list_entry)
1162 if (scen->id == scen_id) {
1163 LIST_DEL(&scen->list_entry);