1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2001-2020 Intel Corporation
8 /* Determine the TCAM index of entry 'e' within the ACL table */
9 #define ICE_ACL_TBL_TCAM_IDX(e) ((e) / ICE_AQC_ACL_TCAM_DEPTH)
11 /* Determine the entry index within the TCAM */
12 #define ICE_ACL_TBL_TCAM_ENTRY_IDX(e) ((e) % ICE_AQC_ACL_TCAM_DEPTH)
14 #define ICE_ACL_SCEN_ENTRY_INVAL 0xFFFF
18 * @scen: pointer to the scenario struct
20 * Initialize the scenario control structure.
22 static void ice_acl_init_entry(struct ice_acl_scen *scen)
24 /* low priority: start from the highest index, 25% of total entries
25 * normal priority: start from the highest index, 50% of total entries
26 * high priority: start from the lowest index, 25% of total entries
28 scen->first_idx[ICE_LOW] = scen->num_entry - 1;
29 scen->first_idx[ICE_NORMAL] = scen->num_entry - scen->num_entry / 4 - 1;
30 scen->first_idx[ICE_HIGH] = 0;
32 scen->last_idx[ICE_LOW] = scen->num_entry - scen->num_entry / 4;
33 scen->last_idx[ICE_NORMAL] = scen->num_entry / 4;
34 scen->last_idx[ICE_HIGH] = scen->num_entry / 4 - 1;
38 * ice_acl_scen_assign_entry_idx
39 * @scen: pointer to the scenario struct
40 * @prior: the priority of the flow entry being allocated
42 * To find the index of an available entry in scenario
44 * Returns ICE_ACL_SCEN_ENTRY_INVAL if fails
45 * Returns index on success
48 ice_acl_scen_assign_entry_idx(struct ice_acl_scen *scen,
49 enum ice_acl_entry_prior prior)
51 u16 first_idx, last_idx, i;
54 if (prior >= ICE_MAX_PRIOR)
55 return ICE_ACL_SCEN_ENTRY_INVAL;
57 first_idx = scen->first_idx[prior];
58 last_idx = scen->last_idx[prior];
59 step = first_idx <= last_idx ? 1 : -1;
61 for (i = first_idx; i != last_idx + step; i += step)
62 if (!ice_test_and_set_bit(i, scen->entry_bitmap))
65 return ICE_ACL_SCEN_ENTRY_INVAL;
69 * ice_acl_scen_free_entry_idx
70 * @scen: pointer to the scenario struct
71 * @idx: the index of the flow entry being de-allocated
73 * To mark an entry available in scenario
75 static enum ice_status
76 ice_acl_scen_free_entry_idx(struct ice_acl_scen *scen, u16 idx)
78 if (idx >= scen->num_entry)
79 return ICE_ERR_MAX_LIMIT;
81 if (!ice_test_and_clear_bit(idx, scen->entry_bitmap))
82 return ICE_ERR_DOES_NOT_EXIST;
88 * ice_acl_tbl_calc_end_idx
89 * @start: start index of the TCAM entry of this partition
90 * @num_entries: number of entries in this partition
91 * @width: width of a partition in number of TCAMs
93 * Calculate the end entry index for a partition with starting entry index
94 * 'start', entries 'num_entries', and width 'width'.
96 static u16 ice_acl_tbl_calc_end_idx(u16 start, u16 num_entries, u16 width)
98 u16 end_idx, add_entries = 0;
100 end_idx = start + (num_entries - 1);
102 /* In case that our ACL partition requires cascading TCAMs */
106 /* Figure out the TCAM stacked level in this ACL scenario */
107 num_stack_level = (start % ICE_AQC_ACL_TCAM_DEPTH) +
109 num_stack_level = DIVIDE_AND_ROUND_UP(num_stack_level,
110 ICE_AQC_ACL_TCAM_DEPTH);
112 /* In this case, each entries in our ACL partition span
113 * multiple TCAMs. Thus, we will need to add
114 * ((width - 1) * num_stack_level) TCAM's entries to
117 * For example : In our case, our scenario is 2x2:
120 * Assuming that a TCAM will have 512 entries. If "start"
121 * is 500, "num_entries" is 3 and "width" = 2, then end_idx
122 * should be 1024 (belongs to TCAM 2).
123 * Before going to this if statement, end_idx will have the
124 * value of 512. If "width" is 1, then the final value of
125 * end_idx is 512. However, in our case, width is 2, then we
126 * will need add (2 - 1) * 1 * 512. As result, end_idx will
127 * have the value of 1024.
129 add_entries = (width - 1) * num_stack_level *
130 ICE_AQC_ACL_TCAM_DEPTH;
133 return end_idx + add_entries;
138 * @hw: pointer to the hardware structure
140 * Initialize the ACL table by invalidating TCAM entries and action pairs.
142 static enum ice_status ice_acl_init_tbl(struct ice_hw *hw)
144 struct ice_aqc_actpair act_buf;
145 struct ice_aqc_acl_data buf;
146 enum ice_status status = ICE_SUCCESS;
147 struct ice_acl_tbl *tbl;
155 ice_memset(&buf, 0, sizeof(buf), ICE_NONDMA_MEM);
156 ice_memset(&act_buf, 0, sizeof(act_buf), ICE_NONDMA_MEM);
158 tcam_idx = tbl->first_tcam;
159 idx = tbl->first_entry;
160 while (tcam_idx < tbl->last_tcam ||
161 (tcam_idx == tbl->last_tcam && idx <= tbl->last_entry)) {
162 /* Use the same value for entry_key and entry_key_inv since
163 * we are initializing the fields to 0
165 status = ice_aq_program_acl_entry(hw, tcam_idx, idx, &buf,
170 if (++idx > tbl->last_entry) {
172 idx = tbl->first_entry;
176 for (i = 0; i < ICE_AQC_MAX_ACTION_MEMORIES; i++) {
177 u16 act_entry_idx, start, end;
179 if (tbl->act_mems[i].act_mem == ICE_ACL_ACT_PAIR_MEM_INVAL)
182 start = tbl->first_entry;
183 end = tbl->last_entry;
185 for (act_entry_idx = start; act_entry_idx <= end;
187 /* Invalidate all allocated action pairs */
188 status = ice_aq_program_actpair(hw, i, act_entry_idx,
199 * ice_acl_assign_act_mems_to_tcam
200 * @tbl: pointer to ACL table structure
201 * @cur_tcam: Index of current TCAM. Value = 0 to (ICE_AQC_ACL_SLICES - 1)
202 * @cur_mem_idx: Index of current action memory bank. Value = 0 to
203 * (ICE_AQC_MAX_ACTION_MEMORIES - 1)
204 * @num_mem: Number of action memory banks for this TCAM
206 * Assign "num_mem" valid action memory banks from "curr_mem_idx" to
210 ice_acl_assign_act_mems_to_tcam(struct ice_acl_tbl *tbl, u8 cur_tcam,
211 u8 *cur_mem_idx, u8 num_mem)
216 *cur_mem_idx < ICE_AQC_MAX_ACTION_MEMORIES && mem_cnt < num_mem;
218 struct ice_acl_act_mem *p_mem = &tbl->act_mems[*cur_mem_idx];
220 if (p_mem->act_mem == ICE_ACL_ACT_PAIR_MEM_INVAL)
223 p_mem->member_of_tcam = cur_tcam;
230 * ice_acl_divide_act_mems_to_tcams
231 * @tbl: pointer to ACL table structure
233 * Figure out how to divide given action memory banks to given TCAMs. This
234 * division is for SW book keeping. In the time when scenario is created,
235 * an action memory bank can be used for different TCAM.
237 * For example, given that we have 2x2 ACL table with each table entry has
238 * 2 action memory pairs. As the result, we will have 4 TCAMs (T1,T2,T3,T4)
239 * and 4 action memory banks (A1,A2,A3,A4)
240 * [T1 - T2] { A1 - A2 }
241 * [T3 - T4] { A3 - A4 }
242 * In the time when we need to create a scenario, for example, 2x1 scenario,
243 * we will use [T3,T4] in a cascaded layout. As it is a requirement that all
244 * action memory banks in a cascaded TCAM's row will need to associate with
245 * the last TCAM. Thus, we will associate action memory banks [A3] and [A4]
247 * For SW book-keeping purpose, we will keep theoretical maps between TCAM
248 * [Tn] to action memory bank [An].
250 static void ice_acl_divide_act_mems_to_tcams(struct ice_acl_tbl *tbl)
252 u16 num_cscd, stack_level, stack_idx, min_act_mem;
253 u8 tcam_idx = tbl->first_tcam;
254 u16 max_idx_to_get_extra;
257 /* Determine number of stacked TCAMs */
258 stack_level = DIVIDE_AND_ROUND_UP(tbl->info.depth,
259 ICE_AQC_ACL_TCAM_DEPTH);
261 /* Determine number of cascaded TCAMs */
262 num_cscd = DIVIDE_AND_ROUND_UP(tbl->info.width,
263 ICE_AQC_ACL_KEY_WIDTH_BYTES);
265 /* In a line of cascaded TCAM, given the number of action memory
266 * banks per ACL table entry, we want to fairly divide these action
267 * memory banks between these TCAMs.
269 * For example, there are 3 TCAMs (TCAM 3,4,5) in a line of
270 * cascaded TCAM, and there are 7 act_mems for each ACL table entry.
272 * [TCAM_3 will have 3 act_mems]
273 * [TCAM_4 will have 2 act_mems]
274 * [TCAM_5 will have 2 act_mems]
276 min_act_mem = tbl->info.entry_act_pairs / num_cscd;
277 max_idx_to_get_extra = tbl->info.entry_act_pairs % num_cscd;
279 for (stack_idx = 0; stack_idx < stack_level; stack_idx++) {
282 for (i = 0; i < num_cscd; i++) {
283 u8 total_act_mem = min_act_mem;
285 if (i < max_idx_to_get_extra)
288 ice_acl_assign_act_mems_to_tcam(tbl, tcam_idx,
299 * @hw: pointer to the HW struct
300 * @params: parameters for the table to be created
302 * Create a LEM table for ACL usage. We are currently starting with some fixed
303 * values for the size of the table, but this will need to grow as more flow
304 * entries are added by the user level.
307 ice_acl_create_tbl(struct ice_hw *hw, struct ice_acl_tbl_params *params)
309 u16 width, depth, first_e, last_e, i;
310 struct ice_aqc_acl_generic *resp_buf;
311 struct ice_acl_alloc_tbl tbl_alloc;
312 struct ice_acl_tbl *tbl;
313 enum ice_status status;
316 return ICE_ERR_ALREADY_EXISTS;
319 return ICE_ERR_PARAM;
321 /* round up the width to the next TCAM width boundary. */
322 width = ROUND_UP(params->width, (u16)ICE_AQC_ACL_KEY_WIDTH_BYTES);
323 /* depth should be provided in chunk (64 entry) increments */
324 depth = ICE_ALIGN(params->depth, ICE_ACL_ENTRY_ALLOC_UNIT);
326 if (params->entry_act_pairs < width / ICE_AQC_ACL_KEY_WIDTH_BYTES) {
327 params->entry_act_pairs = width / ICE_AQC_ACL_KEY_WIDTH_BYTES;
329 if (params->entry_act_pairs > ICE_AQC_TBL_MAX_ACTION_PAIRS)
330 params->entry_act_pairs = ICE_AQC_TBL_MAX_ACTION_PAIRS;
333 /* Validate that width*depth will not exceed the TCAM limit */
334 if ((DIVIDE_AND_ROUND_UP(depth, ICE_AQC_ACL_TCAM_DEPTH) *
335 (width / ICE_AQC_ACL_KEY_WIDTH_BYTES)) > ICE_AQC_ACL_SLICES)
336 return ICE_ERR_MAX_LIMIT;
338 ice_memset(&tbl_alloc, 0, sizeof(tbl_alloc), ICE_NONDMA_MEM);
339 tbl_alloc.width = width;
340 tbl_alloc.depth = depth;
341 tbl_alloc.act_pairs_per_entry = params->entry_act_pairs;
342 tbl_alloc.concurr = params->concurr;
343 /* Set dependent_alloc_id only for concurrent table type */
344 if (params->concurr) {
345 tbl_alloc.num_dependent_alloc_ids =
346 ICE_AQC_MAX_CONCURRENT_ACL_TBL;
348 for (i = 0; i < ICE_AQC_MAX_CONCURRENT_ACL_TBL; i++)
349 tbl_alloc.buf.data_buf.alloc_ids[i] =
350 CPU_TO_LE16(params->dep_tbls[i]);
353 /* call the AQ command to create the ACL table with these values */
354 status = ice_aq_alloc_acl_tbl(hw, &tbl_alloc, NULL);
356 if (LE16_TO_CPU(tbl_alloc.buf.resp_buf.alloc_id) <
357 ICE_AQC_ALLOC_ID_LESS_THAN_4K)
358 ice_debug(hw, ICE_DBG_ACL, "Alloc ACL table failed. Unavailable resource.\n");
360 ice_debug(hw, ICE_DBG_ACL, "AQ allocation of ACL failed with error. status: %d\n",
365 tbl = (struct ice_acl_tbl *)ice_malloc(hw, sizeof(*tbl));
367 status = ICE_ERR_NO_MEMORY;
372 resp_buf = &tbl_alloc.buf.resp_buf;
374 /* Retrieve information of the allocated table */
375 tbl->id = LE16_TO_CPU(resp_buf->alloc_id);
376 tbl->first_tcam = resp_buf->ops.table.first_tcam;
377 tbl->last_tcam = resp_buf->ops.table.last_tcam;
378 tbl->first_entry = LE16_TO_CPU(resp_buf->first_entry);
379 tbl->last_entry = LE16_TO_CPU(resp_buf->last_entry);
382 tbl->info.width = width;
383 tbl->info.depth = depth;
386 for (i = 0; i < ICE_AQC_MAX_ACTION_MEMORIES; i++)
387 tbl->act_mems[i].act_mem = resp_buf->act_mem[i];
389 /* Figure out which TCAMs that these newly allocated action memories
392 ice_acl_divide_act_mems_to_tcams(tbl);
394 /* Initialize the resources allocated by invalidating all TCAM entries
395 * and all the action pairs
397 status = ice_acl_init_tbl(hw);
401 ice_debug(hw, ICE_DBG_ACL, "Initialization of TCAM entries failed. status: %d\n",
406 first_e = (tbl->first_tcam * ICE_AQC_MAX_TCAM_ALLOC_UNITS) +
407 (tbl->first_entry / ICE_ACL_ENTRY_ALLOC_UNIT);
408 last_e = (tbl->last_tcam * ICE_AQC_MAX_TCAM_ALLOC_UNITS) +
409 (tbl->last_entry / ICE_ACL_ENTRY_ALLOC_UNIT);
411 /* Indicate available entries in the table */
412 ice_bitmap_set(tbl->avail, first_e, last_e - first_e + 1);
414 INIT_LIST_HEAD(&tbl->scens);
421 * ice_acl_alloc_partition - Allocate a partition from the ACL table
422 * @hw: pointer to the hardware structure
423 * @req: info of partition being allocated
425 static enum ice_status
426 ice_acl_alloc_partition(struct ice_hw *hw, struct ice_acl_scen *req)
428 u16 start = 0, cnt = 0, off = 0;
429 u16 width, r_entries, row;
433 /* Determine the number of TCAMs each entry overlaps */
434 width = DIVIDE_AND_ROUND_UP(req->width, ICE_AQC_ACL_KEY_WIDTH_BYTES);
436 /* Check if we have enough TCAMs to accommodate the width */
437 if (width > hw->acl_tbl->last_tcam - hw->acl_tbl->first_tcam + 1)
438 return ICE_ERR_MAX_LIMIT;
440 /* Number of entries must be multiple of ICE_ACL_ENTRY_ALLOC_UNIT's */
441 r_entries = ICE_ALIGN(req->num_entry, ICE_ACL_ENTRY_ALLOC_UNIT);
443 /* To look for an available partition that can accommodate the request,
444 * the process first logically arranges available TCAMs in rows such
445 * that each row produces entries with the requested width. It then
446 * scans the TCAMs' available bitmap, one bit at a time, and
447 * accumulates contiguous available 64-entry chunks until there are
448 * enough of them or when all TCAM configurations have been checked.
450 * For width of 1 TCAM, the scanning process starts from the top most
451 * TCAM, and goes downward. Available bitmaps are examined from LSB
454 * For width of multiple TCAMs, the process starts from the bottom-most
455 * row of TCAMs, and goes upward. Available bitmaps are examined from
456 * the MSB to the LSB.
458 * To make sure that adjacent TCAMs can be logically arranged in the
459 * same row, the scanning process may have multiple passes. In each
460 * pass, the first TCAM of the bottom-most row is displaced by one
461 * additional TCAM. The width of the row and the number of the TCAMs
462 * available determine the number of passes. When the displacement is
463 * more than the size of width, the TCAM row configurations will
464 * repeat. The process will terminate when the configurations repeat.
466 * Available partitions can span more than one row of TCAMs.
469 row = hw->acl_tbl->first_tcam;
472 /* Start with the bottom-most row, and scan for available
475 row = hw->acl_tbl->last_tcam + 1 - width;
482 /* Scan all 64-entry chunks, one chunk at a time, in the
486 i < ICE_AQC_MAX_TCAM_ALLOC_UNITS && cnt < r_entries;
491 /* Compute the cumulative available mask across the
492 * TCAM row to determine if the current 64-entry chunk
495 p = dir > 0 ? i : ICE_AQC_MAX_TCAM_ALLOC_UNITS - i - 1;
496 for (w = row; w < row + width && avail; w++) {
499 b = (w * ICE_AQC_MAX_TCAM_ALLOC_UNITS) + p;
500 avail &= ice_is_bit_set(hw->acl_tbl->avail, b);
506 /* Compute the starting index of the newly
507 * found partition. When 'dir' is negative, the
508 * scan processes is going upward. If so, the
509 * starting index needs to be updated for every
510 * available 64-entry chunk found.
513 start = (row * ICE_AQC_ACL_TCAM_DEPTH) +
514 (p * ICE_ACL_ENTRY_ALLOC_UNIT);
515 cnt += ICE_ACL_ENTRY_ALLOC_UNIT;
519 if (cnt >= r_entries) {
521 req->num_entry = r_entries;
522 req->end = ice_acl_tbl_calc_end_idx(start, r_entries,
527 row = dir > 0 ? row + width : row - width;
528 if (row > hw->acl_tbl->last_tcam ||
529 row < hw->acl_tbl->first_tcam) {
530 /* All rows have been checked. Increment 'off' that
531 * will help yield a different TCAM configuration in
532 * which adjacent TCAMs can be alternatively in the
537 /* However, if the new 'off' value yields previously
538 * checked configurations, then exit.
543 row = dir > 0 ? off :
544 hw->acl_tbl->last_tcam + 1 - off -
549 return cnt >= r_entries ? ICE_SUCCESS : ICE_ERR_MAX_LIMIT;
553 * ice_acl_fill_tcam_select
554 * @scen_buf: Pointer to the scenario buffer that needs to be populated
555 * @scen: Pointer to the available space for the scenario
556 * @tcam_idx: Index of the TCAM used for this scenario
557 * @tcam_idx_in_cascade : Local index of the TCAM in the cascade scenario
559 * For all TCAM that participate in this scenario, fill out the tcam_select
563 ice_acl_fill_tcam_select(struct ice_aqc_acl_scen *scen_buf,
564 struct ice_acl_scen *scen, u16 tcam_idx,
565 u16 tcam_idx_in_cascade)
567 u16 cascade_cnt, idx;
570 idx = tcam_idx_in_cascade * ICE_AQC_ACL_KEY_WIDTH_BYTES;
571 cascade_cnt = DIVIDE_AND_ROUND_UP(scen->width,
572 ICE_AQC_ACL_KEY_WIDTH_BYTES);
574 /* For each scenario, we reserved last three bytes of scenario width for
575 * profile ID, range checker, and packet direction. Thus, the last three
576 * bytes of the last cascaded TCAMs will have value of 1st, 31st and
577 * 32nd byte location of BYTE selection base.
579 * For other bytes in the TCAMs:
580 * For non-cascade mode (1 TCAM wide) scenario, TCAM[x]'s Select {0-1}
581 * select indices 0-1 of the Byte Selection Base
582 * For cascade mode, the leftmost TCAM of the first cascade row selects
583 * indices 0-4 of the Byte Selection Base; the second TCAM in the
584 * cascade row selects indices starting with 5-n
586 for (j = 0; j < ICE_AQC_ACL_KEY_WIDTH_BYTES; j++) {
587 /* PKT DIR uses the 1st location of Byte Selection Base: + 1 */
588 u8 val = ICE_AQC_ACL_BYTE_SEL_BASE + 1 + idx;
590 if (tcam_idx_in_cascade == cascade_cnt - 1) {
591 if (j == ICE_ACL_SCEN_RNG_CHK_IDX_IN_TCAM)
592 val = ICE_AQC_ACL_BYTE_SEL_BASE_RNG_CHK;
593 else if (j == ICE_ACL_SCEN_PID_IDX_IN_TCAM)
594 val = ICE_AQC_ACL_BYTE_SEL_BASE_PID;
595 else if (j == ICE_ACL_SCEN_PKT_DIR_IDX_IN_TCAM)
596 val = ICE_AQC_ACL_BYTE_SEL_BASE_PKT_DIR;
599 /* In case that scenario's width is greater than the width of
600 * the Byte selection base, we will not assign a value to the
601 * tcam_select[j]. As a result, the tcam_select[j] will have
602 * default value which is zero.
604 if (val > ICE_AQC_ACL_BYTE_SEL_BASE_RNG_CHK)
607 scen_buf->tcam_cfg[tcam_idx].tcam_select[j] = val;
614 * ice_acl_set_scen_chnk_msk
615 * @scen_buf: Pointer to the scenario buffer that needs to be populated
616 * @scen: pointer to the available space for the scenario
618 * Set the chunk mask for the entries that will be used by this scenario
621 ice_acl_set_scen_chnk_msk(struct ice_aqc_acl_scen *scen_buf,
622 struct ice_acl_scen *scen)
624 u16 tcam_idx, num_cscd, units, cnt;
627 /* Determine the starting TCAM index and offset of the start entry */
628 tcam_idx = ICE_ACL_TBL_TCAM_IDX(scen->start);
629 chnk_offst = (u8)((scen->start % ICE_AQC_ACL_TCAM_DEPTH) /
630 ICE_ACL_ENTRY_ALLOC_UNIT);
632 /* Entries are allocated and tracked in multiple of 64's */
633 units = scen->num_entry / ICE_ACL_ENTRY_ALLOC_UNIT;
635 /* Determine number of cascaded TCAMs */
636 num_cscd = scen->width / ICE_AQC_ACL_KEY_WIDTH_BYTES;
638 for (cnt = 0; cnt < units; cnt++) {
641 /* Set the corresponding bitmap of individual 64-entry
642 * chunk spans across a cascade of 1 or more TCAMs
643 * For each TCAM, there will be (ICE_AQC_ACL_TCAM_DEPTH
644 * / ICE_ACL_ENTRY_ALLOC_UNIT) or 8 chunks.
646 for (i = tcam_idx; i < tcam_idx + num_cscd; i++)
647 scen_buf->tcam_cfg[i].chnk_msk |= BIT(chnk_offst);
649 chnk_offst = (chnk_offst + 1) % ICE_AQC_MAX_TCAM_ALLOC_UNITS;
651 tcam_idx += num_cscd;
656 * ice_acl_assign_act_mem_for_scen
657 * @tbl: pointer to ACL table structure
658 * @scen: pointer to the scenario struct
659 * @scen_buf: pointer to the available space for the scenario
660 * @current_tcam_idx: theoretical index of the TCAM that we associated those
661 * action memory banks with, at the table creation time.
662 * @target_tcam_idx: index of the TCAM that we want to associate those action
666 ice_acl_assign_act_mem_for_scen(struct ice_acl_tbl *tbl,
667 struct ice_acl_scen *scen,
668 struct ice_aqc_acl_scen *scen_buf,
669 u8 current_tcam_idx, u8 target_tcam_idx)
673 for (i = 0; i < ICE_AQC_MAX_ACTION_MEMORIES; i++) {
674 struct ice_acl_act_mem *p_mem = &tbl->act_mems[i];
676 if (p_mem->act_mem == ICE_ACL_ACT_PAIR_MEM_INVAL ||
677 p_mem->member_of_tcam != current_tcam_idx)
680 scen_buf->act_mem_cfg[i] = target_tcam_idx;
681 scen_buf->act_mem_cfg[i] |= ICE_AQC_ACL_SCE_ACT_MEM_EN;
682 ice_set_bit(i, scen->act_mem_bitmap);
687 * ice_acl_commit_partition - Indicate if the specified partition is active
688 * @hw: pointer to the hardware structure
689 * @scen: pointer to the scenario struct
690 * @commit: true if the partition is being commit
693 ice_acl_commit_partition(struct ice_hw *hw, struct ice_acl_scen *scen,
696 u16 tcam_idx, off, num_cscd, units, cnt;
698 /* Determine the starting TCAM index and offset of the start entry */
699 tcam_idx = ICE_ACL_TBL_TCAM_IDX(scen->start);
700 off = (scen->start % ICE_AQC_ACL_TCAM_DEPTH) /
701 ICE_ACL_ENTRY_ALLOC_UNIT;
703 /* Entries are allocated and tracked in multiple of 64's */
704 units = scen->num_entry / ICE_ACL_ENTRY_ALLOC_UNIT;
706 /* Determine number of cascaded TCAM */
707 num_cscd = scen->width / ICE_AQC_ACL_KEY_WIDTH_BYTES;
709 for (cnt = 0; cnt < units; cnt++) {
712 /* Set/clear the corresponding bitmap of individual 64-entry
713 * chunk spans across a row of 1 or more TCAMs
715 for (w = 0; w < num_cscd; w++) {
718 b = ((tcam_idx + w) * ICE_AQC_MAX_TCAM_ALLOC_UNITS) +
721 ice_set_bit(b, hw->acl_tbl->avail);
723 ice_clear_bit(b, hw->acl_tbl->avail);
726 off = (off + 1) % ICE_AQC_MAX_TCAM_ALLOC_UNITS;
728 tcam_idx += num_cscd;
733 * ice_acl_create_scen
734 * @hw: pointer to the hardware structure
735 * @match_width: number of bytes to be matched in this scenario
736 * @num_entries: number of entries to be allocated for the scenario
737 * @scen_id: holds returned scenario ID if successful
740 ice_acl_create_scen(struct ice_hw *hw, u16 match_width, u16 num_entries,
743 u8 cascade_cnt, first_tcam, last_tcam, i, k;
744 struct ice_aqc_acl_scen scen_buf;
745 struct ice_acl_scen *scen;
746 enum ice_status status;
749 return ICE_ERR_DOES_NOT_EXIST;
751 scen = (struct ice_acl_scen *)ice_malloc(hw, sizeof(*scen));
753 return ICE_ERR_NO_MEMORY;
755 scen->start = hw->acl_tbl->first_entry;
756 scen->width = ICE_AQC_ACL_KEY_WIDTH_BYTES *
757 DIVIDE_AND_ROUND_UP(match_width, ICE_AQC_ACL_KEY_WIDTH_BYTES);
758 scen->num_entry = num_entries;
760 status = ice_acl_alloc_partition(hw, scen);
764 ice_memset(&scen_buf, 0, sizeof(scen_buf), ICE_NONDMA_MEM);
766 /* Determine the number of cascade TCAMs, given the scenario's width */
767 cascade_cnt = DIVIDE_AND_ROUND_UP(scen->width,
768 ICE_AQC_ACL_KEY_WIDTH_BYTES);
769 first_tcam = ICE_ACL_TBL_TCAM_IDX(scen->start);
770 last_tcam = ICE_ACL_TBL_TCAM_IDX(scen->end);
772 /* For each scenario, we reserved last three bytes of scenario width for
773 * packet direction flag, profile ID and range checker. Thus, we want to
774 * return back to the caller the eff_width, pkt_dir_idx, rng_chk_idx and
777 scen->eff_width = cascade_cnt * ICE_AQC_ACL_KEY_WIDTH_BYTES -
778 ICE_ACL_SCEN_MIN_WIDTH;
779 scen->rng_chk_idx = (cascade_cnt - 1) * ICE_AQC_ACL_KEY_WIDTH_BYTES +
780 ICE_ACL_SCEN_RNG_CHK_IDX_IN_TCAM;
781 scen->pid_idx = (cascade_cnt - 1) * ICE_AQC_ACL_KEY_WIDTH_BYTES +
782 ICE_ACL_SCEN_PID_IDX_IN_TCAM;
783 scen->pkt_dir_idx = (cascade_cnt - 1) * ICE_AQC_ACL_KEY_WIDTH_BYTES +
784 ICE_ACL_SCEN_PKT_DIR_IDX_IN_TCAM;
786 /* set the chunk mask for the tcams */
787 ice_acl_set_scen_chnk_msk(&scen_buf, scen);
789 /* set the TCAM select and start_cmp and start_set bits */
791 /* set the START_SET bit at the beginning of the stack */
792 scen_buf.tcam_cfg[k].start_cmp_set |= ICE_AQC_ACL_ALLOC_SCE_START_SET;
793 while (k <= last_tcam) {
794 u8 last_tcam_idx_cascade = cascade_cnt + k - 1;
796 /* set start_cmp for the first cascaded TCAM */
797 scen_buf.tcam_cfg[k].start_cmp_set |=
798 ICE_AQC_ACL_ALLOC_SCE_START_CMP;
800 /* cascade TCAMs up to the width of the scenario */
801 for (i = k; i < cascade_cnt + k; i++) {
802 ice_acl_fill_tcam_select(&scen_buf, scen, i, i - k);
803 ice_acl_assign_act_mem_for_scen(hw->acl_tbl, scen,
806 last_tcam_idx_cascade);
812 /* We need to set the start_cmp bit for the unused TCAMs. */
814 while (i < first_tcam)
815 scen_buf.tcam_cfg[i++].start_cmp_set =
816 ICE_AQC_ACL_ALLOC_SCE_START_CMP;
819 while (i < ICE_AQC_ACL_SLICES)
820 scen_buf.tcam_cfg[i++].start_cmp_set =
821 ICE_AQC_ACL_ALLOC_SCE_START_CMP;
823 status = ice_aq_alloc_acl_scen(hw, scen_id, &scen_buf, NULL);
825 ice_debug(hw, ICE_DBG_ACL, "AQ allocation of ACL scenario failed. status: %d\n",
831 ice_acl_commit_partition(hw, scen, false);
832 ice_acl_init_entry(scen);
833 LIST_ADD(&scen->list_entry, &hw->acl_tbl->scens);
843 * ice_acl_destroy_scen - Destroy an ACL scenario
844 * @hw: pointer to the HW struct
845 * @scen_id: ID of the remove scenario
847 static enum ice_status ice_acl_destroy_scen(struct ice_hw *hw, u16 scen_id)
849 struct ice_acl_scen *scen, *tmp_scen;
850 struct ice_flow_prof *p, *tmp;
851 enum ice_status status;
854 return ICE_ERR_DOES_NOT_EXIST;
856 /* Remove profiles that use "scen_id" scenario */
857 LIST_FOR_EACH_ENTRY_SAFE(p, tmp, &hw->fl_profs[ICE_BLK_ACL],
858 ice_flow_prof, l_entry)
859 if (p->cfg.scen && p->cfg.scen->id == scen_id) {
860 status = ice_flow_rem_prof(hw, ICE_BLK_ACL, p->id);
862 ice_debug(hw, ICE_DBG_ACL, "ice_flow_rem_prof failed. status: %d\n",
868 /* Call the AQ command to destroy the targeted scenario */
869 status = ice_aq_dealloc_acl_scen(hw, scen_id, NULL);
871 ice_debug(hw, ICE_DBG_ACL, "AQ de-allocation of scenario failed. status: %d\n",
876 /* Remove scenario from hw->acl_tbl->scens */
877 LIST_FOR_EACH_ENTRY_SAFE(scen, tmp_scen, &hw->acl_tbl->scens,
878 ice_acl_scen, list_entry)
879 if (scen->id == scen_id) {
880 LIST_DEL(&scen->list_entry);
888 * ice_acl_destroy_tbl - Destroy a previously created LEM table for ACL
889 * @hw: pointer to the HW struct
891 enum ice_status ice_acl_destroy_tbl(struct ice_hw *hw)
893 struct ice_acl_scen *pos_scen, *tmp_scen;
894 struct ice_aqc_acl_generic resp_buf;
895 struct ice_aqc_acl_scen buf;
896 enum ice_status status;
900 return ICE_ERR_DOES_NOT_EXIST;
902 /* Mark all the created scenario's TCAM to stop the packet lookup and
903 * delete them afterward
905 LIST_FOR_EACH_ENTRY_SAFE(pos_scen, tmp_scen, &hw->acl_tbl->scens,
906 ice_acl_scen, list_entry) {
907 status = ice_aq_query_acl_scen(hw, pos_scen->id, &buf, NULL);
909 ice_debug(hw, ICE_DBG_ACL, "ice_aq_query_acl_scen() failed. status: %d\n",
914 for (i = 0; i < ICE_AQC_ACL_SLICES; i++) {
915 buf.tcam_cfg[i].chnk_msk = 0;
916 buf.tcam_cfg[i].start_cmp_set =
917 ICE_AQC_ACL_ALLOC_SCE_START_CMP;
920 for (i = 0; i < ICE_AQC_MAX_ACTION_MEMORIES; i++)
921 buf.act_mem_cfg[i] = 0;
923 status = ice_aq_update_acl_scen(hw, pos_scen->id, &buf, NULL);
925 ice_debug(hw, ICE_DBG_ACL, "ice_aq_update_acl_scen() failed. status: %d\n",
930 status = ice_acl_destroy_scen(hw, pos_scen->id);
932 ice_debug(hw, ICE_DBG_ACL, "deletion of scenario failed. status: %d\n",
938 /* call the AQ command to destroy the ACL table */
939 status = ice_aq_dealloc_acl_tbl(hw, hw->acl_tbl->id, &resp_buf, NULL);
941 ice_debug(hw, ICE_DBG_ACL, "AQ de-allocation of ACL failed. status: %d\n",
946 ice_free(hw, hw->acl_tbl);
953 * ice_acl_add_entry - Add a flow entry to an ACL scenario
954 * @hw: pointer to the HW struct
955 * @scen: scenario to add the entry to
956 * @prior: priority level of the entry being added
957 * @keys: buffer of the value of the key to be programmed to the ACL entry
958 * @inverts: buffer of the value of the key inverts to be programmed
959 * @acts: pointer to a buffer containing formatted actions
960 * @acts_cnt: indicates the number of actions stored in "acts"
961 * @entry_idx: returned scenario relative index of the added flow entry
963 * Given an ACL table and a scenario, to add the specified key and key invert
964 * to an available entry in the specified scenario.
965 * The "keys" and "inverts" buffers must be of the size which is the same as
966 * the scenario's width
969 ice_acl_add_entry(struct ice_hw *hw, struct ice_acl_scen *scen,
970 enum ice_acl_entry_prior prior, u8 *keys, u8 *inverts,
971 struct ice_acl_act_entry *acts, u8 acts_cnt, u16 *entry_idx)
973 u8 i, entry_tcam, num_cscd, offset;
974 struct ice_aqc_acl_data buf;
975 enum ice_status status = ICE_SUCCESS;
979 return ICE_ERR_DOES_NOT_EXIST;
981 *entry_idx = ice_acl_scen_assign_entry_idx(scen, prior);
982 if (*entry_idx >= scen->num_entry) {
984 return ICE_ERR_MAX_LIMIT;
987 /* Determine number of cascaded TCAMs */
988 num_cscd = DIVIDE_AND_ROUND_UP(scen->width,
989 ICE_AQC_ACL_KEY_WIDTH_BYTES);
991 entry_tcam = ICE_ACL_TBL_TCAM_IDX(scen->start);
992 idx = ICE_ACL_TBL_TCAM_ENTRY_IDX(scen->start + *entry_idx);
994 ice_memset(&buf, 0, sizeof(buf), ICE_NONDMA_MEM);
995 for (i = 0; i < num_cscd; i++) {
996 /* If the key spans more than one TCAM in the case of cascaded
997 * TCAMs, the key and key inverts need to be properly split
998 * among TCAMs.E.g.bytes 0 - 4 go to an index in the first TCAM
999 * and bytes 5 - 9 go to the same index in the next TCAM, etc.
1000 * If the entry spans more than one TCAM in a cascaded TCAM
1001 * mode, the programming of the entries in the TCAMs must be in
1002 * reversed order - the TCAM entry of the rightmost TCAM should
1003 * be programmed first; the TCAM entry of the leftmost TCAM
1004 * should be programmed last.
1006 offset = num_cscd - i - 1;
1007 ice_memcpy(&buf.entry_key.val,
1008 &keys[offset * sizeof(buf.entry_key.val)],
1009 sizeof(buf.entry_key.val), ICE_NONDMA_TO_NONDMA);
1010 ice_memcpy(&buf.entry_key_invert.val,
1011 &inverts[offset * sizeof(buf.entry_key_invert.val)],
1012 sizeof(buf.entry_key_invert.val),
1013 ICE_NONDMA_TO_NONDMA);
1014 status = ice_aq_program_acl_entry(hw, entry_tcam + offset, idx,
1017 ice_debug(hw, ICE_DBG_ACL, "aq program acl entry failed status: %d\n",
1023 /* Program the action memory */
1024 status = ice_acl_prog_act(hw, scen, acts, acts_cnt, *entry_idx);
1028 ice_acl_rem_entry(hw, scen, *entry_idx);
1036 * ice_acl_prog_act - Program a scenario's action memory
1037 * @hw: pointer to the HW struct
1038 * @scen: scenario to add the entry to
1039 * @acts: pointer to a buffer containing formatted actions
1040 * @acts_cnt: indicates the number of actions stored in "acts"
1041 * @entry_idx: scenario relative index of the added flow entry
1043 * Program a scenario's action memory
1046 ice_acl_prog_act(struct ice_hw *hw, struct ice_acl_scen *scen,
1047 struct ice_acl_act_entry *acts, u8 acts_cnt,
1050 u8 entry_tcam, num_cscd, i, actx_idx = 0;
1051 struct ice_aqc_actpair act_buf;
1052 enum ice_status status = ICE_SUCCESS;
1055 if (entry_idx >= scen->num_entry)
1056 return ICE_ERR_MAX_LIMIT;
1058 ice_memset(&act_buf, 0, sizeof(act_buf), ICE_NONDMA_MEM);
1060 /* Determine number of cascaded TCAMs */
1061 num_cscd = DIVIDE_AND_ROUND_UP(scen->width,
1062 ICE_AQC_ACL_KEY_WIDTH_BYTES);
1064 entry_tcam = ICE_ACL_TBL_TCAM_IDX(scen->start);
1065 idx = ICE_ACL_TBL_TCAM_ENTRY_IDX(scen->start + entry_idx);
1067 ice_for_each_set_bit(i, scen->act_mem_bitmap,
1068 ICE_AQC_MAX_ACTION_MEMORIES) {
1069 struct ice_acl_act_mem *mem = &hw->acl_tbl->act_mems[i];
1071 if (actx_idx >= acts_cnt)
1073 if (mem->member_of_tcam >= entry_tcam &&
1074 mem->member_of_tcam < entry_tcam + num_cscd) {
1075 ice_memcpy(&act_buf.act[0], &acts[actx_idx],
1076 sizeof(struct ice_acl_act_entry),
1077 ICE_NONDMA_TO_NONDMA);
1079 if (++actx_idx < acts_cnt) {
1080 ice_memcpy(&act_buf.act[1], &acts[actx_idx],
1081 sizeof(struct ice_acl_act_entry),
1082 ICE_NONDMA_TO_NONDMA);
1085 status = ice_aq_program_actpair(hw, i, idx, &act_buf,
1088 ice_debug(hw, ICE_DBG_ACL, "program actpair failed status: %d\n",
1096 if (!status && actx_idx < acts_cnt)
1097 status = ICE_ERR_MAX_LIMIT;
1103 * ice_acl_rem_entry - Remove a flow entry from an ACL scenario
1104 * @hw: pointer to the HW struct
1105 * @scen: scenario to remove the entry from
1106 * @entry_idx: the scenario-relative index of the flow entry being removed
1109 ice_acl_rem_entry(struct ice_hw *hw, struct ice_acl_scen *scen, u16 entry_idx)
1111 struct ice_aqc_actpair act_buf;
1112 struct ice_aqc_acl_data buf;
1113 u8 entry_tcam, num_cscd, i;
1114 enum ice_status status = ICE_SUCCESS;
1118 return ICE_ERR_DOES_NOT_EXIST;
1120 if (entry_idx >= scen->num_entry)
1121 return ICE_ERR_MAX_LIMIT;
1123 if (!ice_is_bit_set(scen->entry_bitmap, entry_idx))
1124 return ICE_ERR_DOES_NOT_EXIST;
1126 /* Determine number of cascaded TCAMs */
1127 num_cscd = DIVIDE_AND_ROUND_UP(scen->width,
1128 ICE_AQC_ACL_KEY_WIDTH_BYTES);
1130 entry_tcam = ICE_ACL_TBL_TCAM_IDX(scen->start);
1131 idx = ICE_ACL_TBL_TCAM_ENTRY_IDX(scen->start + entry_idx);
1133 /* invalidate the flow entry */
1134 ice_memset(&buf, 0, sizeof(buf), ICE_NONDMA_MEM);
1135 for (i = 0; i < num_cscd; i++) {
1136 status = ice_aq_program_acl_entry(hw, entry_tcam + i, idx, &buf,
1139 ice_debug(hw, ICE_DBG_ACL, "AQ program ACL entry failed status: %d\n",
1143 ice_memset(&act_buf, 0, sizeof(act_buf), ICE_NONDMA_MEM);
1145 ice_for_each_set_bit(i, scen->act_mem_bitmap,
1146 ICE_AQC_MAX_ACTION_MEMORIES) {
1147 struct ice_acl_act_mem *mem = &hw->acl_tbl->act_mems[i];
1149 if (mem->member_of_tcam >= entry_tcam &&
1150 mem->member_of_tcam < entry_tcam + num_cscd) {
1151 /* Invalidate allocated action pairs */
1152 status = ice_aq_program_actpair(hw, i, idx, &act_buf,
1155 ice_debug(hw, ICE_DBG_ACL, "program actpair failed status: %d\n",
1160 ice_acl_scen_free_entry_idx(scen, entry_idx);