1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2001-2019
5 #ifndef _ICE_ADMINQ_CMD_H_
6 #define _ICE_ADMINQ_CMD_H_
8 /* This header file defines the Admin Queue commands, error codes and
9 * descriptor format. It is shared between Firmware and Software.
13 #define ICE_MAX_VSI 768
14 #define ICE_AQC_TOPO_MAX_LEVEL_NUM 0x9
15 #define ICE_AQ_SET_MAC_FRAME_SIZE_MAX 9728
18 struct ice_aqc_generic {
26 /* Get version (direct 0x0001) */
27 struct ice_aqc_get_ver {
42 /* Queue Shutdown (direct 0x0003) */
43 struct ice_aqc_q_shutdown {
44 __le32 driver_unloading;
45 #define ICE_AQC_DRIVER_UNLOADING BIT(0)
52 /* Request resource ownership (direct 0x0008)
53 * Release resource ownership (direct 0x0009)
55 struct ice_aqc_req_res {
57 #define ICE_AQC_RES_ID_NVM 1
58 #define ICE_AQC_RES_ID_SDP 2
59 #define ICE_AQC_RES_ID_CHNG_LOCK 3
60 #define ICE_AQC_RES_ID_GLBL_LOCK 4
62 #define ICE_AQC_RES_ACCESS_READ 1
63 #define ICE_AQC_RES_ACCESS_WRITE 2
65 /* Upon successful completion, FW writes this value and driver is
66 * expected to release resource before timeout. This value is provided
70 #define ICE_AQ_RES_NVM_READ_DFLT_TIMEOUT_MS 3000
71 #define ICE_AQ_RES_NVM_WRITE_DFLT_TIMEOUT_MS 180000
72 #define ICE_AQ_RES_CHNG_LOCK_DFLT_TIMEOUT_MS 1000
73 #define ICE_AQ_RES_GLBL_LOCK_DFLT_TIMEOUT_MS 3000
74 /* For SDP: pin ID of the SDP */
76 /* Status is only used for ICE_AQC_RES_ID_GLBL_LOCK */
78 #define ICE_AQ_RES_GLBL_SUCCESS 0
79 #define ICE_AQ_RES_GLBL_IN_PROG 1
80 #define ICE_AQ_RES_GLBL_DONE 2
85 /* Get function capabilities (indirect 0x000A)
86 * Get device capabilities (indirect 0x000B)
88 struct ice_aqc_list_caps {
98 /* Device/Function buffer entry, repeated per reported capability */
99 struct ice_aqc_list_caps_elem {
101 #define ICE_AQC_CAPS_VALID_FUNCTIONS 0x0005
102 #define ICE_AQC_CAPS_VSI 0x0017
103 #define ICE_AQC_CAPS_DCB 0x0018
104 #define ICE_AQC_CAPS_RSS 0x0040
105 #define ICE_AQC_CAPS_RXQS 0x0041
106 #define ICE_AQC_CAPS_TXQS 0x0042
107 #define ICE_AQC_CAPS_MSIX 0x0043
108 #define ICE_AQC_CAPS_MAX_MTU 0x0047
112 /* Number of resources described by this capability */
114 /* Only meaningful for some types of resources */
116 /* Only meaningful for some types of resources */
123 /* Manage MAC address, read command - indirect (0x0107)
124 * This struct is also used for the response
126 struct ice_aqc_manage_mac_read {
127 __le16 flags; /* Zeroed by device driver */
128 #define ICE_AQC_MAN_MAC_LAN_ADDR_VALID BIT(4)
129 #define ICE_AQC_MAN_MAC_SAN_ADDR_VALID BIT(5)
130 #define ICE_AQC_MAN_MAC_PORT_ADDR_VALID BIT(6)
131 #define ICE_AQC_MAN_MAC_WOL_ADDR_VALID BIT(7)
132 #define ICE_AQC_MAN_MAC_READ_S 4
133 #define ICE_AQC_MAN_MAC_READ_M (0xF << ICE_AQC_MAN_MAC_READ_S)
136 #define ICE_AQC_MAN_MAC_PORT_NUM_IS_VALID BIT(0)
137 u8 num_addr; /* Used in response */
144 /* Response buffer format for manage MAC read command */
145 struct ice_aqc_manage_mac_read_resp {
148 #define ICE_AQC_MAN_MAC_ADDR_TYPE_LAN 0
149 #define ICE_AQC_MAN_MAC_ADDR_TYPE_WOL 1
150 u8 mac_addr[ETH_ALEN];
154 /* Manage MAC address, write command - direct (0x0108) */
155 struct ice_aqc_manage_mac_write {
158 #define ICE_AQC_MAN_MAC_WR_MC_MAG_EN BIT(0)
159 #define ICE_AQC_MAN_MAC_WR_WOL_LAA_PFR_KEEP BIT(1)
160 #define ICE_AQC_MAN_MAC_WR_S 6
161 #define ICE_AQC_MAN_MAC_WR_M (3 << ICE_AQC_MAN_MAC_WR_S)
162 #define ICE_AQC_MAN_MAC_UPDATE_LAA 0
163 #define ICE_AQC_MAN_MAC_UPDATE_LAA_WOL (BIT(0) << ICE_AQC_MAN_MAC_WR_S)
164 /* High 16 bits of MAC address in big endian order */
166 /* Low 32 bits of MAC address in big endian order */
173 /* Clear PXE Command and response (direct 0x0110) */
174 struct ice_aqc_clear_pxe {
176 #define ICE_AQC_CLEAR_PXE_RX_CNT 0x2
181 /* Configure No-Drop Policy Command (direct 0x0112) */
182 struct ice_aqc_config_no_drop_policy {
184 #define ICE_AQC_FORCE_NO_DROP BIT(0)
188 /* Get switch configuration (0x0200) */
189 struct ice_aqc_get_sw_cfg {
190 /* Reserved for command and copy of request flags for response */
192 /* First desc in case of command and next_elem in case of response
193 * In case of response, if it is not zero, means all the configuration
194 * was not returned and new command shall be sent with this value in
195 * the 'first desc' field
198 /* Reserved for command, only used for response */
206 /* Each entry in the response buffer is of the following type: */
207 struct ice_aqc_get_sw_cfg_resp_elem {
208 /* VSI/Port Number */
210 #define ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_S 0
211 #define ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_M \
212 (0x3FF << ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_S)
213 #define ICE_AQC_GET_SW_CONF_RESP_TYPE_S 14
214 #define ICE_AQC_GET_SW_CONF_RESP_TYPE_M (0x3 << ICE_AQC_GET_SW_CONF_RESP_TYPE_S)
215 #define ICE_AQC_GET_SW_CONF_RESP_PHYS_PORT 0
216 #define ICE_AQC_GET_SW_CONF_RESP_VIRT_PORT 1
217 #define ICE_AQC_GET_SW_CONF_RESP_VSI 2
219 /* SWID VSI/Port belongs to */
222 /* Bit 14..0 : PF/VF number VSI belongs to
223 * Bit 15 : VF indication bit
226 #define ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_S 0
227 #define ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_M \
228 (0x7FFF << ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_S)
229 #define ICE_AQC_GET_SW_CONF_RESP_IS_VF BIT(15)
233 /* The response buffer is as follows. Note that the length of the
234 * elements array varies with the length of the command response.
236 struct ice_aqc_get_sw_cfg_resp {
237 struct ice_aqc_get_sw_cfg_resp_elem elements[1];
242 /* These resource type defines are used for all switch resource
243 * commands where a resource type is required, such as:
244 * Get Resource Allocation command (indirect 0x0204)
245 * Allocate Resources command (indirect 0x0208)
246 * Free Resources command (indirect 0x0209)
247 * Get Allocated Resource Descriptors Command (indirect 0x020A)
249 #define ICE_AQC_RES_TYPE_VEB_COUNTER 0x00
250 #define ICE_AQC_RES_TYPE_VLAN_COUNTER 0x01
251 #define ICE_AQC_RES_TYPE_MIRROR_RULE 0x02
252 #define ICE_AQC_RES_TYPE_VSI_LIST_REP 0x03
253 #define ICE_AQC_RES_TYPE_VSI_LIST_PRUNE 0x04
254 #define ICE_AQC_RES_TYPE_RECIPE 0x05
255 #define ICE_AQC_RES_TYPE_PROFILE 0x06
256 #define ICE_AQC_RES_TYPE_SWID 0x07
257 #define ICE_AQC_RES_TYPE_VSI 0x08
258 #define ICE_AQC_RES_TYPE_FLU 0x09
259 #define ICE_AQC_RES_TYPE_WIDE_TABLE_1 0x0A
260 #define ICE_AQC_RES_TYPE_WIDE_TABLE_2 0x0B
261 #define ICE_AQC_RES_TYPE_WIDE_TABLE_4 0x0C
262 #define ICE_AQC_RES_TYPE_GLOBAL_RSS_HASH 0x20
263 #define ICE_AQC_RES_TYPE_FDIR_COUNTER_BLOCK 0x21
264 #define ICE_AQC_RES_TYPE_FDIR_GUARANTEED_ENTRIES 0x22
265 #define ICE_AQC_RES_TYPE_FDIR_SHARED_ENTRIES 0x23
266 #define ICE_AQC_RES_TYPE_FLEX_DESC_PROG 0x30
267 #define ICE_AQC_RES_TYPE_SWITCH_PROF_BLDR_PROFID 0x48
268 #define ICE_AQC_RES_TYPE_SWITCH_PROF_BLDR_TCAM 0x49
269 #define ICE_AQC_RES_TYPE_ACL_PROF_BLDR_PROFID 0x50
270 #define ICE_AQC_RES_TYPE_ACL_PROF_BLDR_TCAM 0x51
271 #define ICE_AQC_RES_TYPE_FD_PROF_BLDR_PROFID 0x58
272 #define ICE_AQC_RES_TYPE_FD_PROF_BLDR_TCAM 0x59
273 #define ICE_AQC_RES_TYPE_HASH_PROF_BLDR_PROFID 0x60
274 #define ICE_AQC_RES_TYPE_HASH_PROF_BLDR_TCAM 0x61
275 /* Resource types 0x62-67 are reserved for Hash profile builder */
276 #define ICE_AQC_RES_TYPE_QHASH_PROF_BLDR_PROFID 0x68
277 #define ICE_AQC_RES_TYPE_QHASH_PROF_BLDR_TCAM 0x69
279 #define ICE_AQC_RES_TYPE_FLAG_SHARED BIT(7)
280 #define ICE_AQC_RES_TYPE_FLAG_SCAN_BOTTOM BIT(12)
281 #define ICE_AQC_RES_TYPE_FLAG_IGNORE_INDEX BIT(13)
283 #define ICE_AQC_RES_TYPE_FLAG_DEDICATED 0x00
285 #define ICE_AQC_RES_TYPE_S 0
286 #define ICE_AQC_RES_TYPE_M (0x07F << ICE_AQC_RES_TYPE_S)
288 /* Get Resource Allocation command (indirect 0x0204) */
289 struct ice_aqc_get_res_alloc {
290 __le16 resp_elem_num; /* Used in response, reserved in command */
296 /* Get Resource Allocation Response Buffer per response */
297 struct ice_aqc_get_res_resp_elem {
298 __le16 res_type; /* Types defined above cmd 0x0204 */
299 __le16 total_capacity; /* Resources available to all PF's */
300 __le16 total_function; /* Resources allocated for a PF */
301 __le16 total_shared; /* Resources allocated as shared */
302 __le16 total_free; /* Resources un-allocated/not reserved by any PF */
305 /* Buffer for Get Resource command */
306 struct ice_aqc_get_res_resp {
307 /* Number of resource entries to be calculated using
308 * datalen/sizeof(struct ice_aqc_cmd_resp)).
309 * Value of 'datalen' gets updated as part of response.
311 struct ice_aqc_get_res_resp_elem elem[1];
315 /* Allocate Resources command (indirect 0x0208)
316 * Free Resources command (indirect 0x0209)
318 struct ice_aqc_alloc_free_res_cmd {
319 __le16 num_entries; /* Number of Resource entries */
326 /* Resource descriptor */
327 struct ice_aqc_res_elem {
335 /* Buffer for Allocate/Free Resources commands */
336 struct ice_aqc_alloc_free_res_elem {
337 __le16 res_type; /* Types defined above cmd 0x0204 */
338 #define ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_S 8
339 #define ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_M \
340 (0xF << ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_S)
342 struct ice_aqc_res_elem elem[1];
346 /* Get Allocated Resource Descriptors Command (indirect 0x020A) */
347 struct ice_aqc_get_allocd_res_desc {
350 __le16 res; /* Types defined above cmd 0x0204 */
365 struct ice_aqc_get_allocd_res_desc_resp {
366 struct ice_aqc_res_elem elem[1];
370 /* Add VSI (indirect 0x0210)
371 * Update VSI (indirect 0x0211)
372 * Get VSI (indirect 0x0212)
373 * Free VSI (indirect 0x0213)
375 struct ice_aqc_add_get_update_free_vsi {
377 #define ICE_AQ_VSI_NUM_S 0
378 #define ICE_AQ_VSI_NUM_M (0x03FF << ICE_AQ_VSI_NUM_S)
379 #define ICE_AQ_VSI_IS_VALID BIT(15)
381 #define ICE_AQ_VSI_KEEP_ALLOC 0x1
385 #define ICE_AQ_VSI_TYPE_S 0
386 #define ICE_AQ_VSI_TYPE_M (0x3 << ICE_AQ_VSI_TYPE_S)
387 #define ICE_AQ_VSI_TYPE_VF 0x0
388 #define ICE_AQ_VSI_TYPE_VMDQ2 0x1
389 #define ICE_AQ_VSI_TYPE_PF 0x2
390 #define ICE_AQ_VSI_TYPE_EMP_MNG 0x3
396 /* Response descriptor for:
397 * Add VSI (indirect 0x0210)
398 * Update VSI (indirect 0x0211)
399 * Free VSI (indirect 0x0213)
401 struct ice_aqc_add_update_free_vsi_resp {
411 struct ice_aqc_get_vsi_resp {
414 /* The vsi_flags field uses the ICE_AQ_VSI_TYPE_* defines for values.
415 * These are found above in struct ice_aqc_add_get_update_free_vsi.
425 struct ice_aqc_vsi_props {
426 __le16 valid_sections;
427 #define ICE_AQ_VSI_PROP_SW_VALID BIT(0)
428 #define ICE_AQ_VSI_PROP_SECURITY_VALID BIT(1)
429 #define ICE_AQ_VSI_PROP_VLAN_VALID BIT(2)
430 #define ICE_AQ_VSI_PROP_OUTER_TAG_VALID BIT(3)
431 #define ICE_AQ_VSI_PROP_INGRESS_UP_VALID BIT(4)
432 #define ICE_AQ_VSI_PROP_EGRESS_UP_VALID BIT(5)
433 #define ICE_AQ_VSI_PROP_RXQ_MAP_VALID BIT(6)
434 #define ICE_AQ_VSI_PROP_Q_OPT_VALID BIT(7)
435 #define ICE_AQ_VSI_PROP_OUTER_UP_VALID BIT(8)
436 #define ICE_AQ_VSI_PROP_FLOW_DIR_VALID BIT(11)
437 #define ICE_AQ_VSI_PROP_PASID_VALID BIT(12)
441 #define ICE_AQ_VSI_SW_FLAG_ALLOW_LB BIT(5)
442 #define ICE_AQ_VSI_SW_FLAG_LOCAL_LB BIT(6)
443 #define ICE_AQ_VSI_SW_FLAG_SRC_PRUNE BIT(7)
445 #define ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_S 0
446 #define ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_M \
447 (0xF << ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_S)
448 #define ICE_AQ_VSI_SW_FLAG_RX_VLAN_PRUNE_ENA BIT(0)
449 #define ICE_AQ_VSI_SW_FLAG_LAN_ENA BIT(4)
451 #define ICE_AQ_VSI_SW_VEB_STAT_ID_S 0
452 #define ICE_AQ_VSI_SW_VEB_STAT_ID_M (0x1F << ICE_AQ_VSI_SW_VEB_STAT_ID_S)
453 #define ICE_AQ_VSI_SW_VEB_STAT_ID_VALID BIT(5)
454 /* security section */
456 #define ICE_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD BIT(0)
457 #define ICE_AQ_VSI_SEC_FLAG_ENA_MAC_ANTI_SPOOF BIT(2)
458 #define ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S 4
459 #define ICE_AQ_VSI_SEC_TX_PRUNE_ENA_M (0xF << ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S)
460 #define ICE_AQ_VSI_SEC_TX_VLAN_PRUNE_ENA BIT(0)
463 __le16 pvid; /* VLANS include priority bits */
464 u8 pvlan_reserved[2];
466 #define ICE_AQ_VSI_VLAN_MODE_S 0
467 #define ICE_AQ_VSI_VLAN_MODE_M (0x3 << ICE_AQ_VSI_VLAN_MODE_S)
468 #define ICE_AQ_VSI_VLAN_MODE_UNTAGGED 0x1
469 #define ICE_AQ_VSI_VLAN_MODE_TAGGED 0x2
470 #define ICE_AQ_VSI_VLAN_MODE_ALL 0x3
471 #define ICE_AQ_VSI_PVLAN_INSERT_PVID BIT(2)
472 #define ICE_AQ_VSI_VLAN_EMOD_S 3
473 #define ICE_AQ_VSI_VLAN_EMOD_M (0x3 << ICE_AQ_VSI_VLAN_EMOD_S)
474 #define ICE_AQ_VSI_VLAN_EMOD_STR_BOTH (0x0 << ICE_AQ_VSI_VLAN_EMOD_S)
475 #define ICE_AQ_VSI_VLAN_EMOD_STR_UP (0x1 << ICE_AQ_VSI_VLAN_EMOD_S)
476 #define ICE_AQ_VSI_VLAN_EMOD_STR (0x2 << ICE_AQ_VSI_VLAN_EMOD_S)
477 #define ICE_AQ_VSI_VLAN_EMOD_NOTHING (0x3 << ICE_AQ_VSI_VLAN_EMOD_S)
478 u8 pvlan_reserved2[3];
479 /* ingress egress up sections */
480 __le32 ingress_table; /* bitmap, 3 bits per up */
481 #define ICE_AQ_VSI_UP_TABLE_UP0_S 0
482 #define ICE_AQ_VSI_UP_TABLE_UP0_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP0_S)
483 #define ICE_AQ_VSI_UP_TABLE_UP1_S 3
484 #define ICE_AQ_VSI_UP_TABLE_UP1_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP1_S)
485 #define ICE_AQ_VSI_UP_TABLE_UP2_S 6
486 #define ICE_AQ_VSI_UP_TABLE_UP2_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP2_S)
487 #define ICE_AQ_VSI_UP_TABLE_UP3_S 9
488 #define ICE_AQ_VSI_UP_TABLE_UP3_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP3_S)
489 #define ICE_AQ_VSI_UP_TABLE_UP4_S 12
490 #define ICE_AQ_VSI_UP_TABLE_UP4_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP4_S)
491 #define ICE_AQ_VSI_UP_TABLE_UP5_S 15
492 #define ICE_AQ_VSI_UP_TABLE_UP5_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP5_S)
493 #define ICE_AQ_VSI_UP_TABLE_UP6_S 18
494 #define ICE_AQ_VSI_UP_TABLE_UP6_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP6_S)
495 #define ICE_AQ_VSI_UP_TABLE_UP7_S 21
496 #define ICE_AQ_VSI_UP_TABLE_UP7_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP7_S)
497 __le32 egress_table; /* same defines as for ingress table */
498 /* outer tags section */
501 #define ICE_AQ_VSI_OUTER_TAG_MODE_S 0
502 #define ICE_AQ_VSI_OUTER_TAG_MODE_M (0x3 << ICE_AQ_VSI_OUTER_TAG_MODE_S)
503 #define ICE_AQ_VSI_OUTER_TAG_NOTHING 0x0
504 #define ICE_AQ_VSI_OUTER_TAG_REMOVE 0x1
505 #define ICE_AQ_VSI_OUTER_TAG_COPY 0x2
506 #define ICE_AQ_VSI_OUTER_TAG_TYPE_S 2
507 #define ICE_AQ_VSI_OUTER_TAG_TYPE_M (0x3 << ICE_AQ_VSI_OUTER_TAG_TYPE_S)
508 #define ICE_AQ_VSI_OUTER_TAG_NONE 0x0
509 #define ICE_AQ_VSI_OUTER_TAG_STAG 0x1
510 #define ICE_AQ_VSI_OUTER_TAG_VLAN_8100 0x2
511 #define ICE_AQ_VSI_OUTER_TAG_VLAN_9100 0x3
512 #define ICE_AQ_VSI_OUTER_TAG_INSERT BIT(4)
513 #define ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST BIT(6)
514 u8 outer_tag_reserved;
515 /* queue mapping section */
516 __le16 mapping_flags;
517 #define ICE_AQ_VSI_Q_MAP_CONTIG 0x0
518 #define ICE_AQ_VSI_Q_MAP_NONCONTIG BIT(0)
519 __le16 q_mapping[16];
520 #define ICE_AQ_VSI_Q_S 0
521 #define ICE_AQ_VSI_Q_M (0x7FF << ICE_AQ_VSI_Q_S)
522 __le16 tc_mapping[8];
523 #define ICE_AQ_VSI_TC_Q_OFFSET_S 0
524 #define ICE_AQ_VSI_TC_Q_OFFSET_M (0x7FF << ICE_AQ_VSI_TC_Q_OFFSET_S)
525 #define ICE_AQ_VSI_TC_Q_NUM_S 11
526 #define ICE_AQ_VSI_TC_Q_NUM_M (0xF << ICE_AQ_VSI_TC_Q_NUM_S)
527 /* queueing option section */
529 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_S 0
530 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_M (0x3 << ICE_AQ_VSI_Q_OPT_RSS_LUT_S)
531 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_VSI 0x0
532 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_PF 0x2
533 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_GBL 0x3
534 #define ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_S 2
535 #define ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_M (0xF << ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_S)
536 #define ICE_AQ_VSI_Q_OPT_RSS_HASH_S 6
537 #define ICE_AQ_VSI_Q_OPT_RSS_HASH_M (0x3 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S)
538 #define ICE_AQ_VSI_Q_OPT_RSS_TPLZ (0x0 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S)
539 #define ICE_AQ_VSI_Q_OPT_RSS_SYM_TPLZ (0x1 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S)
540 #define ICE_AQ_VSI_Q_OPT_RSS_XOR (0x2 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S)
541 #define ICE_AQ_VSI_Q_OPT_RSS_JHASH (0x3 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S)
543 #define ICE_AQ_VSI_Q_OPT_TC_OVR_S 0
544 #define ICE_AQ_VSI_Q_OPT_TC_OVR_M (0x1F << ICE_AQ_VSI_Q_OPT_TC_OVR_S)
545 #define ICE_AQ_VSI_Q_OPT_PROF_TC_OVR BIT(7)
547 #define ICE_AQ_VSI_Q_OPT_PE_FLTR_EN BIT(0)
548 u8 q_opt_reserved[3];
549 /* outer up section */
550 __le32 outer_up_table; /* same structure and defines as ingress tbl */
552 __le16 sect_10_reserved;
553 /* flow director section */
555 #define ICE_AQ_VSI_FD_ENABLE BIT(0)
556 #define ICE_AQ_VSI_FD_TX_AUTO_ENABLE BIT(1)
557 #define ICE_AQ_VSI_FD_PROG_ENABLE BIT(3)
558 __le16 max_fd_fltr_dedicated;
559 __le16 max_fd_fltr_shared;
561 #define ICE_AQ_VSI_FD_DEF_Q_S 0
562 #define ICE_AQ_VSI_FD_DEF_Q_M (0x7FF << ICE_AQ_VSI_FD_DEF_Q_S)
563 #define ICE_AQ_VSI_FD_DEF_GRP_S 12
564 #define ICE_AQ_VSI_FD_DEF_GRP_M (0x7 << ICE_AQ_VSI_FD_DEF_GRP_S)
565 __le16 fd_report_opt;
566 #define ICE_AQ_VSI_FD_REPORT_Q_S 0
567 #define ICE_AQ_VSI_FD_REPORT_Q_M (0x7FF << ICE_AQ_VSI_FD_REPORT_Q_S)
568 #define ICE_AQ_VSI_FD_DEF_PRIORITY_S 12
569 #define ICE_AQ_VSI_FD_DEF_PRIORITY_M (0x7 << ICE_AQ_VSI_FD_DEF_PRIORITY_S)
570 #define ICE_AQ_VSI_FD_DEF_DROP BIT(15)
573 #define ICE_AQ_VSI_PASID_ID_S 0
574 #define ICE_AQ_VSI_PASID_ID_M (0xFFFFF << ICE_AQ_VSI_PASID_ID_S)
575 #define ICE_AQ_VSI_PASID_ID_VALID BIT(31)
580 /* Add/update mirror rule - direct (0x0260) */
581 #define ICE_AQC_RULE_ID_VALID_S 7
582 #define ICE_AQC_RULE_ID_VALID_M (0x1 << ICE_AQC_RULE_ID_VALID_S)
583 #define ICE_AQC_RULE_ID_S 0
584 #define ICE_AQC_RULE_ID_M (0x3F << ICE_AQC_RULE_ID_S)
586 /* Following defines to be used while processing caller specified mirror list
589 /* Action: Byte.bit (1.7)
590 * 0 = Remove VSI from mirror rule
591 * 1 = Add VSI to mirror rule
593 #define ICE_AQC_RULE_ACT_S 15
594 #define ICE_AQC_RULE_ACT_M (0x1 << ICE_AQC_RULE_ACT_S)
595 /* Action: 1.2:0.0 = Mirrored VSI */
596 #define ICE_AQC_RULE_MIRRORED_VSI_S 0
597 #define ICE_AQC_RULE_MIRRORED_VSI_M (0x7FF << ICE_AQC_RULE_MIRRORED_VSI_S)
599 /* This is to be used by add/update mirror rule Admin Queue command.
600 * In case of add mirror rule - if rule ID is specified as
601 * INVAL_MIRROR_RULE_ID, new rule ID is allocated from shared pool.
602 * If specified rule_id is valid, then it is used. If specified rule_id
603 * is in use then new mirroring rule is added.
605 #define ICE_INVAL_MIRROR_RULE_ID 0xFFFF
607 struct ice_aqc_add_update_mir_rule {
611 #define ICE_AQC_RULE_TYPE_S 0
612 #define ICE_AQC_RULE_TYPE_M (0x7 << ICE_AQC_RULE_TYPE_S)
613 /* VPORT ingress/egress */
614 #define ICE_AQC_RULE_TYPE_VPORT_INGRESS 0x1
615 #define ICE_AQC_RULE_TYPE_VPORT_EGRESS 0x2
616 /* Physical port ingress mirroring.
617 * All traffic received by this port
619 #define ICE_AQC_RULE_TYPE_PPORT_INGRESS 0x6
620 /* Physical port egress mirroring. All traffic sent by this port */
621 #define ICE_AQC_RULE_TYPE_PPORT_EGRESS 0x7
623 /* Number of mirrored entries.
624 * The values are in the command buffer
628 /* Destination VSI */
634 /* Delete mirror rule - direct(0x0261) */
635 struct ice_aqc_delete_mir_rule {
639 /* Byte.bit: 20.0 = Keep allocation. If set VSI stays part of
640 * the PF allocated resources, otherwise it is returned to the
643 #define ICE_AQC_FLAG_KEEP_ALLOCD_S 0
644 #define ICE_AQC_FLAG_KEEP_ALLOCD_M (0x1 << ICE_AQC_FLAG_KEEP_ALLOCD_S)
650 /* Set/Get storm config - (direct 0x0280, 0x0281) */
651 /* This structure holds get storm configuration response and same structure
652 * is used to perform set_storm_cfg
654 struct ice_aqc_storm_cfg {
655 __le32 bcast_thresh_size;
656 __le32 mcast_thresh_size;
657 /* Bit 18:0 - Traffic upper threshold size
658 * Bit 31:19 - Reserved
660 #define ICE_AQ_THRESHOLD_S 0
661 #define ICE_AQ_THRESHOLD_M (0x7FFFF << ICE_AQ_THRESHOLD_S)
663 __le32 storm_ctrl_ctrl;
664 /* Bit 0: MDIPW - Drop Multicast packets in previous window
665 * Bit 1: MDICW - Drop multicast packets in current window
666 * Bit 2: BDIPW - Drop broadcast packets in previous window
667 * Bit 3: BDICW - Drop broadcast packets in current window
669 #define ICE_AQ_STORM_CTRL_MDIPW_DROP_MULTICAST BIT(0)
670 #define ICE_AQ_STORM_CTRL_MDICW_DROP_MULTICAST BIT(1)
671 #define ICE_AQ_STORM_CTRL_BDIPW_DROP_MULTICAST BIT(2)
672 #define ICE_AQ_STORM_CTRL_BDICW_DROP_MULTICAST BIT(3)
673 /* Bit 7:5 : Reserved */
674 /* Bit 27:8 : Interval - BSC/MSC Time-interval specification: The
675 * interval size for applying ingress broadcast or multicast storm
678 #define ICE_AQ_STORM_BSC_MSC_TIME_INTERVAL_S 8
679 #define ICE_AQ_STORM_BSC_MSC_TIME_INTERVAL_M \
680 (0xFFFFF << ICE_AQ_STORM_BSC_MSC_TIME_INTERVAL_S)
685 #define ICE_MAX_NUM_RECIPES 64
688 /* Add/Update/Remove/Get switch rules (indirect 0x02A0, 0x02A1, 0x02A2, 0x02A3)
690 struct ice_aqc_sw_rules {
691 /* ops: add switch rules, referring the number of rules.
692 * ops: update switch rules, referring the number of filters
693 * ops: remove switch rules, referring the entry index.
694 * ops: get switch rules, referring to the number of filters.
696 __le16 num_rules_fltr_entry_index;
704 /* Add/Update/Get/Remove lookup Rx/Tx command/response entry
705 * This structures describes the lookup rules and associated actions. "index"
706 * is returned as part of a response to a successful Add command, and can be
707 * used to identify the rule for Update/Get/Remove commands.
709 struct ice_sw_rule_lkup_rx_tx {
711 #define ICE_SW_RECIPE_LOGICAL_PORT_FWD 10
712 /* Source port for LOOKUP_RX and source VSI in case of LOOKUP_TX */
716 /* Bit 0:1 - Action type */
717 #define ICE_SINGLE_ACT_TYPE_S 0x00
718 #define ICE_SINGLE_ACT_TYPE_M (0x3 << ICE_SINGLE_ACT_TYPE_S)
720 /* Bit 2 - Loop back enable
723 #define ICE_SINGLE_ACT_LB_ENABLE BIT(2)
724 #define ICE_SINGLE_ACT_LAN_ENABLE BIT(3)
726 /* Action type = 0 - Forward to VSI or VSI list */
727 #define ICE_SINGLE_ACT_VSI_FORWARDING 0x0
729 #define ICE_SINGLE_ACT_VSI_ID_S 4
730 #define ICE_SINGLE_ACT_VSI_ID_M (0x3FF << ICE_SINGLE_ACT_VSI_ID_S)
731 #define ICE_SINGLE_ACT_VSI_LIST_ID_S 4
732 #define ICE_SINGLE_ACT_VSI_LIST_ID_M (0x3FF << ICE_SINGLE_ACT_VSI_LIST_ID_S)
733 /* This bit needs to be set if action is forward to VSI list */
734 #define ICE_SINGLE_ACT_VSI_LIST BIT(14)
735 #define ICE_SINGLE_ACT_VALID_BIT BIT(17)
736 #define ICE_SINGLE_ACT_DROP BIT(18)
738 /* Action type = 1 - Forward to Queue of Queue group */
739 #define ICE_SINGLE_ACT_TO_Q 0x1
740 #define ICE_SINGLE_ACT_Q_INDEX_S 4
741 #define ICE_SINGLE_ACT_Q_INDEX_M (0x7FF << ICE_SINGLE_ACT_Q_INDEX_S)
742 #define ICE_SINGLE_ACT_Q_REGION_S 15
743 #define ICE_SINGLE_ACT_Q_REGION_M (0x7 << ICE_SINGLE_ACT_Q_REGION_S)
744 #define ICE_SINGLE_ACT_Q_PRIORITY BIT(18)
746 /* Action type = 2 - Prune */
747 #define ICE_SINGLE_ACT_PRUNE 0x2
748 #define ICE_SINGLE_ACT_EGRESS BIT(15)
749 #define ICE_SINGLE_ACT_INGRESS BIT(16)
750 #define ICE_SINGLE_ACT_PRUNET BIT(17)
751 /* Bit 18 should be set to 0 for this action */
753 /* Action type = 2 - Pointer */
754 #define ICE_SINGLE_ACT_PTR 0x2
755 #define ICE_SINGLE_ACT_PTR_VAL_S 4
756 #define ICE_SINGLE_ACT_PTR_VAL_M (0x1FFF << ICE_SINGLE_ACT_PTR_VAL_S)
757 /* Bit 18 should be set to 1 */
758 #define ICE_SINGLE_ACT_PTR_BIT BIT(18)
760 /* Action type = 3 - Other actions. Last two bits
761 * are other action identifier
763 #define ICE_SINGLE_ACT_OTHER_ACTS 0x3
764 #define ICE_SINGLE_OTHER_ACT_IDENTIFIER_S 17
765 #define ICE_SINGLE_OTHER_ACT_IDENTIFIER_M \
766 (0x3 << \ ICE_SINGLE_OTHER_ACT_IDENTIFIER_S)
768 /* Bit 17:18 - Defines other actions */
769 /* Other action = 0 - Mirror VSI */
770 #define ICE_SINGLE_OTHER_ACT_MIRROR 0
771 #define ICE_SINGLE_ACT_MIRROR_VSI_ID_S 4
772 #define ICE_SINGLE_ACT_MIRROR_VSI_ID_M \
773 (0x3FF << ICE_SINGLE_ACT_MIRROR_VSI_ID_S)
775 /* Other action = 3 - Set Stat count */
776 #define ICE_SINGLE_OTHER_ACT_STAT_COUNT 3
777 #define ICE_SINGLE_ACT_STAT_COUNT_INDEX_S 4
778 #define ICE_SINGLE_ACT_STAT_COUNT_INDEX_M \
779 (0x7F << ICE_SINGLE_ACT_STAT_COUNT_INDEX_S)
781 __le16 index; /* The index of the rule in the lookup table */
782 /* Length and values of the header to be matched per recipe or
791 /* Add/Update/Remove large action command/response entry
792 * "index" is returned as part of a response to a successful Add command, and
793 * can be used to identify the action for Update/Get/Remove commands.
795 struct ice_sw_rule_lg_act {
796 __le16 index; /* Index in large action table */
798 __le32 act[1]; /* array of size for actions */
799 /* Max number of large actions */
800 #define ICE_MAX_LG_ACT 4
801 /* Bit 0:1 - Action type */
802 #define ICE_LG_ACT_TYPE_S 0
803 #define ICE_LG_ACT_TYPE_M (0x7 << ICE_LG_ACT_TYPE_S)
805 /* Action type = 0 - Forward to VSI or VSI list */
806 #define ICE_LG_ACT_VSI_FORWARDING 0
807 #define ICE_LG_ACT_VSI_ID_S 3
808 #define ICE_LG_ACT_VSI_ID_M (0x3FF << ICE_LG_ACT_VSI_ID_S)
809 #define ICE_LG_ACT_VSI_LIST_ID_S 3
810 #define ICE_LG_ACT_VSI_LIST_ID_M (0x3FF << ICE_LG_ACT_VSI_LIST_ID_S)
811 /* This bit needs to be set if action is forward to VSI list */
812 #define ICE_LG_ACT_VSI_LIST BIT(13)
814 #define ICE_LG_ACT_VALID_BIT BIT(16)
816 /* Action type = 1 - Forward to Queue of Queue group */
817 #define ICE_LG_ACT_TO_Q 0x1
818 #define ICE_LG_ACT_Q_INDEX_S 3
819 #define ICE_LG_ACT_Q_INDEX_M (0x7FF << ICE_LG_ACT_Q_INDEX_S)
820 #define ICE_LG_ACT_Q_REGION_S 14
821 #define ICE_LG_ACT_Q_REGION_M (0x7 << ICE_LG_ACT_Q_REGION_S)
822 #define ICE_LG_ACT_Q_PRIORITY_SET BIT(17)
824 /* Action type = 2 - Prune */
825 #define ICE_LG_ACT_PRUNE 0x2
826 #define ICE_LG_ACT_EGRESS BIT(14)
827 #define ICE_LG_ACT_INGRESS BIT(15)
828 #define ICE_LG_ACT_PRUNET BIT(16)
830 /* Action type = 3 - Mirror VSI */
831 #define ICE_LG_OTHER_ACT_MIRROR 0x3
832 #define ICE_LG_ACT_MIRROR_VSI_ID_S 3
833 #define ICE_LG_ACT_MIRROR_VSI_ID_M (0x3FF << ICE_LG_ACT_MIRROR_VSI_ID_S)
835 /* Action type = 5 - Generic Value */
836 #define ICE_LG_ACT_GENERIC 0x5
837 #define ICE_LG_ACT_GENERIC_VALUE_S 3
838 #define ICE_LG_ACT_GENERIC_VALUE_M (0xFFFF << ICE_LG_ACT_GENERIC_VALUE_S)
839 #define ICE_LG_ACT_GENERIC_OFFSET_S 19
840 #define ICE_LG_ACT_GENERIC_OFFSET_M (0x7 << ICE_LG_ACT_GENERIC_OFFSET_S)
841 #define ICE_LG_ACT_GENERIC_PRIORITY_S 22
842 #define ICE_LG_ACT_GENERIC_PRIORITY_M (0x7 << ICE_LG_ACT_GENERIC_PRIORITY_S)
843 #define ICE_LG_ACT_GENERIC_OFF_RX_DESC_PROF_IDX 7
845 /* Action = 7 - Set Stat count */
846 #define ICE_LG_ACT_STAT_COUNT 0x7
847 #define ICE_LG_ACT_STAT_COUNT_S 3
848 #define ICE_LG_ACT_STAT_COUNT_M (0x7F << ICE_LG_ACT_STAT_COUNT_S)
852 /* Add/Update/Remove VSI list command/response entry
853 * "index" is returned as part of a response to a successful Add command, and
854 * can be used to identify the VSI list for Update/Get/Remove commands.
856 struct ice_sw_rule_vsi_list {
857 __le16 index; /* Index of VSI/Prune list */
859 __le16 vsi[1]; /* Array of number_vsi VSI numbers */
864 /* Query VSI list command/response entry */
865 struct ice_sw_rule_vsi_list_query {
867 ice_declare_bitmap(vsi_list, ICE_MAX_VSI);
873 /* Add switch rule response:
874 * Content of return buffer is same as the input buffer. The status field and
875 * LUT index are updated as part of the response
877 struct ice_aqc_sw_rules_elem {
878 __le16 type; /* Switch rule type, one of T_... */
879 #define ICE_AQC_SW_RULES_T_LKUP_RX 0x0
880 #define ICE_AQC_SW_RULES_T_LKUP_TX 0x1
881 #define ICE_AQC_SW_RULES_T_LG_ACT 0x2
882 #define ICE_AQC_SW_RULES_T_VSI_LIST_SET 0x3
883 #define ICE_AQC_SW_RULES_T_VSI_LIST_CLEAR 0x4
884 #define ICE_AQC_SW_RULES_T_PRUNE_LIST_SET 0x5
885 #define ICE_AQC_SW_RULES_T_PRUNE_LIST_CLEAR 0x6
888 struct ice_sw_rule_lkup_rx_tx lkup_tx_rx;
889 struct ice_sw_rule_lg_act lg_act;
890 struct ice_sw_rule_vsi_list vsi_list;
891 struct ice_sw_rule_vsi_list_query vsi_list_query;
898 /* PFC Ignore (direct 0x0301)
899 * The command and response use the same descriptor structure
901 struct ice_aqc_pfc_ignore {
903 u8 cmd_flags; /* unused in response */
904 #define ICE_AQC_PFC_IGNORE_SET BIT(7)
905 #define ICE_AQC_PFC_IGNORE_CLEAR 0
909 /* Set PFC Mode (direct 0x0303)
910 * Query PFC Mode (direct 0x0302)
912 struct ice_aqc_set_query_pfc_mode {
914 /* For Set Command response, reserved in all other cases */
915 #define ICE_AQC_PFC_NOT_CONFIGURED 0
916 /* For Query Command response, reserved in all other cases */
917 #define ICE_AQC_DCB_DIS 0
918 #define ICE_AQC_PFC_VLAN_BASED_PFC 1
919 #define ICE_AQC_PFC_DSCP_BASED_PFC 2
923 /* Set DCB Parameters (direct 0x0306) */
924 struct ice_aqc_set_dcb_params {
925 u8 cmd_flags; /* unused in response */
926 #define ICE_AQC_LINK_UP_DCB_CFG BIT(0)
927 u8 valid_flags; /* unused in response */
928 #define ICE_AQC_LINK_UP_DCB_CFG_VALID BIT(0)
933 /* Get Default Topology (indirect 0x0400) */
934 struct ice_aqc_get_topo {
944 /* Update TSE (indirect 0x0403)
945 * Get TSE (indirect 0x0404)
946 * Add TSE (indirect 0x0401)
947 * Delete TSE (indirect 0x040F)
948 * Move TSE (indirect 0x0408)
949 * Suspend Nodes (indirect 0x0409)
950 * Resume Nodes (indirect 0x040A)
952 struct ice_aqc_sched_elem_cmd {
953 __le16 num_elem_req; /* Used by commands */
954 __le16 num_elem_resp; /* Used by responses */
961 /* This is the buffer for:
962 * Suspend Nodes (indirect 0x0409)
963 * Resume Nodes (indirect 0x040A)
965 struct ice_aqc_suspend_resume_elem {
970 struct ice_aqc_txsched_move_grp_info_hdr {
971 __le32 src_parent_teid;
972 __le32 dest_parent_teid;
978 struct ice_aqc_move_elem {
979 struct ice_aqc_txsched_move_grp_info_hdr hdr;
984 struct ice_aqc_elem_info_bw {
985 __le16 bw_profile_idx;
990 struct ice_aqc_txsched_elem {
991 u8 elem_type; /* Special field, reserved for some aq calls */
992 #define ICE_AQC_ELEM_TYPE_UNDEFINED 0x0
993 #define ICE_AQC_ELEM_TYPE_ROOT_PORT 0x1
994 #define ICE_AQC_ELEM_TYPE_TC 0x2
995 #define ICE_AQC_ELEM_TYPE_SE_GENERIC 0x3
996 #define ICE_AQC_ELEM_TYPE_ENTRY_POINT 0x4
997 #define ICE_AQC_ELEM_TYPE_LEAF 0x5
998 #define ICE_AQC_ELEM_TYPE_SE_PADDED 0x6
1000 #define ICE_AQC_ELEM_VALID_GENERIC BIT(0)
1001 #define ICE_AQC_ELEM_VALID_CIR BIT(1)
1002 #define ICE_AQC_ELEM_VALID_EIR BIT(2)
1003 #define ICE_AQC_ELEM_VALID_SHARED BIT(3)
1005 #define ICE_AQC_ELEM_GENERIC_MODE_M 0x1
1006 #define ICE_AQC_ELEM_GENERIC_PRIO_S 0x1
1007 #define ICE_AQC_ELEM_GENERIC_PRIO_M (0x7 << ICE_AQC_ELEM_GENERIC_PRIO_S)
1008 #define ICE_AQC_ELEM_GENERIC_SP_S 0x4
1009 #define ICE_AQC_ELEM_GENERIC_SP_M (0x1 << ICE_AQC_ELEM_GENERIC_SP_S)
1010 #define ICE_AQC_ELEM_GENERIC_ADJUST_VAL_S 0x5
1011 #define ICE_AQC_ELEM_GENERIC_ADJUST_VAL_M \
1012 (0x3 << ICE_AQC_ELEM_GENERIC_ADJUST_VAL_S)
1013 u8 flags; /* Special field, reserved for some aq calls */
1014 #define ICE_AQC_ELEM_FLAG_SUSPEND_M 0x1
1015 struct ice_aqc_elem_info_bw cir_bw;
1016 struct ice_aqc_elem_info_bw eir_bw;
1022 struct ice_aqc_txsched_elem_data {
1025 struct ice_aqc_txsched_elem data;
1029 struct ice_aqc_txsched_topo_grp_info_hdr {
1036 struct ice_aqc_add_elem {
1037 struct ice_aqc_txsched_topo_grp_info_hdr hdr;
1038 struct ice_aqc_txsched_elem_data generic[1];
1042 struct ice_aqc_conf_elem {
1043 struct ice_aqc_txsched_elem_data generic[1];
1047 struct ice_aqc_get_elem {
1048 struct ice_aqc_txsched_elem_data generic[1];
1052 struct ice_aqc_get_topo_elem {
1053 struct ice_aqc_txsched_topo_grp_info_hdr hdr;
1054 struct ice_aqc_txsched_elem_data
1055 generic[ICE_AQC_TOPO_MAX_LEVEL_NUM];
1059 struct ice_aqc_delete_elem {
1060 struct ice_aqc_txsched_topo_grp_info_hdr hdr;
1065 /* Query Port ETS (indirect 0x040E)
1067 * This indirect command is used to query port TC node configuration.
1069 struct ice_aqc_query_port_ets {
1076 struct ice_aqc_port_ets_elem {
1079 /* 3 bits for UP per TC 0-7, 4th byte reserved */
1082 __le32 port_eir_prof_id;
1083 __le32 port_cir_prof_id;
1084 /* 3 bits per Node priority to TC 0-7, 4th byte reserved */
1085 __le32 tc_node_prio;
1086 #define ICE_TC_NODE_PRIO_S 0x4
1088 __le32 tc_node_teid[8]; /* Used for response, reserved in command */
1092 /* Rate limiting profile for
1093 * Add RL profile (indirect 0x0410)
1094 * Query RL profile (indirect 0x0411)
1095 * Remove RL profile (indirect 0x0415)
1096 * These indirect commands acts on single or multiple
1097 * RL profiles with specified data.
1099 struct ice_aqc_rl_profile {
1100 __le16 num_profiles;
1101 __le16 num_processed; /* Only for response. Reserved in Command. */
1108 struct ice_aqc_rl_profile_elem {
1111 #define ICE_AQC_RL_PROFILE_TYPE_S 0x0
1112 #define ICE_AQC_RL_PROFILE_TYPE_M (0x3 << ICE_AQC_RL_PROFILE_TYPE_S)
1113 #define ICE_AQC_RL_PROFILE_TYPE_CIR 0
1114 #define ICE_AQC_RL_PROFILE_TYPE_EIR 1
1115 #define ICE_AQC_RL_PROFILE_TYPE_SRL 2
1116 /* The following flag is used for Query RL Profile Data */
1117 #define ICE_AQC_RL_PROFILE_INVAL_S 0x7
1118 #define ICE_AQC_RL_PROFILE_INVAL_M (0x1 << ICE_AQC_RL_PROFILE_INVAL_S)
1121 __le16 max_burst_size;
1123 __le16 wake_up_calc;
1128 struct ice_aqc_rl_profile_generic_elem {
1129 struct ice_aqc_rl_profile_elem generic[1];
1134 /* Configure L2 Node CGD (indirect 0x0414)
1135 * This indirect command allows configuring a congestion domain for given L2
1136 * node TEIDs in the scheduler topology.
1138 struct ice_aqc_cfg_l2_node_cgd {
1139 __le16 num_l2_nodes;
1146 struct ice_aqc_cfg_l2_node_cgd_elem {
1153 struct ice_aqc_cfg_l2_node_cgd_data {
1154 struct ice_aqc_cfg_l2_node_cgd_elem elem[1];
1158 /* Query Scheduler Resource Allocation (indirect 0x0412)
1159 * This indirect command retrieves the scheduler resources allocated by
1160 * EMP Firmware to the given PF.
1162 struct ice_aqc_query_txsched_res {
1169 struct ice_aqc_generic_sched_props {
1171 __le16 logical_levels;
1172 u8 flattening_bitmap;
1181 struct ice_aqc_layer_props {
1184 __le16 max_device_nodes;
1185 __le16 max_pf_nodes;
1187 __le16 max_sibl_grp_sz;
1188 __le16 max_cir_rl_profiles;
1189 __le16 max_eir_rl_profiles;
1190 __le16 max_srl_profiles;
1195 struct ice_aqc_query_txsched_res_resp {
1196 struct ice_aqc_generic_sched_props sched_props;
1197 struct ice_aqc_layer_props layer_props[ICE_AQC_TOPO_MAX_LEVEL_NUM];
1201 /* Query Node to Root Topology (indirect 0x0413)
1202 * This command uses ice_aqc_get_elem as its data buffer.
1204 struct ice_aqc_query_node_to_root {
1206 __le32 num_nodes; /* Response only */
1212 /* Get PHY capabilities (indirect 0x0600) */
1213 struct ice_aqc_get_phy_caps {
1217 /* 18.0 - Report qualified modules */
1218 #define ICE_AQC_GET_PHY_RQM BIT(0)
1219 /* 18.1 - 18.2 : Report mode
1220 * 00b - Report NVM capabilities
1221 * 01b - Report topology capabilities
1222 * 10b - Report SW configured
1224 #define ICE_AQC_REPORT_MODE_S 1
1225 #define ICE_AQC_REPORT_MODE_M (3 << ICE_AQC_REPORT_MODE_S)
1226 #define ICE_AQC_REPORT_NVM_CAP 0
1227 #define ICE_AQC_REPORT_TOPO_CAP BIT(1)
1228 #define ICE_AQC_REPORT_SW_CFG BIT(2)
1235 /* This is #define of PHY type (Extended):
1236 * The first set of defines is for phy_type_low.
1238 #define ICE_PHY_TYPE_LOW_100BASE_TX BIT_ULL(0)
1239 #define ICE_PHY_TYPE_LOW_100M_SGMII BIT_ULL(1)
1240 #define ICE_PHY_TYPE_LOW_1000BASE_T BIT_ULL(2)
1241 #define ICE_PHY_TYPE_LOW_1000BASE_SX BIT_ULL(3)
1242 #define ICE_PHY_TYPE_LOW_1000BASE_LX BIT_ULL(4)
1243 #define ICE_PHY_TYPE_LOW_1000BASE_KX BIT_ULL(5)
1244 #define ICE_PHY_TYPE_LOW_1G_SGMII BIT_ULL(6)
1245 #define ICE_PHY_TYPE_LOW_2500BASE_T BIT_ULL(7)
1246 #define ICE_PHY_TYPE_LOW_2500BASE_X BIT_ULL(8)
1247 #define ICE_PHY_TYPE_LOW_2500BASE_KX BIT_ULL(9)
1248 #define ICE_PHY_TYPE_LOW_5GBASE_T BIT_ULL(10)
1249 #define ICE_PHY_TYPE_LOW_5GBASE_KR BIT_ULL(11)
1250 #define ICE_PHY_TYPE_LOW_10GBASE_T BIT_ULL(12)
1251 #define ICE_PHY_TYPE_LOW_10G_SFI_DA BIT_ULL(13)
1252 #define ICE_PHY_TYPE_LOW_10GBASE_SR BIT_ULL(14)
1253 #define ICE_PHY_TYPE_LOW_10GBASE_LR BIT_ULL(15)
1254 #define ICE_PHY_TYPE_LOW_10GBASE_KR_CR1 BIT_ULL(16)
1255 #define ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC BIT_ULL(17)
1256 #define ICE_PHY_TYPE_LOW_10G_SFI_C2C BIT_ULL(18)
1257 #define ICE_PHY_TYPE_LOW_25GBASE_T BIT_ULL(19)
1258 #define ICE_PHY_TYPE_LOW_25GBASE_CR BIT_ULL(20)
1259 #define ICE_PHY_TYPE_LOW_25GBASE_CR_S BIT_ULL(21)
1260 #define ICE_PHY_TYPE_LOW_25GBASE_CR1 BIT_ULL(22)
1261 #define ICE_PHY_TYPE_LOW_25GBASE_SR BIT_ULL(23)
1262 #define ICE_PHY_TYPE_LOW_25GBASE_LR BIT_ULL(24)
1263 #define ICE_PHY_TYPE_LOW_25GBASE_KR BIT_ULL(25)
1264 #define ICE_PHY_TYPE_LOW_25GBASE_KR_S BIT_ULL(26)
1265 #define ICE_PHY_TYPE_LOW_25GBASE_KR1 BIT_ULL(27)
1266 #define ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC BIT_ULL(28)
1267 #define ICE_PHY_TYPE_LOW_25G_AUI_C2C BIT_ULL(29)
1268 #define ICE_PHY_TYPE_LOW_40GBASE_CR4 BIT_ULL(30)
1269 #define ICE_PHY_TYPE_LOW_40GBASE_SR4 BIT_ULL(31)
1270 #define ICE_PHY_TYPE_LOW_40GBASE_LR4 BIT_ULL(32)
1271 #define ICE_PHY_TYPE_LOW_40GBASE_KR4 BIT_ULL(33)
1272 #define ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC BIT_ULL(34)
1273 #define ICE_PHY_TYPE_LOW_40G_XLAUI BIT_ULL(35)
1274 #define ICE_PHY_TYPE_LOW_50GBASE_CR2 BIT_ULL(36)
1275 #define ICE_PHY_TYPE_LOW_50GBASE_SR2 BIT_ULL(37)
1276 #define ICE_PHY_TYPE_LOW_50GBASE_LR2 BIT_ULL(38)
1277 #define ICE_PHY_TYPE_LOW_50GBASE_KR2 BIT_ULL(39)
1278 #define ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC BIT_ULL(40)
1279 #define ICE_PHY_TYPE_LOW_50G_LAUI2 BIT_ULL(41)
1280 #define ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC BIT_ULL(42)
1281 #define ICE_PHY_TYPE_LOW_50G_AUI2 BIT_ULL(43)
1282 #define ICE_PHY_TYPE_LOW_50GBASE_CP BIT_ULL(44)
1283 #define ICE_PHY_TYPE_LOW_50GBASE_SR BIT_ULL(45)
1284 #define ICE_PHY_TYPE_LOW_50GBASE_FR BIT_ULL(46)
1285 #define ICE_PHY_TYPE_LOW_50GBASE_LR BIT_ULL(47)
1286 #define ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4 BIT_ULL(48)
1287 #define ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC BIT_ULL(49)
1288 #define ICE_PHY_TYPE_LOW_50G_AUI1 BIT_ULL(50)
1289 #define ICE_PHY_TYPE_LOW_100GBASE_CR4 BIT_ULL(51)
1290 #define ICE_PHY_TYPE_LOW_100GBASE_SR4 BIT_ULL(52)
1291 #define ICE_PHY_TYPE_LOW_100GBASE_LR4 BIT_ULL(53)
1292 #define ICE_PHY_TYPE_LOW_100GBASE_KR4 BIT_ULL(54)
1293 #define ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC BIT_ULL(55)
1294 #define ICE_PHY_TYPE_LOW_100G_CAUI4 BIT_ULL(56)
1295 #define ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC BIT_ULL(57)
1296 #define ICE_PHY_TYPE_LOW_100G_AUI4 BIT_ULL(58)
1297 #define ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4 BIT_ULL(59)
1298 #define ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4 BIT_ULL(60)
1299 #define ICE_PHY_TYPE_LOW_100GBASE_CP2 BIT_ULL(61)
1300 #define ICE_PHY_TYPE_LOW_100GBASE_SR2 BIT_ULL(62)
1301 #define ICE_PHY_TYPE_LOW_100GBASE_DR BIT_ULL(63)
1302 #define ICE_PHY_TYPE_LOW_MAX_INDEX 63
1303 /* The second set of defines is for phy_type_high. */
1304 #define ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4 BIT_ULL(0)
1305 #define ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC BIT_ULL(1)
1306 #define ICE_PHY_TYPE_HIGH_100G_CAUI2 BIT_ULL(2)
1307 #define ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC BIT_ULL(3)
1308 #define ICE_PHY_TYPE_HIGH_100G_AUI2 BIT_ULL(4)
1309 #define ICE_PHY_TYPE_HIGH_MAX_INDEX 19
1311 struct ice_aqc_get_phy_caps_data {
1312 __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */
1313 __le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */
1315 #define ICE_AQC_PHY_EN_TX_LINK_PAUSE BIT(0)
1316 #define ICE_AQC_PHY_EN_RX_LINK_PAUSE BIT(1)
1317 #define ICE_AQC_PHY_LOW_POWER_MODE BIT(2)
1318 #define ICE_AQC_PHY_EN_LINK BIT(3)
1319 #define ICE_AQC_PHY_AN_MODE BIT(4)
1320 #define ICE_AQC_PHY_EN_MOD_QUAL BIT(5)
1321 #define ICE_AQC_PHY_EN_LESM BIT(6)
1322 #define ICE_AQC_PHY_EN_AUTO_FEC BIT(7)
1323 #define ICE_AQC_PHY_CAPS_MASK MAKEMASK(0xff, 0)
1325 #define ICE_AQC_PHY_EN_D3COLD_LOW_POWER_AUTONEG BIT(0)
1327 #define ICE_AQC_PHY_EEE_EN_100BASE_TX BIT(0)
1328 #define ICE_AQC_PHY_EEE_EN_1000BASE_T BIT(1)
1329 #define ICE_AQC_PHY_EEE_EN_10GBASE_T BIT(2)
1330 #define ICE_AQC_PHY_EEE_EN_1000BASE_KX BIT(3)
1331 #define ICE_AQC_PHY_EEE_EN_10GBASE_KR BIT(4)
1332 #define ICE_AQC_PHY_EEE_EN_25GBASE_KR BIT(5)
1333 #define ICE_AQC_PHY_EEE_EN_40GBASE_KR4 BIT(6)
1334 #define ICE_AQC_PHY_EEE_EN_50GBASE_KR2 BIT(7)
1335 #define ICE_AQC_PHY_EEE_EN_50GBASE_KR_PAM4 BIT(8)
1336 #define ICE_AQC_PHY_EEE_EN_100GBASE_KR4 BIT(9)
1337 #define ICE_AQC_PHY_EEE_EN_100GBASE_KR2_PAM4 BIT(10)
1339 u8 phy_id_oui[4]; /* PHY/Module ID connected on the port */
1341 u8 link_fec_options;
1342 #define ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN BIT(0)
1343 #define ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ BIT(1)
1344 #define ICE_AQC_PHY_FEC_25G_RS_528_REQ BIT(2)
1345 #define ICE_AQC_PHY_FEC_25G_KR_REQ BIT(3)
1346 #define ICE_AQC_PHY_FEC_25G_RS_544_REQ BIT(4)
1347 #define ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN BIT(6)
1348 #define ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN BIT(7)
1349 #define ICE_AQC_PHY_FEC_MASK MAKEMASK(0xdf, 0)
1350 u8 extended_compliance_code;
1351 #define ICE_MODULE_TYPE_TOTAL_BYTE 3
1352 u8 module_type[ICE_MODULE_TYPE_TOTAL_BYTE];
1353 #define ICE_AQC_MOD_TYPE_BYTE0_SFP_PLUS 0xA0
1354 #define ICE_AQC_MOD_TYPE_BYTE0_QSFP_PLUS 0x80
1355 #define ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_PASSIVE BIT(0)
1356 #define ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_ACTIVE BIT(1)
1357 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_SR BIT(4)
1358 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_LR BIT(5)
1359 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_LRM BIT(6)
1360 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_ER BIT(7)
1361 #define ICE_AQC_MOD_TYPE_BYTE2_SFP_PLUS 0xA0
1362 #define ICE_AQC_MOD_TYPE_BYTE2_QSFP_PLUS 0x86
1363 u8 qualified_module_count;
1364 #define ICE_AQC_QUAL_MOD_COUNT_MAX 16
1371 } qual_modules[ICE_AQC_QUAL_MOD_COUNT_MAX];
1375 /* Set PHY capabilities (direct 0x0601)
1376 * NOTE: This command must be followed by setup link and restart auto-neg
1378 struct ice_aqc_set_phy_cfg {
1386 /* Set PHY config command data structure */
1387 struct ice_aqc_set_phy_cfg_data {
1388 __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */
1389 __le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */
1391 #define ICE_AQ_PHY_ENA_VALID_MASK MAKEMASK(0xef, 0)
1392 #define ICE_AQ_PHY_ENA_TX_PAUSE_ABILITY BIT(0)
1393 #define ICE_AQ_PHY_ENA_RX_PAUSE_ABILITY BIT(1)
1394 #define ICE_AQ_PHY_ENA_LOW_POWER BIT(2)
1395 #define ICE_AQ_PHY_ENA_LINK BIT(3)
1396 #define ICE_AQ_PHY_ENA_AUTO_LINK_UPDT BIT(5)
1397 #define ICE_AQ_PHY_ENA_LESM BIT(6)
1398 #define ICE_AQ_PHY_ENA_AUTO_FEC BIT(7)
1400 __le16 eee_cap; /* Value from ice_aqc_get_phy_caps */
1402 u8 link_fec_opt; /* Use defines from ice_aqc_get_phy_caps */
1407 /* Set MAC Config command data structure (direct 0x0603) */
1408 struct ice_aqc_set_mac_cfg {
1409 __le16 max_frame_size;
1411 #define ICE_AQ_SET_MAC_PACE_S 3
1412 #define ICE_AQ_SET_MAC_PACE_M (0xF << ICE_AQ_SET_MAC_PACE_S)
1413 #define ICE_AQ_SET_MAC_PACE_TYPE_M BIT(7)
1414 #define ICE_AQ_SET_MAC_PACE_TYPE_RATE 0
1415 #define ICE_AQ_SET_MAC_PACE_TYPE_FIXED ICE_AQ_SET_MAC_PACE_TYPE_M
1417 __le16 tx_tmr_value;
1418 __le16 fc_refresh_threshold;
1420 #define ICE_AQ_SET_MAC_AUTO_DROP_MASK BIT(0)
1421 #define ICE_AQ_SET_MAC_AUTO_DROP_NONE 0
1422 #define ICE_AQ_SET_MAC_AUTO_DROP_BLOCKING_PKTS BIT(0)
1427 /* Restart AN command data structure (direct 0x0605)
1428 * Also used for response, with only the lport_num field present.
1430 struct ice_aqc_restart_an {
1434 #define ICE_AQC_RESTART_AN_LINK_RESTART BIT(1)
1435 #define ICE_AQC_RESTART_AN_LINK_ENABLE BIT(2)
1440 /* Get link status (indirect 0x0607), also used for Link Status Event */
1441 struct ice_aqc_get_link_status {
1445 #define ICE_AQ_LSE_M 0x3
1446 #define ICE_AQ_LSE_NOP 0x0
1447 #define ICE_AQ_LSE_DIS 0x2
1448 #define ICE_AQ_LSE_ENA 0x3
1449 /* only response uses this flag */
1450 #define ICE_AQ_LSE_IS_ENABLED 0x1
1457 /* Get link status response data structure, also used for Link Status Event */
1458 struct ice_aqc_get_link_status_data {
1459 u8 topo_media_conflict;
1460 #define ICE_AQ_LINK_TOPO_CONFLICT BIT(0)
1461 #define ICE_AQ_LINK_MEDIA_CONFLICT BIT(1)
1462 #define ICE_AQ_LINK_TOPO_CORRUPT BIT(2)
1463 #define ICE_AQ_LINK_TOPO_UNREACH_PRT BIT(4)
1464 #define ICE_AQ_LINK_TOPO_UNDRUTIL_PRT BIT(5)
1465 #define ICE_AQ_LINK_TOPO_UNDRUTIL_MEDIA BIT(6)
1466 #define ICE_AQ_LINK_TOPO_UNSUPP_MEDIA BIT(7)
1468 #define ICE_AQ_LINK_CFG_ERR BIT(0)
1470 #define ICE_AQ_LINK_UP BIT(0) /* Link Status */
1471 #define ICE_AQ_LINK_FAULT BIT(1)
1472 #define ICE_AQ_LINK_FAULT_TX BIT(2)
1473 #define ICE_AQ_LINK_FAULT_RX BIT(3)
1474 #define ICE_AQ_LINK_FAULT_REMOTE BIT(4)
1475 #define ICE_AQ_LINK_UP_PORT BIT(5) /* External Port Link Status */
1476 #define ICE_AQ_MEDIA_AVAILABLE BIT(6)
1477 #define ICE_AQ_SIGNAL_DETECT BIT(7)
1479 #define ICE_AQ_AN_COMPLETED BIT(0)
1480 #define ICE_AQ_LP_AN_ABILITY BIT(1)
1481 #define ICE_AQ_PD_FAULT BIT(2) /* Parallel Detection Fault */
1482 #define ICE_AQ_FEC_EN BIT(3)
1483 #define ICE_AQ_PHY_LOW_POWER BIT(4) /* Low Power State */
1484 #define ICE_AQ_LINK_PAUSE_TX BIT(5)
1485 #define ICE_AQ_LINK_PAUSE_RX BIT(6)
1486 #define ICE_AQ_QUALIFIED_MODULE BIT(7)
1488 #define ICE_AQ_LINK_PHY_TEMP_ALARM BIT(0)
1489 #define ICE_AQ_LINK_EXCESSIVE_ERRORS BIT(1) /* Excessive Link Errors */
1490 /* Port Tx Suspended */
1491 #define ICE_AQ_LINK_TX_S 2
1492 #define ICE_AQ_LINK_TX_M (0x03 << ICE_AQ_LINK_TX_S)
1493 #define ICE_AQ_LINK_TX_ACTIVE 0
1494 #define ICE_AQ_LINK_TX_DRAINED 1
1495 #define ICE_AQ_LINK_TX_FLUSHED 3
1497 __le16 max_frame_size;
1499 #define ICE_AQ_LINK_25G_KR_FEC_EN BIT(0)
1500 #define ICE_AQ_LINK_25G_RS_528_FEC_EN BIT(1)
1501 #define ICE_AQ_LINK_25G_RS_544_FEC_EN BIT(2)
1502 #define ICE_AQ_FEC_MASK MAKEMASK(0x7, 0)
1504 #define ICE_AQ_CFG_PACING_S 3
1505 #define ICE_AQ_CFG_PACING_M (0xF << ICE_AQ_CFG_PACING_S)
1506 #define ICE_AQ_CFG_PACING_TYPE_M BIT(7)
1507 #define ICE_AQ_CFG_PACING_TYPE_AVG 0
1508 #define ICE_AQ_CFG_PACING_TYPE_FIXED ICE_AQ_CFG_PACING_TYPE_M
1509 /* External Device Power Ability */
1511 #define ICE_AQ_PWR_CLASS_M 0x3
1512 #define ICE_AQ_LINK_PWR_BASET_LOW_HIGH 0
1513 #define ICE_AQ_LINK_PWR_BASET_HIGH 1
1514 #define ICE_AQ_LINK_PWR_QSFP_CLASS_1 0
1515 #define ICE_AQ_LINK_PWR_QSFP_CLASS_2 1
1516 #define ICE_AQ_LINK_PWR_QSFP_CLASS_3 2
1517 #define ICE_AQ_LINK_PWR_QSFP_CLASS_4 3
1519 #define ICE_AQ_LINK_SPEED_10MB BIT(0)
1520 #define ICE_AQ_LINK_SPEED_100MB BIT(1)
1521 #define ICE_AQ_LINK_SPEED_1000MB BIT(2)
1522 #define ICE_AQ_LINK_SPEED_2500MB BIT(3)
1523 #define ICE_AQ_LINK_SPEED_5GB BIT(4)
1524 #define ICE_AQ_LINK_SPEED_10GB BIT(5)
1525 #define ICE_AQ_LINK_SPEED_20GB BIT(6)
1526 #define ICE_AQ_LINK_SPEED_25GB BIT(7)
1527 #define ICE_AQ_LINK_SPEED_40GB BIT(8)
1528 #define ICE_AQ_LINK_SPEED_50GB BIT(9)
1529 #define ICE_AQ_LINK_SPEED_100GB BIT(10)
1530 #define ICE_AQ_LINK_SPEED_UNKNOWN BIT(15)
1531 __le32 reserved3; /* Aligns next field to 8-byte boundary */
1532 __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */
1533 __le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */
1537 /* Set event mask command (direct 0x0613) */
1538 struct ice_aqc_set_event_mask {
1542 #define ICE_AQ_LINK_EVENT_UPDOWN BIT(1)
1543 #define ICE_AQ_LINK_EVENT_MEDIA_NA BIT(2)
1544 #define ICE_AQ_LINK_EVENT_LINK_FAULT BIT(3)
1545 #define ICE_AQ_LINK_EVENT_PHY_TEMP_ALARM BIT(4)
1546 #define ICE_AQ_LINK_EVENT_EXCESSIVE_ERRORS BIT(5)
1547 #define ICE_AQ_LINK_EVENT_SIGNAL_DETECT BIT(6)
1548 #define ICE_AQ_LINK_EVENT_AN_COMPLETED BIT(7)
1549 #define ICE_AQ_LINK_EVENT_MODULE_QUAL_FAIL BIT(8)
1550 #define ICE_AQ_LINK_EVENT_PORT_TX_SUSPENDED BIT(9)
1556 /* Set MAC Loopback command (direct 0x0620) */
1557 struct ice_aqc_set_mac_lb {
1559 #define ICE_AQ_MAC_LB_EN BIT(0)
1560 #define ICE_AQ_MAC_LB_OSC_CLK BIT(1)
1568 /* Set Port Identification LED (direct, 0x06E9) */
1569 struct ice_aqc_set_port_id_led {
1572 #define ICE_AQC_PORT_ID_PORT_NUM_VALID BIT(0)
1574 #define ICE_AQC_PORT_IDENT_LED_BLINK BIT(0)
1575 #define ICE_AQC_PORT_IDENT_LED_ORIG 0
1581 /* NVM Read command (indirect 0x0701)
1582 * NVM Erase commands (direct 0x0702)
1583 * NVM Update commands (indirect 0x0703)
1585 struct ice_aqc_nvm {
1589 #define ICE_AQC_NVM_LAST_CMD BIT(0)
1590 #define ICE_AQC_NVM_PCIR_REQ BIT(0) /* Used by NVM Update reply */
1591 #define ICE_AQC_NVM_PRESERVATION_S 1
1592 #define ICE_AQC_NVM_PRESERVATION_M (3 << ICE_AQC_NVM_PRESERVATION_S)
1593 #define ICE_AQC_NVM_NO_PRESERVATION (0 << ICE_AQC_NVM_PRESERVATION_S)
1594 #define ICE_AQC_NVM_PRESERVE_ALL BIT(1)
1595 #define ICE_AQC_NVM_FACTORY_DEFAULT (2 << ICE_AQC_NVM_PRESERVATION_S)
1596 #define ICE_AQC_NVM_PRESERVE_SELECTED (3 << ICE_AQC_NVM_PRESERVATION_S)
1597 #define ICE_AQC_NVM_FLASH_ONLY BIT(7)
1598 __le16 module_typeid;
1600 #define ICE_AQC_NVM_ERASE_LEN 0xFFFF
1606 /* Used for 0x0704 as well as for 0x0705 commands */
1607 struct ice_aqc_nvm_cfg {
1609 #define ICE_AQC_ANVM_MULTIPLE_ELEMS BIT(0)
1610 #define ICE_AQC_ANVM_IMMEDIATE_FIELD BIT(1)
1611 #define ICE_AQC_ANVM_NEW_CFG BIT(2)
1621 struct ice_aqc_nvm_cfg_data {
1623 __le16 field_options;
1628 /* NVM Checksum Command (direct, 0x0706) */
1629 struct ice_aqc_nvm_checksum {
1631 #define ICE_AQC_NVM_CHECKSUM_VERIFY BIT(0)
1632 #define ICE_AQC_NVM_CHECKSUM_RECALC BIT(1)
1634 __le16 checksum; /* Used only by response */
1635 #define ICE_AQC_NVM_CHECKSUM_CORRECT 0xBABA
1642 /* Get LLDP MIB (indirect 0x0A00)
1643 * Note: This is also used by the LLDP MIB Change Event (0x0A01)
1644 * as the format is the same.
1646 struct ice_aqc_lldp_get_mib {
1648 #define ICE_AQ_LLDP_MIB_TYPE_S 0
1649 #define ICE_AQ_LLDP_MIB_TYPE_M (0x3 << ICE_AQ_LLDP_MIB_TYPE_S)
1650 #define ICE_AQ_LLDP_MIB_LOCAL 0
1651 #define ICE_AQ_LLDP_MIB_REMOTE 1
1652 #define ICE_AQ_LLDP_MIB_LOCAL_AND_REMOTE 2
1653 #define ICE_AQ_LLDP_BRID_TYPE_S 2
1654 #define ICE_AQ_LLDP_BRID_TYPE_M (0x3 << ICE_AQ_LLDP_BRID_TYPE_S)
1655 #define ICE_AQ_LLDP_BRID_TYPE_NEAREST_BRID 0
1656 #define ICE_AQ_LLDP_BRID_TYPE_NON_TPMR 1
1657 /* Tx pause flags in the 0xA01 event use ICE_AQ_LLDP_TX_* */
1658 #define ICE_AQ_LLDP_TX_S 0x4
1659 #define ICE_AQ_LLDP_TX_M (0x03 << ICE_AQ_LLDP_TX_S)
1660 #define ICE_AQ_LLDP_TX_ACTIVE 0
1661 #define ICE_AQ_LLDP_TX_SUSPENDED 1
1662 #define ICE_AQ_LLDP_TX_FLUSHED 3
1663 /* The following bytes are reserved for the Get LLDP MIB command (0x0A00)
1664 * and in the LLDP MIB Change Event (0x0A01). They are valid for the
1665 * Get LLDP MIB (0x0A00) response only.
1675 /* Configure LLDP MIB Change Event (direct 0x0A01) */
1676 /* For MIB Change Event use ice_aqc_lldp_get_mib structure above */
1677 struct ice_aqc_lldp_set_mib_change {
1679 #define ICE_AQ_LLDP_MIB_UPDATE_ENABLE 0x0
1680 #define ICE_AQ_LLDP_MIB_UPDATE_DIS 0x1
1684 /* Add LLDP TLV (indirect 0x0A02)
1685 * Delete LLDP TLV (indirect 0x0A04)
1687 struct ice_aqc_lldp_add_delete_tlv {
1688 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */
1696 /* Update LLDP TLV (indirect 0x0A03) */
1697 struct ice_aqc_lldp_update_tlv {
1698 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */
1707 /* Stop LLDP (direct 0x0A05) */
1708 struct ice_aqc_lldp_stop {
1710 #define ICE_AQ_LLDP_AGENT_STATE_MASK BIT(0)
1711 #define ICE_AQ_LLDP_AGENT_STOP 0x0
1712 #define ICE_AQ_LLDP_AGENT_SHUTDOWN ICE_AQ_LLDP_AGENT_STATE_MASK
1713 #define ICE_AQ_LLDP_AGENT_PERSIST_DIS BIT(1)
1717 /* Start LLDP (direct 0x0A06) */
1718 struct ice_aqc_lldp_start {
1720 #define ICE_AQ_LLDP_AGENT_START BIT(0)
1721 #define ICE_AQ_LLDP_AGENT_PERSIST_ENA BIT(1)
1725 /* Get CEE DCBX Oper Config (0x0A07)
1726 * The command uses the generic descriptor struct and
1727 * returns the struct below as an indirect response.
1729 struct ice_aqc_get_cee_dcb_cfg_resp {
1734 __le16 oper_app_prio;
1735 #define ICE_AQC_CEE_APP_FCOE_S 0
1736 #define ICE_AQC_CEE_APP_FCOE_M (0x7 << ICE_AQC_CEE_APP_FCOE_S)
1737 #define ICE_AQC_CEE_APP_ISCSI_S 3
1738 #define ICE_AQC_CEE_APP_ISCSI_M (0x7 << ICE_AQC_CEE_APP_ISCSI_S)
1739 #define ICE_AQC_CEE_APP_FIP_S 8
1740 #define ICE_AQC_CEE_APP_FIP_M (0x7 << ICE_AQC_CEE_APP_FIP_S)
1742 #define ICE_AQC_CEE_PG_STATUS_S 0
1743 #define ICE_AQC_CEE_PG_STATUS_M (0x7 << ICE_AQC_CEE_PG_STATUS_S)
1744 #define ICE_AQC_CEE_PFC_STATUS_S 3
1745 #define ICE_AQC_CEE_PFC_STATUS_M (0x7 << ICE_AQC_CEE_PFC_STATUS_S)
1746 #define ICE_AQC_CEE_FCOE_STATUS_S 8
1747 #define ICE_AQC_CEE_FCOE_STATUS_M (0x7 << ICE_AQC_CEE_FCOE_STATUS_S)
1748 #define ICE_AQC_CEE_ISCSI_STATUS_S 11
1749 #define ICE_AQC_CEE_ISCSI_STATUS_M (0x7 << ICE_AQC_CEE_ISCSI_STATUS_S)
1750 #define ICE_AQC_CEE_FIP_STATUS_S 16
1751 #define ICE_AQC_CEE_FIP_STATUS_M (0x7 << ICE_AQC_CEE_FIP_STATUS_S)
1755 /* Set Local LLDP MIB (indirect 0x0A08)
1756 * Used to replace the local MIB of a given LLDP agent. e.g. DCBx
1758 struct ice_aqc_lldp_set_local_mib {
1760 #define SET_LOCAL_MIB_TYPE_DCBX_M BIT(0)
1761 #define SET_LOCAL_MIB_TYPE_LOCAL_MIB 0
1762 #define SET_LOCAL_MIB_TYPE_CEE_M BIT(1)
1763 #define SET_LOCAL_MIB_TYPE_CEE_WILLING 0
1764 #define SET_LOCAL_MIB_TYPE_CEE_NON_WILLING SET_LOCAL_MIB_TYPE_CEE_M
1772 struct ice_aqc_lldp_set_local_mib_resp {
1774 #define SET_LOCAL_MIB_RESP_EVENT_M BIT(0)
1775 #define SET_LOCAL_MIB_RESP_MIB_CHANGE_SILENT 0
1776 #define SET_LOCAL_MIB_RESP_MIB_CHANGE_EVENT SET_LOCAL_MIB_RESP_EVENT_M
1780 /* Stop/Start LLDP Agent (direct 0x0A09)
1781 * Used for stopping/starting specific LLDP agent. e.g. DCBx.
1782 * The same structure is used for the response, with the command field
1783 * being used as the status field.
1785 struct ice_aqc_lldp_stop_start_specific_agent {
1787 #define ICE_AQC_START_STOP_AGENT_M BIT(0)
1788 #define ICE_AQC_START_STOP_AGENT_STOP_DCBX 0
1789 #define ICE_AQC_START_STOP_AGENT_START_DCBX ICE_AQC_START_STOP_AGENT_M
1794 /* Get/Set RSS key (indirect 0x0B04/0x0B02) */
1795 struct ice_aqc_get_set_rss_key {
1796 #define ICE_AQC_GSET_RSS_KEY_VSI_VALID BIT(15)
1797 #define ICE_AQC_GSET_RSS_KEY_VSI_ID_S 0
1798 #define ICE_AQC_GSET_RSS_KEY_VSI_ID_M (0x3FF << ICE_AQC_GSET_RSS_KEY_VSI_ID_S)
1806 #define ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE 0x28
1807 #define ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE 0xC
1808 #define ICE_GET_SET_RSS_KEY_EXTEND_KEY_SIZE \
1809 (ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE + \
1810 ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE)
1813 * struct ice_aqc_get_set_rss_keys - Get/Set RSS hash key command buffer
1814 * @standard_rss_key: 40 most significant bytes of hash key
1815 * @extended_hash_key: 12 least significant bytes of hash key
1817 * Set/Get 40 byte hash key using standard_rss_key field, and set
1818 * extended_hash_key field to zero. Set/Get 52 byte hash key using
1819 * standard_rss_key field for 40 most significant bytes and the
1820 * extended_hash_key field for the 12 least significant bytes of hash key.
1822 struct ice_aqc_get_set_rss_keys {
1823 u8 standard_rss_key[ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE];
1824 u8 extended_hash_key[ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE];
1828 /* Get/Set RSS LUT (indirect 0x0B05/0x0B03) */
1829 struct ice_aqc_get_set_rss_lut {
1830 #define ICE_AQC_GSET_RSS_LUT_VSI_VALID BIT(15)
1831 #define ICE_AQC_GSET_RSS_LUT_VSI_ID_S 0
1832 #define ICE_AQC_GSET_RSS_LUT_VSI_ID_M (0x1FF << ICE_AQC_GSET_RSS_LUT_VSI_ID_S)
1834 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S 0
1835 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_M \
1836 (0x3 << ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S)
1838 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_VSI 0
1839 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF 1
1840 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL 2
1842 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S 2
1843 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M \
1844 (0x3 << ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S)
1846 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128 128
1847 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128_FLAG 0
1848 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512 512
1849 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512_FLAG 1
1850 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K 2048
1851 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K_FLAG 2
1853 #define ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S 4
1854 #define ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_M \
1855 (0xF << ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S)
1867 /* Add Tx LAN Queues (indirect 0x0C30) */
1868 struct ice_aqc_add_txqs {
1877 /* This is the descriptor of each queue entry for the Add Tx LAN Queues
1878 * command (0x0C30). Only used within struct ice_aqc_add_tx_qgrp.
1880 struct ice_aqc_add_txqs_perq {
1886 struct ice_aqc_txsched_elem info;
1890 /* The format of the command buffer for Add Tx LAN Queues (0x0C30)
1891 * is an array of the following structs. Please note that the length of
1892 * each struct ice_aqc_add_tx_qgrp is variable due
1893 * to the variable number of queues in each group!
1895 struct ice_aqc_add_tx_qgrp {
1899 struct ice_aqc_add_txqs_perq txqs[1];
1903 /* Disable Tx LAN Queues (indirect 0x0C31) */
1904 struct ice_aqc_dis_txqs {
1906 #define ICE_AQC_Q_DIS_CMD_S 0
1907 #define ICE_AQC_Q_DIS_CMD_M (0x3 << ICE_AQC_Q_DIS_CMD_S)
1908 #define ICE_AQC_Q_DIS_CMD_NO_FUNC_RESET (0 << ICE_AQC_Q_DIS_CMD_S)
1909 #define ICE_AQC_Q_DIS_CMD_VM_RESET BIT(ICE_AQC_Q_DIS_CMD_S)
1910 #define ICE_AQC_Q_DIS_CMD_VF_RESET (2 << ICE_AQC_Q_DIS_CMD_S)
1911 #define ICE_AQC_Q_DIS_CMD_PF_RESET (3 << ICE_AQC_Q_DIS_CMD_S)
1912 #define ICE_AQC_Q_DIS_CMD_SUBSEQ_CALL BIT(2)
1913 #define ICE_AQC_Q_DIS_CMD_FLUSH_PIPE BIT(3)
1915 __le16 vmvf_and_timeout;
1916 #define ICE_AQC_Q_DIS_VMVF_NUM_S 0
1917 #define ICE_AQC_Q_DIS_VMVF_NUM_M (0x3FF << ICE_AQC_Q_DIS_VMVF_NUM_S)
1918 #define ICE_AQC_Q_DIS_TIMEOUT_S 10
1919 #define ICE_AQC_Q_DIS_TIMEOUT_M (0x3F << ICE_AQC_Q_DIS_TIMEOUT_S)
1920 __le32 blocked_cgds;
1926 /* The buffer for Disable Tx LAN Queues (indirect 0x0C31)
1927 * contains the following structures, arrayed one after the
1929 * Note: Since the q_id is 16 bits wide, if the
1930 * number of queues is even, then 2 bytes of alignment MUST be
1931 * added before the start of the next group, to allow correct
1932 * alignment of the parent_teid field.
1934 struct ice_aqc_dis_txq_item {
1938 /* The length of the q_id array varies according to num_qs */
1940 /* This only applies from F8 onward */
1941 #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S 15
1942 #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_LAN_Q \
1943 (0 << ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S)
1944 #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_RDMA_QSET \
1945 (1 << ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S)
1949 struct ice_aqc_dis_txq {
1950 struct ice_aqc_dis_txq_item qgrps[1];
1954 /* Tx LAN Queues Cleanup Event (0x0C31) */
1955 struct ice_aqc_txqs_cleanup {
1962 /* Move / Reconfigure Tx Queues (indirect 0x0C32) */
1963 struct ice_aqc_move_txqs {
1965 #define ICE_AQC_Q_CMD_TYPE_S 0
1966 #define ICE_AQC_Q_CMD_TYPE_M (0x3 << ICE_AQC_Q_CMD_TYPE_S)
1967 #define ICE_AQC_Q_CMD_TYPE_MOVE 1
1968 #define ICE_AQC_Q_CMD_TYPE_TC_CHANGE 2
1969 #define ICE_AQC_Q_CMD_TYPE_MOVE_AND_TC 3
1970 #define ICE_AQC_Q_CMD_SUBSEQ_CALL BIT(2)
1971 #define ICE_AQC_Q_CMD_FLUSH_PIPE BIT(3)
1975 #define ICE_AQC_Q_CMD_TIMEOUT_S 2
1976 #define ICE_AQC_Q_CMD_TIMEOUT_M (0x3F << ICE_AQC_Q_CMD_TIMEOUT_S)
1977 __le32 blocked_cgds;
1983 /* This is the descriptor of each queue entry for the move Tx LAN Queues
1986 struct ice_aqc_move_txqs_elem {
1994 struct ice_aqc_move_txqs_data {
1997 struct ice_aqc_move_txqs_elem txqs[1];
2002 /* Download Package (indirect 0x0C40) */
2003 /* Also used for Update Package (indirect 0x0C42) */
2004 struct ice_aqc_download_pkg {
2006 #define ICE_AQC_DOWNLOAD_PKG_LAST_BUF 0x01
2013 struct ice_aqc_download_pkg_resp {
2014 __le32 error_offset;
2020 /* Get Package Info List (indirect 0x0C43) */
2021 struct ice_aqc_get_pkg_info_list {
2028 /* Version format for packages */
2029 struct ice_pkg_ver {
2036 #define ICE_PKG_NAME_SIZE 32
2038 struct ice_aqc_get_pkg_info {
2039 struct ice_pkg_ver ver;
2040 char name[ICE_PKG_NAME_SIZE];
2043 u8 is_active_at_boot;
2047 /* Get Package Info List response buffer format (0x0C43) */
2048 struct ice_aqc_get_pkg_info_resp {
2050 struct ice_aqc_get_pkg_info pkg_info[1];
2056 /* Lan Queue Overflow Event (direct, 0x1001) */
2057 struct ice_aqc_event_lan_overflow {
2058 __le32 prtdcb_ruptq;
2065 /* Configure Firmware Logging Command (indirect 0xFF09)
2066 * Logging Information Read Response (indirect 0xFF10)
2067 * Note: The 0xFF10 command has no input parameters.
2069 struct ice_aqc_fw_logging {
2071 #define ICE_AQC_FW_LOG_AQ_EN BIT(0)
2072 #define ICE_AQC_FW_LOG_UART_EN BIT(1)
2074 u8 log_ctrl_valid; /* Not used by 0xFF10 Response */
2075 #define ICE_AQC_FW_LOG_AQ_VALID BIT(0)
2076 #define ICE_AQC_FW_LOG_UART_VALID BIT(1)
2083 enum ice_aqc_fw_logging_mod {
2084 ICE_AQC_FW_LOG_ID_GENERAL = 0,
2085 ICE_AQC_FW_LOG_ID_CTRL,
2086 ICE_AQC_FW_LOG_ID_LINK,
2087 ICE_AQC_FW_LOG_ID_LINK_TOPO,
2088 ICE_AQC_FW_LOG_ID_DNL,
2089 ICE_AQC_FW_LOG_ID_I2C,
2090 ICE_AQC_FW_LOG_ID_SDP,
2091 ICE_AQC_FW_LOG_ID_MDIO,
2092 ICE_AQC_FW_LOG_ID_ADMINQ,
2093 ICE_AQC_FW_LOG_ID_HDMA,
2094 ICE_AQC_FW_LOG_ID_LLDP,
2095 ICE_AQC_FW_LOG_ID_DCBX,
2096 ICE_AQC_FW_LOG_ID_DCB,
2097 ICE_AQC_FW_LOG_ID_NETPROXY,
2098 ICE_AQC_FW_LOG_ID_NVM,
2099 ICE_AQC_FW_LOG_ID_AUTH,
2100 ICE_AQC_FW_LOG_ID_VPD,
2101 ICE_AQC_FW_LOG_ID_IOSF,
2102 ICE_AQC_FW_LOG_ID_PARSER,
2103 ICE_AQC_FW_LOG_ID_SW,
2104 ICE_AQC_FW_LOG_ID_SCHEDULER,
2105 ICE_AQC_FW_LOG_ID_TXQ,
2106 ICE_AQC_FW_LOG_ID_RSVD,
2107 ICE_AQC_FW_LOG_ID_POST,
2108 ICE_AQC_FW_LOG_ID_WATCHDOG,
2109 ICE_AQC_FW_LOG_ID_TASK_DISPATCH,
2110 ICE_AQC_FW_LOG_ID_MNG,
2111 ICE_AQC_FW_LOG_ID_MAX,
2114 /* This is the buffer for both of the logging commands.
2115 * The entry array size depends on the datalen parameter in the descriptor.
2116 * There will be a total of datalen / 2 entries.
2118 struct ice_aqc_fw_logging_data {
2120 #define ICE_AQC_FW_LOG_ID_S 0
2121 #define ICE_AQC_FW_LOG_ID_M (0xFFF << ICE_AQC_FW_LOG_ID_S)
2123 #define ICE_AQC_FW_LOG_CONF_SUCCESS 0 /* Used by response */
2124 #define ICE_AQC_FW_LOG_CONF_BAD_INDX BIT(12) /* Used by response */
2126 #define ICE_AQC_FW_LOG_EN_S 12
2127 #define ICE_AQC_FW_LOG_EN_M (0xF << ICE_AQC_FW_LOG_EN_S)
2128 #define ICE_AQC_FW_LOG_INFO_EN BIT(12) /* Used by command */
2129 #define ICE_AQC_FW_LOG_INIT_EN BIT(13) /* Used by command */
2130 #define ICE_AQC_FW_LOG_FLOW_EN BIT(14) /* Used by command */
2131 #define ICE_AQC_FW_LOG_ERR_EN BIT(15) /* Used by command */
2135 /* Get/Clear FW Log (indirect 0xFF11) */
2136 struct ice_aqc_get_clear_fw_log {
2138 #define ICE_AQC_FW_LOG_CLEAR BIT(0)
2139 #define ICE_AQC_FW_LOG_MORE_DATA_AVAIL BIT(1)
2147 * struct ice_aq_desc - Admin Queue (AQ) descriptor
2148 * @flags: ICE_AQ_FLAG_* flags
2149 * @opcode: AQ command opcode
2150 * @datalen: length in bytes of indirect/external data buffer
2151 * @retval: return value from firmware
2152 * @cookie_h: opaque data high-half
2153 * @cookie_l: opaque data low-half
2154 * @params: command-specific parameters
2156 * Descriptor format for commands the driver posts on the Admin Transmit Queue
2157 * (ATQ). The firmware writes back onto the command descriptor and returns
2158 * the result of the command. Asynchronous events that are not an immediate
2159 * result of the command are written to the Admin Receive Queue (ARQ) using
2160 * the same descriptor format. Descriptors are in little-endian notation with
2163 struct ice_aq_desc {
2172 struct ice_aqc_generic generic;
2173 struct ice_aqc_get_ver get_ver;
2174 struct ice_aqc_q_shutdown q_shutdown;
2175 struct ice_aqc_req_res res_owner;
2176 struct ice_aqc_manage_mac_read mac_read;
2177 struct ice_aqc_manage_mac_write mac_write;
2178 struct ice_aqc_clear_pxe clear_pxe;
2179 struct ice_aqc_config_no_drop_policy no_drop;
2180 struct ice_aqc_add_update_mir_rule add_update_rule;
2181 struct ice_aqc_delete_mir_rule del_rule;
2182 struct ice_aqc_list_caps get_cap;
2183 struct ice_aqc_get_phy_caps get_phy;
2184 struct ice_aqc_set_phy_cfg set_phy;
2185 struct ice_aqc_restart_an restart_an;
2186 struct ice_aqc_set_port_id_led set_port_id_led;
2187 struct ice_aqc_get_sw_cfg get_sw_conf;
2188 struct ice_aqc_sw_rules sw_rules;
2189 struct ice_aqc_storm_cfg storm_conf;
2190 struct ice_aqc_get_topo get_topo;
2191 struct ice_aqc_sched_elem_cmd sched_elem_cmd;
2192 struct ice_aqc_query_txsched_res query_sched_res;
2193 struct ice_aqc_query_node_to_root query_node_to_root;
2194 struct ice_aqc_cfg_l2_node_cgd cfg_l2_node_cgd;
2195 struct ice_aqc_query_port_ets port_ets;
2196 struct ice_aqc_rl_profile rl_profile;
2197 struct ice_aqc_nvm nvm;
2198 struct ice_aqc_nvm_cfg nvm_cfg;
2199 struct ice_aqc_nvm_checksum nvm_checksum;
2200 struct ice_aqc_pfc_ignore pfc_ignore;
2201 struct ice_aqc_set_query_pfc_mode set_query_pfc_mode;
2202 struct ice_aqc_set_dcb_params set_dcb_params;
2203 struct ice_aqc_lldp_get_mib lldp_get_mib;
2204 struct ice_aqc_lldp_set_mib_change lldp_set_event;
2205 struct ice_aqc_lldp_add_delete_tlv lldp_add_delete_tlv;
2206 struct ice_aqc_lldp_update_tlv lldp_update_tlv;
2207 struct ice_aqc_lldp_stop lldp_stop;
2208 struct ice_aqc_lldp_start lldp_start;
2209 struct ice_aqc_lldp_set_local_mib lldp_set_mib;
2210 struct ice_aqc_lldp_stop_start_specific_agent lldp_agent_ctrl;
2211 struct ice_aqc_get_set_rss_lut get_set_rss_lut;
2212 struct ice_aqc_get_set_rss_key get_set_rss_key;
2213 struct ice_aqc_add_txqs add_txqs;
2214 struct ice_aqc_dis_txqs dis_txqs;
2215 struct ice_aqc_txqs_cleanup txqs_cleanup;
2216 struct ice_aqc_add_get_update_free_vsi vsi_cmd;
2217 struct ice_aqc_add_update_free_vsi_resp add_update_free_vsi_res;
2218 struct ice_aqc_get_vsi_resp get_vsi_resp;
2219 struct ice_aqc_download_pkg download_pkg;
2220 struct ice_aqc_get_pkg_info_list get_pkg_info_list;
2221 struct ice_aqc_fw_logging fw_logging;
2222 struct ice_aqc_get_clear_fw_log get_clear_fw_log;
2223 struct ice_aqc_set_mac_lb set_mac_lb;
2224 struct ice_aqc_alloc_free_res_cmd sw_res_ctrl;
2225 struct ice_aqc_get_res_alloc get_res;
2226 struct ice_aqc_get_allocd_res_desc get_res_desc;
2227 struct ice_aqc_set_mac_cfg set_mac_cfg;
2228 struct ice_aqc_set_event_mask set_event_mask;
2229 struct ice_aqc_get_link_status get_link_status;
2234 /* FW defined boundary for a large buffer, 4k >= Large buffer > 512 bytes */
2235 #define ICE_AQ_LG_BUF 512
2237 /* Flags sub-structure
2238 * |0 |1 |2 |3 |4 |5 |6 |7 |8 |9 |10 |11 |12 |13 |14 |15 |
2239 * |DD |CMP|ERR|VFE| * * RESERVED * * |LB |RD |VFC|BUF|SI |EI |FE |
2242 /* command flags and offsets */
2243 #define ICE_AQ_FLAG_DD_S 0
2244 #define ICE_AQ_FLAG_CMP_S 1
2245 #define ICE_AQ_FLAG_ERR_S 2
2246 #define ICE_AQ_FLAG_VFE_S 3
2247 #define ICE_AQ_FLAG_LB_S 9
2248 #define ICE_AQ_FLAG_RD_S 10
2249 #define ICE_AQ_FLAG_VFC_S 11
2250 #define ICE_AQ_FLAG_BUF_S 12
2251 #define ICE_AQ_FLAG_SI_S 13
2252 #define ICE_AQ_FLAG_EI_S 14
2253 #define ICE_AQ_FLAG_FE_S 15
2255 #define ICE_AQ_FLAG_DD BIT(ICE_AQ_FLAG_DD_S) /* 0x1 */
2256 #define ICE_AQ_FLAG_CMP BIT(ICE_AQ_FLAG_CMP_S) /* 0x2 */
2257 #define ICE_AQ_FLAG_ERR BIT(ICE_AQ_FLAG_ERR_S) /* 0x4 */
2258 #define ICE_AQ_FLAG_VFE BIT(ICE_AQ_FLAG_VFE_S) /* 0x8 */
2259 #define ICE_AQ_FLAG_LB BIT(ICE_AQ_FLAG_LB_S) /* 0x200 */
2260 #define ICE_AQ_FLAG_RD BIT(ICE_AQ_FLAG_RD_S) /* 0x400 */
2261 #define ICE_AQ_FLAG_VFC BIT(ICE_AQ_FLAG_VFC_S) /* 0x800 */
2262 #define ICE_AQ_FLAG_BUF BIT(ICE_AQ_FLAG_BUF_S) /* 0x1000 */
2263 #define ICE_AQ_FLAG_SI BIT(ICE_AQ_FLAG_SI_S) /* 0x2000 */
2264 #define ICE_AQ_FLAG_EI BIT(ICE_AQ_FLAG_EI_S) /* 0x4000 */
2265 #define ICE_AQ_FLAG_FE BIT(ICE_AQ_FLAG_FE_S) /* 0x8000 */
2269 ICE_AQ_RC_OK = 0, /* Success */
2270 ICE_AQ_RC_EPERM = 1, /* Operation not permitted */
2271 ICE_AQ_RC_ENOENT = 2, /* No such element */
2272 ICE_AQ_RC_ESRCH = 3, /* Bad opcode */
2273 ICE_AQ_RC_EINTR = 4, /* Operation interrupted */
2274 ICE_AQ_RC_EIO = 5, /* I/O error */
2275 ICE_AQ_RC_ENXIO = 6, /* No such resource */
2276 ICE_AQ_RC_E2BIG = 7, /* Arg too long */
2277 ICE_AQ_RC_EAGAIN = 8, /* Try again */
2278 ICE_AQ_RC_ENOMEM = 9, /* Out of memory */
2279 ICE_AQ_RC_EACCES = 10, /* Permission denied */
2280 ICE_AQ_RC_EFAULT = 11, /* Bad address */
2281 ICE_AQ_RC_EBUSY = 12, /* Device or resource busy */
2282 ICE_AQ_RC_EEXIST = 13, /* Object already exists */
2283 ICE_AQ_RC_EINVAL = 14, /* Invalid argument */
2284 ICE_AQ_RC_ENOTTY = 15, /* Not a typewriter */
2285 ICE_AQ_RC_ENOSPC = 16, /* No space left or allocation failure */
2286 ICE_AQ_RC_ENOSYS = 17, /* Function not implemented */
2287 ICE_AQ_RC_ERANGE = 18, /* Parameter out of range */
2288 ICE_AQ_RC_EFLUSHED = 19, /* Cmd flushed due to prev cmd error */
2289 ICE_AQ_RC_BAD_ADDR = 20, /* Descriptor contains a bad pointer */
2290 ICE_AQ_RC_EMODE = 21, /* Op not allowed in current dev mode */
2291 ICE_AQ_RC_EFBIG = 22, /* File too big */
2292 ICE_AQ_RC_ESBCOMP = 23, /* SB-IOSF completion unsuccessful */
2293 ICE_AQ_RC_ENOSEC = 24, /* Missing security manifest */
2294 ICE_AQ_RC_EBADSIG = 25, /* Bad RSA signature */
2295 ICE_AQ_RC_ESVN = 26, /* SVN number prohibits this package */
2296 ICE_AQ_RC_EBADMAN = 27, /* Manifest hash mismatch */
2297 ICE_AQ_RC_EBADBUF = 28, /* Buffer hash mismatches manifest */
2300 /* Admin Queue command opcodes */
2301 enum ice_adminq_opc {
2303 ice_aqc_opc_get_ver = 0x0001,
2304 ice_aqc_opc_driver_ver = 0x0002,
2305 ice_aqc_opc_q_shutdown = 0x0003,
2306 ice_aqc_opc_get_exp_err = 0x0005,
2308 /* resource ownership */
2309 ice_aqc_opc_req_res = 0x0008,
2310 ice_aqc_opc_release_res = 0x0009,
2312 /* device/function capabilities */
2313 ice_aqc_opc_list_func_caps = 0x000A,
2314 ice_aqc_opc_list_dev_caps = 0x000B,
2316 /* manage MAC address */
2317 ice_aqc_opc_manage_mac_read = 0x0107,
2318 ice_aqc_opc_manage_mac_write = 0x0108,
2321 ice_aqc_opc_clear_pxe_mode = 0x0110,
2323 ice_aqc_opc_config_no_drop_policy = 0x0112,
2325 /* internal switch commands */
2326 ice_aqc_opc_get_sw_cfg = 0x0200,
2328 /* Alloc/Free/Get Resources */
2329 ice_aqc_opc_get_res_alloc = 0x0204,
2330 ice_aqc_opc_alloc_res = 0x0208,
2331 ice_aqc_opc_free_res = 0x0209,
2332 ice_aqc_opc_get_allocd_res_desc = 0x020A,
2335 ice_aqc_opc_add_vsi = 0x0210,
2336 ice_aqc_opc_update_vsi = 0x0211,
2337 ice_aqc_opc_get_vsi_params = 0x0212,
2338 ice_aqc_opc_free_vsi = 0x0213,
2340 /* Mirroring rules - add/update, delete */
2341 ice_aqc_opc_add_update_mir_rule = 0x0260,
2342 ice_aqc_opc_del_mir_rule = 0x0261,
2344 /* storm configuration */
2345 ice_aqc_opc_set_storm_cfg = 0x0280,
2346 ice_aqc_opc_get_storm_cfg = 0x0281,
2349 /* switch rules population commands */
2350 ice_aqc_opc_add_sw_rules = 0x02A0,
2351 ice_aqc_opc_update_sw_rules = 0x02A1,
2352 ice_aqc_opc_remove_sw_rules = 0x02A2,
2353 ice_aqc_opc_get_sw_rules = 0x02A3,
2354 ice_aqc_opc_clear_pf_cfg = 0x02A4,
2357 ice_aqc_opc_pfc_ignore = 0x0301,
2358 ice_aqc_opc_query_pfc_mode = 0x0302,
2359 ice_aqc_opc_set_pfc_mode = 0x0303,
2360 ice_aqc_opc_set_dcb_params = 0x0306,
2362 /* transmit scheduler commands */
2363 ice_aqc_opc_get_dflt_topo = 0x0400,
2364 ice_aqc_opc_add_sched_elems = 0x0401,
2365 ice_aqc_opc_cfg_sched_elems = 0x0403,
2366 ice_aqc_opc_get_sched_elems = 0x0404,
2367 ice_aqc_opc_move_sched_elems = 0x0408,
2368 ice_aqc_opc_suspend_sched_elems = 0x0409,
2369 ice_aqc_opc_resume_sched_elems = 0x040A,
2370 ice_aqc_opc_query_port_ets = 0x040E,
2371 ice_aqc_opc_delete_sched_elems = 0x040F,
2372 ice_aqc_opc_add_rl_profiles = 0x0410,
2373 ice_aqc_opc_query_rl_profiles = 0x0411,
2374 ice_aqc_opc_query_sched_res = 0x0412,
2375 ice_aqc_opc_query_node_to_root = 0x0413,
2376 ice_aqc_opc_cfg_l2_node_cgd = 0x0414,
2377 ice_aqc_opc_remove_rl_profiles = 0x0415,
2380 ice_aqc_opc_get_phy_caps = 0x0600,
2381 ice_aqc_opc_set_phy_cfg = 0x0601,
2382 ice_aqc_opc_set_mac_cfg = 0x0603,
2383 ice_aqc_opc_restart_an = 0x0605,
2384 ice_aqc_opc_get_link_status = 0x0607,
2385 ice_aqc_opc_set_event_mask = 0x0613,
2386 ice_aqc_opc_set_mac_lb = 0x0620,
2387 ice_aqc_opc_set_port_id_led = 0x06E9,
2388 ice_aqc_opc_get_port_options = 0x06EA,
2389 ice_aqc_opc_set_port_option = 0x06EB,
2390 ice_aqc_opc_set_gpio = 0x06EC,
2391 ice_aqc_opc_get_gpio = 0x06ED,
2394 ice_aqc_opc_nvm_read = 0x0701,
2395 ice_aqc_opc_nvm_erase = 0x0702,
2396 ice_aqc_opc_nvm_update = 0x0703,
2397 ice_aqc_opc_nvm_cfg_read = 0x0704,
2398 ice_aqc_opc_nvm_cfg_write = 0x0705,
2399 ice_aqc_opc_nvm_checksum = 0x0706,
2402 ice_aqc_opc_lldp_get_mib = 0x0A00,
2403 ice_aqc_opc_lldp_set_mib_change = 0x0A01,
2404 ice_aqc_opc_lldp_add_tlv = 0x0A02,
2405 ice_aqc_opc_lldp_update_tlv = 0x0A03,
2406 ice_aqc_opc_lldp_delete_tlv = 0x0A04,
2407 ice_aqc_opc_lldp_stop = 0x0A05,
2408 ice_aqc_opc_lldp_start = 0x0A06,
2409 ice_aqc_opc_get_cee_dcb_cfg = 0x0A07,
2410 ice_aqc_opc_lldp_set_local_mib = 0x0A08,
2411 ice_aqc_opc_lldp_stop_start_specific_agent = 0x0A09,
2414 ice_aqc_opc_set_rss_key = 0x0B02,
2415 ice_aqc_opc_set_rss_lut = 0x0B03,
2416 ice_aqc_opc_get_rss_key = 0x0B04,
2417 ice_aqc_opc_get_rss_lut = 0x0B05,
2419 /* Tx queue handling commands/events */
2420 ice_aqc_opc_add_txqs = 0x0C30,
2421 ice_aqc_opc_dis_txqs = 0x0C31,
2422 ice_aqc_opc_txqs_cleanup = 0x0C31,
2423 ice_aqc_opc_move_recfg_txqs = 0x0C32,
2425 /* package commands */
2426 ice_aqc_opc_download_pkg = 0x0C40,
2427 ice_aqc_opc_upload_section = 0x0C41,
2428 ice_aqc_opc_update_pkg = 0x0C42,
2429 ice_aqc_opc_get_pkg_info_list = 0x0C43,
2433 /* Standalone Commands/Events */
2434 ice_aqc_opc_event_lan_overflow = 0x1001,
2436 /* debug commands */
2437 ice_aqc_opc_fw_logging = 0xFF09,
2438 ice_aqc_opc_fw_logging_info = 0xFF10,
2439 ice_aqc_opc_get_clear_fw_log = 0xFF11
2442 #endif /* _ICE_ADMINQ_CMD_H_ */