1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2001-2018
5 #ifndef _ICE_ADMINQ_CMD_H_
6 #define _ICE_ADMINQ_CMD_H_
8 /* This header file defines the Admin Queue commands, error codes and
9 * descriptor format. It is shared between Firmware and Software.
13 #define ICE_MAX_VSI 768
14 #define ICE_AQC_TOPO_MAX_LEVEL_NUM 0x9
15 #define ICE_AQ_SET_MAC_FRAME_SIZE_MAX 9728
18 struct ice_aqc_generic {
26 /* Get version (direct 0x0001) */
27 struct ice_aqc_get_ver {
42 /* Queue Shutdown (direct 0x0003) */
43 struct ice_aqc_q_shutdown {
44 __le32 driver_unloading;
45 #define ICE_AQC_DRIVER_UNLOADING BIT(0)
52 /* Request resource ownership (direct 0x0008)
53 * Release resource ownership (direct 0x0009)
55 struct ice_aqc_req_res {
57 #define ICE_AQC_RES_ID_NVM 1
58 #define ICE_AQC_RES_ID_SDP 2
59 #define ICE_AQC_RES_ID_CHNG_LOCK 3
60 #define ICE_AQC_RES_ID_GLBL_LOCK 4
62 #define ICE_AQC_RES_ACCESS_READ 1
63 #define ICE_AQC_RES_ACCESS_WRITE 2
65 /* Upon successful completion, FW writes this value and driver is
66 * expected to release resource before timeout. This value is provided
70 #define ICE_AQ_RES_NVM_READ_DFLT_TIMEOUT_MS 3000
71 #define ICE_AQ_RES_NVM_WRITE_DFLT_TIMEOUT_MS 180000
72 #define ICE_AQ_RES_CHNG_LOCK_DFLT_TIMEOUT_MS 1000
73 #define ICE_AQ_RES_GLBL_LOCK_DFLT_TIMEOUT_MS 3000
74 /* For SDP: pin ID of the SDP */
76 /* Status is only used for ICE_AQC_RES_ID_GLBL_LOCK */
78 #define ICE_AQ_RES_GLBL_SUCCESS 0
79 #define ICE_AQ_RES_GLBL_IN_PROG 1
80 #define ICE_AQ_RES_GLBL_DONE 2
85 /* Get function capabilities (indirect 0x000A)
86 * Get device capabilities (indirect 0x000B)
88 struct ice_aqc_list_caps {
98 /* Device/Function buffer entry, repeated per reported capability */
99 struct ice_aqc_list_caps_elem {
101 #define ICE_AQC_CAPS_VALID_FUNCTIONS 0x0005
102 #define ICE_AQC_CAPS_VSI 0x0017
103 #define ICE_AQC_CAPS_RSS 0x0040
104 #define ICE_AQC_CAPS_RXQS 0x0041
105 #define ICE_AQC_CAPS_TXQS 0x0042
106 #define ICE_AQC_CAPS_MSIX 0x0043
107 #define ICE_AQC_CAPS_MAX_MTU 0x0047
111 /* Number of resources described by this capability */
113 /* Only meaningful for some types of resources */
115 /* Only meaningful for some types of resources */
122 /* Manage MAC address, read command - indirect (0x0107)
123 * This struct is also used for the response
125 struct ice_aqc_manage_mac_read {
126 __le16 flags; /* Zeroed by device driver */
127 #define ICE_AQC_MAN_MAC_LAN_ADDR_VALID BIT(4)
128 #define ICE_AQC_MAN_MAC_SAN_ADDR_VALID BIT(5)
129 #define ICE_AQC_MAN_MAC_PORT_ADDR_VALID BIT(6)
130 #define ICE_AQC_MAN_MAC_WOL_ADDR_VALID BIT(7)
131 #define ICE_AQC_MAN_MAC_READ_S 4
132 #define ICE_AQC_MAN_MAC_READ_M (0xF << ICE_AQC_MAN_MAC_READ_S)
135 #define ICE_AQC_MAN_MAC_PORT_NUM_IS_VALID BIT(0)
136 u8 num_addr; /* Used in response */
143 /* Response buffer format for manage MAC read command */
144 struct ice_aqc_manage_mac_read_resp {
147 #define ICE_AQC_MAN_MAC_ADDR_TYPE_LAN 0
148 #define ICE_AQC_MAN_MAC_ADDR_TYPE_WOL 1
149 u8 mac_addr[ETH_ALEN];
153 /* Manage MAC address, write command - direct (0x0108) */
154 struct ice_aqc_manage_mac_write {
157 #define ICE_AQC_MAN_MAC_WR_MC_MAG_EN BIT(0)
158 #define ICE_AQC_MAN_MAC_WR_WOL_LAA_PFR_KEEP BIT(1)
159 #define ICE_AQC_MAN_MAC_WR_S 6
160 #define ICE_AQC_MAN_MAC_WR_M (3 << ICE_AQC_MAN_MAC_WR_S)
161 #define ICE_AQC_MAN_MAC_UPDATE_LAA 0
162 #define ICE_AQC_MAN_MAC_UPDATE_LAA_WOL (BIT(0) << ICE_AQC_MAN_MAC_WR_S)
163 /* High 16 bits of MAC address in big endian order */
165 /* Low 32 bits of MAC address in big endian order */
172 /* Clear PXE Command and response (direct 0x0110) */
173 struct ice_aqc_clear_pxe {
175 #define ICE_AQC_CLEAR_PXE_RX_CNT 0x2
180 /* Configure No-Drop Policy Command (direct 0x0112) */
181 struct ice_aqc_config_no_drop_policy {
183 #define ICE_AQC_FORCE_NO_DROP BIT(0)
187 /* Get switch configuration (0x0200) */
188 struct ice_aqc_get_sw_cfg {
189 /* Reserved for command and copy of request flags for response */
191 /* First desc in case of command and next_elem in case of response
192 * In case of response, if it is not zero, means all the configuration
193 * was not returned and new command shall be sent with this value in
194 * the 'first desc' field
197 /* Reserved for command, only used for response */
205 /* Each entry in the response buffer is of the following type: */
206 struct ice_aqc_get_sw_cfg_resp_elem {
207 /* VSI/Port Number */
209 #define ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_S 0
210 #define ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_M \
211 (0x3FF << ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_S)
212 #define ICE_AQC_GET_SW_CONF_RESP_TYPE_S 14
213 #define ICE_AQC_GET_SW_CONF_RESP_TYPE_M (0x3 << ICE_AQC_GET_SW_CONF_RESP_TYPE_S)
214 #define ICE_AQC_GET_SW_CONF_RESP_PHYS_PORT 0
215 #define ICE_AQC_GET_SW_CONF_RESP_VIRT_PORT 1
216 #define ICE_AQC_GET_SW_CONF_RESP_VSI 2
218 /* SWID VSI/Port belongs to */
221 /* Bit 14..0 : PF/VF number VSI belongs to
222 * Bit 15 : VF indication bit
225 #define ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_S 0
226 #define ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_M \
227 (0x7FFF << ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_S)
228 #define ICE_AQC_GET_SW_CONF_RESP_IS_VF BIT(15)
232 /* The response buffer is as follows. Note that the length of the
233 * elements array varies with the length of the command response.
235 struct ice_aqc_get_sw_cfg_resp {
236 struct ice_aqc_get_sw_cfg_resp_elem elements[1];
241 /* These resource type defines are used for all switch resource
242 * commands where a resource type is required, such as:
243 * Get Resource Allocation command (indirect 0x0204)
244 * Allocate Resources command (indirect 0x0208)
245 * Free Resources command (indirect 0x0209)
246 * Get Allocated Resource Descriptors Command (indirect 0x020A)
248 #define ICE_AQC_RES_TYPE_VEB_COUNTER 0x00
249 #define ICE_AQC_RES_TYPE_VLAN_COUNTER 0x01
250 #define ICE_AQC_RES_TYPE_MIRROR_RULE 0x02
251 #define ICE_AQC_RES_TYPE_VSI_LIST_REP 0x03
252 #define ICE_AQC_RES_TYPE_VSI_LIST_PRUNE 0x04
253 #define ICE_AQC_RES_TYPE_RECIPE 0x05
254 #define ICE_AQC_RES_TYPE_PROFILE 0x06
255 #define ICE_AQC_RES_TYPE_SWID 0x07
256 #define ICE_AQC_RES_TYPE_VSI 0x08
257 #define ICE_AQC_RES_TYPE_FLU 0x09
258 #define ICE_AQC_RES_TYPE_WIDE_TABLE_1 0x0A
259 #define ICE_AQC_RES_TYPE_WIDE_TABLE_2 0x0B
260 #define ICE_AQC_RES_TYPE_WIDE_TABLE_4 0x0C
261 #define ICE_AQC_RES_TYPE_GLOBAL_RSS_HASH 0x20
262 #define ICE_AQC_RES_TYPE_FDIR_COUNTER_BLOCK 0x21
263 #define ICE_AQC_RES_TYPE_FDIR_GUARANTEED_ENTRIES 0x22
264 #define ICE_AQC_RES_TYPE_FDIR_SHARED_ENTRIES 0x23
265 #define ICE_AQC_RES_TYPE_FLEX_DESC_PROG 0x30
266 #define ICE_AQC_RES_TYPE_SWITCH_PROF_BLDR_PROFID 0x48
267 #define ICE_AQC_RES_TYPE_SWITCH_PROF_BLDR_TCAM 0x49
268 #define ICE_AQC_RES_TYPE_ACL_PROF_BLDR_PROFID 0x50
269 #define ICE_AQC_RES_TYPE_ACL_PROF_BLDR_TCAM 0x51
270 #define ICE_AQC_RES_TYPE_FD_PROF_BLDR_PROFID 0x58
271 #define ICE_AQC_RES_TYPE_FD_PROF_BLDR_TCAM 0x59
272 #define ICE_AQC_RES_TYPE_HASH_PROF_BLDR_PROFID 0x60
273 #define ICE_AQC_RES_TYPE_HASH_PROF_BLDR_TCAM 0x61
274 /* Resource types 0x62-67 are reserved for Hash profile builder */
275 #define ICE_AQC_RES_TYPE_QHASH_PROF_BLDR_PROFID 0x68
276 #define ICE_AQC_RES_TYPE_QHASH_PROF_BLDR_TCAM 0x69
278 #define ICE_AQC_RES_TYPE_FLAG_SHARED BIT(7)
279 #define ICE_AQC_RES_TYPE_FLAG_SCAN_BOTTOM BIT(12)
280 #define ICE_AQC_RES_TYPE_FLAG_IGNORE_INDEX BIT(13)
282 #define ICE_AQC_RES_TYPE_FLAG_DEDICATED 0x00
286 /* Allocate Resources command (indirect 0x0208)
287 * Free Resources command (indirect 0x0209)
289 struct ice_aqc_alloc_free_res_cmd {
290 __le16 num_entries; /* Number of Resource entries */
297 /* Resource descriptor */
298 struct ice_aqc_res_elem {
306 /* Buffer for Allocate/Free Resources commands */
307 struct ice_aqc_alloc_free_res_elem {
308 __le16 res_type; /* Types defined above cmd 0x0204 */
309 #define ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_S 8
310 #define ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_M \
311 (0xF << ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_S)
313 struct ice_aqc_res_elem elem[1];
319 /* Add VSI (indirect 0x0210)
320 * Update VSI (indirect 0x0211)
321 * Get VSI (indirect 0x0212)
322 * Free VSI (indirect 0x0213)
324 struct ice_aqc_add_get_update_free_vsi {
326 #define ICE_AQ_VSI_NUM_S 0
327 #define ICE_AQ_VSI_NUM_M (0x03FF << ICE_AQ_VSI_NUM_S)
328 #define ICE_AQ_VSI_IS_VALID BIT(15)
330 #define ICE_AQ_VSI_KEEP_ALLOC 0x1
334 #define ICE_AQ_VSI_TYPE_S 0
335 #define ICE_AQ_VSI_TYPE_M (0x3 << ICE_AQ_VSI_TYPE_S)
336 #define ICE_AQ_VSI_TYPE_VF 0x0
337 #define ICE_AQ_VSI_TYPE_VMDQ2 0x1
338 #define ICE_AQ_VSI_TYPE_PF 0x2
339 #define ICE_AQ_VSI_TYPE_EMP_MNG 0x3
345 /* Response descriptor for:
346 * Add VSI (indirect 0x0210)
347 * Update VSI (indirect 0x0211)
348 * Free VSI (indirect 0x0213)
350 struct ice_aqc_add_update_free_vsi_resp {
360 struct ice_aqc_get_vsi_resp {
363 /* The vsi_flags field uses the ICE_AQ_VSI_TYPE_* defines for values.
364 * These are found above in struct ice_aqc_add_get_update_free_vsi.
374 struct ice_aqc_vsi_props {
375 __le16 valid_sections;
376 #define ICE_AQ_VSI_PROP_SW_VALID BIT(0)
377 #define ICE_AQ_VSI_PROP_SECURITY_VALID BIT(1)
378 #define ICE_AQ_VSI_PROP_VLAN_VALID BIT(2)
379 #define ICE_AQ_VSI_PROP_OUTER_TAG_VALID BIT(3)
380 #define ICE_AQ_VSI_PROP_INGRESS_UP_VALID BIT(4)
381 #define ICE_AQ_VSI_PROP_EGRESS_UP_VALID BIT(5)
382 #define ICE_AQ_VSI_PROP_RXQ_MAP_VALID BIT(6)
383 #define ICE_AQ_VSI_PROP_Q_OPT_VALID BIT(7)
384 #define ICE_AQ_VSI_PROP_OUTER_UP_VALID BIT(8)
385 #define ICE_AQ_VSI_PROP_FLOW_DIR_VALID BIT(11)
386 #define ICE_AQ_VSI_PROP_PASID_VALID BIT(12)
390 #define ICE_AQ_VSI_SW_FLAG_ALLOW_LB BIT(5)
391 #define ICE_AQ_VSI_SW_FLAG_LOCAL_LB BIT(6)
392 #define ICE_AQ_VSI_SW_FLAG_SRC_PRUNE BIT(7)
394 #define ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_S 0
395 #define ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_M \
396 (0xF << ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_S)
397 #define ICE_AQ_VSI_SW_FLAG_RX_VLAN_PRUNE_ENA BIT(0)
398 #define ICE_AQ_VSI_SW_FLAG_LAN_ENA BIT(4)
400 #define ICE_AQ_VSI_SW_VEB_STAT_ID_S 0
401 #define ICE_AQ_VSI_SW_VEB_STAT_ID_M (0x1F << ICE_AQ_VSI_SW_VEB_STAT_ID_S)
402 #define ICE_AQ_VSI_SW_VEB_STAT_ID_VALID BIT(5)
403 /* security section */
405 #define ICE_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD BIT(0)
406 #define ICE_AQ_VSI_SEC_FLAG_ENA_MAC_ANTI_SPOOF BIT(2)
407 #define ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S 4
408 #define ICE_AQ_VSI_SEC_TX_PRUNE_ENA_M (0xF << ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S)
409 #define ICE_AQ_VSI_SEC_TX_VLAN_PRUNE_ENA BIT(0)
412 __le16 pvid; /* VLANS include priority bits */
413 u8 pvlan_reserved[2];
415 #define ICE_AQ_VSI_VLAN_MODE_S 0
416 #define ICE_AQ_VSI_VLAN_MODE_M (0x3 << ICE_AQ_VSI_VLAN_MODE_S)
417 #define ICE_AQ_VSI_VLAN_MODE_UNTAGGED 0x1
418 #define ICE_AQ_VSI_VLAN_MODE_TAGGED 0x2
419 #define ICE_AQ_VSI_VLAN_MODE_ALL 0x3
420 #define ICE_AQ_VSI_PVLAN_INSERT_PVID BIT(2)
421 #define ICE_AQ_VSI_VLAN_EMOD_S 3
422 #define ICE_AQ_VSI_VLAN_EMOD_M (0x3 << ICE_AQ_VSI_VLAN_EMOD_S)
423 #define ICE_AQ_VSI_VLAN_EMOD_STR_BOTH (0x0 << ICE_AQ_VSI_VLAN_EMOD_S)
424 #define ICE_AQ_VSI_VLAN_EMOD_STR_UP (0x1 << ICE_AQ_VSI_VLAN_EMOD_S)
425 #define ICE_AQ_VSI_VLAN_EMOD_STR (0x2 << ICE_AQ_VSI_VLAN_EMOD_S)
426 #define ICE_AQ_VSI_VLAN_EMOD_NOTHING (0x3 << ICE_AQ_VSI_VLAN_EMOD_S)
427 u8 pvlan_reserved2[3];
428 /* ingress egress up sections */
429 __le32 ingress_table; /* bitmap, 3 bits per up */
430 #define ICE_AQ_VSI_UP_TABLE_UP0_S 0
431 #define ICE_AQ_VSI_UP_TABLE_UP0_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP0_S)
432 #define ICE_AQ_VSI_UP_TABLE_UP1_S 3
433 #define ICE_AQ_VSI_UP_TABLE_UP1_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP1_S)
434 #define ICE_AQ_VSI_UP_TABLE_UP2_S 6
435 #define ICE_AQ_VSI_UP_TABLE_UP2_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP2_S)
436 #define ICE_AQ_VSI_UP_TABLE_UP3_S 9
437 #define ICE_AQ_VSI_UP_TABLE_UP3_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP3_S)
438 #define ICE_AQ_VSI_UP_TABLE_UP4_S 12
439 #define ICE_AQ_VSI_UP_TABLE_UP4_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP4_S)
440 #define ICE_AQ_VSI_UP_TABLE_UP5_S 15
441 #define ICE_AQ_VSI_UP_TABLE_UP5_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP5_S)
442 #define ICE_AQ_VSI_UP_TABLE_UP6_S 18
443 #define ICE_AQ_VSI_UP_TABLE_UP6_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP6_S)
444 #define ICE_AQ_VSI_UP_TABLE_UP7_S 21
445 #define ICE_AQ_VSI_UP_TABLE_UP7_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP7_S)
446 __le32 egress_table; /* same defines as for ingress table */
447 /* outer tags section */
450 #define ICE_AQ_VSI_OUTER_TAG_MODE_S 0
451 #define ICE_AQ_VSI_OUTER_TAG_MODE_M (0x3 << ICE_AQ_VSI_OUTER_TAG_MODE_S)
452 #define ICE_AQ_VSI_OUTER_TAG_NOTHING 0x0
453 #define ICE_AQ_VSI_OUTER_TAG_REMOVE 0x1
454 #define ICE_AQ_VSI_OUTER_TAG_COPY 0x2
455 #define ICE_AQ_VSI_OUTER_TAG_TYPE_S 2
456 #define ICE_AQ_VSI_OUTER_TAG_TYPE_M (0x3 << ICE_AQ_VSI_OUTER_TAG_TYPE_S)
457 #define ICE_AQ_VSI_OUTER_TAG_NONE 0x0
458 #define ICE_AQ_VSI_OUTER_TAG_STAG 0x1
459 #define ICE_AQ_VSI_OUTER_TAG_VLAN_8100 0x2
460 #define ICE_AQ_VSI_OUTER_TAG_VLAN_9100 0x3
461 #define ICE_AQ_VSI_OUTER_TAG_INSERT BIT(4)
462 #define ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST BIT(6)
463 u8 outer_tag_reserved;
464 /* queue mapping section */
465 __le16 mapping_flags;
466 #define ICE_AQ_VSI_Q_MAP_CONTIG 0x0
467 #define ICE_AQ_VSI_Q_MAP_NONCONTIG BIT(0)
468 __le16 q_mapping[16];
469 #define ICE_AQ_VSI_Q_S 0
470 #define ICE_AQ_VSI_Q_M (0x7FF << ICE_AQ_VSI_Q_S)
471 __le16 tc_mapping[8];
472 #define ICE_AQ_VSI_TC_Q_OFFSET_S 0
473 #define ICE_AQ_VSI_TC_Q_OFFSET_M (0x7FF << ICE_AQ_VSI_TC_Q_OFFSET_S)
474 #define ICE_AQ_VSI_TC_Q_NUM_S 11
475 #define ICE_AQ_VSI_TC_Q_NUM_M (0xF << ICE_AQ_VSI_TC_Q_NUM_S)
476 /* queueing option section */
478 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_S 0
479 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_M (0x3 << ICE_AQ_VSI_Q_OPT_RSS_LUT_S)
480 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_VSI 0x0
481 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_PF 0x2
482 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_GBL 0x3
483 #define ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_S 2
484 #define ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_M (0xF << ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_S)
485 #define ICE_AQ_VSI_Q_OPT_RSS_HASH_S 6
486 #define ICE_AQ_VSI_Q_OPT_RSS_HASH_M (0x3 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S)
487 #define ICE_AQ_VSI_Q_OPT_RSS_TPLZ (0x0 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S)
488 #define ICE_AQ_VSI_Q_OPT_RSS_SYM_TPLZ (0x1 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S)
489 #define ICE_AQ_VSI_Q_OPT_RSS_XOR (0x2 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S)
490 #define ICE_AQ_VSI_Q_OPT_RSS_JHASH (0x3 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S)
492 #define ICE_AQ_VSI_Q_OPT_TC_OVR_S 0
493 #define ICE_AQ_VSI_Q_OPT_TC_OVR_M (0x1F << ICE_AQ_VSI_Q_OPT_TC_OVR_S)
494 #define ICE_AQ_VSI_Q_OPT_PROF_TC_OVR BIT(7)
496 #define ICE_AQ_VSI_Q_OPT_PE_FLTR_EN BIT(0)
497 u8 q_opt_reserved[3];
498 /* outer up section */
499 __le32 outer_up_table; /* same structure and defines as ingress tbl */
501 __le16 sect_10_reserved;
502 /* flow director section */
504 #define ICE_AQ_VSI_FD_ENABLE BIT(0)
505 #define ICE_AQ_VSI_FD_TX_AUTO_ENABLE BIT(1)
506 #define ICE_AQ_VSI_FD_PROG_ENABLE BIT(3)
507 __le16 max_fd_fltr_dedicated;
508 __le16 max_fd_fltr_shared;
510 #define ICE_AQ_VSI_FD_DEF_Q_S 0
511 #define ICE_AQ_VSI_FD_DEF_Q_M (0x7FF << ICE_AQ_VSI_FD_DEF_Q_S)
512 #define ICE_AQ_VSI_FD_DEF_GRP_S 12
513 #define ICE_AQ_VSI_FD_DEF_GRP_M (0x7 << ICE_AQ_VSI_FD_DEF_GRP_S)
514 __le16 fd_report_opt;
515 #define ICE_AQ_VSI_FD_REPORT_Q_S 0
516 #define ICE_AQ_VSI_FD_REPORT_Q_M (0x7FF << ICE_AQ_VSI_FD_REPORT_Q_S)
517 #define ICE_AQ_VSI_FD_DEF_PRIORITY_S 12
518 #define ICE_AQ_VSI_FD_DEF_PRIORITY_M (0x7 << ICE_AQ_VSI_FD_DEF_PRIORITY_S)
519 #define ICE_AQ_VSI_FD_DEF_DROP BIT(15)
522 #define ICE_AQ_VSI_PASID_ID_S 0
523 #define ICE_AQ_VSI_PASID_ID_M (0xFFFFF << ICE_AQ_VSI_PASID_ID_S)
524 #define ICE_AQ_VSI_PASID_ID_VALID BIT(31)
529 /* Add/update mirror rule - direct (0x0260) */
530 #define ICE_AQC_RULE_ID_VALID_S 7
531 #define ICE_AQC_RULE_ID_VALID_M (0x1 << ICE_AQC_RULE_ID_VALID_S)
532 #define ICE_AQC_RULE_ID_S 0
533 #define ICE_AQC_RULE_ID_M (0x3F << ICE_AQC_RULE_ID_S)
535 /* Following defines to be used while processing caller specified mirror list
538 /* Action: Byte.bit (1.7)
539 * 0 = Remove VSI from mirror rule
540 * 1 = Add VSI to mirror rule
542 #define ICE_AQC_RULE_ACT_S 15
543 #define ICE_AQC_RULE_ACT_M (0x1 << ICE_AQC_RULE_ACT_S)
544 /* Action: 1.2:0.0 = Mirrored VSI */
545 #define ICE_AQC_RULE_MIRRORED_VSI_S 0
546 #define ICE_AQC_RULE_MIRRORED_VSI_M (0x7FF << ICE_AQC_RULE_MIRRORED_VSI_S)
548 /* This is to be used by add/update mirror rule Admin Queue command.
549 * In case of add mirror rule - if rule ID is specified as
550 * INVAL_MIRROR_RULE_ID, new rule ID is allocated from shared pool.
551 * If specified rule_id is valid, then it is used. If specified rule_id
552 * is in use then new mirroring rule is added.
554 #define ICE_INVAL_MIRROR_RULE_ID 0xFFFF
556 struct ice_aqc_add_update_mir_rule {
560 #define ICE_AQC_RULE_TYPE_S 0
561 #define ICE_AQC_RULE_TYPE_M (0x7 << ICE_AQC_RULE_TYPE_S)
562 /* VPORT ingress/egress */
563 #define ICE_AQC_RULE_TYPE_VPORT_INGRESS 0x1
564 #define ICE_AQC_RULE_TYPE_VPORT_EGRESS 0x2
565 /* Physical port ingress mirroring.
566 * All traffic received by this port
568 #define ICE_AQC_RULE_TYPE_PPORT_INGRESS 0x6
569 /* Physical port egress mirroring. All traffic sent by this port */
570 #define ICE_AQC_RULE_TYPE_PPORT_EGRESS 0x7
572 /* Number of mirrored entries.
573 * The values are in the command buffer
577 /* Destination VSI */
583 /* Delete mirror rule - direct(0x0261) */
584 struct ice_aqc_delete_mir_rule {
588 /* Byte.bit: 20.0 = Keep allocation. If set VSI stays part of
589 * the PF allocated resources, otherwise it is returned to the
592 #define ICE_AQC_FLAG_KEEP_ALLOCD_S 0
593 #define ICE_AQC_FLAG_KEEP_ALLOCD_M (0x1 << ICE_AQC_FLAG_KEEP_ALLOCD_S)
599 /* Set/Get storm config - (direct 0x0280, 0x0281) */
600 /* This structure holds get storm configuration response and same structure
601 * is used to perform set_storm_cfg
603 struct ice_aqc_storm_cfg {
604 __le32 bcast_thresh_size;
605 __le32 mcast_thresh_size;
606 /* Bit 18:0 - Traffic upper threshold size
607 * Bit 31:19 - Reserved
609 #define ICE_AQ_THRESHOLD_S 0
610 #define ICE_AQ_THRESHOLD_M (0x7FFFF << ICE_AQ_THRESHOLD_S)
612 __le32 storm_ctrl_ctrl;
613 /* Bit 0: MDIPW - Drop Multicast packets in previous window
614 * Bit 1: MDICW - Drop multicast packets in current window
615 * Bit 2: BDIPW - Drop broadcast packets in previous window
616 * Bit 3: BDICW - Drop broadcast packets in current window
618 #define ICE_AQ_STORM_CTRL_MDIPW_DROP_MULTICAST BIT(0)
619 #define ICE_AQ_STORM_CTRL_MDICW_DROP_MULTICAST BIT(1)
620 #define ICE_AQ_STORM_CTRL_BDIPW_DROP_MULTICAST BIT(2)
621 #define ICE_AQ_STORM_CTRL_BDICW_DROP_MULTICAST BIT(3)
622 /* Bit 7:5 : Reserved */
623 /* Bit 27:8 : Interval - BSC/MSC Time-interval specification: The
624 * interval size for applying ingress broadcast or multicast storm
627 #define ICE_AQ_STORM_BSC_MSC_TIME_INTERVAL_S 8
628 #define ICE_AQ_STORM_BSC_MSC_TIME_INTERVAL_M \
629 (0xFFFFF << ICE_AQ_STORM_BSC_MSC_TIME_INTERVAL_S)
634 #define ICE_MAX_NUM_RECIPES 64
637 /* Add/Update/Remove/Get switch rules (indirect 0x02A0, 0x02A1, 0x02A2, 0x02A3)
639 struct ice_aqc_sw_rules {
640 /* ops: add switch rules, referring the number of rules.
641 * ops: update switch rules, referring the number of filters
642 * ops: remove switch rules, referring the entry index.
643 * ops: get switch rules, referring to the number of filters.
645 __le16 num_rules_fltr_entry_index;
653 /* Add/Update/Get/Remove lookup Rx/Tx command/response entry
654 * This structures describes the lookup rules and associated actions. "index"
655 * is returned as part of a response to a successful Add command, and can be
656 * used to identify the rule for Update/Get/Remove commands.
658 struct ice_sw_rule_lkup_rx_tx {
660 #define ICE_SW_RECIPE_LOGICAL_PORT_FWD 10
661 /* Source port for LOOKUP_RX and source VSI in case of LOOKUP_TX */
665 /* Bit 0:1 - Action type */
666 #define ICE_SINGLE_ACT_TYPE_S 0x00
667 #define ICE_SINGLE_ACT_TYPE_M (0x3 << ICE_SINGLE_ACT_TYPE_S)
669 /* Bit 2 - Loop back enable
672 #define ICE_SINGLE_ACT_LB_ENABLE BIT(2)
673 #define ICE_SINGLE_ACT_LAN_ENABLE BIT(3)
675 /* Action type = 0 - Forward to VSI or VSI list */
676 #define ICE_SINGLE_ACT_VSI_FORWARDING 0x0
678 #define ICE_SINGLE_ACT_VSI_ID_S 4
679 #define ICE_SINGLE_ACT_VSI_ID_M (0x3FF << ICE_SINGLE_ACT_VSI_ID_S)
680 #define ICE_SINGLE_ACT_VSI_LIST_ID_S 4
681 #define ICE_SINGLE_ACT_VSI_LIST_ID_M (0x3FF << ICE_SINGLE_ACT_VSI_LIST_ID_S)
682 /* This bit needs to be set if action is forward to VSI list */
683 #define ICE_SINGLE_ACT_VSI_LIST BIT(14)
684 #define ICE_SINGLE_ACT_VALID_BIT BIT(17)
685 #define ICE_SINGLE_ACT_DROP BIT(18)
687 /* Action type = 1 - Forward to Queue of Queue group */
688 #define ICE_SINGLE_ACT_TO_Q 0x1
689 #define ICE_SINGLE_ACT_Q_INDEX_S 4
690 #define ICE_SINGLE_ACT_Q_INDEX_M (0x7FF << ICE_SINGLE_ACT_Q_INDEX_S)
691 #define ICE_SINGLE_ACT_Q_REGION_S 15
692 #define ICE_SINGLE_ACT_Q_REGION_M (0x7 << ICE_SINGLE_ACT_Q_REGION_S)
693 #define ICE_SINGLE_ACT_Q_PRIORITY BIT(18)
695 /* Action type = 2 - Prune */
696 #define ICE_SINGLE_ACT_PRUNE 0x2
697 #define ICE_SINGLE_ACT_EGRESS BIT(15)
698 #define ICE_SINGLE_ACT_INGRESS BIT(16)
699 #define ICE_SINGLE_ACT_PRUNET BIT(17)
700 /* Bit 18 should be set to 0 for this action */
702 /* Action type = 2 - Pointer */
703 #define ICE_SINGLE_ACT_PTR 0x2
704 #define ICE_SINGLE_ACT_PTR_VAL_S 4
705 #define ICE_SINGLE_ACT_PTR_VAL_M (0x1FFF << ICE_SINGLE_ACT_PTR_VAL_S)
706 /* Bit 18 should be set to 1 */
707 #define ICE_SINGLE_ACT_PTR_BIT BIT(18)
709 /* Action type = 3 - Other actions. Last two bits
710 * are other action identifier
712 #define ICE_SINGLE_ACT_OTHER_ACTS 0x3
713 #define ICE_SINGLE_OTHER_ACT_IDENTIFIER_S 17
714 #define ICE_SINGLE_OTHER_ACT_IDENTIFIER_M \
715 (0x3 << \ ICE_SINGLE_OTHER_ACT_IDENTIFIER_S)
717 /* Bit 17:18 - Defines other actions */
718 /* Other action = 0 - Mirror VSI */
719 #define ICE_SINGLE_OTHER_ACT_MIRROR 0
720 #define ICE_SINGLE_ACT_MIRROR_VSI_ID_S 4
721 #define ICE_SINGLE_ACT_MIRROR_VSI_ID_M \
722 (0x3FF << ICE_SINGLE_ACT_MIRROR_VSI_ID_S)
724 /* Other action = 3 - Set Stat count */
725 #define ICE_SINGLE_OTHER_ACT_STAT_COUNT 3
726 #define ICE_SINGLE_ACT_STAT_COUNT_INDEX_S 4
727 #define ICE_SINGLE_ACT_STAT_COUNT_INDEX_M \
728 (0x7F << ICE_SINGLE_ACT_STAT_COUNT_INDEX_S)
730 __le16 index; /* The index of the rule in the lookup table */
731 /* Length and values of the header to be matched per recipe or
740 /* Add/Update/Remove large action command/response entry
741 * "index" is returned as part of a response to a successful Add command, and
742 * can be used to identify the action for Update/Get/Remove commands.
744 struct ice_sw_rule_lg_act {
745 __le16 index; /* Index in large action table */
747 __le32 act[1]; /* array of size for actions */
748 /* Max number of large actions */
749 #define ICE_MAX_LG_ACT 4
750 /* Bit 0:1 - Action type */
751 #define ICE_LG_ACT_TYPE_S 0
752 #define ICE_LG_ACT_TYPE_M (0x7 << ICE_LG_ACT_TYPE_S)
754 /* Action type = 0 - Forward to VSI or VSI list */
755 #define ICE_LG_ACT_VSI_FORWARDING 0
756 #define ICE_LG_ACT_VSI_ID_S 3
757 #define ICE_LG_ACT_VSI_ID_M (0x3FF << ICE_LG_ACT_VSI_ID_S)
758 #define ICE_LG_ACT_VSI_LIST_ID_S 3
759 #define ICE_LG_ACT_VSI_LIST_ID_M (0x3FF << ICE_LG_ACT_VSI_LIST_ID_S)
760 /* This bit needs to be set if action is forward to VSI list */
761 #define ICE_LG_ACT_VSI_LIST BIT(13)
763 #define ICE_LG_ACT_VALID_BIT BIT(16)
765 /* Action type = 1 - Forward to Queue of Queue group */
766 #define ICE_LG_ACT_TO_Q 0x1
767 #define ICE_LG_ACT_Q_INDEX_S 3
768 #define ICE_LG_ACT_Q_INDEX_M (0x7FF << ICE_LG_ACT_Q_INDEX_S)
769 #define ICE_LG_ACT_Q_REGION_S 14
770 #define ICE_LG_ACT_Q_REGION_M (0x7 << ICE_LG_ACT_Q_REGION_S)
771 #define ICE_LG_ACT_Q_PRIORITY_SET BIT(17)
773 /* Action type = 2 - Prune */
774 #define ICE_LG_ACT_PRUNE 0x2
775 #define ICE_LG_ACT_EGRESS BIT(14)
776 #define ICE_LG_ACT_INGRESS BIT(15)
777 #define ICE_LG_ACT_PRUNET BIT(16)
779 /* Action type = 3 - Mirror VSI */
780 #define ICE_LG_OTHER_ACT_MIRROR 0x3
781 #define ICE_LG_ACT_MIRROR_VSI_ID_S 3
782 #define ICE_LG_ACT_MIRROR_VSI_ID_M (0x3FF << ICE_LG_ACT_MIRROR_VSI_ID_S)
784 /* Action type = 5 - Generic Value */
785 #define ICE_LG_ACT_GENERIC 0x5
786 #define ICE_LG_ACT_GENERIC_VALUE_S 3
787 #define ICE_LG_ACT_GENERIC_VALUE_M (0xFFFF << ICE_LG_ACT_GENERIC_VALUE_S)
788 #define ICE_LG_ACT_GENERIC_OFFSET_S 19
789 #define ICE_LG_ACT_GENERIC_OFFSET_M (0x7 << ICE_LG_ACT_GENERIC_OFFSET_S)
790 #define ICE_LG_ACT_GENERIC_PRIORITY_S 22
791 #define ICE_LG_ACT_GENERIC_PRIORITY_M (0x7 << ICE_LG_ACT_GENERIC_PRIORITY_S)
792 #define ICE_LG_ACT_GENERIC_OFF_RX_DESC_PROF_IDX 7
794 /* Action = 7 - Set Stat count */
795 #define ICE_LG_ACT_STAT_COUNT 0x7
796 #define ICE_LG_ACT_STAT_COUNT_S 3
797 #define ICE_LG_ACT_STAT_COUNT_M (0x7F << ICE_LG_ACT_STAT_COUNT_S)
801 /* Add/Update/Remove VSI list command/response entry
802 * "index" is returned as part of a response to a successful Add command, and
803 * can be used to identify the VSI list for Update/Get/Remove commands.
805 struct ice_sw_rule_vsi_list {
806 __le16 index; /* Index of VSI/Prune list */
808 __le16 vsi[1]; /* Array of number_vsi VSI numbers */
813 /* Query VSI list command/response entry */
814 struct ice_sw_rule_vsi_list_query {
816 ice_declare_bitmap(vsi_list, ICE_MAX_VSI);
822 /* Add switch rule response:
823 * Content of return buffer is same as the input buffer. The status field and
824 * LUT index are updated as part of the response
826 struct ice_aqc_sw_rules_elem {
827 __le16 type; /* Switch rule type, one of T_... */
828 #define ICE_AQC_SW_RULES_T_LKUP_RX 0x0
829 #define ICE_AQC_SW_RULES_T_LKUP_TX 0x1
830 #define ICE_AQC_SW_RULES_T_LG_ACT 0x2
831 #define ICE_AQC_SW_RULES_T_VSI_LIST_SET 0x3
832 #define ICE_AQC_SW_RULES_T_VSI_LIST_CLEAR 0x4
833 #define ICE_AQC_SW_RULES_T_PRUNE_LIST_SET 0x5
834 #define ICE_AQC_SW_RULES_T_PRUNE_LIST_CLEAR 0x6
837 struct ice_sw_rule_lkup_rx_tx lkup_tx_rx;
838 struct ice_sw_rule_lg_act lg_act;
839 struct ice_sw_rule_vsi_list vsi_list;
840 struct ice_sw_rule_vsi_list_query vsi_list_query;
848 /* Get Default Topology (indirect 0x0400) */
849 struct ice_aqc_get_topo {
859 /* Update TSE (indirect 0x0403)
860 * Get TSE (indirect 0x0404)
861 * Add TSE (indirect 0x0401)
862 * Delete TSE (indirect 0x040F)
863 * Move TSE (indirect 0x0408)
864 * Suspend Nodes (indirect 0x0409)
865 * Resume Nodes (indirect 0x040A)
867 struct ice_aqc_sched_elem_cmd {
868 __le16 num_elem_req; /* Used by commands */
869 __le16 num_elem_resp; /* Used by responses */
876 /* This is the buffer for:
877 * Suspend Nodes (indirect 0x0409)
878 * Resume Nodes (indirect 0x040A)
880 struct ice_aqc_suspend_resume_elem {
885 struct ice_aqc_txsched_move_grp_info_hdr {
886 __le32 src_parent_teid;
887 __le32 dest_parent_teid;
893 struct ice_aqc_move_elem {
894 struct ice_aqc_txsched_move_grp_info_hdr hdr;
899 struct ice_aqc_elem_info_bw {
900 __le16 bw_profile_idx;
905 struct ice_aqc_txsched_elem {
906 u8 elem_type; /* Special field, reserved for some aq calls */
907 #define ICE_AQC_ELEM_TYPE_UNDEFINED 0x0
908 #define ICE_AQC_ELEM_TYPE_ROOT_PORT 0x1
909 #define ICE_AQC_ELEM_TYPE_TC 0x2
910 #define ICE_AQC_ELEM_TYPE_SE_GENERIC 0x3
911 #define ICE_AQC_ELEM_TYPE_ENTRY_POINT 0x4
912 #define ICE_AQC_ELEM_TYPE_LEAF 0x5
913 #define ICE_AQC_ELEM_TYPE_SE_PADDED 0x6
915 #define ICE_AQC_ELEM_VALID_GENERIC BIT(0)
916 #define ICE_AQC_ELEM_VALID_CIR BIT(1)
917 #define ICE_AQC_ELEM_VALID_EIR BIT(2)
918 #define ICE_AQC_ELEM_VALID_SHARED BIT(3)
920 #define ICE_AQC_ELEM_GENERIC_MODE_M 0x1
921 #define ICE_AQC_ELEM_GENERIC_PRIO_S 0x1
922 #define ICE_AQC_ELEM_GENERIC_PRIO_M (0x7 << ICE_AQC_ELEM_GENERIC_PRIO_S)
923 #define ICE_AQC_ELEM_GENERIC_SP_S 0x4
924 #define ICE_AQC_ELEM_GENERIC_SP_M (0x1 << ICE_AQC_ELEM_GENERIC_SP_S)
925 #define ICE_AQC_ELEM_GENERIC_ADJUST_VAL_S 0x5
926 #define ICE_AQC_ELEM_GENERIC_ADJUST_VAL_M \
927 (0x3 << ICE_AQC_ELEM_GENERIC_ADJUST_VAL_S)
928 u8 flags; /* Special field, reserved for some aq calls */
929 #define ICE_AQC_ELEM_FLAG_SUSPEND_M 0x1
930 struct ice_aqc_elem_info_bw cir_bw;
931 struct ice_aqc_elem_info_bw eir_bw;
937 struct ice_aqc_txsched_elem_data {
940 struct ice_aqc_txsched_elem data;
944 struct ice_aqc_txsched_topo_grp_info_hdr {
951 struct ice_aqc_add_elem {
952 struct ice_aqc_txsched_topo_grp_info_hdr hdr;
953 struct ice_aqc_txsched_elem_data generic[1];
957 struct ice_aqc_conf_elem {
958 struct ice_aqc_txsched_elem_data generic[1];
962 struct ice_aqc_get_elem {
963 struct ice_aqc_txsched_elem_data generic[1];
967 struct ice_aqc_get_topo_elem {
968 struct ice_aqc_txsched_topo_grp_info_hdr hdr;
969 struct ice_aqc_txsched_elem_data
970 generic[ICE_AQC_TOPO_MAX_LEVEL_NUM];
974 struct ice_aqc_delete_elem {
975 struct ice_aqc_txsched_topo_grp_info_hdr hdr;
981 /* Rate limiting profile for
982 * Add RL profile (indirect 0x0410)
983 * Query RL profile (indirect 0x0411)
984 * Remove RL profile (indirect 0x0415)
985 * These indirect commands acts on single or multiple
986 * RL profiles with specified data.
988 struct ice_aqc_rl_profile {
990 __le16 num_processed; /* Only for response. Reserved in Command. */
997 struct ice_aqc_rl_profile_elem {
1000 #define ICE_AQC_RL_PROFILE_TYPE_S 0x0
1001 #define ICE_AQC_RL_PROFILE_TYPE_M (0x3 << ICE_AQC_RL_PROFILE_TYPE_S)
1002 #define ICE_AQC_RL_PROFILE_TYPE_CIR 0
1003 #define ICE_AQC_RL_PROFILE_TYPE_EIR 1
1004 #define ICE_AQC_RL_PROFILE_TYPE_SRL 2
1005 /* The following flag is used for Query RL Profile Data */
1006 #define ICE_AQC_RL_PROFILE_INVAL_S 0x7
1007 #define ICE_AQC_RL_PROFILE_INVAL_M (0x1 << ICE_AQC_RL_PROFILE_INVAL_S)
1010 __le16 max_burst_size;
1012 __le16 wake_up_calc;
1017 struct ice_aqc_rl_profile_generic_elem {
1018 struct ice_aqc_rl_profile_elem generic[1];
1023 /* Configure L2 Node CGD (indirect 0x0414)
1024 * This indirect command allows configuring a congestion domain for given L2
1025 * node TEIDs in the scheduler topology.
1027 struct ice_aqc_cfg_l2_node_cgd {
1028 __le16 num_l2_nodes;
1035 struct ice_aqc_cfg_l2_node_cgd_elem {
1042 struct ice_aqc_cfg_l2_node_cgd_data {
1043 struct ice_aqc_cfg_l2_node_cgd_elem elem[1];
1047 /* Query Scheduler Resource Allocation (indirect 0x0412)
1048 * This indirect command retrieves the scheduler resources allocated by
1049 * EMP Firmware to the given PF.
1051 struct ice_aqc_query_txsched_res {
1058 struct ice_aqc_generic_sched_props {
1060 __le16 logical_levels;
1061 u8 flattening_bitmap;
1070 struct ice_aqc_layer_props {
1073 __le16 max_device_nodes;
1074 __le16 max_pf_nodes;
1076 __le16 max_sibl_grp_sz;
1077 __le16 max_cir_rl_profiles;
1078 __le16 max_eir_rl_profiles;
1079 __le16 max_srl_profiles;
1084 struct ice_aqc_query_txsched_res_resp {
1085 struct ice_aqc_generic_sched_props sched_props;
1086 struct ice_aqc_layer_props layer_props[ICE_AQC_TOPO_MAX_LEVEL_NUM];
1090 /* Query Node to Root Topology (indirect 0x0413)
1091 * This command uses ice_aqc_get_elem as its data buffer.
1093 struct ice_aqc_query_node_to_root {
1095 __le32 num_nodes; /* Response only */
1101 /* Get PHY capabilities (indirect 0x0600) */
1102 struct ice_aqc_get_phy_caps {
1106 /* 18.0 - Report qualified modules */
1107 #define ICE_AQC_GET_PHY_RQM BIT(0)
1108 /* 18.1 - 18.2 : Report mode
1109 * 00b - Report NVM capabilities
1110 * 01b - Report topology capabilities
1111 * 10b - Report SW configured
1113 #define ICE_AQC_REPORT_MODE_S 1
1114 #define ICE_AQC_REPORT_MODE_M (3 << ICE_AQC_REPORT_MODE_S)
1115 #define ICE_AQC_REPORT_NVM_CAP 0
1116 #define ICE_AQC_REPORT_TOPO_CAP BIT(1)
1117 #define ICE_AQC_REPORT_SW_CFG BIT(2)
1124 /* This is #define of PHY type (Extended):
1125 * The first set of defines is for phy_type_low.
1127 #define ICE_PHY_TYPE_LOW_100BASE_TX BIT_ULL(0)
1128 #define ICE_PHY_TYPE_LOW_100M_SGMII BIT_ULL(1)
1129 #define ICE_PHY_TYPE_LOW_1000BASE_T BIT_ULL(2)
1130 #define ICE_PHY_TYPE_LOW_1000BASE_SX BIT_ULL(3)
1131 #define ICE_PHY_TYPE_LOW_1000BASE_LX BIT_ULL(4)
1132 #define ICE_PHY_TYPE_LOW_1000BASE_KX BIT_ULL(5)
1133 #define ICE_PHY_TYPE_LOW_1G_SGMII BIT_ULL(6)
1134 #define ICE_PHY_TYPE_LOW_2500BASE_T BIT_ULL(7)
1135 #define ICE_PHY_TYPE_LOW_2500BASE_X BIT_ULL(8)
1136 #define ICE_PHY_TYPE_LOW_2500BASE_KX BIT_ULL(9)
1137 #define ICE_PHY_TYPE_LOW_5GBASE_T BIT_ULL(10)
1138 #define ICE_PHY_TYPE_LOW_5GBASE_KR BIT_ULL(11)
1139 #define ICE_PHY_TYPE_LOW_10GBASE_T BIT_ULL(12)
1140 #define ICE_PHY_TYPE_LOW_10G_SFI_DA BIT_ULL(13)
1141 #define ICE_PHY_TYPE_LOW_10GBASE_SR BIT_ULL(14)
1142 #define ICE_PHY_TYPE_LOW_10GBASE_LR BIT_ULL(15)
1143 #define ICE_PHY_TYPE_LOW_10GBASE_KR_CR1 BIT_ULL(16)
1144 #define ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC BIT_ULL(17)
1145 #define ICE_PHY_TYPE_LOW_10G_SFI_C2C BIT_ULL(18)
1146 #define ICE_PHY_TYPE_LOW_25GBASE_T BIT_ULL(19)
1147 #define ICE_PHY_TYPE_LOW_25GBASE_CR BIT_ULL(20)
1148 #define ICE_PHY_TYPE_LOW_25GBASE_CR_S BIT_ULL(21)
1149 #define ICE_PHY_TYPE_LOW_25GBASE_CR1 BIT_ULL(22)
1150 #define ICE_PHY_TYPE_LOW_25GBASE_SR BIT_ULL(23)
1151 #define ICE_PHY_TYPE_LOW_25GBASE_LR BIT_ULL(24)
1152 #define ICE_PHY_TYPE_LOW_25GBASE_KR BIT_ULL(25)
1153 #define ICE_PHY_TYPE_LOW_25GBASE_KR_S BIT_ULL(26)
1154 #define ICE_PHY_TYPE_LOW_25GBASE_KR1 BIT_ULL(27)
1155 #define ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC BIT_ULL(28)
1156 #define ICE_PHY_TYPE_LOW_25G_AUI_C2C BIT_ULL(29)
1157 #define ICE_PHY_TYPE_LOW_40GBASE_CR4 BIT_ULL(30)
1158 #define ICE_PHY_TYPE_LOW_40GBASE_SR4 BIT_ULL(31)
1159 #define ICE_PHY_TYPE_LOW_40GBASE_LR4 BIT_ULL(32)
1160 #define ICE_PHY_TYPE_LOW_40GBASE_KR4 BIT_ULL(33)
1161 #define ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC BIT_ULL(34)
1162 #define ICE_PHY_TYPE_LOW_40G_XLAUI BIT_ULL(35)
1163 #define ICE_PHY_TYPE_LOW_50GBASE_CR2 BIT_ULL(36)
1164 #define ICE_PHY_TYPE_LOW_50GBASE_SR2 BIT_ULL(37)
1165 #define ICE_PHY_TYPE_LOW_50GBASE_LR2 BIT_ULL(38)
1166 #define ICE_PHY_TYPE_LOW_50GBASE_KR2 BIT_ULL(39)
1167 #define ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC BIT_ULL(40)
1168 #define ICE_PHY_TYPE_LOW_50G_LAUI2 BIT_ULL(41)
1169 #define ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC BIT_ULL(42)
1170 #define ICE_PHY_TYPE_LOW_50G_AUI2 BIT_ULL(43)
1171 #define ICE_PHY_TYPE_LOW_50GBASE_CP BIT_ULL(44)
1172 #define ICE_PHY_TYPE_LOW_50GBASE_SR BIT_ULL(45)
1173 #define ICE_PHY_TYPE_LOW_50GBASE_FR BIT_ULL(46)
1174 #define ICE_PHY_TYPE_LOW_50GBASE_LR BIT_ULL(47)
1175 #define ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4 BIT_ULL(48)
1176 #define ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC BIT_ULL(49)
1177 #define ICE_PHY_TYPE_LOW_50G_AUI1 BIT_ULL(50)
1178 #define ICE_PHY_TYPE_LOW_100GBASE_CR4 BIT_ULL(51)
1179 #define ICE_PHY_TYPE_LOW_100GBASE_SR4 BIT_ULL(52)
1180 #define ICE_PHY_TYPE_LOW_100GBASE_LR4 BIT_ULL(53)
1181 #define ICE_PHY_TYPE_LOW_100GBASE_KR4 BIT_ULL(54)
1182 #define ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC BIT_ULL(55)
1183 #define ICE_PHY_TYPE_LOW_100G_CAUI4 BIT_ULL(56)
1184 #define ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC BIT_ULL(57)
1185 #define ICE_PHY_TYPE_LOW_100G_AUI4 BIT_ULL(58)
1186 #define ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4 BIT_ULL(59)
1187 #define ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4 BIT_ULL(60)
1188 #define ICE_PHY_TYPE_LOW_100GBASE_CP2 BIT_ULL(61)
1189 #define ICE_PHY_TYPE_LOW_100GBASE_SR2 BIT_ULL(62)
1190 #define ICE_PHY_TYPE_LOW_100GBASE_DR BIT_ULL(63)
1191 #define ICE_PHY_TYPE_LOW_MAX_INDEX 63
1192 /* The second set of defines is for phy_type_high. */
1193 #define ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4 BIT_ULL(0)
1194 #define ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC BIT_ULL(1)
1195 #define ICE_PHY_TYPE_HIGH_100G_CAUI2 BIT_ULL(2)
1196 #define ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC BIT_ULL(3)
1197 #define ICE_PHY_TYPE_HIGH_100G_AUI2 BIT_ULL(4)
1198 #define ICE_PHY_TYPE_HIGH_MAX_INDEX 19
1200 struct ice_aqc_get_phy_caps_data {
1201 __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */
1202 __le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */
1204 #define ICE_AQC_PHY_EN_TX_LINK_PAUSE BIT(0)
1205 #define ICE_AQC_PHY_EN_RX_LINK_PAUSE BIT(1)
1206 #define ICE_AQC_PHY_LOW_POWER_MODE BIT(2)
1207 #define ICE_AQC_PHY_EN_LINK BIT(3)
1208 #define ICE_AQC_PHY_AN_MODE BIT(4)
1209 #define ICE_AQC_PHY_EN_MOD_QUAL BIT(5)
1210 #define ICE_AQC_PHY_EN_LESM BIT(6)
1211 #define ICE_AQC_PHY_EN_AUTO_FEC BIT(7)
1212 #define ICE_AQC_PHY_CAPS_MASK MAKEMASK(0xff, 0)
1214 #define ICE_AQC_PHY_EN_D3COLD_LOW_POWER_AUTONEG BIT(0)
1216 #define ICE_AQC_PHY_EEE_EN_100BASE_TX BIT(0)
1217 #define ICE_AQC_PHY_EEE_EN_1000BASE_T BIT(1)
1218 #define ICE_AQC_PHY_EEE_EN_10GBASE_T BIT(2)
1219 #define ICE_AQC_PHY_EEE_EN_1000BASE_KX BIT(3)
1220 #define ICE_AQC_PHY_EEE_EN_10GBASE_KR BIT(4)
1221 #define ICE_AQC_PHY_EEE_EN_25GBASE_KR BIT(5)
1222 #define ICE_AQC_PHY_EEE_EN_40GBASE_KR4 BIT(6)
1223 #define ICE_AQC_PHY_EEE_EN_50GBASE_KR2 BIT(7)
1224 #define ICE_AQC_PHY_EEE_EN_50GBASE_KR_PAM4 BIT(8)
1225 #define ICE_AQC_PHY_EEE_EN_100GBASE_KR4 BIT(9)
1226 #define ICE_AQC_PHY_EEE_EN_100GBASE_KR2_PAM4 BIT(10)
1228 u8 phy_id_oui[4]; /* PHY/Module ID connected on the port */
1230 u8 link_fec_options;
1231 #define ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN BIT(0)
1232 #define ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ BIT(1)
1233 #define ICE_AQC_PHY_FEC_25G_RS_528_REQ BIT(2)
1234 #define ICE_AQC_PHY_FEC_25G_KR_REQ BIT(3)
1235 #define ICE_AQC_PHY_FEC_25G_RS_544_REQ BIT(4)
1236 #define ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN BIT(6)
1237 #define ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN BIT(7)
1238 #define ICE_AQC_PHY_FEC_MASK MAKEMASK(0xdf, 0)
1239 u8 extended_compliance_code;
1240 #define ICE_MODULE_TYPE_TOTAL_BYTE 3
1241 u8 module_type[ICE_MODULE_TYPE_TOTAL_BYTE];
1242 #define ICE_AQC_MOD_TYPE_BYTE0_SFP_PLUS 0xA0
1243 #define ICE_AQC_MOD_TYPE_BYTE0_QSFP_PLUS 0x80
1244 #define ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_PASSIVE BIT(0)
1245 #define ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_ACTIVE BIT(1)
1246 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_SR BIT(4)
1247 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_LR BIT(5)
1248 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_LRM BIT(6)
1249 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_ER BIT(7)
1250 #define ICE_AQC_MOD_TYPE_BYTE2_SFP_PLUS 0xA0
1251 #define ICE_AQC_MOD_TYPE_BYTE2_QSFP_PLUS 0x86
1252 u8 qualified_module_count;
1253 #define ICE_AQC_QUAL_MOD_COUNT_MAX 16
1260 } qual_modules[ICE_AQC_QUAL_MOD_COUNT_MAX];
1264 /* Set PHY capabilities (direct 0x0601)
1265 * NOTE: This command must be followed by setup link and restart auto-neg
1267 struct ice_aqc_set_phy_cfg {
1275 /* Set PHY config command data structure */
1276 struct ice_aqc_set_phy_cfg_data {
1277 __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */
1278 __le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */
1280 #define ICE_AQ_PHY_ENA_TX_PAUSE_ABILITY BIT(0)
1281 #define ICE_AQ_PHY_ENA_RX_PAUSE_ABILITY BIT(1)
1282 #define ICE_AQ_PHY_ENA_LOW_POWER BIT(2)
1283 #define ICE_AQ_PHY_ENA_LINK BIT(3)
1284 #define ICE_AQ_PHY_ENA_AUTO_LINK_UPDT BIT(5)
1285 #define ICE_AQ_PHY_ENA_LESM BIT(6)
1286 #define ICE_AQ_PHY_ENA_AUTO_FEC BIT(7)
1288 __le16 eee_cap; /* Value from ice_aqc_get_phy_caps */
1290 u8 link_fec_opt; /* Use defines from ice_aqc_get_phy_caps */
1295 /* Set MAC Config command data structure (direct 0x0603) */
1296 struct ice_aqc_set_mac_cfg {
1297 __le16 max_frame_size;
1299 #define ICE_AQ_SET_MAC_PACE_S 3
1300 #define ICE_AQ_SET_MAC_PACE_M (0xF << ICE_AQ_SET_MAC_PACE_S)
1301 #define ICE_AQ_SET_MAC_PACE_TYPE_M BIT(7)
1302 #define ICE_AQ_SET_MAC_PACE_TYPE_RATE 0
1303 #define ICE_AQ_SET_MAC_PACE_TYPE_FIXED ICE_AQ_SET_MAC_PACE_TYPE_M
1305 __le16 tx_tmr_value;
1306 __le16 fc_refresh_threshold;
1308 #define ICE_AQ_SET_MAC_AUTO_DROP_MASK BIT(0)
1309 #define ICE_AQ_SET_MAC_AUTO_DROP_NONE 0
1310 #define ICE_AQ_SET_MAC_AUTO_DROP_BLOCKING_PKTS BIT(0)
1315 /* Restart AN command data structure (direct 0x0605)
1316 * Also used for response, with only the lport_num field present.
1318 struct ice_aqc_restart_an {
1322 #define ICE_AQC_RESTART_AN_LINK_RESTART BIT(1)
1323 #define ICE_AQC_RESTART_AN_LINK_ENABLE BIT(2)
1328 /* Get link status (indirect 0x0607), also used for Link Status Event */
1329 struct ice_aqc_get_link_status {
1333 #define ICE_AQ_LSE_M 0x3
1334 #define ICE_AQ_LSE_NOP 0x0
1335 #define ICE_AQ_LSE_DIS 0x2
1336 #define ICE_AQ_LSE_ENA 0x3
1337 /* only response uses this flag */
1338 #define ICE_AQ_LSE_IS_ENABLED 0x1
1345 /* Get link status response data structure, also used for Link Status Event */
1346 struct ice_aqc_get_link_status_data {
1347 u8 topo_media_conflict;
1348 #define ICE_AQ_LINK_TOPO_CONFLICT BIT(0)
1349 #define ICE_AQ_LINK_MEDIA_CONFLICT BIT(1)
1350 #define ICE_AQ_LINK_TOPO_CORRUPT BIT(2)
1353 #define ICE_AQ_LINK_UP BIT(0) /* Link Status */
1354 #define ICE_AQ_LINK_FAULT BIT(1)
1355 #define ICE_AQ_LINK_FAULT_TX BIT(2)
1356 #define ICE_AQ_LINK_FAULT_RX BIT(3)
1357 #define ICE_AQ_LINK_FAULT_REMOTE BIT(4)
1358 #define ICE_AQ_LINK_UP_PORT BIT(5) /* External Port Link Status */
1359 #define ICE_AQ_MEDIA_AVAILABLE BIT(6)
1360 #define ICE_AQ_SIGNAL_DETECT BIT(7)
1362 #define ICE_AQ_AN_COMPLETED BIT(0)
1363 #define ICE_AQ_LP_AN_ABILITY BIT(1)
1364 #define ICE_AQ_PD_FAULT BIT(2) /* Parallel Detection Fault */
1365 #define ICE_AQ_FEC_EN BIT(3)
1366 #define ICE_AQ_PHY_LOW_POWER BIT(4) /* Low Power State */
1367 #define ICE_AQ_LINK_PAUSE_TX BIT(5)
1368 #define ICE_AQ_LINK_PAUSE_RX BIT(6)
1369 #define ICE_AQ_QUALIFIED_MODULE BIT(7)
1371 #define ICE_AQ_LINK_PHY_TEMP_ALARM BIT(0)
1372 #define ICE_AQ_LINK_EXCESSIVE_ERRORS BIT(1) /* Excessive Link Errors */
1373 /* Port Tx Suspended */
1374 #define ICE_AQ_LINK_TX_S 2
1375 #define ICE_AQ_LINK_TX_M (0x03 << ICE_AQ_LINK_TX_S)
1376 #define ICE_AQ_LINK_TX_ACTIVE 0
1377 #define ICE_AQ_LINK_TX_DRAINED 1
1378 #define ICE_AQ_LINK_TX_FLUSHED 3
1380 __le16 max_frame_size;
1382 #define ICE_AQ_LINK_25G_KR_FEC_EN BIT(0)
1383 #define ICE_AQ_LINK_25G_RS_528_FEC_EN BIT(1)
1384 #define ICE_AQ_LINK_25G_RS_544_FEC_EN BIT(2)
1385 #define ICE_AQ_FEC_MASK MAKEMASK(0x7, 0)
1387 #define ICE_AQ_CFG_PACING_S 3
1388 #define ICE_AQ_CFG_PACING_M (0xF << ICE_AQ_CFG_PACING_S)
1389 #define ICE_AQ_CFG_PACING_TYPE_M BIT(7)
1390 #define ICE_AQ_CFG_PACING_TYPE_AVG 0
1391 #define ICE_AQ_CFG_PACING_TYPE_FIXED ICE_AQ_CFG_PACING_TYPE_M
1392 /* External Device Power Ability */
1394 #define ICE_AQ_PWR_CLASS_M 0x3
1395 #define ICE_AQ_LINK_PWR_BASET_LOW_HIGH 0
1396 #define ICE_AQ_LINK_PWR_BASET_HIGH 1
1397 #define ICE_AQ_LINK_PWR_QSFP_CLASS_1 0
1398 #define ICE_AQ_LINK_PWR_QSFP_CLASS_2 1
1399 #define ICE_AQ_LINK_PWR_QSFP_CLASS_3 2
1400 #define ICE_AQ_LINK_PWR_QSFP_CLASS_4 3
1402 #define ICE_AQ_LINK_SPEED_10MB BIT(0)
1403 #define ICE_AQ_LINK_SPEED_100MB BIT(1)
1404 #define ICE_AQ_LINK_SPEED_1000MB BIT(2)
1405 #define ICE_AQ_LINK_SPEED_2500MB BIT(3)
1406 #define ICE_AQ_LINK_SPEED_5GB BIT(4)
1407 #define ICE_AQ_LINK_SPEED_10GB BIT(5)
1408 #define ICE_AQ_LINK_SPEED_20GB BIT(6)
1409 #define ICE_AQ_LINK_SPEED_25GB BIT(7)
1410 #define ICE_AQ_LINK_SPEED_40GB BIT(8)
1411 #define ICE_AQ_LINK_SPEED_50GB BIT(9)
1412 #define ICE_AQ_LINK_SPEED_100GB BIT(10)
1413 #define ICE_AQ_LINK_SPEED_UNKNOWN BIT(15)
1414 __le32 reserved3; /* Aligns next field to 8-byte boundary */
1415 __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */
1416 __le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */
1420 /* Set event mask command (direct 0x0613) */
1421 struct ice_aqc_set_event_mask {
1425 #define ICE_AQ_LINK_EVENT_UPDOWN BIT(1)
1426 #define ICE_AQ_LINK_EVENT_MEDIA_NA BIT(2)
1427 #define ICE_AQ_LINK_EVENT_LINK_FAULT BIT(3)
1428 #define ICE_AQ_LINK_EVENT_PHY_TEMP_ALARM BIT(4)
1429 #define ICE_AQ_LINK_EVENT_EXCESSIVE_ERRORS BIT(5)
1430 #define ICE_AQ_LINK_EVENT_SIGNAL_DETECT BIT(6)
1431 #define ICE_AQ_LINK_EVENT_AN_COMPLETED BIT(7)
1432 #define ICE_AQ_LINK_EVENT_MODULE_QUAL_FAIL BIT(8)
1433 #define ICE_AQ_LINK_EVENT_PORT_TX_SUSPENDED BIT(9)
1439 /* Set MAC Loopback command (direct 0x0620) */
1440 struct ice_aqc_set_mac_lb {
1442 #define ICE_AQ_MAC_LB_EN BIT(0)
1443 #define ICE_AQ_MAC_LB_OSC_CLK BIT(1)
1451 /* Set Port Identification LED (direct, 0x06E9) */
1452 struct ice_aqc_set_port_id_led {
1455 #define ICE_AQC_PORT_ID_PORT_NUM_VALID BIT(0)
1457 #define ICE_AQC_PORT_IDENT_LED_BLINK BIT(0)
1458 #define ICE_AQC_PORT_IDENT_LED_ORIG 0
1464 /* NVM Read command (indirect 0x0701)
1465 * NVM Erase commands (direct 0x0702)
1466 * NVM Update commands (indirect 0x0703)
1468 struct ice_aqc_nvm {
1472 #define ICE_AQC_NVM_LAST_CMD BIT(0)
1473 #define ICE_AQC_NVM_PCIR_REQ BIT(0) /* Used by NVM Update reply */
1474 #define ICE_AQC_NVM_PRESERVATION_S 1
1475 #define ICE_AQC_NVM_PRESERVATION_M (3 << ICE_AQC_NVM_PRESERVATION_S)
1476 #define ICE_AQC_NVM_NO_PRESERVATION (0 << ICE_AQC_NVM_PRESERVATION_S)
1477 #define ICE_AQC_NVM_PRESERVE_ALL BIT(1)
1478 #define ICE_AQC_NVM_FACTORY_DEFAULT (2 << ICE_AQC_NVM_PRESERVATION_S)
1479 #define ICE_AQC_NVM_PRESERVE_SELECTED (3 << ICE_AQC_NVM_PRESERVATION_S)
1480 #define ICE_AQC_NVM_FLASH_ONLY BIT(7)
1481 __le16 module_typeid;
1483 #define ICE_AQC_NVM_ERASE_LEN 0xFFFF
1489 /* Used for 0x0704 as well as for 0x0705 commands */
1490 struct ice_aqc_nvm_cfg {
1492 #define ICE_AQC_ANVM_MULTIPLE_ELEMS BIT(0)
1493 #define ICE_AQC_ANVM_IMMEDIATE_FIELD BIT(1)
1494 #define ICE_AQC_ANVM_NEW_CFG BIT(2)
1504 struct ice_aqc_nvm_cfg_data {
1506 __le16 field_options;
1511 /* NVM Checksum Command (direct, 0x0706) */
1512 struct ice_aqc_nvm_checksum {
1514 #define ICE_AQC_NVM_CHECKSUM_VERIFY BIT(0)
1515 #define ICE_AQC_NVM_CHECKSUM_RECALC BIT(1)
1517 __le16 checksum; /* Used only by response */
1518 #define ICE_AQC_NVM_CHECKSUM_CORRECT 0xBABA
1526 /* Get/Set RSS key (indirect 0x0B04/0x0B02) */
1527 struct ice_aqc_get_set_rss_key {
1528 #define ICE_AQC_GSET_RSS_KEY_VSI_VALID BIT(15)
1529 #define ICE_AQC_GSET_RSS_KEY_VSI_ID_S 0
1530 #define ICE_AQC_GSET_RSS_KEY_VSI_ID_M (0x3FF << ICE_AQC_GSET_RSS_KEY_VSI_ID_S)
1538 #define ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE 0x28
1539 #define ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE 0xC
1541 struct ice_aqc_get_set_rss_keys {
1542 u8 standard_rss_key[ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE];
1543 u8 extended_hash_key[ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE];
1547 /* Get/Set RSS LUT (indirect 0x0B05/0x0B03) */
1548 struct ice_aqc_get_set_rss_lut {
1549 #define ICE_AQC_GSET_RSS_LUT_VSI_VALID BIT(15)
1550 #define ICE_AQC_GSET_RSS_LUT_VSI_ID_S 0
1551 #define ICE_AQC_GSET_RSS_LUT_VSI_ID_M (0x1FF << ICE_AQC_GSET_RSS_LUT_VSI_ID_S)
1553 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S 0
1554 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_M \
1555 (0x3 << ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S)
1557 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_VSI 0
1558 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF 1
1559 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL 2
1561 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S 2
1562 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M \
1563 (0x3 << ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S)
1565 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128 128
1566 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128_FLAG 0
1567 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512 512
1568 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512_FLAG 1
1569 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K 2048
1570 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K_FLAG 2
1572 #define ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S 4
1573 #define ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_M \
1574 (0xF << ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S)
1586 /* Add Tx LAN Queues (indirect 0x0C30) */
1587 struct ice_aqc_add_txqs {
1596 /* This is the descriptor of each queue entry for the Add Tx LAN Queues
1597 * command (0x0C30). Only used within struct ice_aqc_add_tx_qgrp.
1599 struct ice_aqc_add_txqs_perq {
1605 struct ice_aqc_txsched_elem info;
1609 /* The format of the command buffer for Add Tx LAN Queues (0x0C30)
1610 * is an array of the following structs. Please note that the length of
1611 * each struct ice_aqc_add_tx_qgrp is variable due
1612 * to the variable number of queues in each group!
1614 struct ice_aqc_add_tx_qgrp {
1618 struct ice_aqc_add_txqs_perq txqs[1];
1622 /* Disable Tx LAN Queues (indirect 0x0C31) */
1623 struct ice_aqc_dis_txqs {
1625 #define ICE_AQC_Q_DIS_CMD_S 0
1626 #define ICE_AQC_Q_DIS_CMD_M (0x3 << ICE_AQC_Q_DIS_CMD_S)
1627 #define ICE_AQC_Q_DIS_CMD_NO_FUNC_RESET (0 << ICE_AQC_Q_DIS_CMD_S)
1628 #define ICE_AQC_Q_DIS_CMD_VM_RESET BIT(ICE_AQC_Q_DIS_CMD_S)
1629 #define ICE_AQC_Q_DIS_CMD_VF_RESET (2 << ICE_AQC_Q_DIS_CMD_S)
1630 #define ICE_AQC_Q_DIS_CMD_PF_RESET (3 << ICE_AQC_Q_DIS_CMD_S)
1631 #define ICE_AQC_Q_DIS_CMD_SUBSEQ_CALL BIT(2)
1632 #define ICE_AQC_Q_DIS_CMD_FLUSH_PIPE BIT(3)
1634 __le16 vmvf_and_timeout;
1635 #define ICE_AQC_Q_DIS_VMVF_NUM_S 0
1636 #define ICE_AQC_Q_DIS_VMVF_NUM_M (0x3FF << ICE_AQC_Q_DIS_VMVF_NUM_S)
1637 #define ICE_AQC_Q_DIS_TIMEOUT_S 10
1638 #define ICE_AQC_Q_DIS_TIMEOUT_M (0x3F << ICE_AQC_Q_DIS_TIMEOUT_S)
1639 __le32 blocked_cgds;
1645 /* The buffer for Disable Tx LAN Queues (indirect 0x0C31)
1646 * contains the following structures, arrayed one after the
1648 * Note: Since the q_id is 16 bits wide, if the
1649 * number of queues is even, then 2 bytes of alignment MUST be
1650 * added before the start of the next group, to allow correct
1651 * alignment of the parent_teid field.
1653 struct ice_aqc_dis_txq_item {
1657 /* The length of the q_id array varies according to num_qs */
1659 /* This only applies from F8 onward */
1660 #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S 15
1661 #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_LAN_Q \
1662 (0 << ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S)
1663 #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_RDMA_QSET \
1664 (1 << ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S)
1668 struct ice_aqc_dis_txq {
1669 struct ice_aqc_dis_txq_item qgrps[1];
1673 /* Tx LAN Queues Cleanup Event (0x0C31) */
1674 struct ice_aqc_txqs_cleanup {
1681 /* Move / Reconfigure Tx Queues (indirect 0x0C32) */
1682 struct ice_aqc_move_txqs {
1684 #define ICE_AQC_Q_CMD_TYPE_S 0
1685 #define ICE_AQC_Q_CMD_TYPE_M (0x3 << ICE_AQC_Q_CMD_TYPE_S)
1686 #define ICE_AQC_Q_CMD_TYPE_MOVE 1
1687 #define ICE_AQC_Q_CMD_TYPE_TC_CHANGE 2
1688 #define ICE_AQC_Q_CMD_TYPE_MOVE_AND_TC 3
1689 #define ICE_AQC_Q_CMD_SUBSEQ_CALL BIT(2)
1690 #define ICE_AQC_Q_CMD_FLUSH_PIPE BIT(3)
1694 #define ICE_AQC_Q_CMD_TIMEOUT_S 2
1695 #define ICE_AQC_Q_CMD_TIMEOUT_M (0x3F << ICE_AQC_Q_CMD_TIMEOUT_S)
1696 __le32 blocked_cgds;
1702 /* This is the descriptor of each queue entry for the move Tx LAN Queues
1705 struct ice_aqc_move_txqs_elem {
1713 struct ice_aqc_move_txqs_data {
1716 struct ice_aqc_move_txqs_elem txqs[1];
1721 /* Download Package (indirect 0x0C40) */
1722 /* Also used for Update Package (indirect 0x0C42) */
1723 struct ice_aqc_download_pkg {
1725 #define ICE_AQC_DOWNLOAD_PKG_LAST_BUF 0x01
1732 struct ice_aqc_download_pkg_resp {
1733 __le32 error_offset;
1739 /* Get Package Info List (indirect 0x0C43) */
1740 struct ice_aqc_get_pkg_info_list {
1747 /* Version format for packages */
1748 struct ice_pkg_ver {
1755 #define ICE_PKG_NAME_SIZE 32
1757 struct ice_aqc_get_pkg_info {
1758 struct ice_pkg_ver ver;
1759 char name[ICE_PKG_NAME_SIZE];
1762 u8 is_active_at_boot;
1766 /* Get Package Info List response buffer format (0x0C43) */
1767 struct ice_aqc_get_pkg_info_resp {
1769 struct ice_aqc_get_pkg_info pkg_info[1];
1775 /* Lan Queue Overflow Event (direct, 0x1001) */
1776 struct ice_aqc_event_lan_overflow {
1777 __le32 prtdcb_ruptq;
1784 /* Configure Firmware Logging Command (indirect 0xFF09)
1785 * Logging Information Read Response (indirect 0xFF10)
1786 * Note: The 0xFF10 command has no input parameters.
1788 struct ice_aqc_fw_logging {
1790 #define ICE_AQC_FW_LOG_AQ_EN BIT(0)
1791 #define ICE_AQC_FW_LOG_UART_EN BIT(1)
1793 u8 log_ctrl_valid; /* Not used by 0xFF10 Response */
1794 #define ICE_AQC_FW_LOG_AQ_VALID BIT(0)
1795 #define ICE_AQC_FW_LOG_UART_VALID BIT(1)
1802 enum ice_aqc_fw_logging_mod {
1803 ICE_AQC_FW_LOG_ID_GENERAL = 0,
1804 ICE_AQC_FW_LOG_ID_CTRL,
1805 ICE_AQC_FW_LOG_ID_LINK,
1806 ICE_AQC_FW_LOG_ID_LINK_TOPO,
1807 ICE_AQC_FW_LOG_ID_DNL,
1808 ICE_AQC_FW_LOG_ID_I2C,
1809 ICE_AQC_FW_LOG_ID_SDP,
1810 ICE_AQC_FW_LOG_ID_MDIO,
1811 ICE_AQC_FW_LOG_ID_ADMINQ,
1812 ICE_AQC_FW_LOG_ID_HDMA,
1813 ICE_AQC_FW_LOG_ID_LLDP,
1814 ICE_AQC_FW_LOG_ID_DCBX,
1815 ICE_AQC_FW_LOG_ID_DCB,
1816 ICE_AQC_FW_LOG_ID_NETPROXY,
1817 ICE_AQC_FW_LOG_ID_NVM,
1818 ICE_AQC_FW_LOG_ID_AUTH,
1819 ICE_AQC_FW_LOG_ID_VPD,
1820 ICE_AQC_FW_LOG_ID_IOSF,
1821 ICE_AQC_FW_LOG_ID_PARSER,
1822 ICE_AQC_FW_LOG_ID_SW,
1823 ICE_AQC_FW_LOG_ID_SCHEDULER,
1824 ICE_AQC_FW_LOG_ID_TXQ,
1825 ICE_AQC_FW_LOG_ID_RSVD,
1826 ICE_AQC_FW_LOG_ID_POST,
1827 ICE_AQC_FW_LOG_ID_WATCHDOG,
1828 ICE_AQC_FW_LOG_ID_TASK_DISPATCH,
1829 ICE_AQC_FW_LOG_ID_MNG,
1830 ICE_AQC_FW_LOG_ID_MAX,
1833 /* This is the buffer for both of the logging commands.
1834 * The entry array size depends on the datalen parameter in the descriptor.
1835 * There will be a total of datalen / 2 entries.
1837 struct ice_aqc_fw_logging_data {
1839 #define ICE_AQC_FW_LOG_ID_S 0
1840 #define ICE_AQC_FW_LOG_ID_M (0xFFF << ICE_AQC_FW_LOG_ID_S)
1842 #define ICE_AQC_FW_LOG_CONF_SUCCESS 0 /* Used by response */
1843 #define ICE_AQC_FW_LOG_CONF_BAD_INDX BIT(12) /* Used by response */
1845 #define ICE_AQC_FW_LOG_EN_S 12
1846 #define ICE_AQC_FW_LOG_EN_M (0xF << ICE_AQC_FW_LOG_EN_S)
1847 #define ICE_AQC_FW_LOG_INFO_EN BIT(12) /* Used by command */
1848 #define ICE_AQC_FW_LOG_INIT_EN BIT(13) /* Used by command */
1849 #define ICE_AQC_FW_LOG_FLOW_EN BIT(14) /* Used by command */
1850 #define ICE_AQC_FW_LOG_ERR_EN BIT(15) /* Used by command */
1854 /* Get/Clear FW Log (indirect 0xFF11) */
1855 struct ice_aqc_get_clear_fw_log {
1857 #define ICE_AQC_FW_LOG_CLEAR BIT(0)
1858 #define ICE_AQC_FW_LOG_MORE_DATA_AVAIL BIT(1)
1866 * struct ice_aq_desc - Admin Queue (AQ) descriptor
1867 * @flags: ICE_AQ_FLAG_* flags
1868 * @opcode: AQ command opcode
1869 * @datalen: length in bytes of indirect/external data buffer
1870 * @retval: return value from firmware
1871 * @cookie_h: opaque data high-half
1872 * @cookie_l: opaque data low-half
1873 * @params: command-specific parameters
1875 * Descriptor format for commands the driver posts on the Admin Transmit Queue
1876 * (ATQ). The firmware writes back onto the command descriptor and returns
1877 * the result of the command. Asynchronous events that are not an immediate
1878 * result of the command are written to the Admin Receive Queue (ARQ) using
1879 * the same descriptor format. Descriptors are in little-endian notation with
1882 struct ice_aq_desc {
1891 struct ice_aqc_generic generic;
1892 struct ice_aqc_get_ver get_ver;
1893 struct ice_aqc_q_shutdown q_shutdown;
1894 struct ice_aqc_req_res res_owner;
1895 struct ice_aqc_manage_mac_read mac_read;
1896 struct ice_aqc_manage_mac_write mac_write;
1897 struct ice_aqc_clear_pxe clear_pxe;
1898 struct ice_aqc_config_no_drop_policy no_drop;
1899 struct ice_aqc_add_update_mir_rule add_update_rule;
1900 struct ice_aqc_delete_mir_rule del_rule;
1901 struct ice_aqc_list_caps get_cap;
1902 struct ice_aqc_get_phy_caps get_phy;
1903 struct ice_aqc_set_phy_cfg set_phy;
1904 struct ice_aqc_restart_an restart_an;
1905 struct ice_aqc_set_port_id_led set_port_id_led;
1906 struct ice_aqc_get_sw_cfg get_sw_conf;
1907 struct ice_aqc_sw_rules sw_rules;
1908 struct ice_aqc_storm_cfg storm_conf;
1909 struct ice_aqc_get_topo get_topo;
1910 struct ice_aqc_sched_elem_cmd sched_elem_cmd;
1911 struct ice_aqc_query_txsched_res query_sched_res;
1912 struct ice_aqc_query_node_to_root query_node_to_root;
1913 struct ice_aqc_cfg_l2_node_cgd cfg_l2_node_cgd;
1914 struct ice_aqc_rl_profile rl_profile;
1916 struct ice_aqc_nvm nvm;
1917 struct ice_aqc_nvm_cfg nvm_cfg;
1918 struct ice_aqc_nvm_checksum nvm_checksum;
1919 struct ice_aqc_get_set_rss_lut get_set_rss_lut;
1920 struct ice_aqc_get_set_rss_key get_set_rss_key;
1921 struct ice_aqc_add_txqs add_txqs;
1922 struct ice_aqc_dis_txqs dis_txqs;
1923 struct ice_aqc_txqs_cleanup txqs_cleanup;
1924 struct ice_aqc_add_get_update_free_vsi vsi_cmd;
1925 struct ice_aqc_add_update_free_vsi_resp add_update_free_vsi_res;
1926 struct ice_aqc_get_vsi_resp get_vsi_resp;
1927 struct ice_aqc_download_pkg download_pkg;
1928 struct ice_aqc_get_pkg_info_list get_pkg_info_list;
1929 struct ice_aqc_fw_logging fw_logging;
1930 struct ice_aqc_get_clear_fw_log get_clear_fw_log;
1931 struct ice_aqc_set_mac_lb set_mac_lb;
1932 struct ice_aqc_alloc_free_res_cmd sw_res_ctrl;
1933 struct ice_aqc_set_mac_cfg set_mac_cfg;
1934 struct ice_aqc_set_event_mask set_event_mask;
1935 struct ice_aqc_get_link_status get_link_status;
1940 /* FW defined boundary for a large buffer, 4k >= Large buffer > 512 bytes */
1941 #define ICE_AQ_LG_BUF 512
1943 /* Flags sub-structure
1944 * |0 |1 |2 |3 |4 |5 |6 |7 |8 |9 |10 |11 |12 |13 |14 |15 |
1945 * |DD |CMP|ERR|VFE| * * RESERVED * * |LB |RD |VFC|BUF|SI |EI |FE |
1948 /* command flags and offsets */
1949 #define ICE_AQ_FLAG_DD_S 0
1950 #define ICE_AQ_FLAG_CMP_S 1
1951 #define ICE_AQ_FLAG_ERR_S 2
1952 #define ICE_AQ_FLAG_VFE_S 3
1953 #define ICE_AQ_FLAG_LB_S 9
1954 #define ICE_AQ_FLAG_RD_S 10
1955 #define ICE_AQ_FLAG_VFC_S 11
1956 #define ICE_AQ_FLAG_BUF_S 12
1957 #define ICE_AQ_FLAG_SI_S 13
1958 #define ICE_AQ_FLAG_EI_S 14
1959 #define ICE_AQ_FLAG_FE_S 15
1961 #define ICE_AQ_FLAG_DD BIT(ICE_AQ_FLAG_DD_S) /* 0x1 */
1962 #define ICE_AQ_FLAG_CMP BIT(ICE_AQ_FLAG_CMP_S) /* 0x2 */
1963 #define ICE_AQ_FLAG_ERR BIT(ICE_AQ_FLAG_ERR_S) /* 0x4 */
1964 #define ICE_AQ_FLAG_VFE BIT(ICE_AQ_FLAG_VFE_S) /* 0x8 */
1965 #define ICE_AQ_FLAG_LB BIT(ICE_AQ_FLAG_LB_S) /* 0x200 */
1966 #define ICE_AQ_FLAG_RD BIT(ICE_AQ_FLAG_RD_S) /* 0x400 */
1967 #define ICE_AQ_FLAG_VFC BIT(ICE_AQ_FLAG_VFC_S) /* 0x800 */
1968 #define ICE_AQ_FLAG_BUF BIT(ICE_AQ_FLAG_BUF_S) /* 0x1000 */
1969 #define ICE_AQ_FLAG_SI BIT(ICE_AQ_FLAG_SI_S) /* 0x2000 */
1970 #define ICE_AQ_FLAG_EI BIT(ICE_AQ_FLAG_EI_S) /* 0x4000 */
1971 #define ICE_AQ_FLAG_FE BIT(ICE_AQ_FLAG_FE_S) /* 0x8000 */
1975 ICE_AQ_RC_OK = 0, /* Success */
1976 ICE_AQ_RC_EPERM = 1, /* Operation not permitted */
1977 ICE_AQ_RC_ENOENT = 2, /* No such element */
1978 ICE_AQ_RC_ESRCH = 3, /* Bad opcode */
1979 ICE_AQ_RC_EINTR = 4, /* Operation interrupted */
1980 ICE_AQ_RC_EIO = 5, /* I/O error */
1981 ICE_AQ_RC_ENXIO = 6, /* No such resource */
1982 ICE_AQ_RC_E2BIG = 7, /* Arg too long */
1983 ICE_AQ_RC_EAGAIN = 8, /* Try again */
1984 ICE_AQ_RC_ENOMEM = 9, /* Out of memory */
1985 ICE_AQ_RC_EACCES = 10, /* Permission denied */
1986 ICE_AQ_RC_EFAULT = 11, /* Bad address */
1987 ICE_AQ_RC_EBUSY = 12, /* Device or resource busy */
1988 ICE_AQ_RC_EEXIST = 13, /* Object already exists */
1989 ICE_AQ_RC_EINVAL = 14, /* Invalid argument */
1990 ICE_AQ_RC_ENOTTY = 15, /* Not a typewriter */
1991 ICE_AQ_RC_ENOSPC = 16, /* No space left or allocation failure */
1992 ICE_AQ_RC_ENOSYS = 17, /* Function not implemented */
1993 ICE_AQ_RC_ERANGE = 18, /* Parameter out of range */
1994 ICE_AQ_RC_EFLUSHED = 19, /* Cmd flushed due to prev cmd error */
1995 ICE_AQ_RC_BAD_ADDR = 20, /* Descriptor contains a bad pointer */
1996 ICE_AQ_RC_EMODE = 21, /* Op not allowed in current dev mode */
1997 ICE_AQ_RC_EFBIG = 22, /* File too big */
1998 ICE_AQ_RC_ESBCOMP = 23, /* SB-IOSF completion unsuccessful */
1999 ICE_AQ_RC_ENOSEC = 24, /* Missing security manifest */
2000 ICE_AQ_RC_EBADSIG = 25, /* Bad RSA signature */
2001 ICE_AQ_RC_ESVN = 26, /* SVN number prohibits this package */
2002 ICE_AQ_RC_EBADMAN = 27, /* Manifest hash mismatch */
2003 ICE_AQ_RC_EBADBUF = 28, /* Buffer hash mismatches manifest */
2006 /* Admin Queue command opcodes */
2007 enum ice_adminq_opc {
2009 ice_aqc_opc_get_ver = 0x0001,
2010 ice_aqc_opc_driver_ver = 0x0002,
2011 ice_aqc_opc_q_shutdown = 0x0003,
2012 ice_aqc_opc_get_exp_err = 0x0005,
2014 /* resource ownership */
2015 ice_aqc_opc_req_res = 0x0008,
2016 ice_aqc_opc_release_res = 0x0009,
2018 /* device/function capabilities */
2019 ice_aqc_opc_list_func_caps = 0x000A,
2020 ice_aqc_opc_list_dev_caps = 0x000B,
2022 /* manage MAC address */
2023 ice_aqc_opc_manage_mac_read = 0x0107,
2024 ice_aqc_opc_manage_mac_write = 0x0108,
2027 ice_aqc_opc_clear_pxe_mode = 0x0110,
2029 /* internal switch commands */
2030 ice_aqc_opc_get_sw_cfg = 0x0200,
2032 /* Alloc/Free/Get Resources */
2033 ice_aqc_opc_get_res_alloc = 0x0204,
2034 ice_aqc_opc_alloc_res = 0x0208,
2035 ice_aqc_opc_free_res = 0x0209,
2036 ice_aqc_opc_get_allocd_res_desc = 0x020A,
2039 ice_aqc_opc_add_vsi = 0x0210,
2040 ice_aqc_opc_update_vsi = 0x0211,
2041 ice_aqc_opc_get_vsi_params = 0x0212,
2042 ice_aqc_opc_free_vsi = 0x0213,
2044 /* Mirroring rules - add/update, delete */
2045 ice_aqc_opc_add_update_mir_rule = 0x0260,
2046 ice_aqc_opc_del_mir_rule = 0x0261,
2048 /* storm configuration */
2049 ice_aqc_opc_set_storm_cfg = 0x0280,
2050 ice_aqc_opc_get_storm_cfg = 0x0281,
2053 /* switch rules population commands */
2054 ice_aqc_opc_add_sw_rules = 0x02A0,
2055 ice_aqc_opc_update_sw_rules = 0x02A1,
2056 ice_aqc_opc_remove_sw_rules = 0x02A2,
2057 ice_aqc_opc_get_sw_rules = 0x02A3,
2058 ice_aqc_opc_clear_pf_cfg = 0x02A4,
2061 /* transmit scheduler commands */
2062 ice_aqc_opc_get_dflt_topo = 0x0400,
2063 ice_aqc_opc_add_sched_elems = 0x0401,
2064 ice_aqc_opc_cfg_sched_elems = 0x0403,
2065 ice_aqc_opc_get_sched_elems = 0x0404,
2066 ice_aqc_opc_move_sched_elems = 0x0408,
2067 ice_aqc_opc_suspend_sched_elems = 0x0409,
2068 ice_aqc_opc_resume_sched_elems = 0x040A,
2069 ice_aqc_opc_delete_sched_elems = 0x040F,
2070 ice_aqc_opc_add_rl_profiles = 0x0410,
2071 ice_aqc_opc_query_rl_profiles = 0x0411,
2072 ice_aqc_opc_query_sched_res = 0x0412,
2073 ice_aqc_opc_query_node_to_root = 0x0413,
2074 ice_aqc_opc_cfg_l2_node_cgd = 0x0414,
2075 ice_aqc_opc_remove_rl_profiles = 0x0415,
2078 ice_aqc_opc_get_phy_caps = 0x0600,
2079 ice_aqc_opc_set_phy_cfg = 0x0601,
2080 ice_aqc_opc_set_mac_cfg = 0x0603,
2081 ice_aqc_opc_restart_an = 0x0605,
2082 ice_aqc_opc_get_link_status = 0x0607,
2083 ice_aqc_opc_set_event_mask = 0x0613,
2084 ice_aqc_opc_set_mac_lb = 0x0620,
2085 ice_aqc_opc_set_port_id_led = 0x06E9,
2086 ice_aqc_opc_get_port_options = 0x06EA,
2087 ice_aqc_opc_set_port_option = 0x06EB,
2088 ice_aqc_opc_set_gpio = 0x06EC,
2089 ice_aqc_opc_get_gpio = 0x06ED,
2092 ice_aqc_opc_nvm_read = 0x0701,
2093 ice_aqc_opc_nvm_erase = 0x0702,
2094 ice_aqc_opc_nvm_update = 0x0703,
2095 ice_aqc_opc_nvm_cfg_read = 0x0704,
2096 ice_aqc_opc_nvm_cfg_write = 0x0705,
2097 ice_aqc_opc_nvm_checksum = 0x0706,
2101 ice_aqc_opc_set_rss_key = 0x0B02,
2102 ice_aqc_opc_set_rss_lut = 0x0B03,
2103 ice_aqc_opc_get_rss_key = 0x0B04,
2104 ice_aqc_opc_get_rss_lut = 0x0B05,
2106 /* Tx queue handling commands/events */
2107 ice_aqc_opc_add_txqs = 0x0C30,
2108 ice_aqc_opc_dis_txqs = 0x0C31,
2109 ice_aqc_opc_txqs_cleanup = 0x0C31,
2110 ice_aqc_opc_move_recfg_txqs = 0x0C32,
2112 /* package commands */
2113 ice_aqc_opc_download_pkg = 0x0C40,
2114 ice_aqc_opc_upload_section = 0x0C41,
2115 ice_aqc_opc_update_pkg = 0x0C42,
2116 ice_aqc_opc_get_pkg_info_list = 0x0C43,
2120 /* Standalone Commands/Events */
2121 ice_aqc_opc_event_lan_overflow = 0x1001,
2123 /* debug commands */
2124 ice_aqc_opc_fw_logging = 0xFF09,
2125 ice_aqc_opc_fw_logging_info = 0xFF10,
2126 ice_aqc_opc_get_clear_fw_log = 0xFF11
2129 #endif /* _ICE_ADMINQ_CMD_H_ */