1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2001-2021 Intel Corporation
5 #ifndef _ICE_ADMINQ_CMD_H_
6 #define _ICE_ADMINQ_CMD_H_
8 /* This header file defines the Admin Queue commands, error codes and
9 * descriptor format. It is shared between Firmware and Software.
12 #define ICE_MAX_VSI 768
13 #define ICE_AQC_TOPO_MAX_LEVEL_NUM 0x9
14 #define ICE_AQ_SET_MAC_FRAME_SIZE_MAX 9728
16 struct ice_aqc_generic {
23 /* Get version (direct 0x0001) */
24 struct ice_aqc_get_ver {
37 /* Send driver version (indirect 0x0002) */
38 struct ice_aqc_driver_ver {
48 /* Queue Shutdown (direct 0x0003) */
49 struct ice_aqc_q_shutdown {
51 #define ICE_AQC_DRIVER_UNLOADING BIT(0)
55 /* Request resource ownership (direct 0x0008)
56 * Release resource ownership (direct 0x0009)
58 struct ice_aqc_req_res {
60 #define ICE_AQC_RES_ID_NVM 1
61 #define ICE_AQC_RES_ID_SDP 2
62 #define ICE_AQC_RES_ID_CHNG_LOCK 3
63 #define ICE_AQC_RES_ID_GLBL_LOCK 4
65 #define ICE_AQC_RES_ACCESS_READ 1
66 #define ICE_AQC_RES_ACCESS_WRITE 2
68 /* Upon successful completion, FW writes this value and driver is
69 * expected to release resource before timeout. This value is provided
73 #define ICE_AQ_RES_NVM_READ_DFLT_TIMEOUT_MS 3000
74 #define ICE_AQ_RES_NVM_WRITE_DFLT_TIMEOUT_MS 180000
75 #define ICE_AQ_RES_CHNG_LOCK_DFLT_TIMEOUT_MS 1000
76 #define ICE_AQ_RES_GLBL_LOCK_DFLT_TIMEOUT_MS 3000
77 /* For SDP: pin ID of the SDP */
79 /* Status is only used for ICE_AQC_RES_ID_GLBL_LOCK */
81 #define ICE_AQ_RES_GLBL_SUCCESS 0
82 #define ICE_AQ_RES_GLBL_IN_PROG 1
83 #define ICE_AQ_RES_GLBL_DONE 2
87 /* Get function capabilities (indirect 0x000A)
88 * Get device capabilities (indirect 0x000B)
90 struct ice_aqc_list_caps {
99 /* Device/Function buffer entry, repeated per reported capability */
100 struct ice_aqc_list_caps_elem {
102 #define ICE_AQC_CAPS_VALID_FUNCTIONS 0x0005
103 #define ICE_AQC_MAX_VALID_FUNCTIONS 0x8
104 #define ICE_AQC_CAPS_VSI 0x0017
105 #define ICE_AQC_CAPS_DCB 0x0018
106 #define ICE_AQC_CAPS_RSS 0x0040
107 #define ICE_AQC_CAPS_RXQS 0x0041
108 #define ICE_AQC_CAPS_TXQS 0x0042
109 #define ICE_AQC_CAPS_MSIX 0x0043
110 #define ICE_AQC_CAPS_FD 0x0045
111 #define ICE_AQC_CAPS_MAX_MTU 0x0047
112 #define ICE_AQC_CAPS_IWARP 0x0051
113 #define ICE_AQC_CAPS_PCIE_RESET_AVOIDANCE 0x0076
114 #define ICE_AQC_CAPS_POST_UPDATE_RESET_RESTRICT 0x0077
115 #define ICE_AQC_CAPS_NVM_MGMT 0x0080
116 #define ICE_AQC_CAPS_EXT_TOPO_DEV_IMG0 0x0081
117 #define ICE_AQC_CAPS_EXT_TOPO_DEV_IMG1 0x0082
118 #define ICE_AQC_CAPS_EXT_TOPO_DEV_IMG2 0x0083
119 #define ICE_AQC_CAPS_EXT_TOPO_DEV_IMG3 0x0084
123 /* Number of resources described by this capability */
125 /* Only meaningful for some types of resources */
127 /* Only meaningful for some types of resources */
133 /* Manage MAC address, read command - indirect (0x0107)
134 * This struct is also used for the response
136 struct ice_aqc_manage_mac_read {
137 __le16 flags; /* Zeroed by device driver */
138 #define ICE_AQC_MAN_MAC_LAN_ADDR_VALID BIT(4)
139 #define ICE_AQC_MAN_MAC_SAN_ADDR_VALID BIT(5)
140 #define ICE_AQC_MAN_MAC_PORT_ADDR_VALID BIT(6)
141 #define ICE_AQC_MAN_MAC_WOL_ADDR_VALID BIT(7)
142 #define ICE_AQC_MAN_MAC_MC_MAG_EN BIT(8)
143 #define ICE_AQC_MAN_MAC_WOL_PRESERVE_ON_PFR BIT(9)
144 #define ICE_AQC_MAN_MAC_READ_S 4
145 #define ICE_AQC_MAN_MAC_READ_M (0xF << ICE_AQC_MAN_MAC_READ_S)
147 u8 num_addr; /* Used in response */
153 /* Response buffer format for manage MAC read command */
154 struct ice_aqc_manage_mac_read_resp {
157 #define ICE_AQC_MAN_MAC_ADDR_TYPE_LAN 0
158 #define ICE_AQC_MAN_MAC_ADDR_TYPE_WOL 1
159 u8 mac_addr[ETH_ALEN];
162 /* Manage MAC address, write command - direct (0x0108) */
163 struct ice_aqc_manage_mac_write {
166 #define ICE_AQC_MAN_MAC_WR_MC_MAG_EN BIT(0)
167 #define ICE_AQC_MAN_MAC_WR_WOL_LAA_PFR_KEEP BIT(1)
168 #define ICE_AQC_MAN_MAC_WR_S 6
169 #define ICE_AQC_MAN_MAC_WR_M MAKEMASK(3, ICE_AQC_MAN_MAC_WR_S)
170 #define ICE_AQC_MAN_MAC_UPDATE_LAA 0
171 #define ICE_AQC_MAN_MAC_UPDATE_LAA_WOL BIT(ICE_AQC_MAN_MAC_WR_S)
172 /* byte stream in network order */
173 u8 mac_addr[ETH_ALEN];
178 /* Clear PXE Command and response (direct 0x0110) */
179 struct ice_aqc_clear_pxe {
181 #define ICE_AQC_CLEAR_PXE_RX_CNT 0x2
185 /* Configure No-Drop Policy Command (direct 0x0112) */
186 struct ice_aqc_config_no_drop_policy {
188 #define ICE_AQC_FORCE_NO_DROP BIT(0)
192 /* Get switch configuration (0x0200) */
193 struct ice_aqc_get_sw_cfg {
194 /* Reserved for command and copy of request flags for response */
196 /* First desc in case of command and next_elem in case of response
197 * In case of response, if it is not zero, means all the configuration
198 * was not returned and new command shall be sent with this value in
199 * the 'first desc' field
202 /* Reserved for command, only used for response */
209 /* Each entry in the response buffer is of the following type: */
210 struct ice_aqc_get_sw_cfg_resp_elem {
211 /* VSI/Port Number */
213 #define ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_S 0
214 #define ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_M \
215 (0x3FF << ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_S)
216 #define ICE_AQC_GET_SW_CONF_RESP_TYPE_S 14
217 #define ICE_AQC_GET_SW_CONF_RESP_TYPE_M (0x3 << ICE_AQC_GET_SW_CONF_RESP_TYPE_S)
218 #define ICE_AQC_GET_SW_CONF_RESP_PHYS_PORT 0
219 #define ICE_AQC_GET_SW_CONF_RESP_VIRT_PORT 1
220 #define ICE_AQC_GET_SW_CONF_RESP_VSI 2
222 /* SWID VSI/Port belongs to */
225 /* Bit 14..0 : PF/VF number VSI belongs to
226 * Bit 15 : VF indication bit
229 #define ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_S 0
230 #define ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_M \
231 (0x7FFF << ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_S)
232 #define ICE_AQC_GET_SW_CONF_RESP_IS_VF BIT(15)
235 /* Set Port parameters, (direct, 0x0203) */
236 struct ice_aqc_set_port_params {
238 #define ICE_AQC_SET_P_PARAMS_SAVE_BAD_PACKETS BIT(0)
239 #define ICE_AQC_SET_P_PARAMS_PAD_SHORT_PACKETS BIT(1)
240 #define ICE_AQC_SET_P_PARAMS_DOUBLE_VLAN_ENA BIT(2)
241 __le16 bad_frame_vsi;
242 #define ICE_AQC_SET_P_PARAMS_VSI_S 0
243 #define ICE_AQC_SET_P_PARAMS_VSI_M (0x3FF << ICE_AQC_SET_P_PARAMS_VSI_S)
244 #define ICE_AQC_SET_P_PARAMS_VSI_VALID BIT(15)
246 #define ICE_AQC_SET_P_PARAMS_SWID_S 0
247 #define ICE_AQC_SET_P_PARAMS_SWID_M (0xFF << ICE_AQC_SET_P_PARAMS_SWID_S)
248 #define ICE_AQC_SET_P_PARAMS_LOGI_PORT_ID_S 8
249 #define ICE_AQC_SET_P_PARAMS_LOGI_PORT_ID_M \
250 (0x3F << ICE_AQC_SET_P_PARAMS_LOGI_PORT_ID_S)
251 #define ICE_AQC_SET_P_PARAMS_IS_LOGI_PORT BIT(14)
252 #define ICE_AQC_SET_P_PARAMS_SWID_VALID BIT(15)
256 /* These resource type defines are used for all switch resource
257 * commands where a resource type is required, such as:
258 * Get Resource Allocation command (indirect 0x0204)
259 * Allocate Resources command (indirect 0x0208)
260 * Free Resources command (indirect 0x0209)
261 * Get Allocated Resource Descriptors Command (indirect 0x020A)
263 #define ICE_AQC_RES_TYPE_VEB_COUNTER 0x00
264 #define ICE_AQC_RES_TYPE_VLAN_COUNTER 0x01
265 #define ICE_AQC_RES_TYPE_MIRROR_RULE 0x02
266 #define ICE_AQC_RES_TYPE_VSI_LIST_REP 0x03
267 #define ICE_AQC_RES_TYPE_VSI_LIST_PRUNE 0x04
268 #define ICE_AQC_RES_TYPE_RECIPE 0x05
269 #define ICE_AQC_RES_TYPE_PROFILE 0x06
270 #define ICE_AQC_RES_TYPE_SWID 0x07
271 #define ICE_AQC_RES_TYPE_VSI 0x08
272 #define ICE_AQC_RES_TYPE_FLU 0x09
273 #define ICE_AQC_RES_TYPE_WIDE_TABLE_1 0x0A
274 #define ICE_AQC_RES_TYPE_WIDE_TABLE_2 0x0B
275 #define ICE_AQC_RES_TYPE_WIDE_TABLE_4 0x0C
276 #define ICE_AQC_RES_TYPE_GLOBAL_RSS_HASH 0x20
277 #define ICE_AQC_RES_TYPE_FDIR_COUNTER_BLOCK 0x21
278 #define ICE_AQC_RES_TYPE_FDIR_GUARANTEED_ENTRIES 0x22
279 #define ICE_AQC_RES_TYPE_FDIR_SHARED_ENTRIES 0x23
280 #define ICE_AQC_RES_TYPE_FLEX_DESC_PROG 0x30
281 #define ICE_AQC_RES_TYPE_SWITCH_PROF_BLDR_PROFID 0x48
282 #define ICE_AQC_RES_TYPE_SWITCH_PROF_BLDR_TCAM 0x49
283 #define ICE_AQC_RES_TYPE_ACL_PROF_BLDR_PROFID 0x50
284 #define ICE_AQC_RES_TYPE_ACL_PROF_BLDR_TCAM 0x51
285 #define ICE_AQC_RES_TYPE_FD_PROF_BLDR_PROFID 0x58
286 #define ICE_AQC_RES_TYPE_FD_PROF_BLDR_TCAM 0x59
287 #define ICE_AQC_RES_TYPE_HASH_PROF_BLDR_PROFID 0x60
288 #define ICE_AQC_RES_TYPE_HASH_PROF_BLDR_TCAM 0x61
289 /* Resource types 0x62-67 are reserved for Hash profile builder */
290 #define ICE_AQC_RES_TYPE_QHASH_PROF_BLDR_PROFID 0x68
291 #define ICE_AQC_RES_TYPE_QHASH_PROF_BLDR_TCAM 0x69
293 #define ICE_AQC_RES_TYPE_FLAG_SHARED BIT(7)
294 #define ICE_AQC_RES_TYPE_FLAG_SCAN_BOTTOM BIT(12)
295 #define ICE_AQC_RES_TYPE_FLAG_IGNORE_INDEX BIT(13)
297 #define ICE_AQC_RES_TYPE_FLAG_DEDICATED 0x00
299 #define ICE_AQC_RES_TYPE_S 0
300 #define ICE_AQC_RES_TYPE_M (0x07F << ICE_AQC_RES_TYPE_S)
302 /* Get Resource Allocation command (indirect 0x0204) */
303 struct ice_aqc_get_res_alloc {
304 __le16 resp_elem_num; /* Used in response, reserved in command */
310 /* Get Resource Allocation Response Buffer per response */
311 struct ice_aqc_get_res_resp_elem {
312 __le16 res_type; /* Types defined above cmd 0x0204 */
313 __le16 total_capacity; /* Resources available to all PF's */
314 __le16 total_function; /* Resources allocated for a PF */
315 __le16 total_shared; /* Resources allocated as shared */
316 __le16 total_free; /* Resources un-allocated/not reserved by any PF */
319 /* Allocate Resources command (indirect 0x0208)
320 * Free Resources command (indirect 0x0209)
322 struct ice_aqc_alloc_free_res_cmd {
323 __le16 num_entries; /* Number of Resource entries */
329 /* Resource descriptor */
330 struct ice_aqc_res_elem {
337 /* Buffer for Allocate/Free Resources commands */
338 struct ice_aqc_alloc_free_res_elem {
339 __le16 res_type; /* Types defined above cmd 0x0204 */
340 #define ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_S 8
341 #define ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_M \
342 (0xF << ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_S)
344 struct ice_aqc_res_elem elem[STRUCT_HACK_VAR_LEN];
347 /* Get Allocated Resource Descriptors Command (indirect 0x020A) */
348 struct ice_aqc_get_allocd_res_desc {
351 __le16 res; /* Types defined above cmd 0x0204 */
366 /* Request buffer for Set VLAN Mode AQ command (indirect 0x020C) */
367 struct ice_aqc_set_vlan_mode {
369 u8 l2tag_prio_tagging;
370 #define ICE_AQ_VLAN_PRIO_TAG_S 0
371 #define ICE_AQ_VLAN_PRIO_TAG_M (0x7 << ICE_AQ_VLAN_PRIO_TAG_S)
372 #define ICE_AQ_VLAN_PRIO_TAG_NOT_SUPPORTED 0x0
373 #define ICE_AQ_VLAN_PRIO_TAG_STAG 0x1
374 #define ICE_AQ_VLAN_PRIO_TAG_OUTER_CTAG 0x2
375 #define ICE_AQ_VLAN_PRIO_TAG_OUTER_VLAN 0x3
376 #define ICE_AQ_VLAN_PRIO_TAG_INNER_CTAG 0x4
377 #define ICE_AQ_VLAN_PRIO_TAG_MAX 0x4
378 #define ICE_AQ_VLAN_PRIO_TAG_ERROR 0x7
379 u8 l2tag_reserved[64];
381 #define ICE_AQ_VLAN_RDMA_TAG_S 0
382 #define ICE_AQ_VLAN_RDMA_TAG_M (0x3F << ICE_AQ_VLAN_RDMA_TAG_S)
383 #define ICE_AQ_SVM_VLAN_RDMA_PKT_FLAG_SETTING 0x10
384 #define ICE_AQ_DVM_VLAN_RDMA_PKT_FLAG_SETTING 0x1A
387 #define ICE_AQ_VLAN_MNG_PROTOCOL_ID_OUTER 0x10
388 #define ICE_AQ_VLAN_MNG_PROTOCOL_ID_INNER 0x11
389 u8 prot_id_reserved[30];
392 /* Response buffer for Get VLAN Mode AQ command (indirect 0x020D) */
393 struct ice_aqc_get_vlan_mode {
395 #define ICE_AQ_VLAN_MODE_DVM_ENA BIT(0)
396 u8 l2tag_prio_tagging;
400 /* Add VSI (indirect 0x0210)
401 * Update VSI (indirect 0x0211)
402 * Get VSI (indirect 0x0212)
403 * Free VSI (indirect 0x0213)
405 struct ice_aqc_add_get_update_free_vsi {
407 #define ICE_AQ_VSI_NUM_S 0
408 #define ICE_AQ_VSI_NUM_M (0x03FF << ICE_AQ_VSI_NUM_S)
409 #define ICE_AQ_VSI_IS_VALID BIT(15)
411 #define ICE_AQ_VSI_KEEP_ALLOC 0x1
415 #define ICE_AQ_VSI_TYPE_S 0
416 #define ICE_AQ_VSI_TYPE_M (0x3 << ICE_AQ_VSI_TYPE_S)
417 #define ICE_AQ_VSI_TYPE_VF 0x0
418 #define ICE_AQ_VSI_TYPE_VMDQ2 0x1
419 #define ICE_AQ_VSI_TYPE_PF 0x2
420 #define ICE_AQ_VSI_TYPE_EMP_MNG 0x3
425 /* Response descriptor for:
426 * Add VSI (indirect 0x0210)
427 * Update VSI (indirect 0x0211)
428 * Free VSI (indirect 0x0213)
430 struct ice_aqc_add_update_free_vsi_resp {
439 struct ice_aqc_get_vsi_resp {
442 /* The vsi_flags field uses the ICE_AQ_VSI_TYPE_* defines for values.
443 * These are found above in struct ice_aqc_add_get_update_free_vsi.
452 struct ice_aqc_vsi_props {
453 __le16 valid_sections;
454 #define ICE_AQ_VSI_PROP_SW_VALID BIT(0)
455 #define ICE_AQ_VSI_PROP_SECURITY_VALID BIT(1)
456 #define ICE_AQ_VSI_PROP_VLAN_VALID BIT(2)
457 #define ICE_AQ_VSI_PROP_OUTER_TAG_VALID BIT(3)
458 #define ICE_AQ_VSI_PROP_INGRESS_UP_VALID BIT(4)
459 #define ICE_AQ_VSI_PROP_EGRESS_UP_VALID BIT(5)
460 #define ICE_AQ_VSI_PROP_RXQ_MAP_VALID BIT(6)
461 #define ICE_AQ_VSI_PROP_Q_OPT_VALID BIT(7)
462 #define ICE_AQ_VSI_PROP_OUTER_UP_VALID BIT(8)
463 #define ICE_AQ_VSI_PROP_ACL_VALID BIT(10)
464 #define ICE_AQ_VSI_PROP_FLOW_DIR_VALID BIT(11)
465 #define ICE_AQ_VSI_PROP_PASID_VALID BIT(12)
469 #define ICE_AQ_VSI_SW_FLAG_ALLOW_LB BIT(5)
470 #define ICE_AQ_VSI_SW_FLAG_LOCAL_LB BIT(6)
471 #define ICE_AQ_VSI_SW_FLAG_SRC_PRUNE BIT(7)
473 #define ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_S 0
474 #define ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_M (0xF << ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_S)
475 #define ICE_AQ_VSI_SW_FLAG_RX_VLAN_PRUNE_ENA BIT(0)
476 #define ICE_AQ_VSI_SW_FLAG_LAN_ENA BIT(4)
478 #define ICE_AQ_VSI_SW_VEB_STAT_ID_S 0
479 #define ICE_AQ_VSI_SW_VEB_STAT_ID_M (0x1F << ICE_AQ_VSI_SW_VEB_STAT_ID_S)
480 #define ICE_AQ_VSI_SW_VEB_STAT_ID_VALID BIT(5)
481 /* security section */
483 #define ICE_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD BIT(0)
484 #define ICE_AQ_VSI_SEC_FLAG_ENA_MAC_ANTI_SPOOF BIT(2)
485 #define ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S 4
486 #define ICE_AQ_VSI_SEC_TX_PRUNE_ENA_M (0xF << ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S)
487 #define ICE_AQ_VSI_SEC_TX_VLAN_PRUNE_ENA BIT(0)
490 __le16 port_based_inner_vlan; /* VLANS include priority bits */
491 u8 inner_vlan_reserved[2];
493 #define ICE_AQ_VSI_INNER_VLAN_TX_MODE_S 0
494 #define ICE_AQ_VSI_INNER_VLAN_TX_MODE_M (0x3 << ICE_AQ_VSI_INNER_VLAN_TX_MODE_S)
495 #define ICE_AQ_VSI_INNER_VLAN_TX_MODE_ACCEPTUNTAGGED 0x1
496 #define ICE_AQ_VSI_INNER_VLAN_TX_MODE_ACCEPTTAGGED 0x2
497 #define ICE_AQ_VSI_INNER_VLAN_TX_MODE_ALL 0x3
498 #define ICE_AQ_VSI_INNER_VLAN_INSERT_PVID BIT(2)
499 #define ICE_AQ_VSI_INNER_VLAN_EMODE_S 3
500 #define ICE_AQ_VSI_INNER_VLAN_EMODE_M (0x3 << ICE_AQ_VSI_INNER_VLAN_EMODE_S)
501 #define ICE_AQ_VSI_INNER_VLAN_EMODE_STR_BOTH (0x0 << ICE_AQ_VSI_INNER_VLAN_EMODE_S)
502 #define ICE_AQ_VSI_INNER_VLAN_EMODE_STR_UP (0x1 << ICE_AQ_VSI_INNER_VLAN_EMODE_S)
503 #define ICE_AQ_VSI_INNER_VLAN_EMODE_STR (0x2 << ICE_AQ_VSI_INNER_VLAN_EMODE_S)
504 #define ICE_AQ_VSI_INNER_VLAN_EMODE_NOTHING (0x3 << ICE_AQ_VSI_INNER_VLAN_EMODE_S)
505 #define ICE_AQ_VSI_INNER_VLAN_BLOCK_TX_DESC BIT(5)
506 u8 inner_vlan_reserved2[3];
507 /* ingress egress up sections */
508 __le32 ingress_table; /* bitmap, 3 bits per up */
509 #define ICE_AQ_VSI_UP_TABLE_UP0_S 0
510 #define ICE_AQ_VSI_UP_TABLE_UP0_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP0_S)
511 #define ICE_AQ_VSI_UP_TABLE_UP1_S 3
512 #define ICE_AQ_VSI_UP_TABLE_UP1_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP1_S)
513 #define ICE_AQ_VSI_UP_TABLE_UP2_S 6
514 #define ICE_AQ_VSI_UP_TABLE_UP2_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP2_S)
515 #define ICE_AQ_VSI_UP_TABLE_UP3_S 9
516 #define ICE_AQ_VSI_UP_TABLE_UP3_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP3_S)
517 #define ICE_AQ_VSI_UP_TABLE_UP4_S 12
518 #define ICE_AQ_VSI_UP_TABLE_UP4_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP4_S)
519 #define ICE_AQ_VSI_UP_TABLE_UP5_S 15
520 #define ICE_AQ_VSI_UP_TABLE_UP5_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP5_S)
521 #define ICE_AQ_VSI_UP_TABLE_UP6_S 18
522 #define ICE_AQ_VSI_UP_TABLE_UP6_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP6_S)
523 #define ICE_AQ_VSI_UP_TABLE_UP7_S 21
524 #define ICE_AQ_VSI_UP_TABLE_UP7_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP7_S)
525 __le32 egress_table; /* same defines as for ingress table */
526 /* outer tags section */
527 __le16 port_based_outer_vlan;
529 #define ICE_AQ_VSI_OUTER_VLAN_EMODE_S 0
530 #define ICE_AQ_VSI_OUTER_VLAN_EMODE_M (0x3 << ICE_AQ_VSI_OUTER_VLAN_EMODE_S)
531 #define ICE_AQ_VSI_OUTER_VLAN_EMODE_SHOW_BOTH 0x0
532 #define ICE_AQ_VSI_OUTER_VLAN_EMODE_SHOW_UP 0x1
533 #define ICE_AQ_VSI_OUTER_VLAN_EMODE_SHOW 0x2
534 #define ICE_AQ_VSI_OUTER_VLAN_EMODE_NOTHING 0x3
535 #define ICE_AQ_VSI_OUTER_TAG_TYPE_S 2
536 #define ICE_AQ_VSI_OUTER_TAG_TYPE_M (0x3 << ICE_AQ_VSI_OUTER_TAG_TYPE_S)
537 #define ICE_AQ_VSI_OUTER_TAG_NONE 0x0
538 #define ICE_AQ_VSI_OUTER_TAG_STAG 0x1
539 #define ICE_AQ_VSI_OUTER_TAG_VLAN_8100 0x2
540 #define ICE_AQ_VSI_OUTER_TAG_VLAN_9100 0x3
541 #define ICE_AQ_VSI_OUTER_VLAN_PORT_BASED_INSERT BIT(4)
542 #define ICE_AQ_VSI_OUTER_VLAN_PORT_BASED_ACCEPT_HOST BIT(6)
543 #define ICE_AQ_VSI_OUTER_VLAN_TX_MODE_S 5
544 #define ICE_AQ_VSI_OUTER_VLAN_TX_MODE_M (0x3 << ICE_AQ_VSI_OUTER_VLAN_TX_MODE_S)
545 #define ICE_AQ_VSI_OUTER_VLAN_TX_MODE_ACCEPTUNTAGGED 0x1
546 #define ICE_AQ_VSI_OUTER_VLAN_TX_MODE_ACCEPTTAGGED 0x2
547 #define ICE_AQ_VSI_OUTER_VLAN_TX_MODE_ALL 0x3
548 #define ICE_AQ_VSI_OUTER_VLAN_BLOCK_TX_DESC BIT(7)
549 u8 outer_vlan_reserved;
550 /* queue mapping section */
551 __le16 mapping_flags;
552 #define ICE_AQ_VSI_Q_MAP_CONTIG 0x0
553 #define ICE_AQ_VSI_Q_MAP_NONCONTIG BIT(0)
554 __le16 q_mapping[16];
555 #define ICE_AQ_VSI_Q_S 0
556 #define ICE_AQ_VSI_Q_M (0x7FF << ICE_AQ_VSI_Q_S)
557 __le16 tc_mapping[8];
558 #define ICE_AQ_VSI_TC_Q_OFFSET_S 0
559 #define ICE_AQ_VSI_TC_Q_OFFSET_M (0x7FF << ICE_AQ_VSI_TC_Q_OFFSET_S)
560 #define ICE_AQ_VSI_TC_Q_NUM_S 11
561 #define ICE_AQ_VSI_TC_Q_NUM_M (0xF << ICE_AQ_VSI_TC_Q_NUM_S)
562 /* queueing option section */
564 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_S 0
565 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_M (0x3 << ICE_AQ_VSI_Q_OPT_RSS_LUT_S)
566 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_VSI 0x0
567 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_PF 0x2
568 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_GBL 0x3
569 #define ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_S 2
570 #define ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_M (0xF << ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_S)
571 #define ICE_AQ_VSI_Q_OPT_RSS_HASH_S 6
572 #define ICE_AQ_VSI_Q_OPT_RSS_HASH_M (0x3 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S)
573 #define ICE_AQ_VSI_Q_OPT_RSS_TPLZ (0x0 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S)
574 #define ICE_AQ_VSI_Q_OPT_RSS_SYM_TPLZ (0x1 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S)
575 #define ICE_AQ_VSI_Q_OPT_RSS_XOR (0x2 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S)
576 #define ICE_AQ_VSI_Q_OPT_RSS_JHASH (0x3 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S)
578 #define ICE_AQ_VSI_Q_OPT_TC_OVR_S 0
579 #define ICE_AQ_VSI_Q_OPT_TC_OVR_M (0x1F << ICE_AQ_VSI_Q_OPT_TC_OVR_S)
580 #define ICE_AQ_VSI_Q_OPT_PROF_TC_OVR BIT(7)
582 #define ICE_AQ_VSI_Q_OPT_PE_FLTR_EN BIT(0)
583 u8 q_opt_reserved[3];
584 /* outer up section */
585 __le32 outer_up_table; /* same structure and defines as ingress tbl */
588 #define ICE_AQ_VSI_ACL_DEF_RX_PROF_S 0
589 #define ICE_AQ_VSI_ACL_DEF_RX_PROF_M (0xF << ICE_AQ_VSI_ACL_DEF_RX_PROF_S)
590 #define ICE_AQ_VSI_ACL_DEF_RX_TABLE_S 4
591 #define ICE_AQ_VSI_ACL_DEF_RX_TABLE_M (0xF << ICE_AQ_VSI_ACL_DEF_RX_TABLE_S)
592 #define ICE_AQ_VSI_ACL_DEF_TX_PROF_S 8
593 #define ICE_AQ_VSI_ACL_DEF_TX_PROF_M (0xF << ICE_AQ_VSI_ACL_DEF_TX_PROF_S)
594 #define ICE_AQ_VSI_ACL_DEF_TX_TABLE_S 12
595 #define ICE_AQ_VSI_ACL_DEF_TX_TABLE_M (0xF << ICE_AQ_VSI_ACL_DEF_TX_TABLE_S)
596 /* flow director section */
598 #define ICE_AQ_VSI_FD_ENABLE BIT(0)
599 #define ICE_AQ_VSI_FD_TX_AUTO_ENABLE BIT(1)
600 #define ICE_AQ_VSI_FD_PROG_ENABLE BIT(3)
601 __le16 max_fd_fltr_dedicated;
602 __le16 max_fd_fltr_shared;
604 #define ICE_AQ_VSI_FD_DEF_Q_S 0
605 #define ICE_AQ_VSI_FD_DEF_Q_M (0x7FF << ICE_AQ_VSI_FD_DEF_Q_S)
606 #define ICE_AQ_VSI_FD_DEF_GRP_S 12
607 #define ICE_AQ_VSI_FD_DEF_GRP_M (0x7 << ICE_AQ_VSI_FD_DEF_GRP_S)
608 __le16 fd_report_opt;
609 #define ICE_AQ_VSI_FD_REPORT_Q_S 0
610 #define ICE_AQ_VSI_FD_REPORT_Q_M (0x7FF << ICE_AQ_VSI_FD_REPORT_Q_S)
611 #define ICE_AQ_VSI_FD_DEF_PRIORITY_S 12
612 #define ICE_AQ_VSI_FD_DEF_PRIORITY_M (0x7 << ICE_AQ_VSI_FD_DEF_PRIORITY_S)
613 #define ICE_AQ_VSI_FD_DEF_DROP BIT(15)
616 #define ICE_AQ_VSI_PASID_ID_S 0
617 #define ICE_AQ_VSI_PASID_ID_M (0xFFFFF << ICE_AQ_VSI_PASID_ID_S)
618 #define ICE_AQ_VSI_PASID_ID_VALID BIT(31)
622 /* Add/update mirror rule - direct (0x0260) */
623 #define ICE_AQC_RULE_ID_VALID_S 7
624 #define ICE_AQC_RULE_ID_VALID_M (0x1 << ICE_AQC_RULE_ID_VALID_S)
625 #define ICE_AQC_RULE_ID_S 0
626 #define ICE_AQC_RULE_ID_M (0x3F << ICE_AQC_RULE_ID_S)
628 /* Following defines to be used while processing caller specified mirror list
631 /* Action: Byte.bit (1.7)
632 * 0 = Remove VSI from mirror rule
633 * 1 = Add VSI to mirror rule
635 #define ICE_AQC_RULE_ACT_S 15
636 #define ICE_AQC_RULE_ACT_M (0x1 << ICE_AQC_RULE_ACT_S)
637 /* Action: 1.2:0.0 = Mirrored VSI */
638 #define ICE_AQC_RULE_MIRRORED_VSI_S 0
639 #define ICE_AQC_RULE_MIRRORED_VSI_M (0x7FF << ICE_AQC_RULE_MIRRORED_VSI_S)
641 /* This is to be used by add/update mirror rule Admin Queue command.
642 * In case of add mirror rule - if rule ID is specified as
643 * INVAL_MIRROR_RULE_ID, new rule ID is allocated from shared pool.
644 * If specified rule_id is valid, then it is used. If specified rule_id
645 * is in use then new mirroring rule is added.
647 #define ICE_INVAL_MIRROR_RULE_ID 0xFFFF
649 struct ice_aqc_add_update_mir_rule {
653 #define ICE_AQC_RULE_TYPE_S 0
654 #define ICE_AQC_RULE_TYPE_M (0x7 << ICE_AQC_RULE_TYPE_S)
655 /* VPORT ingress/egress */
656 #define ICE_AQC_RULE_TYPE_VPORT_INGRESS 0x1
657 #define ICE_AQC_RULE_TYPE_VPORT_EGRESS 0x2
658 /* Physical port ingress mirroring.
659 * All traffic received by this port
661 #define ICE_AQC_RULE_TYPE_PPORT_INGRESS 0x6
662 /* Physical port egress mirroring. All traffic sent by this port */
663 #define ICE_AQC_RULE_TYPE_PPORT_EGRESS 0x7
665 /* Number of mirrored entries.
666 * The values are in the command buffer
670 /* Destination VSI */
676 /* Delete mirror rule - direct(0x0261) */
677 struct ice_aqc_delete_mir_rule {
681 /* Byte.bit: 20.0 = Keep allocation. If set VSI stays part of
682 * the PF allocated resources, otherwise it is returned to the
685 #define ICE_AQC_FLAG_KEEP_ALLOCD_S 0
686 #define ICE_AQC_FLAG_KEEP_ALLOCD_M (0x1 << ICE_AQC_FLAG_KEEP_ALLOCD_S)
692 /* Set/Get storm config - (direct 0x0280, 0x0281) */
693 /* This structure holds get storm configuration response and same structure
694 * is used to perform set_storm_cfg
696 struct ice_aqc_storm_cfg {
697 __le32 bcast_thresh_size;
698 __le32 mcast_thresh_size;
699 /* Bit 18:0 - Traffic upper threshold size
700 * Bit 31:19 - Reserved
702 #define ICE_AQ_THRESHOLD_S 0
703 #define ICE_AQ_THRESHOLD_M (0x7FFFF << ICE_AQ_THRESHOLD_S)
705 __le32 storm_ctrl_ctrl;
706 /* Bit 0: MDIPW - Drop Multicast packets in previous window
707 * Bit 1: MDICW - Drop multicast packets in current window
708 * Bit 2: BDIPW - Drop broadcast packets in previous window
709 * Bit 3: BDICW - Drop broadcast packets in current window
711 #define ICE_AQ_STORM_CTRL_MDIPW_DROP_MULTICAST BIT(0)
712 #define ICE_AQ_STORM_CTRL_MDICW_DROP_MULTICAST BIT(1)
713 #define ICE_AQ_STORM_CTRL_BDIPW_DROP_MULTICAST BIT(2)
714 #define ICE_AQ_STORM_CTRL_BDICW_DROP_MULTICAST BIT(3)
715 /* Bit 7:5 : Reserved */
716 /* Bit 27:8 : Interval - BSC/MSC Time-interval specification: The
717 * interval size for applying ingress broadcast or multicast storm
720 #define ICE_AQ_STORM_BSC_MSC_TIME_INTERVAL_S 8
721 #define ICE_AQ_STORM_BSC_MSC_TIME_INTERVAL_M \
722 (0xFFFFF << ICE_AQ_STORM_BSC_MSC_TIME_INTERVAL_S)
726 #define ICE_MAX_NUM_RECIPES 64
728 /* Add/Get Recipe (indirect 0x0290/0x0292) */
729 struct ice_aqc_add_get_recipe {
730 __le16 num_sub_recipes; /* Input in Add cmd, Output in Get cmd */
731 __le16 return_index; /* Input, used for Get cmd only */
737 struct ice_aqc_recipe_content {
739 #define ICE_AQ_RECIPE_ID_S 0
740 #define ICE_AQ_RECIPE_ID_M (0x3F << ICE_AQ_RECIPE_ID_S)
741 #define ICE_AQ_RECIPE_ID_IS_ROOT BIT(7)
742 #define ICE_AQ_SW_ID_LKUP_IDX 0
744 #define ICE_AQ_RECIPE_LKUP_DATA_S 0
745 #define ICE_AQ_RECIPE_LKUP_DATA_M (0x3F << ICE_AQ_RECIPE_LKUP_DATA_S)
746 #define ICE_AQ_RECIPE_LKUP_IGNORE BIT(7)
747 #define ICE_AQ_SW_ID_LKUP_MASK 0x00FF
750 #define ICE_AQ_RECIPE_RESULT_DATA_S 0
751 #define ICE_AQ_RECIPE_RESULT_DATA_M (0x3F << ICE_AQ_RECIPE_RESULT_DATA_S)
752 #define ICE_AQ_RECIPE_RESULT_EN BIT(7)
754 u8 act_ctrl_join_priority;
755 u8 act_ctrl_fwd_priority;
756 #define ICE_AQ_RECIPE_FWD_PRIORITY_S 0
757 #define ICE_AQ_RECIPE_FWD_PRIORITY_M (0xF << ICE_AQ_RECIPE_FWD_PRIORITY_S)
759 #define ICE_AQ_RECIPE_ACT_NEED_PASS_L2 BIT(0)
760 #define ICE_AQ_RECIPE_ACT_ALLOW_PASS_L2 BIT(1)
761 #define ICE_AQ_RECIPE_ACT_INV_ACT BIT(2)
762 #define ICE_AQ_RECIPE_ACT_PRUNE_INDX_S 4
763 #define ICE_AQ_RECIPE_ACT_PRUNE_INDX_M (0x3 << ICE_AQ_RECIPE_ACT_PRUNE_INDX_S)
766 #define ICE_AQ_RECIPE_DFLT_ACT_S 0
767 #define ICE_AQ_RECIPE_DFLT_ACT_M (0x7FFFF << ICE_AQ_RECIPE_DFLT_ACT_S)
768 #define ICE_AQ_RECIPE_DFLT_ACT_VALID BIT(31)
771 struct ice_aqc_recipe_data_elem {
774 #define ICE_AQ_RECIPE_WAS_UPDATED BIT(0)
778 struct ice_aqc_recipe_content content;
782 /* Set/Get Recipes to Profile Association (direct 0x0291/0x0293) */
783 struct ice_aqc_recipe_to_profile {
786 ice_declare_bitmap(recipe_assoc, ICE_MAX_NUM_RECIPES);
789 /* Add/Update/Remove/Get switch rules (indirect 0x02A0, 0x02A1, 0x02A2, 0x02A3)
791 struct ice_aqc_sw_rules {
792 /* ops: add switch rules, referring the number of rules.
793 * ops: update switch rules, referring the number of filters
794 * ops: remove switch rules, referring the entry index.
795 * ops: get switch rules, referring to the number of filters.
797 __le16 num_rules_fltr_entry_index;
803 /* Add/Update/Get/Remove lookup Rx/Tx command/response entry
804 * This structures describes the lookup rules and associated actions. "index"
805 * is returned as part of a response to a successful Add command, and can be
806 * used to identify the rule for Update/Get/Remove commands.
808 struct ice_sw_rule_lkup_rx_tx {
810 #define ICE_SW_RECIPE_LOGICAL_PORT_FWD 10
811 /* Source port for LOOKUP_RX and source VSI in case of LOOKUP_TX */
815 /* Bit 0:1 - Action type */
816 #define ICE_SINGLE_ACT_TYPE_S 0x00
817 #define ICE_SINGLE_ACT_TYPE_M (0x3 << ICE_SINGLE_ACT_TYPE_S)
819 /* Bit 2 - Loop back enable
822 #define ICE_SINGLE_ACT_LB_ENABLE BIT(2)
823 #define ICE_SINGLE_ACT_LAN_ENABLE BIT(3)
825 /* Action type = 0 - Forward to VSI or VSI list */
826 #define ICE_SINGLE_ACT_VSI_FORWARDING 0x0
828 #define ICE_SINGLE_ACT_VSI_ID_S 4
829 #define ICE_SINGLE_ACT_VSI_ID_M (0x3FF << ICE_SINGLE_ACT_VSI_ID_S)
830 #define ICE_SINGLE_ACT_VSI_LIST_ID_S 4
831 #define ICE_SINGLE_ACT_VSI_LIST_ID_M (0x3FF << ICE_SINGLE_ACT_VSI_LIST_ID_S)
832 /* This bit needs to be set if action is forward to VSI list */
833 #define ICE_SINGLE_ACT_VSI_LIST BIT(14)
834 #define ICE_SINGLE_ACT_VALID_BIT BIT(17)
835 #define ICE_SINGLE_ACT_DROP BIT(18)
837 /* Action type = 1 - Forward to Queue of Queue group */
838 #define ICE_SINGLE_ACT_TO_Q 0x1
839 #define ICE_SINGLE_ACT_Q_INDEX_S 4
840 #define ICE_SINGLE_ACT_Q_INDEX_M (0x7FF << ICE_SINGLE_ACT_Q_INDEX_S)
841 #define ICE_SINGLE_ACT_Q_REGION_S 15
842 #define ICE_SINGLE_ACT_Q_REGION_M (0x7 << ICE_SINGLE_ACT_Q_REGION_S)
843 #define ICE_SINGLE_ACT_Q_PRIORITY BIT(18)
845 /* Action type = 2 - Prune */
846 #define ICE_SINGLE_ACT_PRUNE 0x2
847 #define ICE_SINGLE_ACT_EGRESS BIT(15)
848 #define ICE_SINGLE_ACT_INGRESS BIT(16)
849 #define ICE_SINGLE_ACT_PRUNET BIT(17)
850 /* Bit 18 should be set to 0 for this action */
852 /* Action type = 2 - Pointer */
853 #define ICE_SINGLE_ACT_PTR 0x2
854 #define ICE_SINGLE_ACT_PTR_VAL_S 4
855 #define ICE_SINGLE_ACT_PTR_VAL_M (0x1FFF << ICE_SINGLE_ACT_PTR_VAL_S)
856 /* Bit 18 should be set to 1 */
857 #define ICE_SINGLE_ACT_PTR_BIT BIT(18)
859 /* Action type = 3 - Other actions. Last two bits
860 * are other action identifier
862 #define ICE_SINGLE_ACT_OTHER_ACTS 0x3
863 #define ICE_SINGLE_OTHER_ACT_IDENTIFIER_S 17
864 #define ICE_SINGLE_OTHER_ACT_IDENTIFIER_M \
865 (0x3 << ICE_SINGLE_OTHER_ACT_IDENTIFIER_S)
867 /* Bit 17:18 - Defines other actions */
868 /* Other action = 0 - Mirror VSI */
869 #define ICE_SINGLE_OTHER_ACT_MIRROR 0
870 #define ICE_SINGLE_ACT_MIRROR_VSI_ID_S 4
871 #define ICE_SINGLE_ACT_MIRROR_VSI_ID_M \
872 (0x3FF << ICE_SINGLE_ACT_MIRROR_VSI_ID_S)
874 /* Other action = 3 - Set Stat count */
875 #define ICE_SINGLE_OTHER_ACT_STAT_COUNT 3
876 #define ICE_SINGLE_ACT_STAT_COUNT_INDEX_S 4
877 #define ICE_SINGLE_ACT_STAT_COUNT_INDEX_M \
878 (0x7F << ICE_SINGLE_ACT_STAT_COUNT_INDEX_S)
880 __le16 index; /* The index of the rule in the lookup table */
881 /* Length and values of the header to be matched per recipe or
885 u8 hdr[STRUCT_HACK_VAR_LEN];
888 /* Add/Update/Remove large action command/response entry
889 * "index" is returned as part of a response to a successful Add command, and
890 * can be used to identify the action for Update/Get/Remove commands.
892 struct ice_sw_rule_lg_act {
893 __le16 index; /* Index in large action table */
895 /* Max number of large actions */
896 #define ICE_MAX_LG_ACT 4
897 /* Bit 0:1 - Action type */
898 #define ICE_LG_ACT_TYPE_S 0
899 #define ICE_LG_ACT_TYPE_M (0x7 << ICE_LG_ACT_TYPE_S)
901 /* Action type = 0 - Forward to VSI or VSI list */
902 #define ICE_LG_ACT_VSI_FORWARDING 0
903 #define ICE_LG_ACT_VSI_ID_S 3
904 #define ICE_LG_ACT_VSI_ID_M (0x3FF << ICE_LG_ACT_VSI_ID_S)
905 #define ICE_LG_ACT_VSI_LIST_ID_S 3
906 #define ICE_LG_ACT_VSI_LIST_ID_M (0x3FF << ICE_LG_ACT_VSI_LIST_ID_S)
907 /* This bit needs to be set if action is forward to VSI list */
908 #define ICE_LG_ACT_VSI_LIST BIT(13)
910 #define ICE_LG_ACT_VALID_BIT BIT(16)
912 /* Action type = 1 - Forward to Queue of Queue group */
913 #define ICE_LG_ACT_TO_Q 0x1
914 #define ICE_LG_ACT_Q_INDEX_S 3
915 #define ICE_LG_ACT_Q_INDEX_M (0x7FF << ICE_LG_ACT_Q_INDEX_S)
916 #define ICE_LG_ACT_Q_REGION_S 14
917 #define ICE_LG_ACT_Q_REGION_M (0x7 << ICE_LG_ACT_Q_REGION_S)
918 #define ICE_LG_ACT_Q_PRIORITY_SET BIT(17)
920 /* Action type = 2 - Prune */
921 #define ICE_LG_ACT_PRUNE 0x2
922 #define ICE_LG_ACT_EGRESS BIT(14)
923 #define ICE_LG_ACT_INGRESS BIT(15)
924 #define ICE_LG_ACT_PRUNET BIT(16)
926 /* Action type = 3 - Mirror VSI */
927 #define ICE_LG_OTHER_ACT_MIRROR 0x3
928 #define ICE_LG_ACT_MIRROR_VSI_ID_S 3
929 #define ICE_LG_ACT_MIRROR_VSI_ID_M (0x3FF << ICE_LG_ACT_MIRROR_VSI_ID_S)
931 /* Action type = 5 - Generic Value */
932 #define ICE_LG_ACT_GENERIC 0x5
933 #define ICE_LG_ACT_GENERIC_VALUE_S 3
934 #define ICE_LG_ACT_GENERIC_VALUE_M (0xFFFF << ICE_LG_ACT_GENERIC_VALUE_S)
935 #define ICE_LG_ACT_GENERIC_OFFSET_S 19
936 #define ICE_LG_ACT_GENERIC_OFFSET_M (0x7 << ICE_LG_ACT_GENERIC_OFFSET_S)
937 #define ICE_LG_ACT_GENERIC_PRIORITY_S 22
938 #define ICE_LG_ACT_GENERIC_PRIORITY_M (0x7 << ICE_LG_ACT_GENERIC_PRIORITY_S)
939 #define ICE_LG_ACT_GENERIC_OFF_RX_DESC_PROF_IDX 7
941 /* Action = 7 - Set Stat count */
942 #define ICE_LG_ACT_STAT_COUNT 0x7
943 #define ICE_LG_ACT_STAT_COUNT_S 3
944 #define ICE_LG_ACT_STAT_COUNT_M (0x7F << ICE_LG_ACT_STAT_COUNT_S)
945 __le32 act[STRUCT_HACK_VAR_LEN]; /* array of size for actions */
948 /* Add/Update/Remove VSI list command/response entry
949 * "index" is returned as part of a response to a successful Add command, and
950 * can be used to identify the VSI list for Update/Get/Remove commands.
952 struct ice_sw_rule_vsi_list {
953 __le16 index; /* Index of VSI/Prune list */
955 __le16 vsi[STRUCT_HACK_VAR_LEN]; /* Array of number_vsi VSI numbers */
959 /* Query VSI list command/response entry */
960 struct ice_sw_rule_vsi_list_query {
962 ice_declare_bitmap(vsi_list, ICE_MAX_VSI);
967 /* Add switch rule response:
968 * Content of return buffer is same as the input buffer. The status field and
969 * LUT index are updated as part of the response
971 struct ice_aqc_sw_rules_elem {
972 __le16 type; /* Switch rule type, one of T_... */
973 #define ICE_AQC_SW_RULES_T_LKUP_RX 0x0
974 #define ICE_AQC_SW_RULES_T_LKUP_TX 0x1
975 #define ICE_AQC_SW_RULES_T_LG_ACT 0x2
976 #define ICE_AQC_SW_RULES_T_VSI_LIST_SET 0x3
977 #define ICE_AQC_SW_RULES_T_VSI_LIST_CLEAR 0x4
978 #define ICE_AQC_SW_RULES_T_PRUNE_LIST_SET 0x5
979 #define ICE_AQC_SW_RULES_T_PRUNE_LIST_CLEAR 0x6
982 struct ice_sw_rule_lkup_rx_tx lkup_tx_rx;
983 struct ice_sw_rule_lg_act lg_act;
984 struct ice_sw_rule_vsi_list vsi_list;
985 struct ice_sw_rule_vsi_list_query vsi_list_query;
991 /* PFC Ignore (direct 0x0301)
992 * The command and response use the same descriptor structure
994 struct ice_aqc_pfc_ignore {
996 u8 cmd_flags; /* unused in response */
997 #define ICE_AQC_PFC_IGNORE_SET BIT(7)
998 #define ICE_AQC_PFC_IGNORE_CLEAR 0
1002 /* Set PFC Mode (direct 0x0303)
1003 * Query PFC Mode (direct 0x0302)
1005 struct ice_aqc_set_query_pfc_mode {
1007 /* For Set Command response, reserved in all other cases */
1008 #define ICE_AQC_PFC_NOT_CONFIGURED 0
1009 /* For Query Command response, reserved in all other cases */
1010 #define ICE_AQC_DCB_DIS 0
1011 #define ICE_AQC_PFC_VLAN_BASED_PFC 1
1012 #define ICE_AQC_PFC_DSCP_BASED_PFC 2
1016 /* Set DCB Parameters (direct 0x0306) */
1017 struct ice_aqc_set_dcb_params {
1018 u8 cmd_flags; /* unused in response */
1019 #define ICE_AQC_LINK_UP_DCB_CFG BIT(0)
1020 #define ICE_AQC_PERSIST_DCB_CFG BIT(1)
1021 u8 valid_flags; /* unused in response */
1022 #define ICE_AQC_LINK_UP_DCB_CFG_VALID BIT(0)
1023 #define ICE_AQC_PERSIST_DCB_CFG_VALID BIT(1)
1027 /* Get Default Topology (indirect 0x0400) */
1028 struct ice_aqc_get_topo {
1037 /* Update TSE (indirect 0x0403)
1038 * Get TSE (indirect 0x0404)
1039 * Add TSE (indirect 0x0401)
1040 * Delete TSE (indirect 0x040F)
1041 * Move TSE (indirect 0x0408)
1042 * Suspend Nodes (indirect 0x0409)
1043 * Resume Nodes (indirect 0x040A)
1045 struct ice_aqc_sched_elem_cmd {
1046 __le16 num_elem_req; /* Used by commands */
1047 __le16 num_elem_resp; /* Used by responses */
1053 struct ice_aqc_txsched_move_grp_info_hdr {
1054 __le32 src_parent_teid;
1055 __le32 dest_parent_teid;
1061 struct ice_aqc_move_elem {
1062 struct ice_aqc_txsched_move_grp_info_hdr hdr;
1063 __le32 teid[STRUCT_HACK_VAR_LEN];
1066 struct ice_aqc_elem_info_bw {
1067 __le16 bw_profile_idx;
1071 struct ice_aqc_txsched_elem {
1072 u8 elem_type; /* Special field, reserved for some aq calls */
1073 #define ICE_AQC_ELEM_TYPE_UNDEFINED 0x0
1074 #define ICE_AQC_ELEM_TYPE_ROOT_PORT 0x1
1075 #define ICE_AQC_ELEM_TYPE_TC 0x2
1076 #define ICE_AQC_ELEM_TYPE_SE_GENERIC 0x3
1077 #define ICE_AQC_ELEM_TYPE_ENTRY_POINT 0x4
1078 #define ICE_AQC_ELEM_TYPE_LEAF 0x5
1079 #define ICE_AQC_ELEM_TYPE_SE_PADDED 0x6
1081 #define ICE_AQC_ELEM_VALID_GENERIC BIT(0)
1082 #define ICE_AQC_ELEM_VALID_CIR BIT(1)
1083 #define ICE_AQC_ELEM_VALID_EIR BIT(2)
1084 #define ICE_AQC_ELEM_VALID_SHARED BIT(3)
1086 #define ICE_AQC_ELEM_GENERIC_MODE_M 0x1
1087 #define ICE_AQC_ELEM_GENERIC_PRIO_S 0x1
1088 #define ICE_AQC_ELEM_GENERIC_PRIO_M (0x7 << ICE_AQC_ELEM_GENERIC_PRIO_S)
1089 #define ICE_AQC_ELEM_GENERIC_SP_S 0x4
1090 #define ICE_AQC_ELEM_GENERIC_SP_M (0x1 << ICE_AQC_ELEM_GENERIC_SP_S)
1091 #define ICE_AQC_ELEM_GENERIC_ADJUST_VAL_S 0x5
1092 #define ICE_AQC_ELEM_GENERIC_ADJUST_VAL_M \
1093 (0x3 << ICE_AQC_ELEM_GENERIC_ADJUST_VAL_S)
1094 u8 flags; /* Special field, reserved for some aq calls */
1095 #define ICE_AQC_ELEM_FLAG_SUSPEND_M 0x1
1096 struct ice_aqc_elem_info_bw cir_bw;
1097 struct ice_aqc_elem_info_bw eir_bw;
1102 struct ice_aqc_txsched_elem_data {
1105 struct ice_aqc_txsched_elem data;
1108 struct ice_aqc_txsched_topo_grp_info_hdr {
1114 struct ice_aqc_add_elem {
1115 struct ice_aqc_txsched_topo_grp_info_hdr hdr;
1116 struct ice_aqc_txsched_elem_data generic[STRUCT_HACK_VAR_LEN];
1119 struct ice_aqc_get_topo_elem {
1120 struct ice_aqc_txsched_topo_grp_info_hdr hdr;
1121 struct ice_aqc_txsched_elem_data
1122 generic[ICE_AQC_TOPO_MAX_LEVEL_NUM];
1125 struct ice_aqc_delete_elem {
1126 struct ice_aqc_txsched_topo_grp_info_hdr hdr;
1127 __le32 teid[STRUCT_HACK_VAR_LEN];
1130 /* Query Port ETS (indirect 0x040E)
1132 * This indirect command is used to query port TC node configuration.
1134 struct ice_aqc_query_port_ets {
1141 struct ice_aqc_port_ets_elem {
1144 /* 3 bits for UP per TC 0-7, 4th byte reserved */
1147 __le32 port_eir_prof_id;
1148 __le32 port_cir_prof_id;
1149 /* 3 bits per Node priority to TC 0-7, 4th byte reserved */
1150 __le32 tc_node_prio;
1151 #define ICE_TC_NODE_PRIO_S 0x4
1153 __le32 tc_node_teid[8]; /* Used for response, reserved in command */
1156 /* Rate limiting profile for
1157 * Add RL profile (indirect 0x0410)
1158 * Query RL profile (indirect 0x0411)
1159 * Remove RL profile (indirect 0x0415)
1160 * These indirect commands acts on single or multiple
1161 * RL profiles with specified data.
1163 struct ice_aqc_rl_profile {
1164 __le16 num_profiles;
1165 __le16 num_processed; /* Only for response. Reserved in Command. */
1171 struct ice_aqc_rl_profile_elem {
1174 #define ICE_AQC_RL_PROFILE_TYPE_S 0x0
1175 #define ICE_AQC_RL_PROFILE_TYPE_M (0x3 << ICE_AQC_RL_PROFILE_TYPE_S)
1176 #define ICE_AQC_RL_PROFILE_TYPE_CIR 0
1177 #define ICE_AQC_RL_PROFILE_TYPE_EIR 1
1178 #define ICE_AQC_RL_PROFILE_TYPE_SRL 2
1179 /* The following flag is used for Query RL Profile Data */
1180 #define ICE_AQC_RL_PROFILE_INVAL_S 0x7
1181 #define ICE_AQC_RL_PROFILE_INVAL_M (0x1 << ICE_AQC_RL_PROFILE_INVAL_S)
1184 __le16 max_burst_size;
1186 __le16 wake_up_calc;
1190 /* Configure L2 Node CGD (indirect 0x0414)
1191 * This indirect command allows configuring a congestion domain for given L2
1192 * node TEIDs in the scheduler topology.
1194 struct ice_aqc_cfg_l2_node_cgd {
1195 __le16 num_l2_nodes;
1201 struct ice_aqc_cfg_l2_node_cgd_elem {
1207 /* Query Scheduler Resource Allocation (indirect 0x0412)
1208 * This indirect command retrieves the scheduler resources allocated by
1209 * EMP Firmware to the given PF.
1211 struct ice_aqc_query_txsched_res {
1217 struct ice_aqc_generic_sched_props {
1219 __le16 logical_levels;
1220 u8 flattening_bitmap;
1228 struct ice_aqc_layer_props {
1231 __le16 max_device_nodes;
1232 __le16 max_pf_nodes;
1234 __le16 max_sibl_grp_sz;
1235 __le16 max_cir_rl_profiles;
1236 __le16 max_eir_rl_profiles;
1237 __le16 max_srl_profiles;
1241 struct ice_aqc_query_txsched_res_resp {
1242 struct ice_aqc_generic_sched_props sched_props;
1243 struct ice_aqc_layer_props layer_props[ICE_AQC_TOPO_MAX_LEVEL_NUM];
1246 /* Query Node to Root Topology (indirect 0x0413)
1247 * This command uses ice_aqc_get_elem as its data buffer.
1249 struct ice_aqc_query_node_to_root {
1251 __le32 num_nodes; /* Response only */
1256 /* Get PHY capabilities (indirect 0x0600) */
1257 struct ice_aqc_get_phy_caps {
1261 /* 18.0 - Report qualified modules */
1262 #define ICE_AQC_GET_PHY_RQM BIT(0)
1263 /* 18.1 - 18.3 : Report mode
1264 * 000b - Report NVM capabilities
1265 * 001b - Report topology capabilities
1266 * 010b - Report SW configured
1267 * 100b - Report default capabilities
1269 #define ICE_AQC_REPORT_MODE_S 1
1270 #define ICE_AQC_REPORT_MODE_M (7 << ICE_AQC_REPORT_MODE_S)
1271 #define ICE_AQC_REPORT_TOPO_CAP_NO_MEDIA 0
1272 #define ICE_AQC_REPORT_TOPO_CAP_MEDIA BIT(1)
1273 #define ICE_AQC_REPORT_ACTIVE_CFG BIT(2)
1274 #define ICE_AQC_REPORT_DFLT_CFG BIT(3)
1280 /* This is #define of PHY type (Extended):
1281 * The first set of defines is for phy_type_low.
1283 #define ICE_PHY_TYPE_LOW_100BASE_TX BIT_ULL(0)
1284 #define ICE_PHY_TYPE_LOW_100M_SGMII BIT_ULL(1)
1285 #define ICE_PHY_TYPE_LOW_1000BASE_T BIT_ULL(2)
1286 #define ICE_PHY_TYPE_LOW_1000BASE_SX BIT_ULL(3)
1287 #define ICE_PHY_TYPE_LOW_1000BASE_LX BIT_ULL(4)
1288 #define ICE_PHY_TYPE_LOW_1000BASE_KX BIT_ULL(5)
1289 #define ICE_PHY_TYPE_LOW_1G_SGMII BIT_ULL(6)
1290 #define ICE_PHY_TYPE_LOW_2500BASE_T BIT_ULL(7)
1291 #define ICE_PHY_TYPE_LOW_2500BASE_X BIT_ULL(8)
1292 #define ICE_PHY_TYPE_LOW_2500BASE_KX BIT_ULL(9)
1293 #define ICE_PHY_TYPE_LOW_5GBASE_T BIT_ULL(10)
1294 #define ICE_PHY_TYPE_LOW_5GBASE_KR BIT_ULL(11)
1295 #define ICE_PHY_TYPE_LOW_10GBASE_T BIT_ULL(12)
1296 #define ICE_PHY_TYPE_LOW_10G_SFI_DA BIT_ULL(13)
1297 #define ICE_PHY_TYPE_LOW_10GBASE_SR BIT_ULL(14)
1298 #define ICE_PHY_TYPE_LOW_10GBASE_LR BIT_ULL(15)
1299 #define ICE_PHY_TYPE_LOW_10GBASE_KR_CR1 BIT_ULL(16)
1300 #define ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC BIT_ULL(17)
1301 #define ICE_PHY_TYPE_LOW_10G_SFI_C2C BIT_ULL(18)
1302 #define ICE_PHY_TYPE_LOW_25GBASE_T BIT_ULL(19)
1303 #define ICE_PHY_TYPE_LOW_25GBASE_CR BIT_ULL(20)
1304 #define ICE_PHY_TYPE_LOW_25GBASE_CR_S BIT_ULL(21)
1305 #define ICE_PHY_TYPE_LOW_25GBASE_CR1 BIT_ULL(22)
1306 #define ICE_PHY_TYPE_LOW_25GBASE_SR BIT_ULL(23)
1307 #define ICE_PHY_TYPE_LOW_25GBASE_LR BIT_ULL(24)
1308 #define ICE_PHY_TYPE_LOW_25GBASE_KR BIT_ULL(25)
1309 #define ICE_PHY_TYPE_LOW_25GBASE_KR_S BIT_ULL(26)
1310 #define ICE_PHY_TYPE_LOW_25GBASE_KR1 BIT_ULL(27)
1311 #define ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC BIT_ULL(28)
1312 #define ICE_PHY_TYPE_LOW_25G_AUI_C2C BIT_ULL(29)
1313 #define ICE_PHY_TYPE_LOW_40GBASE_CR4 BIT_ULL(30)
1314 #define ICE_PHY_TYPE_LOW_40GBASE_SR4 BIT_ULL(31)
1315 #define ICE_PHY_TYPE_LOW_40GBASE_LR4 BIT_ULL(32)
1316 #define ICE_PHY_TYPE_LOW_40GBASE_KR4 BIT_ULL(33)
1317 #define ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC BIT_ULL(34)
1318 #define ICE_PHY_TYPE_LOW_40G_XLAUI BIT_ULL(35)
1319 #define ICE_PHY_TYPE_LOW_50GBASE_CR2 BIT_ULL(36)
1320 #define ICE_PHY_TYPE_LOW_50GBASE_SR2 BIT_ULL(37)
1321 #define ICE_PHY_TYPE_LOW_50GBASE_LR2 BIT_ULL(38)
1322 #define ICE_PHY_TYPE_LOW_50GBASE_KR2 BIT_ULL(39)
1323 #define ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC BIT_ULL(40)
1324 #define ICE_PHY_TYPE_LOW_50G_LAUI2 BIT_ULL(41)
1325 #define ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC BIT_ULL(42)
1326 #define ICE_PHY_TYPE_LOW_50G_AUI2 BIT_ULL(43)
1327 #define ICE_PHY_TYPE_LOW_50GBASE_CP BIT_ULL(44)
1328 #define ICE_PHY_TYPE_LOW_50GBASE_SR BIT_ULL(45)
1329 #define ICE_PHY_TYPE_LOW_50GBASE_FR BIT_ULL(46)
1330 #define ICE_PHY_TYPE_LOW_50GBASE_LR BIT_ULL(47)
1331 #define ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4 BIT_ULL(48)
1332 #define ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC BIT_ULL(49)
1333 #define ICE_PHY_TYPE_LOW_50G_AUI1 BIT_ULL(50)
1334 #define ICE_PHY_TYPE_LOW_100GBASE_CR4 BIT_ULL(51)
1335 #define ICE_PHY_TYPE_LOW_100GBASE_SR4 BIT_ULL(52)
1336 #define ICE_PHY_TYPE_LOW_100GBASE_LR4 BIT_ULL(53)
1337 #define ICE_PHY_TYPE_LOW_100GBASE_KR4 BIT_ULL(54)
1338 #define ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC BIT_ULL(55)
1339 #define ICE_PHY_TYPE_LOW_100G_CAUI4 BIT_ULL(56)
1340 #define ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC BIT_ULL(57)
1341 #define ICE_PHY_TYPE_LOW_100G_AUI4 BIT_ULL(58)
1342 #define ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4 BIT_ULL(59)
1343 #define ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4 BIT_ULL(60)
1344 #define ICE_PHY_TYPE_LOW_100GBASE_CP2 BIT_ULL(61)
1345 #define ICE_PHY_TYPE_LOW_100GBASE_SR2 BIT_ULL(62)
1346 #define ICE_PHY_TYPE_LOW_100GBASE_DR BIT_ULL(63)
1347 #define ICE_PHY_TYPE_LOW_MAX_INDEX 63
1348 /* The second set of defines is for phy_type_high. */
1349 #define ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4 BIT_ULL(0)
1350 #define ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC BIT_ULL(1)
1351 #define ICE_PHY_TYPE_HIGH_100G_CAUI2 BIT_ULL(2)
1352 #define ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC BIT_ULL(3)
1353 #define ICE_PHY_TYPE_HIGH_100G_AUI2 BIT_ULL(4)
1354 #define ICE_PHY_TYPE_HIGH_MAX_INDEX 5
1356 struct ice_aqc_get_phy_caps_data {
1357 __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */
1358 __le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */
1360 #define ICE_AQC_PHY_EN_TX_LINK_PAUSE BIT(0)
1361 #define ICE_AQC_PHY_EN_RX_LINK_PAUSE BIT(1)
1362 #define ICE_AQC_PHY_LOW_POWER_MODE BIT(2)
1363 #define ICE_AQC_PHY_EN_LINK BIT(3)
1364 #define ICE_AQC_PHY_AN_MODE BIT(4)
1365 #define ICE_AQC_PHY_EN_MOD_QUAL BIT(5)
1366 #define ICE_AQC_PHY_EN_LESM BIT(6)
1367 #define ICE_AQC_PHY_EN_AUTO_FEC BIT(7)
1368 #define ICE_AQC_PHY_CAPS_MASK MAKEMASK(0xff, 0)
1369 u8 low_power_ctrl_an;
1370 #define ICE_AQC_PHY_EN_D3COLD_LOW_POWER_AUTONEG BIT(0)
1371 #define ICE_AQC_PHY_AN_EN_CLAUSE28 BIT(1)
1372 #define ICE_AQC_PHY_AN_EN_CLAUSE73 BIT(2)
1373 #define ICE_AQC_PHY_AN_EN_CLAUSE37 BIT(3)
1375 #define ICE_AQC_PHY_EEE_EN_100BASE_TX BIT(0)
1376 #define ICE_AQC_PHY_EEE_EN_1000BASE_T BIT(1)
1377 #define ICE_AQC_PHY_EEE_EN_10GBASE_T BIT(2)
1378 #define ICE_AQC_PHY_EEE_EN_1000BASE_KX BIT(3)
1379 #define ICE_AQC_PHY_EEE_EN_10GBASE_KR BIT(4)
1380 #define ICE_AQC_PHY_EEE_EN_25GBASE_KR BIT(5)
1381 #define ICE_AQC_PHY_EEE_EN_40GBASE_KR4 BIT(6)
1382 #define ICE_AQC_PHY_EEE_EN_50GBASE_KR2 BIT(7)
1383 #define ICE_AQC_PHY_EEE_EN_50GBASE_KR_PAM4 BIT(8)
1384 #define ICE_AQC_PHY_EEE_EN_100GBASE_KR4 BIT(9)
1385 #define ICE_AQC_PHY_EEE_EN_100GBASE_KR2_PAM4 BIT(10)
1387 u8 phy_id_oui[4]; /* PHY/Module ID connected on the port */
1389 u8 link_fec_options;
1390 #define ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN BIT(0)
1391 #define ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ BIT(1)
1392 #define ICE_AQC_PHY_FEC_25G_RS_528_REQ BIT(2)
1393 #define ICE_AQC_PHY_FEC_25G_KR_REQ BIT(3)
1394 #define ICE_AQC_PHY_FEC_25G_RS_544_REQ BIT(4)
1395 #define ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN BIT(6)
1396 #define ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN BIT(7)
1397 #define ICE_AQC_PHY_FEC_MASK MAKEMASK(0xdf, 0)
1398 u8 module_compliance_enforcement;
1399 #define ICE_AQC_MOD_ENFORCE_STRICT_MODE BIT(0)
1400 u8 extended_compliance_code;
1401 #define ICE_MODULE_TYPE_TOTAL_BYTE 3
1402 u8 module_type[ICE_MODULE_TYPE_TOTAL_BYTE];
1403 #define ICE_AQC_MOD_TYPE_BYTE0_SFP_PLUS 0xA0
1404 #define ICE_AQC_MOD_TYPE_BYTE0_QSFP_PLUS 0x80
1405 #define ICE_AQC_MOD_TYPE_IDENT 1
1406 #define ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_PASSIVE BIT(0)
1407 #define ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_ACTIVE BIT(1)
1408 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_SR BIT(4)
1409 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_LR BIT(5)
1410 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_LRM BIT(6)
1411 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_ER BIT(7)
1412 #define ICE_AQC_MOD_TYPE_BYTE2_SFP_PLUS 0xA0
1413 #define ICE_AQC_MOD_TYPE_BYTE2_QSFP_PLUS 0x86
1414 u8 qualified_module_count;
1415 u8 rsvd2[7]; /* Bytes 47:41 reserved */
1416 #define ICE_AQC_QUAL_MOD_COUNT_MAX 16
1423 } qual_modules[ICE_AQC_QUAL_MOD_COUNT_MAX];
1426 /* Set PHY capabilities (direct 0x0601)
1427 * NOTE: This command must be followed by setup link and restart auto-neg
1429 struct ice_aqc_set_phy_cfg {
1436 /* Set PHY config command data structure */
1437 struct ice_aqc_set_phy_cfg_data {
1438 __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */
1439 __le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */
1441 #define ICE_AQ_PHY_ENA_VALID_MASK MAKEMASK(0xef, 0)
1442 #define ICE_AQ_PHY_ENA_TX_PAUSE_ABILITY BIT(0)
1443 #define ICE_AQ_PHY_ENA_RX_PAUSE_ABILITY BIT(1)
1444 #define ICE_AQ_PHY_ENA_LOW_POWER BIT(2)
1445 #define ICE_AQ_PHY_ENA_LINK BIT(3)
1446 #define ICE_AQ_PHY_ENA_AUTO_LINK_UPDT BIT(5)
1447 #define ICE_AQ_PHY_ENA_LESM BIT(6)
1448 #define ICE_AQ_PHY_ENA_AUTO_FEC BIT(7)
1449 u8 low_power_ctrl_an;
1450 __le16 eee_cap; /* Value from ice_aqc_get_phy_caps */
1452 u8 link_fec_opt; /* Use defines from ice_aqc_get_phy_caps */
1453 u8 module_compliance_enforcement;
1456 /* Set MAC Config command data structure (direct 0x0603) */
1457 struct ice_aqc_set_mac_cfg {
1458 __le16 max_frame_size;
1460 #define ICE_AQ_SET_MAC_PACE_S 3
1461 #define ICE_AQ_SET_MAC_PACE_M (0xF << ICE_AQ_SET_MAC_PACE_S)
1462 #define ICE_AQ_SET_MAC_PACE_TYPE_M BIT(7)
1463 #define ICE_AQ_SET_MAC_PACE_TYPE_RATE 0
1464 #define ICE_AQ_SET_MAC_PACE_TYPE_FIXED ICE_AQ_SET_MAC_PACE_TYPE_M
1466 __le16 tx_tmr_value;
1467 __le16 fc_refresh_threshold;
1469 #define ICE_AQ_SET_MAC_AUTO_DROP_MASK BIT(0)
1470 #define ICE_AQ_SET_MAC_AUTO_DROP_NONE 0
1471 #define ICE_AQ_SET_MAC_AUTO_DROP_BLOCKING_PKTS BIT(0)
1475 /* Restart AN command data structure (direct 0x0605)
1476 * Also used for response, with only the lport_num field present.
1478 struct ice_aqc_restart_an {
1482 #define ICE_AQC_RESTART_AN_LINK_RESTART BIT(1)
1483 #define ICE_AQC_RESTART_AN_LINK_ENABLE BIT(2)
1487 /* Get link status (indirect 0x0607), also used for Link Status Event */
1488 struct ice_aqc_get_link_status {
1492 #define ICE_AQ_LSE_M 0x3
1493 #define ICE_AQ_LSE_NOP 0x0
1494 #define ICE_AQ_LSE_DIS 0x2
1495 #define ICE_AQ_LSE_ENA 0x3
1496 /* only response uses this flag */
1497 #define ICE_AQ_LSE_IS_ENABLED 0x1
1503 /* Get link status response data structure, also used for Link Status Event */
1504 struct ice_aqc_get_link_status_data {
1505 u8 topo_media_conflict;
1506 #define ICE_AQ_LINK_TOPO_CONFLICT BIT(0)
1507 #define ICE_AQ_LINK_MEDIA_CONFLICT BIT(1)
1508 #define ICE_AQ_LINK_TOPO_CORRUPT BIT(2)
1509 #define ICE_AQ_LINK_TOPO_UNREACH_PRT BIT(4)
1510 #define ICE_AQ_LINK_TOPO_UNDRUTIL_PRT BIT(5)
1511 #define ICE_AQ_LINK_TOPO_UNDRUTIL_MEDIA BIT(6)
1512 #define ICE_AQ_LINK_TOPO_UNSUPP_MEDIA BIT(7)
1514 #define ICE_AQ_LINK_CFG_ERR BIT(0)
1515 #define ICE_AQ_LINK_ACT_PORT_OPT_INVAL BIT(2)
1516 #define ICE_AQ_LINK_FEAT_ID_OR_CONFIG_ID_INVAL BIT(3)
1517 #define ICE_AQ_LINK_TOPO_CRITICAL_SDP_ERR BIT(4)
1518 #define ICE_AQ_LINK_MODULE_POWER_UNSUPPORTED BIT(5)
1519 #define ICE_AQ_LINK_EXTERNAL_PHY_LOAD_FAILURE BIT(6)
1520 #define ICE_AQ_LINK_INVAL_MAX_POWER_LIMIT BIT(7)
1522 #define ICE_AQ_LINK_UP BIT(0) /* Link Status */
1523 #define ICE_AQ_LINK_FAULT BIT(1)
1524 #define ICE_AQ_LINK_FAULT_TX BIT(2)
1525 #define ICE_AQ_LINK_FAULT_RX BIT(3)
1526 #define ICE_AQ_LINK_FAULT_REMOTE BIT(4)
1527 #define ICE_AQ_LINK_UP_PORT BIT(5) /* External Port Link Status */
1528 #define ICE_AQ_MEDIA_AVAILABLE BIT(6)
1529 #define ICE_AQ_SIGNAL_DETECT BIT(7)
1531 #define ICE_AQ_AN_COMPLETED BIT(0)
1532 #define ICE_AQ_LP_AN_ABILITY BIT(1)
1533 #define ICE_AQ_PD_FAULT BIT(2) /* Parallel Detection Fault */
1534 #define ICE_AQ_FEC_EN BIT(3)
1535 #define ICE_AQ_PHY_LOW_POWER BIT(4) /* Low Power State */
1536 #define ICE_AQ_LINK_PAUSE_TX BIT(5)
1537 #define ICE_AQ_LINK_PAUSE_RX BIT(6)
1538 #define ICE_AQ_QUALIFIED_MODULE BIT(7)
1540 #define ICE_AQ_LINK_PHY_TEMP_ALARM BIT(0)
1541 #define ICE_AQ_LINK_EXCESSIVE_ERRORS BIT(1) /* Excessive Link Errors */
1542 /* Port Tx Suspended */
1543 #define ICE_AQ_LINK_TX_S 2
1544 #define ICE_AQ_LINK_TX_M (0x03 << ICE_AQ_LINK_TX_S)
1545 #define ICE_AQ_LINK_TX_ACTIVE 0
1546 #define ICE_AQ_LINK_TX_DRAINED 1
1547 #define ICE_AQ_LINK_TX_FLUSHED 3
1549 #define ICE_AQ_LINK_LB_PHY_LCL BIT(0)
1550 #define ICE_AQ_LINK_LB_PHY_RMT BIT(1)
1551 #define ICE_AQ_LINK_LB_MAC_LCL BIT(2)
1552 #define ICE_AQ_LINK_LB_PHY_IDX_S 3
1553 #define ICE_AQ_LINK_LB_PHY_IDX_M (0x7 << ICE_AQ_LB_PHY_IDX_S)
1554 __le16 max_frame_size;
1556 #define ICE_AQ_LINK_25G_KR_FEC_EN BIT(0)
1557 #define ICE_AQ_LINK_25G_RS_528_FEC_EN BIT(1)
1558 #define ICE_AQ_LINK_25G_RS_544_FEC_EN BIT(2)
1559 #define ICE_AQ_FEC_MASK MAKEMASK(0x7, 0)
1561 #define ICE_AQ_CFG_PACING_S 3
1562 #define ICE_AQ_CFG_PACING_M (0xF << ICE_AQ_CFG_PACING_S)
1563 #define ICE_AQ_CFG_PACING_TYPE_M BIT(7)
1564 #define ICE_AQ_CFG_PACING_TYPE_AVG 0
1565 #define ICE_AQ_CFG_PACING_TYPE_FIXED ICE_AQ_CFG_PACING_TYPE_M
1566 /* External Device Power Ability */
1568 #define ICE_AQ_PWR_CLASS_M 0x3F
1569 #define ICE_AQ_LINK_PWR_BASET_LOW_HIGH 0
1570 #define ICE_AQ_LINK_PWR_BASET_HIGH 1
1571 #define ICE_AQ_LINK_PWR_QSFP_CLASS_1 0
1572 #define ICE_AQ_LINK_PWR_QSFP_CLASS_2 1
1573 #define ICE_AQ_LINK_PWR_QSFP_CLASS_3 2
1574 #define ICE_AQ_LINK_PWR_QSFP_CLASS_4 3
1576 #define ICE_AQ_LINK_SPEED_M 0x7FF
1577 #define ICE_AQ_LINK_SPEED_10MB BIT(0)
1578 #define ICE_AQ_LINK_SPEED_100MB BIT(1)
1579 #define ICE_AQ_LINK_SPEED_1000MB BIT(2)
1580 #define ICE_AQ_LINK_SPEED_2500MB BIT(3)
1581 #define ICE_AQ_LINK_SPEED_5GB BIT(4)
1582 #define ICE_AQ_LINK_SPEED_10GB BIT(5)
1583 #define ICE_AQ_LINK_SPEED_20GB BIT(6)
1584 #define ICE_AQ_LINK_SPEED_25GB BIT(7)
1585 #define ICE_AQ_LINK_SPEED_40GB BIT(8)
1586 #define ICE_AQ_LINK_SPEED_50GB BIT(9)
1587 #define ICE_AQ_LINK_SPEED_100GB BIT(10)
1588 #define ICE_AQ_LINK_SPEED_UNKNOWN BIT(15)
1589 __le32 reserved3; /* Aligns next field to 8-byte boundary */
1590 __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */
1591 __le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */
1594 /* Set event mask command (direct 0x0613) */
1595 struct ice_aqc_set_event_mask {
1599 #define ICE_AQ_LINK_EVENT_UPDOWN BIT(1)
1600 #define ICE_AQ_LINK_EVENT_MEDIA_NA BIT(2)
1601 #define ICE_AQ_LINK_EVENT_LINK_FAULT BIT(3)
1602 #define ICE_AQ_LINK_EVENT_PHY_TEMP_ALARM BIT(4)
1603 #define ICE_AQ_LINK_EVENT_EXCESSIVE_ERRORS BIT(5)
1604 #define ICE_AQ_LINK_EVENT_SIGNAL_DETECT BIT(6)
1605 #define ICE_AQ_LINK_EVENT_AN_COMPLETED BIT(7)
1606 #define ICE_AQ_LINK_EVENT_MODULE_QUAL_FAIL BIT(8)
1607 #define ICE_AQ_LINK_EVENT_PORT_TX_SUSPENDED BIT(9)
1608 #define ICE_AQ_LINK_EVENT_TOPO_CONFLICT BIT(10)
1609 #define ICE_AQ_LINK_EVENT_MEDIA_CONFLICT BIT(11)
1613 /* Set MAC Loopback command (direct 0x0620) */
1614 struct ice_aqc_set_mac_lb {
1616 #define ICE_AQ_MAC_LB_EN BIT(0)
1617 #define ICE_AQ_MAC_LB_OSC_CLK BIT(1)
1621 struct ice_aqc_link_topo_params {
1624 #define ICE_AQC_LINK_TOPO_PORT_NUM_VALID BIT(0)
1626 #define ICE_AQC_LINK_TOPO_NODE_TYPE_S 0
1627 #define ICE_AQC_LINK_TOPO_NODE_TYPE_M (0xF << ICE_AQC_LINK_TOPO_NODE_TYPE_S)
1628 #define ICE_AQC_LINK_TOPO_NODE_TYPE_PHY 0
1629 #define ICE_AQC_LINK_TOPO_NODE_TYPE_GPIO_CTRL 1
1630 #define ICE_AQC_LINK_TOPO_NODE_TYPE_MUX_CTRL 2
1631 #define ICE_AQC_LINK_TOPO_NODE_TYPE_LED_CTRL 3
1632 #define ICE_AQC_LINK_TOPO_NODE_TYPE_LED 4
1633 #define ICE_AQC_LINK_TOPO_NODE_TYPE_THERMAL 5
1634 #define ICE_AQC_LINK_TOPO_NODE_TYPE_CAGE 6
1635 #define ICE_AQC_LINK_TOPO_NODE_TYPE_MEZZ 7
1636 #define ICE_AQC_LINK_TOPO_NODE_TYPE_ID_EEPROM 8
1637 #define ICE_AQC_LINK_TOPO_NODE_CTX_S 4
1638 #define ICE_AQC_LINK_TOPO_NODE_CTX_M \
1639 (0xF << ICE_AQC_LINK_TOPO_NODE_CTX_S)
1640 #define ICE_AQC_LINK_TOPO_NODE_CTX_GLOBAL 0
1641 #define ICE_AQC_LINK_TOPO_NODE_CTX_BOARD 1
1642 #define ICE_AQC_LINK_TOPO_NODE_CTX_PORT 2
1643 #define ICE_AQC_LINK_TOPO_NODE_CTX_NODE 3
1644 #define ICE_AQC_LINK_TOPO_NODE_CTX_PROVIDED 4
1645 #define ICE_AQC_LINK_TOPO_NODE_CTX_OVERRIDE 5
1649 struct ice_aqc_link_topo_addr {
1650 struct ice_aqc_link_topo_params topo_params;
1652 #define ICE_AQC_LINK_TOPO_HANDLE_S 0
1653 #define ICE_AQC_LINK_TOPO_HANDLE_M (0x3FF << ICE_AQC_LINK_TOPO_HANDLE_S)
1654 /* Used to decode the handle field */
1655 #define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_M BIT(9)
1656 #define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_LOM BIT(9)
1657 #define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_MEZZ 0
1658 #define ICE_AQC_LINK_TOPO_HANDLE_NODE_S 0
1659 /* In case of a Mezzanine type */
1660 #define ICE_AQC_LINK_TOPO_HANDLE_MEZZ_NODE_M \
1661 (0x3F << ICE_AQC_LINK_TOPO_HANDLE_NODE_S)
1662 #define ICE_AQC_LINK_TOPO_HANDLE_MEZZ_S 6
1663 #define ICE_AQC_LINK_TOPO_HANDLE_MEZZ_M (0x7 << ICE_AQC_LINK_TOPO_HANDLE_MEZZ_S)
1664 /* In case of a LOM type */
1665 #define ICE_AQC_LINK_TOPO_HANDLE_LOM_NODE_M \
1666 (0x1FF << ICE_AQC_LINK_TOPO_HANDLE_NODE_S)
1669 /* Get Link Topology Handle (direct, 0x06E0) */
1670 struct ice_aqc_get_link_topo {
1671 struct ice_aqc_link_topo_addr addr;
1673 #define ICE_ACQ_GET_LINK_TOPO_NODE_NR_PCA9575 0x21
1677 /* Read/Write I2C (direct, 0x06E2/0x06E3) */
1678 struct ice_aqc_i2c {
1679 struct ice_aqc_link_topo_addr topo_addr;
1682 #define ICE_AQC_I2C_DATA_SIZE_S 0
1683 #define ICE_AQC_I2C_DATA_SIZE_M (0xF << ICE_AQC_I2C_DATA_SIZE_S)
1684 #define ICE_AQC_I2C_ADDR_TYPE_M BIT(4)
1685 #define ICE_AQC_I2C_ADDR_TYPE_7BIT 0
1686 #define ICE_AQC_I2C_ADDR_TYPE_10BIT ICE_AQC_I2C_ADDR_TYPE_M
1687 #define ICE_AQC_I2C_DATA_OFFSET_S 5
1688 #define ICE_AQC_I2C_DATA_OFFSET_M (0x3 << ICE_AQC_I2C_DATA_OFFSET_S)
1689 #define ICE_AQC_I2C_USE_REPEATED_START BIT(7)
1691 __le16 i2c_bus_addr;
1692 #define ICE_AQC_I2C_ADDR_7BIT_MASK 0x7F
1693 #define ICE_AQC_I2C_ADDR_10BIT_MASK 0x3FF
1694 u8 i2c_data[4]; /* Used only by write command, reserved in read. */
1697 /* Read I2C Response (direct, 0x06E2) */
1698 struct ice_aqc_read_i2c_resp {
1702 /* Set Port Identification LED (direct, 0x06E9) */
1703 struct ice_aqc_set_port_id_led {
1706 #define ICE_AQC_PORT_ID_PORT_NUM_VALID BIT(0)
1708 #define ICE_AQC_PORT_IDENT_LED_BLINK BIT(0)
1709 #define ICE_AQC_PORT_IDENT_LED_ORIG 0
1713 /* Set/Get GPIO (direct, 0x06EC/0x06ED) */
1714 struct ice_aqc_gpio {
1715 __le16 gpio_ctrl_handle;
1716 #define ICE_AQC_GPIO_HANDLE_S 0
1717 #define ICE_AQC_GPIO_HANDLE_M (0x3FF << ICE_AQC_GPIO_HANDLE_S)
1723 /* Read/Write SFF EEPROM command (indirect 0x06EE) */
1724 struct ice_aqc_sff_eeprom {
1727 #define ICE_AQC_SFF_PORT_NUM_VALID BIT(0)
1728 __le16 i2c_bus_addr;
1729 #define ICE_AQC_SFF_I2CBUS_7BIT_M 0x7F
1730 #define ICE_AQC_SFF_I2CBUS_10BIT_M 0x3FF
1731 #define ICE_AQC_SFF_I2CBUS_TYPE_M BIT(10)
1732 #define ICE_AQC_SFF_I2CBUS_TYPE_7BIT 0
1733 #define ICE_AQC_SFF_I2CBUS_TYPE_10BIT ICE_AQC_SFF_I2CBUS_TYPE_M
1734 #define ICE_AQC_SFF_SET_EEPROM_PAGE_S 11
1735 #define ICE_AQC_SFF_SET_EEPROM_PAGE_M (0x3 << ICE_AQC_SFF_SET_EEPROM_PAGE_S)
1736 #define ICE_AQC_SFF_NO_PAGE_CHANGE 0
1737 #define ICE_AQC_SFF_SET_23_ON_MISMATCH 1
1738 #define ICE_AQC_SFF_SET_22_ON_MISMATCH 2
1739 #define ICE_AQC_SFF_IS_WRITE BIT(15)
1740 __le16 i2c_mem_addr;
1742 #define ICE_AQC_SFF_EEPROM_BANK_S 0
1743 #define ICE_AQC_SFF_EEPROM_BANK_M (0xFF << ICE_AQC_SFF_EEPROM_BANK_S)
1744 #define ICE_AQC_SFF_EEPROM_PAGE_S 8
1745 #define ICE_AQC_SFF_EEPROM_PAGE_M (0xFF << ICE_AQC_SFF_EEPROM_PAGE_S)
1750 /* SW Set GPIO command (indirect 0x6EF)
1751 * SW Get GPIO command (indirect 0x6F0)
1753 struct ice_aqc_sw_gpio {
1754 __le16 gpio_ctrl_handle;
1755 #define ICE_AQC_SW_GPIO_CONTROLLER_HANDLE_S 0
1756 #define ICE_AQC_SW_GPIO_CONTROLLER_HANDLE_M (0x3FF << ICE_AQC_SW_GPIO_CONTROLLER_HANDLE_S)
1758 #define ICE_AQC_SW_GPIO_NUMBER_S 0
1759 #define ICE_AQC_SW_GPIO_NUMBER_M (0x1F << ICE_AQC_SW_GPIO_NUMBER_S)
1761 #define ICE_AQC_SW_GPIO_PARAMS_DIRECTION BIT(1)
1762 #define ICE_AQC_SW_GPIO_PARAMS_VALUE BIT(0)
1766 /* Program Topology Device NVM (direct, 0x06F2) */
1767 struct ice_aqc_prog_topo_dev_nvm {
1768 struct ice_aqc_link_topo_params topo_params;
1772 /* Read Topology Device NVM (direct, 0x06F3) */
1773 struct ice_aqc_read_topo_dev_nvm {
1774 struct ice_aqc_link_topo_params topo_params;
1775 __le32 start_address;
1776 #define ICE_AQC_READ_TOPO_DEV_NVM_DATA_READ_SIZE 8
1777 u8 data_read[ICE_AQC_READ_TOPO_DEV_NVM_DATA_READ_SIZE];
1780 /* NVM Read command (indirect 0x0701)
1781 * NVM Erase commands (direct 0x0702)
1782 * NVM Write commands (indirect 0x0703)
1783 * NVM Write Activate commands (direct 0x0707)
1784 * NVM Shadow RAM Dump commands (direct 0x0707)
1786 struct ice_aqc_nvm {
1787 #define ICE_AQC_NVM_MAX_OFFSET 0xFFFFFF
1789 u8 offset_high; /* For Write Activate offset_high is used as flags2 */
1791 #define ICE_AQC_NVM_LAST_CMD BIT(0)
1792 #define ICE_AQC_NVM_PCIR_REQ BIT(0) /* Used by NVM Write reply */
1793 #define ICE_AQC_NVM_PRESERVATION_S 1 /* Used by NVM Write Activate only */
1794 #define ICE_AQC_NVM_PRESERVATION_M (3 << ICE_AQC_NVM_PRESERVATION_S)
1795 #define ICE_AQC_NVM_NO_PRESERVATION (0 << ICE_AQC_NVM_PRESERVATION_S)
1796 #define ICE_AQC_NVM_PRESERVE_ALL BIT(1)
1797 #define ICE_AQC_NVM_FACTORY_DEFAULT (2 << ICE_AQC_NVM_PRESERVATION_S)
1798 #define ICE_AQC_NVM_PRESERVE_SELECTED (3 << ICE_AQC_NVM_PRESERVATION_S)
1799 #define ICE_AQC_NVM_ACTIV_SEL_NVM BIT(3) /* Write Activate/SR Dump only */
1800 #define ICE_AQC_NVM_ACTIV_SEL_OROM BIT(4)
1801 #define ICE_AQC_NVM_ACTIV_SEL_NETLIST BIT(5)
1802 #define ICE_AQC_NVM_SPECIAL_UPDATE BIT(6)
1803 #define ICE_AQC_NVM_REVERT_LAST_ACTIV BIT(6) /* Write Activate only */
1804 #define ICE_AQC_NVM_ACTIV_SEL_MASK MAKEMASK(0x7, 3)
1805 #define ICE_AQC_NVM_FLASH_ONLY BIT(7)
1806 #define ICE_AQC_NVM_POR_FLAG 0 /* Used by NVM Write completion on ARQ */
1807 #define ICE_AQC_NVM_PERST_FLAG 1
1808 #define ICE_AQC_NVM_EMPR_FLAG 2
1809 #define ICE_AQC_NVM_EMPR_ENA BIT(0)
1810 __le16 module_typeid;
1812 #define ICE_AQC_NVM_ERASE_LEN 0xFFFF
1817 /* NVM Module_Type ID, needed offset and read_len for struct ice_aqc_nvm. */
1818 #define ICE_AQC_NVM_SECTOR_UNIT 4096 /* In Bytes */
1819 #define ICE_AQC_NVM_WORD_UNIT 2 /* In Bytes */
1821 #define ICE_AQC_NVM_START_POINT 0
1822 #define ICE_AQC_NVM_EMP_SR_PTR_OFFSET 0x90
1823 #define ICE_AQC_NVM_EMP_SR_PTR_RD_LEN 2 /* In Bytes */
1824 #define ICE_AQC_NVM_EMP_SR_PTR_M MAKEMASK(0x7FFF, 0)
1825 #define ICE_AQC_NVM_EMP_SR_PTR_TYPE_S 15
1826 #define ICE_AQC_NVM_EMP_SR_PTR_TYPE_M BIT(15)
1827 #define ICE_AQC_NVM_EMP_SR_PTR_TYPE_SECTOR 1
1829 #define ICE_AQC_NVM_LLDP_CFG_PTR_OFFSET 0x46
1830 #define ICE_AQC_NVM_LLDP_CFG_HEADER_LEN 2 /* In Bytes */
1831 #define ICE_AQC_NVM_LLDP_CFG_PTR_RD_LEN 2 /* In Bytes */
1833 #define ICE_AQC_NVM_LLDP_PRESERVED_MOD_ID 0x129
1834 #define ICE_AQC_NVM_CUR_LLDP_PERSIST_RD_OFFSET 2 /* In Bytes */
1835 #define ICE_AQC_NVM_LLDP_STATUS_M MAKEMASK(0xF, 0)
1836 #define ICE_AQC_NVM_LLDP_STATUS_M_LEN 4 /* In Bits */
1837 #define ICE_AQC_NVM_LLDP_STATUS_RD_LEN 4 /* In Bytes */
1839 /* Used for 0x0704 as well as for 0x0705 commands */
1840 struct ice_aqc_nvm_cfg {
1842 #define ICE_AQC_ANVM_MULTIPLE_ELEMS BIT(0)
1843 #define ICE_AQC_ANVM_IMMEDIATE_FIELD BIT(1)
1844 #define ICE_AQC_ANVM_NEW_CFG BIT(2)
1853 struct ice_aqc_nvm_cfg_data {
1855 __le16 field_options;
1859 /* NVM Checksum Command (direct, 0x0706) */
1860 struct ice_aqc_nvm_checksum {
1862 #define ICE_AQC_NVM_CHECKSUM_VERIFY BIT(0)
1863 #define ICE_AQC_NVM_CHECKSUM_RECALC BIT(1)
1865 __le16 checksum; /* Used only by response */
1866 #define ICE_AQC_NVM_CHECKSUM_CORRECT 0xBABA
1870 /* Get LLDP MIB (indirect 0x0A00)
1871 * Note: This is also used by the LLDP MIB Change Event (0x0A01)
1872 * as the format is the same.
1874 struct ice_aqc_lldp_get_mib {
1876 #define ICE_AQ_LLDP_MIB_TYPE_S 0
1877 #define ICE_AQ_LLDP_MIB_TYPE_M (0x3 << ICE_AQ_LLDP_MIB_TYPE_S)
1878 #define ICE_AQ_LLDP_MIB_LOCAL 0
1879 #define ICE_AQ_LLDP_MIB_REMOTE 1
1880 #define ICE_AQ_LLDP_MIB_LOCAL_AND_REMOTE 2
1881 #define ICE_AQ_LLDP_BRID_TYPE_S 2
1882 #define ICE_AQ_LLDP_BRID_TYPE_M (0x3 << ICE_AQ_LLDP_BRID_TYPE_S)
1883 #define ICE_AQ_LLDP_BRID_TYPE_NEAREST_BRID 0
1884 #define ICE_AQ_LLDP_BRID_TYPE_NON_TPMR 1
1885 /* Tx pause flags in the 0xA01 event use ICE_AQ_LLDP_TX_* */
1886 #define ICE_AQ_LLDP_TX_S 0x4
1887 #define ICE_AQ_LLDP_TX_M (0x03 << ICE_AQ_LLDP_TX_S)
1888 #define ICE_AQ_LLDP_TX_ACTIVE 0
1889 #define ICE_AQ_LLDP_TX_SUSPENDED 1
1890 #define ICE_AQ_LLDP_TX_FLUSHED 3
1891 /* The following bytes are reserved for the Get LLDP MIB command (0x0A00)
1892 * and in the LLDP MIB Change Event (0x0A01). They are valid for the
1893 * Get LLDP MIB (0x0A00) response only.
1903 /* Configure LLDP MIB Change Event (direct 0x0A01) */
1904 /* For MIB Change Event use ice_aqc_lldp_get_mib structure above */
1905 struct ice_aqc_lldp_set_mib_change {
1907 #define ICE_AQ_LLDP_MIB_UPDATE_ENABLE 0x0
1908 #define ICE_AQ_LLDP_MIB_UPDATE_DIS 0x1
1912 /* Add LLDP TLV (indirect 0x0A02)
1913 * Delete LLDP TLV (indirect 0x0A04)
1915 struct ice_aqc_lldp_add_delete_tlv {
1916 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */
1924 /* Update LLDP TLV (indirect 0x0A03) */
1925 struct ice_aqc_lldp_update_tlv {
1926 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */
1935 /* Stop LLDP (direct 0x0A05) */
1936 struct ice_aqc_lldp_stop {
1938 #define ICE_AQ_LLDP_AGENT_STATE_MASK BIT(0)
1939 #define ICE_AQ_LLDP_AGENT_STOP 0x0
1940 #define ICE_AQ_LLDP_AGENT_SHUTDOWN ICE_AQ_LLDP_AGENT_STATE_MASK
1941 #define ICE_AQ_LLDP_AGENT_PERSIST_DIS BIT(1)
1945 /* Start LLDP (direct 0x0A06) */
1946 struct ice_aqc_lldp_start {
1948 #define ICE_AQ_LLDP_AGENT_START BIT(0)
1949 #define ICE_AQ_LLDP_AGENT_PERSIST_ENA BIT(1)
1953 /* Get CEE DCBX Oper Config (0x0A07)
1954 * The command uses the generic descriptor struct and
1955 * returns the struct below as an indirect response.
1957 struct ice_aqc_get_cee_dcb_cfg_resp {
1962 __le16 oper_app_prio;
1963 #define ICE_AQC_CEE_APP_FCOE_S 0
1964 #define ICE_AQC_CEE_APP_FCOE_M (0x7 << ICE_AQC_CEE_APP_FCOE_S)
1965 #define ICE_AQC_CEE_APP_ISCSI_S 3
1966 #define ICE_AQC_CEE_APP_ISCSI_M (0x7 << ICE_AQC_CEE_APP_ISCSI_S)
1967 #define ICE_AQC_CEE_APP_FIP_S 8
1968 #define ICE_AQC_CEE_APP_FIP_M (0x7 << ICE_AQC_CEE_APP_FIP_S)
1970 #define ICE_AQC_CEE_PG_STATUS_S 0
1971 #define ICE_AQC_CEE_PG_STATUS_M (0x7 << ICE_AQC_CEE_PG_STATUS_S)
1972 #define ICE_AQC_CEE_PFC_STATUS_S 3
1973 #define ICE_AQC_CEE_PFC_STATUS_M (0x7 << ICE_AQC_CEE_PFC_STATUS_S)
1974 #define ICE_AQC_CEE_FCOE_STATUS_S 8
1975 #define ICE_AQC_CEE_FCOE_STATUS_M (0x7 << ICE_AQC_CEE_FCOE_STATUS_S)
1976 #define ICE_AQC_CEE_ISCSI_STATUS_S 11
1977 #define ICE_AQC_CEE_ISCSI_STATUS_M (0x7 << ICE_AQC_CEE_ISCSI_STATUS_S)
1978 #define ICE_AQC_CEE_FIP_STATUS_S 16
1979 #define ICE_AQC_CEE_FIP_STATUS_M (0x7 << ICE_AQC_CEE_FIP_STATUS_S)
1983 /* Set Local LLDP MIB (indirect 0x0A08)
1984 * Used to replace the local MIB of a given LLDP agent. e.g. DCBX
1986 struct ice_aqc_lldp_set_local_mib {
1988 #define SET_LOCAL_MIB_TYPE_DCBX_M BIT(0)
1989 #define SET_LOCAL_MIB_TYPE_LOCAL_MIB 0
1990 #define SET_LOCAL_MIB_TYPE_CEE_M BIT(1)
1991 #define SET_LOCAL_MIB_TYPE_CEE_WILLING 0
1992 #define SET_LOCAL_MIB_TYPE_CEE_NON_WILLING SET_LOCAL_MIB_TYPE_CEE_M
2000 struct ice_aqc_lldp_set_local_mib_resp {
2002 #define SET_LOCAL_MIB_RESP_EVENT_M BIT(0)
2003 #define SET_LOCAL_MIB_RESP_MIB_CHANGE_SILENT 0
2004 #define SET_LOCAL_MIB_RESP_MIB_CHANGE_EVENT SET_LOCAL_MIB_RESP_EVENT_M
2008 /* Stop/Start LLDP Agent (direct 0x0A09)
2009 * Used for stopping/starting specific LLDP agent. e.g. DCBX.
2010 * The same structure is used for the response, with the command field
2011 * being used as the status field.
2013 struct ice_aqc_lldp_stop_start_specific_agent {
2015 #define ICE_AQC_START_STOP_AGENT_M BIT(0)
2016 #define ICE_AQC_START_STOP_AGENT_STOP_DCBX 0
2017 #define ICE_AQC_START_STOP_AGENT_START_DCBX ICE_AQC_START_STOP_AGENT_M
2021 /* LLDP Filter Control (direct 0x0A0A) */
2022 struct ice_aqc_lldp_filter_ctrl {
2024 #define ICE_AQC_LLDP_FILTER_ACTION_M MAKEMASK(3, 0)
2025 #define ICE_AQC_LLDP_FILTER_ACTION_ADD 0x0
2026 #define ICE_AQC_LLDP_FILTER_ACTION_DELETE 0x1
2027 #define ICE_AQC_LLDP_FILTER_ACTION_UPDATE 0x2
2033 /* Get/Set RSS key (indirect 0x0B04/0x0B02) */
2034 struct ice_aqc_get_set_rss_key {
2035 #define ICE_AQC_GSET_RSS_KEY_VSI_VALID BIT(15)
2036 #define ICE_AQC_GSET_RSS_KEY_VSI_ID_S 0
2037 #define ICE_AQC_GSET_RSS_KEY_VSI_ID_M (0x3FF << ICE_AQC_GSET_RSS_KEY_VSI_ID_S)
2044 #define ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE 0x28
2045 #define ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE 0xC
2046 #define ICE_GET_SET_RSS_KEY_EXTEND_KEY_SIZE \
2047 (ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE + \
2048 ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE)
2051 * struct ice_aqc_get_set_rss_keys - Get/Set RSS hash key command buffer
2052 * @standard_rss_key: 40 most significant bytes of hash key
2053 * @extended_hash_key: 12 least significant bytes of hash key
2055 * Set/Get 40 byte hash key using standard_rss_key field, and set
2056 * extended_hash_key field to zero. Set/Get 52 byte hash key using
2057 * standard_rss_key field for 40 most significant bytes and the
2058 * extended_hash_key field for the 12 least significant bytes of hash key.
2060 struct ice_aqc_get_set_rss_keys {
2061 u8 standard_rss_key[ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE];
2062 u8 extended_hash_key[ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE];
2065 /* Get/Set RSS LUT (indirect 0x0B05/0x0B03) */
2066 struct ice_aqc_get_set_rss_lut {
2067 #define ICE_AQC_GSET_RSS_LUT_VSI_VALID BIT(15)
2068 #define ICE_AQC_GSET_RSS_LUT_VSI_ID_S 0
2069 #define ICE_AQC_GSET_RSS_LUT_VSI_ID_M (0x3FF << ICE_AQC_GSET_RSS_LUT_VSI_ID_S)
2071 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S 0
2072 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_M \
2073 (0x3 << ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S)
2075 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_VSI 0
2076 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF 1
2077 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL 2
2079 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S 2
2080 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M \
2081 (0x3 << ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S)
2083 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128 128
2084 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128_FLAG 0
2085 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512 512
2086 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512_FLAG 1
2087 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K 2048
2088 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K_FLAG 2
2090 #define ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S 4
2091 #define ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_M \
2092 (0xF << ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S)
2100 /* Clear FD Table Command (direct, 0x0B06) */
2101 struct ice_aqc_clear_fd_table {
2103 #define CL_FD_VM_VF_TYPE_VSI_IDX 1
2104 #define CL_FD_VM_VF_TYPE_PF_IDX 2
2110 /* Allocate ACL table (indirect 0x0C10) */
2111 #define ICE_AQC_ACL_KEY_WIDTH 40
2112 #define ICE_AQC_ACL_KEY_WIDTH_BYTES 5
2113 #define ICE_AQC_ACL_TCAM_DEPTH 512
2114 #define ICE_ACL_ENTRY_ALLOC_UNIT 64
2115 #define ICE_AQC_MAX_CONCURRENT_ACL_TBL 15
2116 #define ICE_AQC_MAX_ACTION_MEMORIES 20
2117 #define ICE_AQC_MAX_ACTION_ENTRIES 512
2118 #define ICE_AQC_ACL_SLICES 16
2119 #define ICE_AQC_ALLOC_ID_LESS_THAN_4K 0x1000
2120 /* The ACL block supports up to 8 actions per a single output. */
2121 #define ICE_AQC_TBL_MAX_ACTION_PAIRS 4
2123 #define ICE_AQC_MAX_TCAM_ALLOC_UNITS (ICE_AQC_ACL_TCAM_DEPTH / \
2124 ICE_ACL_ENTRY_ALLOC_UNIT)
2125 #define ICE_AQC_ACL_ALLOC_UNITS (ICE_AQC_ACL_SLICES * \
2126 ICE_AQC_MAX_TCAM_ALLOC_UNITS)
2128 struct ice_aqc_acl_alloc_table {
2131 u8 act_pairs_per_entry;
2132 /* For non-concurrent table allocation, this field needs
2133 * to be set to zero(0) otherwise it shall specify the
2134 * amount of concurrent tables whose AllocIDs are
2135 * specified in buffer. Thus the newly allocated table
2136 * is concurrent with table IDs specified in AllocIDs.
2138 #define ICE_AQC_ACL_ALLOC_TABLE_TYPE_NONCONCURR 0
2145 /* Allocate ACL table command buffer format */
2146 struct ice_aqc_acl_alloc_table_data {
2147 /* Dependent table AllocIDs. Each word in this 15 word array specifies
2148 * a dependent table AllocID according to the amount specified in the
2149 * "table_type" field. All unused words shall be set to 0xFFFF
2151 #define ICE_AQC_CONCURR_ID_INVALID 0xffff
2152 __le16 alloc_ids[ICE_AQC_MAX_CONCURRENT_ACL_TBL];
2155 /* Deallocate ACL table (indirect 0x0C11)
2156 * Allocate ACL action-pair (indirect 0x0C12)
2157 * Deallocate ACL action-pair (indirect 0x0C13)
2160 /* Following structure is common and used in case of deallocation
2161 * of ACL table and action-pair
2163 struct ice_aqc_acl_tbl_actpair {
2164 /* Alloc ID of the table being released */
2171 /* This response structure is same in case of alloc/dealloc table,
2172 * alloc/dealloc action-pair
2174 struct ice_aqc_acl_generic {
2175 /* if alloc_id is below 0x1000 then alllocation failed due to
2176 * unavailable resources, else this is set by FW to identify
2182 /* to be used only in case of alloc/dealloc table */
2184 /* Index of the first TCAM block, otherwise set to 0xFF
2185 * for a failed allocation
2188 /* Index of the last TCAM block. This index shall be
2189 * set to the value of first_tcam for single TCAM block
2190 * allocation, otherwise set to 0xFF for a failed
2195 /* reserved in case of alloc/dealloc action-pair */
2201 /* index of first entry (in both TCAM and action memories),
2202 * otherwise set to 0xFF for a failed allocation
2205 /* index of last entry (in both TCAM and action memories),
2206 * otherwise set to 0xFF for a failed allocation
2210 /* Each act_mem element specifies the order of the memory
2213 u8 act_mem[ICE_AQC_MAX_ACTION_MEMORIES];
2216 /* Allocate ACL scenario (indirect 0x0C14). This command doesn't have separate
2217 * response buffer since original command buffer gets updated with
2218 * 'scen_id' in case of success
2220 struct ice_aqc_acl_alloc_scen {
2234 /* De-allocate ACL scenario (direct 0x0C15). This command doesn't need
2235 * separate response buffer since nothing to be returned as a response
2238 struct ice_aqc_acl_dealloc_scen {
2243 /* Update ACL scenario (direct 0x0C1B)
2244 * Query ACL scenario (direct 0x0C23)
2246 struct ice_aqc_acl_update_query_scen {
2253 /* Input buffer format in case allocate/update ACL scenario and same format
2254 * is used for response buffer in case of query ACL scenario.
2255 * NOTE: de-allocate ACL scenario is direct command and doesn't require
2256 * "buffer", hence no buffer format.
2258 struct ice_aqc_acl_scen {
2260 /* Byte [x] selection for the TCAM key. This value must be
2261 * set to 0x0 for unusued TCAM.
2262 * Only Bit 6..0 is used in each byte and MSB is reserved
2264 #define ICE_AQC_ACL_ALLOC_SCE_SELECT_M 0x7F
2265 #define ICE_AQC_ACL_BYTE_SEL_BASE 0x20
2266 #define ICE_AQC_ACL_BYTE_SEL_BASE_PID 0x3E
2267 #define ICE_AQC_ACL_BYTE_SEL_BASE_PKT_DIR ICE_AQC_ACL_BYTE_SEL_BASE
2268 #define ICE_AQC_ACL_BYTE_SEL_BASE_RNG_CHK 0x3F
2270 /* TCAM Block entry masking. This value should be set to 0x0 for
2274 /* Bit 0 : masks TCAM entries 0-63
2275 * Bit 1 : masks TCAM entries 64-127
2276 * Bit 2 to 7 : follow the pattern of bit 0 and 1
2278 #define ICE_AQC_ACL_ALLOC_SCE_START_CMP BIT(0)
2279 #define ICE_AQC_ACL_ALLOC_SCE_START_SET BIT(1)
2282 } tcam_cfg[ICE_AQC_ACL_SLICES];
2284 /* Each byte, Bit 6..0: Action memory association to a TCAM block,
2285 * otherwise it shall be set to 0x0 for disabled memory action.
2286 * Bit 7 : Action memory enable for this scenario
2288 #define ICE_AQC_ACL_SCE_ACT_MEM_TCAM_ASSOC_M 0x7F
2289 #define ICE_AQC_ACL_SCE_ACT_MEM_EN BIT(7)
2290 u8 act_mem_cfg[ICE_AQC_MAX_ACTION_MEMORIES];
2293 /* Allocate ACL counters (indirect 0x0C16) */
2294 struct ice_aqc_acl_alloc_counters {
2295 /* Amount of contiguous counters requested. Min value is 1 and
2298 #define ICE_AQC_ACL_ALLOC_CNT_MIN_AMT 0x1
2299 #define ICE_AQC_ACL_ALLOC_CNT_MAX_AMT 0xFF
2302 /* Counter type: 'single counter' which can be configured to count
2303 * either bytes or packets
2305 #define ICE_AQC_ACL_CNT_TYPE_SINGLE 0x0
2307 /* Counter type: 'counter pair' which counts number of bytes and number
2310 #define ICE_AQC_ACL_CNT_TYPE_DUAL 0x1
2311 /* requested counter type, single/dual */
2314 /* counter bank allocation shall be 0-3 for 'byte or packet counter' */
2315 #define ICE_AQC_ACL_MAX_CNT_SINGLE 0x3
2316 /* counter bank allocation shall be 0-1 for 'byte and packet counter dual' */
2317 #define ICE_AQC_ACL_MAX_CNT_DUAL 0x1
2318 /* requested counter bank allocation */
2324 /* Applicable only in case of command */
2328 /* Applicable only in case of response */
2329 #define ICE_AQC_ACL_ALLOC_CNT_INVAL 0xFFFF
2331 /* Index of first allocated counter. 0xFFFF in case
2332 * of unsuccessful allocation
2334 __le16 first_counter;
2335 /* Index of last allocated counter. 0xFFFF in case
2336 * of unsuccessful allocation
2338 __le16 last_counter;
2344 /* De-allocate ACL counters (direct 0x0C17) */
2345 struct ice_aqc_acl_dealloc_counters {
2346 /* first counter being released */
2347 __le16 first_counter;
2348 /* last counter being released */
2349 __le16 last_counter;
2350 /* requested counter type, single/dual */
2352 /* requested counter bank allocation */
2357 /* De-allocate ACL resources (direct 0x0C1A). Used by SW to release all the
2358 * resources allocated for it using a single command
2360 struct ice_aqc_acl_dealloc_res {
2364 /* Program ACL actionpair (indirect 0x0C1C)
2365 * Query ACL actionpair (indirect 0x0C25)
2367 struct ice_aqc_acl_actpair {
2368 /* action mem index to program/update */
2371 /* The entry index in action memory to be programmed/updated */
2372 __le16 act_entry_index;
2378 /* Input buffer format for program/query action-pair admin command */
2379 struct ice_acl_act_entry {
2380 /* Action priority, values must be between 0..7 */
2381 #define ICE_AQC_ACT_PRIO_VALID_MAX 7
2382 #define ICE_AQC_ACT_PRIO_MSK MAKEMASK(0xff, 0)
2384 /* Action meta-data identifier. This field should be set to 0x0
2387 #define ICE_AQC_ACT_MDID_S 8
2388 #define ICE_AQC_ACT_MDID_MSK MAKEMASK(0xff00, ICE_AQC_ACT_MDID_S)
2391 #define ICE_AQC_ACT_VALUE_S 16
2392 #define ICE_AQC_ACT_VALUE_MSK MAKEMASK(0xffff0000, 16)
2396 #define ICE_ACL_NUM_ACT_PER_ACT_PAIR 2
2397 struct ice_aqc_actpair {
2398 struct ice_acl_act_entry act[ICE_ACL_NUM_ACT_PER_ACT_PAIR];
2401 /* Generic format used to describe either input or response buffer
2402 * for admin commands related to ACL profile
2404 struct ice_aqc_acl_prof_generic_frmt {
2405 /* The first byte of the byte selection base is reserved to keep the
2406 * first byte of the field vector where the packet direction info is
2407 * available. Thus we should start at index 1 of the field vector to
2408 * map its entries to the byte selection base.
2410 #define ICE_AQC_ACL_PROF_BYTE_SEL_START_IDX 1
2412 * Bit 0..5 = Byte selection for the byte selection base from the
2413 * extracted fields (expressed as byte offset in extracted fields).
2414 * Applicable values are 0..63
2415 * Bit 6..7 = Reserved
2417 #define ICE_AQC_ACL_PROF_BYTE_SEL_ELEMS 30
2418 u8 byte_selection[ICE_AQC_ACL_PROF_BYTE_SEL_ELEMS];
2420 * Bit 0..4 = Word selection for the word selection base from the
2421 * extracted fields (expressed as word offset in extracted fields).
2422 * Applicable values are 0..31
2423 * Bit 5..7 = Reserved
2425 #define ICE_AQC_ACL_PROF_WORD_SEL_ELEMS 32
2426 u8 word_selection[ICE_AQC_ACL_PROF_WORD_SEL_ELEMS];
2428 * Bit 0..3 = Double word selection for the double-word selection base
2429 * from the extracted fields (expressed as double-word offset in
2430 * extracted fields).
2431 * Applicable values are 0..15
2432 * Bit 4..7 = Reserved
2434 #define ICE_AQC_ACL_PROF_DWORD_SEL_ELEMS 15
2435 u8 dword_selection[ICE_AQC_ACL_PROF_DWORD_SEL_ELEMS];
2436 /* Scenario numbers for individual Physical Function's */
2437 #define ICE_AQC_ACL_PROF_PF_SCEN_NUM_ELEMS 8
2438 u8 pf_scenario_num[ICE_AQC_ACL_PROF_PF_SCEN_NUM_ELEMS];
2441 /* Program ACL profile extraction (indirect 0x0C1D)
2442 * Program ACL profile ranges (indirect 0x0C1E)
2443 * Query ACL profile (indirect 0x0C21)
2444 * Query ACL profile ranges (indirect 0x0C22)
2446 struct ice_aqc_acl_profile {
2447 u8 profile_id; /* Programmed/Updated profile ID */
2453 /* Input buffer format for program profile extraction admin command and
2454 * response buffer format for query profile admin command is as defined
2455 * in struct ice_aqc_acl_prof_generic_frmt
2458 /* Input buffer format for program profile ranges and query profile ranges
2459 * admin commands. Same format is used for response buffer in case of query
2460 * profile ranges command
2462 struct ice_acl_rng_data {
2463 /* The range checker output shall be sent when the value
2464 * related to this range checker is lower than low boundary
2466 __be16 low_boundary;
2467 /* The range checker output shall be sent when the value
2468 * related to this range checker is higher than high boundary
2470 __be16 high_boundary;
2471 /* A value of '0' in bit shall clear the relevant bit input
2472 * to the range checker
2477 struct ice_aqc_acl_profile_ranges {
2478 #define ICE_AQC_ACL_PROF_RANGES_NUM_CFG 8
2479 struct ice_acl_rng_data checker_cfg[ICE_AQC_ACL_PROF_RANGES_NUM_CFG];
2482 /* Program ACL entry (indirect 0x0C20)
2483 * Query ACL entry (indirect 0x0C24)
2485 struct ice_aqc_acl_entry {
2486 u8 tcam_index; /* Updated TCAM block index */
2488 __le16 entry_index; /* Updated entry index */
2494 /* Input buffer format in case of program ACL entry and response buffer format
2495 * in case of query ACL entry
2497 struct ice_aqc_acl_data {
2498 /* Entry key and entry key invert are 40 bits wide.
2499 * Byte 0..4 : entry key and Byte 5..7 are reserved
2500 * Byte 8..12: entry key invert and Byte 13..15 are reserved
2505 } entry_key, entry_key_invert;
2508 /* Query ACL counter (direct 0x0C27) */
2509 struct ice_aqc_acl_query_counter {
2510 /* Queried counter index */
2511 __le16 counter_index;
2512 /* Queried counter bank */
2519 /* Holds counter value/packet counter value */
2526 /* Add Tx LAN Queues (indirect 0x0C30) */
2527 struct ice_aqc_add_txqs {
2535 /* This is the descriptor of each queue entry for the Add Tx LAN Queues
2536 * command (0x0C30). Only used within struct ice_aqc_add_tx_qgrp.
2538 struct ice_aqc_add_txqs_perq {
2544 struct ice_aqc_txsched_elem info;
2547 /* The format of the command buffer for Add Tx LAN Queues (0x0C30)
2548 * is an array of the following structs. Please note that the length of
2549 * each struct ice_aqc_add_tx_qgrp is variable due
2550 * to the variable number of queues in each group!
2552 struct ice_aqc_add_tx_qgrp {
2556 struct ice_aqc_add_txqs_perq txqs[STRUCT_HACK_VAR_LEN];
2559 /* Disable Tx LAN Queues (indirect 0x0C31) */
2560 struct ice_aqc_dis_txqs {
2562 #define ICE_AQC_Q_DIS_CMD_S 0
2563 #define ICE_AQC_Q_DIS_CMD_M (0x3 << ICE_AQC_Q_DIS_CMD_S)
2564 #define ICE_AQC_Q_DIS_CMD_NO_FUNC_RESET (0 << ICE_AQC_Q_DIS_CMD_S)
2565 #define ICE_AQC_Q_DIS_CMD_VM_RESET BIT(ICE_AQC_Q_DIS_CMD_S)
2566 #define ICE_AQC_Q_DIS_CMD_VF_RESET (2 << ICE_AQC_Q_DIS_CMD_S)
2567 #define ICE_AQC_Q_DIS_CMD_PF_RESET (3 << ICE_AQC_Q_DIS_CMD_S)
2568 #define ICE_AQC_Q_DIS_CMD_SUBSEQ_CALL BIT(2)
2569 #define ICE_AQC_Q_DIS_CMD_FLUSH_PIPE BIT(3)
2571 __le16 vmvf_and_timeout;
2572 #define ICE_AQC_Q_DIS_VMVF_NUM_S 0
2573 #define ICE_AQC_Q_DIS_VMVF_NUM_M (0x3FF << ICE_AQC_Q_DIS_VMVF_NUM_S)
2574 #define ICE_AQC_Q_DIS_TIMEOUT_S 10
2575 #define ICE_AQC_Q_DIS_TIMEOUT_M (0x3F << ICE_AQC_Q_DIS_TIMEOUT_S)
2576 __le32 blocked_cgds;
2581 /* The buffer for Disable Tx LAN Queues (indirect 0x0C31)
2582 * contains the following structures, arrayed one after the
2584 * Note: Since the q_id is 16 bits wide, if the
2585 * number of queues is even, then 2 bytes of alignment MUST be
2586 * added before the start of the next group, to allow correct
2587 * alignment of the parent_teid field.
2590 struct ice_aqc_dis_txq_item {
2594 /* The length of the q_id array varies according to num_qs */
2595 #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S 15
2596 #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_LAN_Q \
2597 (0 << ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S)
2598 #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_RDMA_QSET \
2599 (1 << ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S)
2600 __le16 q_id[STRUCT_HACK_VAR_LEN];
2605 /* Tx LAN Queues Cleanup Event (0x0C31) */
2606 struct ice_aqc_txqs_cleanup {
2612 /* Move / Reconfigure Tx Queues (indirect 0x0C32) */
2613 struct ice_aqc_move_txqs {
2615 #define ICE_AQC_Q_CMD_TYPE_S 0
2616 #define ICE_AQC_Q_CMD_TYPE_M (0x3 << ICE_AQC_Q_CMD_TYPE_S)
2617 #define ICE_AQC_Q_CMD_TYPE_MOVE 1
2618 #define ICE_AQC_Q_CMD_TYPE_TC_CHANGE 2
2619 #define ICE_AQC_Q_CMD_TYPE_MOVE_AND_TC 3
2620 #define ICE_AQC_Q_CMD_SUBSEQ_CALL BIT(2)
2621 #define ICE_AQC_Q_CMD_FLUSH_PIPE BIT(3)
2625 #define ICE_AQC_Q_CMD_TIMEOUT_S 2
2626 #define ICE_AQC_Q_CMD_TIMEOUT_M (0x3F << ICE_AQC_Q_CMD_TIMEOUT_S)
2627 __le32 blocked_cgds;
2632 /* Per-queue data buffer for the Move Tx LAN Queues command/response */
2633 struct ice_aqc_move_txqs_elem {
2640 /* Indirect data buffer for the Move Tx LAN Queues command/response */
2641 struct ice_aqc_move_txqs_data {
2644 struct ice_aqc_move_txqs_elem txqs[STRUCT_HACK_VAR_LEN];
2647 /* Download Package (indirect 0x0C40) */
2648 /* Also used for Update Package (indirect 0x0C42 and 0x0C41) */
2649 struct ice_aqc_download_pkg {
2651 #define ICE_AQC_DOWNLOAD_PKG_LAST_BUF 0x01
2658 struct ice_aqc_download_pkg_resp {
2659 __le32 error_offset;
2665 /* Get Package Info List (indirect 0x0C43) */
2666 struct ice_aqc_get_pkg_info_list {
2673 /* Version format for packages */
2674 struct ice_pkg_ver {
2681 #define ICE_PKG_NAME_SIZE 32
2682 #define ICE_SEG_ID_SIZE 28
2683 #define ICE_SEG_NAME_SIZE 28
2685 struct ice_aqc_get_pkg_info {
2686 struct ice_pkg_ver ver;
2687 char name[ICE_SEG_NAME_SIZE];
2691 u8 is_active_at_boot;
2695 /* Get Package Info List response buffer format (0x0C43) */
2696 struct ice_aqc_get_pkg_info_resp {
2698 struct ice_aqc_get_pkg_info pkg_info[STRUCT_HACK_VAR_LEN];
2701 /* Driver Shared Parameters (direct, 0x0C90) */
2702 struct ice_aqc_driver_shared_params {
2704 #define ICE_AQC_DRIVER_PARAM_OP_MASK BIT(0)
2705 #define ICE_AQC_DRIVER_PARAM_SET 0
2706 #define ICE_AQC_DRIVER_PARAM_GET 1
2708 #define ICE_AQC_DRIVER_PARAM_MAX_IDX 15
2715 /* Lan Queue Overflow Event (direct, 0x1001) */
2716 struct ice_aqc_event_lan_overflow {
2717 __le32 prtdcb_ruptq;
2722 /* Set Health Status (direct 0xFF20) */
2723 struct ice_aqc_set_health_status_config {
2725 #define ICE_AQC_HEALTH_STATUS_SET_PF_SPECIFIC_MASK BIT(0)
2726 #define ICE_AQC_HEALTH_STATUS_SET_ALL_PF_MASK BIT(1)
2727 #define ICE_AQC_HEALTH_STATUS_SET_GLOBAL_MASK BIT(2)
2731 #define ICE_AQC_HEALTH_STATUS_ERR_UNKNOWN_MOD_STRICT 0x101
2732 #define ICE_AQC_HEALTH_STATUS_ERR_MOD_TYPE 0x102
2733 #define ICE_AQC_HEALTH_STATUS_ERR_MOD_QUAL 0x103
2734 #define ICE_AQC_HEALTH_STATUS_ERR_MOD_COMM 0x104
2735 #define ICE_AQC_HEALTH_STATUS_ERR_MOD_CONFLICT 0x105
2736 #define ICE_AQC_HEALTH_STATUS_ERR_MOD_NOT_PRESENT 0x106
2737 #define ICE_AQC_HEALTH_STATUS_INFO_MOD_UNDERUTILIZED 0x107
2738 #define ICE_AQC_HEALTH_STATUS_ERR_UNKNOWN_MOD_LENIENT 0x108
2739 #define ICE_AQC_HEALTH_STATUS_ERR_INVALID_LINK_CFG 0x10B
2740 #define ICE_AQC_HEALTH_STATUS_ERR_PORT_ACCESS 0x10C
2741 #define ICE_AQC_HEALTH_STATUS_ERR_PORT_UNREACHABLE 0x10D
2742 #define ICE_AQC_HEALTH_STATUS_INFO_PORT_SPEED_MOD_LIMITED 0x10F
2743 #define ICE_AQC_HEALTH_STATUS_ERR_PARALLEL_FAULT 0x110
2744 #define ICE_AQC_HEALTH_STATUS_INFO_PORT_SPEED_PHY_LIMITED 0x111
2745 #define ICE_AQC_HEALTH_STATUS_ERR_NETLIST_TOPO 0x112
2746 #define ICE_AQC_HEALTH_STATUS_ERR_NETLIST 0x113
2747 #define ICE_AQC_HEALTH_STATUS_ERR_TOPO_CONFLICT 0x114
2748 #define ICE_AQC_HEALTH_STATUS_ERR_LINK_HW_ACCESS 0x115
2749 #define ICE_AQC_HEALTH_STATUS_ERR_LINK_RUNTIME 0x116
2750 #define ICE_AQC_HEALTH_STATUS_ERR_DNL_INIT 0x117
2751 #define ICE_AQC_HEALTH_STATUS_ERR_PHY_NVM_PROG 0x120
2752 #define ICE_AQC_HEALTH_STATUS_ERR_PHY_FW_LOAD 0x121
2753 #define ICE_AQC_HEALTH_STATUS_INFO_RECOVERY 0x500
2754 #define ICE_AQC_HEALTH_STATUS_ERR_FLASH_ACCESS 0x501
2755 #define ICE_AQC_HEALTH_STATUS_ERR_NVM_AUTH 0x502
2756 #define ICE_AQC_HEALTH_STATUS_ERR_OROM_AUTH 0x503
2757 #define ICE_AQC_HEALTH_STATUS_ERR_DDP_AUTH 0x504
2758 #define ICE_AQC_HEALTH_STATUS_ERR_NVM_COMPAT 0x505
2759 #define ICE_AQC_HEALTH_STATUS_ERR_OROM_COMPAT 0x506
2760 #define ICE_AQC_HEALTH_STATUS_ERR_DCB_MIB 0x509
2762 /* Get Health Status codes (indirect 0xFF21) */
2763 struct ice_aqc_get_supported_health_status_codes {
2764 __le16 health_code_count;
2770 /* Get Health Status (indirect 0xFF22) */
2771 struct ice_aqc_get_health_status {
2772 __le16 health_status_count;
2778 /* Get Health Status event buffer entry, (0xFF22)
2779 * repeated per reported health status
2781 struct ice_aqc_health_status_elem {
2782 __le16 health_status_code;
2783 __le16 event_source;
2784 #define ICE_AQC_HEALTH_STATUS_PF (0x1)
2785 #define ICE_AQC_HEALTH_STATUS_PORT (0x2)
2786 #define ICE_AQC_HEALTH_STATUS_GLOBAL (0x3)
2787 __le32 internal_data1;
2788 #define ICE_AQC_HEALTH_STATUS_UNDEFINED_DATA (0xDEADBEEF)
2789 __le32 internal_data2;
2792 /* Clear Health Status (direct 0xFF23) */
2793 struct ice_aqc_clear_health_status {
2798 * struct ice_aq_desc - Admin Queue (AQ) descriptor
2799 * @flags: ICE_AQ_FLAG_* flags
2800 * @opcode: AQ command opcode
2801 * @datalen: length in bytes of indirect/external data buffer
2802 * @retval: return value from firmware
2803 * @cookie_high: opaque data high-half
2804 * @cookie_low: opaque data low-half
2805 * @params: command-specific parameters
2807 * Descriptor format for commands the driver posts on the Admin Transmit Queue
2808 * (ATQ). The firmware writes back onto the command descriptor and returns
2809 * the result of the command. Asynchronous events that are not an immediate
2810 * result of the command are written to the Admin Receive Queue (ARQ) using
2811 * the same descriptor format. Descriptors are in little-endian notation with
2814 struct ice_aq_desc {
2823 struct ice_aqc_generic generic;
2824 struct ice_aqc_get_ver get_ver;
2825 struct ice_aqc_driver_ver driver_ver;
2826 struct ice_aqc_q_shutdown q_shutdown;
2827 struct ice_aqc_req_res res_owner;
2828 struct ice_aqc_manage_mac_read mac_read;
2829 struct ice_aqc_manage_mac_write mac_write;
2830 struct ice_aqc_clear_pxe clear_pxe;
2831 struct ice_aqc_config_no_drop_policy no_drop;
2832 struct ice_aqc_add_update_mir_rule add_update_rule;
2833 struct ice_aqc_delete_mir_rule del_rule;
2834 struct ice_aqc_list_caps get_cap;
2835 struct ice_aqc_get_phy_caps get_phy;
2836 struct ice_aqc_set_phy_cfg set_phy;
2837 struct ice_aqc_restart_an restart_an;
2838 struct ice_aqc_i2c read_write_i2c;
2839 struct ice_aqc_read_i2c_resp read_i2c_resp;
2840 struct ice_aqc_gpio read_write_gpio;
2841 struct ice_aqc_sff_eeprom read_write_sff_param;
2842 struct ice_aqc_set_port_id_led set_port_id_led;
2843 struct ice_aqc_get_sw_cfg get_sw_conf;
2844 struct ice_aqc_set_port_params set_port_params;
2845 struct ice_aqc_sw_rules sw_rules;
2846 struct ice_aqc_storm_cfg storm_conf;
2847 struct ice_aqc_add_get_recipe add_get_recipe;
2848 struct ice_aqc_recipe_to_profile recipe_to_profile;
2849 struct ice_aqc_get_topo get_topo;
2850 struct ice_aqc_sched_elem_cmd sched_elem_cmd;
2851 struct ice_aqc_query_txsched_res query_sched_res;
2852 struct ice_aqc_query_node_to_root query_node_to_root;
2853 struct ice_aqc_cfg_l2_node_cgd cfg_l2_node_cgd;
2854 struct ice_aqc_query_port_ets port_ets;
2855 struct ice_aqc_rl_profile rl_profile;
2856 struct ice_aqc_nvm nvm;
2857 struct ice_aqc_nvm_cfg nvm_cfg;
2858 struct ice_aqc_nvm_checksum nvm_checksum;
2859 struct ice_aqc_pfc_ignore pfc_ignore;
2860 struct ice_aqc_set_query_pfc_mode set_query_pfc_mode;
2861 struct ice_aqc_set_dcb_params set_dcb_params;
2862 struct ice_aqc_lldp_get_mib lldp_get_mib;
2863 struct ice_aqc_lldp_set_mib_change lldp_set_event;
2864 struct ice_aqc_lldp_add_delete_tlv lldp_add_delete_tlv;
2865 struct ice_aqc_lldp_update_tlv lldp_update_tlv;
2866 struct ice_aqc_lldp_stop lldp_stop;
2867 struct ice_aqc_lldp_start lldp_start;
2868 struct ice_aqc_lldp_set_local_mib lldp_set_mib;
2869 struct ice_aqc_lldp_stop_start_specific_agent lldp_agent_ctrl;
2870 struct ice_aqc_lldp_filter_ctrl lldp_filter_ctrl;
2871 struct ice_aqc_get_set_rss_lut get_set_rss_lut;
2872 struct ice_aqc_get_set_rss_key get_set_rss_key;
2873 struct ice_aqc_clear_fd_table clear_fd_table;
2874 struct ice_aqc_acl_alloc_table alloc_table;
2875 struct ice_aqc_acl_tbl_actpair tbl_actpair;
2876 struct ice_aqc_acl_alloc_scen alloc_scen;
2877 struct ice_aqc_acl_dealloc_scen dealloc_scen;
2878 struct ice_aqc_acl_update_query_scen update_query_scen;
2879 struct ice_aqc_acl_alloc_counters alloc_counters;
2880 struct ice_aqc_acl_dealloc_counters dealloc_counters;
2881 struct ice_aqc_acl_dealloc_res dealloc_res;
2882 struct ice_aqc_acl_entry program_query_entry;
2883 struct ice_aqc_acl_actpair program_query_actpair;
2884 struct ice_aqc_acl_profile profile;
2885 struct ice_aqc_acl_query_counter query_counter;
2886 struct ice_aqc_add_txqs add_txqs;
2887 struct ice_aqc_dis_txqs dis_txqs;
2888 struct ice_aqc_move_txqs move_txqs;
2889 struct ice_aqc_txqs_cleanup txqs_cleanup;
2890 struct ice_aqc_add_get_update_free_vsi vsi_cmd;
2891 struct ice_aqc_add_update_free_vsi_resp add_update_free_vsi_res;
2892 struct ice_aqc_get_vsi_resp get_vsi_resp;
2893 struct ice_aqc_download_pkg download_pkg;
2894 struct ice_aqc_get_pkg_info_list get_pkg_info_list;
2895 struct ice_aqc_driver_shared_params drv_shared_params;
2896 struct ice_aqc_set_mac_lb set_mac_lb;
2897 struct ice_aqc_alloc_free_res_cmd sw_res_ctrl;
2898 struct ice_aqc_get_res_alloc get_res;
2899 struct ice_aqc_get_allocd_res_desc get_res_desc;
2900 struct ice_aqc_set_mac_cfg set_mac_cfg;
2901 struct ice_aqc_set_event_mask set_event_mask;
2902 struct ice_aqc_get_link_status get_link_status;
2903 struct ice_aqc_event_lan_overflow lan_overflow;
2904 struct ice_aqc_get_link_topo get_link_topo;
2905 struct ice_aqc_set_health_status_config
2906 set_health_status_config;
2907 struct ice_aqc_get_supported_health_status_codes
2908 get_supported_health_status_codes;
2909 struct ice_aqc_get_health_status get_health_status;
2910 struct ice_aqc_clear_health_status clear_health_status;
2911 struct ice_aqc_prog_topo_dev_nvm prog_topo_dev_nvm;
2912 struct ice_aqc_read_topo_dev_nvm read_topo_dev_nvm;
2916 /* FW defined boundary for a large buffer, 4k >= Large buffer > 512 bytes */
2917 #define ICE_AQ_LG_BUF 512
2919 /* Flags sub-structure
2920 * |0 |1 |2 |3 |4 |5 |6 |7 |8 |9 |10 |11 |12 |13 |14 |15 |
2921 * |DD |CMP|ERR|VFE| * * RESERVED * * |LB |RD |VFC|BUF|SI |EI |FE |
2924 /* command flags and offsets */
2925 #define ICE_AQ_FLAG_DD_S 0
2926 #define ICE_AQ_FLAG_CMP_S 1
2927 #define ICE_AQ_FLAG_ERR_S 2
2928 #define ICE_AQ_FLAG_VFE_S 3
2929 #define ICE_AQ_FLAG_LB_S 9
2930 #define ICE_AQ_FLAG_RD_S 10
2931 #define ICE_AQ_FLAG_VFC_S 11
2932 #define ICE_AQ_FLAG_BUF_S 12
2933 #define ICE_AQ_FLAG_SI_S 13
2934 #define ICE_AQ_FLAG_EI_S 14
2935 #define ICE_AQ_FLAG_FE_S 15
2937 #define ICE_AQ_FLAG_DD BIT(ICE_AQ_FLAG_DD_S) /* 0x1 */
2938 #define ICE_AQ_FLAG_CMP BIT(ICE_AQ_FLAG_CMP_S) /* 0x2 */
2939 #define ICE_AQ_FLAG_ERR BIT(ICE_AQ_FLAG_ERR_S) /* 0x4 */
2940 #define ICE_AQ_FLAG_VFE BIT(ICE_AQ_FLAG_VFE_S) /* 0x8 */
2941 #define ICE_AQ_FLAG_LB BIT(ICE_AQ_FLAG_LB_S) /* 0x200 */
2942 #define ICE_AQ_FLAG_RD BIT(ICE_AQ_FLAG_RD_S) /* 0x400 */
2943 #define ICE_AQ_FLAG_VFC BIT(ICE_AQ_FLAG_VFC_S) /* 0x800 */
2944 #define ICE_AQ_FLAG_BUF BIT(ICE_AQ_FLAG_BUF_S) /* 0x1000 */
2945 #define ICE_AQ_FLAG_SI BIT(ICE_AQ_FLAG_SI_S) /* 0x2000 */
2946 #define ICE_AQ_FLAG_EI BIT(ICE_AQ_FLAG_EI_S) /* 0x4000 */
2947 #define ICE_AQ_FLAG_FE BIT(ICE_AQ_FLAG_FE_S) /* 0x8000 */
2951 ICE_AQ_RC_OK = 0, /* Success */
2952 ICE_AQ_RC_EPERM = 1, /* Operation not permitted */
2953 ICE_AQ_RC_ENOENT = 2, /* No such element */
2954 ICE_AQ_RC_ESRCH = 3, /* Bad opcode */
2955 ICE_AQ_RC_EINTR = 4, /* Operation interrupted */
2956 ICE_AQ_RC_EIO = 5, /* I/O error */
2957 ICE_AQ_RC_ENXIO = 6, /* No such resource */
2958 ICE_AQ_RC_E2BIG = 7, /* Arg too long */
2959 ICE_AQ_RC_EAGAIN = 8, /* Try again */
2960 ICE_AQ_RC_ENOMEM = 9, /* Out of memory */
2961 ICE_AQ_RC_EACCES = 10, /* Permission denied */
2962 ICE_AQ_RC_EFAULT = 11, /* Bad address */
2963 ICE_AQ_RC_EBUSY = 12, /* Device or resource busy */
2964 ICE_AQ_RC_EEXIST = 13, /* Object already exists */
2965 ICE_AQ_RC_EINVAL = 14, /* Invalid argument */
2966 ICE_AQ_RC_ENOTTY = 15, /* Not a typewriter */
2967 ICE_AQ_RC_ENOSPC = 16, /* No space left or allocation failure */
2968 ICE_AQ_RC_ENOSYS = 17, /* Function not implemented */
2969 ICE_AQ_RC_ERANGE = 18, /* Parameter out of range */
2970 ICE_AQ_RC_EFLUSHED = 19, /* Cmd flushed due to prev cmd error */
2971 ICE_AQ_RC_BAD_ADDR = 20, /* Descriptor contains a bad pointer */
2972 ICE_AQ_RC_EMODE = 21, /* Op not allowed in current dev mode */
2973 ICE_AQ_RC_EFBIG = 22, /* File too big */
2974 ICE_AQ_RC_ESBCOMP = 23, /* SB-IOSF completion unsuccessful */
2975 ICE_AQ_RC_ENOSEC = 24, /* Missing security manifest */
2976 ICE_AQ_RC_EBADSIG = 25, /* Bad RSA signature */
2977 ICE_AQ_RC_ESVN = 26, /* SVN number prohibits this package */
2978 ICE_AQ_RC_EBADMAN = 27, /* Manifest hash mismatch */
2979 ICE_AQ_RC_EBADBUF = 28, /* Buffer hash mismatches manifest */
2980 ICE_AQ_RC_EACCES_BMCU = 29, /* BMC Update in progress */
2983 /* Admin Queue command opcodes */
2984 enum ice_adminq_opc {
2986 ice_aqc_opc_get_ver = 0x0001,
2987 ice_aqc_opc_driver_ver = 0x0002,
2988 ice_aqc_opc_q_shutdown = 0x0003,
2989 ice_aqc_opc_get_exp_err = 0x0005,
2991 /* resource ownership */
2992 ice_aqc_opc_req_res = 0x0008,
2993 ice_aqc_opc_release_res = 0x0009,
2995 /* device/function capabilities */
2996 ice_aqc_opc_list_func_caps = 0x000A,
2997 ice_aqc_opc_list_dev_caps = 0x000B,
2999 /* manage MAC address */
3000 ice_aqc_opc_manage_mac_read = 0x0107,
3001 ice_aqc_opc_manage_mac_write = 0x0108,
3004 ice_aqc_opc_clear_pxe_mode = 0x0110,
3006 ice_aqc_opc_config_no_drop_policy = 0x0112,
3008 /* internal switch commands */
3009 ice_aqc_opc_get_sw_cfg = 0x0200,
3010 ice_aqc_opc_set_port_params = 0x0203,
3012 /* Alloc/Free/Get Resources */
3013 ice_aqc_opc_get_res_alloc = 0x0204,
3014 ice_aqc_opc_alloc_res = 0x0208,
3015 ice_aqc_opc_free_res = 0x0209,
3016 ice_aqc_opc_get_allocd_res_desc = 0x020A,
3017 ice_aqc_opc_set_vlan_mode_parameters = 0x020C,
3018 ice_aqc_opc_get_vlan_mode_parameters = 0x020D,
3021 ice_aqc_opc_add_vsi = 0x0210,
3022 ice_aqc_opc_update_vsi = 0x0211,
3023 ice_aqc_opc_get_vsi_params = 0x0212,
3024 ice_aqc_opc_free_vsi = 0x0213,
3026 /* Mirroring rules - add/update, delete */
3027 ice_aqc_opc_add_update_mir_rule = 0x0260,
3028 ice_aqc_opc_del_mir_rule = 0x0261,
3030 /* storm configuration */
3031 ice_aqc_opc_set_storm_cfg = 0x0280,
3032 ice_aqc_opc_get_storm_cfg = 0x0281,
3034 /* recipe commands */
3035 ice_aqc_opc_add_recipe = 0x0290,
3036 ice_aqc_opc_recipe_to_profile = 0x0291,
3037 ice_aqc_opc_get_recipe = 0x0292,
3038 ice_aqc_opc_get_recipe_to_profile = 0x0293,
3040 /* switch rules population commands */
3041 ice_aqc_opc_add_sw_rules = 0x02A0,
3042 ice_aqc_opc_update_sw_rules = 0x02A1,
3043 ice_aqc_opc_remove_sw_rules = 0x02A2,
3044 ice_aqc_opc_get_sw_rules = 0x02A3,
3045 ice_aqc_opc_clear_pf_cfg = 0x02A4,
3048 ice_aqc_opc_pfc_ignore = 0x0301,
3049 ice_aqc_opc_query_pfc_mode = 0x0302,
3050 ice_aqc_opc_set_pfc_mode = 0x0303,
3051 ice_aqc_opc_set_dcb_params = 0x0306,
3053 /* transmit scheduler commands */
3054 ice_aqc_opc_get_dflt_topo = 0x0400,
3055 ice_aqc_opc_add_sched_elems = 0x0401,
3056 ice_aqc_opc_cfg_sched_elems = 0x0403,
3057 ice_aqc_opc_get_sched_elems = 0x0404,
3058 ice_aqc_opc_move_sched_elems = 0x0408,
3059 ice_aqc_opc_suspend_sched_elems = 0x0409,
3060 ice_aqc_opc_resume_sched_elems = 0x040A,
3061 ice_aqc_opc_query_port_ets = 0x040E,
3062 ice_aqc_opc_delete_sched_elems = 0x040F,
3063 ice_aqc_opc_add_rl_profiles = 0x0410,
3064 ice_aqc_opc_query_rl_profiles = 0x0411,
3065 ice_aqc_opc_query_sched_res = 0x0412,
3066 ice_aqc_opc_query_node_to_root = 0x0413,
3067 ice_aqc_opc_cfg_l2_node_cgd = 0x0414,
3068 ice_aqc_opc_remove_rl_profiles = 0x0415,
3071 ice_aqc_opc_get_phy_caps = 0x0600,
3072 ice_aqc_opc_set_phy_cfg = 0x0601,
3073 ice_aqc_opc_set_mac_cfg = 0x0603,
3074 ice_aqc_opc_restart_an = 0x0605,
3075 ice_aqc_opc_get_link_status = 0x0607,
3076 ice_aqc_opc_set_event_mask = 0x0613,
3077 ice_aqc_opc_set_mac_lb = 0x0620,
3078 ice_aqc_opc_get_link_topo = 0x06E0,
3079 ice_aqc_opc_read_i2c = 0x06E2,
3080 ice_aqc_opc_write_i2c = 0x06E3,
3081 ice_aqc_opc_set_port_id_led = 0x06E9,
3082 ice_aqc_opc_get_port_options = 0x06EA,
3083 ice_aqc_opc_set_port_option = 0x06EB,
3084 ice_aqc_opc_set_gpio = 0x06EC,
3085 ice_aqc_opc_get_gpio = 0x06ED,
3086 ice_aqc_opc_sff_eeprom = 0x06EE,
3087 ice_aqc_opc_sw_set_gpio = 0x06EF,
3088 ice_aqc_opc_sw_get_gpio = 0x06F0,
3089 ice_aqc_opc_prog_topo_dev_nvm = 0x06F2,
3090 ice_aqc_opc_read_topo_dev_nvm = 0x06F3,
3093 ice_aqc_opc_nvm_read = 0x0701,
3094 ice_aqc_opc_nvm_erase = 0x0702,
3095 ice_aqc_opc_nvm_write = 0x0703,
3096 ice_aqc_opc_nvm_cfg_read = 0x0704,
3097 ice_aqc_opc_nvm_cfg_write = 0x0705,
3098 ice_aqc_opc_nvm_checksum = 0x0706,
3099 ice_aqc_opc_nvm_write_activate = 0x0707,
3100 ice_aqc_opc_nvm_sr_dump = 0x0707,
3101 ice_aqc_opc_nvm_save_factory_settings = 0x0708,
3102 ice_aqc_opc_nvm_update_empr = 0x0709,
3105 ice_aqc_opc_lldp_get_mib = 0x0A00,
3106 ice_aqc_opc_lldp_set_mib_change = 0x0A01,
3107 ice_aqc_opc_lldp_add_tlv = 0x0A02,
3108 ice_aqc_opc_lldp_update_tlv = 0x0A03,
3109 ice_aqc_opc_lldp_delete_tlv = 0x0A04,
3110 ice_aqc_opc_lldp_stop = 0x0A05,
3111 ice_aqc_opc_lldp_start = 0x0A06,
3112 ice_aqc_opc_get_cee_dcb_cfg = 0x0A07,
3113 ice_aqc_opc_lldp_set_local_mib = 0x0A08,
3114 ice_aqc_opc_lldp_stop_start_specific_agent = 0x0A09,
3115 ice_aqc_opc_lldp_filter_ctrl = 0x0A0A,
3118 ice_aqc_opc_set_rss_key = 0x0B02,
3119 ice_aqc_opc_set_rss_lut = 0x0B03,
3120 ice_aqc_opc_get_rss_key = 0x0B04,
3121 ice_aqc_opc_get_rss_lut = 0x0B05,
3122 ice_aqc_opc_clear_fd_table = 0x0B06,
3124 ice_aqc_opc_alloc_acl_tbl = 0x0C10,
3125 ice_aqc_opc_dealloc_acl_tbl = 0x0C11,
3126 ice_aqc_opc_alloc_acl_actpair = 0x0C12,
3127 ice_aqc_opc_dealloc_acl_actpair = 0x0C13,
3128 ice_aqc_opc_alloc_acl_scen = 0x0C14,
3129 ice_aqc_opc_dealloc_acl_scen = 0x0C15,
3130 ice_aqc_opc_alloc_acl_counters = 0x0C16,
3131 ice_aqc_opc_dealloc_acl_counters = 0x0C17,
3132 ice_aqc_opc_dealloc_acl_res = 0x0C1A,
3133 ice_aqc_opc_update_acl_scen = 0x0C1B,
3134 ice_aqc_opc_program_acl_actpair = 0x0C1C,
3135 ice_aqc_opc_program_acl_prof_extraction = 0x0C1D,
3136 ice_aqc_opc_program_acl_prof_ranges = 0x0C1E,
3137 ice_aqc_opc_program_acl_entry = 0x0C20,
3138 ice_aqc_opc_query_acl_prof = 0x0C21,
3139 ice_aqc_opc_query_acl_prof_ranges = 0x0C22,
3140 ice_aqc_opc_query_acl_scen = 0x0C23,
3141 ice_aqc_opc_query_acl_entry = 0x0C24,
3142 ice_aqc_opc_query_acl_actpair = 0x0C25,
3143 ice_aqc_opc_query_acl_counter = 0x0C27,
3145 /* Tx queue handling commands/events */
3146 ice_aqc_opc_add_txqs = 0x0C30,
3147 ice_aqc_opc_dis_txqs = 0x0C31,
3148 ice_aqc_opc_txqs_cleanup = 0x0C31,
3149 ice_aqc_opc_move_recfg_txqs = 0x0C32,
3151 /* package commands */
3152 ice_aqc_opc_download_pkg = 0x0C40,
3153 ice_aqc_opc_upload_section = 0x0C41,
3154 ice_aqc_opc_update_pkg = 0x0C42,
3155 ice_aqc_opc_get_pkg_info_list = 0x0C43,
3157 ice_aqc_opc_driver_shared_params = 0x0C90,
3159 /* Standalone Commands/Events */
3160 ice_aqc_opc_event_lan_overflow = 0x1001,
3162 /* SystemDiagnostic commands */
3163 ice_aqc_opc_set_health_status_config = 0xFF20,
3164 ice_aqc_opc_get_supported_health_status_codes = 0xFF21,
3165 ice_aqc_opc_get_health_status = 0xFF22,
3166 ice_aqc_opc_clear_health_status = 0xFF23,
3169 #endif /* _ICE_ADMINQ_CMD_H_ */