1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2001-2018
5 #ifndef _ICE_ADMINQ_CMD_H_
6 #define _ICE_ADMINQ_CMD_H_
8 /* This header file defines the Admin Queue commands, error codes and
9 * descriptor format. It is shared between Firmware and Software.
13 #define ICE_MAX_VSI 768
14 #define ICE_AQC_TOPO_MAX_LEVEL_NUM 0x9
15 #define ICE_AQ_SET_MAC_FRAME_SIZE_MAX 9728
18 struct ice_aqc_generic {
26 /* Get version (direct 0x0001) */
27 struct ice_aqc_get_ver {
42 /* Queue Shutdown (direct 0x0003) */
43 struct ice_aqc_q_shutdown {
44 __le32 driver_unloading;
45 #define ICE_AQC_DRIVER_UNLOADING BIT(0)
52 /* Request resource ownership (direct 0x0008)
53 * Release resource ownership (direct 0x0009)
55 struct ice_aqc_req_res {
57 #define ICE_AQC_RES_ID_NVM 1
58 #define ICE_AQC_RES_ID_SDP 2
59 #define ICE_AQC_RES_ID_CHNG_LOCK 3
60 #define ICE_AQC_RES_ID_GLBL_LOCK 4
62 #define ICE_AQC_RES_ACCESS_READ 1
63 #define ICE_AQC_RES_ACCESS_WRITE 2
65 /* Upon successful completion, FW writes this value and driver is
66 * expected to release resource before timeout. This value is provided
70 #define ICE_AQ_RES_NVM_READ_DFLT_TIMEOUT_MS 3000
71 #define ICE_AQ_RES_NVM_WRITE_DFLT_TIMEOUT_MS 180000
72 #define ICE_AQ_RES_CHNG_LOCK_DFLT_TIMEOUT_MS 1000
73 #define ICE_AQ_RES_GLBL_LOCK_DFLT_TIMEOUT_MS 3000
74 /* For SDP: pin id of the SDP */
76 /* Status is only used for ICE_AQC_RES_ID_GLBL_LOCK */
78 #define ICE_AQ_RES_GLBL_SUCCESS 0
79 #define ICE_AQ_RES_GLBL_IN_PROG 1
80 #define ICE_AQ_RES_GLBL_DONE 2
85 /* Get function capabilities (indirect 0x000A)
86 * Get device capabilities (indirect 0x000B)
88 struct ice_aqc_list_caps {
98 /* Device/Function buffer entry, repeated per reported capability */
99 struct ice_aqc_list_caps_elem {
101 #define ICE_AQC_CAPS_VALID_FUNCTIONS 0x0005
102 #define ICE_AQC_CAPS_VSI 0x0017
103 #define ICE_AQC_CAPS_RSS 0x0040
104 #define ICE_AQC_CAPS_RXQS 0x0041
105 #define ICE_AQC_CAPS_TXQS 0x0042
106 #define ICE_AQC_CAPS_MSIX 0x0043
107 #define ICE_AQC_CAPS_MAX_MTU 0x0047
111 /* Number of resources described by this capability */
113 /* Only meaningful for some types of resources */
115 /* Only meaningful for some types of resources */
122 /* Manage MAC address, read command - indirect (0x0107)
123 * This struct is also used for the response
125 struct ice_aqc_manage_mac_read {
126 __le16 flags; /* Zeroed by device driver */
127 #define ICE_AQC_MAN_MAC_LAN_ADDR_VALID BIT(4)
128 #define ICE_AQC_MAN_MAC_SAN_ADDR_VALID BIT(5)
129 #define ICE_AQC_MAN_MAC_PORT_ADDR_VALID BIT(6)
130 #define ICE_AQC_MAN_MAC_WOL_ADDR_VALID BIT(7)
131 #define ICE_AQC_MAN_MAC_READ_S 4
132 #define ICE_AQC_MAN_MAC_READ_M (0xF << ICE_AQC_MAN_MAC_READ_S)
135 #define ICE_AQC_MAN_MAC_PORT_NUM_IS_VALID BIT(0)
136 u8 num_addr; /* Used in response */
143 /* Response buffer format for manage MAC read command */
144 struct ice_aqc_manage_mac_read_resp {
147 #define ICE_AQC_MAN_MAC_ADDR_TYPE_LAN 0
148 #define ICE_AQC_MAN_MAC_ADDR_TYPE_WOL 1
149 u8 mac_addr[ETH_ALEN];
153 /* Manage MAC address, write command - direct (0x0108) */
154 struct ice_aqc_manage_mac_write {
157 #define ICE_AQC_MAN_MAC_WR_MC_MAG_EN BIT(0)
158 #define ICE_AQC_MAN_MAC_WR_WOL_LAA_PFR_KEEP BIT(1)
159 #define ICE_AQC_MAN_MAC_WR_S 6
160 #define ICE_AQC_MAN_MAC_WR_M (3 << ICE_AQC_MAN_MAC_WR_S)
161 #define ICE_AQC_MAN_MAC_UPDATE_LAA 0
162 #define ICE_AQC_MAN_MAC_UPDATE_LAA_WOL (BIT(0) << ICE_AQC_MAN_MAC_WR_S)
163 /* High 16 bits of MAC address in big endian order */
165 /* Low 32 bits of MAC address in big endian order */
172 /* Clear PXE Command and response (direct 0x0110) */
173 struct ice_aqc_clear_pxe {
175 #define ICE_AQC_CLEAR_PXE_RX_CNT 0x2
180 /* Get switch configuration (0x0200) */
181 struct ice_aqc_get_sw_cfg {
182 /* Reserved for command and copy of request flags for response */
184 /* First desc in case of command and next_elem in case of response
185 * In case of response, if it is not zero, means all the configuration
186 * was not returned and new command shall be sent with this value in
187 * the 'first desc' field
190 /* Reserved for command, only used for response */
198 /* Each entry in the response buffer is of the following type: */
199 struct ice_aqc_get_sw_cfg_resp_elem {
200 /* VSI/Port Number */
202 #define ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_S 0
203 #define ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_M \
204 (0x3FF << ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_S)
205 #define ICE_AQC_GET_SW_CONF_RESP_TYPE_S 14
206 #define ICE_AQC_GET_SW_CONF_RESP_TYPE_M (0x3 << ICE_AQC_GET_SW_CONF_RESP_TYPE_S)
207 #define ICE_AQC_GET_SW_CONF_RESP_PHYS_PORT 0
208 #define ICE_AQC_GET_SW_CONF_RESP_VIRT_PORT 1
209 #define ICE_AQC_GET_SW_CONF_RESP_VSI 2
211 /* SWID VSI/Port belongs to */
214 /* Bit 14..0 : PF/VF number VSI belongs to
215 * Bit 15 : VF indication bit
218 #define ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_S 0
219 #define ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_M \
220 (0x7FFF << ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_S)
221 #define ICE_AQC_GET_SW_CONF_RESP_IS_VF BIT(15)
225 /* The response buffer is as follows. Note that the length of the
226 * elements array varies with the length of the command response.
228 struct ice_aqc_get_sw_cfg_resp {
229 struct ice_aqc_get_sw_cfg_resp_elem elements[1];
234 /* These resource type defines are used for all switch resource
235 * commands where a resource type is required, such as:
236 * Get Resource Allocation command (indirect 0x0204)
237 * Allocate Resources command (indirect 0x0208)
238 * Free Resources command (indirect 0x0209)
239 * Get Allocated Resource Descriptors Command (indirect 0x020A)
241 #define ICE_AQC_RES_TYPE_VSI_LIST_REP 0x03
242 #define ICE_AQC_RES_TYPE_VSI_LIST_PRUNE 0x04
244 #define ICE_AQC_RES_TYPE_FLAG_SHARED BIT(7)
245 #define ICE_AQC_RES_TYPE_FLAG_SCAN_BOTTOM BIT(12)
246 #define ICE_AQC_RES_TYPE_FLAG_IGNORE_INDEX BIT(13)
248 #define ICE_AQC_RES_TYPE_FLAG_DEDICATED 0x00
252 /* Allocate Resources command (indirect 0x0208)
253 * Free Resources command (indirect 0x0209)
255 struct ice_aqc_alloc_free_res_cmd {
256 __le16 num_entries; /* Number of Resource entries */
263 /* Resource descriptor */
264 struct ice_aqc_res_elem {
272 /* Buffer for Allocate/Free Resources commands */
273 struct ice_aqc_alloc_free_res_elem {
274 __le16 res_type; /* Types defined above cmd 0x0204 */
275 #define ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_S 8
276 #define ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_M \
277 (0xF << ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_S)
279 struct ice_aqc_res_elem elem[1];
285 /* Add VSI (indirect 0x0210)
286 * Update VSI (indirect 0x0211)
287 * Get VSI (indirect 0x0212)
288 * Free VSI (indirect 0x0213)
290 struct ice_aqc_add_get_update_free_vsi {
292 #define ICE_AQ_VSI_NUM_S 0
293 #define ICE_AQ_VSI_NUM_M (0x03FF << ICE_AQ_VSI_NUM_S)
294 #define ICE_AQ_VSI_IS_VALID BIT(15)
296 #define ICE_AQ_VSI_KEEP_ALLOC 0x1
300 #define ICE_AQ_VSI_TYPE_S 0
301 #define ICE_AQ_VSI_TYPE_M (0x3 << ICE_AQ_VSI_TYPE_S)
302 #define ICE_AQ_VSI_TYPE_VF 0x0
303 #define ICE_AQ_VSI_TYPE_VMDQ2 0x1
304 #define ICE_AQ_VSI_TYPE_PF 0x2
305 #define ICE_AQ_VSI_TYPE_EMP_MNG 0x3
311 /* Response descriptor for:
312 * Add VSI (indirect 0x0210)
313 * Update VSI (indirect 0x0211)
314 * Free VSI (indirect 0x0213)
316 struct ice_aqc_add_update_free_vsi_resp {
327 struct ice_aqc_vsi_props {
328 __le16 valid_sections;
329 #define ICE_AQ_VSI_PROP_SW_VALID BIT(0)
330 #define ICE_AQ_VSI_PROP_SECURITY_VALID BIT(1)
331 #define ICE_AQ_VSI_PROP_VLAN_VALID BIT(2)
332 #define ICE_AQ_VSI_PROP_OUTER_TAG_VALID BIT(3)
333 #define ICE_AQ_VSI_PROP_INGRESS_UP_VALID BIT(4)
334 #define ICE_AQ_VSI_PROP_EGRESS_UP_VALID BIT(5)
335 #define ICE_AQ_VSI_PROP_RXQ_MAP_VALID BIT(6)
336 #define ICE_AQ_VSI_PROP_Q_OPT_VALID BIT(7)
337 #define ICE_AQ_VSI_PROP_OUTER_UP_VALID BIT(8)
338 #define ICE_AQ_VSI_PROP_FLOW_DIR_VALID BIT(11)
339 #define ICE_AQ_VSI_PROP_PASID_VALID BIT(12)
343 #define ICE_AQ_VSI_SW_FLAG_ALLOW_LB BIT(5)
344 #define ICE_AQ_VSI_SW_FLAG_LOCAL_LB BIT(6)
345 #define ICE_AQ_VSI_SW_FLAG_SRC_PRUNE BIT(7)
347 #define ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_S 0
348 #define ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_M \
349 (0xF << ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_S)
350 #define ICE_AQ_VSI_SW_FLAG_RX_VLAN_PRUNE_ENA BIT(0)
351 #define ICE_AQ_VSI_SW_FLAG_LAN_ENA BIT(4)
353 #define ICE_AQ_VSI_SW_VEB_STAT_ID_S 0
354 #define ICE_AQ_VSI_SW_VEB_STAT_ID_M (0x1F << ICE_AQ_VSI_SW_VEB_STAT_ID_S)
355 #define ICE_AQ_VSI_SW_VEB_STAT_ID_VALID BIT(5)
356 /* security section */
358 #define ICE_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD BIT(0)
359 #define ICE_AQ_VSI_SEC_FLAG_ENA_MAC_ANTI_SPOOF BIT(2)
360 #define ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S 4
361 #define ICE_AQ_VSI_SEC_TX_PRUNE_ENA_M (0xF << ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S)
362 #define ICE_AQ_VSI_SEC_TX_VLAN_PRUNE_ENA BIT(0)
365 __le16 pvid; /* VLANS include priority bits */
366 u8 pvlan_reserved[2];
368 #define ICE_AQ_VSI_VLAN_MODE_S 0
369 #define ICE_AQ_VSI_VLAN_MODE_M (0x3 << ICE_AQ_VSI_VLAN_MODE_S)
370 #define ICE_AQ_VSI_VLAN_MODE_UNTAGGED 0x1
371 #define ICE_AQ_VSI_VLAN_MODE_TAGGED 0x2
372 #define ICE_AQ_VSI_VLAN_MODE_ALL 0x3
373 #define ICE_AQ_VSI_PVLAN_INSERT_PVID BIT(2)
374 #define ICE_AQ_VSI_VLAN_EMOD_S 3
375 #define ICE_AQ_VSI_VLAN_EMOD_M (0x3 << ICE_AQ_VSI_VLAN_EMOD_S)
376 #define ICE_AQ_VSI_VLAN_EMOD_STR_BOTH (0x0 << ICE_AQ_VSI_VLAN_EMOD_S)
377 #define ICE_AQ_VSI_VLAN_EMOD_STR_UP (0x1 << ICE_AQ_VSI_VLAN_EMOD_S)
378 #define ICE_AQ_VSI_VLAN_EMOD_STR (0x2 << ICE_AQ_VSI_VLAN_EMOD_S)
379 #define ICE_AQ_VSI_VLAN_EMOD_NOTHING (0x3 << ICE_AQ_VSI_VLAN_EMOD_S)
380 u8 pvlan_reserved2[3];
381 /* ingress egress up sections */
382 __le32 ingress_table; /* bitmap, 3 bits per up */
383 #define ICE_AQ_VSI_UP_TABLE_UP0_S 0
384 #define ICE_AQ_VSI_UP_TABLE_UP0_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP0_S)
385 #define ICE_AQ_VSI_UP_TABLE_UP1_S 3
386 #define ICE_AQ_VSI_UP_TABLE_UP1_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP1_S)
387 #define ICE_AQ_VSI_UP_TABLE_UP2_S 6
388 #define ICE_AQ_VSI_UP_TABLE_UP2_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP2_S)
389 #define ICE_AQ_VSI_UP_TABLE_UP3_S 9
390 #define ICE_AQ_VSI_UP_TABLE_UP3_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP3_S)
391 #define ICE_AQ_VSI_UP_TABLE_UP4_S 12
392 #define ICE_AQ_VSI_UP_TABLE_UP4_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP4_S)
393 #define ICE_AQ_VSI_UP_TABLE_UP5_S 15
394 #define ICE_AQ_VSI_UP_TABLE_UP5_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP5_S)
395 #define ICE_AQ_VSI_UP_TABLE_UP6_S 18
396 #define ICE_AQ_VSI_UP_TABLE_UP6_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP6_S)
397 #define ICE_AQ_VSI_UP_TABLE_UP7_S 21
398 #define ICE_AQ_VSI_UP_TABLE_UP7_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP7_S)
399 __le32 egress_table; /* same defines as for ingress table */
400 /* outer tags section */
403 #define ICE_AQ_VSI_OUTER_TAG_MODE_S 0
404 #define ICE_AQ_VSI_OUTER_TAG_MODE_M (0x3 << ICE_AQ_VSI_OUTER_TAG_MODE_S)
405 #define ICE_AQ_VSI_OUTER_TAG_NOTHING 0x0
406 #define ICE_AQ_VSI_OUTER_TAG_REMOVE 0x1
407 #define ICE_AQ_VSI_OUTER_TAG_COPY 0x2
408 #define ICE_AQ_VSI_OUTER_TAG_TYPE_S 2
409 #define ICE_AQ_VSI_OUTER_TAG_TYPE_M (0x3 << ICE_AQ_VSI_OUTER_TAG_TYPE_S)
410 #define ICE_AQ_VSI_OUTER_TAG_NONE 0x0
411 #define ICE_AQ_VSI_OUTER_TAG_STAG 0x1
412 #define ICE_AQ_VSI_OUTER_TAG_VLAN_8100 0x2
413 #define ICE_AQ_VSI_OUTER_TAG_VLAN_9100 0x3
414 #define ICE_AQ_VSI_OUTER_TAG_INSERT BIT(4)
415 #define ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST BIT(6)
416 u8 outer_tag_reserved;
417 /* queue mapping section */
418 __le16 mapping_flags;
419 #define ICE_AQ_VSI_Q_MAP_CONTIG 0x0
420 #define ICE_AQ_VSI_Q_MAP_NONCONTIG BIT(0)
421 __le16 q_mapping[16];
422 #define ICE_AQ_VSI_Q_S 0
423 #define ICE_AQ_VSI_Q_M (0x7FF << ICE_AQ_VSI_Q_S)
424 __le16 tc_mapping[8];
425 #define ICE_AQ_VSI_TC_Q_OFFSET_S 0
426 #define ICE_AQ_VSI_TC_Q_OFFSET_M (0x7FF << ICE_AQ_VSI_TC_Q_OFFSET_S)
427 #define ICE_AQ_VSI_TC_Q_NUM_S 11
428 #define ICE_AQ_VSI_TC_Q_NUM_M (0xF << ICE_AQ_VSI_TC_Q_NUM_S)
429 /* queueing option section */
431 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_S 0
432 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_M (0x3 << ICE_AQ_VSI_Q_OPT_RSS_LUT_S)
433 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_VSI 0x0
434 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_PF 0x2
435 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_GBL 0x3
436 #define ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_S 2
437 #define ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_M (0xF << ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_S)
438 #define ICE_AQ_VSI_Q_OPT_RSS_HASH_S 6
439 #define ICE_AQ_VSI_Q_OPT_RSS_HASH_M (0x3 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S)
440 #define ICE_AQ_VSI_Q_OPT_RSS_TPLZ (0x0 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S)
441 #define ICE_AQ_VSI_Q_OPT_RSS_SYM_TPLZ (0x1 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S)
442 #define ICE_AQ_VSI_Q_OPT_RSS_XOR (0x2 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S)
443 #define ICE_AQ_VSI_Q_OPT_RSS_JHASH (0x3 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S)
445 #define ICE_AQ_VSI_Q_OPT_TC_OVR_S 0
446 #define ICE_AQ_VSI_Q_OPT_TC_OVR_M (0x1F << ICE_AQ_VSI_Q_OPT_TC_OVR_S)
447 #define ICE_AQ_VSI_Q_OPT_PROF_TC_OVR BIT(7)
449 #define ICE_AQ_VSI_Q_OPT_PE_FLTR_EN BIT(0)
450 u8 q_opt_reserved[3];
451 /* outer up section */
452 __le32 outer_up_table; /* same structure and defines as ingress tbl */
454 __le16 sect_10_reserved;
455 /* flow director section */
457 #define ICE_AQ_VSI_FD_ENABLE BIT(0)
458 #define ICE_AQ_VSI_FD_TX_AUTO_ENABLE BIT(1)
459 #define ICE_AQ_VSI_FD_PROG_ENABLE BIT(3)
460 __le16 max_fd_fltr_dedicated;
461 __le16 max_fd_fltr_shared;
463 #define ICE_AQ_VSI_FD_DEF_Q_S 0
464 #define ICE_AQ_VSI_FD_DEF_Q_M (0x7FF << ICE_AQ_VSI_FD_DEF_Q_S)
465 #define ICE_AQ_VSI_FD_DEF_GRP_S 12
466 #define ICE_AQ_VSI_FD_DEF_GRP_M (0x7 << ICE_AQ_VSI_FD_DEF_GRP_S)
467 __le16 fd_report_opt;
468 #define ICE_AQ_VSI_FD_REPORT_Q_S 0
469 #define ICE_AQ_VSI_FD_REPORT_Q_M (0x7FF << ICE_AQ_VSI_FD_REPORT_Q_S)
470 #define ICE_AQ_VSI_FD_DEF_PRIORITY_S 12
471 #define ICE_AQ_VSI_FD_DEF_PRIORITY_M (0x7 << ICE_AQ_VSI_FD_DEF_PRIORITY_S)
472 #define ICE_AQ_VSI_FD_DEF_DROP BIT(15)
475 #define ICE_AQ_VSI_PASID_ID_S 0
476 #define ICE_AQ_VSI_PASID_ID_M (0xFFFFF << ICE_AQ_VSI_PASID_ID_S)
477 #define ICE_AQ_VSI_PASID_ID_VALID BIT(31)
483 #define ICE_MAX_NUM_RECIPES 64
486 /* Add/Update/Remove/Get switch rules (indirect 0x02A0, 0x02A1, 0x02A2, 0x02A3)
488 struct ice_aqc_sw_rules {
489 /* ops: add switch rules, referring the number of rules.
490 * ops: update switch rules, referring the number of filters
491 * ops: remove switch rules, referring the entry index.
492 * ops: get switch rules, referring to the number of filters.
494 __le16 num_rules_fltr_entry_index;
502 /* Add/Update/Get/Remove lookup Rx/Tx command/response entry
503 * This structures describes the lookup rules and associated actions. "index"
504 * is returned as part of a response to a successful Add command, and can be
505 * used to identify the rule for Update/Get/Remove commands.
507 struct ice_sw_rule_lkup_rx_tx {
509 #define ICE_SW_RECIPE_LOGICAL_PORT_FWD 10
510 /* Source port for LOOKUP_RX and source VSI in case of LOOKUP_TX */
514 /* Bit 0:1 - Action type */
515 #define ICE_SINGLE_ACT_TYPE_S 0x00
516 #define ICE_SINGLE_ACT_TYPE_M (0x3 << ICE_SINGLE_ACT_TYPE_S)
518 /* Bit 2 - Loop back enable
521 #define ICE_SINGLE_ACT_LB_ENABLE BIT(2)
522 #define ICE_SINGLE_ACT_LAN_ENABLE BIT(3)
524 /* Action type = 0 - Forward to VSI or VSI list */
525 #define ICE_SINGLE_ACT_VSI_FORWARDING 0x0
527 #define ICE_SINGLE_ACT_VSI_ID_S 4
528 #define ICE_SINGLE_ACT_VSI_ID_M (0x3FF << ICE_SINGLE_ACT_VSI_ID_S)
529 #define ICE_SINGLE_ACT_VSI_LIST_ID_S 4
530 #define ICE_SINGLE_ACT_VSI_LIST_ID_M (0x3FF << ICE_SINGLE_ACT_VSI_LIST_ID_S)
531 /* This bit needs to be set if action is forward to VSI list */
532 #define ICE_SINGLE_ACT_VSI_LIST BIT(14)
533 #define ICE_SINGLE_ACT_VALID_BIT BIT(17)
534 #define ICE_SINGLE_ACT_DROP BIT(18)
536 /* Action type = 1 - Forward to Queue of Queue group */
537 #define ICE_SINGLE_ACT_TO_Q 0x1
538 #define ICE_SINGLE_ACT_Q_INDEX_S 4
539 #define ICE_SINGLE_ACT_Q_INDEX_M (0x7FF << ICE_SINGLE_ACT_Q_INDEX_S)
540 #define ICE_SINGLE_ACT_Q_REGION_S 15
541 #define ICE_SINGLE_ACT_Q_REGION_M (0x7 << ICE_SINGLE_ACT_Q_REGION_S)
542 #define ICE_SINGLE_ACT_Q_PRIORITY BIT(18)
544 /* Action type = 2 - Prune */
545 #define ICE_SINGLE_ACT_PRUNE 0x2
546 #define ICE_SINGLE_ACT_EGRESS BIT(15)
547 #define ICE_SINGLE_ACT_INGRESS BIT(16)
548 #define ICE_SINGLE_ACT_PRUNET BIT(17)
549 /* Bit 18 should be set to 0 for this action */
551 /* Action type = 2 - Pointer */
552 #define ICE_SINGLE_ACT_PTR 0x2
553 #define ICE_SINGLE_ACT_PTR_VAL_S 4
554 #define ICE_SINGLE_ACT_PTR_VAL_M (0x1FFF << ICE_SINGLE_ACT_PTR_VAL_S)
555 /* Bit 18 should be set to 1 */
556 #define ICE_SINGLE_ACT_PTR_BIT BIT(18)
558 /* Action type = 3 - Other actions. Last two bits
559 * are other action identifier
561 #define ICE_SINGLE_ACT_OTHER_ACTS 0x3
562 #define ICE_SINGLE_OTHER_ACT_IDENTIFIER_S 17
563 #define ICE_SINGLE_OTHER_ACT_IDENTIFIER_M \
564 (0x3 << \ ICE_SINGLE_OTHER_ACT_IDENTIFIER_S)
566 /* Bit 17:18 - Defines other actions */
567 /* Other action = 0 - Mirror VSI */
568 #define ICE_SINGLE_OTHER_ACT_MIRROR 0
569 #define ICE_SINGLE_ACT_MIRROR_VSI_ID_S 4
570 #define ICE_SINGLE_ACT_MIRROR_VSI_ID_M \
571 (0x3FF << ICE_SINGLE_ACT_MIRROR_VSI_ID_S)
573 /* Other action = 3 - Set Stat count */
574 #define ICE_SINGLE_OTHER_ACT_STAT_COUNT 3
575 #define ICE_SINGLE_ACT_STAT_COUNT_INDEX_S 4
576 #define ICE_SINGLE_ACT_STAT_COUNT_INDEX_M \
577 (0x7F << ICE_SINGLE_ACT_STAT_COUNT_INDEX_S)
579 __le16 index; /* The index of the rule in the lookup table */
580 /* Length and values of the header to be matched per recipe or
589 /* Add/Update/Remove large action command/response entry
590 * "index" is returned as part of a response to a successful Add command, and
591 * can be used to identify the action for Update/Get/Remove commands.
593 struct ice_sw_rule_lg_act {
594 __le16 index; /* Index in large action table */
596 __le32 act[1]; /* array of size for actions */
597 /* Max number of large actions */
598 #define ICE_MAX_LG_ACT 4
599 /* Bit 0:1 - Action type */
600 #define ICE_LG_ACT_TYPE_S 0
601 #define ICE_LG_ACT_TYPE_M (0x7 << ICE_LG_ACT_TYPE_S)
603 /* Action type = 0 - Forward to VSI or VSI list */
604 #define ICE_LG_ACT_VSI_FORWARDING 0
605 #define ICE_LG_ACT_VSI_ID_S 3
606 #define ICE_LG_ACT_VSI_ID_M (0x3FF << ICE_LG_ACT_VSI_ID_S)
607 #define ICE_LG_ACT_VSI_LIST_ID_S 3
608 #define ICE_LG_ACT_VSI_LIST_ID_M (0x3FF << ICE_LG_ACT_VSI_LIST_ID_S)
609 /* This bit needs to be set if action is forward to VSI list */
610 #define ICE_LG_ACT_VSI_LIST BIT(13)
612 #define ICE_LG_ACT_VALID_BIT BIT(16)
614 /* Action type = 1 - Forward to Queue of Queue group */
615 #define ICE_LG_ACT_TO_Q 0x1
616 #define ICE_LG_ACT_Q_INDEX_S 3
617 #define ICE_LG_ACT_Q_INDEX_M (0x7FF << ICE_LG_ACT_Q_INDEX_S)
618 #define ICE_LG_ACT_Q_REGION_S 14
619 #define ICE_LG_ACT_Q_REGION_M (0x7 << ICE_LG_ACT_Q_REGION_S)
620 #define ICE_LG_ACT_Q_PRIORITY_SET BIT(17)
622 /* Action type = 2 - Prune */
623 #define ICE_LG_ACT_PRUNE 0x2
624 #define ICE_LG_ACT_EGRESS BIT(14)
625 #define ICE_LG_ACT_INGRESS BIT(15)
626 #define ICE_LG_ACT_PRUNET BIT(16)
628 /* Action type = 3 - Mirror VSI */
629 #define ICE_LG_OTHER_ACT_MIRROR 0x3
630 #define ICE_LG_ACT_MIRROR_VSI_ID_S 3
631 #define ICE_LG_ACT_MIRROR_VSI_ID_M (0x3FF << ICE_LG_ACT_MIRROR_VSI_ID_S)
633 /* Action type = 5 - Generic Value */
634 #define ICE_LG_ACT_GENERIC 0x5
635 #define ICE_LG_ACT_GENERIC_VALUE_S 3
636 #define ICE_LG_ACT_GENERIC_VALUE_M (0xFFFF << ICE_LG_ACT_GENERIC_VALUE_S)
637 #define ICE_LG_ACT_GENERIC_OFFSET_S 19
638 #define ICE_LG_ACT_GENERIC_OFFSET_M (0x7 << ICE_LG_ACT_GENERIC_OFFSET_S)
639 #define ICE_LG_ACT_GENERIC_PRIORITY_S 22
640 #define ICE_LG_ACT_GENERIC_PRIORITY_M (0x7 << ICE_LG_ACT_GENERIC_PRIORITY_S)
641 #define ICE_LG_ACT_GENERIC_OFF_RX_DESC_PROF_IDX 7
643 /* Action = 7 - Set Stat count */
644 #define ICE_LG_ACT_STAT_COUNT 0x7
645 #define ICE_LG_ACT_STAT_COUNT_S 3
646 #define ICE_LG_ACT_STAT_COUNT_M (0x7F << ICE_LG_ACT_STAT_COUNT_S)
650 /* Add/Update/Remove VSI list command/response entry
651 * "index" is returned as part of a response to a successful Add command, and
652 * can be used to identify the VSI list for Update/Get/Remove commands.
654 struct ice_sw_rule_vsi_list {
655 __le16 index; /* Index of VSI/Prune list */
657 __le16 vsi[1]; /* Array of number_vsi VSI numbers */
662 /* Query VSI list command/response entry */
663 struct ice_sw_rule_vsi_list_query {
665 ice_declare_bitmap(vsi_list, ICE_MAX_VSI);
671 /* Add switch rule response:
672 * Content of return buffer is same as the input buffer. The status field and
673 * LUT index are updated as part of the response
675 struct ice_aqc_sw_rules_elem {
676 __le16 type; /* Switch rule type, one of T_... */
677 #define ICE_AQC_SW_RULES_T_LKUP_RX 0x0
678 #define ICE_AQC_SW_RULES_T_LKUP_TX 0x1
679 #define ICE_AQC_SW_RULES_T_LG_ACT 0x2
680 #define ICE_AQC_SW_RULES_T_VSI_LIST_SET 0x3
681 #define ICE_AQC_SW_RULES_T_VSI_LIST_CLEAR 0x4
682 #define ICE_AQC_SW_RULES_T_PRUNE_LIST_SET 0x5
683 #define ICE_AQC_SW_RULES_T_PRUNE_LIST_CLEAR 0x6
686 struct ice_sw_rule_lkup_rx_tx lkup_tx_rx;
687 struct ice_sw_rule_lg_act lg_act;
688 struct ice_sw_rule_vsi_list vsi_list;
689 struct ice_sw_rule_vsi_list_query vsi_list_query;
697 /* Get Default Topology (indirect 0x0400) */
698 struct ice_aqc_get_topo {
708 /* Update TSE (indirect 0x0403)
709 * Get TSE (indirect 0x0404)
710 * Add TSE (indirect 0x0401)
711 * Delete TSE (indirect 0x040F)
712 * Move TSE (indirect 0x0408)
713 * Suspend Nodes (indirect 0x0409)
714 * Resume Nodes (indirect 0x040A)
716 struct ice_aqc_sched_elem_cmd {
717 __le16 num_elem_req; /* Used by commands */
718 __le16 num_elem_resp; /* Used by responses */
725 /* This is the buffer for:
726 * Suspend Nodes (indirect 0x0409)
727 * Resume Nodes (indirect 0x040A)
729 struct ice_aqc_suspend_resume_elem {
734 struct ice_aqc_txsched_move_grp_info_hdr {
735 __le32 src_parent_teid;
736 __le32 dest_parent_teid;
742 struct ice_aqc_move_elem {
743 struct ice_aqc_txsched_move_grp_info_hdr hdr;
748 struct ice_aqc_elem_info_bw {
749 __le16 bw_profile_idx;
754 struct ice_aqc_txsched_elem {
755 u8 elem_type; /* Special field, reserved for some aq calls */
756 #define ICE_AQC_ELEM_TYPE_UNDEFINED 0x0
757 #define ICE_AQC_ELEM_TYPE_ROOT_PORT 0x1
758 #define ICE_AQC_ELEM_TYPE_TC 0x2
759 #define ICE_AQC_ELEM_TYPE_SE_GENERIC 0x3
760 #define ICE_AQC_ELEM_TYPE_ENTRY_POINT 0x4
761 #define ICE_AQC_ELEM_TYPE_LEAF 0x5
762 #define ICE_AQC_ELEM_TYPE_SE_PADDED 0x6
764 #define ICE_AQC_ELEM_VALID_GENERIC BIT(0)
765 #define ICE_AQC_ELEM_VALID_CIR BIT(1)
766 #define ICE_AQC_ELEM_VALID_EIR BIT(2)
767 #define ICE_AQC_ELEM_VALID_SHARED BIT(3)
769 #define ICE_AQC_ELEM_GENERIC_MODE_M 0x1
770 #define ICE_AQC_ELEM_GENERIC_PRIO_S 0x1
771 #define ICE_AQC_ELEM_GENERIC_PRIO_M (0x7 << ICE_AQC_ELEM_GENERIC_PRIO_S)
772 #define ICE_AQC_ELEM_GENERIC_SP_S 0x4
773 #define ICE_AQC_ELEM_GENERIC_SP_M (0x1 << ICE_AQC_ELEM_GENERIC_SP_S)
774 #define ICE_AQC_ELEM_GENERIC_ADJUST_VAL_S 0x5
775 #define ICE_AQC_ELEM_GENERIC_ADJUST_VAL_M \
776 (0x3 << ICE_AQC_ELEM_GENERIC_ADJUST_VAL_S)
777 u8 flags; /* Special field, reserved for some aq calls */
778 #define ICE_AQC_ELEM_FLAG_SUSPEND_M 0x1
779 struct ice_aqc_elem_info_bw cir_bw;
780 struct ice_aqc_elem_info_bw eir_bw;
786 struct ice_aqc_txsched_elem_data {
789 struct ice_aqc_txsched_elem data;
793 struct ice_aqc_txsched_topo_grp_info_hdr {
800 struct ice_aqc_add_elem {
801 struct ice_aqc_txsched_topo_grp_info_hdr hdr;
802 struct ice_aqc_txsched_elem_data generic[1];
806 struct ice_aqc_conf_elem {
807 struct ice_aqc_txsched_elem_data generic[1];
811 struct ice_aqc_get_elem {
812 struct ice_aqc_txsched_elem_data generic[1];
816 struct ice_aqc_get_topo_elem {
817 struct ice_aqc_txsched_topo_grp_info_hdr hdr;
818 struct ice_aqc_txsched_elem_data
819 generic[ICE_AQC_TOPO_MAX_LEVEL_NUM];
823 struct ice_aqc_delete_elem {
824 struct ice_aqc_txsched_topo_grp_info_hdr hdr;
831 /* Rate limiting profile for
832 * Add RL profile (indirect 0x0410)
833 * Query RL profile (indirect 0x0411)
834 * Remove RL profile (indirect 0x0415)
835 * These indirect commands acts on single or multiple
836 * RL profiles with specified data.
838 struct ice_aqc_rl_profile {
840 __le16 num_processed; /* Only for response. Reserved in Command. */
847 struct ice_aqc_rl_profile_elem {
850 #define ICE_AQC_RL_PROFILE_TYPE_S 0x0
851 #define ICE_AQC_RL_PROFILE_TYPE_M (0x3 << ICE_AQC_RL_PROFILE_TYPE_S)
852 #define ICE_AQC_RL_PROFILE_TYPE_CIR 0
853 #define ICE_AQC_RL_PROFILE_TYPE_EIR 1
854 #define ICE_AQC_RL_PROFILE_TYPE_SRL 2
855 /* The following flag is used for Query RL Profile Data */
856 #define ICE_AQC_RL_PROFILE_INVAL_S 0x7
857 #define ICE_AQC_RL_PROFILE_INVAL_M (0x1 << ICE_AQC_RL_PROFILE_INVAL_S)
860 __le16 max_burst_size;
867 struct ice_aqc_rl_profile_generic_elem {
868 struct ice_aqc_rl_profile_elem generic[1];
873 /* Configure L2 Node CGD (indirect 0x0414)
874 * This indirect command allows configuring a congestion domain for given L2
875 * node TEIDs in the scheduler topology.
877 struct ice_aqc_cfg_l2_node_cgd {
885 struct ice_aqc_cfg_l2_node_cgd_elem {
892 struct ice_aqc_cfg_l2_node_cgd_data {
893 struct ice_aqc_cfg_l2_node_cgd_elem elem[1];
897 /* Query Scheduler Resource Allocation (indirect 0x0412)
898 * This indirect command retrieves the scheduler resources allocated by
899 * EMP Firmware to the given PF.
901 struct ice_aqc_query_txsched_res {
908 struct ice_aqc_generic_sched_props {
910 __le16 logical_levels;
911 u8 flattening_bitmap;
920 struct ice_aqc_layer_props {
923 __le16 max_device_nodes;
926 __le16 max_sibl_grp_sz;
927 __le16 max_cir_rl_profiles;
928 __le16 max_eir_rl_profiles;
929 __le16 max_srl_profiles;
934 struct ice_aqc_query_txsched_res_resp {
935 struct ice_aqc_generic_sched_props sched_props;
936 struct ice_aqc_layer_props layer_props[ICE_AQC_TOPO_MAX_LEVEL_NUM];
940 /* Query Node to Root Topology (indirect 0x0413)
941 * This command uses ice_aqc_get_elem as its data buffer.
943 struct ice_aqc_query_node_to_root {
945 __le32 num_nodes; /* Response only */
951 /* Get PHY capabilities (indirect 0x0600) */
952 struct ice_aqc_get_phy_caps {
956 /* 18.0 - Report qualified modules */
957 #define ICE_AQC_GET_PHY_RQM BIT(0)
958 /* 18.1 - 18.2 : Report mode
959 * 00b - Report NVM capabilities
960 * 01b - Report topology capabilities
961 * 10b - Report SW configured
963 #define ICE_AQC_REPORT_MODE_S 1
964 #define ICE_AQC_REPORT_MODE_M (3 << ICE_AQC_REPORT_MODE_S)
965 #define ICE_AQC_REPORT_NVM_CAP 0
966 #define ICE_AQC_REPORT_TOPO_CAP BIT(1)
967 #define ICE_AQC_REPORT_SW_CFG BIT(2)
974 /* This is #define of PHY type (Extended):
975 * The first set of defines is for phy_type_low.
977 #define ICE_PHY_TYPE_LOW_100BASE_TX BIT_ULL(0)
978 #define ICE_PHY_TYPE_LOW_100M_SGMII BIT_ULL(1)
979 #define ICE_PHY_TYPE_LOW_1000BASE_T BIT_ULL(2)
980 #define ICE_PHY_TYPE_LOW_1000BASE_SX BIT_ULL(3)
981 #define ICE_PHY_TYPE_LOW_1000BASE_LX BIT_ULL(4)
982 #define ICE_PHY_TYPE_LOW_1000BASE_KX BIT_ULL(5)
983 #define ICE_PHY_TYPE_LOW_1G_SGMII BIT_ULL(6)
984 #define ICE_PHY_TYPE_LOW_2500BASE_T BIT_ULL(7)
985 #define ICE_PHY_TYPE_LOW_2500BASE_X BIT_ULL(8)
986 #define ICE_PHY_TYPE_LOW_2500BASE_KX BIT_ULL(9)
987 #define ICE_PHY_TYPE_LOW_5GBASE_T BIT_ULL(10)
988 #define ICE_PHY_TYPE_LOW_5GBASE_KR BIT_ULL(11)
989 #define ICE_PHY_TYPE_LOW_10GBASE_T BIT_ULL(12)
990 #define ICE_PHY_TYPE_LOW_10G_SFI_DA BIT_ULL(13)
991 #define ICE_PHY_TYPE_LOW_10GBASE_SR BIT_ULL(14)
992 #define ICE_PHY_TYPE_LOW_10GBASE_LR BIT_ULL(15)
993 #define ICE_PHY_TYPE_LOW_10GBASE_KR_CR1 BIT_ULL(16)
994 #define ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC BIT_ULL(17)
995 #define ICE_PHY_TYPE_LOW_10G_SFI_C2C BIT_ULL(18)
996 #define ICE_PHY_TYPE_LOW_25GBASE_T BIT_ULL(19)
997 #define ICE_PHY_TYPE_LOW_25GBASE_CR BIT_ULL(20)
998 #define ICE_PHY_TYPE_LOW_25GBASE_CR_S BIT_ULL(21)
999 #define ICE_PHY_TYPE_LOW_25GBASE_CR1 BIT_ULL(22)
1000 #define ICE_PHY_TYPE_LOW_25GBASE_SR BIT_ULL(23)
1001 #define ICE_PHY_TYPE_LOW_25GBASE_LR BIT_ULL(24)
1002 #define ICE_PHY_TYPE_LOW_25GBASE_KR BIT_ULL(25)
1003 #define ICE_PHY_TYPE_LOW_25GBASE_KR_S BIT_ULL(26)
1004 #define ICE_PHY_TYPE_LOW_25GBASE_KR1 BIT_ULL(27)
1005 #define ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC BIT_ULL(28)
1006 #define ICE_PHY_TYPE_LOW_25G_AUI_C2C BIT_ULL(29)
1007 #define ICE_PHY_TYPE_LOW_40GBASE_CR4 BIT_ULL(30)
1008 #define ICE_PHY_TYPE_LOW_40GBASE_SR4 BIT_ULL(31)
1009 #define ICE_PHY_TYPE_LOW_40GBASE_LR4 BIT_ULL(32)
1010 #define ICE_PHY_TYPE_LOW_40GBASE_KR4 BIT_ULL(33)
1011 #define ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC BIT_ULL(34)
1012 #define ICE_PHY_TYPE_LOW_40G_XLAUI BIT_ULL(35)
1013 #define ICE_PHY_TYPE_LOW_50GBASE_CR2 BIT_ULL(36)
1014 #define ICE_PHY_TYPE_LOW_50GBASE_SR2 BIT_ULL(37)
1015 #define ICE_PHY_TYPE_LOW_50GBASE_LR2 BIT_ULL(38)
1016 #define ICE_PHY_TYPE_LOW_50GBASE_KR2 BIT_ULL(39)
1017 #define ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC BIT_ULL(40)
1018 #define ICE_PHY_TYPE_LOW_50G_LAUI2 BIT_ULL(41)
1019 #define ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC BIT_ULL(42)
1020 #define ICE_PHY_TYPE_LOW_50G_AUI2 BIT_ULL(43)
1021 #define ICE_PHY_TYPE_LOW_50GBASE_CP BIT_ULL(44)
1022 #define ICE_PHY_TYPE_LOW_50GBASE_SR BIT_ULL(45)
1023 #define ICE_PHY_TYPE_LOW_50GBASE_FR BIT_ULL(46)
1024 #define ICE_PHY_TYPE_LOW_50GBASE_LR BIT_ULL(47)
1025 #define ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4 BIT_ULL(48)
1026 #define ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC BIT_ULL(49)
1027 #define ICE_PHY_TYPE_LOW_50G_AUI1 BIT_ULL(50)
1028 #define ICE_PHY_TYPE_LOW_100GBASE_CR4 BIT_ULL(51)
1029 #define ICE_PHY_TYPE_LOW_100GBASE_SR4 BIT_ULL(52)
1030 #define ICE_PHY_TYPE_LOW_100GBASE_LR4 BIT_ULL(53)
1031 #define ICE_PHY_TYPE_LOW_100GBASE_KR4 BIT_ULL(54)
1032 #define ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC BIT_ULL(55)
1033 #define ICE_PHY_TYPE_LOW_100G_CAUI4 BIT_ULL(56)
1034 #define ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC BIT_ULL(57)
1035 #define ICE_PHY_TYPE_LOW_100G_AUI4 BIT_ULL(58)
1036 #define ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4 BIT_ULL(59)
1037 #define ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4 BIT_ULL(60)
1038 #define ICE_PHY_TYPE_LOW_100GBASE_CP2 BIT_ULL(61)
1039 #define ICE_PHY_TYPE_LOW_100GBASE_SR2 BIT_ULL(62)
1040 #define ICE_PHY_TYPE_LOW_100GBASE_DR BIT_ULL(63)
1041 #define ICE_PHY_TYPE_LOW_MAX_INDEX 63
1042 /* The second set of defines is for phy_type_high. */
1043 #define ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4 BIT_ULL(0)
1044 #define ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC BIT_ULL(1)
1045 #define ICE_PHY_TYPE_HIGH_100G_CAUI2 BIT_ULL(2)
1046 #define ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC BIT_ULL(3)
1047 #define ICE_PHY_TYPE_HIGH_100G_AUI2 BIT_ULL(4)
1048 #define ICE_PHY_TYPE_HIGH_MAX_INDEX 19
1050 struct ice_aqc_get_phy_caps_data {
1051 __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */
1052 __le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */
1054 #define ICE_AQC_PHY_EN_TX_LINK_PAUSE BIT(0)
1055 #define ICE_AQC_PHY_EN_RX_LINK_PAUSE BIT(1)
1056 #define ICE_AQC_PHY_LOW_POWER_MODE BIT(2)
1057 #define ICE_AQC_PHY_EN_LINK BIT(3)
1058 #define ICE_AQC_PHY_AN_MODE BIT(4)
1059 #define ICE_AQC_PHY_EN_MOD_QUAL BIT(5)
1060 #define ICE_AQC_PHY_EN_LESM BIT(6)
1061 #define ICE_AQC_PHY_EN_AUTO_FEC BIT(7)
1062 #define ICE_AQC_PHY_CAPS_MASK MAKEMASK(0xff, 0)
1064 #define ICE_AQC_PHY_EN_D3COLD_LOW_POWER_AUTONEG BIT(0)
1066 #define ICE_AQC_PHY_EEE_EN_100BASE_TX BIT(0)
1067 #define ICE_AQC_PHY_EEE_EN_1000BASE_T BIT(1)
1068 #define ICE_AQC_PHY_EEE_EN_10GBASE_T BIT(2)
1069 #define ICE_AQC_PHY_EEE_EN_1000BASE_KX BIT(3)
1070 #define ICE_AQC_PHY_EEE_EN_10GBASE_KR BIT(4)
1071 #define ICE_AQC_PHY_EEE_EN_25GBASE_KR BIT(5)
1072 #define ICE_AQC_PHY_EEE_EN_40GBASE_KR4 BIT(6)
1073 #define ICE_AQC_PHY_EEE_EN_50GBASE_KR2 BIT(7)
1074 #define ICE_AQC_PHY_EEE_EN_50GBASE_KR_PAM4 BIT(8)
1075 #define ICE_AQC_PHY_EEE_EN_100GBASE_KR4 BIT(9)
1076 #define ICE_AQC_PHY_EEE_EN_100GBASE_KR2_PAM4 BIT(10)
1078 u8 phy_id_oui[4]; /* PHY/Module ID connected on the port */
1080 u8 link_fec_options;
1081 #define ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN BIT(0)
1082 #define ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ BIT(1)
1083 #define ICE_AQC_PHY_FEC_25G_RS_528_REQ BIT(2)
1084 #define ICE_AQC_PHY_FEC_25G_KR_REQ BIT(3)
1085 #define ICE_AQC_PHY_FEC_25G_RS_544_REQ BIT(4)
1086 #define ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN BIT(6)
1087 #define ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN BIT(7)
1088 #define ICE_AQC_PHY_FEC_MASK MAKEMASK(0xdf, 0)
1089 u8 extended_compliance_code;
1090 #define ICE_MODULE_TYPE_TOTAL_BYTE 3
1091 u8 module_type[ICE_MODULE_TYPE_TOTAL_BYTE];
1092 #define ICE_AQC_MOD_TYPE_BYTE0_SFP_PLUS 0xA0
1093 #define ICE_AQC_MOD_TYPE_BYTE0_QSFP_PLUS 0x80
1094 #define ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_PASSIVE BIT(0)
1095 #define ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_ACTIVE BIT(1)
1096 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_SR BIT(4)
1097 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_LR BIT(5)
1098 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_LRM BIT(6)
1099 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_ER BIT(7)
1100 #define ICE_AQC_MOD_TYPE_BYTE2_SFP_PLUS 0xA0
1101 #define ICE_AQC_MOD_TYPE_BYTE2_QSFP_PLUS 0x86
1102 u8 qualified_module_count;
1103 #define ICE_AQC_QUAL_MOD_COUNT_MAX 16
1110 } qual_modules[ICE_AQC_QUAL_MOD_COUNT_MAX];
1114 /* Set PHY capabilities (direct 0x0601)
1115 * NOTE: This command must be followed by setup link and restart auto-neg
1117 struct ice_aqc_set_phy_cfg {
1125 /* Set PHY config command data structure */
1126 struct ice_aqc_set_phy_cfg_data {
1127 __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */
1128 __le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */
1130 #define ICE_AQ_PHY_ENA_TX_PAUSE_ABILITY BIT(0)
1131 #define ICE_AQ_PHY_ENA_RX_PAUSE_ABILITY BIT(1)
1132 #define ICE_AQ_PHY_ENA_LOW_POWER BIT(2)
1133 #define ICE_AQ_PHY_ENA_LINK BIT(3)
1134 #define ICE_AQ_PHY_ENA_AUTO_LINK_UPDT BIT(5)
1135 #define ICE_AQ_PHY_ENA_LESM BIT(6)
1136 #define ICE_AQ_PHY_ENA_AUTO_FEC BIT(7)
1138 __le16 eee_cap; /* Value from ice_aqc_get_phy_caps */
1140 u8 link_fec_opt; /* Use defines from ice_aqc_get_phy_caps */
1146 /* Restart AN command data structure (direct 0x0605)
1147 * Also used for response, with only the lport_num field present.
1149 struct ice_aqc_restart_an {
1153 #define ICE_AQC_RESTART_AN_LINK_RESTART BIT(1)
1154 #define ICE_AQC_RESTART_AN_LINK_ENABLE BIT(2)
1159 /* Get link status (indirect 0x0607), also used for Link Status Event */
1160 struct ice_aqc_get_link_status {
1164 #define ICE_AQ_LSE_M 0x3
1165 #define ICE_AQ_LSE_NOP 0x0
1166 #define ICE_AQ_LSE_DIS 0x2
1167 #define ICE_AQ_LSE_ENA 0x3
1168 /* only response uses this flag */
1169 #define ICE_AQ_LSE_IS_ENABLED 0x1
1176 /* Get link status response data structure, also used for Link Status Event */
1177 struct ice_aqc_get_link_status_data {
1178 u8 topo_media_conflict;
1179 #define ICE_AQ_LINK_TOPO_CONFLICT BIT(0)
1180 #define ICE_AQ_LINK_MEDIA_CONFLICT BIT(1)
1181 #define ICE_AQ_LINK_TOPO_CORRUPT BIT(2)
1184 #define ICE_AQ_LINK_UP BIT(0) /* Link Status */
1185 #define ICE_AQ_LINK_FAULT BIT(1)
1186 #define ICE_AQ_LINK_FAULT_TX BIT(2)
1187 #define ICE_AQ_LINK_FAULT_RX BIT(3)
1188 #define ICE_AQ_LINK_FAULT_REMOTE BIT(4)
1189 #define ICE_AQ_LINK_UP_PORT BIT(5) /* External Port Link Status */
1190 #define ICE_AQ_MEDIA_AVAILABLE BIT(6)
1191 #define ICE_AQ_SIGNAL_DETECT BIT(7)
1193 #define ICE_AQ_AN_COMPLETED BIT(0)
1194 #define ICE_AQ_LP_AN_ABILITY BIT(1)
1195 #define ICE_AQ_PD_FAULT BIT(2) /* Parallel Detection Fault */
1196 #define ICE_AQ_FEC_EN BIT(3)
1197 #define ICE_AQ_PHY_LOW_POWER BIT(4) /* Low Power State */
1198 #define ICE_AQ_LINK_PAUSE_TX BIT(5)
1199 #define ICE_AQ_LINK_PAUSE_RX BIT(6)
1200 #define ICE_AQ_QUALIFIED_MODULE BIT(7)
1202 #define ICE_AQ_LINK_PHY_TEMP_ALARM BIT(0)
1203 #define ICE_AQ_LINK_EXCESSIVE_ERRORS BIT(1) /* Excessive Link Errors */
1204 /* Port TX Suspended */
1205 #define ICE_AQ_LINK_TX_S 2
1206 #define ICE_AQ_LINK_TX_M (0x03 << ICE_AQ_LINK_TX_S)
1207 #define ICE_AQ_LINK_TX_ACTIVE 0
1208 #define ICE_AQ_LINK_TX_DRAINED 1
1209 #define ICE_AQ_LINK_TX_FLUSHED 3
1211 __le16 max_frame_size;
1213 #define ICE_AQ_LINK_25G_KR_FEC_EN BIT(0)
1214 #define ICE_AQ_LINK_25G_RS_528_FEC_EN BIT(1)
1215 #define ICE_AQ_LINK_25G_RS_544_FEC_EN BIT(2)
1216 #define ICE_AQ_FEC_MASK MAKEMASK(0x7, 0)
1218 #define ICE_AQ_CFG_PACING_S 3
1219 #define ICE_AQ_CFG_PACING_M (0xF << ICE_AQ_CFG_PACING_S)
1220 #define ICE_AQ_CFG_PACING_TYPE_M BIT(7)
1221 #define ICE_AQ_CFG_PACING_TYPE_AVG 0
1222 #define ICE_AQ_CFG_PACING_TYPE_FIXED ICE_AQ_CFG_PACING_TYPE_M
1223 /* External Device Power Ability */
1225 #define ICE_AQ_PWR_CLASS_M 0x3
1226 #define ICE_AQ_LINK_PWR_BASET_LOW_HIGH 0
1227 #define ICE_AQ_LINK_PWR_BASET_HIGH 1
1228 #define ICE_AQ_LINK_PWR_QSFP_CLASS_1 0
1229 #define ICE_AQ_LINK_PWR_QSFP_CLASS_2 1
1230 #define ICE_AQ_LINK_PWR_QSFP_CLASS_3 2
1231 #define ICE_AQ_LINK_PWR_QSFP_CLASS_4 3
1233 #define ICE_AQ_LINK_SPEED_10MB BIT(0)
1234 #define ICE_AQ_LINK_SPEED_100MB BIT(1)
1235 #define ICE_AQ_LINK_SPEED_1000MB BIT(2)
1236 #define ICE_AQ_LINK_SPEED_2500MB BIT(3)
1237 #define ICE_AQ_LINK_SPEED_5GB BIT(4)
1238 #define ICE_AQ_LINK_SPEED_10GB BIT(5)
1239 #define ICE_AQ_LINK_SPEED_20GB BIT(6)
1240 #define ICE_AQ_LINK_SPEED_25GB BIT(7)
1241 #define ICE_AQ_LINK_SPEED_40GB BIT(8)
1242 #define ICE_AQ_LINK_SPEED_50GB BIT(9)
1243 #define ICE_AQ_LINK_SPEED_100GB BIT(10)
1244 #define ICE_AQ_LINK_SPEED_UNKNOWN BIT(15)
1245 __le32 reserved3; /* Aligns next field to 8-byte boundary */
1246 __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */
1247 __le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */
1251 /* Set event mask command (direct 0x0613) */
1252 struct ice_aqc_set_event_mask {
1256 #define ICE_AQ_LINK_EVENT_UPDOWN BIT(1)
1257 #define ICE_AQ_LINK_EVENT_MEDIA_NA BIT(2)
1258 #define ICE_AQ_LINK_EVENT_LINK_FAULT BIT(3)
1259 #define ICE_AQ_LINK_EVENT_PHY_TEMP_ALARM BIT(4)
1260 #define ICE_AQ_LINK_EVENT_EXCESSIVE_ERRORS BIT(5)
1261 #define ICE_AQ_LINK_EVENT_SIGNAL_DETECT BIT(6)
1262 #define ICE_AQ_LINK_EVENT_AN_COMPLETED BIT(7)
1263 #define ICE_AQ_LINK_EVENT_MODULE_QUAL_FAIL BIT(8)
1264 #define ICE_AQ_LINK_EVENT_PORT_TX_SUSPENDED BIT(9)
1270 /* Set MAC Loopback command (direct 0x0620) */
1271 struct ice_aqc_set_mac_lb {
1273 #define ICE_AQ_MAC_LB_EN BIT(0)
1274 #define ICE_AQ_MAC_LB_OSC_CLK BIT(1)
1282 /* Set Port Identification LED (direct, 0x06E9) */
1283 struct ice_aqc_set_port_id_led {
1286 #define ICE_AQC_PORT_ID_PORT_NUM_VALID BIT(0)
1288 #define ICE_AQC_PORT_IDENT_LED_BLINK BIT(0)
1289 #define ICE_AQC_PORT_IDENT_LED_ORIG 0
1295 /* NVM Read command (indirect 0x0701)
1296 * NVM Erase commands (direct 0x0702)
1297 * NVM Update commands (indirect 0x0703)
1299 struct ice_aqc_nvm {
1303 #define ICE_AQC_NVM_LAST_CMD BIT(0)
1304 #define ICE_AQC_NVM_PCIR_REQ BIT(0) /* Used by NVM Update reply */
1305 #define ICE_AQC_NVM_PRESERVATION_S 1
1306 #define ICE_AQC_NVM_PRESERVATION_M (3 << ICE_AQC_NVM_PRESERVATION_S)
1307 #define ICE_AQC_NVM_NO_PRESERVATION (0 << ICE_AQC_NVM_PRESERVATION_S)
1308 #define ICE_AQC_NVM_PRESERVE_ALL BIT(1)
1309 #define ICE_AQC_NVM_FACTORY_DEFAULT (2 << ICE_AQC_NVM_PRESERVATION_S)
1310 #define ICE_AQC_NVM_PRESERVE_SELECTED (3 << ICE_AQC_NVM_PRESERVATION_S)
1311 #define ICE_AQC_NVM_FLASH_ONLY BIT(7)
1312 __le16 module_typeid;
1314 #define ICE_AQC_NVM_ERASE_LEN 0xFFFF
1320 /* Used for 0x0704 as well as for 0x0705 commands */
1321 struct ice_aqc_nvm_cfg {
1323 #define ICE_AQC_ANVM_MULTIPLE_ELEMS BIT(0)
1324 #define ICE_AQC_ANVM_IMMEDIATE_FIELD BIT(1)
1325 #define ICE_AQC_ANVM_NEW_CFG BIT(2)
1335 struct ice_aqc_nvm_cfg_data {
1337 __le16 field_options;
1342 /* NVM Checksum Command (direct, 0x0706) */
1343 struct ice_aqc_nvm_checksum {
1345 #define ICE_AQC_NVM_CHECKSUM_VERIFY BIT(0)
1346 #define ICE_AQC_NVM_CHECKSUM_RECALC BIT(1)
1348 __le16 checksum; /* Used only by response */
1349 #define ICE_AQC_NVM_CHECKSUM_CORRECT 0xBABA
1357 /* Get/Set RSS key (indirect 0x0B04/0x0B02) */
1358 struct ice_aqc_get_set_rss_key {
1359 #define ICE_AQC_GSET_RSS_KEY_VSI_VALID BIT(15)
1360 #define ICE_AQC_GSET_RSS_KEY_VSI_ID_S 0
1361 #define ICE_AQC_GSET_RSS_KEY_VSI_ID_M (0x3FF << ICE_AQC_GSET_RSS_KEY_VSI_ID_S)
1369 #define ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE 0x28
1370 #define ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE 0xC
1372 struct ice_aqc_get_set_rss_keys {
1373 u8 standard_rss_key[ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE];
1374 u8 extended_hash_key[ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE];
1378 /* Get/Set RSS LUT (indirect 0x0B05/0x0B03) */
1379 struct ice_aqc_get_set_rss_lut {
1380 #define ICE_AQC_GSET_RSS_LUT_VSI_VALID BIT(15)
1381 #define ICE_AQC_GSET_RSS_LUT_VSI_ID_S 0
1382 #define ICE_AQC_GSET_RSS_LUT_VSI_ID_M (0x1FF << ICE_AQC_GSET_RSS_LUT_VSI_ID_S)
1384 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S 0
1385 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_M \
1386 (0x3 << ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S)
1388 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_VSI 0
1389 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF 1
1390 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL 2
1392 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S 2
1393 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M \
1394 (0x3 << ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S)
1396 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128 128
1397 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128_FLAG 0
1398 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512 512
1399 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512_FLAG 1
1400 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K 2048
1401 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K_FLAG 2
1403 #define ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S 4
1404 #define ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_M \
1405 (0xF << ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S)
1417 /* Add TX LAN Queues (indirect 0x0C30) */
1418 struct ice_aqc_add_txqs {
1427 /* This is the descriptor of each queue entry for the Add TX LAN Queues
1428 * command (0x0C30). Only used within struct ice_aqc_add_tx_qgrp.
1430 struct ice_aqc_add_txqs_perq {
1436 struct ice_aqc_txsched_elem info;
1440 /* The format of the command buffer for Add TX LAN Queues (0x0C30)
1441 * is an array of the following structs. Please note that the length of
1442 * each struct ice_aqc_add_tx_qgrp is variable due
1443 * to the variable number of queues in each group!
1445 struct ice_aqc_add_tx_qgrp {
1449 struct ice_aqc_add_txqs_perq txqs[1];
1453 /* Disable TX LAN Queues (indirect 0x0C31) */
1454 struct ice_aqc_dis_txqs {
1456 #define ICE_AQC_Q_DIS_CMD_S 0
1457 #define ICE_AQC_Q_DIS_CMD_M (0x3 << ICE_AQC_Q_DIS_CMD_S)
1458 #define ICE_AQC_Q_DIS_CMD_NO_FUNC_RESET (0 << ICE_AQC_Q_DIS_CMD_S)
1459 #define ICE_AQC_Q_DIS_CMD_VM_RESET BIT(ICE_AQC_Q_DIS_CMD_S)
1460 #define ICE_AQC_Q_DIS_CMD_VF_RESET (2 << ICE_AQC_Q_DIS_CMD_S)
1461 #define ICE_AQC_Q_DIS_CMD_PF_RESET (3 << ICE_AQC_Q_DIS_CMD_S)
1462 #define ICE_AQC_Q_DIS_CMD_SUBSEQ_CALL BIT(2)
1463 #define ICE_AQC_Q_DIS_CMD_FLUSH_PIPE BIT(3)
1465 __le16 vmvf_and_timeout;
1466 #define ICE_AQC_Q_DIS_VMVF_NUM_S 0
1467 #define ICE_AQC_Q_DIS_VMVF_NUM_M (0x3FF << ICE_AQC_Q_DIS_VMVF_NUM_S)
1468 #define ICE_AQC_Q_DIS_TIMEOUT_S 10
1469 #define ICE_AQC_Q_DIS_TIMEOUT_M (0x3F << ICE_AQC_Q_DIS_TIMEOUT_S)
1470 __le32 blocked_cgds;
1476 /* The buffer for Disable TX LAN Queues (indirect 0x0C31)
1477 * contains the following structures, arrayed one after the
1479 * Note: Since the q_id is 16 bits wide, if the
1480 * number of queues is even, then 2 bytes of alignment MUST be
1481 * added before the start of the next group, to allow correct
1482 * alignment of the parent_teid field.
1484 struct ice_aqc_dis_txq_item {
1488 /* The length of the q_id array varies according to num_qs */
1490 /* This only applies from F8 onward */
1491 #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S 15
1492 #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_LAN_Q \
1493 (0 << ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S)
1494 #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_RDMA_QSET \
1495 (1 << ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S)
1499 struct ice_aqc_dis_txq {
1500 struct ice_aqc_dis_txq_item qgrps[1];
1504 /* TX LAN Queues Cleanup Event (0x0C31) */
1505 struct ice_aqc_txqs_cleanup {
1512 /* Move / Reconfigure TX Queues (indirect 0x0C32) */
1513 struct ice_aqc_move_txqs {
1515 #define ICE_AQC_Q_CMD_TYPE_S 0
1516 #define ICE_AQC_Q_CMD_TYPE_M (0x3 << ICE_AQC_Q_CMD_TYPE_S)
1517 #define ICE_AQC_Q_CMD_TYPE_MOVE 1
1518 #define ICE_AQC_Q_CMD_TYPE_TC_CHANGE 2
1519 #define ICE_AQC_Q_CMD_TYPE_MOVE_AND_TC 3
1520 #define ICE_AQC_Q_CMD_SUBSEQ_CALL BIT(2)
1521 #define ICE_AQC_Q_CMD_FLUSH_PIPE BIT(3)
1525 #define ICE_AQC_Q_CMD_TIMEOUT_S 2
1526 #define ICE_AQC_Q_CMD_TIMEOUT_M (0x3F << ICE_AQC_Q_CMD_TIMEOUT_S)
1527 __le32 blocked_cgds;
1533 /* This is the descriptor of each queue entry for the move TX LAN Queues
1536 struct ice_aqc_move_txqs_elem {
1544 struct ice_aqc_move_txqs_data {
1547 struct ice_aqc_move_txqs_elem txqs[1];
1555 /* Lan Queue Overflow Event (direct, 0x1001) */
1556 struct ice_aqc_event_lan_overflow {
1557 __le32 prtdcb_ruptq;
1564 /* Configure Firmware Logging Command (indirect 0xFF09)
1565 * Logging Information Read Response (indirect 0xFF10)
1566 * Note: The 0xFF10 command has no input parameters.
1568 struct ice_aqc_fw_logging {
1570 #define ICE_AQC_FW_LOG_AQ_EN BIT(0)
1571 #define ICE_AQC_FW_LOG_UART_EN BIT(1)
1573 u8 log_ctrl_valid; /* Not used by 0xFF10 Response */
1574 #define ICE_AQC_FW_LOG_AQ_VALID BIT(0)
1575 #define ICE_AQC_FW_LOG_UART_VALID BIT(1)
1582 enum ice_aqc_fw_logging_mod {
1583 ICE_AQC_FW_LOG_ID_GENERAL = 0,
1584 ICE_AQC_FW_LOG_ID_CTRL,
1585 ICE_AQC_FW_LOG_ID_LINK,
1586 ICE_AQC_FW_LOG_ID_LINK_TOPO,
1587 ICE_AQC_FW_LOG_ID_DNL,
1588 ICE_AQC_FW_LOG_ID_I2C,
1589 ICE_AQC_FW_LOG_ID_SDP,
1590 ICE_AQC_FW_LOG_ID_MDIO,
1591 ICE_AQC_FW_LOG_ID_ADMINQ,
1592 ICE_AQC_FW_LOG_ID_HDMA,
1593 ICE_AQC_FW_LOG_ID_LLDP,
1594 ICE_AQC_FW_LOG_ID_DCBX,
1595 ICE_AQC_FW_LOG_ID_DCB,
1596 ICE_AQC_FW_LOG_ID_NETPROXY,
1597 ICE_AQC_FW_LOG_ID_NVM,
1598 ICE_AQC_FW_LOG_ID_AUTH,
1599 ICE_AQC_FW_LOG_ID_VPD,
1600 ICE_AQC_FW_LOG_ID_IOSF,
1601 ICE_AQC_FW_LOG_ID_PARSER,
1602 ICE_AQC_FW_LOG_ID_SW,
1603 ICE_AQC_FW_LOG_ID_SCHEDULER,
1604 ICE_AQC_FW_LOG_ID_TXQ,
1605 ICE_AQC_FW_LOG_ID_RSVD,
1606 ICE_AQC_FW_LOG_ID_POST,
1607 ICE_AQC_FW_LOG_ID_WATCHDOG,
1608 ICE_AQC_FW_LOG_ID_TASK_DISPATCH,
1609 ICE_AQC_FW_LOG_ID_MNG,
1610 ICE_AQC_FW_LOG_ID_MAX,
1613 /* This is the buffer for both of the logging commands.
1614 * The entry array size depends on the datalen parameter in the descriptor.
1615 * There will be a total of datalen / 2 entries.
1617 struct ice_aqc_fw_logging_data {
1619 #define ICE_AQC_FW_LOG_ID_S 0
1620 #define ICE_AQC_FW_LOG_ID_M (0xFFF << ICE_AQC_FW_LOG_ID_S)
1622 #define ICE_AQC_FW_LOG_CONF_SUCCESS 0 /* Used by response */
1623 #define ICE_AQC_FW_LOG_CONF_BAD_INDX BIT(12) /* Used by response */
1625 #define ICE_AQC_FW_LOG_EN_S 12
1626 #define ICE_AQC_FW_LOG_EN_M (0xF << ICE_AQC_FW_LOG_EN_S)
1627 #define ICE_AQC_FW_LOG_INFO_EN BIT(12) /* Used by command */
1628 #define ICE_AQC_FW_LOG_INIT_EN BIT(13) /* Used by command */
1629 #define ICE_AQC_FW_LOG_FLOW_EN BIT(14) /* Used by command */
1630 #define ICE_AQC_FW_LOG_ERR_EN BIT(15) /* Used by command */
1634 /* Get/Clear FW Log (indirect 0xFF11) */
1635 struct ice_aqc_get_clear_fw_log {
1637 #define ICE_AQC_FW_LOG_CLEAR BIT(0)
1638 #define ICE_AQC_FW_LOG_MORE_DATA_AVAIL BIT(1)
1646 * struct ice_aq_desc - Admin Queue (AQ) descriptor
1647 * @flags: ICE_AQ_FLAG_* flags
1648 * @opcode: AQ command opcode
1649 * @datalen: length in bytes of indirect/external data buffer
1650 * @retval: return value from firmware
1651 * @cookie_h: opaque data high-half
1652 * @cookie_l: opaque data low-half
1653 * @params: command-specific parameters
1655 * Descriptor format for commands the driver posts on the Admin Transmit Queue
1656 * (ATQ). The firmware writes back onto the command descriptor and returns
1657 * the result of the command. Asynchronous events that are not an immediate
1658 * result of the command are written to the Admin Receive Queue (ARQ) using
1659 * the same descriptor format. Descriptors are in little-endian notation with
1662 struct ice_aq_desc {
1671 struct ice_aqc_generic generic;
1672 struct ice_aqc_get_ver get_ver;
1673 struct ice_aqc_q_shutdown q_shutdown;
1674 struct ice_aqc_req_res res_owner;
1675 struct ice_aqc_manage_mac_read mac_read;
1676 struct ice_aqc_manage_mac_write mac_write;
1677 struct ice_aqc_clear_pxe clear_pxe;
1678 struct ice_aqc_list_caps get_cap;
1679 struct ice_aqc_get_phy_caps get_phy;
1680 struct ice_aqc_set_phy_cfg set_phy;
1681 struct ice_aqc_restart_an restart_an;
1682 struct ice_aqc_set_port_id_led set_port_id_led;
1683 struct ice_aqc_get_sw_cfg get_sw_conf;
1684 struct ice_aqc_sw_rules sw_rules;
1685 struct ice_aqc_get_topo get_topo;
1686 struct ice_aqc_sched_elem_cmd sched_elem_cmd;
1687 struct ice_aqc_query_txsched_res query_sched_res;
1688 struct ice_aqc_query_node_to_root query_node_to_root;
1689 struct ice_aqc_cfg_l2_node_cgd cfg_l2_node_cgd;
1690 struct ice_aqc_rl_profile rl_profile;
1692 struct ice_aqc_nvm nvm;
1693 struct ice_aqc_nvm_cfg nvm_cfg;
1694 struct ice_aqc_nvm_checksum nvm_checksum;
1695 struct ice_aqc_get_set_rss_lut get_set_rss_lut;
1696 struct ice_aqc_get_set_rss_key get_set_rss_key;
1697 struct ice_aqc_add_txqs add_txqs;
1698 struct ice_aqc_dis_txqs dis_txqs;
1699 struct ice_aqc_txqs_cleanup txqs_cleanup;
1700 struct ice_aqc_add_get_update_free_vsi vsi_cmd;
1701 struct ice_aqc_add_update_free_vsi_resp add_update_free_vsi_res;
1702 struct ice_aqc_fw_logging fw_logging;
1703 struct ice_aqc_get_clear_fw_log get_clear_fw_log;
1704 struct ice_aqc_set_mac_lb set_mac_lb;
1705 struct ice_aqc_alloc_free_res_cmd sw_res_ctrl;
1706 struct ice_aqc_set_event_mask set_event_mask;
1707 struct ice_aqc_get_link_status get_link_status;
1712 /* FW defined boundary for a large buffer, 4k >= Large buffer > 512 bytes */
1713 #define ICE_AQ_LG_BUF 512
1715 /* Flags sub-structure
1716 * |0 |1 |2 |3 |4 |5 |6 |7 |8 |9 |10 |11 |12 |13 |14 |15 |
1717 * |DD |CMP|ERR|VFE| * * RESERVED * * |LB |RD |VFC|BUF|SI |EI |FE |
1720 /* command flags and offsets */
1721 #define ICE_AQ_FLAG_DD_S 0
1722 #define ICE_AQ_FLAG_CMP_S 1
1723 #define ICE_AQ_FLAG_ERR_S 2
1724 #define ICE_AQ_FLAG_VFE_S 3
1725 #define ICE_AQ_FLAG_LB_S 9
1726 #define ICE_AQ_FLAG_RD_S 10
1727 #define ICE_AQ_FLAG_VFC_S 11
1728 #define ICE_AQ_FLAG_BUF_S 12
1729 #define ICE_AQ_FLAG_SI_S 13
1730 #define ICE_AQ_FLAG_EI_S 14
1731 #define ICE_AQ_FLAG_FE_S 15
1733 #define ICE_AQ_FLAG_DD BIT(ICE_AQ_FLAG_DD_S) /* 0x1 */
1734 #define ICE_AQ_FLAG_CMP BIT(ICE_AQ_FLAG_CMP_S) /* 0x2 */
1735 #define ICE_AQ_FLAG_ERR BIT(ICE_AQ_FLAG_ERR_S) /* 0x4 */
1736 #define ICE_AQ_FLAG_VFE BIT(ICE_AQ_FLAG_VFE_S) /* 0x8 */
1737 #define ICE_AQ_FLAG_LB BIT(ICE_AQ_FLAG_LB_S) /* 0x200 */
1738 #define ICE_AQ_FLAG_RD BIT(ICE_AQ_FLAG_RD_S) /* 0x400 */
1739 #define ICE_AQ_FLAG_VFC BIT(ICE_AQ_FLAG_VFC_S) /* 0x800 */
1740 #define ICE_AQ_FLAG_BUF BIT(ICE_AQ_FLAG_BUF_S) /* 0x1000 */
1741 #define ICE_AQ_FLAG_SI BIT(ICE_AQ_FLAG_SI_S) /* 0x2000 */
1742 #define ICE_AQ_FLAG_EI BIT(ICE_AQ_FLAG_EI_S) /* 0x4000 */
1743 #define ICE_AQ_FLAG_FE BIT(ICE_AQ_FLAG_FE_S) /* 0x8000 */
1747 ICE_AQ_RC_OK = 0, /* Success */
1748 ICE_AQ_RC_EPERM = 1, /* Operation not permitted */
1749 ICE_AQ_RC_ENOENT = 2, /* No such element */
1750 ICE_AQ_RC_ESRCH = 3, /* Bad opcode */
1751 ICE_AQ_RC_EINTR = 4, /* Operation interrupted */
1752 ICE_AQ_RC_EIO = 5, /* I/O error */
1753 ICE_AQ_RC_ENXIO = 6, /* No such resource */
1754 ICE_AQ_RC_E2BIG = 7, /* Arg too long */
1755 ICE_AQ_RC_EAGAIN = 8, /* Try again */
1756 ICE_AQ_RC_ENOMEM = 9, /* Out of memory */
1757 ICE_AQ_RC_EACCES = 10, /* Permission denied */
1758 ICE_AQ_RC_EFAULT = 11, /* Bad address */
1759 ICE_AQ_RC_EBUSY = 12, /* Device or resource busy */
1760 ICE_AQ_RC_EEXIST = 13, /* Object already exists */
1761 ICE_AQ_RC_EINVAL = 14, /* Invalid argument */
1762 ICE_AQ_RC_ENOTTY = 15, /* Not a typewriter */
1763 ICE_AQ_RC_ENOSPC = 16, /* No space left or allocation failure */
1764 ICE_AQ_RC_ENOSYS = 17, /* Function not implemented */
1765 ICE_AQ_RC_ERANGE = 18, /* Parameter out of range */
1766 ICE_AQ_RC_EFLUSHED = 19, /* Cmd flushed due to prev cmd error */
1767 ICE_AQ_RC_BAD_ADDR = 20, /* Descriptor contains a bad pointer */
1768 ICE_AQ_RC_EMODE = 21, /* Op not allowed in current dev mode */
1769 ICE_AQ_RC_EFBIG = 22, /* File too big */
1770 ICE_AQ_RC_ESBCOMP = 23, /* SB-IOSF completion unsuccessful */
1771 ICE_AQ_RC_ENOSEC = 24, /* Missing security manifest */
1772 ICE_AQ_RC_EBADSIG = 25, /* Bad RSA signature */
1773 ICE_AQ_RC_ESVN = 26, /* SVN number prohibits this package */
1774 ICE_AQ_RC_EBADMAN = 27, /* Manifest hash mismatch */
1775 ICE_AQ_RC_EBADBUF = 28, /* Buffer hash mismatches manifest */
1778 /* Admin Queue command opcodes */
1779 enum ice_adminq_opc {
1781 ice_aqc_opc_get_ver = 0x0001,
1782 ice_aqc_opc_driver_ver = 0x0002,
1783 ice_aqc_opc_q_shutdown = 0x0003,
1784 ice_aqc_opc_get_exp_err = 0x0005,
1786 /* resource ownership */
1787 ice_aqc_opc_req_res = 0x0008,
1788 ice_aqc_opc_release_res = 0x0009,
1790 /* device/function capabilities */
1791 ice_aqc_opc_list_func_caps = 0x000A,
1792 ice_aqc_opc_list_dev_caps = 0x000B,
1794 /* manage MAC address */
1795 ice_aqc_opc_manage_mac_read = 0x0107,
1796 ice_aqc_opc_manage_mac_write = 0x0108,
1799 ice_aqc_opc_clear_pxe_mode = 0x0110,
1801 /* internal switch commands */
1802 ice_aqc_opc_get_sw_cfg = 0x0200,
1804 /* Alloc/Free/Get Resources */
1805 ice_aqc_opc_get_res_alloc = 0x0204,
1806 ice_aqc_opc_alloc_res = 0x0208,
1807 ice_aqc_opc_free_res = 0x0209,
1808 ice_aqc_opc_get_allocd_res_desc = 0x020A,
1811 ice_aqc_opc_add_vsi = 0x0210,
1812 ice_aqc_opc_update_vsi = 0x0211,
1813 ice_aqc_opc_get_vsi_params = 0x0212,
1814 ice_aqc_opc_free_vsi = 0x0213,
1818 /* switch rules population commands */
1819 ice_aqc_opc_add_sw_rules = 0x02A0,
1820 ice_aqc_opc_update_sw_rules = 0x02A1,
1821 ice_aqc_opc_remove_sw_rules = 0x02A2,
1822 ice_aqc_opc_get_sw_rules = 0x02A3,
1823 ice_aqc_opc_clear_pf_cfg = 0x02A4,
1826 /* transmit scheduler commands */
1827 ice_aqc_opc_get_dflt_topo = 0x0400,
1828 ice_aqc_opc_add_sched_elems = 0x0401,
1829 ice_aqc_opc_cfg_sched_elems = 0x0403,
1830 ice_aqc_opc_get_sched_elems = 0x0404,
1831 ice_aqc_opc_move_sched_elems = 0x0408,
1832 ice_aqc_opc_suspend_sched_elems = 0x0409,
1833 ice_aqc_opc_resume_sched_elems = 0x040A,
1834 ice_aqc_opc_suspend_sched_traffic = 0x040B,
1835 ice_aqc_opc_resume_sched_traffic = 0x040C,
1836 ice_aqc_opc_delete_sched_elems = 0x040F,
1837 ice_aqc_opc_add_rl_profiles = 0x0410,
1838 ice_aqc_opc_query_rl_profiles = 0x0411,
1839 ice_aqc_opc_query_sched_res = 0x0412,
1840 ice_aqc_opc_query_node_to_root = 0x0413,
1841 ice_aqc_opc_cfg_l2_node_cgd = 0x0414,
1842 ice_aqc_opc_remove_rl_profiles = 0x0415,
1845 ice_aqc_opc_get_phy_caps = 0x0600,
1846 ice_aqc_opc_set_phy_cfg = 0x0601,
1847 ice_aqc_opc_set_mac_cfg = 0x0603,
1848 ice_aqc_opc_restart_an = 0x0605,
1849 ice_aqc_opc_get_link_status = 0x0607,
1850 ice_aqc_opc_set_event_mask = 0x0613,
1851 ice_aqc_opc_set_mac_lb = 0x0620,
1852 ice_aqc_opc_set_port_id_led = 0x06E9,
1853 ice_aqc_opc_get_port_options = 0x06EA,
1854 ice_aqc_opc_set_port_option = 0x06EB,
1855 ice_aqc_opc_set_gpio = 0x06EC,
1856 ice_aqc_opc_get_gpio = 0x06ED,
1859 ice_aqc_opc_nvm_read = 0x0701,
1860 ice_aqc_opc_nvm_erase = 0x0702,
1861 ice_aqc_opc_nvm_update = 0x0703,
1862 ice_aqc_opc_nvm_cfg_read = 0x0704,
1863 ice_aqc_opc_nvm_cfg_write = 0x0705,
1864 ice_aqc_opc_nvm_checksum = 0x0706,
1868 ice_aqc_opc_set_rss_key = 0x0B02,
1869 ice_aqc_opc_set_rss_lut = 0x0B03,
1870 ice_aqc_opc_get_rss_key = 0x0B04,
1871 ice_aqc_opc_get_rss_lut = 0x0B05,
1873 /* TX queue handling commands/events */
1874 ice_aqc_opc_add_txqs = 0x0C30,
1875 ice_aqc_opc_dis_txqs = 0x0C31,
1876 ice_aqc_opc_txqs_cleanup = 0x0C31,
1877 ice_aqc_opc_move_recfg_txqs = 0x0C32,
1882 /* Standalone Commands/Events */
1883 ice_aqc_opc_event_lan_overflow = 0x1001,
1885 /* debug commands */
1886 ice_aqc_opc_fw_logging = 0xFF09,
1887 ice_aqc_opc_fw_logging_info = 0xFF10,
1888 ice_aqc_opc_get_clear_fw_log = 0xFF11
1891 #endif /* _ICE_ADMINQ_CMD_H_ */