1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2001-2020 Intel Corporation
5 #ifndef _ICE_ADMINQ_CMD_H_
6 #define _ICE_ADMINQ_CMD_H_
8 /* This header file defines the Admin Queue commands, error codes and
9 * descriptor format. It is shared between Firmware and Software.
12 #define ICE_MAX_VSI 768
13 #define ICE_AQC_TOPO_MAX_LEVEL_NUM 0x9
14 #define ICE_AQ_SET_MAC_FRAME_SIZE_MAX 9728
16 struct ice_aqc_generic {
23 /* Get version (direct 0x0001) */
24 struct ice_aqc_get_ver {
37 /* Send driver version (indirect 0x0002) */
38 struct ice_aqc_driver_ver {
48 /* Queue Shutdown (direct 0x0003) */
49 struct ice_aqc_q_shutdown {
51 #define ICE_AQC_DRIVER_UNLOADING BIT(0)
55 /* Request resource ownership (direct 0x0008)
56 * Release resource ownership (direct 0x0009)
58 struct ice_aqc_req_res {
60 #define ICE_AQC_RES_ID_NVM 1
61 #define ICE_AQC_RES_ID_SDP 2
62 #define ICE_AQC_RES_ID_CHNG_LOCK 3
63 #define ICE_AQC_RES_ID_GLBL_LOCK 4
65 #define ICE_AQC_RES_ACCESS_READ 1
66 #define ICE_AQC_RES_ACCESS_WRITE 2
68 /* Upon successful completion, FW writes this value and driver is
69 * expected to release resource before timeout. This value is provided
73 #define ICE_AQ_RES_NVM_READ_DFLT_TIMEOUT_MS 3000
74 #define ICE_AQ_RES_NVM_WRITE_DFLT_TIMEOUT_MS 180000
75 #define ICE_AQ_RES_CHNG_LOCK_DFLT_TIMEOUT_MS 1000
76 #define ICE_AQ_RES_GLBL_LOCK_DFLT_TIMEOUT_MS 3000
77 /* For SDP: pin ID of the SDP */
79 /* Status is only used for ICE_AQC_RES_ID_GLBL_LOCK */
81 #define ICE_AQ_RES_GLBL_SUCCESS 0
82 #define ICE_AQ_RES_GLBL_IN_PROG 1
83 #define ICE_AQ_RES_GLBL_DONE 2
87 /* Get function capabilities (indirect 0x000A)
88 * Get device capabilities (indirect 0x000B)
90 struct ice_aqc_list_caps {
99 /* Device/Function buffer entry, repeated per reported capability */
100 struct ice_aqc_list_caps_elem {
102 #define ICE_AQC_CAPS_VALID_FUNCTIONS 0x0005
103 #define ICE_AQC_MAX_VALID_FUNCTIONS 0x8
104 #define ICE_AQC_CAPS_VSI 0x0017
105 #define ICE_AQC_CAPS_DCB 0x0018
106 #define ICE_AQC_CAPS_RSS 0x0040
107 #define ICE_AQC_CAPS_RXQS 0x0041
108 #define ICE_AQC_CAPS_TXQS 0x0042
109 #define ICE_AQC_CAPS_MSIX 0x0043
110 #define ICE_AQC_CAPS_FD 0x0045
111 #define ICE_AQC_CAPS_MAX_MTU 0x0047
115 /* Number of resources described by this capability */
117 /* Only meaningful for some types of resources */
119 /* Only meaningful for some types of resources */
125 /* Manage MAC address, read command - indirect (0x0107)
126 * This struct is also used for the response
128 struct ice_aqc_manage_mac_read {
129 __le16 flags; /* Zeroed by device driver */
130 #define ICE_AQC_MAN_MAC_LAN_ADDR_VALID BIT(4)
131 #define ICE_AQC_MAN_MAC_SAN_ADDR_VALID BIT(5)
132 #define ICE_AQC_MAN_MAC_PORT_ADDR_VALID BIT(6)
133 #define ICE_AQC_MAN_MAC_WOL_ADDR_VALID BIT(7)
134 #define ICE_AQC_MAN_MAC_MC_MAG_EN BIT(8)
135 #define ICE_AQC_MAN_MAC_WOL_PRESERVE_ON_PFR BIT(9)
136 #define ICE_AQC_MAN_MAC_READ_S 4
137 #define ICE_AQC_MAN_MAC_READ_M (0xF << ICE_AQC_MAN_MAC_READ_S)
139 u8 num_addr; /* Used in response */
145 /* Response buffer format for manage MAC read command */
146 struct ice_aqc_manage_mac_read_resp {
149 #define ICE_AQC_MAN_MAC_ADDR_TYPE_LAN 0
150 #define ICE_AQC_MAN_MAC_ADDR_TYPE_WOL 1
151 u8 mac_addr[ETH_ALEN];
154 /* Manage MAC address, write command - direct (0x0108) */
155 struct ice_aqc_manage_mac_write {
158 #define ICE_AQC_MAN_MAC_WR_MC_MAG_EN BIT(0)
159 #define ICE_AQC_MAN_MAC_WR_WOL_LAA_PFR_KEEP BIT(1)
160 #define ICE_AQC_MAN_MAC_WR_S 6
161 #define ICE_AQC_MAN_MAC_WR_M MAKEMASK(3, ICE_AQC_MAN_MAC_WR_S)
162 #define ICE_AQC_MAN_MAC_UPDATE_LAA 0
163 #define ICE_AQC_MAN_MAC_UPDATE_LAA_WOL BIT(ICE_AQC_MAN_MAC_WR_S)
164 /* byte stream in network order */
165 u8 mac_addr[ETH_ALEN];
170 /* Clear PXE Command and response (direct 0x0110) */
171 struct ice_aqc_clear_pxe {
173 #define ICE_AQC_CLEAR_PXE_RX_CNT 0x2
177 /* Configure No-Drop Policy Command (direct 0x0112) */
178 struct ice_aqc_config_no_drop_policy {
180 #define ICE_AQC_FORCE_NO_DROP BIT(0)
184 /* Get switch configuration (0x0200) */
185 struct ice_aqc_get_sw_cfg {
186 /* Reserved for command and copy of request flags for response */
188 /* First desc in case of command and next_elem in case of response
189 * In case of response, if it is not zero, means all the configuration
190 * was not returned and new command shall be sent with this value in
191 * the 'first desc' field
194 /* Reserved for command, only used for response */
201 /* Each entry in the response buffer is of the following type: */
202 struct ice_aqc_get_sw_cfg_resp_elem {
203 /* VSI/Port Number */
205 #define ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_S 0
206 #define ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_M \
207 (0x3FF << ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_S)
208 #define ICE_AQC_GET_SW_CONF_RESP_TYPE_S 14
209 #define ICE_AQC_GET_SW_CONF_RESP_TYPE_M (0x3 << ICE_AQC_GET_SW_CONF_RESP_TYPE_S)
210 #define ICE_AQC_GET_SW_CONF_RESP_PHYS_PORT 0
211 #define ICE_AQC_GET_SW_CONF_RESP_VIRT_PORT 1
212 #define ICE_AQC_GET_SW_CONF_RESP_VSI 2
214 /* SWID VSI/Port belongs to */
217 /* Bit 14..0 : PF/VF number VSI belongs to
218 * Bit 15 : VF indication bit
221 #define ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_S 0
222 #define ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_M \
223 (0x7FFF << ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_S)
224 #define ICE_AQC_GET_SW_CONF_RESP_IS_VF BIT(15)
227 /* These resource type defines are used for all switch resource
228 * commands where a resource type is required, such as:
229 * Get Resource Allocation command (indirect 0x0204)
230 * Allocate Resources command (indirect 0x0208)
231 * Free Resources command (indirect 0x0209)
232 * Get Allocated Resource Descriptors Command (indirect 0x020A)
234 #define ICE_AQC_RES_TYPE_VEB_COUNTER 0x00
235 #define ICE_AQC_RES_TYPE_VLAN_COUNTER 0x01
236 #define ICE_AQC_RES_TYPE_MIRROR_RULE 0x02
237 #define ICE_AQC_RES_TYPE_VSI_LIST_REP 0x03
238 #define ICE_AQC_RES_TYPE_VSI_LIST_PRUNE 0x04
239 #define ICE_AQC_RES_TYPE_RECIPE 0x05
240 #define ICE_AQC_RES_TYPE_PROFILE 0x06
241 #define ICE_AQC_RES_TYPE_SWID 0x07
242 #define ICE_AQC_RES_TYPE_VSI 0x08
243 #define ICE_AQC_RES_TYPE_FLU 0x09
244 #define ICE_AQC_RES_TYPE_WIDE_TABLE_1 0x0A
245 #define ICE_AQC_RES_TYPE_WIDE_TABLE_2 0x0B
246 #define ICE_AQC_RES_TYPE_WIDE_TABLE_4 0x0C
247 #define ICE_AQC_RES_TYPE_GLOBAL_RSS_HASH 0x20
248 #define ICE_AQC_RES_TYPE_FDIR_COUNTER_BLOCK 0x21
249 #define ICE_AQC_RES_TYPE_FDIR_GUARANTEED_ENTRIES 0x22
250 #define ICE_AQC_RES_TYPE_FDIR_SHARED_ENTRIES 0x23
251 #define ICE_AQC_RES_TYPE_FLEX_DESC_PROG 0x30
252 #define ICE_AQC_RES_TYPE_SWITCH_PROF_BLDR_PROFID 0x48
253 #define ICE_AQC_RES_TYPE_SWITCH_PROF_BLDR_TCAM 0x49
254 #define ICE_AQC_RES_TYPE_ACL_PROF_BLDR_PROFID 0x50
255 #define ICE_AQC_RES_TYPE_ACL_PROF_BLDR_TCAM 0x51
256 #define ICE_AQC_RES_TYPE_FD_PROF_BLDR_PROFID 0x58
257 #define ICE_AQC_RES_TYPE_FD_PROF_BLDR_TCAM 0x59
258 #define ICE_AQC_RES_TYPE_HASH_PROF_BLDR_PROFID 0x60
259 #define ICE_AQC_RES_TYPE_HASH_PROF_BLDR_TCAM 0x61
260 /* Resource types 0x62-67 are reserved for Hash profile builder */
261 #define ICE_AQC_RES_TYPE_QHASH_PROF_BLDR_PROFID 0x68
262 #define ICE_AQC_RES_TYPE_QHASH_PROF_BLDR_TCAM 0x69
264 #define ICE_AQC_RES_TYPE_FLAG_SHARED BIT(7)
265 #define ICE_AQC_RES_TYPE_FLAG_SCAN_BOTTOM BIT(12)
266 #define ICE_AQC_RES_TYPE_FLAG_IGNORE_INDEX BIT(13)
268 #define ICE_AQC_RES_TYPE_FLAG_DEDICATED 0x00
270 #define ICE_AQC_RES_TYPE_S 0
271 #define ICE_AQC_RES_TYPE_M (0x07F << ICE_AQC_RES_TYPE_S)
273 /* Get Resource Allocation command (indirect 0x0204) */
274 struct ice_aqc_get_res_alloc {
275 __le16 resp_elem_num; /* Used in response, reserved in command */
281 /* Get Resource Allocation Response Buffer per response */
282 struct ice_aqc_get_res_resp_elem {
283 __le16 res_type; /* Types defined above cmd 0x0204 */
284 __le16 total_capacity; /* Resources available to all PF's */
285 __le16 total_function; /* Resources allocated for a PF */
286 __le16 total_shared; /* Resources allocated as shared */
287 __le16 total_free; /* Resources un-allocated/not reserved by any PF */
290 /* Allocate Resources command (indirect 0x0208)
291 * Free Resources command (indirect 0x0209)
293 struct ice_aqc_alloc_free_res_cmd {
294 __le16 num_entries; /* Number of Resource entries */
300 /* Resource descriptor */
301 struct ice_aqc_res_elem {
308 /* Buffer for Allocate/Free Resources commands */
309 struct ice_aqc_alloc_free_res_elem {
310 __le16 res_type; /* Types defined above cmd 0x0204 */
311 #define ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_S 8
312 #define ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_M \
313 (0xF << ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_S)
315 struct ice_aqc_res_elem elem[STRUCT_HACK_VAR_LEN];
318 /* Get Allocated Resource Descriptors Command (indirect 0x020A) */
319 struct ice_aqc_get_allocd_res_desc {
322 __le16 res; /* Types defined above cmd 0x0204 */
337 /* Add VSI (indirect 0x0210)
338 * Update VSI (indirect 0x0211)
339 * Get VSI (indirect 0x0212)
340 * Free VSI (indirect 0x0213)
342 struct ice_aqc_add_get_update_free_vsi {
344 #define ICE_AQ_VSI_NUM_S 0
345 #define ICE_AQ_VSI_NUM_M (0x03FF << ICE_AQ_VSI_NUM_S)
346 #define ICE_AQ_VSI_IS_VALID BIT(15)
348 #define ICE_AQ_VSI_KEEP_ALLOC 0x1
352 #define ICE_AQ_VSI_TYPE_S 0
353 #define ICE_AQ_VSI_TYPE_M (0x3 << ICE_AQ_VSI_TYPE_S)
354 #define ICE_AQ_VSI_TYPE_VF 0x0
355 #define ICE_AQ_VSI_TYPE_VMDQ2 0x1
356 #define ICE_AQ_VSI_TYPE_PF 0x2
357 #define ICE_AQ_VSI_TYPE_EMP_MNG 0x3
362 /* Response descriptor for:
363 * Add VSI (indirect 0x0210)
364 * Update VSI (indirect 0x0211)
365 * Free VSI (indirect 0x0213)
367 struct ice_aqc_add_update_free_vsi_resp {
376 struct ice_aqc_get_vsi_resp {
379 /* The vsi_flags field uses the ICE_AQ_VSI_TYPE_* defines for values.
380 * These are found above in struct ice_aqc_add_get_update_free_vsi.
389 struct ice_aqc_vsi_props {
390 __le16 valid_sections;
391 #define ICE_AQ_VSI_PROP_SW_VALID BIT(0)
392 #define ICE_AQ_VSI_PROP_SECURITY_VALID BIT(1)
393 #define ICE_AQ_VSI_PROP_VLAN_VALID BIT(2)
394 #define ICE_AQ_VSI_PROP_OUTER_TAG_VALID BIT(3)
395 #define ICE_AQ_VSI_PROP_INGRESS_UP_VALID BIT(4)
396 #define ICE_AQ_VSI_PROP_EGRESS_UP_VALID BIT(5)
397 #define ICE_AQ_VSI_PROP_RXQ_MAP_VALID BIT(6)
398 #define ICE_AQ_VSI_PROP_Q_OPT_VALID BIT(7)
399 #define ICE_AQ_VSI_PROP_OUTER_UP_VALID BIT(8)
400 #define ICE_AQ_VSI_PROP_ACL_VALID BIT(10)
401 #define ICE_AQ_VSI_PROP_FLOW_DIR_VALID BIT(11)
402 #define ICE_AQ_VSI_PROP_PASID_VALID BIT(12)
406 #define ICE_AQ_VSI_SW_FLAG_ALLOW_LB BIT(5)
407 #define ICE_AQ_VSI_SW_FLAG_LOCAL_LB BIT(6)
408 #define ICE_AQ_VSI_SW_FLAG_SRC_PRUNE BIT(7)
410 #define ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_S 0
411 #define ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_M \
412 (0xF << ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_S)
413 #define ICE_AQ_VSI_SW_FLAG_RX_VLAN_PRUNE_ENA BIT(0)
414 #define ICE_AQ_VSI_SW_FLAG_LAN_ENA BIT(4)
416 #define ICE_AQ_VSI_SW_VEB_STAT_ID_S 0
417 #define ICE_AQ_VSI_SW_VEB_STAT_ID_M (0x1F << ICE_AQ_VSI_SW_VEB_STAT_ID_S)
418 #define ICE_AQ_VSI_SW_VEB_STAT_ID_VALID BIT(5)
419 /* security section */
421 #define ICE_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD BIT(0)
422 #define ICE_AQ_VSI_SEC_FLAG_ENA_MAC_ANTI_SPOOF BIT(2)
423 #define ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S 4
424 #define ICE_AQ_VSI_SEC_TX_PRUNE_ENA_M (0xF << ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S)
425 #define ICE_AQ_VSI_SEC_TX_VLAN_PRUNE_ENA BIT(0)
428 __le16 pvid; /* VLANS include priority bits */
429 u8 pvlan_reserved[2];
431 #define ICE_AQ_VSI_VLAN_MODE_S 0
432 #define ICE_AQ_VSI_VLAN_MODE_M (0x3 << ICE_AQ_VSI_VLAN_MODE_S)
433 #define ICE_AQ_VSI_VLAN_MODE_UNTAGGED 0x1
434 #define ICE_AQ_VSI_VLAN_MODE_TAGGED 0x2
435 #define ICE_AQ_VSI_VLAN_MODE_ALL 0x3
436 #define ICE_AQ_VSI_PVLAN_INSERT_PVID BIT(2)
437 #define ICE_AQ_VSI_VLAN_EMOD_S 3
438 #define ICE_AQ_VSI_VLAN_EMOD_M (0x3 << ICE_AQ_VSI_VLAN_EMOD_S)
439 #define ICE_AQ_VSI_VLAN_EMOD_STR_BOTH (0x0 << ICE_AQ_VSI_VLAN_EMOD_S)
440 #define ICE_AQ_VSI_VLAN_EMOD_STR_UP (0x1 << ICE_AQ_VSI_VLAN_EMOD_S)
441 #define ICE_AQ_VSI_VLAN_EMOD_STR (0x2 << ICE_AQ_VSI_VLAN_EMOD_S)
442 #define ICE_AQ_VSI_VLAN_EMOD_NOTHING (0x3 << ICE_AQ_VSI_VLAN_EMOD_S)
443 u8 pvlan_reserved2[3];
444 /* ingress egress up sections */
445 __le32 ingress_table; /* bitmap, 3 bits per up */
446 #define ICE_AQ_VSI_UP_TABLE_UP0_S 0
447 #define ICE_AQ_VSI_UP_TABLE_UP0_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP0_S)
448 #define ICE_AQ_VSI_UP_TABLE_UP1_S 3
449 #define ICE_AQ_VSI_UP_TABLE_UP1_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP1_S)
450 #define ICE_AQ_VSI_UP_TABLE_UP2_S 6
451 #define ICE_AQ_VSI_UP_TABLE_UP2_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP2_S)
452 #define ICE_AQ_VSI_UP_TABLE_UP3_S 9
453 #define ICE_AQ_VSI_UP_TABLE_UP3_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP3_S)
454 #define ICE_AQ_VSI_UP_TABLE_UP4_S 12
455 #define ICE_AQ_VSI_UP_TABLE_UP4_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP4_S)
456 #define ICE_AQ_VSI_UP_TABLE_UP5_S 15
457 #define ICE_AQ_VSI_UP_TABLE_UP5_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP5_S)
458 #define ICE_AQ_VSI_UP_TABLE_UP6_S 18
459 #define ICE_AQ_VSI_UP_TABLE_UP6_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP6_S)
460 #define ICE_AQ_VSI_UP_TABLE_UP7_S 21
461 #define ICE_AQ_VSI_UP_TABLE_UP7_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP7_S)
462 __le32 egress_table; /* same defines as for ingress table */
463 /* outer tags section */
466 #define ICE_AQ_VSI_OUTER_TAG_MODE_S 0
467 #define ICE_AQ_VSI_OUTER_TAG_MODE_M (0x3 << ICE_AQ_VSI_OUTER_TAG_MODE_S)
468 #define ICE_AQ_VSI_OUTER_TAG_NOTHING 0x0
469 #define ICE_AQ_VSI_OUTER_TAG_REMOVE 0x1
470 #define ICE_AQ_VSI_OUTER_TAG_COPY 0x2
471 #define ICE_AQ_VSI_OUTER_TAG_TYPE_S 2
472 #define ICE_AQ_VSI_OUTER_TAG_TYPE_M (0x3 << ICE_AQ_VSI_OUTER_TAG_TYPE_S)
473 #define ICE_AQ_VSI_OUTER_TAG_NONE 0x0
474 #define ICE_AQ_VSI_OUTER_TAG_STAG 0x1
475 #define ICE_AQ_VSI_OUTER_TAG_VLAN_8100 0x2
476 #define ICE_AQ_VSI_OUTER_TAG_VLAN_9100 0x3
477 #define ICE_AQ_VSI_OUTER_TAG_INSERT BIT(4)
478 #define ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST BIT(6)
479 u8 outer_tag_reserved;
480 /* queue mapping section */
481 __le16 mapping_flags;
482 #define ICE_AQ_VSI_Q_MAP_CONTIG 0x0
483 #define ICE_AQ_VSI_Q_MAP_NONCONTIG BIT(0)
484 __le16 q_mapping[16];
485 #define ICE_AQ_VSI_Q_S 0
486 #define ICE_AQ_VSI_Q_M (0x7FF << ICE_AQ_VSI_Q_S)
487 __le16 tc_mapping[8];
488 #define ICE_AQ_VSI_TC_Q_OFFSET_S 0
489 #define ICE_AQ_VSI_TC_Q_OFFSET_M (0x7FF << ICE_AQ_VSI_TC_Q_OFFSET_S)
490 #define ICE_AQ_VSI_TC_Q_NUM_S 11
491 #define ICE_AQ_VSI_TC_Q_NUM_M (0xF << ICE_AQ_VSI_TC_Q_NUM_S)
492 /* queueing option section */
494 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_S 0
495 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_M (0x3 << ICE_AQ_VSI_Q_OPT_RSS_LUT_S)
496 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_VSI 0x0
497 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_PF 0x2
498 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_GBL 0x3
499 #define ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_S 2
500 #define ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_M (0xF << ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_S)
501 #define ICE_AQ_VSI_Q_OPT_RSS_HASH_S 6
502 #define ICE_AQ_VSI_Q_OPT_RSS_HASH_M (0x3 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S)
503 #define ICE_AQ_VSI_Q_OPT_RSS_TPLZ (0x0 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S)
504 #define ICE_AQ_VSI_Q_OPT_RSS_SYM_TPLZ (0x1 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S)
505 #define ICE_AQ_VSI_Q_OPT_RSS_XOR (0x2 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S)
506 #define ICE_AQ_VSI_Q_OPT_RSS_JHASH (0x3 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S)
508 #define ICE_AQ_VSI_Q_OPT_TC_OVR_S 0
509 #define ICE_AQ_VSI_Q_OPT_TC_OVR_M (0x1F << ICE_AQ_VSI_Q_OPT_TC_OVR_S)
510 #define ICE_AQ_VSI_Q_OPT_PROF_TC_OVR BIT(7)
512 #define ICE_AQ_VSI_Q_OPT_PE_FLTR_EN BIT(0)
513 u8 q_opt_reserved[3];
514 /* outer up section */
515 __le32 outer_up_table; /* same structure and defines as ingress tbl */
518 #define ICE_AQ_VSI_ACL_DEF_RX_PROF_S 0
519 #define ICE_AQ_VSI_ACL_DEF_RX_PROF_M (0xF << ICE_AQ_VSI_ACL_DEF_RX_PROF_S)
520 #define ICE_AQ_VSI_ACL_DEF_RX_TABLE_S 4
521 #define ICE_AQ_VSI_ACL_DEF_RX_TABLE_M (0xF << ICE_AQ_VSI_ACL_DEF_RX_TABLE_S)
522 #define ICE_AQ_VSI_ACL_DEF_TX_PROF_S 8
523 #define ICE_AQ_VSI_ACL_DEF_TX_PROF_M (0xF << ICE_AQ_VSI_ACL_DEF_TX_PROF_S)
524 #define ICE_AQ_VSI_ACL_DEF_TX_TABLE_S 12
525 #define ICE_AQ_VSI_ACL_DEF_TX_TABLE_M (0xF << ICE_AQ_VSI_ACL_DEF_TX_TABLE_S)
526 /* flow director section */
528 #define ICE_AQ_VSI_FD_ENABLE BIT(0)
529 #define ICE_AQ_VSI_FD_TX_AUTO_ENABLE BIT(1)
530 #define ICE_AQ_VSI_FD_PROG_ENABLE BIT(3)
531 __le16 max_fd_fltr_dedicated;
532 __le16 max_fd_fltr_shared;
534 #define ICE_AQ_VSI_FD_DEF_Q_S 0
535 #define ICE_AQ_VSI_FD_DEF_Q_M (0x7FF << ICE_AQ_VSI_FD_DEF_Q_S)
536 #define ICE_AQ_VSI_FD_DEF_GRP_S 12
537 #define ICE_AQ_VSI_FD_DEF_GRP_M (0x7 << ICE_AQ_VSI_FD_DEF_GRP_S)
538 __le16 fd_report_opt;
539 #define ICE_AQ_VSI_FD_REPORT_Q_S 0
540 #define ICE_AQ_VSI_FD_REPORT_Q_M (0x7FF << ICE_AQ_VSI_FD_REPORT_Q_S)
541 #define ICE_AQ_VSI_FD_DEF_PRIORITY_S 12
542 #define ICE_AQ_VSI_FD_DEF_PRIORITY_M (0x7 << ICE_AQ_VSI_FD_DEF_PRIORITY_S)
543 #define ICE_AQ_VSI_FD_DEF_DROP BIT(15)
546 #define ICE_AQ_VSI_PASID_ID_S 0
547 #define ICE_AQ_VSI_PASID_ID_M (0xFFFFF << ICE_AQ_VSI_PASID_ID_S)
548 #define ICE_AQ_VSI_PASID_ID_VALID BIT(31)
552 /* Add/update mirror rule - direct (0x0260) */
553 #define ICE_AQC_RULE_ID_VALID_S 7
554 #define ICE_AQC_RULE_ID_VALID_M (0x1 << ICE_AQC_RULE_ID_VALID_S)
555 #define ICE_AQC_RULE_ID_S 0
556 #define ICE_AQC_RULE_ID_M (0x3F << ICE_AQC_RULE_ID_S)
558 /* Following defines to be used while processing caller specified mirror list
561 /* Action: Byte.bit (1.7)
562 * 0 = Remove VSI from mirror rule
563 * 1 = Add VSI to mirror rule
565 #define ICE_AQC_RULE_ACT_S 15
566 #define ICE_AQC_RULE_ACT_M (0x1 << ICE_AQC_RULE_ACT_S)
567 /* Action: 1.2:0.0 = Mirrored VSI */
568 #define ICE_AQC_RULE_MIRRORED_VSI_S 0
569 #define ICE_AQC_RULE_MIRRORED_VSI_M (0x7FF << ICE_AQC_RULE_MIRRORED_VSI_S)
571 /* This is to be used by add/update mirror rule Admin Queue command.
572 * In case of add mirror rule - if rule ID is specified as
573 * INVAL_MIRROR_RULE_ID, new rule ID is allocated from shared pool.
574 * If specified rule_id is valid, then it is used. If specified rule_id
575 * is in use then new mirroring rule is added.
577 #define ICE_INVAL_MIRROR_RULE_ID 0xFFFF
579 struct ice_aqc_add_update_mir_rule {
583 #define ICE_AQC_RULE_TYPE_S 0
584 #define ICE_AQC_RULE_TYPE_M (0x7 << ICE_AQC_RULE_TYPE_S)
585 /* VPORT ingress/egress */
586 #define ICE_AQC_RULE_TYPE_VPORT_INGRESS 0x1
587 #define ICE_AQC_RULE_TYPE_VPORT_EGRESS 0x2
588 /* Physical port ingress mirroring.
589 * All traffic received by this port
591 #define ICE_AQC_RULE_TYPE_PPORT_INGRESS 0x6
592 /* Physical port egress mirroring. All traffic sent by this port */
593 #define ICE_AQC_RULE_TYPE_PPORT_EGRESS 0x7
595 /* Number of mirrored entries.
596 * The values are in the command buffer
600 /* Destination VSI */
606 /* Delete mirror rule - direct(0x0261) */
607 struct ice_aqc_delete_mir_rule {
611 /* Byte.bit: 20.0 = Keep allocation. If set VSI stays part of
612 * the PF allocated resources, otherwise it is returned to the
615 #define ICE_AQC_FLAG_KEEP_ALLOCD_S 0
616 #define ICE_AQC_FLAG_KEEP_ALLOCD_M (0x1 << ICE_AQC_FLAG_KEEP_ALLOCD_S)
622 /* Set/Get storm config - (direct 0x0280, 0x0281) */
623 /* This structure holds get storm configuration response and same structure
624 * is used to perform set_storm_cfg
626 struct ice_aqc_storm_cfg {
627 __le32 bcast_thresh_size;
628 __le32 mcast_thresh_size;
629 /* Bit 18:0 - Traffic upper threshold size
630 * Bit 31:19 - Reserved
632 #define ICE_AQ_THRESHOLD_S 0
633 #define ICE_AQ_THRESHOLD_M (0x7FFFF << ICE_AQ_THRESHOLD_S)
635 __le32 storm_ctrl_ctrl;
636 /* Bit 0: MDIPW - Drop Multicast packets in previous window
637 * Bit 1: MDICW - Drop multicast packets in current window
638 * Bit 2: BDIPW - Drop broadcast packets in previous window
639 * Bit 3: BDICW - Drop broadcast packets in current window
641 #define ICE_AQ_STORM_CTRL_MDIPW_DROP_MULTICAST BIT(0)
642 #define ICE_AQ_STORM_CTRL_MDICW_DROP_MULTICAST BIT(1)
643 #define ICE_AQ_STORM_CTRL_BDIPW_DROP_MULTICAST BIT(2)
644 #define ICE_AQ_STORM_CTRL_BDICW_DROP_MULTICAST BIT(3)
645 /* Bit 7:5 : Reserved */
646 /* Bit 27:8 : Interval - BSC/MSC Time-interval specification: The
647 * interval size for applying ingress broadcast or multicast storm
650 #define ICE_AQ_STORM_BSC_MSC_TIME_INTERVAL_S 8
651 #define ICE_AQ_STORM_BSC_MSC_TIME_INTERVAL_M \
652 (0xFFFFF << ICE_AQ_STORM_BSC_MSC_TIME_INTERVAL_S)
656 #define ICE_MAX_NUM_RECIPES 64
658 /* Add/Get Recipe (indirect 0x0290/0x0292) */
659 struct ice_aqc_add_get_recipe {
660 __le16 num_sub_recipes; /* Input in Add cmd, Output in Get cmd */
661 __le16 return_index; /* Input, used for Get cmd only */
667 struct ice_aqc_recipe_content {
669 #define ICE_AQ_RECIPE_ID_S 0
670 #define ICE_AQ_RECIPE_ID_M (0x3F << ICE_AQ_RECIPE_ID_S)
671 #define ICE_AQ_RECIPE_ID_IS_ROOT BIT(7)
672 #define ICE_AQ_SW_ID_LKUP_IDX 0
674 #define ICE_AQ_RECIPE_LKUP_DATA_S 0
675 #define ICE_AQ_RECIPE_LKUP_DATA_M (0x3F << ICE_AQ_RECIPE_LKUP_DATA_S)
676 #define ICE_AQ_RECIPE_LKUP_IGNORE BIT(7)
677 #define ICE_AQ_SW_ID_LKUP_MASK 0x00FF
680 #define ICE_AQ_RECIPE_RESULT_DATA_S 0
681 #define ICE_AQ_RECIPE_RESULT_DATA_M (0x3F << ICE_AQ_RECIPE_RESULT_DATA_S)
682 #define ICE_AQ_RECIPE_RESULT_EN BIT(7)
684 u8 act_ctrl_join_priority;
685 u8 act_ctrl_fwd_priority;
686 #define ICE_AQ_RECIPE_FWD_PRIORITY_S 0
687 #define ICE_AQ_RECIPE_FWD_PRIORITY_M (0xF << ICE_AQ_RECIPE_FWD_PRIORITY_S)
689 #define ICE_AQ_RECIPE_ACT_NEED_PASS_L2 BIT(0)
690 #define ICE_AQ_RECIPE_ACT_ALLOW_PASS_L2 BIT(1)
691 #define ICE_AQ_RECIPE_ACT_INV_ACT BIT(2)
692 #define ICE_AQ_RECIPE_ACT_PRUNE_INDX_S 4
693 #define ICE_AQ_RECIPE_ACT_PRUNE_INDX_M (0x3 << ICE_AQ_RECIPE_ACT_PRUNE_INDX_S)
696 #define ICE_AQ_RECIPE_DFLT_ACT_S 0
697 #define ICE_AQ_RECIPE_DFLT_ACT_M (0x7FFFF << ICE_AQ_RECIPE_DFLT_ACT_S)
698 #define ICE_AQ_RECIPE_DFLT_ACT_VALID BIT(31)
701 struct ice_aqc_recipe_data_elem {
704 #define ICE_AQ_RECIPE_WAS_UPDATED BIT(0)
708 struct ice_aqc_recipe_content content;
712 /* Set/Get Recipes to Profile Association (direct 0x0291/0x0293) */
713 struct ice_aqc_recipe_to_profile {
716 ice_declare_bitmap(recipe_assoc, ICE_MAX_NUM_RECIPES);
719 /* Add/Update/Remove/Get switch rules (indirect 0x02A0, 0x02A1, 0x02A2, 0x02A3)
721 struct ice_aqc_sw_rules {
722 /* ops: add switch rules, referring the number of rules.
723 * ops: update switch rules, referring the number of filters
724 * ops: remove switch rules, referring the entry index.
725 * ops: get switch rules, referring to the number of filters.
727 __le16 num_rules_fltr_entry_index;
733 /* Add/Update/Get/Remove lookup Rx/Tx command/response entry
734 * This structures describes the lookup rules and associated actions. "index"
735 * is returned as part of a response to a successful Add command, and can be
736 * used to identify the rule for Update/Get/Remove commands.
738 struct ice_sw_rule_lkup_rx_tx {
740 #define ICE_SW_RECIPE_LOGICAL_PORT_FWD 10
741 /* Source port for LOOKUP_RX and source VSI in case of LOOKUP_TX */
745 /* Bit 0:1 - Action type */
746 #define ICE_SINGLE_ACT_TYPE_S 0x00
747 #define ICE_SINGLE_ACT_TYPE_M (0x3 << ICE_SINGLE_ACT_TYPE_S)
749 /* Bit 2 - Loop back enable
752 #define ICE_SINGLE_ACT_LB_ENABLE BIT(2)
753 #define ICE_SINGLE_ACT_LAN_ENABLE BIT(3)
755 /* Action type = 0 - Forward to VSI or VSI list */
756 #define ICE_SINGLE_ACT_VSI_FORWARDING 0x0
758 #define ICE_SINGLE_ACT_VSI_ID_S 4
759 #define ICE_SINGLE_ACT_VSI_ID_M (0x3FF << ICE_SINGLE_ACT_VSI_ID_S)
760 #define ICE_SINGLE_ACT_VSI_LIST_ID_S 4
761 #define ICE_SINGLE_ACT_VSI_LIST_ID_M (0x3FF << ICE_SINGLE_ACT_VSI_LIST_ID_S)
762 /* This bit needs to be set if action is forward to VSI list */
763 #define ICE_SINGLE_ACT_VSI_LIST BIT(14)
764 #define ICE_SINGLE_ACT_VALID_BIT BIT(17)
765 #define ICE_SINGLE_ACT_DROP BIT(18)
767 /* Action type = 1 - Forward to Queue of Queue group */
768 #define ICE_SINGLE_ACT_TO_Q 0x1
769 #define ICE_SINGLE_ACT_Q_INDEX_S 4
770 #define ICE_SINGLE_ACT_Q_INDEX_M (0x7FF << ICE_SINGLE_ACT_Q_INDEX_S)
771 #define ICE_SINGLE_ACT_Q_REGION_S 15
772 #define ICE_SINGLE_ACT_Q_REGION_M (0x7 << ICE_SINGLE_ACT_Q_REGION_S)
773 #define ICE_SINGLE_ACT_Q_PRIORITY BIT(18)
775 /* Action type = 2 - Prune */
776 #define ICE_SINGLE_ACT_PRUNE 0x2
777 #define ICE_SINGLE_ACT_EGRESS BIT(15)
778 #define ICE_SINGLE_ACT_INGRESS BIT(16)
779 #define ICE_SINGLE_ACT_PRUNET BIT(17)
780 /* Bit 18 should be set to 0 for this action */
782 /* Action type = 2 - Pointer */
783 #define ICE_SINGLE_ACT_PTR 0x2
784 #define ICE_SINGLE_ACT_PTR_VAL_S 4
785 #define ICE_SINGLE_ACT_PTR_VAL_M (0x1FFF << ICE_SINGLE_ACT_PTR_VAL_S)
786 /* Bit 18 should be set to 1 */
787 #define ICE_SINGLE_ACT_PTR_BIT BIT(18)
789 /* Action type = 3 - Other actions. Last two bits
790 * are other action identifier
792 #define ICE_SINGLE_ACT_OTHER_ACTS 0x3
793 #define ICE_SINGLE_OTHER_ACT_IDENTIFIER_S 17
794 #define ICE_SINGLE_OTHER_ACT_IDENTIFIER_M \
795 (0x3 << ICE_SINGLE_OTHER_ACT_IDENTIFIER_S)
797 /* Bit 17:18 - Defines other actions */
798 /* Other action = 0 - Mirror VSI */
799 #define ICE_SINGLE_OTHER_ACT_MIRROR 0
800 #define ICE_SINGLE_ACT_MIRROR_VSI_ID_S 4
801 #define ICE_SINGLE_ACT_MIRROR_VSI_ID_M \
802 (0x3FF << ICE_SINGLE_ACT_MIRROR_VSI_ID_S)
804 /* Other action = 3 - Set Stat count */
805 #define ICE_SINGLE_OTHER_ACT_STAT_COUNT 3
806 #define ICE_SINGLE_ACT_STAT_COUNT_INDEX_S 4
807 #define ICE_SINGLE_ACT_STAT_COUNT_INDEX_M \
808 (0x7F << ICE_SINGLE_ACT_STAT_COUNT_INDEX_S)
810 __le16 index; /* The index of the rule in the lookup table */
811 /* Length and values of the header to be matched per recipe or
815 u8 hdr[STRUCT_HACK_VAR_LEN];
818 /* Add/Update/Remove large action command/response entry
819 * "index" is returned as part of a response to a successful Add command, and
820 * can be used to identify the action for Update/Get/Remove commands.
822 struct ice_sw_rule_lg_act {
823 __le16 index; /* Index in large action table */
825 /* Max number of large actions */
826 #define ICE_MAX_LG_ACT 4
827 /* Bit 0:1 - Action type */
828 #define ICE_LG_ACT_TYPE_S 0
829 #define ICE_LG_ACT_TYPE_M (0x7 << ICE_LG_ACT_TYPE_S)
831 /* Action type = 0 - Forward to VSI or VSI list */
832 #define ICE_LG_ACT_VSI_FORWARDING 0
833 #define ICE_LG_ACT_VSI_ID_S 3
834 #define ICE_LG_ACT_VSI_ID_M (0x3FF << ICE_LG_ACT_VSI_ID_S)
835 #define ICE_LG_ACT_VSI_LIST_ID_S 3
836 #define ICE_LG_ACT_VSI_LIST_ID_M (0x3FF << ICE_LG_ACT_VSI_LIST_ID_S)
837 /* This bit needs to be set if action is forward to VSI list */
838 #define ICE_LG_ACT_VSI_LIST BIT(13)
840 #define ICE_LG_ACT_VALID_BIT BIT(16)
842 /* Action type = 1 - Forward to Queue of Queue group */
843 #define ICE_LG_ACT_TO_Q 0x1
844 #define ICE_LG_ACT_Q_INDEX_S 3
845 #define ICE_LG_ACT_Q_INDEX_M (0x7FF << ICE_LG_ACT_Q_INDEX_S)
846 #define ICE_LG_ACT_Q_REGION_S 14
847 #define ICE_LG_ACT_Q_REGION_M (0x7 << ICE_LG_ACT_Q_REGION_S)
848 #define ICE_LG_ACT_Q_PRIORITY_SET BIT(17)
850 /* Action type = 2 - Prune */
851 #define ICE_LG_ACT_PRUNE 0x2
852 #define ICE_LG_ACT_EGRESS BIT(14)
853 #define ICE_LG_ACT_INGRESS BIT(15)
854 #define ICE_LG_ACT_PRUNET BIT(16)
856 /* Action type = 3 - Mirror VSI */
857 #define ICE_LG_OTHER_ACT_MIRROR 0x3
858 #define ICE_LG_ACT_MIRROR_VSI_ID_S 3
859 #define ICE_LG_ACT_MIRROR_VSI_ID_M (0x3FF << ICE_LG_ACT_MIRROR_VSI_ID_S)
861 /* Action type = 5 - Generic Value */
862 #define ICE_LG_ACT_GENERIC 0x5
863 #define ICE_LG_ACT_GENERIC_VALUE_S 3
864 #define ICE_LG_ACT_GENERIC_VALUE_M (0xFFFF << ICE_LG_ACT_GENERIC_VALUE_S)
865 #define ICE_LG_ACT_GENERIC_OFFSET_S 19
866 #define ICE_LG_ACT_GENERIC_OFFSET_M (0x7 << ICE_LG_ACT_GENERIC_OFFSET_S)
867 #define ICE_LG_ACT_GENERIC_PRIORITY_S 22
868 #define ICE_LG_ACT_GENERIC_PRIORITY_M (0x7 << ICE_LG_ACT_GENERIC_PRIORITY_S)
869 #define ICE_LG_ACT_GENERIC_OFF_RX_DESC_PROF_IDX 7
871 /* Action = 7 - Set Stat count */
872 #define ICE_LG_ACT_STAT_COUNT 0x7
873 #define ICE_LG_ACT_STAT_COUNT_S 3
874 #define ICE_LG_ACT_STAT_COUNT_M (0x7F << ICE_LG_ACT_STAT_COUNT_S)
875 __le32 act[STRUCT_HACK_VAR_LEN]; /* array of size for actions */
878 /* Add/Update/Remove VSI list command/response entry
879 * "index" is returned as part of a response to a successful Add command, and
880 * can be used to identify the VSI list for Update/Get/Remove commands.
882 struct ice_sw_rule_vsi_list {
883 __le16 index; /* Index of VSI/Prune list */
885 __le16 vsi[STRUCT_HACK_VAR_LEN]; /* Array of number_vsi VSI numbers */
889 /* Query VSI list command/response entry */
890 struct ice_sw_rule_vsi_list_query {
892 ice_declare_bitmap(vsi_list, ICE_MAX_VSI);
897 /* Add switch rule response:
898 * Content of return buffer is same as the input buffer. The status field and
899 * LUT index are updated as part of the response
901 struct ice_aqc_sw_rules_elem {
902 __le16 type; /* Switch rule type, one of T_... */
903 #define ICE_AQC_SW_RULES_T_LKUP_RX 0x0
904 #define ICE_AQC_SW_RULES_T_LKUP_TX 0x1
905 #define ICE_AQC_SW_RULES_T_LG_ACT 0x2
906 #define ICE_AQC_SW_RULES_T_VSI_LIST_SET 0x3
907 #define ICE_AQC_SW_RULES_T_VSI_LIST_CLEAR 0x4
908 #define ICE_AQC_SW_RULES_T_PRUNE_LIST_SET 0x5
909 #define ICE_AQC_SW_RULES_T_PRUNE_LIST_CLEAR 0x6
912 struct ice_sw_rule_lkup_rx_tx lkup_tx_rx;
913 struct ice_sw_rule_lg_act lg_act;
914 struct ice_sw_rule_vsi_list vsi_list;
915 struct ice_sw_rule_vsi_list_query vsi_list_query;
921 /* PFC Ignore (direct 0x0301)
922 * The command and response use the same descriptor structure
924 struct ice_aqc_pfc_ignore {
926 u8 cmd_flags; /* unused in response */
927 #define ICE_AQC_PFC_IGNORE_SET BIT(7)
928 #define ICE_AQC_PFC_IGNORE_CLEAR 0
932 /* Set PFC Mode (direct 0x0303)
933 * Query PFC Mode (direct 0x0302)
935 struct ice_aqc_set_query_pfc_mode {
937 /* For Set Command response, reserved in all other cases */
938 #define ICE_AQC_PFC_NOT_CONFIGURED 0
939 /* For Query Command response, reserved in all other cases */
940 #define ICE_AQC_DCB_DIS 0
941 #define ICE_AQC_PFC_VLAN_BASED_PFC 1
942 #define ICE_AQC_PFC_DSCP_BASED_PFC 2
946 /* Set DCB Parameters (direct 0x0306) */
947 struct ice_aqc_set_dcb_params {
948 u8 cmd_flags; /* unused in response */
949 #define ICE_AQC_LINK_UP_DCB_CFG BIT(0)
950 #define ICE_AQC_PERSIST_DCB_CFG BIT(1)
951 u8 valid_flags; /* unused in response */
952 #define ICE_AQC_LINK_UP_DCB_CFG_VALID BIT(0)
953 #define ICE_AQC_PERSIST_DCB_CFG_VALID BIT(1)
957 /* Get Default Topology (indirect 0x0400) */
958 struct ice_aqc_get_topo {
967 /* Update TSE (indirect 0x0403)
968 * Get TSE (indirect 0x0404)
969 * Add TSE (indirect 0x0401)
970 * Delete TSE (indirect 0x040F)
971 * Move TSE (indirect 0x0408)
972 * Suspend Nodes (indirect 0x0409)
973 * Resume Nodes (indirect 0x040A)
975 struct ice_aqc_sched_elem_cmd {
976 __le16 num_elem_req; /* Used by commands */
977 __le16 num_elem_resp; /* Used by responses */
983 struct ice_aqc_txsched_move_grp_info_hdr {
984 __le32 src_parent_teid;
985 __le32 dest_parent_teid;
990 struct ice_aqc_move_elem {
991 struct ice_aqc_txsched_move_grp_info_hdr hdr;
992 __le32 teid[STRUCT_HACK_VAR_LEN];
995 struct ice_aqc_elem_info_bw {
996 __le16 bw_profile_idx;
1000 struct ice_aqc_txsched_elem {
1001 u8 elem_type; /* Special field, reserved for some aq calls */
1002 #define ICE_AQC_ELEM_TYPE_UNDEFINED 0x0
1003 #define ICE_AQC_ELEM_TYPE_ROOT_PORT 0x1
1004 #define ICE_AQC_ELEM_TYPE_TC 0x2
1005 #define ICE_AQC_ELEM_TYPE_SE_GENERIC 0x3
1006 #define ICE_AQC_ELEM_TYPE_ENTRY_POINT 0x4
1007 #define ICE_AQC_ELEM_TYPE_LEAF 0x5
1008 #define ICE_AQC_ELEM_TYPE_SE_PADDED 0x6
1010 #define ICE_AQC_ELEM_VALID_GENERIC BIT(0)
1011 #define ICE_AQC_ELEM_VALID_CIR BIT(1)
1012 #define ICE_AQC_ELEM_VALID_EIR BIT(2)
1013 #define ICE_AQC_ELEM_VALID_SHARED BIT(3)
1015 #define ICE_AQC_ELEM_GENERIC_MODE_M 0x1
1016 #define ICE_AQC_ELEM_GENERIC_PRIO_S 0x1
1017 #define ICE_AQC_ELEM_GENERIC_PRIO_M (0x7 << ICE_AQC_ELEM_GENERIC_PRIO_S)
1018 #define ICE_AQC_ELEM_GENERIC_SP_S 0x4
1019 #define ICE_AQC_ELEM_GENERIC_SP_M (0x1 << ICE_AQC_ELEM_GENERIC_SP_S)
1020 #define ICE_AQC_ELEM_GENERIC_ADJUST_VAL_S 0x5
1021 #define ICE_AQC_ELEM_GENERIC_ADJUST_VAL_M \
1022 (0x3 << ICE_AQC_ELEM_GENERIC_ADJUST_VAL_S)
1023 u8 flags; /* Special field, reserved for some aq calls */
1024 #define ICE_AQC_ELEM_FLAG_SUSPEND_M 0x1
1025 struct ice_aqc_elem_info_bw cir_bw;
1026 struct ice_aqc_elem_info_bw eir_bw;
1031 struct ice_aqc_txsched_elem_data {
1034 struct ice_aqc_txsched_elem data;
1037 struct ice_aqc_txsched_topo_grp_info_hdr {
1043 struct ice_aqc_add_elem {
1044 struct ice_aqc_txsched_topo_grp_info_hdr hdr;
1045 struct ice_aqc_txsched_elem_data generic[STRUCT_HACK_VAR_LEN];
1048 struct ice_aqc_get_topo_elem {
1049 struct ice_aqc_txsched_topo_grp_info_hdr hdr;
1050 struct ice_aqc_txsched_elem_data
1051 generic[ICE_AQC_TOPO_MAX_LEVEL_NUM];
1054 struct ice_aqc_delete_elem {
1055 struct ice_aqc_txsched_topo_grp_info_hdr hdr;
1056 __le32 teid[STRUCT_HACK_VAR_LEN];
1059 /* Query Port ETS (indirect 0x040E)
1061 * This indirect command is used to query port TC node configuration.
1063 struct ice_aqc_query_port_ets {
1070 struct ice_aqc_port_ets_elem {
1073 /* 3 bits for UP per TC 0-7, 4th byte reserved */
1076 __le32 port_eir_prof_id;
1077 __le32 port_cir_prof_id;
1078 /* 3 bits per Node priority to TC 0-7, 4th byte reserved */
1079 __le32 tc_node_prio;
1080 #define ICE_TC_NODE_PRIO_S 0x4
1082 __le32 tc_node_teid[8]; /* Used for response, reserved in command */
1085 /* Rate limiting profile for
1086 * Add RL profile (indirect 0x0410)
1087 * Query RL profile (indirect 0x0411)
1088 * Remove RL profile (indirect 0x0415)
1089 * These indirect commands acts on single or multiple
1090 * RL profiles with specified data.
1092 struct ice_aqc_rl_profile {
1093 __le16 num_profiles;
1094 __le16 num_processed; /* Only for response. Reserved in Command. */
1100 struct ice_aqc_rl_profile_elem {
1103 #define ICE_AQC_RL_PROFILE_TYPE_S 0x0
1104 #define ICE_AQC_RL_PROFILE_TYPE_M (0x3 << ICE_AQC_RL_PROFILE_TYPE_S)
1105 #define ICE_AQC_RL_PROFILE_TYPE_CIR 0
1106 #define ICE_AQC_RL_PROFILE_TYPE_EIR 1
1107 #define ICE_AQC_RL_PROFILE_TYPE_SRL 2
1108 /* The following flag is used for Query RL Profile Data */
1109 #define ICE_AQC_RL_PROFILE_INVAL_S 0x7
1110 #define ICE_AQC_RL_PROFILE_INVAL_M (0x1 << ICE_AQC_RL_PROFILE_INVAL_S)
1113 __le16 max_burst_size;
1115 __le16 wake_up_calc;
1119 /* Configure L2 Node CGD (indirect 0x0414)
1120 * This indirect command allows configuring a congestion domain for given L2
1121 * node TEIDs in the scheduler topology.
1123 struct ice_aqc_cfg_l2_node_cgd {
1124 __le16 num_l2_nodes;
1130 struct ice_aqc_cfg_l2_node_cgd_elem {
1136 /* Query Scheduler Resource Allocation (indirect 0x0412)
1137 * This indirect command retrieves the scheduler resources allocated by
1138 * EMP Firmware to the given PF.
1140 struct ice_aqc_query_txsched_res {
1146 struct ice_aqc_generic_sched_props {
1148 __le16 logical_levels;
1149 u8 flattening_bitmap;
1157 struct ice_aqc_layer_props {
1160 __le16 max_device_nodes;
1161 __le16 max_pf_nodes;
1163 __le16 max_sibl_grp_sz;
1164 __le16 max_cir_rl_profiles;
1165 __le16 max_eir_rl_profiles;
1166 __le16 max_srl_profiles;
1170 struct ice_aqc_query_txsched_res_resp {
1171 struct ice_aqc_generic_sched_props sched_props;
1172 struct ice_aqc_layer_props layer_props[ICE_AQC_TOPO_MAX_LEVEL_NUM];
1175 /* Query Node to Root Topology (indirect 0x0413)
1176 * This command uses ice_aqc_get_elem as its data buffer.
1178 struct ice_aqc_query_node_to_root {
1180 __le32 num_nodes; /* Response only */
1185 /* Get PHY capabilities (indirect 0x0600) */
1186 struct ice_aqc_get_phy_caps {
1190 /* 18.0 - Report qualified modules */
1191 #define ICE_AQC_GET_PHY_RQM BIT(0)
1192 /* 18.1 - 18.2 : Report mode
1193 * 00b - Report NVM capabilities
1194 * 01b - Report topology capabilities
1195 * 10b - Report SW configured
1197 #define ICE_AQC_REPORT_MODE_S 1
1198 #define ICE_AQC_REPORT_MODE_M (3 << ICE_AQC_REPORT_MODE_S)
1199 #define ICE_AQC_REPORT_NVM_CAP 0
1200 #define ICE_AQC_REPORT_TOPO_CAP BIT(1)
1201 #define ICE_AQC_REPORT_SW_CFG BIT(2)
1207 /* This is #define of PHY type (Extended):
1208 * The first set of defines is for phy_type_low.
1210 #define ICE_PHY_TYPE_LOW_100BASE_TX BIT_ULL(0)
1211 #define ICE_PHY_TYPE_LOW_100M_SGMII BIT_ULL(1)
1212 #define ICE_PHY_TYPE_LOW_1000BASE_T BIT_ULL(2)
1213 #define ICE_PHY_TYPE_LOW_1000BASE_SX BIT_ULL(3)
1214 #define ICE_PHY_TYPE_LOW_1000BASE_LX BIT_ULL(4)
1215 #define ICE_PHY_TYPE_LOW_1000BASE_KX BIT_ULL(5)
1216 #define ICE_PHY_TYPE_LOW_1G_SGMII BIT_ULL(6)
1217 #define ICE_PHY_TYPE_LOW_2500BASE_T BIT_ULL(7)
1218 #define ICE_PHY_TYPE_LOW_2500BASE_X BIT_ULL(8)
1219 #define ICE_PHY_TYPE_LOW_2500BASE_KX BIT_ULL(9)
1220 #define ICE_PHY_TYPE_LOW_5GBASE_T BIT_ULL(10)
1221 #define ICE_PHY_TYPE_LOW_5GBASE_KR BIT_ULL(11)
1222 #define ICE_PHY_TYPE_LOW_10GBASE_T BIT_ULL(12)
1223 #define ICE_PHY_TYPE_LOW_10G_SFI_DA BIT_ULL(13)
1224 #define ICE_PHY_TYPE_LOW_10GBASE_SR BIT_ULL(14)
1225 #define ICE_PHY_TYPE_LOW_10GBASE_LR BIT_ULL(15)
1226 #define ICE_PHY_TYPE_LOW_10GBASE_KR_CR1 BIT_ULL(16)
1227 #define ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC BIT_ULL(17)
1228 #define ICE_PHY_TYPE_LOW_10G_SFI_C2C BIT_ULL(18)
1229 #define ICE_PHY_TYPE_LOW_25GBASE_T BIT_ULL(19)
1230 #define ICE_PHY_TYPE_LOW_25GBASE_CR BIT_ULL(20)
1231 #define ICE_PHY_TYPE_LOW_25GBASE_CR_S BIT_ULL(21)
1232 #define ICE_PHY_TYPE_LOW_25GBASE_CR1 BIT_ULL(22)
1233 #define ICE_PHY_TYPE_LOW_25GBASE_SR BIT_ULL(23)
1234 #define ICE_PHY_TYPE_LOW_25GBASE_LR BIT_ULL(24)
1235 #define ICE_PHY_TYPE_LOW_25GBASE_KR BIT_ULL(25)
1236 #define ICE_PHY_TYPE_LOW_25GBASE_KR_S BIT_ULL(26)
1237 #define ICE_PHY_TYPE_LOW_25GBASE_KR1 BIT_ULL(27)
1238 #define ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC BIT_ULL(28)
1239 #define ICE_PHY_TYPE_LOW_25G_AUI_C2C BIT_ULL(29)
1240 #define ICE_PHY_TYPE_LOW_40GBASE_CR4 BIT_ULL(30)
1241 #define ICE_PHY_TYPE_LOW_40GBASE_SR4 BIT_ULL(31)
1242 #define ICE_PHY_TYPE_LOW_40GBASE_LR4 BIT_ULL(32)
1243 #define ICE_PHY_TYPE_LOW_40GBASE_KR4 BIT_ULL(33)
1244 #define ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC BIT_ULL(34)
1245 #define ICE_PHY_TYPE_LOW_40G_XLAUI BIT_ULL(35)
1246 #define ICE_PHY_TYPE_LOW_50GBASE_CR2 BIT_ULL(36)
1247 #define ICE_PHY_TYPE_LOW_50GBASE_SR2 BIT_ULL(37)
1248 #define ICE_PHY_TYPE_LOW_50GBASE_LR2 BIT_ULL(38)
1249 #define ICE_PHY_TYPE_LOW_50GBASE_KR2 BIT_ULL(39)
1250 #define ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC BIT_ULL(40)
1251 #define ICE_PHY_TYPE_LOW_50G_LAUI2 BIT_ULL(41)
1252 #define ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC BIT_ULL(42)
1253 #define ICE_PHY_TYPE_LOW_50G_AUI2 BIT_ULL(43)
1254 #define ICE_PHY_TYPE_LOW_50GBASE_CP BIT_ULL(44)
1255 #define ICE_PHY_TYPE_LOW_50GBASE_SR BIT_ULL(45)
1256 #define ICE_PHY_TYPE_LOW_50GBASE_FR BIT_ULL(46)
1257 #define ICE_PHY_TYPE_LOW_50GBASE_LR BIT_ULL(47)
1258 #define ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4 BIT_ULL(48)
1259 #define ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC BIT_ULL(49)
1260 #define ICE_PHY_TYPE_LOW_50G_AUI1 BIT_ULL(50)
1261 #define ICE_PHY_TYPE_LOW_100GBASE_CR4 BIT_ULL(51)
1262 #define ICE_PHY_TYPE_LOW_100GBASE_SR4 BIT_ULL(52)
1263 #define ICE_PHY_TYPE_LOW_100GBASE_LR4 BIT_ULL(53)
1264 #define ICE_PHY_TYPE_LOW_100GBASE_KR4 BIT_ULL(54)
1265 #define ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC BIT_ULL(55)
1266 #define ICE_PHY_TYPE_LOW_100G_CAUI4 BIT_ULL(56)
1267 #define ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC BIT_ULL(57)
1268 #define ICE_PHY_TYPE_LOW_100G_AUI4 BIT_ULL(58)
1269 #define ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4 BIT_ULL(59)
1270 #define ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4 BIT_ULL(60)
1271 #define ICE_PHY_TYPE_LOW_100GBASE_CP2 BIT_ULL(61)
1272 #define ICE_PHY_TYPE_LOW_100GBASE_SR2 BIT_ULL(62)
1273 #define ICE_PHY_TYPE_LOW_100GBASE_DR BIT_ULL(63)
1274 #define ICE_PHY_TYPE_LOW_MAX_INDEX 63
1275 /* The second set of defines is for phy_type_high. */
1276 #define ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4 BIT_ULL(0)
1277 #define ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC BIT_ULL(1)
1278 #define ICE_PHY_TYPE_HIGH_100G_CAUI2 BIT_ULL(2)
1279 #define ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC BIT_ULL(3)
1280 #define ICE_PHY_TYPE_HIGH_100G_AUI2 BIT_ULL(4)
1281 #define ICE_PHY_TYPE_HIGH_MAX_INDEX 5
1283 struct ice_aqc_get_phy_caps_data {
1284 __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */
1285 __le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */
1287 #define ICE_AQC_PHY_EN_TX_LINK_PAUSE BIT(0)
1288 #define ICE_AQC_PHY_EN_RX_LINK_PAUSE BIT(1)
1289 #define ICE_AQC_PHY_LOW_POWER_MODE BIT(2)
1290 #define ICE_AQC_PHY_EN_LINK BIT(3)
1291 #define ICE_AQC_PHY_AN_MODE BIT(4)
1292 #define ICE_AQC_PHY_EN_MOD_QUAL BIT(5)
1293 #define ICE_AQC_PHY_EN_LESM BIT(6)
1294 #define ICE_AQC_PHY_EN_AUTO_FEC BIT(7)
1295 #define ICE_AQC_PHY_CAPS_MASK MAKEMASK(0xff, 0)
1296 u8 low_power_ctrl_an;
1297 #define ICE_AQC_PHY_EN_D3COLD_LOW_POWER_AUTONEG BIT(0)
1298 #define ICE_AQC_PHY_AN_EN_CLAUSE28 BIT(1)
1299 #define ICE_AQC_PHY_AN_EN_CLAUSE73 BIT(2)
1300 #define ICE_AQC_PHY_AN_EN_CLAUSE37 BIT(3)
1302 #define ICE_AQC_PHY_EEE_EN_100BASE_TX BIT(0)
1303 #define ICE_AQC_PHY_EEE_EN_1000BASE_T BIT(1)
1304 #define ICE_AQC_PHY_EEE_EN_10GBASE_T BIT(2)
1305 #define ICE_AQC_PHY_EEE_EN_1000BASE_KX BIT(3)
1306 #define ICE_AQC_PHY_EEE_EN_10GBASE_KR BIT(4)
1307 #define ICE_AQC_PHY_EEE_EN_25GBASE_KR BIT(5)
1308 #define ICE_AQC_PHY_EEE_EN_40GBASE_KR4 BIT(6)
1309 #define ICE_AQC_PHY_EEE_EN_50GBASE_KR2 BIT(7)
1310 #define ICE_AQC_PHY_EEE_EN_50GBASE_KR_PAM4 BIT(8)
1311 #define ICE_AQC_PHY_EEE_EN_100GBASE_KR4 BIT(9)
1312 #define ICE_AQC_PHY_EEE_EN_100GBASE_KR2_PAM4 BIT(10)
1314 u8 phy_id_oui[4]; /* PHY/Module ID connected on the port */
1316 u8 link_fec_options;
1317 #define ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN BIT(0)
1318 #define ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ BIT(1)
1319 #define ICE_AQC_PHY_FEC_25G_RS_528_REQ BIT(2)
1320 #define ICE_AQC_PHY_FEC_25G_KR_REQ BIT(3)
1321 #define ICE_AQC_PHY_FEC_25G_RS_544_REQ BIT(4)
1322 #define ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN BIT(6)
1323 #define ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN BIT(7)
1324 #define ICE_AQC_PHY_FEC_MASK MAKEMASK(0xdf, 0)
1325 u8 module_compliance_enforcement;
1326 #define ICE_AQC_MOD_ENFORCE_STRICT_MODE BIT(0)
1327 u8 extended_compliance_code;
1328 #define ICE_MODULE_TYPE_TOTAL_BYTE 3
1329 u8 module_type[ICE_MODULE_TYPE_TOTAL_BYTE];
1330 #define ICE_AQC_MOD_TYPE_BYTE0_SFP_PLUS 0xA0
1331 #define ICE_AQC_MOD_TYPE_BYTE0_QSFP_PLUS 0x80
1332 #define ICE_AQC_MOD_TYPE_IDENT 1
1333 #define ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_PASSIVE BIT(0)
1334 #define ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_ACTIVE BIT(1)
1335 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_SR BIT(4)
1336 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_LR BIT(5)
1337 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_LRM BIT(6)
1338 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_ER BIT(7)
1339 #define ICE_AQC_MOD_TYPE_BYTE2_SFP_PLUS 0xA0
1340 #define ICE_AQC_MOD_TYPE_BYTE2_QSFP_PLUS 0x86
1341 u8 qualified_module_count;
1342 u8 rsvd2[7]; /* Bytes 47:41 reserved */
1343 #define ICE_AQC_QUAL_MOD_COUNT_MAX 16
1350 } qual_modules[ICE_AQC_QUAL_MOD_COUNT_MAX];
1353 /* Set PHY capabilities (direct 0x0601)
1354 * NOTE: This command must be followed by setup link and restart auto-neg
1356 struct ice_aqc_set_phy_cfg {
1363 /* Set PHY config command data structure */
1364 struct ice_aqc_set_phy_cfg_data {
1365 __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */
1366 __le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */
1368 #define ICE_AQ_PHY_ENA_VALID_MASK MAKEMASK(0xef, 0)
1369 #define ICE_AQ_PHY_ENA_TX_PAUSE_ABILITY BIT(0)
1370 #define ICE_AQ_PHY_ENA_RX_PAUSE_ABILITY BIT(1)
1371 #define ICE_AQ_PHY_ENA_LOW_POWER BIT(2)
1372 #define ICE_AQ_PHY_ENA_LINK BIT(3)
1373 #define ICE_AQ_PHY_ENA_AUTO_LINK_UPDT BIT(5)
1374 #define ICE_AQ_PHY_ENA_LESM BIT(6)
1375 #define ICE_AQ_PHY_ENA_AUTO_FEC BIT(7)
1376 u8 low_power_ctrl_an;
1377 __le16 eee_cap; /* Value from ice_aqc_get_phy_caps */
1379 u8 link_fec_opt; /* Use defines from ice_aqc_get_phy_caps */
1380 u8 module_compliance_enforcement;
1383 /* Set MAC Config command data structure (direct 0x0603) */
1384 struct ice_aqc_set_mac_cfg {
1385 __le16 max_frame_size;
1387 #define ICE_AQ_SET_MAC_PACE_S 3
1388 #define ICE_AQ_SET_MAC_PACE_M (0xF << ICE_AQ_SET_MAC_PACE_S)
1389 #define ICE_AQ_SET_MAC_PACE_TYPE_M BIT(7)
1390 #define ICE_AQ_SET_MAC_PACE_TYPE_RATE 0
1391 #define ICE_AQ_SET_MAC_PACE_TYPE_FIXED ICE_AQ_SET_MAC_PACE_TYPE_M
1393 __le16 tx_tmr_value;
1394 __le16 fc_refresh_threshold;
1396 #define ICE_AQ_SET_MAC_AUTO_DROP_MASK BIT(0)
1397 #define ICE_AQ_SET_MAC_AUTO_DROP_NONE 0
1398 #define ICE_AQ_SET_MAC_AUTO_DROP_BLOCKING_PKTS BIT(0)
1402 /* Restart AN command data structure (direct 0x0605)
1403 * Also used for response, with only the lport_num field present.
1405 struct ice_aqc_restart_an {
1409 #define ICE_AQC_RESTART_AN_LINK_RESTART BIT(1)
1410 #define ICE_AQC_RESTART_AN_LINK_ENABLE BIT(2)
1414 /* Get link status (indirect 0x0607), also used for Link Status Event */
1415 struct ice_aqc_get_link_status {
1419 #define ICE_AQ_LSE_M 0x3
1420 #define ICE_AQ_LSE_NOP 0x0
1421 #define ICE_AQ_LSE_DIS 0x2
1422 #define ICE_AQ_LSE_ENA 0x3
1423 /* only response uses this flag */
1424 #define ICE_AQ_LSE_IS_ENABLED 0x1
1430 /* Get link status response data structure, also used for Link Status Event */
1431 struct ice_aqc_get_link_status_data {
1432 u8 topo_media_conflict;
1433 #define ICE_AQ_LINK_TOPO_CONFLICT BIT(0)
1434 #define ICE_AQ_LINK_MEDIA_CONFLICT BIT(1)
1435 #define ICE_AQ_LINK_TOPO_CORRUPT BIT(2)
1436 #define ICE_AQ_LINK_TOPO_UNREACH_PRT BIT(4)
1437 #define ICE_AQ_LINK_TOPO_UNDRUTIL_PRT BIT(5)
1438 #define ICE_AQ_LINK_TOPO_UNDRUTIL_MEDIA BIT(6)
1439 #define ICE_AQ_LINK_TOPO_UNSUPP_MEDIA BIT(7)
1441 #define ICE_AQ_LINK_CFG_ERR BIT(0)
1443 #define ICE_AQ_LINK_UP BIT(0) /* Link Status */
1444 #define ICE_AQ_LINK_FAULT BIT(1)
1445 #define ICE_AQ_LINK_FAULT_TX BIT(2)
1446 #define ICE_AQ_LINK_FAULT_RX BIT(3)
1447 #define ICE_AQ_LINK_FAULT_REMOTE BIT(4)
1448 #define ICE_AQ_LINK_UP_PORT BIT(5) /* External Port Link Status */
1449 #define ICE_AQ_MEDIA_AVAILABLE BIT(6)
1450 #define ICE_AQ_SIGNAL_DETECT BIT(7)
1452 #define ICE_AQ_AN_COMPLETED BIT(0)
1453 #define ICE_AQ_LP_AN_ABILITY BIT(1)
1454 #define ICE_AQ_PD_FAULT BIT(2) /* Parallel Detection Fault */
1455 #define ICE_AQ_FEC_EN BIT(3)
1456 #define ICE_AQ_PHY_LOW_POWER BIT(4) /* Low Power State */
1457 #define ICE_AQ_LINK_PAUSE_TX BIT(5)
1458 #define ICE_AQ_LINK_PAUSE_RX BIT(6)
1459 #define ICE_AQ_QUALIFIED_MODULE BIT(7)
1461 #define ICE_AQ_LINK_PHY_TEMP_ALARM BIT(0)
1462 #define ICE_AQ_LINK_EXCESSIVE_ERRORS BIT(1) /* Excessive Link Errors */
1463 /* Port Tx Suspended */
1464 #define ICE_AQ_LINK_TX_S 2
1465 #define ICE_AQ_LINK_TX_M (0x03 << ICE_AQ_LINK_TX_S)
1466 #define ICE_AQ_LINK_TX_ACTIVE 0
1467 #define ICE_AQ_LINK_TX_DRAINED 1
1468 #define ICE_AQ_LINK_TX_FLUSHED 3
1470 #define ICE_AQ_LINK_LB_PHY_LCL BIT(0)
1471 #define ICE_AQ_LINK_LB_PHY_RMT BIT(1)
1472 #define ICE_AQ_LINK_LB_MAC_LCL BIT(2)
1473 #define ICE_AQ_LINK_LB_PHY_IDX_S 3
1474 #define ICE_AQ_LINK_LB_PHY_IDX_M (0x7 << ICE_AQ_LB_PHY_IDX_S)
1475 __le16 max_frame_size;
1477 #define ICE_AQ_LINK_25G_KR_FEC_EN BIT(0)
1478 #define ICE_AQ_LINK_25G_RS_528_FEC_EN BIT(1)
1479 #define ICE_AQ_LINK_25G_RS_544_FEC_EN BIT(2)
1480 #define ICE_AQ_FEC_MASK MAKEMASK(0x7, 0)
1482 #define ICE_AQ_CFG_PACING_S 3
1483 #define ICE_AQ_CFG_PACING_M (0xF << ICE_AQ_CFG_PACING_S)
1484 #define ICE_AQ_CFG_PACING_TYPE_M BIT(7)
1485 #define ICE_AQ_CFG_PACING_TYPE_AVG 0
1486 #define ICE_AQ_CFG_PACING_TYPE_FIXED ICE_AQ_CFG_PACING_TYPE_M
1487 /* External Device Power Ability */
1489 #define ICE_AQ_PWR_CLASS_M 0x3
1490 #define ICE_AQ_LINK_PWR_BASET_LOW_HIGH 0
1491 #define ICE_AQ_LINK_PWR_BASET_HIGH 1
1492 #define ICE_AQ_LINK_PWR_QSFP_CLASS_1 0
1493 #define ICE_AQ_LINK_PWR_QSFP_CLASS_2 1
1494 #define ICE_AQ_LINK_PWR_QSFP_CLASS_3 2
1495 #define ICE_AQ_LINK_PWR_QSFP_CLASS_4 3
1497 #define ICE_AQ_LINK_SPEED_M 0x7FF
1498 #define ICE_AQ_LINK_SPEED_10MB BIT(0)
1499 #define ICE_AQ_LINK_SPEED_100MB BIT(1)
1500 #define ICE_AQ_LINK_SPEED_1000MB BIT(2)
1501 #define ICE_AQ_LINK_SPEED_2500MB BIT(3)
1502 #define ICE_AQ_LINK_SPEED_5GB BIT(4)
1503 #define ICE_AQ_LINK_SPEED_10GB BIT(5)
1504 #define ICE_AQ_LINK_SPEED_20GB BIT(6)
1505 #define ICE_AQ_LINK_SPEED_25GB BIT(7)
1506 #define ICE_AQ_LINK_SPEED_40GB BIT(8)
1507 #define ICE_AQ_LINK_SPEED_50GB BIT(9)
1508 #define ICE_AQ_LINK_SPEED_100GB BIT(10)
1509 #define ICE_AQ_LINK_SPEED_UNKNOWN BIT(15)
1510 __le32 reserved3; /* Aligns next field to 8-byte boundary */
1511 __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */
1512 __le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */
1515 /* Set event mask command (direct 0x0613) */
1516 struct ice_aqc_set_event_mask {
1520 #define ICE_AQ_LINK_EVENT_UPDOWN BIT(1)
1521 #define ICE_AQ_LINK_EVENT_MEDIA_NA BIT(2)
1522 #define ICE_AQ_LINK_EVENT_LINK_FAULT BIT(3)
1523 #define ICE_AQ_LINK_EVENT_PHY_TEMP_ALARM BIT(4)
1524 #define ICE_AQ_LINK_EVENT_EXCESSIVE_ERRORS BIT(5)
1525 #define ICE_AQ_LINK_EVENT_SIGNAL_DETECT BIT(6)
1526 #define ICE_AQ_LINK_EVENT_AN_COMPLETED BIT(7)
1527 #define ICE_AQ_LINK_EVENT_MODULE_QUAL_FAIL BIT(8)
1528 #define ICE_AQ_LINK_EVENT_PORT_TX_SUSPENDED BIT(9)
1529 #define ICE_AQ_LINK_EVENT_TOPO_CONFLICT BIT(10)
1530 #define ICE_AQ_LINK_EVENT_MEDIA_CONFLICT BIT(11)
1534 /* Set MAC Loopback command (direct 0x0620) */
1535 struct ice_aqc_set_mac_lb {
1537 #define ICE_AQ_MAC_LB_EN BIT(0)
1538 #define ICE_AQ_MAC_LB_OSC_CLK BIT(1)
1542 struct ice_aqc_link_topo_addr {
1545 #define ICE_AQC_LINK_TOPO_PORT_NUM_VALID BIT(0)
1547 #define ICE_AQC_LINK_TOPO_NODE_TYPE_S 0
1548 #define ICE_AQC_LINK_TOPO_NODE_TYPE_M (0xF << ICE_AQC_LINK_TOPO_NODE_TYPE_S)
1549 #define ICE_AQC_LINK_TOPO_NODE_TYPE_PHY 0
1550 #define ICE_AQC_LINK_TOPO_NODE_TYPE_GPIO_CTRL 1
1551 #define ICE_AQC_LINK_TOPO_NODE_TYPE_MUX_CTRL 2
1552 #define ICE_AQC_LINK_TOPO_NODE_TYPE_LED_CTRL 3
1553 #define ICE_AQC_LINK_TOPO_NODE_TYPE_LED 4
1554 #define ICE_AQC_LINK_TOPO_NODE_TYPE_THERMAL 5
1555 #define ICE_AQC_LINK_TOPO_NODE_TYPE_CAGE 6
1556 #define ICE_AQC_LINK_TOPO_NODE_TYPE_MEZZ 7
1557 #define ICE_AQC_LINK_TOPO_NODE_TYPE_ID_EEPROM 8
1558 #define ICE_AQC_LINK_TOPO_NODE_CTX_S 4
1559 #define ICE_AQC_LINK_TOPO_NODE_CTX_M \
1560 (0xF << ICE_AQC_LINK_TOPO_NODE_CTX_S)
1561 #define ICE_AQC_LINK_TOPO_NODE_CTX_GLOBAL 0
1562 #define ICE_AQC_LINK_TOPO_NODE_CTX_BOARD 1
1563 #define ICE_AQC_LINK_TOPO_NODE_CTX_PORT 2
1564 #define ICE_AQC_LINK_TOPO_NODE_CTX_NODE 3
1565 #define ICE_AQC_LINK_TOPO_NODE_CTX_PROVIDED 4
1566 #define ICE_AQC_LINK_TOPO_NODE_CTX_OVERRIDE 5
1569 #define ICE_AQC_LINK_TOPO_HANDLE_S 0
1570 #define ICE_AQC_LINK_TOPO_HANDLE_M (0x3FF << ICE_AQC_LINK_TOPO_HANDLE_S)
1571 /* Used to decode the handle field */
1572 #define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_M BIT(9)
1573 #define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_LOM BIT(9)
1574 #define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_MEZZ 0
1575 #define ICE_AQC_LINK_TOPO_HANDLE_NODE_S 0
1576 /* In case of a Mezzanine type */
1577 #define ICE_AQC_LINK_TOPO_HANDLE_MEZZ_NODE_M \
1578 (0x3F << ICE_AQC_LINK_TOPO_HANDLE_NODE_S)
1579 #define ICE_AQC_LINK_TOPO_HANDLE_MEZZ_S 6
1580 #define ICE_AQC_LINK_TOPO_HANDLE_MEZZ_M (0x7 << ICE_AQC_LINK_TOPO_HANDLE_MEZZ_S)
1581 /* In case of a LOM type */
1582 #define ICE_AQC_LINK_TOPO_HANDLE_LOM_NODE_M \
1583 (0x1FF << ICE_AQC_LINK_TOPO_HANDLE_NODE_S)
1586 /* Get Link Topology Handle (direct, 0x06E0) */
1587 struct ice_aqc_get_link_topo {
1588 struct ice_aqc_link_topo_addr addr;
1593 /* Set Port Identification LED (direct, 0x06E9) */
1594 struct ice_aqc_set_port_id_led {
1597 #define ICE_AQC_PORT_ID_PORT_NUM_VALID BIT(0)
1599 #define ICE_AQC_PORT_IDENT_LED_BLINK BIT(0)
1600 #define ICE_AQC_PORT_IDENT_LED_ORIG 0
1604 /* Read/Write SFF EEPROM command (indirect 0x06EE) */
1605 struct ice_aqc_sff_eeprom {
1608 #define ICE_AQC_SFF_PORT_NUM_VALID BIT(0)
1609 __le16 i2c_bus_addr;
1610 #define ICE_AQC_SFF_I2CBUS_7BIT_M 0x7F
1611 #define ICE_AQC_SFF_I2CBUS_10BIT_M 0x3FF
1612 #define ICE_AQC_SFF_I2CBUS_TYPE_M BIT(10)
1613 #define ICE_AQC_SFF_I2CBUS_TYPE_7BIT 0
1614 #define ICE_AQC_SFF_I2CBUS_TYPE_10BIT ICE_AQC_SFF_I2CBUS_TYPE_M
1615 #define ICE_AQC_SFF_SET_EEPROM_PAGE_S 11
1616 #define ICE_AQC_SFF_SET_EEPROM_PAGE_M (0x3 << ICE_AQC_SFF_SET_EEPROM_PAGE_S)
1617 #define ICE_AQC_SFF_NO_PAGE_CHANGE 0
1618 #define ICE_AQC_SFF_SET_23_ON_MISMATCH 1
1619 #define ICE_AQC_SFF_SET_22_ON_MISMATCH 2
1620 #define ICE_AQC_SFF_IS_WRITE BIT(15)
1621 __le16 i2c_mem_addr;
1623 #define ICE_AQC_SFF_EEPROM_BANK_S 0
1624 #define ICE_AQC_SFF_EEPROM_BANK_M (0xFF << ICE_AQC_SFF_EEPROM_BANK_S)
1625 #define ICE_AQC_SFF_EEPROM_PAGE_S 8
1626 #define ICE_AQC_SFF_EEPROM_PAGE_M (0xFF << ICE_AQC_SFF_EEPROM_PAGE_S)
1631 /* NVM Read command (indirect 0x0701)
1632 * NVM Erase commands (direct 0x0702)
1633 * NVM Write commands (indirect 0x0703)
1634 * NVM Write Activate commands (direct 0x0707)
1635 * NVM Shadow RAM Dump commands (direct 0x0707)
1637 struct ice_aqc_nvm {
1638 #define ICE_AQC_NVM_MAX_OFFSET 0xFFFFFF
1640 u8 offset_high; /* For Write Activate offset_high is used as flags2 */
1642 #define ICE_AQC_NVM_LAST_CMD BIT(0)
1643 #define ICE_AQC_NVM_PCIR_REQ BIT(0) /* Used by NVM Write reply */
1644 #define ICE_AQC_NVM_PRESERVATION_S 1 /* Used by NVM Write Activate only */
1645 #define ICE_AQC_NVM_PRESERVATION_M (3 << ICE_AQC_NVM_PRESERVATION_S)
1646 #define ICE_AQC_NVM_NO_PRESERVATION (0 << ICE_AQC_NVM_PRESERVATION_S)
1647 #define ICE_AQC_NVM_PRESERVE_ALL BIT(1)
1648 #define ICE_AQC_NVM_FACTORY_DEFAULT (2 << ICE_AQC_NVM_PRESERVATION_S)
1649 #define ICE_AQC_NVM_PRESERVE_SELECTED (3 << ICE_AQC_NVM_PRESERVATION_S)
1650 #define ICE_AQC_NVM_ACTIV_SEL_NVM BIT(3) /* Write Activate/SR Dump only */
1651 #define ICE_AQC_NVM_ACTIV_SEL_OROM BIT(4)
1652 #define ICE_AQC_NVM_ACTIV_SEL_NETLIST BIT(5)
1653 #define ICE_AQC_NVM_SPECIAL_UPDATE BIT(6)
1654 #define ICE_AQC_NVM_REVERT_LAST_ACTIV BIT(6) /* Write Activate only */
1655 #define ICE_AQC_NVM_ACTIV_SEL_MASK MAKEMASK(0x7, 3)
1656 #define ICE_AQC_NVM_FLASH_ONLY BIT(7)
1657 #define ICE_AQC_NVM_POR_FLAG 0 /* Used by NVM Write completion on ARQ */
1658 #define ICE_AQC_NVM_PERST_FLAG 1
1659 #define ICE_AQC_NVM_EMPR_FLAG 2
1660 __le16 module_typeid;
1662 #define ICE_AQC_NVM_ERASE_LEN 0xFFFF
1667 /* NVM Module_Type ID, needed offset and read_len for struct ice_aqc_nvm. */
1668 #define ICE_AQC_NVM_SECTOR_UNIT 4096 /* In Bytes */
1669 #define ICE_AQC_NVM_WORD_UNIT 2 /* In Bytes */
1671 #define ICE_AQC_NVM_START_POINT 0
1672 #define ICE_AQC_NVM_EMP_SR_PTR_OFFSET 0x90
1673 #define ICE_AQC_NVM_EMP_SR_PTR_RD_LEN 2 /* In Bytes */
1674 #define ICE_AQC_NVM_EMP_SR_PTR_M MAKEMASK(0x7FFF, 0)
1675 #define ICE_AQC_NVM_EMP_SR_PTR_TYPE_S 15
1676 #define ICE_AQC_NVM_EMP_SR_PTR_TYPE_M BIT(15)
1677 #define ICE_AQC_NVM_EMP_SR_PTR_TYPE_SECTOR 1
1679 #define ICE_AQC_NVM_LLDP_CFG_PTR_OFFSET 0x46
1680 #define ICE_AQC_NVM_LLDP_CFG_HEADER_LEN 2 /* In Bytes */
1681 #define ICE_AQC_NVM_LLDP_CFG_PTR_RD_LEN 2 /* In Bytes */
1683 #define ICE_AQC_NVM_LLDP_PRESERVED_MOD_ID 0x129
1684 #define ICE_AQC_NVM_CUR_LLDP_PERSIST_RD_OFFSET 2 /* In Bytes */
1685 #define ICE_AQC_NVM_LLDP_STATUS_M MAKEMASK(0xF, 0)
1686 #define ICE_AQC_NVM_LLDP_STATUS_M_LEN 4 /* In Bits */
1687 #define ICE_AQC_NVM_LLDP_STATUS_RD_LEN 4 /* In Bytes */
1689 /* The result of netlist NVM read comes in a TLV format. The actual data
1690 * (netlist header) starts from word offset 1 (byte 2). The FW strips
1691 * out the type field from the TLV header so all the netlist fields
1692 * should adjust their offset value by 1 word (2 bytes) in order to map
1693 * their correct location.
1695 #define ICE_AQC_NVM_LINK_TOPO_NETLIST_MOD_ID 0x11B
1696 #define ICE_AQC_NVM_LINK_TOPO_NETLIST_LEN_OFFSET 1
1697 #define ICE_AQC_NVM_LINK_TOPO_NETLIST_LEN 2 /* In bytes */
1698 #define ICE_AQC_NVM_NETLIST_NODE_COUNT_OFFSET 2
1699 #define ICE_AQC_NVM_NETLIST_NODE_COUNT_LEN 2 /* In bytes */
1700 #define ICE_AQC_NVM_NETLIST_ID_BLK_START_OFFSET 5
1701 #define ICE_AQC_NVM_NETLIST_ID_BLK_LEN 0x30 /* In words */
1703 /* netlist ID block field offsets (word offsets) */
1704 #define ICE_AQC_NVM_NETLIST_ID_BLK_MAJOR_VER_LOW 2
1705 #define ICE_AQC_NVM_NETLIST_ID_BLK_MAJOR_VER_HIGH 3
1706 #define ICE_AQC_NVM_NETLIST_ID_BLK_MINOR_VER_LOW 4
1707 #define ICE_AQC_NVM_NETLIST_ID_BLK_MINOR_VER_HIGH 5
1708 #define ICE_AQC_NVM_NETLIST_ID_BLK_TYPE_LOW 6
1709 #define ICE_AQC_NVM_NETLIST_ID_BLK_TYPE_HIGH 7
1710 #define ICE_AQC_NVM_NETLIST_ID_BLK_REV_LOW 8
1711 #define ICE_AQC_NVM_NETLIST_ID_BLK_REV_HIGH 9
1712 #define ICE_AQC_NVM_NETLIST_ID_BLK_SHA_HASH 0xA
1713 #define ICE_AQC_NVM_NETLIST_ID_BLK_CUST_VER 0x2F
1715 /* Used for 0x0704 as well as for 0x0705 commands */
1716 struct ice_aqc_nvm_cfg {
1718 #define ICE_AQC_ANVM_MULTIPLE_ELEMS BIT(0)
1719 #define ICE_AQC_ANVM_IMMEDIATE_FIELD BIT(1)
1720 #define ICE_AQC_ANVM_NEW_CFG BIT(2)
1729 struct ice_aqc_nvm_cfg_data {
1731 __le16 field_options;
1735 /* NVM Checksum Command (direct, 0x0706) */
1736 struct ice_aqc_nvm_checksum {
1738 #define ICE_AQC_NVM_CHECKSUM_VERIFY BIT(0)
1739 #define ICE_AQC_NVM_CHECKSUM_RECALC BIT(1)
1741 __le16 checksum; /* Used only by response */
1742 #define ICE_AQC_NVM_CHECKSUM_CORRECT 0xBABA
1746 /* Get LLDP MIB (indirect 0x0A00)
1747 * Note: This is also used by the LLDP MIB Change Event (0x0A01)
1748 * as the format is the same.
1750 struct ice_aqc_lldp_get_mib {
1752 #define ICE_AQ_LLDP_MIB_TYPE_S 0
1753 #define ICE_AQ_LLDP_MIB_TYPE_M (0x3 << ICE_AQ_LLDP_MIB_TYPE_S)
1754 #define ICE_AQ_LLDP_MIB_LOCAL 0
1755 #define ICE_AQ_LLDP_MIB_REMOTE 1
1756 #define ICE_AQ_LLDP_MIB_LOCAL_AND_REMOTE 2
1757 #define ICE_AQ_LLDP_BRID_TYPE_S 2
1758 #define ICE_AQ_LLDP_BRID_TYPE_M (0x3 << ICE_AQ_LLDP_BRID_TYPE_S)
1759 #define ICE_AQ_LLDP_BRID_TYPE_NEAREST_BRID 0
1760 #define ICE_AQ_LLDP_BRID_TYPE_NON_TPMR 1
1761 /* Tx pause flags in the 0xA01 event use ICE_AQ_LLDP_TX_* */
1762 #define ICE_AQ_LLDP_TX_S 0x4
1763 #define ICE_AQ_LLDP_TX_M (0x03 << ICE_AQ_LLDP_TX_S)
1764 #define ICE_AQ_LLDP_TX_ACTIVE 0
1765 #define ICE_AQ_LLDP_TX_SUSPENDED 1
1766 #define ICE_AQ_LLDP_TX_FLUSHED 3
1767 /* The following bytes are reserved for the Get LLDP MIB command (0x0A00)
1768 * and in the LLDP MIB Change Event (0x0A01). They are valid for the
1769 * Get LLDP MIB (0x0A00) response only.
1779 /* Configure LLDP MIB Change Event (direct 0x0A01) */
1780 /* For MIB Change Event use ice_aqc_lldp_get_mib structure above */
1781 struct ice_aqc_lldp_set_mib_change {
1783 #define ICE_AQ_LLDP_MIB_UPDATE_ENABLE 0x0
1784 #define ICE_AQ_LLDP_MIB_UPDATE_DIS 0x1
1788 /* Add LLDP TLV (indirect 0x0A02)
1789 * Delete LLDP TLV (indirect 0x0A04)
1791 struct ice_aqc_lldp_add_delete_tlv {
1792 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */
1800 /* Update LLDP TLV (indirect 0x0A03) */
1801 struct ice_aqc_lldp_update_tlv {
1802 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */
1811 /* Stop LLDP (direct 0x0A05) */
1812 struct ice_aqc_lldp_stop {
1814 #define ICE_AQ_LLDP_AGENT_STATE_MASK BIT(0)
1815 #define ICE_AQ_LLDP_AGENT_STOP 0x0
1816 #define ICE_AQ_LLDP_AGENT_SHUTDOWN ICE_AQ_LLDP_AGENT_STATE_MASK
1817 #define ICE_AQ_LLDP_AGENT_PERSIST_DIS BIT(1)
1821 /* Start LLDP (direct 0x0A06) */
1822 struct ice_aqc_lldp_start {
1824 #define ICE_AQ_LLDP_AGENT_START BIT(0)
1825 #define ICE_AQ_LLDP_AGENT_PERSIST_ENA BIT(1)
1829 /* Get CEE DCBX Oper Config (0x0A07)
1830 * The command uses the generic descriptor struct and
1831 * returns the struct below as an indirect response.
1833 struct ice_aqc_get_cee_dcb_cfg_resp {
1838 __le16 oper_app_prio;
1839 #define ICE_AQC_CEE_APP_FCOE_S 0
1840 #define ICE_AQC_CEE_APP_FCOE_M (0x7 << ICE_AQC_CEE_APP_FCOE_S)
1841 #define ICE_AQC_CEE_APP_ISCSI_S 3
1842 #define ICE_AQC_CEE_APP_ISCSI_M (0x7 << ICE_AQC_CEE_APP_ISCSI_S)
1843 #define ICE_AQC_CEE_APP_FIP_S 8
1844 #define ICE_AQC_CEE_APP_FIP_M (0x7 << ICE_AQC_CEE_APP_FIP_S)
1846 #define ICE_AQC_CEE_PG_STATUS_S 0
1847 #define ICE_AQC_CEE_PG_STATUS_M (0x7 << ICE_AQC_CEE_PG_STATUS_S)
1848 #define ICE_AQC_CEE_PFC_STATUS_S 3
1849 #define ICE_AQC_CEE_PFC_STATUS_M (0x7 << ICE_AQC_CEE_PFC_STATUS_S)
1850 #define ICE_AQC_CEE_FCOE_STATUS_S 8
1851 #define ICE_AQC_CEE_FCOE_STATUS_M (0x7 << ICE_AQC_CEE_FCOE_STATUS_S)
1852 #define ICE_AQC_CEE_ISCSI_STATUS_S 11
1853 #define ICE_AQC_CEE_ISCSI_STATUS_M (0x7 << ICE_AQC_CEE_ISCSI_STATUS_S)
1854 #define ICE_AQC_CEE_FIP_STATUS_S 16
1855 #define ICE_AQC_CEE_FIP_STATUS_M (0x7 << ICE_AQC_CEE_FIP_STATUS_S)
1859 /* Set Local LLDP MIB (indirect 0x0A08)
1860 * Used to replace the local MIB of a given LLDP agent. e.g. DCBX
1862 struct ice_aqc_lldp_set_local_mib {
1864 #define SET_LOCAL_MIB_TYPE_DCBX_M BIT(0)
1865 #define SET_LOCAL_MIB_TYPE_LOCAL_MIB 0
1866 #define SET_LOCAL_MIB_TYPE_CEE_M BIT(1)
1867 #define SET_LOCAL_MIB_TYPE_CEE_WILLING 0
1868 #define SET_LOCAL_MIB_TYPE_CEE_NON_WILLING SET_LOCAL_MIB_TYPE_CEE_M
1876 struct ice_aqc_lldp_set_local_mib_resp {
1878 #define SET_LOCAL_MIB_RESP_EVENT_M BIT(0)
1879 #define SET_LOCAL_MIB_RESP_MIB_CHANGE_SILENT 0
1880 #define SET_LOCAL_MIB_RESP_MIB_CHANGE_EVENT SET_LOCAL_MIB_RESP_EVENT_M
1884 /* Stop/Start LLDP Agent (direct 0x0A09)
1885 * Used for stopping/starting specific LLDP agent. e.g. DCBX.
1886 * The same structure is used for the response, with the command field
1887 * being used as the status field.
1889 struct ice_aqc_lldp_stop_start_specific_agent {
1891 #define ICE_AQC_START_STOP_AGENT_M BIT(0)
1892 #define ICE_AQC_START_STOP_AGENT_STOP_DCBX 0
1893 #define ICE_AQC_START_STOP_AGENT_START_DCBX ICE_AQC_START_STOP_AGENT_M
1897 /* LLDP Filter Control (direct 0x0A0A) */
1898 struct ice_aqc_lldp_filter_ctrl {
1900 #define ICE_AQC_LLDP_FILTER_ACTION_M MAKEMASK(3, 0)
1901 #define ICE_AQC_LLDP_FILTER_ACTION_ADD 0x0
1902 #define ICE_AQC_LLDP_FILTER_ACTION_DELETE 0x1
1903 #define ICE_AQC_LLDP_FILTER_ACTION_UPDATE 0x2
1909 /* Get/Set RSS key (indirect 0x0B04/0x0B02) */
1910 struct ice_aqc_get_set_rss_key {
1911 #define ICE_AQC_GSET_RSS_KEY_VSI_VALID BIT(15)
1912 #define ICE_AQC_GSET_RSS_KEY_VSI_ID_S 0
1913 #define ICE_AQC_GSET_RSS_KEY_VSI_ID_M (0x3FF << ICE_AQC_GSET_RSS_KEY_VSI_ID_S)
1920 #define ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE 0x28
1921 #define ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE 0xC
1922 #define ICE_GET_SET_RSS_KEY_EXTEND_KEY_SIZE \
1923 (ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE + \
1924 ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE)
1927 * struct ice_aqc_get_set_rss_keys - Get/Set RSS hash key command buffer
1928 * @standard_rss_key: 40 most significant bytes of hash key
1929 * @extended_hash_key: 12 least significant bytes of hash key
1931 * Set/Get 40 byte hash key using standard_rss_key field, and set
1932 * extended_hash_key field to zero. Set/Get 52 byte hash key using
1933 * standard_rss_key field for 40 most significant bytes and the
1934 * extended_hash_key field for the 12 least significant bytes of hash key.
1936 struct ice_aqc_get_set_rss_keys {
1937 u8 standard_rss_key[ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE];
1938 u8 extended_hash_key[ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE];
1941 /* Get/Set RSS LUT (indirect 0x0B05/0x0B03) */
1942 struct ice_aqc_get_set_rss_lut {
1943 #define ICE_AQC_GSET_RSS_LUT_VSI_VALID BIT(15)
1944 #define ICE_AQC_GSET_RSS_LUT_VSI_ID_S 0
1945 #define ICE_AQC_GSET_RSS_LUT_VSI_ID_M (0x3FF << ICE_AQC_GSET_RSS_LUT_VSI_ID_S)
1947 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S 0
1948 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_M \
1949 (0x3 << ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S)
1951 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_VSI 0
1952 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF 1
1953 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL 2
1955 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S 2
1956 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M \
1957 (0x3 << ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S)
1959 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128 128
1960 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128_FLAG 0
1961 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512 512
1962 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512_FLAG 1
1963 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K 2048
1964 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K_FLAG 2
1966 #define ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S 4
1967 #define ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_M \
1968 (0xF << ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S)
1976 /* Clear FD Table Command (direct, 0x0B06) */
1977 struct ice_aqc_clear_fd_table {
1979 #define CL_FD_VM_VF_TYPE_VSI_IDX 1
1980 #define CL_FD_VM_VF_TYPE_PF_IDX 2
1986 /* Allocate ACL table (indirect 0x0C10) */
1987 #define ICE_AQC_ACL_KEY_WIDTH 40
1988 #define ICE_AQC_ACL_KEY_WIDTH_BYTES 5
1989 #define ICE_AQC_ACL_TCAM_DEPTH 512
1990 #define ICE_ACL_ENTRY_ALLOC_UNIT 64
1991 #define ICE_AQC_MAX_CONCURRENT_ACL_TBL 15
1992 #define ICE_AQC_MAX_ACTION_MEMORIES 20
1993 #define ICE_AQC_MAX_ACTION_ENTRIES 512
1994 #define ICE_AQC_ACL_SLICES 16
1995 #define ICE_AQC_ALLOC_ID_LESS_THAN_4K 0x1000
1996 /* The ACL block supports up to 8 actions per a single output. */
1997 #define ICE_AQC_TBL_MAX_ACTION_PAIRS 4
1999 #define ICE_AQC_MAX_TCAM_ALLOC_UNITS (ICE_AQC_ACL_TCAM_DEPTH / \
2000 ICE_ACL_ENTRY_ALLOC_UNIT)
2001 #define ICE_AQC_ACL_ALLOC_UNITS (ICE_AQC_ACL_SLICES * \
2002 ICE_AQC_MAX_TCAM_ALLOC_UNITS)
2004 struct ice_aqc_acl_alloc_table {
2007 u8 act_pairs_per_entry;
2008 /* For non-concurrent table allocation, this field needs
2009 * to be set to zero(0) otherwise it shall specify the
2010 * amount of concurrent tables whose AllocIDs are
2011 * specified in buffer. Thus the newly allocated table
2012 * is concurrent with table IDs specified in AllocIDs.
2014 #define ICE_AQC_ACL_ALLOC_TABLE_TYPE_NONCONCURR 0
2021 /* Allocate ACL table command buffer format */
2022 struct ice_aqc_acl_alloc_table_data {
2023 /* Dependent table AllocIDs. Each word in this 15 word array specifies
2024 * a dependent table AllocID according to the amount specified in the
2025 * "table_type" field. All unused words shall be set to 0xFFFF
2027 #define ICE_AQC_CONCURR_ID_INVALID 0xffff
2028 __le16 alloc_ids[ICE_AQC_MAX_CONCURRENT_ACL_TBL];
2031 /* Deallocate ACL table (indirect 0x0C11)
2032 * Allocate ACL action-pair (indirect 0x0C12)
2033 * Deallocate ACL action-pair (indirect 0x0C13)
2036 /* Following structure is common and used in case of deallocation
2037 * of ACL table and action-pair
2039 struct ice_aqc_acl_tbl_actpair {
2040 /* Alloc ID of the table being released */
2047 /* This response structure is same in case of alloc/dealloc table,
2048 * alloc/dealloc action-pair
2050 struct ice_aqc_acl_generic {
2051 /* if alloc_id is below 0x1000 then alllocation failed due to
2052 * unavailable resources, else this is set by FW to identify
2058 /* to be used only in case of alloc/dealloc table */
2060 /* Index of the first TCAM block, otherwise set to 0xFF
2061 * for a failed allocation
2064 /* Index of the last TCAM block. This index shall be
2065 * set to the value of first_tcam for single TCAM block
2066 * allocation, otherwise set to 0xFF for a failed
2071 /* reserved in case of alloc/dealloc action-pair */
2077 /* index of first entry (in both TCAM and action memories),
2078 * otherwise set to 0xFF for a failed allocation
2081 /* index of last entry (in both TCAM and action memories),
2082 * otherwise set to 0xFF for a failed allocation
2086 /* Each act_mem element specifies the order of the memory
2089 u8 act_mem[ICE_AQC_MAX_ACTION_MEMORIES];
2092 /* Allocate ACL scenario (indirect 0x0C14). This command doesn't have separate
2093 * response buffer since original command buffer gets updated with
2094 * 'scen_id' in case of success
2096 struct ice_aqc_acl_alloc_scen {
2110 /* De-allocate ACL scenario (direct 0x0C15). This command doesn't need
2111 * separate response buffer since nothing to be returned as a response
2114 struct ice_aqc_acl_dealloc_scen {
2119 /* Update ACL scenario (direct 0x0C1B)
2120 * Query ACL scenario (direct 0x0C23)
2122 struct ice_aqc_acl_update_query_scen {
2129 /* Input buffer format in case allocate/update ACL scenario and same format
2130 * is used for response buffer in case of query ACL scenario.
2131 * NOTE: de-allocate ACL scenario is direct command and doesn't require
2132 * "buffer", hence no buffer format.
2134 struct ice_aqc_acl_scen {
2136 /* Byte [x] selection for the TCAM key. This value must be
2137 * set to 0x0 for unusued TCAM.
2138 * Only Bit 6..0 is used in each byte and MSB is reserved
2140 #define ICE_AQC_ACL_ALLOC_SCE_SELECT_M 0x7F
2141 #define ICE_AQC_ACL_BYTE_SEL_BASE 0x20
2142 #define ICE_AQC_ACL_BYTE_SEL_BASE_PID 0x3E
2143 #define ICE_AQC_ACL_BYTE_SEL_BASE_PKT_DIR ICE_AQC_ACL_BYTE_SEL_BASE
2144 #define ICE_AQC_ACL_BYTE_SEL_BASE_RNG_CHK 0x3F
2146 /* TCAM Block entry masking. This value should be set to 0x0 for
2150 /* Bit 0 : masks TCAM entries 0-63
2151 * Bit 1 : masks TCAM entries 64-127
2152 * Bit 2 to 7 : follow the pattern of bit 0 and 1
2154 #define ICE_AQC_ACL_ALLOC_SCE_START_CMP BIT(0)
2155 #define ICE_AQC_ACL_ALLOC_SCE_START_SET BIT(1)
2158 } tcam_cfg[ICE_AQC_ACL_SLICES];
2160 /* Each byte, Bit 6..0: Action memory association to a TCAM block,
2161 * otherwise it shall be set to 0x0 for disabled memory action.
2162 * Bit 7 : Action memory enable for this scenario
2164 #define ICE_AQC_ACL_SCE_ACT_MEM_TCAM_ASSOC_M 0x7F
2165 #define ICE_AQC_ACL_SCE_ACT_MEM_EN BIT(7)
2166 u8 act_mem_cfg[ICE_AQC_MAX_ACTION_MEMORIES];
2169 /* Allocate ACL counters (indirect 0x0C16) */
2170 struct ice_aqc_acl_alloc_counters {
2171 /* Amount of contiguous counters requested. Min value is 1 and
2174 #define ICE_AQC_ACL_ALLOC_CNT_MIN_AMT 0x1
2175 #define ICE_AQC_ACL_ALLOC_CNT_MAX_AMT 0xFF
2178 /* Counter type: 'single counter' which can be configured to count
2179 * either bytes or packets
2181 #define ICE_AQC_ACL_CNT_TYPE_SINGLE 0x0
2183 /* Counter type: 'counter pair' which counts number of bytes and number
2186 #define ICE_AQC_ACL_CNT_TYPE_DUAL 0x1
2187 /* requested counter type, single/dual */
2190 /* counter bank allocation shall be 0-3 for 'byte or packet counter' */
2191 #define ICE_AQC_ACL_MAX_CNT_SINGLE 0x3
2192 /* counter bank allocation shall be 0-1 for 'byte and packet counter dual' */
2193 #define ICE_AQC_ACL_MAX_CNT_DUAL 0x1
2194 /* requested counter bank allocation */
2200 /* Applicable only in case of command */
2204 /* Applicable only in case of response */
2205 #define ICE_AQC_ACL_ALLOC_CNT_INVAL 0xFFFF
2207 /* Index of first allocated counter. 0xFFFF in case
2208 * of unsuccessful allocation
2210 __le16 first_counter;
2211 /* Index of last allocated counter. 0xFFFF in case
2212 * of unsuccessful allocation
2214 __le16 last_counter;
2220 /* De-allocate ACL counters (direct 0x0C17) */
2221 struct ice_aqc_acl_dealloc_counters {
2222 /* first counter being released */
2223 __le16 first_counter;
2224 /* last counter being released */
2225 __le16 last_counter;
2226 /* requested counter type, single/dual */
2228 /* requested counter bank allocation */
2233 /* De-allocate ACL resources (direct 0x0C1A). Used by SW to release all the
2234 * resources allocated for it using a single command
2236 struct ice_aqc_acl_dealloc_res {
2240 /* Program ACL actionpair (indirect 0x0C1C)
2241 * Query ACL actionpair (indirect 0x0C25)
2243 struct ice_aqc_acl_actpair {
2244 /* action mem index to program/update */
2247 /* The entry index in action memory to be programmed/updated */
2248 __le16 act_entry_index;
2254 /* Input buffer format for program/query action-pair admin command */
2255 struct ice_acl_act_entry {
2256 /* Action priority, values must be between 0..7 */
2257 #define ICE_AQC_ACT_PRIO_VALID_MAX 7
2258 #define ICE_AQC_ACT_PRIO_MSK MAKEMASK(0xff, 0)
2260 /* Action meta-data identifier. This field should be set to 0x0
2263 #define ICE_AQC_ACT_MDID_S 8
2264 #define ICE_AQC_ACT_MDID_MSK MAKEMASK(0xff00, ICE_AQC_ACT_MDID_S)
2267 #define ICE_AQC_ACT_VALUE_S 16
2268 #define ICE_AQC_ACT_VALUE_MSK MAKEMASK(0xffff0000, 16)
2272 #define ICE_ACL_NUM_ACT_PER_ACT_PAIR 2
2273 struct ice_aqc_actpair {
2274 struct ice_acl_act_entry act[ICE_ACL_NUM_ACT_PER_ACT_PAIR];
2277 /* Generic format used to describe either input or response buffer
2278 * for admin commands related to ACL profile
2280 struct ice_aqc_acl_prof_generic_frmt {
2281 /* The first byte of the byte selection base is reserved to keep the
2282 * first byte of the field vector where the packet direction info is
2283 * available. Thus we should start at index 1 of the field vector to
2284 * map its entries to the byte selection base.
2286 #define ICE_AQC_ACL_PROF_BYTE_SEL_START_IDX 1
2288 * Bit 0..5 = Byte selection for the byte selection base from the
2289 * extracted fields (expressed as byte offset in extracted fields).
2290 * Applicable values are 0..63
2291 * Bit 6..7 = Reserved
2293 #define ICE_AQC_ACL_PROF_BYTE_SEL_ELEMS 30
2294 u8 byte_selection[ICE_AQC_ACL_PROF_BYTE_SEL_ELEMS];
2296 * Bit 0..4 = Word selection for the word selection base from the
2297 * extracted fields (expressed as word offset in extracted fields).
2298 * Applicable values are 0..31
2299 * Bit 5..7 = Reserved
2301 #define ICE_AQC_ACL_PROF_WORD_SEL_ELEMS 32
2302 u8 word_selection[ICE_AQC_ACL_PROF_WORD_SEL_ELEMS];
2304 * Bit 0..3 = Double word selection for the double-word selection base
2305 * from the extracted fields (expressed as double-word offset in
2306 * extracted fields).
2307 * Applicable values are 0..15
2308 * Bit 4..7 = Reserved
2310 #define ICE_AQC_ACL_PROF_DWORD_SEL_ELEMS 15
2311 u8 dword_selection[ICE_AQC_ACL_PROF_DWORD_SEL_ELEMS];
2312 /* Scenario numbers for individual Physical Function's */
2313 #define ICE_AQC_ACL_PROF_PF_SCEN_NUM_ELEMS 8
2314 u8 pf_scenario_num[ICE_AQC_ACL_PROF_PF_SCEN_NUM_ELEMS];
2317 /* Program ACL profile extraction (indirect 0x0C1D)
2318 * Program ACL profile ranges (indirect 0x0C1E)
2319 * Query ACL profile (indirect 0x0C21)
2320 * Query ACL profile ranges (indirect 0x0C22)
2322 struct ice_aqc_acl_profile {
2323 u8 profile_id; /* Programmed/Updated profile ID */
2329 /* Input buffer format for program profile extraction admin command and
2330 * response buffer format for query profile admin command is as defined
2331 * in struct ice_aqc_acl_prof_generic_frmt
2334 /* Input buffer format for program profile ranges and query profile ranges
2335 * admin commands. Same format is used for response buffer in case of query
2336 * profile ranges command
2338 struct ice_acl_rng_data {
2339 /* The range checker output shall be sent when the value
2340 * related to this range checker is lower than low boundary
2342 __be16 low_boundary;
2343 /* The range checker output shall be sent when the value
2344 * related to this range checker is higher than high boundary
2346 __be16 high_boundary;
2347 /* A value of '0' in bit shall clear the relevant bit input
2348 * to the range checker
2353 struct ice_aqc_acl_profile_ranges {
2354 #define ICE_AQC_ACL_PROF_RANGES_NUM_CFG 8
2355 struct ice_acl_rng_data checker_cfg[ICE_AQC_ACL_PROF_RANGES_NUM_CFG];
2358 /* Program ACL entry (indirect 0x0C20)
2359 * Query ACL entry (indirect 0x0C24)
2361 struct ice_aqc_acl_entry {
2362 u8 tcam_index; /* Updated TCAM block index */
2364 __le16 entry_index; /* Updated entry index */
2370 /* Input buffer format in case of program ACL entry and response buffer format
2371 * in case of query ACL entry
2373 struct ice_aqc_acl_data {
2374 /* Entry key and entry key invert are 40 bits wide.
2375 * Byte 0..4 : entry key and Byte 5..7 are reserved
2376 * Byte 8..12: entry key invert and Byte 13..15 are reserved
2381 } entry_key, entry_key_invert;
2384 /* Query ACL counter (direct 0x0C27) */
2385 struct ice_aqc_acl_query_counter {
2386 /* Queried counter index */
2387 __le16 counter_index;
2388 /* Queried counter bank */
2395 /* Holds counter value/packet counter value */
2402 /* Add Tx LAN Queues (indirect 0x0C30) */
2403 struct ice_aqc_add_txqs {
2411 /* This is the descriptor of each queue entry for the Add Tx LAN Queues
2412 * command (0x0C30). Only used within struct ice_aqc_add_tx_qgrp.
2414 struct ice_aqc_add_txqs_perq {
2420 struct ice_aqc_txsched_elem info;
2423 /* The format of the command buffer for Add Tx LAN Queues (0x0C30)
2424 * is an array of the following structs. Please note that the length of
2425 * each struct ice_aqc_add_tx_qgrp is variable due
2426 * to the variable number of queues in each group!
2428 struct ice_aqc_add_tx_qgrp {
2432 struct ice_aqc_add_txqs_perq txqs[STRUCT_HACK_VAR_LEN];
2435 /* Disable Tx LAN Queues (indirect 0x0C31) */
2436 struct ice_aqc_dis_txqs {
2438 #define ICE_AQC_Q_DIS_CMD_S 0
2439 #define ICE_AQC_Q_DIS_CMD_M (0x3 << ICE_AQC_Q_DIS_CMD_S)
2440 #define ICE_AQC_Q_DIS_CMD_NO_FUNC_RESET (0 << ICE_AQC_Q_DIS_CMD_S)
2441 #define ICE_AQC_Q_DIS_CMD_VM_RESET BIT(ICE_AQC_Q_DIS_CMD_S)
2442 #define ICE_AQC_Q_DIS_CMD_VF_RESET (2 << ICE_AQC_Q_DIS_CMD_S)
2443 #define ICE_AQC_Q_DIS_CMD_PF_RESET (3 << ICE_AQC_Q_DIS_CMD_S)
2444 #define ICE_AQC_Q_DIS_CMD_SUBSEQ_CALL BIT(2)
2445 #define ICE_AQC_Q_DIS_CMD_FLUSH_PIPE BIT(3)
2447 __le16 vmvf_and_timeout;
2448 #define ICE_AQC_Q_DIS_VMVF_NUM_S 0
2449 #define ICE_AQC_Q_DIS_VMVF_NUM_M (0x3FF << ICE_AQC_Q_DIS_VMVF_NUM_S)
2450 #define ICE_AQC_Q_DIS_TIMEOUT_S 10
2451 #define ICE_AQC_Q_DIS_TIMEOUT_M (0x3F << ICE_AQC_Q_DIS_TIMEOUT_S)
2452 __le32 blocked_cgds;
2457 /* The buffer for Disable Tx LAN Queues (indirect 0x0C31)
2458 * contains the following structures, arrayed one after the
2460 * Note: Since the q_id is 16 bits wide, if the
2461 * number of queues is even, then 2 bytes of alignment MUST be
2462 * added before the start of the next group, to allow correct
2463 * alignment of the parent_teid field.
2466 struct ice_aqc_dis_txq_item {
2470 /* The length of the q_id array varies according to num_qs */
2471 #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S 15
2472 #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_LAN_Q \
2473 (0 << ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S)
2474 #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_RDMA_QSET \
2475 (1 << ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S)
2476 __le16 q_id[STRUCT_HACK_VAR_LEN];
2481 /* Tx LAN Queues Cleanup Event (0x0C31) */
2482 struct ice_aqc_txqs_cleanup {
2488 /* Move / Reconfigure Tx Queues (indirect 0x0C32) */
2489 struct ice_aqc_move_txqs {
2491 #define ICE_AQC_Q_CMD_TYPE_S 0
2492 #define ICE_AQC_Q_CMD_TYPE_M (0x3 << ICE_AQC_Q_CMD_TYPE_S)
2493 #define ICE_AQC_Q_CMD_TYPE_MOVE 1
2494 #define ICE_AQC_Q_CMD_TYPE_TC_CHANGE 2
2495 #define ICE_AQC_Q_CMD_TYPE_MOVE_AND_TC 3
2496 #define ICE_AQC_Q_CMD_SUBSEQ_CALL BIT(2)
2497 #define ICE_AQC_Q_CMD_FLUSH_PIPE BIT(3)
2501 #define ICE_AQC_Q_CMD_TIMEOUT_S 2
2502 #define ICE_AQC_Q_CMD_TIMEOUT_M (0x3F << ICE_AQC_Q_CMD_TIMEOUT_S)
2503 __le32 blocked_cgds;
2508 /* Per-queue data buffer for the Move Tx LAN Queues command/response */
2509 struct ice_aqc_move_txqs_elem {
2516 /* Indirect data buffer for the Move Tx LAN Queues command/response */
2517 struct ice_aqc_move_txqs_data {
2520 struct ice_aqc_move_txqs_elem txqs[STRUCT_HACK_VAR_LEN];
2523 /* Download Package (indirect 0x0C40) */
2524 /* Also used for Update Package (indirect 0x0C42 and 0x0C41) */
2525 struct ice_aqc_download_pkg {
2527 #define ICE_AQC_DOWNLOAD_PKG_LAST_BUF 0x01
2534 struct ice_aqc_download_pkg_resp {
2535 __le32 error_offset;
2541 /* Get Package Info List (indirect 0x0C43) */
2542 struct ice_aqc_get_pkg_info_list {
2549 /* Version format for packages */
2550 struct ice_pkg_ver {
2557 #define ICE_PKG_NAME_SIZE 32
2558 #define ICE_SEG_NAME_SIZE 28
2560 struct ice_aqc_get_pkg_info {
2561 struct ice_pkg_ver ver;
2562 char name[ICE_SEG_NAME_SIZE];
2566 u8 is_active_at_boot;
2570 /* Get Package Info List response buffer format (0x0C43) */
2571 struct ice_aqc_get_pkg_info_resp {
2573 struct ice_aqc_get_pkg_info pkg_info[STRUCT_HACK_VAR_LEN];
2576 /* Driver Shared Parameters (direct, 0x0C90) */
2577 struct ice_aqc_driver_shared_params {
2579 #define ICE_AQC_DRIVER_PARAM_OP_MASK BIT(0)
2580 #define ICE_AQC_DRIVER_PARAM_SET 0
2581 #define ICE_AQC_DRIVER_PARAM_GET 1
2583 #define ICE_AQC_DRIVER_PARAM_MAX_IDX 15
2590 /* Lan Queue Overflow Event (direct, 0x1001) */
2591 struct ice_aqc_event_lan_overflow {
2592 __le32 prtdcb_ruptq;
2597 /* Set Health Status (direct 0xFF20) */
2598 struct ice_aqc_set_health_status_config {
2600 #define ICE_AQC_HEALTH_STATUS_SET_PF_SPECIFIC_MASK BIT(0)
2601 #define ICE_AQC_HEALTH_STATUS_SET_ALL_PF_MASK BIT(1)
2602 #define ICE_AQC_HEALTH_STATUS_SET_GLOBAL_MASK BIT(2)
2606 /* Get Health Status codes (indirect 0xFF21) */
2607 struct ice_aqc_get_supported_health_status_codes {
2608 __le16 health_code_count;
2614 /* Get Health Status (indirect 0xFF22) */
2615 struct ice_aqc_get_health_status {
2616 __le16 health_status_count;
2622 /* Get Health Status event buffer entry, (0xFF22)
2623 * repeated per reported health status
2625 struct ice_aqc_health_status_elem {
2626 __le16 health_status_code;
2627 __le16 event_source;
2628 #define ICE_AQC_HEALTH_STATUS_PF (0x1)
2629 #define ICE_AQC_HEALTH_STATUS_PORT (0x2)
2630 #define ICE_AQC_HEALTH_STATUS_GLOBAL (0x3)
2631 __le32 internal_data1;
2632 #define ICE_AQC_HEALTH_STATUS_UNDEFINED_DATA (0xDEADBEEF)
2633 __le32 internal_data2;
2636 /* Clear Health Status (direct 0xFF23) */
2637 struct ice_aqc_clear_health_status {
2642 * struct ice_aq_desc - Admin Queue (AQ) descriptor
2643 * @flags: ICE_AQ_FLAG_* flags
2644 * @opcode: AQ command opcode
2645 * @datalen: length in bytes of indirect/external data buffer
2646 * @retval: return value from firmware
2647 * @cookie_h: opaque data high-half
2648 * @cookie_l: opaque data low-half
2649 * @params: command-specific parameters
2651 * Descriptor format for commands the driver posts on the Admin Transmit Queue
2652 * (ATQ). The firmware writes back onto the command descriptor and returns
2653 * the result of the command. Asynchronous events that are not an immediate
2654 * result of the command are written to the Admin Receive Queue (ARQ) using
2655 * the same descriptor format. Descriptors are in little-endian notation with
2658 struct ice_aq_desc {
2667 struct ice_aqc_generic generic;
2668 struct ice_aqc_get_ver get_ver;
2669 struct ice_aqc_driver_ver driver_ver;
2670 struct ice_aqc_q_shutdown q_shutdown;
2671 struct ice_aqc_req_res res_owner;
2672 struct ice_aqc_manage_mac_read mac_read;
2673 struct ice_aqc_manage_mac_write mac_write;
2674 struct ice_aqc_clear_pxe clear_pxe;
2675 struct ice_aqc_config_no_drop_policy no_drop;
2676 struct ice_aqc_add_update_mir_rule add_update_rule;
2677 struct ice_aqc_delete_mir_rule del_rule;
2678 struct ice_aqc_list_caps get_cap;
2679 struct ice_aqc_get_phy_caps get_phy;
2680 struct ice_aqc_set_phy_cfg set_phy;
2681 struct ice_aqc_restart_an restart_an;
2682 struct ice_aqc_sff_eeprom read_write_sff_param;
2683 struct ice_aqc_set_port_id_led set_port_id_led;
2684 struct ice_aqc_get_sw_cfg get_sw_conf;
2685 struct ice_aqc_sw_rules sw_rules;
2686 struct ice_aqc_storm_cfg storm_conf;
2687 struct ice_aqc_add_get_recipe add_get_recipe;
2688 struct ice_aqc_recipe_to_profile recipe_to_profile;
2689 struct ice_aqc_get_topo get_topo;
2690 struct ice_aqc_sched_elem_cmd sched_elem_cmd;
2691 struct ice_aqc_query_txsched_res query_sched_res;
2692 struct ice_aqc_query_node_to_root query_node_to_root;
2693 struct ice_aqc_cfg_l2_node_cgd cfg_l2_node_cgd;
2694 struct ice_aqc_query_port_ets port_ets;
2695 struct ice_aqc_rl_profile rl_profile;
2696 struct ice_aqc_nvm nvm;
2697 struct ice_aqc_nvm_cfg nvm_cfg;
2698 struct ice_aqc_nvm_checksum nvm_checksum;
2699 struct ice_aqc_pfc_ignore pfc_ignore;
2700 struct ice_aqc_set_query_pfc_mode set_query_pfc_mode;
2701 struct ice_aqc_set_dcb_params set_dcb_params;
2702 struct ice_aqc_lldp_get_mib lldp_get_mib;
2703 struct ice_aqc_lldp_set_mib_change lldp_set_event;
2704 struct ice_aqc_lldp_add_delete_tlv lldp_add_delete_tlv;
2705 struct ice_aqc_lldp_update_tlv lldp_update_tlv;
2706 struct ice_aqc_lldp_stop lldp_stop;
2707 struct ice_aqc_lldp_start lldp_start;
2708 struct ice_aqc_lldp_set_local_mib lldp_set_mib;
2709 struct ice_aqc_lldp_stop_start_specific_agent lldp_agent_ctrl;
2710 struct ice_aqc_lldp_filter_ctrl lldp_filter_ctrl;
2711 struct ice_aqc_get_set_rss_lut get_set_rss_lut;
2712 struct ice_aqc_get_set_rss_key get_set_rss_key;
2713 struct ice_aqc_clear_fd_table clear_fd_table;
2714 struct ice_aqc_acl_alloc_table alloc_table;
2715 struct ice_aqc_acl_tbl_actpair tbl_actpair;
2716 struct ice_aqc_acl_alloc_scen alloc_scen;
2717 struct ice_aqc_acl_dealloc_scen dealloc_scen;
2718 struct ice_aqc_acl_update_query_scen update_query_scen;
2719 struct ice_aqc_acl_alloc_counters alloc_counters;
2720 struct ice_aqc_acl_dealloc_counters dealloc_counters;
2721 struct ice_aqc_acl_dealloc_res dealloc_res;
2722 struct ice_aqc_acl_entry program_query_entry;
2723 struct ice_aqc_acl_actpair program_query_actpair;
2724 struct ice_aqc_acl_profile profile;
2725 struct ice_aqc_acl_query_counter query_counter;
2726 struct ice_aqc_add_txqs add_txqs;
2727 struct ice_aqc_dis_txqs dis_txqs;
2728 struct ice_aqc_move_txqs move_txqs;
2729 struct ice_aqc_txqs_cleanup txqs_cleanup;
2730 struct ice_aqc_add_get_update_free_vsi vsi_cmd;
2731 struct ice_aqc_add_update_free_vsi_resp add_update_free_vsi_res;
2732 struct ice_aqc_get_vsi_resp get_vsi_resp;
2733 struct ice_aqc_download_pkg download_pkg;
2734 struct ice_aqc_get_pkg_info_list get_pkg_info_list;
2735 struct ice_aqc_driver_shared_params drv_shared_params;
2736 struct ice_aqc_set_mac_lb set_mac_lb;
2737 struct ice_aqc_alloc_free_res_cmd sw_res_ctrl;
2738 struct ice_aqc_get_res_alloc get_res;
2739 struct ice_aqc_get_allocd_res_desc get_res_desc;
2740 struct ice_aqc_set_mac_cfg set_mac_cfg;
2741 struct ice_aqc_set_event_mask set_event_mask;
2742 struct ice_aqc_get_link_status get_link_status;
2743 struct ice_aqc_event_lan_overflow lan_overflow;
2744 struct ice_aqc_get_link_topo get_link_topo;
2745 struct ice_aqc_set_health_status_config
2746 set_health_status_config;
2747 struct ice_aqc_get_supported_health_status_codes
2748 get_supported_health_status_codes;
2749 struct ice_aqc_get_health_status get_health_status;
2750 struct ice_aqc_clear_health_status clear_health_status;
2754 /* FW defined boundary for a large buffer, 4k >= Large buffer > 512 bytes */
2755 #define ICE_AQ_LG_BUF 512
2757 /* Flags sub-structure
2758 * |0 |1 |2 |3 |4 |5 |6 |7 |8 |9 |10 |11 |12 |13 |14 |15 |
2759 * |DD |CMP|ERR|VFE| * * RESERVED * * |LB |RD |VFC|BUF|SI |EI |FE |
2762 /* command flags and offsets */
2763 #define ICE_AQ_FLAG_DD_S 0
2764 #define ICE_AQ_FLAG_CMP_S 1
2765 #define ICE_AQ_FLAG_ERR_S 2
2766 #define ICE_AQ_FLAG_VFE_S 3
2767 #define ICE_AQ_FLAG_LB_S 9
2768 #define ICE_AQ_FLAG_RD_S 10
2769 #define ICE_AQ_FLAG_VFC_S 11
2770 #define ICE_AQ_FLAG_BUF_S 12
2771 #define ICE_AQ_FLAG_SI_S 13
2772 #define ICE_AQ_FLAG_EI_S 14
2773 #define ICE_AQ_FLAG_FE_S 15
2775 #define ICE_AQ_FLAG_DD BIT(ICE_AQ_FLAG_DD_S) /* 0x1 */
2776 #define ICE_AQ_FLAG_CMP BIT(ICE_AQ_FLAG_CMP_S) /* 0x2 */
2777 #define ICE_AQ_FLAG_ERR BIT(ICE_AQ_FLAG_ERR_S) /* 0x4 */
2778 #define ICE_AQ_FLAG_VFE BIT(ICE_AQ_FLAG_VFE_S) /* 0x8 */
2779 #define ICE_AQ_FLAG_LB BIT(ICE_AQ_FLAG_LB_S) /* 0x200 */
2780 #define ICE_AQ_FLAG_RD BIT(ICE_AQ_FLAG_RD_S) /* 0x400 */
2781 #define ICE_AQ_FLAG_VFC BIT(ICE_AQ_FLAG_VFC_S) /* 0x800 */
2782 #define ICE_AQ_FLAG_BUF BIT(ICE_AQ_FLAG_BUF_S) /* 0x1000 */
2783 #define ICE_AQ_FLAG_SI BIT(ICE_AQ_FLAG_SI_S) /* 0x2000 */
2784 #define ICE_AQ_FLAG_EI BIT(ICE_AQ_FLAG_EI_S) /* 0x4000 */
2785 #define ICE_AQ_FLAG_FE BIT(ICE_AQ_FLAG_FE_S) /* 0x8000 */
2789 ICE_AQ_RC_OK = 0, /* Success */
2790 ICE_AQ_RC_EPERM = 1, /* Operation not permitted */
2791 ICE_AQ_RC_ENOENT = 2, /* No such element */
2792 ICE_AQ_RC_ESRCH = 3, /* Bad opcode */
2793 ICE_AQ_RC_EINTR = 4, /* Operation interrupted */
2794 ICE_AQ_RC_EIO = 5, /* I/O error */
2795 ICE_AQ_RC_ENXIO = 6, /* No such resource */
2796 ICE_AQ_RC_E2BIG = 7, /* Arg too long */
2797 ICE_AQ_RC_EAGAIN = 8, /* Try again */
2798 ICE_AQ_RC_ENOMEM = 9, /* Out of memory */
2799 ICE_AQ_RC_EACCES = 10, /* Permission denied */
2800 ICE_AQ_RC_EFAULT = 11, /* Bad address */
2801 ICE_AQ_RC_EBUSY = 12, /* Device or resource busy */
2802 ICE_AQ_RC_EEXIST = 13, /* Object already exists */
2803 ICE_AQ_RC_EINVAL = 14, /* Invalid argument */
2804 ICE_AQ_RC_ENOTTY = 15, /* Not a typewriter */
2805 ICE_AQ_RC_ENOSPC = 16, /* No space left or allocation failure */
2806 ICE_AQ_RC_ENOSYS = 17, /* Function not implemented */
2807 ICE_AQ_RC_ERANGE = 18, /* Parameter out of range */
2808 ICE_AQ_RC_EFLUSHED = 19, /* Cmd flushed due to prev cmd error */
2809 ICE_AQ_RC_BAD_ADDR = 20, /* Descriptor contains a bad pointer */
2810 ICE_AQ_RC_EMODE = 21, /* Op not allowed in current dev mode */
2811 ICE_AQ_RC_EFBIG = 22, /* File too big */
2812 ICE_AQ_RC_ESBCOMP = 23, /* SB-IOSF completion unsuccessful */
2813 ICE_AQ_RC_ENOSEC = 24, /* Missing security manifest */
2814 ICE_AQ_RC_EBADSIG = 25, /* Bad RSA signature */
2815 ICE_AQ_RC_ESVN = 26, /* SVN number prohibits this package */
2816 ICE_AQ_RC_EBADMAN = 27, /* Manifest hash mismatch */
2817 ICE_AQ_RC_EBADBUF = 28, /* Buffer hash mismatches manifest */
2818 ICE_AQ_RC_EACCES_BMCU = 29, /* BMC Update in progress */
2821 /* Admin Queue command opcodes */
2822 enum ice_adminq_opc {
2824 ice_aqc_opc_get_ver = 0x0001,
2825 ice_aqc_opc_driver_ver = 0x0002,
2826 ice_aqc_opc_q_shutdown = 0x0003,
2827 ice_aqc_opc_get_exp_err = 0x0005,
2829 /* resource ownership */
2830 ice_aqc_opc_req_res = 0x0008,
2831 ice_aqc_opc_release_res = 0x0009,
2833 /* device/function capabilities */
2834 ice_aqc_opc_list_func_caps = 0x000A,
2835 ice_aqc_opc_list_dev_caps = 0x000B,
2837 /* manage MAC address */
2838 ice_aqc_opc_manage_mac_read = 0x0107,
2839 ice_aqc_opc_manage_mac_write = 0x0108,
2842 ice_aqc_opc_clear_pxe_mode = 0x0110,
2844 ice_aqc_opc_config_no_drop_policy = 0x0112,
2846 /* internal switch commands */
2847 ice_aqc_opc_get_sw_cfg = 0x0200,
2849 /* Alloc/Free/Get Resources */
2850 ice_aqc_opc_get_res_alloc = 0x0204,
2851 ice_aqc_opc_alloc_res = 0x0208,
2852 ice_aqc_opc_free_res = 0x0209,
2853 ice_aqc_opc_get_allocd_res_desc = 0x020A,
2856 ice_aqc_opc_add_vsi = 0x0210,
2857 ice_aqc_opc_update_vsi = 0x0211,
2858 ice_aqc_opc_get_vsi_params = 0x0212,
2859 ice_aqc_opc_free_vsi = 0x0213,
2861 /* Mirroring rules - add/update, delete */
2862 ice_aqc_opc_add_update_mir_rule = 0x0260,
2863 ice_aqc_opc_del_mir_rule = 0x0261,
2865 /* storm configuration */
2866 ice_aqc_opc_set_storm_cfg = 0x0280,
2867 ice_aqc_opc_get_storm_cfg = 0x0281,
2869 /* recipe commands */
2870 ice_aqc_opc_add_recipe = 0x0290,
2871 ice_aqc_opc_recipe_to_profile = 0x0291,
2872 ice_aqc_opc_get_recipe = 0x0292,
2873 ice_aqc_opc_get_recipe_to_profile = 0x0293,
2875 /* switch rules population commands */
2876 ice_aqc_opc_add_sw_rules = 0x02A0,
2877 ice_aqc_opc_update_sw_rules = 0x02A1,
2878 ice_aqc_opc_remove_sw_rules = 0x02A2,
2879 ice_aqc_opc_get_sw_rules = 0x02A3,
2880 ice_aqc_opc_clear_pf_cfg = 0x02A4,
2883 ice_aqc_opc_pfc_ignore = 0x0301,
2884 ice_aqc_opc_query_pfc_mode = 0x0302,
2885 ice_aqc_opc_set_pfc_mode = 0x0303,
2886 ice_aqc_opc_set_dcb_params = 0x0306,
2888 /* transmit scheduler commands */
2889 ice_aqc_opc_get_dflt_topo = 0x0400,
2890 ice_aqc_opc_add_sched_elems = 0x0401,
2891 ice_aqc_opc_cfg_sched_elems = 0x0403,
2892 ice_aqc_opc_get_sched_elems = 0x0404,
2893 ice_aqc_opc_move_sched_elems = 0x0408,
2894 ice_aqc_opc_suspend_sched_elems = 0x0409,
2895 ice_aqc_opc_resume_sched_elems = 0x040A,
2896 ice_aqc_opc_query_port_ets = 0x040E,
2897 ice_aqc_opc_delete_sched_elems = 0x040F,
2898 ice_aqc_opc_add_rl_profiles = 0x0410,
2899 ice_aqc_opc_query_rl_profiles = 0x0411,
2900 ice_aqc_opc_query_sched_res = 0x0412,
2901 ice_aqc_opc_query_node_to_root = 0x0413,
2902 ice_aqc_opc_cfg_l2_node_cgd = 0x0414,
2903 ice_aqc_opc_remove_rl_profiles = 0x0415,
2906 ice_aqc_opc_get_phy_caps = 0x0600,
2907 ice_aqc_opc_set_phy_cfg = 0x0601,
2908 ice_aqc_opc_set_mac_cfg = 0x0603,
2909 ice_aqc_opc_restart_an = 0x0605,
2910 ice_aqc_opc_get_link_status = 0x0607,
2911 ice_aqc_opc_set_event_mask = 0x0613,
2912 ice_aqc_opc_set_mac_lb = 0x0620,
2913 ice_aqc_opc_get_link_topo = 0x06E0,
2914 ice_aqc_opc_set_port_id_led = 0x06E9,
2915 ice_aqc_opc_get_port_options = 0x06EA,
2916 ice_aqc_opc_set_port_option = 0x06EB,
2917 ice_aqc_opc_set_gpio = 0x06EC,
2918 ice_aqc_opc_get_gpio = 0x06ED,
2919 ice_aqc_opc_sff_eeprom = 0x06EE,
2922 ice_aqc_opc_nvm_read = 0x0701,
2923 ice_aqc_opc_nvm_erase = 0x0702,
2924 ice_aqc_opc_nvm_write = 0x0703,
2925 ice_aqc_opc_nvm_cfg_read = 0x0704,
2926 ice_aqc_opc_nvm_cfg_write = 0x0705,
2927 ice_aqc_opc_nvm_checksum = 0x0706,
2928 ice_aqc_opc_nvm_write_activate = 0x0707,
2929 ice_aqc_opc_nvm_sr_dump = 0x0707,
2930 ice_aqc_opc_nvm_save_factory_settings = 0x0708,
2931 ice_aqc_opc_nvm_update_empr = 0x0709,
2934 ice_aqc_opc_lldp_get_mib = 0x0A00,
2935 ice_aqc_opc_lldp_set_mib_change = 0x0A01,
2936 ice_aqc_opc_lldp_add_tlv = 0x0A02,
2937 ice_aqc_opc_lldp_update_tlv = 0x0A03,
2938 ice_aqc_opc_lldp_delete_tlv = 0x0A04,
2939 ice_aqc_opc_lldp_stop = 0x0A05,
2940 ice_aqc_opc_lldp_start = 0x0A06,
2941 ice_aqc_opc_get_cee_dcb_cfg = 0x0A07,
2942 ice_aqc_opc_lldp_set_local_mib = 0x0A08,
2943 ice_aqc_opc_lldp_stop_start_specific_agent = 0x0A09,
2944 ice_aqc_opc_lldp_filter_ctrl = 0x0A0A,
2947 ice_aqc_opc_set_rss_key = 0x0B02,
2948 ice_aqc_opc_set_rss_lut = 0x0B03,
2949 ice_aqc_opc_get_rss_key = 0x0B04,
2950 ice_aqc_opc_get_rss_lut = 0x0B05,
2951 ice_aqc_opc_clear_fd_table = 0x0B06,
2953 ice_aqc_opc_alloc_acl_tbl = 0x0C10,
2954 ice_aqc_opc_dealloc_acl_tbl = 0x0C11,
2955 ice_aqc_opc_alloc_acl_actpair = 0x0C12,
2956 ice_aqc_opc_dealloc_acl_actpair = 0x0C13,
2957 ice_aqc_opc_alloc_acl_scen = 0x0C14,
2958 ice_aqc_opc_dealloc_acl_scen = 0x0C15,
2959 ice_aqc_opc_alloc_acl_counters = 0x0C16,
2960 ice_aqc_opc_dealloc_acl_counters = 0x0C17,
2961 ice_aqc_opc_dealloc_acl_res = 0x0C1A,
2962 ice_aqc_opc_update_acl_scen = 0x0C1B,
2963 ice_aqc_opc_program_acl_actpair = 0x0C1C,
2964 ice_aqc_opc_program_acl_prof_extraction = 0x0C1D,
2965 ice_aqc_opc_program_acl_prof_ranges = 0x0C1E,
2966 ice_aqc_opc_program_acl_entry = 0x0C20,
2967 ice_aqc_opc_query_acl_prof = 0x0C21,
2968 ice_aqc_opc_query_acl_prof_ranges = 0x0C22,
2969 ice_aqc_opc_query_acl_scen = 0x0C23,
2970 ice_aqc_opc_query_acl_entry = 0x0C24,
2971 ice_aqc_opc_query_acl_actpair = 0x0C25,
2972 ice_aqc_opc_query_acl_counter = 0x0C27,
2974 /* Tx queue handling commands/events */
2975 ice_aqc_opc_add_txqs = 0x0C30,
2976 ice_aqc_opc_dis_txqs = 0x0C31,
2977 ice_aqc_opc_txqs_cleanup = 0x0C31,
2978 ice_aqc_opc_move_recfg_txqs = 0x0C32,
2980 /* package commands */
2981 ice_aqc_opc_download_pkg = 0x0C40,
2982 ice_aqc_opc_upload_section = 0x0C41,
2983 ice_aqc_opc_update_pkg = 0x0C42,
2984 ice_aqc_opc_get_pkg_info_list = 0x0C43,
2986 ice_aqc_opc_driver_shared_params = 0x0C90,
2988 /* Standalone Commands/Events */
2989 ice_aqc_opc_event_lan_overflow = 0x1001,
2991 /* SystemDiagnostic commands */
2992 ice_aqc_opc_set_health_status_config = 0xFF20,
2993 ice_aqc_opc_get_supported_health_status_codes = 0xFF21,
2994 ice_aqc_opc_get_health_status = 0xFF22,
2995 ice_aqc_opc_clear_health_status = 0xFF23
2998 #endif /* _ICE_ADMINQ_CMD_H_ */