1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2001-2021 Intel Corporation
5 #ifndef _ICE_ADMINQ_CMD_H_
6 #define _ICE_ADMINQ_CMD_H_
8 /* This header file defines the Admin Queue commands, error codes and
9 * descriptor format. It is shared between Firmware and Software.
12 #define ICE_MAX_VSI 768
13 #define ICE_AQC_TOPO_MAX_LEVEL_NUM 0x9
14 #define ICE_AQ_SET_MAC_FRAME_SIZE_MAX 9728
16 struct ice_aqc_generic {
23 /* Get version (direct 0x0001) */
24 struct ice_aqc_get_ver {
37 /* Send driver version (indirect 0x0002) */
38 struct ice_aqc_driver_ver {
48 /* Queue Shutdown (direct 0x0003) */
49 struct ice_aqc_q_shutdown {
51 #define ICE_AQC_DRIVER_UNLOADING BIT(0)
55 /* Request resource ownership (direct 0x0008)
56 * Release resource ownership (direct 0x0009)
58 struct ice_aqc_req_res {
60 #define ICE_AQC_RES_ID_NVM 1
61 #define ICE_AQC_RES_ID_SDP 2
62 #define ICE_AQC_RES_ID_CHNG_LOCK 3
63 #define ICE_AQC_RES_ID_GLBL_LOCK 4
65 #define ICE_AQC_RES_ACCESS_READ 1
66 #define ICE_AQC_RES_ACCESS_WRITE 2
68 /* Upon successful completion, FW writes this value and driver is
69 * expected to release resource before timeout. This value is provided
73 #define ICE_AQ_RES_NVM_READ_DFLT_TIMEOUT_MS 3000
74 #define ICE_AQ_RES_NVM_WRITE_DFLT_TIMEOUT_MS 180000
75 #define ICE_AQ_RES_CHNG_LOCK_DFLT_TIMEOUT_MS 1000
76 #define ICE_AQ_RES_GLBL_LOCK_DFLT_TIMEOUT_MS 3000
77 /* For SDP: pin ID of the SDP */
79 /* Status is only used for ICE_AQC_RES_ID_GLBL_LOCK */
81 #define ICE_AQ_RES_GLBL_SUCCESS 0
82 #define ICE_AQ_RES_GLBL_IN_PROG 1
83 #define ICE_AQ_RES_GLBL_DONE 2
87 /* Get function capabilities (indirect 0x000A)
88 * Get device capabilities (indirect 0x000B)
90 struct ice_aqc_list_caps {
99 /* Device/Function buffer entry, repeated per reported capability */
100 struct ice_aqc_list_caps_elem {
102 #define ICE_AQC_CAPS_VALID_FUNCTIONS 0x0005
103 #define ICE_AQC_MAX_VALID_FUNCTIONS 0x8
104 #define ICE_AQC_CAPS_VSI 0x0017
105 #define ICE_AQC_CAPS_DCB 0x0018
106 #define ICE_AQC_CAPS_RSS 0x0040
107 #define ICE_AQC_CAPS_RXQS 0x0041
108 #define ICE_AQC_CAPS_TXQS 0x0042
109 #define ICE_AQC_CAPS_MSIX 0x0043
110 #define ICE_AQC_CAPS_FD 0x0045
111 #define ICE_AQC_CAPS_MAX_MTU 0x0047
112 #define ICE_AQC_CAPS_IWARP 0x0051
113 #define ICE_AQC_CAPS_PCIE_RESET_AVOIDANCE 0x0076
114 #define ICE_AQC_CAPS_NVM_MGMT 0x0080
118 /* Number of resources described by this capability */
120 /* Only meaningful for some types of resources */
122 /* Only meaningful for some types of resources */
128 /* Manage MAC address, read command - indirect (0x0107)
129 * This struct is also used for the response
131 struct ice_aqc_manage_mac_read {
132 __le16 flags; /* Zeroed by device driver */
133 #define ICE_AQC_MAN_MAC_LAN_ADDR_VALID BIT(4)
134 #define ICE_AQC_MAN_MAC_SAN_ADDR_VALID BIT(5)
135 #define ICE_AQC_MAN_MAC_PORT_ADDR_VALID BIT(6)
136 #define ICE_AQC_MAN_MAC_WOL_ADDR_VALID BIT(7)
137 #define ICE_AQC_MAN_MAC_MC_MAG_EN BIT(8)
138 #define ICE_AQC_MAN_MAC_WOL_PRESERVE_ON_PFR BIT(9)
139 #define ICE_AQC_MAN_MAC_READ_S 4
140 #define ICE_AQC_MAN_MAC_READ_M (0xF << ICE_AQC_MAN_MAC_READ_S)
142 u8 num_addr; /* Used in response */
148 /* Response buffer format for manage MAC read command */
149 struct ice_aqc_manage_mac_read_resp {
152 #define ICE_AQC_MAN_MAC_ADDR_TYPE_LAN 0
153 #define ICE_AQC_MAN_MAC_ADDR_TYPE_WOL 1
154 u8 mac_addr[ETH_ALEN];
157 /* Manage MAC address, write command - direct (0x0108) */
158 struct ice_aqc_manage_mac_write {
161 #define ICE_AQC_MAN_MAC_WR_MC_MAG_EN BIT(0)
162 #define ICE_AQC_MAN_MAC_WR_WOL_LAA_PFR_KEEP BIT(1)
163 #define ICE_AQC_MAN_MAC_WR_S 6
164 #define ICE_AQC_MAN_MAC_WR_M MAKEMASK(3, ICE_AQC_MAN_MAC_WR_S)
165 #define ICE_AQC_MAN_MAC_UPDATE_LAA 0
166 #define ICE_AQC_MAN_MAC_UPDATE_LAA_WOL BIT(ICE_AQC_MAN_MAC_WR_S)
167 /* byte stream in network order */
168 u8 mac_addr[ETH_ALEN];
173 /* Clear PXE Command and response (direct 0x0110) */
174 struct ice_aqc_clear_pxe {
176 #define ICE_AQC_CLEAR_PXE_RX_CNT 0x2
180 /* Configure No-Drop Policy Command (direct 0x0112) */
181 struct ice_aqc_config_no_drop_policy {
183 #define ICE_AQC_FORCE_NO_DROP BIT(0)
187 /* Get switch configuration (0x0200) */
188 struct ice_aqc_get_sw_cfg {
189 /* Reserved for command and copy of request flags for response */
191 /* First desc in case of command and next_elem in case of response
192 * In case of response, if it is not zero, means all the configuration
193 * was not returned and new command shall be sent with this value in
194 * the 'first desc' field
197 /* Reserved for command, only used for response */
204 /* Each entry in the response buffer is of the following type: */
205 struct ice_aqc_get_sw_cfg_resp_elem {
206 /* VSI/Port Number */
208 #define ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_S 0
209 #define ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_M \
210 (0x3FF << ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_S)
211 #define ICE_AQC_GET_SW_CONF_RESP_TYPE_S 14
212 #define ICE_AQC_GET_SW_CONF_RESP_TYPE_M (0x3 << ICE_AQC_GET_SW_CONF_RESP_TYPE_S)
213 #define ICE_AQC_GET_SW_CONF_RESP_PHYS_PORT 0
214 #define ICE_AQC_GET_SW_CONF_RESP_VIRT_PORT 1
215 #define ICE_AQC_GET_SW_CONF_RESP_VSI 2
217 /* SWID VSI/Port belongs to */
220 /* Bit 14..0 : PF/VF number VSI belongs to
221 * Bit 15 : VF indication bit
224 #define ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_S 0
225 #define ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_M \
226 (0x7FFF << ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_S)
227 #define ICE_AQC_GET_SW_CONF_RESP_IS_VF BIT(15)
230 /* Set Port parameters, (direct, 0x0203) */
231 struct ice_aqc_set_port_params {
233 #define ICE_AQC_SET_P_PARAMS_SAVE_BAD_PACKETS BIT(0)
234 #define ICE_AQC_SET_P_PARAMS_PAD_SHORT_PACKETS BIT(1)
235 #define ICE_AQC_SET_P_PARAMS_DOUBLE_VLAN_ENA BIT(2)
236 __le16 bad_frame_vsi;
237 #define ICE_AQC_SET_P_PARAMS_VSI_S 0
238 #define ICE_AQC_SET_P_PARAMS_VSI_M (0x3FF << ICE_AQC_SET_P_PARAMS_VSI_S)
239 #define ICE_AQC_SET_P_PARAMS_VSI_VALID BIT(15)
241 #define ICE_AQC_SET_P_PARAMS_SWID_S 0
242 #define ICE_AQC_SET_P_PARAMS_SWID_M (0xFF << ICE_AQC_SET_P_PARAMS_SWID_S)
243 #define ICE_AQC_SET_P_PARAMS_LOGI_PORT_ID_S 8
244 #define ICE_AQC_SET_P_PARAMS_LOGI_PORT_ID_M \
245 (0x3F << ICE_AQC_SET_P_PARAMS_LOGI_PORT_ID_S)
246 #define ICE_AQC_SET_P_PARAMS_IS_LOGI_PORT BIT(14)
247 #define ICE_AQC_SET_P_PARAMS_SWID_VALID BIT(15)
251 /* These resource type defines are used for all switch resource
252 * commands where a resource type is required, such as:
253 * Get Resource Allocation command (indirect 0x0204)
254 * Allocate Resources command (indirect 0x0208)
255 * Free Resources command (indirect 0x0209)
256 * Get Allocated Resource Descriptors Command (indirect 0x020A)
258 #define ICE_AQC_RES_TYPE_VEB_COUNTER 0x00
259 #define ICE_AQC_RES_TYPE_VLAN_COUNTER 0x01
260 #define ICE_AQC_RES_TYPE_MIRROR_RULE 0x02
261 #define ICE_AQC_RES_TYPE_VSI_LIST_REP 0x03
262 #define ICE_AQC_RES_TYPE_VSI_LIST_PRUNE 0x04
263 #define ICE_AQC_RES_TYPE_RECIPE 0x05
264 #define ICE_AQC_RES_TYPE_PROFILE 0x06
265 #define ICE_AQC_RES_TYPE_SWID 0x07
266 #define ICE_AQC_RES_TYPE_VSI 0x08
267 #define ICE_AQC_RES_TYPE_FLU 0x09
268 #define ICE_AQC_RES_TYPE_WIDE_TABLE_1 0x0A
269 #define ICE_AQC_RES_TYPE_WIDE_TABLE_2 0x0B
270 #define ICE_AQC_RES_TYPE_WIDE_TABLE_4 0x0C
271 #define ICE_AQC_RES_TYPE_GLOBAL_RSS_HASH 0x20
272 #define ICE_AQC_RES_TYPE_FDIR_COUNTER_BLOCK 0x21
273 #define ICE_AQC_RES_TYPE_FDIR_GUARANTEED_ENTRIES 0x22
274 #define ICE_AQC_RES_TYPE_FDIR_SHARED_ENTRIES 0x23
275 #define ICE_AQC_RES_TYPE_FLEX_DESC_PROG 0x30
276 #define ICE_AQC_RES_TYPE_SWITCH_PROF_BLDR_PROFID 0x48
277 #define ICE_AQC_RES_TYPE_SWITCH_PROF_BLDR_TCAM 0x49
278 #define ICE_AQC_RES_TYPE_ACL_PROF_BLDR_PROFID 0x50
279 #define ICE_AQC_RES_TYPE_ACL_PROF_BLDR_TCAM 0x51
280 #define ICE_AQC_RES_TYPE_FD_PROF_BLDR_PROFID 0x58
281 #define ICE_AQC_RES_TYPE_FD_PROF_BLDR_TCAM 0x59
282 #define ICE_AQC_RES_TYPE_HASH_PROF_BLDR_PROFID 0x60
283 #define ICE_AQC_RES_TYPE_HASH_PROF_BLDR_TCAM 0x61
284 /* Resource types 0x62-67 are reserved for Hash profile builder */
285 #define ICE_AQC_RES_TYPE_QHASH_PROF_BLDR_PROFID 0x68
286 #define ICE_AQC_RES_TYPE_QHASH_PROF_BLDR_TCAM 0x69
288 #define ICE_AQC_RES_TYPE_FLAG_SHARED BIT(7)
289 #define ICE_AQC_RES_TYPE_FLAG_SCAN_BOTTOM BIT(12)
290 #define ICE_AQC_RES_TYPE_FLAG_IGNORE_INDEX BIT(13)
292 #define ICE_AQC_RES_TYPE_FLAG_DEDICATED 0x00
294 #define ICE_AQC_RES_TYPE_S 0
295 #define ICE_AQC_RES_TYPE_M (0x07F << ICE_AQC_RES_TYPE_S)
297 /* Get Resource Allocation command (indirect 0x0204) */
298 struct ice_aqc_get_res_alloc {
299 __le16 resp_elem_num; /* Used in response, reserved in command */
305 /* Get Resource Allocation Response Buffer per response */
306 struct ice_aqc_get_res_resp_elem {
307 __le16 res_type; /* Types defined above cmd 0x0204 */
308 __le16 total_capacity; /* Resources available to all PF's */
309 __le16 total_function; /* Resources allocated for a PF */
310 __le16 total_shared; /* Resources allocated as shared */
311 __le16 total_free; /* Resources un-allocated/not reserved by any PF */
314 /* Allocate Resources command (indirect 0x0208)
315 * Free Resources command (indirect 0x0209)
317 struct ice_aqc_alloc_free_res_cmd {
318 __le16 num_entries; /* Number of Resource entries */
324 /* Resource descriptor */
325 struct ice_aqc_res_elem {
332 /* Buffer for Allocate/Free Resources commands */
333 struct ice_aqc_alloc_free_res_elem {
334 __le16 res_type; /* Types defined above cmd 0x0204 */
335 #define ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_S 8
336 #define ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_M \
337 (0xF << ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_S)
339 struct ice_aqc_res_elem elem[STRUCT_HACK_VAR_LEN];
342 /* Get Allocated Resource Descriptors Command (indirect 0x020A) */
343 struct ice_aqc_get_allocd_res_desc {
346 __le16 res; /* Types defined above cmd 0x0204 */
361 /* Request buffer for Set VLAN Mode AQ command (indirect 0x020C) */
362 struct ice_aqc_set_vlan_mode {
364 u8 l2tag_prio_tagging;
365 #define ICE_AQ_VLAN_PRIO_TAG_S 0
366 #define ICE_AQ_VLAN_PRIO_TAG_M (0x7 << ICE_AQ_VLAN_PRIO_TAG_S)
367 #define ICE_AQ_VLAN_PRIO_TAG_NOT_SUPPORTED 0x0
368 #define ICE_AQ_VLAN_PRIO_TAG_STAG 0x1
369 #define ICE_AQ_VLAN_PRIO_TAG_OUTER_CTAG 0x2
370 #define ICE_AQ_VLAN_PRIO_TAG_OUTER_VLAN 0x3
371 #define ICE_AQ_VLAN_PRIO_TAG_INNER_CTAG 0x4
372 #define ICE_AQ_VLAN_PRIO_TAG_MAX 0x4
373 #define ICE_AQ_VLAN_PRIO_TAG_ERROR 0x7
374 u8 l2tag_reserved[64];
376 #define ICE_AQ_VLAN_RDMA_TAG_S 0
377 #define ICE_AQ_VLAN_RDMA_TAG_M (0x3F << ICE_AQ_VLAN_RDMA_TAG_S)
378 #define ICE_AQ_SVM_VLAN_RDMA_PKT_FLAG_SETTING 0x10
379 #define ICE_AQ_DVM_VLAN_RDMA_PKT_FLAG_SETTING 0x1A
382 #define ICE_AQ_VLAN_MNG_PROTOCOL_ID_OUTER 0x10
383 #define ICE_AQ_VLAN_MNG_PROTOCOL_ID_INNER 0x11
384 u8 prot_id_reserved[30];
387 /* Response buffer for Get VLAN Mode AQ command (indirect 0x020D) */
388 struct ice_aqc_get_vlan_mode {
390 #define ICE_AQ_VLAN_MODE_DVM_ENA BIT(0)
391 u8 l2tag_prio_tagging;
395 /* Add VSI (indirect 0x0210)
396 * Update VSI (indirect 0x0211)
397 * Get VSI (indirect 0x0212)
398 * Free VSI (indirect 0x0213)
400 struct ice_aqc_add_get_update_free_vsi {
402 #define ICE_AQ_VSI_NUM_S 0
403 #define ICE_AQ_VSI_NUM_M (0x03FF << ICE_AQ_VSI_NUM_S)
404 #define ICE_AQ_VSI_IS_VALID BIT(15)
406 #define ICE_AQ_VSI_KEEP_ALLOC 0x1
410 #define ICE_AQ_VSI_TYPE_S 0
411 #define ICE_AQ_VSI_TYPE_M (0x3 << ICE_AQ_VSI_TYPE_S)
412 #define ICE_AQ_VSI_TYPE_VF 0x0
413 #define ICE_AQ_VSI_TYPE_VMDQ2 0x1
414 #define ICE_AQ_VSI_TYPE_PF 0x2
415 #define ICE_AQ_VSI_TYPE_EMP_MNG 0x3
420 /* Response descriptor for:
421 * Add VSI (indirect 0x0210)
422 * Update VSI (indirect 0x0211)
423 * Free VSI (indirect 0x0213)
425 struct ice_aqc_add_update_free_vsi_resp {
434 struct ice_aqc_get_vsi_resp {
437 /* The vsi_flags field uses the ICE_AQ_VSI_TYPE_* defines for values.
438 * These are found above in struct ice_aqc_add_get_update_free_vsi.
447 struct ice_aqc_vsi_props {
448 __le16 valid_sections;
449 #define ICE_AQ_VSI_PROP_SW_VALID BIT(0)
450 #define ICE_AQ_VSI_PROP_SECURITY_VALID BIT(1)
451 #define ICE_AQ_VSI_PROP_VLAN_VALID BIT(2)
452 #define ICE_AQ_VSI_PROP_OUTER_TAG_VALID BIT(3)
453 #define ICE_AQ_VSI_PROP_INGRESS_UP_VALID BIT(4)
454 #define ICE_AQ_VSI_PROP_EGRESS_UP_VALID BIT(5)
455 #define ICE_AQ_VSI_PROP_RXQ_MAP_VALID BIT(6)
456 #define ICE_AQ_VSI_PROP_Q_OPT_VALID BIT(7)
457 #define ICE_AQ_VSI_PROP_OUTER_UP_VALID BIT(8)
458 #define ICE_AQ_VSI_PROP_ACL_VALID BIT(10)
459 #define ICE_AQ_VSI_PROP_FLOW_DIR_VALID BIT(11)
460 #define ICE_AQ_VSI_PROP_PASID_VALID BIT(12)
464 #define ICE_AQ_VSI_SW_FLAG_ALLOW_LB BIT(5)
465 #define ICE_AQ_VSI_SW_FLAG_LOCAL_LB BIT(6)
466 #define ICE_AQ_VSI_SW_FLAG_SRC_PRUNE BIT(7)
468 #define ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_S 0
469 #define ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_M (0xF << ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_S)
470 #define ICE_AQ_VSI_SW_FLAG_RX_VLAN_PRUNE_ENA BIT(0)
471 #define ICE_AQ_VSI_SW_FLAG_LAN_ENA BIT(4)
473 #define ICE_AQ_VSI_SW_VEB_STAT_ID_S 0
474 #define ICE_AQ_VSI_SW_VEB_STAT_ID_M (0x1F << ICE_AQ_VSI_SW_VEB_STAT_ID_S)
475 #define ICE_AQ_VSI_SW_VEB_STAT_ID_VALID BIT(5)
476 /* security section */
478 #define ICE_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD BIT(0)
479 #define ICE_AQ_VSI_SEC_FLAG_ENA_MAC_ANTI_SPOOF BIT(2)
480 #define ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S 4
481 #define ICE_AQ_VSI_SEC_TX_PRUNE_ENA_M (0xF << ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S)
482 #define ICE_AQ_VSI_SEC_TX_VLAN_PRUNE_ENA BIT(0)
485 __le16 port_based_inner_vlan; /* VLANS include priority bits */
486 u8 inner_vlan_reserved[2];
488 #define ICE_AQ_VSI_INNER_VLAN_TX_MODE_S 0
489 #define ICE_AQ_VSI_INNER_VLAN_TX_MODE_M (0x3 << ICE_AQ_VSI_INNER_VLAN_TX_MODE_S)
490 #define ICE_AQ_VSI_INNER_VLAN_TX_MODE_ACCEPTUNTAGGED 0x1
491 #define ICE_AQ_VSI_INNER_VLAN_TX_MODE_ACCEPTTAGGED 0x2
492 #define ICE_AQ_VSI_INNER_VLAN_TX_MODE_ALL 0x3
493 #define ICE_AQ_VSI_INNER_VLAN_INSERT_PVID BIT(2)
494 #define ICE_AQ_VSI_INNER_VLAN_EMODE_S 3
495 #define ICE_AQ_VSI_INNER_VLAN_EMODE_M (0x3 << ICE_AQ_VSI_INNER_VLAN_EMODE_S)
496 #define ICE_AQ_VSI_INNER_VLAN_EMODE_STR_BOTH (0x0 << ICE_AQ_VSI_INNER_VLAN_EMODE_S)
497 #define ICE_AQ_VSI_INNER_VLAN_EMODE_STR_UP (0x1 << ICE_AQ_VSI_INNER_VLAN_EMODE_S)
498 #define ICE_AQ_VSI_INNER_VLAN_EMODE_STR (0x2 << ICE_AQ_VSI_INNER_VLAN_EMODE_S)
499 #define ICE_AQ_VSI_INNER_VLAN_EMODE_NOTHING (0x3 << ICE_AQ_VSI_INNER_VLAN_EMODE_S)
500 #define ICE_AQ_VSI_INNER_VLAN_BLOCK_TX_DESC BIT(5)
501 u8 inner_vlan_reserved2[3];
502 /* ingress egress up sections */
503 __le32 ingress_table; /* bitmap, 3 bits per up */
504 #define ICE_AQ_VSI_UP_TABLE_UP0_S 0
505 #define ICE_AQ_VSI_UP_TABLE_UP0_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP0_S)
506 #define ICE_AQ_VSI_UP_TABLE_UP1_S 3
507 #define ICE_AQ_VSI_UP_TABLE_UP1_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP1_S)
508 #define ICE_AQ_VSI_UP_TABLE_UP2_S 6
509 #define ICE_AQ_VSI_UP_TABLE_UP2_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP2_S)
510 #define ICE_AQ_VSI_UP_TABLE_UP3_S 9
511 #define ICE_AQ_VSI_UP_TABLE_UP3_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP3_S)
512 #define ICE_AQ_VSI_UP_TABLE_UP4_S 12
513 #define ICE_AQ_VSI_UP_TABLE_UP4_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP4_S)
514 #define ICE_AQ_VSI_UP_TABLE_UP5_S 15
515 #define ICE_AQ_VSI_UP_TABLE_UP5_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP5_S)
516 #define ICE_AQ_VSI_UP_TABLE_UP6_S 18
517 #define ICE_AQ_VSI_UP_TABLE_UP6_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP6_S)
518 #define ICE_AQ_VSI_UP_TABLE_UP7_S 21
519 #define ICE_AQ_VSI_UP_TABLE_UP7_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP7_S)
520 __le32 egress_table; /* same defines as for ingress table */
521 /* outer tags section */
522 __le16 port_based_outer_vlan;
524 #define ICE_AQ_VSI_OUTER_VLAN_EMODE_S 0
525 #define ICE_AQ_VSI_OUTER_VLAN_EMODE_M (0x3 << ICE_AQ_VSI_OUTER_VLAN_EMODE_S)
526 #define ICE_AQ_VSI_OUTER_VLAN_EMODE_SHOW_BOTH 0x0
527 #define ICE_AQ_VSI_OUTER_VLAN_EMODE_SHOW_UP 0x1
528 #define ICE_AQ_VSI_OUTER_VLAN_EMODE_SHOW 0x2
529 #define ICE_AQ_VSI_OUTER_VLAN_EMODE_NOTHING 0x3
530 #define ICE_AQ_VSI_OUTER_TAG_TYPE_S 2
531 #define ICE_AQ_VSI_OUTER_TAG_TYPE_M (0x3 << ICE_AQ_VSI_OUTER_TAG_TYPE_S)
532 #define ICE_AQ_VSI_OUTER_TAG_NONE 0x0
533 #define ICE_AQ_VSI_OUTER_TAG_STAG 0x1
534 #define ICE_AQ_VSI_OUTER_TAG_VLAN_8100 0x2
535 #define ICE_AQ_VSI_OUTER_TAG_VLAN_9100 0x3
536 #define ICE_AQ_VSI_OUTER_VLAN_PORT_BASED_INSERT BIT(4)
537 #define ICE_AQ_VSI_OUTER_VLAN_PORT_BASED_ACCEPT_HOST BIT(6)
538 #define ICE_AQ_VSI_OUTER_VLAN_TX_MODE_S 5
539 #define ICE_AQ_VSI_OUTER_VLAN_TX_MODE_M (0x3 << ICE_AQ_VSI_OUTER_VLAN_TX_MODE_S)
540 #define ICE_AQ_VSI_OUTER_VLAN_TX_MODE_ACCEPTUNTAGGED 0x1
541 #define ICE_AQ_VSI_OUTER_VLAN_TX_MODE_ACCEPTTAGGED 0x2
542 #define ICE_AQ_VSI_OUTER_VLAN_TX_MODE_ALL 0x3
543 #define ICE_AQ_VSI_OUTER_VLAN_BLOCK_TX_DESC BIT(7)
544 u8 outer_vlan_reserved;
545 /* queue mapping section */
546 __le16 mapping_flags;
547 #define ICE_AQ_VSI_Q_MAP_CONTIG 0x0
548 #define ICE_AQ_VSI_Q_MAP_NONCONTIG BIT(0)
549 __le16 q_mapping[16];
550 #define ICE_AQ_VSI_Q_S 0
551 #define ICE_AQ_VSI_Q_M (0x7FF << ICE_AQ_VSI_Q_S)
552 __le16 tc_mapping[8];
553 #define ICE_AQ_VSI_TC_Q_OFFSET_S 0
554 #define ICE_AQ_VSI_TC_Q_OFFSET_M (0x7FF << ICE_AQ_VSI_TC_Q_OFFSET_S)
555 #define ICE_AQ_VSI_TC_Q_NUM_S 11
556 #define ICE_AQ_VSI_TC_Q_NUM_M (0xF << ICE_AQ_VSI_TC_Q_NUM_S)
557 /* queueing option section */
559 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_S 0
560 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_M (0x3 << ICE_AQ_VSI_Q_OPT_RSS_LUT_S)
561 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_VSI 0x0
562 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_PF 0x2
563 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_GBL 0x3
564 #define ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_S 2
565 #define ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_M (0xF << ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_S)
566 #define ICE_AQ_VSI_Q_OPT_RSS_HASH_S 6
567 #define ICE_AQ_VSI_Q_OPT_RSS_HASH_M (0x3 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S)
568 #define ICE_AQ_VSI_Q_OPT_RSS_TPLZ (0x0 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S)
569 #define ICE_AQ_VSI_Q_OPT_RSS_SYM_TPLZ (0x1 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S)
570 #define ICE_AQ_VSI_Q_OPT_RSS_XOR (0x2 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S)
571 #define ICE_AQ_VSI_Q_OPT_RSS_JHASH (0x3 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S)
573 #define ICE_AQ_VSI_Q_OPT_TC_OVR_S 0
574 #define ICE_AQ_VSI_Q_OPT_TC_OVR_M (0x1F << ICE_AQ_VSI_Q_OPT_TC_OVR_S)
575 #define ICE_AQ_VSI_Q_OPT_PROF_TC_OVR BIT(7)
577 #define ICE_AQ_VSI_Q_OPT_PE_FLTR_EN BIT(0)
578 u8 q_opt_reserved[3];
579 /* outer up section */
580 __le32 outer_up_table; /* same structure and defines as ingress tbl */
583 #define ICE_AQ_VSI_ACL_DEF_RX_PROF_S 0
584 #define ICE_AQ_VSI_ACL_DEF_RX_PROF_M (0xF << ICE_AQ_VSI_ACL_DEF_RX_PROF_S)
585 #define ICE_AQ_VSI_ACL_DEF_RX_TABLE_S 4
586 #define ICE_AQ_VSI_ACL_DEF_RX_TABLE_M (0xF << ICE_AQ_VSI_ACL_DEF_RX_TABLE_S)
587 #define ICE_AQ_VSI_ACL_DEF_TX_PROF_S 8
588 #define ICE_AQ_VSI_ACL_DEF_TX_PROF_M (0xF << ICE_AQ_VSI_ACL_DEF_TX_PROF_S)
589 #define ICE_AQ_VSI_ACL_DEF_TX_TABLE_S 12
590 #define ICE_AQ_VSI_ACL_DEF_TX_TABLE_M (0xF << ICE_AQ_VSI_ACL_DEF_TX_TABLE_S)
591 /* flow director section */
593 #define ICE_AQ_VSI_FD_ENABLE BIT(0)
594 #define ICE_AQ_VSI_FD_TX_AUTO_ENABLE BIT(1)
595 #define ICE_AQ_VSI_FD_PROG_ENABLE BIT(3)
596 __le16 max_fd_fltr_dedicated;
597 __le16 max_fd_fltr_shared;
599 #define ICE_AQ_VSI_FD_DEF_Q_S 0
600 #define ICE_AQ_VSI_FD_DEF_Q_M (0x7FF << ICE_AQ_VSI_FD_DEF_Q_S)
601 #define ICE_AQ_VSI_FD_DEF_GRP_S 12
602 #define ICE_AQ_VSI_FD_DEF_GRP_M (0x7 << ICE_AQ_VSI_FD_DEF_GRP_S)
603 __le16 fd_report_opt;
604 #define ICE_AQ_VSI_FD_REPORT_Q_S 0
605 #define ICE_AQ_VSI_FD_REPORT_Q_M (0x7FF << ICE_AQ_VSI_FD_REPORT_Q_S)
606 #define ICE_AQ_VSI_FD_DEF_PRIORITY_S 12
607 #define ICE_AQ_VSI_FD_DEF_PRIORITY_M (0x7 << ICE_AQ_VSI_FD_DEF_PRIORITY_S)
608 #define ICE_AQ_VSI_FD_DEF_DROP BIT(15)
611 #define ICE_AQ_VSI_PASID_ID_S 0
612 #define ICE_AQ_VSI_PASID_ID_M (0xFFFFF << ICE_AQ_VSI_PASID_ID_S)
613 #define ICE_AQ_VSI_PASID_ID_VALID BIT(31)
617 /* Add/update mirror rule - direct (0x0260) */
618 #define ICE_AQC_RULE_ID_VALID_S 7
619 #define ICE_AQC_RULE_ID_VALID_M (0x1 << ICE_AQC_RULE_ID_VALID_S)
620 #define ICE_AQC_RULE_ID_S 0
621 #define ICE_AQC_RULE_ID_M (0x3F << ICE_AQC_RULE_ID_S)
623 /* Following defines to be used while processing caller specified mirror list
626 /* Action: Byte.bit (1.7)
627 * 0 = Remove VSI from mirror rule
628 * 1 = Add VSI to mirror rule
630 #define ICE_AQC_RULE_ACT_S 15
631 #define ICE_AQC_RULE_ACT_M (0x1 << ICE_AQC_RULE_ACT_S)
632 /* Action: 1.2:0.0 = Mirrored VSI */
633 #define ICE_AQC_RULE_MIRRORED_VSI_S 0
634 #define ICE_AQC_RULE_MIRRORED_VSI_M (0x7FF << ICE_AQC_RULE_MIRRORED_VSI_S)
636 /* This is to be used by add/update mirror rule Admin Queue command.
637 * In case of add mirror rule - if rule ID is specified as
638 * INVAL_MIRROR_RULE_ID, new rule ID is allocated from shared pool.
639 * If specified rule_id is valid, then it is used. If specified rule_id
640 * is in use then new mirroring rule is added.
642 #define ICE_INVAL_MIRROR_RULE_ID 0xFFFF
644 struct ice_aqc_add_update_mir_rule {
648 #define ICE_AQC_RULE_TYPE_S 0
649 #define ICE_AQC_RULE_TYPE_M (0x7 << ICE_AQC_RULE_TYPE_S)
650 /* VPORT ingress/egress */
651 #define ICE_AQC_RULE_TYPE_VPORT_INGRESS 0x1
652 #define ICE_AQC_RULE_TYPE_VPORT_EGRESS 0x2
653 /* Physical port ingress mirroring.
654 * All traffic received by this port
656 #define ICE_AQC_RULE_TYPE_PPORT_INGRESS 0x6
657 /* Physical port egress mirroring. All traffic sent by this port */
658 #define ICE_AQC_RULE_TYPE_PPORT_EGRESS 0x7
660 /* Number of mirrored entries.
661 * The values are in the command buffer
665 /* Destination VSI */
671 /* Delete mirror rule - direct(0x0261) */
672 struct ice_aqc_delete_mir_rule {
676 /* Byte.bit: 20.0 = Keep allocation. If set VSI stays part of
677 * the PF allocated resources, otherwise it is returned to the
680 #define ICE_AQC_FLAG_KEEP_ALLOCD_S 0
681 #define ICE_AQC_FLAG_KEEP_ALLOCD_M (0x1 << ICE_AQC_FLAG_KEEP_ALLOCD_S)
687 /* Set/Get storm config - (direct 0x0280, 0x0281) */
688 /* This structure holds get storm configuration response and same structure
689 * is used to perform set_storm_cfg
691 struct ice_aqc_storm_cfg {
692 __le32 bcast_thresh_size;
693 __le32 mcast_thresh_size;
694 /* Bit 18:0 - Traffic upper threshold size
695 * Bit 31:19 - Reserved
697 #define ICE_AQ_THRESHOLD_S 0
698 #define ICE_AQ_THRESHOLD_M (0x7FFFF << ICE_AQ_THRESHOLD_S)
700 __le32 storm_ctrl_ctrl;
701 /* Bit 0: MDIPW - Drop Multicast packets in previous window
702 * Bit 1: MDICW - Drop multicast packets in current window
703 * Bit 2: BDIPW - Drop broadcast packets in previous window
704 * Bit 3: BDICW - Drop broadcast packets in current window
706 #define ICE_AQ_STORM_CTRL_MDIPW_DROP_MULTICAST BIT(0)
707 #define ICE_AQ_STORM_CTRL_MDICW_DROP_MULTICAST BIT(1)
708 #define ICE_AQ_STORM_CTRL_BDIPW_DROP_MULTICAST BIT(2)
709 #define ICE_AQ_STORM_CTRL_BDICW_DROP_MULTICAST BIT(3)
710 /* Bit 7:5 : Reserved */
711 /* Bit 27:8 : Interval - BSC/MSC Time-interval specification: The
712 * interval size for applying ingress broadcast or multicast storm
715 #define ICE_AQ_STORM_BSC_MSC_TIME_INTERVAL_S 8
716 #define ICE_AQ_STORM_BSC_MSC_TIME_INTERVAL_M \
717 (0xFFFFF << ICE_AQ_STORM_BSC_MSC_TIME_INTERVAL_S)
721 #define ICE_MAX_NUM_RECIPES 64
723 /* Add/Get Recipe (indirect 0x0290/0x0292) */
724 struct ice_aqc_add_get_recipe {
725 __le16 num_sub_recipes; /* Input in Add cmd, Output in Get cmd */
726 __le16 return_index; /* Input, used for Get cmd only */
732 struct ice_aqc_recipe_content {
734 #define ICE_AQ_RECIPE_ID_S 0
735 #define ICE_AQ_RECIPE_ID_M (0x3F << ICE_AQ_RECIPE_ID_S)
736 #define ICE_AQ_RECIPE_ID_IS_ROOT BIT(7)
737 #define ICE_AQ_SW_ID_LKUP_IDX 0
739 #define ICE_AQ_RECIPE_LKUP_DATA_S 0
740 #define ICE_AQ_RECIPE_LKUP_DATA_M (0x3F << ICE_AQ_RECIPE_LKUP_DATA_S)
741 #define ICE_AQ_RECIPE_LKUP_IGNORE BIT(7)
742 #define ICE_AQ_SW_ID_LKUP_MASK 0x00FF
745 #define ICE_AQ_RECIPE_RESULT_DATA_S 0
746 #define ICE_AQ_RECIPE_RESULT_DATA_M (0x3F << ICE_AQ_RECIPE_RESULT_DATA_S)
747 #define ICE_AQ_RECIPE_RESULT_EN BIT(7)
749 u8 act_ctrl_join_priority;
750 u8 act_ctrl_fwd_priority;
751 #define ICE_AQ_RECIPE_FWD_PRIORITY_S 0
752 #define ICE_AQ_RECIPE_FWD_PRIORITY_M (0xF << ICE_AQ_RECIPE_FWD_PRIORITY_S)
754 #define ICE_AQ_RECIPE_ACT_NEED_PASS_L2 BIT(0)
755 #define ICE_AQ_RECIPE_ACT_ALLOW_PASS_L2 BIT(1)
756 #define ICE_AQ_RECIPE_ACT_INV_ACT BIT(2)
757 #define ICE_AQ_RECIPE_ACT_PRUNE_INDX_S 4
758 #define ICE_AQ_RECIPE_ACT_PRUNE_INDX_M (0x3 << ICE_AQ_RECIPE_ACT_PRUNE_INDX_S)
761 #define ICE_AQ_RECIPE_DFLT_ACT_S 0
762 #define ICE_AQ_RECIPE_DFLT_ACT_M (0x7FFFF << ICE_AQ_RECIPE_DFLT_ACT_S)
763 #define ICE_AQ_RECIPE_DFLT_ACT_VALID BIT(31)
766 struct ice_aqc_recipe_data_elem {
769 #define ICE_AQ_RECIPE_WAS_UPDATED BIT(0)
773 struct ice_aqc_recipe_content content;
777 /* Set/Get Recipes to Profile Association (direct 0x0291/0x0293) */
778 struct ice_aqc_recipe_to_profile {
781 ice_declare_bitmap(recipe_assoc, ICE_MAX_NUM_RECIPES);
784 /* Add/Update/Remove/Get switch rules (indirect 0x02A0, 0x02A1, 0x02A2, 0x02A3)
786 struct ice_aqc_sw_rules {
787 /* ops: add switch rules, referring the number of rules.
788 * ops: update switch rules, referring the number of filters
789 * ops: remove switch rules, referring the entry index.
790 * ops: get switch rules, referring to the number of filters.
792 __le16 num_rules_fltr_entry_index;
798 /* Add/Update/Get/Remove lookup Rx/Tx command/response entry
799 * This structures describes the lookup rules and associated actions. "index"
800 * is returned as part of a response to a successful Add command, and can be
801 * used to identify the rule for Update/Get/Remove commands.
803 struct ice_sw_rule_lkup_rx_tx {
805 #define ICE_SW_RECIPE_LOGICAL_PORT_FWD 10
806 /* Source port for LOOKUP_RX and source VSI in case of LOOKUP_TX */
810 /* Bit 0:1 - Action type */
811 #define ICE_SINGLE_ACT_TYPE_S 0x00
812 #define ICE_SINGLE_ACT_TYPE_M (0x3 << ICE_SINGLE_ACT_TYPE_S)
814 /* Bit 2 - Loop back enable
817 #define ICE_SINGLE_ACT_LB_ENABLE BIT(2)
818 #define ICE_SINGLE_ACT_LAN_ENABLE BIT(3)
820 /* Action type = 0 - Forward to VSI or VSI list */
821 #define ICE_SINGLE_ACT_VSI_FORWARDING 0x0
823 #define ICE_SINGLE_ACT_VSI_ID_S 4
824 #define ICE_SINGLE_ACT_VSI_ID_M (0x3FF << ICE_SINGLE_ACT_VSI_ID_S)
825 #define ICE_SINGLE_ACT_VSI_LIST_ID_S 4
826 #define ICE_SINGLE_ACT_VSI_LIST_ID_M (0x3FF << ICE_SINGLE_ACT_VSI_LIST_ID_S)
827 /* This bit needs to be set if action is forward to VSI list */
828 #define ICE_SINGLE_ACT_VSI_LIST BIT(14)
829 #define ICE_SINGLE_ACT_VALID_BIT BIT(17)
830 #define ICE_SINGLE_ACT_DROP BIT(18)
832 /* Action type = 1 - Forward to Queue of Queue group */
833 #define ICE_SINGLE_ACT_TO_Q 0x1
834 #define ICE_SINGLE_ACT_Q_INDEX_S 4
835 #define ICE_SINGLE_ACT_Q_INDEX_M (0x7FF << ICE_SINGLE_ACT_Q_INDEX_S)
836 #define ICE_SINGLE_ACT_Q_REGION_S 15
837 #define ICE_SINGLE_ACT_Q_REGION_M (0x7 << ICE_SINGLE_ACT_Q_REGION_S)
838 #define ICE_SINGLE_ACT_Q_PRIORITY BIT(18)
840 /* Action type = 2 - Prune */
841 #define ICE_SINGLE_ACT_PRUNE 0x2
842 #define ICE_SINGLE_ACT_EGRESS BIT(15)
843 #define ICE_SINGLE_ACT_INGRESS BIT(16)
844 #define ICE_SINGLE_ACT_PRUNET BIT(17)
845 /* Bit 18 should be set to 0 for this action */
847 /* Action type = 2 - Pointer */
848 #define ICE_SINGLE_ACT_PTR 0x2
849 #define ICE_SINGLE_ACT_PTR_VAL_S 4
850 #define ICE_SINGLE_ACT_PTR_VAL_M (0x1FFF << ICE_SINGLE_ACT_PTR_VAL_S)
851 /* Bit 18 should be set to 1 */
852 #define ICE_SINGLE_ACT_PTR_BIT BIT(18)
854 /* Action type = 3 - Other actions. Last two bits
855 * are other action identifier
857 #define ICE_SINGLE_ACT_OTHER_ACTS 0x3
858 #define ICE_SINGLE_OTHER_ACT_IDENTIFIER_S 17
859 #define ICE_SINGLE_OTHER_ACT_IDENTIFIER_M \
860 (0x3 << ICE_SINGLE_OTHER_ACT_IDENTIFIER_S)
862 /* Bit 17:18 - Defines other actions */
863 /* Other action = 0 - Mirror VSI */
864 #define ICE_SINGLE_OTHER_ACT_MIRROR 0
865 #define ICE_SINGLE_ACT_MIRROR_VSI_ID_S 4
866 #define ICE_SINGLE_ACT_MIRROR_VSI_ID_M \
867 (0x3FF << ICE_SINGLE_ACT_MIRROR_VSI_ID_S)
869 /* Other action = 3 - Set Stat count */
870 #define ICE_SINGLE_OTHER_ACT_STAT_COUNT 3
871 #define ICE_SINGLE_ACT_STAT_COUNT_INDEX_S 4
872 #define ICE_SINGLE_ACT_STAT_COUNT_INDEX_M \
873 (0x7F << ICE_SINGLE_ACT_STAT_COUNT_INDEX_S)
875 __le16 index; /* The index of the rule in the lookup table */
876 /* Length and values of the header to be matched per recipe or
880 u8 hdr[STRUCT_HACK_VAR_LEN];
883 /* Add/Update/Remove large action command/response entry
884 * "index" is returned as part of a response to a successful Add command, and
885 * can be used to identify the action for Update/Get/Remove commands.
887 struct ice_sw_rule_lg_act {
888 __le16 index; /* Index in large action table */
890 /* Max number of large actions */
891 #define ICE_MAX_LG_ACT 4
892 /* Bit 0:1 - Action type */
893 #define ICE_LG_ACT_TYPE_S 0
894 #define ICE_LG_ACT_TYPE_M (0x7 << ICE_LG_ACT_TYPE_S)
896 /* Action type = 0 - Forward to VSI or VSI list */
897 #define ICE_LG_ACT_VSI_FORWARDING 0
898 #define ICE_LG_ACT_VSI_ID_S 3
899 #define ICE_LG_ACT_VSI_ID_M (0x3FF << ICE_LG_ACT_VSI_ID_S)
900 #define ICE_LG_ACT_VSI_LIST_ID_S 3
901 #define ICE_LG_ACT_VSI_LIST_ID_M (0x3FF << ICE_LG_ACT_VSI_LIST_ID_S)
902 /* This bit needs to be set if action is forward to VSI list */
903 #define ICE_LG_ACT_VSI_LIST BIT(13)
905 #define ICE_LG_ACT_VALID_BIT BIT(16)
907 /* Action type = 1 - Forward to Queue of Queue group */
908 #define ICE_LG_ACT_TO_Q 0x1
909 #define ICE_LG_ACT_Q_INDEX_S 3
910 #define ICE_LG_ACT_Q_INDEX_M (0x7FF << ICE_LG_ACT_Q_INDEX_S)
911 #define ICE_LG_ACT_Q_REGION_S 14
912 #define ICE_LG_ACT_Q_REGION_M (0x7 << ICE_LG_ACT_Q_REGION_S)
913 #define ICE_LG_ACT_Q_PRIORITY_SET BIT(17)
915 /* Action type = 2 - Prune */
916 #define ICE_LG_ACT_PRUNE 0x2
917 #define ICE_LG_ACT_EGRESS BIT(14)
918 #define ICE_LG_ACT_INGRESS BIT(15)
919 #define ICE_LG_ACT_PRUNET BIT(16)
921 /* Action type = 3 - Mirror VSI */
922 #define ICE_LG_OTHER_ACT_MIRROR 0x3
923 #define ICE_LG_ACT_MIRROR_VSI_ID_S 3
924 #define ICE_LG_ACT_MIRROR_VSI_ID_M (0x3FF << ICE_LG_ACT_MIRROR_VSI_ID_S)
926 /* Action type = 5 - Generic Value */
927 #define ICE_LG_ACT_GENERIC 0x5
928 #define ICE_LG_ACT_GENERIC_VALUE_S 3
929 #define ICE_LG_ACT_GENERIC_VALUE_M (0xFFFF << ICE_LG_ACT_GENERIC_VALUE_S)
930 #define ICE_LG_ACT_GENERIC_OFFSET_S 19
931 #define ICE_LG_ACT_GENERIC_OFFSET_M (0x7 << ICE_LG_ACT_GENERIC_OFFSET_S)
932 #define ICE_LG_ACT_GENERIC_PRIORITY_S 22
933 #define ICE_LG_ACT_GENERIC_PRIORITY_M (0x7 << ICE_LG_ACT_GENERIC_PRIORITY_S)
934 #define ICE_LG_ACT_GENERIC_OFF_RX_DESC_PROF_IDX 7
936 /* Action = 7 - Set Stat count */
937 #define ICE_LG_ACT_STAT_COUNT 0x7
938 #define ICE_LG_ACT_STAT_COUNT_S 3
939 #define ICE_LG_ACT_STAT_COUNT_M (0x7F << ICE_LG_ACT_STAT_COUNT_S)
940 __le32 act[STRUCT_HACK_VAR_LEN]; /* array of size for actions */
943 /* Add/Update/Remove VSI list command/response entry
944 * "index" is returned as part of a response to a successful Add command, and
945 * can be used to identify the VSI list for Update/Get/Remove commands.
947 struct ice_sw_rule_vsi_list {
948 __le16 index; /* Index of VSI/Prune list */
950 __le16 vsi[STRUCT_HACK_VAR_LEN]; /* Array of number_vsi VSI numbers */
954 /* Query VSI list command/response entry */
955 struct ice_sw_rule_vsi_list_query {
957 ice_declare_bitmap(vsi_list, ICE_MAX_VSI);
962 /* Add switch rule response:
963 * Content of return buffer is same as the input buffer. The status field and
964 * LUT index are updated as part of the response
966 struct ice_aqc_sw_rules_elem {
967 __le16 type; /* Switch rule type, one of T_... */
968 #define ICE_AQC_SW_RULES_T_LKUP_RX 0x0
969 #define ICE_AQC_SW_RULES_T_LKUP_TX 0x1
970 #define ICE_AQC_SW_RULES_T_LG_ACT 0x2
971 #define ICE_AQC_SW_RULES_T_VSI_LIST_SET 0x3
972 #define ICE_AQC_SW_RULES_T_VSI_LIST_CLEAR 0x4
973 #define ICE_AQC_SW_RULES_T_PRUNE_LIST_SET 0x5
974 #define ICE_AQC_SW_RULES_T_PRUNE_LIST_CLEAR 0x6
977 struct ice_sw_rule_lkup_rx_tx lkup_tx_rx;
978 struct ice_sw_rule_lg_act lg_act;
979 struct ice_sw_rule_vsi_list vsi_list;
980 struct ice_sw_rule_vsi_list_query vsi_list_query;
986 /* PFC Ignore (direct 0x0301)
987 * The command and response use the same descriptor structure
989 struct ice_aqc_pfc_ignore {
991 u8 cmd_flags; /* unused in response */
992 #define ICE_AQC_PFC_IGNORE_SET BIT(7)
993 #define ICE_AQC_PFC_IGNORE_CLEAR 0
997 /* Set PFC Mode (direct 0x0303)
998 * Query PFC Mode (direct 0x0302)
1000 struct ice_aqc_set_query_pfc_mode {
1002 /* For Set Command response, reserved in all other cases */
1003 #define ICE_AQC_PFC_NOT_CONFIGURED 0
1004 /* For Query Command response, reserved in all other cases */
1005 #define ICE_AQC_DCB_DIS 0
1006 #define ICE_AQC_PFC_VLAN_BASED_PFC 1
1007 #define ICE_AQC_PFC_DSCP_BASED_PFC 2
1011 /* Set DCB Parameters (direct 0x0306) */
1012 struct ice_aqc_set_dcb_params {
1013 u8 cmd_flags; /* unused in response */
1014 #define ICE_AQC_LINK_UP_DCB_CFG BIT(0)
1015 #define ICE_AQC_PERSIST_DCB_CFG BIT(1)
1016 u8 valid_flags; /* unused in response */
1017 #define ICE_AQC_LINK_UP_DCB_CFG_VALID BIT(0)
1018 #define ICE_AQC_PERSIST_DCB_CFG_VALID BIT(1)
1022 /* Get Default Topology (indirect 0x0400) */
1023 struct ice_aqc_get_topo {
1032 /* Update TSE (indirect 0x0403)
1033 * Get TSE (indirect 0x0404)
1034 * Add TSE (indirect 0x0401)
1035 * Delete TSE (indirect 0x040F)
1036 * Move TSE (indirect 0x0408)
1037 * Suspend Nodes (indirect 0x0409)
1038 * Resume Nodes (indirect 0x040A)
1040 struct ice_aqc_sched_elem_cmd {
1041 __le16 num_elem_req; /* Used by commands */
1042 __le16 num_elem_resp; /* Used by responses */
1048 struct ice_aqc_txsched_move_grp_info_hdr {
1049 __le32 src_parent_teid;
1050 __le32 dest_parent_teid;
1056 struct ice_aqc_move_elem {
1057 struct ice_aqc_txsched_move_grp_info_hdr hdr;
1058 __le32 teid[STRUCT_HACK_VAR_LEN];
1061 struct ice_aqc_elem_info_bw {
1062 __le16 bw_profile_idx;
1066 struct ice_aqc_txsched_elem {
1067 u8 elem_type; /* Special field, reserved for some aq calls */
1068 #define ICE_AQC_ELEM_TYPE_UNDEFINED 0x0
1069 #define ICE_AQC_ELEM_TYPE_ROOT_PORT 0x1
1070 #define ICE_AQC_ELEM_TYPE_TC 0x2
1071 #define ICE_AQC_ELEM_TYPE_SE_GENERIC 0x3
1072 #define ICE_AQC_ELEM_TYPE_ENTRY_POINT 0x4
1073 #define ICE_AQC_ELEM_TYPE_LEAF 0x5
1074 #define ICE_AQC_ELEM_TYPE_SE_PADDED 0x6
1076 #define ICE_AQC_ELEM_VALID_GENERIC BIT(0)
1077 #define ICE_AQC_ELEM_VALID_CIR BIT(1)
1078 #define ICE_AQC_ELEM_VALID_EIR BIT(2)
1079 #define ICE_AQC_ELEM_VALID_SHARED BIT(3)
1081 #define ICE_AQC_ELEM_GENERIC_MODE_M 0x1
1082 #define ICE_AQC_ELEM_GENERIC_PRIO_S 0x1
1083 #define ICE_AQC_ELEM_GENERIC_PRIO_M (0x7 << ICE_AQC_ELEM_GENERIC_PRIO_S)
1084 #define ICE_AQC_ELEM_GENERIC_SP_S 0x4
1085 #define ICE_AQC_ELEM_GENERIC_SP_M (0x1 << ICE_AQC_ELEM_GENERIC_SP_S)
1086 #define ICE_AQC_ELEM_GENERIC_ADJUST_VAL_S 0x5
1087 #define ICE_AQC_ELEM_GENERIC_ADJUST_VAL_M \
1088 (0x3 << ICE_AQC_ELEM_GENERIC_ADJUST_VAL_S)
1089 u8 flags; /* Special field, reserved for some aq calls */
1090 #define ICE_AQC_ELEM_FLAG_SUSPEND_M 0x1
1091 struct ice_aqc_elem_info_bw cir_bw;
1092 struct ice_aqc_elem_info_bw eir_bw;
1097 struct ice_aqc_txsched_elem_data {
1100 struct ice_aqc_txsched_elem data;
1103 struct ice_aqc_txsched_topo_grp_info_hdr {
1109 struct ice_aqc_add_elem {
1110 struct ice_aqc_txsched_topo_grp_info_hdr hdr;
1111 struct ice_aqc_txsched_elem_data generic[STRUCT_HACK_VAR_LEN];
1114 struct ice_aqc_get_topo_elem {
1115 struct ice_aqc_txsched_topo_grp_info_hdr hdr;
1116 struct ice_aqc_txsched_elem_data
1117 generic[ICE_AQC_TOPO_MAX_LEVEL_NUM];
1120 struct ice_aqc_delete_elem {
1121 struct ice_aqc_txsched_topo_grp_info_hdr hdr;
1122 __le32 teid[STRUCT_HACK_VAR_LEN];
1125 /* Query Port ETS (indirect 0x040E)
1127 * This indirect command is used to query port TC node configuration.
1129 struct ice_aqc_query_port_ets {
1136 struct ice_aqc_port_ets_elem {
1139 /* 3 bits for UP per TC 0-7, 4th byte reserved */
1142 __le32 port_eir_prof_id;
1143 __le32 port_cir_prof_id;
1144 /* 3 bits per Node priority to TC 0-7, 4th byte reserved */
1145 __le32 tc_node_prio;
1146 #define ICE_TC_NODE_PRIO_S 0x4
1148 __le32 tc_node_teid[8]; /* Used for response, reserved in command */
1151 /* Rate limiting profile for
1152 * Add RL profile (indirect 0x0410)
1153 * Query RL profile (indirect 0x0411)
1154 * Remove RL profile (indirect 0x0415)
1155 * These indirect commands acts on single or multiple
1156 * RL profiles with specified data.
1158 struct ice_aqc_rl_profile {
1159 __le16 num_profiles;
1160 __le16 num_processed; /* Only for response. Reserved in Command. */
1166 struct ice_aqc_rl_profile_elem {
1169 #define ICE_AQC_RL_PROFILE_TYPE_S 0x0
1170 #define ICE_AQC_RL_PROFILE_TYPE_M (0x3 << ICE_AQC_RL_PROFILE_TYPE_S)
1171 #define ICE_AQC_RL_PROFILE_TYPE_CIR 0
1172 #define ICE_AQC_RL_PROFILE_TYPE_EIR 1
1173 #define ICE_AQC_RL_PROFILE_TYPE_SRL 2
1174 /* The following flag is used for Query RL Profile Data */
1175 #define ICE_AQC_RL_PROFILE_INVAL_S 0x7
1176 #define ICE_AQC_RL_PROFILE_INVAL_M (0x1 << ICE_AQC_RL_PROFILE_INVAL_S)
1179 __le16 max_burst_size;
1181 __le16 wake_up_calc;
1185 /* Configure L2 Node CGD (indirect 0x0414)
1186 * This indirect command allows configuring a congestion domain for given L2
1187 * node TEIDs in the scheduler topology.
1189 struct ice_aqc_cfg_l2_node_cgd {
1190 __le16 num_l2_nodes;
1196 struct ice_aqc_cfg_l2_node_cgd_elem {
1202 /* Query Scheduler Resource Allocation (indirect 0x0412)
1203 * This indirect command retrieves the scheduler resources allocated by
1204 * EMP Firmware to the given PF.
1206 struct ice_aqc_query_txsched_res {
1212 struct ice_aqc_generic_sched_props {
1214 __le16 logical_levels;
1215 u8 flattening_bitmap;
1223 struct ice_aqc_layer_props {
1226 __le16 max_device_nodes;
1227 __le16 max_pf_nodes;
1229 __le16 max_sibl_grp_sz;
1230 __le16 max_cir_rl_profiles;
1231 __le16 max_eir_rl_profiles;
1232 __le16 max_srl_profiles;
1236 struct ice_aqc_query_txsched_res_resp {
1237 struct ice_aqc_generic_sched_props sched_props;
1238 struct ice_aqc_layer_props layer_props[ICE_AQC_TOPO_MAX_LEVEL_NUM];
1241 /* Query Node to Root Topology (indirect 0x0413)
1242 * This command uses ice_aqc_get_elem as its data buffer.
1244 struct ice_aqc_query_node_to_root {
1246 __le32 num_nodes; /* Response only */
1251 /* Get PHY capabilities (indirect 0x0600) */
1252 struct ice_aqc_get_phy_caps {
1256 /* 18.0 - Report qualified modules */
1257 #define ICE_AQC_GET_PHY_RQM BIT(0)
1258 /* 18.1 - 18.3 : Report mode
1259 * 000b - Report NVM capabilities
1260 * 001b - Report topology capabilities
1261 * 010b - Report SW configured
1262 * 100b - Report default capabilities
1264 #define ICE_AQC_REPORT_MODE_S 1
1265 #define ICE_AQC_REPORT_MODE_M (7 << ICE_AQC_REPORT_MODE_S)
1266 #define ICE_AQC_REPORT_TOPO_CAP_NO_MEDIA 0
1267 #define ICE_AQC_REPORT_TOPO_CAP_MEDIA BIT(1)
1268 #define ICE_AQC_REPORT_ACTIVE_CFG BIT(2)
1269 #define ICE_AQC_REPORT_DFLT_CFG BIT(3)
1275 /* This is #define of PHY type (Extended):
1276 * The first set of defines is for phy_type_low.
1278 #define ICE_PHY_TYPE_LOW_100BASE_TX BIT_ULL(0)
1279 #define ICE_PHY_TYPE_LOW_100M_SGMII BIT_ULL(1)
1280 #define ICE_PHY_TYPE_LOW_1000BASE_T BIT_ULL(2)
1281 #define ICE_PHY_TYPE_LOW_1000BASE_SX BIT_ULL(3)
1282 #define ICE_PHY_TYPE_LOW_1000BASE_LX BIT_ULL(4)
1283 #define ICE_PHY_TYPE_LOW_1000BASE_KX BIT_ULL(5)
1284 #define ICE_PHY_TYPE_LOW_1G_SGMII BIT_ULL(6)
1285 #define ICE_PHY_TYPE_LOW_2500BASE_T BIT_ULL(7)
1286 #define ICE_PHY_TYPE_LOW_2500BASE_X BIT_ULL(8)
1287 #define ICE_PHY_TYPE_LOW_2500BASE_KX BIT_ULL(9)
1288 #define ICE_PHY_TYPE_LOW_5GBASE_T BIT_ULL(10)
1289 #define ICE_PHY_TYPE_LOW_5GBASE_KR BIT_ULL(11)
1290 #define ICE_PHY_TYPE_LOW_10GBASE_T BIT_ULL(12)
1291 #define ICE_PHY_TYPE_LOW_10G_SFI_DA BIT_ULL(13)
1292 #define ICE_PHY_TYPE_LOW_10GBASE_SR BIT_ULL(14)
1293 #define ICE_PHY_TYPE_LOW_10GBASE_LR BIT_ULL(15)
1294 #define ICE_PHY_TYPE_LOW_10GBASE_KR_CR1 BIT_ULL(16)
1295 #define ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC BIT_ULL(17)
1296 #define ICE_PHY_TYPE_LOW_10G_SFI_C2C BIT_ULL(18)
1297 #define ICE_PHY_TYPE_LOW_25GBASE_T BIT_ULL(19)
1298 #define ICE_PHY_TYPE_LOW_25GBASE_CR BIT_ULL(20)
1299 #define ICE_PHY_TYPE_LOW_25GBASE_CR_S BIT_ULL(21)
1300 #define ICE_PHY_TYPE_LOW_25GBASE_CR1 BIT_ULL(22)
1301 #define ICE_PHY_TYPE_LOW_25GBASE_SR BIT_ULL(23)
1302 #define ICE_PHY_TYPE_LOW_25GBASE_LR BIT_ULL(24)
1303 #define ICE_PHY_TYPE_LOW_25GBASE_KR BIT_ULL(25)
1304 #define ICE_PHY_TYPE_LOW_25GBASE_KR_S BIT_ULL(26)
1305 #define ICE_PHY_TYPE_LOW_25GBASE_KR1 BIT_ULL(27)
1306 #define ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC BIT_ULL(28)
1307 #define ICE_PHY_TYPE_LOW_25G_AUI_C2C BIT_ULL(29)
1308 #define ICE_PHY_TYPE_LOW_40GBASE_CR4 BIT_ULL(30)
1309 #define ICE_PHY_TYPE_LOW_40GBASE_SR4 BIT_ULL(31)
1310 #define ICE_PHY_TYPE_LOW_40GBASE_LR4 BIT_ULL(32)
1311 #define ICE_PHY_TYPE_LOW_40GBASE_KR4 BIT_ULL(33)
1312 #define ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC BIT_ULL(34)
1313 #define ICE_PHY_TYPE_LOW_40G_XLAUI BIT_ULL(35)
1314 #define ICE_PHY_TYPE_LOW_50GBASE_CR2 BIT_ULL(36)
1315 #define ICE_PHY_TYPE_LOW_50GBASE_SR2 BIT_ULL(37)
1316 #define ICE_PHY_TYPE_LOW_50GBASE_LR2 BIT_ULL(38)
1317 #define ICE_PHY_TYPE_LOW_50GBASE_KR2 BIT_ULL(39)
1318 #define ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC BIT_ULL(40)
1319 #define ICE_PHY_TYPE_LOW_50G_LAUI2 BIT_ULL(41)
1320 #define ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC BIT_ULL(42)
1321 #define ICE_PHY_TYPE_LOW_50G_AUI2 BIT_ULL(43)
1322 #define ICE_PHY_TYPE_LOW_50GBASE_CP BIT_ULL(44)
1323 #define ICE_PHY_TYPE_LOW_50GBASE_SR BIT_ULL(45)
1324 #define ICE_PHY_TYPE_LOW_50GBASE_FR BIT_ULL(46)
1325 #define ICE_PHY_TYPE_LOW_50GBASE_LR BIT_ULL(47)
1326 #define ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4 BIT_ULL(48)
1327 #define ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC BIT_ULL(49)
1328 #define ICE_PHY_TYPE_LOW_50G_AUI1 BIT_ULL(50)
1329 #define ICE_PHY_TYPE_LOW_100GBASE_CR4 BIT_ULL(51)
1330 #define ICE_PHY_TYPE_LOW_100GBASE_SR4 BIT_ULL(52)
1331 #define ICE_PHY_TYPE_LOW_100GBASE_LR4 BIT_ULL(53)
1332 #define ICE_PHY_TYPE_LOW_100GBASE_KR4 BIT_ULL(54)
1333 #define ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC BIT_ULL(55)
1334 #define ICE_PHY_TYPE_LOW_100G_CAUI4 BIT_ULL(56)
1335 #define ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC BIT_ULL(57)
1336 #define ICE_PHY_TYPE_LOW_100G_AUI4 BIT_ULL(58)
1337 #define ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4 BIT_ULL(59)
1338 #define ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4 BIT_ULL(60)
1339 #define ICE_PHY_TYPE_LOW_100GBASE_CP2 BIT_ULL(61)
1340 #define ICE_PHY_TYPE_LOW_100GBASE_SR2 BIT_ULL(62)
1341 #define ICE_PHY_TYPE_LOW_100GBASE_DR BIT_ULL(63)
1342 #define ICE_PHY_TYPE_LOW_MAX_INDEX 63
1343 /* The second set of defines is for phy_type_high. */
1344 #define ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4 BIT_ULL(0)
1345 #define ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC BIT_ULL(1)
1346 #define ICE_PHY_TYPE_HIGH_100G_CAUI2 BIT_ULL(2)
1347 #define ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC BIT_ULL(3)
1348 #define ICE_PHY_TYPE_HIGH_100G_AUI2 BIT_ULL(4)
1349 #define ICE_PHY_TYPE_HIGH_MAX_INDEX 5
1351 struct ice_aqc_get_phy_caps_data {
1352 __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */
1353 __le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */
1355 #define ICE_AQC_PHY_EN_TX_LINK_PAUSE BIT(0)
1356 #define ICE_AQC_PHY_EN_RX_LINK_PAUSE BIT(1)
1357 #define ICE_AQC_PHY_LOW_POWER_MODE BIT(2)
1358 #define ICE_AQC_PHY_EN_LINK BIT(3)
1359 #define ICE_AQC_PHY_AN_MODE BIT(4)
1360 #define ICE_AQC_PHY_EN_MOD_QUAL BIT(5)
1361 #define ICE_AQC_PHY_EN_LESM BIT(6)
1362 #define ICE_AQC_PHY_EN_AUTO_FEC BIT(7)
1363 #define ICE_AQC_PHY_CAPS_MASK MAKEMASK(0xff, 0)
1364 u8 low_power_ctrl_an;
1365 #define ICE_AQC_PHY_EN_D3COLD_LOW_POWER_AUTONEG BIT(0)
1366 #define ICE_AQC_PHY_AN_EN_CLAUSE28 BIT(1)
1367 #define ICE_AQC_PHY_AN_EN_CLAUSE73 BIT(2)
1368 #define ICE_AQC_PHY_AN_EN_CLAUSE37 BIT(3)
1370 #define ICE_AQC_PHY_EEE_EN_100BASE_TX BIT(0)
1371 #define ICE_AQC_PHY_EEE_EN_1000BASE_T BIT(1)
1372 #define ICE_AQC_PHY_EEE_EN_10GBASE_T BIT(2)
1373 #define ICE_AQC_PHY_EEE_EN_1000BASE_KX BIT(3)
1374 #define ICE_AQC_PHY_EEE_EN_10GBASE_KR BIT(4)
1375 #define ICE_AQC_PHY_EEE_EN_25GBASE_KR BIT(5)
1376 #define ICE_AQC_PHY_EEE_EN_40GBASE_KR4 BIT(6)
1377 #define ICE_AQC_PHY_EEE_EN_50GBASE_KR2 BIT(7)
1378 #define ICE_AQC_PHY_EEE_EN_50GBASE_KR_PAM4 BIT(8)
1379 #define ICE_AQC_PHY_EEE_EN_100GBASE_KR4 BIT(9)
1380 #define ICE_AQC_PHY_EEE_EN_100GBASE_KR2_PAM4 BIT(10)
1382 u8 phy_id_oui[4]; /* PHY/Module ID connected on the port */
1384 u8 link_fec_options;
1385 #define ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN BIT(0)
1386 #define ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ BIT(1)
1387 #define ICE_AQC_PHY_FEC_25G_RS_528_REQ BIT(2)
1388 #define ICE_AQC_PHY_FEC_25G_KR_REQ BIT(3)
1389 #define ICE_AQC_PHY_FEC_25G_RS_544_REQ BIT(4)
1390 #define ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN BIT(6)
1391 #define ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN BIT(7)
1392 #define ICE_AQC_PHY_FEC_MASK MAKEMASK(0xdf, 0)
1393 u8 module_compliance_enforcement;
1394 #define ICE_AQC_MOD_ENFORCE_STRICT_MODE BIT(0)
1395 u8 extended_compliance_code;
1396 #define ICE_MODULE_TYPE_TOTAL_BYTE 3
1397 u8 module_type[ICE_MODULE_TYPE_TOTAL_BYTE];
1398 #define ICE_AQC_MOD_TYPE_BYTE0_SFP_PLUS 0xA0
1399 #define ICE_AQC_MOD_TYPE_BYTE0_QSFP_PLUS 0x80
1400 #define ICE_AQC_MOD_TYPE_IDENT 1
1401 #define ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_PASSIVE BIT(0)
1402 #define ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_ACTIVE BIT(1)
1403 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_SR BIT(4)
1404 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_LR BIT(5)
1405 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_LRM BIT(6)
1406 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_ER BIT(7)
1407 #define ICE_AQC_MOD_TYPE_BYTE2_SFP_PLUS 0xA0
1408 #define ICE_AQC_MOD_TYPE_BYTE2_QSFP_PLUS 0x86
1409 u8 qualified_module_count;
1410 u8 rsvd2[7]; /* Bytes 47:41 reserved */
1411 #define ICE_AQC_QUAL_MOD_COUNT_MAX 16
1418 } qual_modules[ICE_AQC_QUAL_MOD_COUNT_MAX];
1421 /* Set PHY capabilities (direct 0x0601)
1422 * NOTE: This command must be followed by setup link and restart auto-neg
1424 struct ice_aqc_set_phy_cfg {
1431 /* Set PHY config command data structure */
1432 struct ice_aqc_set_phy_cfg_data {
1433 __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */
1434 __le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */
1436 #define ICE_AQ_PHY_ENA_VALID_MASK MAKEMASK(0xef, 0)
1437 #define ICE_AQ_PHY_ENA_TX_PAUSE_ABILITY BIT(0)
1438 #define ICE_AQ_PHY_ENA_RX_PAUSE_ABILITY BIT(1)
1439 #define ICE_AQ_PHY_ENA_LOW_POWER BIT(2)
1440 #define ICE_AQ_PHY_ENA_LINK BIT(3)
1441 #define ICE_AQ_PHY_ENA_AUTO_LINK_UPDT BIT(5)
1442 #define ICE_AQ_PHY_ENA_LESM BIT(6)
1443 #define ICE_AQ_PHY_ENA_AUTO_FEC BIT(7)
1444 u8 low_power_ctrl_an;
1445 __le16 eee_cap; /* Value from ice_aqc_get_phy_caps */
1447 u8 link_fec_opt; /* Use defines from ice_aqc_get_phy_caps */
1448 u8 module_compliance_enforcement;
1451 /* Set MAC Config command data structure (direct 0x0603) */
1452 struct ice_aqc_set_mac_cfg {
1453 __le16 max_frame_size;
1455 #define ICE_AQ_SET_MAC_PACE_S 3
1456 #define ICE_AQ_SET_MAC_PACE_M (0xF << ICE_AQ_SET_MAC_PACE_S)
1457 #define ICE_AQ_SET_MAC_PACE_TYPE_M BIT(7)
1458 #define ICE_AQ_SET_MAC_PACE_TYPE_RATE 0
1459 #define ICE_AQ_SET_MAC_PACE_TYPE_FIXED ICE_AQ_SET_MAC_PACE_TYPE_M
1461 __le16 tx_tmr_value;
1462 __le16 fc_refresh_threshold;
1464 #define ICE_AQ_SET_MAC_AUTO_DROP_MASK BIT(0)
1465 #define ICE_AQ_SET_MAC_AUTO_DROP_NONE 0
1466 #define ICE_AQ_SET_MAC_AUTO_DROP_BLOCKING_PKTS BIT(0)
1470 /* Restart AN command data structure (direct 0x0605)
1471 * Also used for response, with only the lport_num field present.
1473 struct ice_aqc_restart_an {
1477 #define ICE_AQC_RESTART_AN_LINK_RESTART BIT(1)
1478 #define ICE_AQC_RESTART_AN_LINK_ENABLE BIT(2)
1482 /* Get link status (indirect 0x0607), also used for Link Status Event */
1483 struct ice_aqc_get_link_status {
1487 #define ICE_AQ_LSE_M 0x3
1488 #define ICE_AQ_LSE_NOP 0x0
1489 #define ICE_AQ_LSE_DIS 0x2
1490 #define ICE_AQ_LSE_ENA 0x3
1491 /* only response uses this flag */
1492 #define ICE_AQ_LSE_IS_ENABLED 0x1
1498 /* Get link status response data structure, also used for Link Status Event */
1499 struct ice_aqc_get_link_status_data {
1500 u8 topo_media_conflict;
1501 #define ICE_AQ_LINK_TOPO_CONFLICT BIT(0)
1502 #define ICE_AQ_LINK_MEDIA_CONFLICT BIT(1)
1503 #define ICE_AQ_LINK_TOPO_CORRUPT BIT(2)
1504 #define ICE_AQ_LINK_TOPO_UNREACH_PRT BIT(4)
1505 #define ICE_AQ_LINK_TOPO_UNDRUTIL_PRT BIT(5)
1506 #define ICE_AQ_LINK_TOPO_UNDRUTIL_MEDIA BIT(6)
1507 #define ICE_AQ_LINK_TOPO_UNSUPP_MEDIA BIT(7)
1509 #define ICE_AQ_LINK_CFG_ERR BIT(0)
1510 #define ICE_AQ_LINK_ACT_PORT_OPT_INVAL BIT(2)
1511 #define ICE_AQ_LINK_FEAT_ID_OR_CONFIG_ID_INVAL BIT(3)
1512 #define ICE_AQ_LINK_TOPO_CRITICAL_SDP_ERR BIT(4)
1513 #define ICE_AQ_LINK_MODULE_POWER_UNSUPPORTED BIT(5)
1515 #define ICE_AQ_LINK_UP BIT(0) /* Link Status */
1516 #define ICE_AQ_LINK_FAULT BIT(1)
1517 #define ICE_AQ_LINK_FAULT_TX BIT(2)
1518 #define ICE_AQ_LINK_FAULT_RX BIT(3)
1519 #define ICE_AQ_LINK_FAULT_REMOTE BIT(4)
1520 #define ICE_AQ_LINK_UP_PORT BIT(5) /* External Port Link Status */
1521 #define ICE_AQ_MEDIA_AVAILABLE BIT(6)
1522 #define ICE_AQ_SIGNAL_DETECT BIT(7)
1524 #define ICE_AQ_AN_COMPLETED BIT(0)
1525 #define ICE_AQ_LP_AN_ABILITY BIT(1)
1526 #define ICE_AQ_PD_FAULT BIT(2) /* Parallel Detection Fault */
1527 #define ICE_AQ_FEC_EN BIT(3)
1528 #define ICE_AQ_PHY_LOW_POWER BIT(4) /* Low Power State */
1529 #define ICE_AQ_LINK_PAUSE_TX BIT(5)
1530 #define ICE_AQ_LINK_PAUSE_RX BIT(6)
1531 #define ICE_AQ_QUALIFIED_MODULE BIT(7)
1533 #define ICE_AQ_LINK_PHY_TEMP_ALARM BIT(0)
1534 #define ICE_AQ_LINK_EXCESSIVE_ERRORS BIT(1) /* Excessive Link Errors */
1535 /* Port Tx Suspended */
1536 #define ICE_AQ_LINK_TX_S 2
1537 #define ICE_AQ_LINK_TX_M (0x03 << ICE_AQ_LINK_TX_S)
1538 #define ICE_AQ_LINK_TX_ACTIVE 0
1539 #define ICE_AQ_LINK_TX_DRAINED 1
1540 #define ICE_AQ_LINK_TX_FLUSHED 3
1542 #define ICE_AQ_LINK_LB_PHY_LCL BIT(0)
1543 #define ICE_AQ_LINK_LB_PHY_RMT BIT(1)
1544 #define ICE_AQ_LINK_LB_MAC_LCL BIT(2)
1545 #define ICE_AQ_LINK_LB_PHY_IDX_S 3
1546 #define ICE_AQ_LINK_LB_PHY_IDX_M (0x7 << ICE_AQ_LB_PHY_IDX_S)
1547 __le16 max_frame_size;
1549 #define ICE_AQ_LINK_25G_KR_FEC_EN BIT(0)
1550 #define ICE_AQ_LINK_25G_RS_528_FEC_EN BIT(1)
1551 #define ICE_AQ_LINK_25G_RS_544_FEC_EN BIT(2)
1552 #define ICE_AQ_FEC_MASK MAKEMASK(0x7, 0)
1554 #define ICE_AQ_CFG_PACING_S 3
1555 #define ICE_AQ_CFG_PACING_M (0xF << ICE_AQ_CFG_PACING_S)
1556 #define ICE_AQ_CFG_PACING_TYPE_M BIT(7)
1557 #define ICE_AQ_CFG_PACING_TYPE_AVG 0
1558 #define ICE_AQ_CFG_PACING_TYPE_FIXED ICE_AQ_CFG_PACING_TYPE_M
1559 /* External Device Power Ability */
1561 #define ICE_AQ_PWR_CLASS_M 0x3F
1562 #define ICE_AQ_LINK_PWR_BASET_LOW_HIGH 0
1563 #define ICE_AQ_LINK_PWR_BASET_HIGH 1
1564 #define ICE_AQ_LINK_PWR_QSFP_CLASS_1 0
1565 #define ICE_AQ_LINK_PWR_QSFP_CLASS_2 1
1566 #define ICE_AQ_LINK_PWR_QSFP_CLASS_3 2
1567 #define ICE_AQ_LINK_PWR_QSFP_CLASS_4 3
1569 #define ICE_AQ_LINK_SPEED_M 0x7FF
1570 #define ICE_AQ_LINK_SPEED_10MB BIT(0)
1571 #define ICE_AQ_LINK_SPEED_100MB BIT(1)
1572 #define ICE_AQ_LINK_SPEED_1000MB BIT(2)
1573 #define ICE_AQ_LINK_SPEED_2500MB BIT(3)
1574 #define ICE_AQ_LINK_SPEED_5GB BIT(4)
1575 #define ICE_AQ_LINK_SPEED_10GB BIT(5)
1576 #define ICE_AQ_LINK_SPEED_20GB BIT(6)
1577 #define ICE_AQ_LINK_SPEED_25GB BIT(7)
1578 #define ICE_AQ_LINK_SPEED_40GB BIT(8)
1579 #define ICE_AQ_LINK_SPEED_50GB BIT(9)
1580 #define ICE_AQ_LINK_SPEED_100GB BIT(10)
1581 #define ICE_AQ_LINK_SPEED_UNKNOWN BIT(15)
1582 __le32 reserved3; /* Aligns next field to 8-byte boundary */
1583 __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */
1584 __le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */
1587 /* Set event mask command (direct 0x0613) */
1588 struct ice_aqc_set_event_mask {
1592 #define ICE_AQ_LINK_EVENT_UPDOWN BIT(1)
1593 #define ICE_AQ_LINK_EVENT_MEDIA_NA BIT(2)
1594 #define ICE_AQ_LINK_EVENT_LINK_FAULT BIT(3)
1595 #define ICE_AQ_LINK_EVENT_PHY_TEMP_ALARM BIT(4)
1596 #define ICE_AQ_LINK_EVENT_EXCESSIVE_ERRORS BIT(5)
1597 #define ICE_AQ_LINK_EVENT_SIGNAL_DETECT BIT(6)
1598 #define ICE_AQ_LINK_EVENT_AN_COMPLETED BIT(7)
1599 #define ICE_AQ_LINK_EVENT_MODULE_QUAL_FAIL BIT(8)
1600 #define ICE_AQ_LINK_EVENT_PORT_TX_SUSPENDED BIT(9)
1601 #define ICE_AQ_LINK_EVENT_TOPO_CONFLICT BIT(10)
1602 #define ICE_AQ_LINK_EVENT_MEDIA_CONFLICT BIT(11)
1606 /* Set MAC Loopback command (direct 0x0620) */
1607 struct ice_aqc_set_mac_lb {
1609 #define ICE_AQ_MAC_LB_EN BIT(0)
1610 #define ICE_AQ_MAC_LB_OSC_CLK BIT(1)
1614 struct ice_aqc_link_topo_addr {
1617 #define ICE_AQC_LINK_TOPO_PORT_NUM_VALID BIT(0)
1619 #define ICE_AQC_LINK_TOPO_NODE_TYPE_S 0
1620 #define ICE_AQC_LINK_TOPO_NODE_TYPE_M (0xF << ICE_AQC_LINK_TOPO_NODE_TYPE_S)
1621 #define ICE_AQC_LINK_TOPO_NODE_TYPE_PHY 0
1622 #define ICE_AQC_LINK_TOPO_NODE_TYPE_GPIO_CTRL 1
1623 #define ICE_AQC_LINK_TOPO_NODE_TYPE_MUX_CTRL 2
1624 #define ICE_AQC_LINK_TOPO_NODE_TYPE_LED_CTRL 3
1625 #define ICE_AQC_LINK_TOPO_NODE_TYPE_LED 4
1626 #define ICE_AQC_LINK_TOPO_NODE_TYPE_THERMAL 5
1627 #define ICE_AQC_LINK_TOPO_NODE_TYPE_CAGE 6
1628 #define ICE_AQC_LINK_TOPO_NODE_TYPE_MEZZ 7
1629 #define ICE_AQC_LINK_TOPO_NODE_TYPE_ID_EEPROM 8
1630 #define ICE_AQC_LINK_TOPO_NODE_CTX_S 4
1631 #define ICE_AQC_LINK_TOPO_NODE_CTX_M \
1632 (0xF << ICE_AQC_LINK_TOPO_NODE_CTX_S)
1633 #define ICE_AQC_LINK_TOPO_NODE_CTX_GLOBAL 0
1634 #define ICE_AQC_LINK_TOPO_NODE_CTX_BOARD 1
1635 #define ICE_AQC_LINK_TOPO_NODE_CTX_PORT 2
1636 #define ICE_AQC_LINK_TOPO_NODE_CTX_NODE 3
1637 #define ICE_AQC_LINK_TOPO_NODE_CTX_PROVIDED 4
1638 #define ICE_AQC_LINK_TOPO_NODE_CTX_OVERRIDE 5
1641 #define ICE_AQC_LINK_TOPO_HANDLE_S 0
1642 #define ICE_AQC_LINK_TOPO_HANDLE_M (0x3FF << ICE_AQC_LINK_TOPO_HANDLE_S)
1643 /* Used to decode the handle field */
1644 #define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_M BIT(9)
1645 #define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_LOM BIT(9)
1646 #define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_MEZZ 0
1647 #define ICE_AQC_LINK_TOPO_HANDLE_NODE_S 0
1648 /* In case of a Mezzanine type */
1649 #define ICE_AQC_LINK_TOPO_HANDLE_MEZZ_NODE_M \
1650 (0x3F << ICE_AQC_LINK_TOPO_HANDLE_NODE_S)
1651 #define ICE_AQC_LINK_TOPO_HANDLE_MEZZ_S 6
1652 #define ICE_AQC_LINK_TOPO_HANDLE_MEZZ_M (0x7 << ICE_AQC_LINK_TOPO_HANDLE_MEZZ_S)
1653 /* In case of a LOM type */
1654 #define ICE_AQC_LINK_TOPO_HANDLE_LOM_NODE_M \
1655 (0x1FF << ICE_AQC_LINK_TOPO_HANDLE_NODE_S)
1658 /* Get Link Topology Handle (direct, 0x06E0) */
1659 struct ice_aqc_get_link_topo {
1660 struct ice_aqc_link_topo_addr addr;
1665 /* Set Port Identification LED (direct, 0x06E9) */
1666 struct ice_aqc_set_port_id_led {
1669 #define ICE_AQC_PORT_ID_PORT_NUM_VALID BIT(0)
1671 #define ICE_AQC_PORT_IDENT_LED_BLINK BIT(0)
1672 #define ICE_AQC_PORT_IDENT_LED_ORIG 0
1676 /* Read/Write SFF EEPROM command (indirect 0x06EE) */
1677 struct ice_aqc_sff_eeprom {
1680 #define ICE_AQC_SFF_PORT_NUM_VALID BIT(0)
1681 __le16 i2c_bus_addr;
1682 #define ICE_AQC_SFF_I2CBUS_7BIT_M 0x7F
1683 #define ICE_AQC_SFF_I2CBUS_10BIT_M 0x3FF
1684 #define ICE_AQC_SFF_I2CBUS_TYPE_M BIT(10)
1685 #define ICE_AQC_SFF_I2CBUS_TYPE_7BIT 0
1686 #define ICE_AQC_SFF_I2CBUS_TYPE_10BIT ICE_AQC_SFF_I2CBUS_TYPE_M
1687 #define ICE_AQC_SFF_SET_EEPROM_PAGE_S 11
1688 #define ICE_AQC_SFF_SET_EEPROM_PAGE_M (0x3 << ICE_AQC_SFF_SET_EEPROM_PAGE_S)
1689 #define ICE_AQC_SFF_NO_PAGE_CHANGE 0
1690 #define ICE_AQC_SFF_SET_23_ON_MISMATCH 1
1691 #define ICE_AQC_SFF_SET_22_ON_MISMATCH 2
1692 #define ICE_AQC_SFF_IS_WRITE BIT(15)
1693 __le16 i2c_mem_addr;
1695 #define ICE_AQC_SFF_EEPROM_BANK_S 0
1696 #define ICE_AQC_SFF_EEPROM_BANK_M (0xFF << ICE_AQC_SFF_EEPROM_BANK_S)
1697 #define ICE_AQC_SFF_EEPROM_PAGE_S 8
1698 #define ICE_AQC_SFF_EEPROM_PAGE_M (0xFF << ICE_AQC_SFF_EEPROM_PAGE_S)
1703 /* SW Set GPIO command (indirect 0x6EF)
1704 * SW Get GPIO command (indirect 0x6F0)
1706 struct ice_aqc_sw_gpio {
1707 __le16 gpio_ctrl_handle;
1708 #define ICE_AQC_SW_GPIO_CONTROLLER_HANDLE_S 0
1709 #define ICE_AQC_SW_GPIO_CONTROLLER_HANDLE_M (0x3FF << ICE_AQC_SW_GPIO_CONTROLLER_HANDLE_S)
1711 #define ICE_AQC_SW_GPIO_NUMBER_S 0
1712 #define ICE_AQC_SW_GPIO_NUMBER_M (0x1F << ICE_AQC_SW_GPIO_NUMBER_S)
1714 #define ICE_AQC_SW_GPIO_PARAMS_DIRECTION BIT(1)
1715 #define ICE_AQC_SW_GPIO_PARAMS_VALUE BIT(0)
1719 /* NVM Read command (indirect 0x0701)
1720 * NVM Erase commands (direct 0x0702)
1721 * NVM Write commands (indirect 0x0703)
1722 * NVM Write Activate commands (direct 0x0707)
1723 * NVM Shadow RAM Dump commands (direct 0x0707)
1725 struct ice_aqc_nvm {
1726 #define ICE_AQC_NVM_MAX_OFFSET 0xFFFFFF
1728 u8 offset_high; /* For Write Activate offset_high is used as flags2 */
1730 #define ICE_AQC_NVM_LAST_CMD BIT(0)
1731 #define ICE_AQC_NVM_PCIR_REQ BIT(0) /* Used by NVM Write reply */
1732 #define ICE_AQC_NVM_PRESERVATION_S 1 /* Used by NVM Write Activate only */
1733 #define ICE_AQC_NVM_PRESERVATION_M (3 << ICE_AQC_NVM_PRESERVATION_S)
1734 #define ICE_AQC_NVM_NO_PRESERVATION (0 << ICE_AQC_NVM_PRESERVATION_S)
1735 #define ICE_AQC_NVM_PRESERVE_ALL BIT(1)
1736 #define ICE_AQC_NVM_FACTORY_DEFAULT (2 << ICE_AQC_NVM_PRESERVATION_S)
1737 #define ICE_AQC_NVM_PRESERVE_SELECTED (3 << ICE_AQC_NVM_PRESERVATION_S)
1738 #define ICE_AQC_NVM_ACTIV_SEL_NVM BIT(3) /* Write Activate/SR Dump only */
1739 #define ICE_AQC_NVM_ACTIV_SEL_OROM BIT(4)
1740 #define ICE_AQC_NVM_ACTIV_SEL_NETLIST BIT(5)
1741 #define ICE_AQC_NVM_SPECIAL_UPDATE BIT(6)
1742 #define ICE_AQC_NVM_REVERT_LAST_ACTIV BIT(6) /* Write Activate only */
1743 #define ICE_AQC_NVM_ACTIV_SEL_MASK MAKEMASK(0x7, 3)
1744 #define ICE_AQC_NVM_FLASH_ONLY BIT(7)
1745 #define ICE_AQC_NVM_POR_FLAG 0 /* Used by NVM Write completion on ARQ */
1746 #define ICE_AQC_NVM_PERST_FLAG 1
1747 #define ICE_AQC_NVM_EMPR_FLAG 2
1748 __le16 module_typeid;
1750 #define ICE_AQC_NVM_ERASE_LEN 0xFFFF
1755 /* NVM Module_Type ID, needed offset and read_len for struct ice_aqc_nvm. */
1756 #define ICE_AQC_NVM_SECTOR_UNIT 4096 /* In Bytes */
1757 #define ICE_AQC_NVM_WORD_UNIT 2 /* In Bytes */
1759 #define ICE_AQC_NVM_START_POINT 0
1760 #define ICE_AQC_NVM_EMP_SR_PTR_OFFSET 0x90
1761 #define ICE_AQC_NVM_EMP_SR_PTR_RD_LEN 2 /* In Bytes */
1762 #define ICE_AQC_NVM_EMP_SR_PTR_M MAKEMASK(0x7FFF, 0)
1763 #define ICE_AQC_NVM_EMP_SR_PTR_TYPE_S 15
1764 #define ICE_AQC_NVM_EMP_SR_PTR_TYPE_M BIT(15)
1765 #define ICE_AQC_NVM_EMP_SR_PTR_TYPE_SECTOR 1
1767 #define ICE_AQC_NVM_LLDP_CFG_PTR_OFFSET 0x46
1768 #define ICE_AQC_NVM_LLDP_CFG_HEADER_LEN 2 /* In Bytes */
1769 #define ICE_AQC_NVM_LLDP_CFG_PTR_RD_LEN 2 /* In Bytes */
1771 #define ICE_AQC_NVM_LLDP_PRESERVED_MOD_ID 0x129
1772 #define ICE_AQC_NVM_CUR_LLDP_PERSIST_RD_OFFSET 2 /* In Bytes */
1773 #define ICE_AQC_NVM_LLDP_STATUS_M MAKEMASK(0xF, 0)
1774 #define ICE_AQC_NVM_LLDP_STATUS_M_LEN 4 /* In Bits */
1775 #define ICE_AQC_NVM_LLDP_STATUS_RD_LEN 4 /* In Bytes */
1777 /* Used for 0x0704 as well as for 0x0705 commands */
1778 struct ice_aqc_nvm_cfg {
1780 #define ICE_AQC_ANVM_MULTIPLE_ELEMS BIT(0)
1781 #define ICE_AQC_ANVM_IMMEDIATE_FIELD BIT(1)
1782 #define ICE_AQC_ANVM_NEW_CFG BIT(2)
1791 struct ice_aqc_nvm_cfg_data {
1793 __le16 field_options;
1797 /* NVM Checksum Command (direct, 0x0706) */
1798 struct ice_aqc_nvm_checksum {
1800 #define ICE_AQC_NVM_CHECKSUM_VERIFY BIT(0)
1801 #define ICE_AQC_NVM_CHECKSUM_RECALC BIT(1)
1803 __le16 checksum; /* Used only by response */
1804 #define ICE_AQC_NVM_CHECKSUM_CORRECT 0xBABA
1808 /* Get LLDP MIB (indirect 0x0A00)
1809 * Note: This is also used by the LLDP MIB Change Event (0x0A01)
1810 * as the format is the same.
1812 struct ice_aqc_lldp_get_mib {
1814 #define ICE_AQ_LLDP_MIB_TYPE_S 0
1815 #define ICE_AQ_LLDP_MIB_TYPE_M (0x3 << ICE_AQ_LLDP_MIB_TYPE_S)
1816 #define ICE_AQ_LLDP_MIB_LOCAL 0
1817 #define ICE_AQ_LLDP_MIB_REMOTE 1
1818 #define ICE_AQ_LLDP_MIB_LOCAL_AND_REMOTE 2
1819 #define ICE_AQ_LLDP_BRID_TYPE_S 2
1820 #define ICE_AQ_LLDP_BRID_TYPE_M (0x3 << ICE_AQ_LLDP_BRID_TYPE_S)
1821 #define ICE_AQ_LLDP_BRID_TYPE_NEAREST_BRID 0
1822 #define ICE_AQ_LLDP_BRID_TYPE_NON_TPMR 1
1823 /* Tx pause flags in the 0xA01 event use ICE_AQ_LLDP_TX_* */
1824 #define ICE_AQ_LLDP_TX_S 0x4
1825 #define ICE_AQ_LLDP_TX_M (0x03 << ICE_AQ_LLDP_TX_S)
1826 #define ICE_AQ_LLDP_TX_ACTIVE 0
1827 #define ICE_AQ_LLDP_TX_SUSPENDED 1
1828 #define ICE_AQ_LLDP_TX_FLUSHED 3
1829 /* The following bytes are reserved for the Get LLDP MIB command (0x0A00)
1830 * and in the LLDP MIB Change Event (0x0A01). They are valid for the
1831 * Get LLDP MIB (0x0A00) response only.
1841 /* Configure LLDP MIB Change Event (direct 0x0A01) */
1842 /* For MIB Change Event use ice_aqc_lldp_get_mib structure above */
1843 struct ice_aqc_lldp_set_mib_change {
1845 #define ICE_AQ_LLDP_MIB_UPDATE_ENABLE 0x0
1846 #define ICE_AQ_LLDP_MIB_UPDATE_DIS 0x1
1850 /* Add LLDP TLV (indirect 0x0A02)
1851 * Delete LLDP TLV (indirect 0x0A04)
1853 struct ice_aqc_lldp_add_delete_tlv {
1854 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */
1862 /* Update LLDP TLV (indirect 0x0A03) */
1863 struct ice_aqc_lldp_update_tlv {
1864 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */
1873 /* Stop LLDP (direct 0x0A05) */
1874 struct ice_aqc_lldp_stop {
1876 #define ICE_AQ_LLDP_AGENT_STATE_MASK BIT(0)
1877 #define ICE_AQ_LLDP_AGENT_STOP 0x0
1878 #define ICE_AQ_LLDP_AGENT_SHUTDOWN ICE_AQ_LLDP_AGENT_STATE_MASK
1879 #define ICE_AQ_LLDP_AGENT_PERSIST_DIS BIT(1)
1883 /* Start LLDP (direct 0x0A06) */
1884 struct ice_aqc_lldp_start {
1886 #define ICE_AQ_LLDP_AGENT_START BIT(0)
1887 #define ICE_AQ_LLDP_AGENT_PERSIST_ENA BIT(1)
1891 /* Get CEE DCBX Oper Config (0x0A07)
1892 * The command uses the generic descriptor struct and
1893 * returns the struct below as an indirect response.
1895 struct ice_aqc_get_cee_dcb_cfg_resp {
1900 __le16 oper_app_prio;
1901 #define ICE_AQC_CEE_APP_FCOE_S 0
1902 #define ICE_AQC_CEE_APP_FCOE_M (0x7 << ICE_AQC_CEE_APP_FCOE_S)
1903 #define ICE_AQC_CEE_APP_ISCSI_S 3
1904 #define ICE_AQC_CEE_APP_ISCSI_M (0x7 << ICE_AQC_CEE_APP_ISCSI_S)
1905 #define ICE_AQC_CEE_APP_FIP_S 8
1906 #define ICE_AQC_CEE_APP_FIP_M (0x7 << ICE_AQC_CEE_APP_FIP_S)
1908 #define ICE_AQC_CEE_PG_STATUS_S 0
1909 #define ICE_AQC_CEE_PG_STATUS_M (0x7 << ICE_AQC_CEE_PG_STATUS_S)
1910 #define ICE_AQC_CEE_PFC_STATUS_S 3
1911 #define ICE_AQC_CEE_PFC_STATUS_M (0x7 << ICE_AQC_CEE_PFC_STATUS_S)
1912 #define ICE_AQC_CEE_FCOE_STATUS_S 8
1913 #define ICE_AQC_CEE_FCOE_STATUS_M (0x7 << ICE_AQC_CEE_FCOE_STATUS_S)
1914 #define ICE_AQC_CEE_ISCSI_STATUS_S 11
1915 #define ICE_AQC_CEE_ISCSI_STATUS_M (0x7 << ICE_AQC_CEE_ISCSI_STATUS_S)
1916 #define ICE_AQC_CEE_FIP_STATUS_S 16
1917 #define ICE_AQC_CEE_FIP_STATUS_M (0x7 << ICE_AQC_CEE_FIP_STATUS_S)
1921 /* Set Local LLDP MIB (indirect 0x0A08)
1922 * Used to replace the local MIB of a given LLDP agent. e.g. DCBX
1924 struct ice_aqc_lldp_set_local_mib {
1926 #define SET_LOCAL_MIB_TYPE_DCBX_M BIT(0)
1927 #define SET_LOCAL_MIB_TYPE_LOCAL_MIB 0
1928 #define SET_LOCAL_MIB_TYPE_CEE_M BIT(1)
1929 #define SET_LOCAL_MIB_TYPE_CEE_WILLING 0
1930 #define SET_LOCAL_MIB_TYPE_CEE_NON_WILLING SET_LOCAL_MIB_TYPE_CEE_M
1938 struct ice_aqc_lldp_set_local_mib_resp {
1940 #define SET_LOCAL_MIB_RESP_EVENT_M BIT(0)
1941 #define SET_LOCAL_MIB_RESP_MIB_CHANGE_SILENT 0
1942 #define SET_LOCAL_MIB_RESP_MIB_CHANGE_EVENT SET_LOCAL_MIB_RESP_EVENT_M
1946 /* Stop/Start LLDP Agent (direct 0x0A09)
1947 * Used for stopping/starting specific LLDP agent. e.g. DCBX.
1948 * The same structure is used for the response, with the command field
1949 * being used as the status field.
1951 struct ice_aqc_lldp_stop_start_specific_agent {
1953 #define ICE_AQC_START_STOP_AGENT_M BIT(0)
1954 #define ICE_AQC_START_STOP_AGENT_STOP_DCBX 0
1955 #define ICE_AQC_START_STOP_AGENT_START_DCBX ICE_AQC_START_STOP_AGENT_M
1959 /* LLDP Filter Control (direct 0x0A0A) */
1960 struct ice_aqc_lldp_filter_ctrl {
1962 #define ICE_AQC_LLDP_FILTER_ACTION_M MAKEMASK(3, 0)
1963 #define ICE_AQC_LLDP_FILTER_ACTION_ADD 0x0
1964 #define ICE_AQC_LLDP_FILTER_ACTION_DELETE 0x1
1965 #define ICE_AQC_LLDP_FILTER_ACTION_UPDATE 0x2
1971 /* Get/Set RSS key (indirect 0x0B04/0x0B02) */
1972 struct ice_aqc_get_set_rss_key {
1973 #define ICE_AQC_GSET_RSS_KEY_VSI_VALID BIT(15)
1974 #define ICE_AQC_GSET_RSS_KEY_VSI_ID_S 0
1975 #define ICE_AQC_GSET_RSS_KEY_VSI_ID_M (0x3FF << ICE_AQC_GSET_RSS_KEY_VSI_ID_S)
1982 #define ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE 0x28
1983 #define ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE 0xC
1984 #define ICE_GET_SET_RSS_KEY_EXTEND_KEY_SIZE \
1985 (ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE + \
1986 ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE)
1989 * struct ice_aqc_get_set_rss_keys - Get/Set RSS hash key command buffer
1990 * @standard_rss_key: 40 most significant bytes of hash key
1991 * @extended_hash_key: 12 least significant bytes of hash key
1993 * Set/Get 40 byte hash key using standard_rss_key field, and set
1994 * extended_hash_key field to zero. Set/Get 52 byte hash key using
1995 * standard_rss_key field for 40 most significant bytes and the
1996 * extended_hash_key field for the 12 least significant bytes of hash key.
1998 struct ice_aqc_get_set_rss_keys {
1999 u8 standard_rss_key[ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE];
2000 u8 extended_hash_key[ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE];
2003 /* Get/Set RSS LUT (indirect 0x0B05/0x0B03) */
2004 struct ice_aqc_get_set_rss_lut {
2005 #define ICE_AQC_GSET_RSS_LUT_VSI_VALID BIT(15)
2006 #define ICE_AQC_GSET_RSS_LUT_VSI_ID_S 0
2007 #define ICE_AQC_GSET_RSS_LUT_VSI_ID_M (0x3FF << ICE_AQC_GSET_RSS_LUT_VSI_ID_S)
2009 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S 0
2010 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_M \
2011 (0x3 << ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S)
2013 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_VSI 0
2014 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF 1
2015 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL 2
2017 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S 2
2018 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M \
2019 (0x3 << ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S)
2021 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128 128
2022 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128_FLAG 0
2023 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512 512
2024 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512_FLAG 1
2025 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K 2048
2026 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K_FLAG 2
2028 #define ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S 4
2029 #define ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_M \
2030 (0xF << ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S)
2038 /* Clear FD Table Command (direct, 0x0B06) */
2039 struct ice_aqc_clear_fd_table {
2041 #define CL_FD_VM_VF_TYPE_VSI_IDX 1
2042 #define CL_FD_VM_VF_TYPE_PF_IDX 2
2048 /* Allocate ACL table (indirect 0x0C10) */
2049 #define ICE_AQC_ACL_KEY_WIDTH 40
2050 #define ICE_AQC_ACL_KEY_WIDTH_BYTES 5
2051 #define ICE_AQC_ACL_TCAM_DEPTH 512
2052 #define ICE_ACL_ENTRY_ALLOC_UNIT 64
2053 #define ICE_AQC_MAX_CONCURRENT_ACL_TBL 15
2054 #define ICE_AQC_MAX_ACTION_MEMORIES 20
2055 #define ICE_AQC_MAX_ACTION_ENTRIES 512
2056 #define ICE_AQC_ACL_SLICES 16
2057 #define ICE_AQC_ALLOC_ID_LESS_THAN_4K 0x1000
2058 /* The ACL block supports up to 8 actions per a single output. */
2059 #define ICE_AQC_TBL_MAX_ACTION_PAIRS 4
2061 #define ICE_AQC_MAX_TCAM_ALLOC_UNITS (ICE_AQC_ACL_TCAM_DEPTH / \
2062 ICE_ACL_ENTRY_ALLOC_UNIT)
2063 #define ICE_AQC_ACL_ALLOC_UNITS (ICE_AQC_ACL_SLICES * \
2064 ICE_AQC_MAX_TCAM_ALLOC_UNITS)
2066 struct ice_aqc_acl_alloc_table {
2069 u8 act_pairs_per_entry;
2070 /* For non-concurrent table allocation, this field needs
2071 * to be set to zero(0) otherwise it shall specify the
2072 * amount of concurrent tables whose AllocIDs are
2073 * specified in buffer. Thus the newly allocated table
2074 * is concurrent with table IDs specified in AllocIDs.
2076 #define ICE_AQC_ACL_ALLOC_TABLE_TYPE_NONCONCURR 0
2083 /* Allocate ACL table command buffer format */
2084 struct ice_aqc_acl_alloc_table_data {
2085 /* Dependent table AllocIDs. Each word in this 15 word array specifies
2086 * a dependent table AllocID according to the amount specified in the
2087 * "table_type" field. All unused words shall be set to 0xFFFF
2089 #define ICE_AQC_CONCURR_ID_INVALID 0xffff
2090 __le16 alloc_ids[ICE_AQC_MAX_CONCURRENT_ACL_TBL];
2093 /* Deallocate ACL table (indirect 0x0C11)
2094 * Allocate ACL action-pair (indirect 0x0C12)
2095 * Deallocate ACL action-pair (indirect 0x0C13)
2098 /* Following structure is common and used in case of deallocation
2099 * of ACL table and action-pair
2101 struct ice_aqc_acl_tbl_actpair {
2102 /* Alloc ID of the table being released */
2109 /* This response structure is same in case of alloc/dealloc table,
2110 * alloc/dealloc action-pair
2112 struct ice_aqc_acl_generic {
2113 /* if alloc_id is below 0x1000 then alllocation failed due to
2114 * unavailable resources, else this is set by FW to identify
2120 /* to be used only in case of alloc/dealloc table */
2122 /* Index of the first TCAM block, otherwise set to 0xFF
2123 * for a failed allocation
2126 /* Index of the last TCAM block. This index shall be
2127 * set to the value of first_tcam for single TCAM block
2128 * allocation, otherwise set to 0xFF for a failed
2133 /* reserved in case of alloc/dealloc action-pair */
2139 /* index of first entry (in both TCAM and action memories),
2140 * otherwise set to 0xFF for a failed allocation
2143 /* index of last entry (in both TCAM and action memories),
2144 * otherwise set to 0xFF for a failed allocation
2148 /* Each act_mem element specifies the order of the memory
2151 u8 act_mem[ICE_AQC_MAX_ACTION_MEMORIES];
2154 /* Allocate ACL scenario (indirect 0x0C14). This command doesn't have separate
2155 * response buffer since original command buffer gets updated with
2156 * 'scen_id' in case of success
2158 struct ice_aqc_acl_alloc_scen {
2172 /* De-allocate ACL scenario (direct 0x0C15). This command doesn't need
2173 * separate response buffer since nothing to be returned as a response
2176 struct ice_aqc_acl_dealloc_scen {
2181 /* Update ACL scenario (direct 0x0C1B)
2182 * Query ACL scenario (direct 0x0C23)
2184 struct ice_aqc_acl_update_query_scen {
2191 /* Input buffer format in case allocate/update ACL scenario and same format
2192 * is used for response buffer in case of query ACL scenario.
2193 * NOTE: de-allocate ACL scenario is direct command and doesn't require
2194 * "buffer", hence no buffer format.
2196 struct ice_aqc_acl_scen {
2198 /* Byte [x] selection for the TCAM key. This value must be
2199 * set to 0x0 for unusued TCAM.
2200 * Only Bit 6..0 is used in each byte and MSB is reserved
2202 #define ICE_AQC_ACL_ALLOC_SCE_SELECT_M 0x7F
2203 #define ICE_AQC_ACL_BYTE_SEL_BASE 0x20
2204 #define ICE_AQC_ACL_BYTE_SEL_BASE_PID 0x3E
2205 #define ICE_AQC_ACL_BYTE_SEL_BASE_PKT_DIR ICE_AQC_ACL_BYTE_SEL_BASE
2206 #define ICE_AQC_ACL_BYTE_SEL_BASE_RNG_CHK 0x3F
2208 /* TCAM Block entry masking. This value should be set to 0x0 for
2212 /* Bit 0 : masks TCAM entries 0-63
2213 * Bit 1 : masks TCAM entries 64-127
2214 * Bit 2 to 7 : follow the pattern of bit 0 and 1
2216 #define ICE_AQC_ACL_ALLOC_SCE_START_CMP BIT(0)
2217 #define ICE_AQC_ACL_ALLOC_SCE_START_SET BIT(1)
2220 } tcam_cfg[ICE_AQC_ACL_SLICES];
2222 /* Each byte, Bit 6..0: Action memory association to a TCAM block,
2223 * otherwise it shall be set to 0x0 for disabled memory action.
2224 * Bit 7 : Action memory enable for this scenario
2226 #define ICE_AQC_ACL_SCE_ACT_MEM_TCAM_ASSOC_M 0x7F
2227 #define ICE_AQC_ACL_SCE_ACT_MEM_EN BIT(7)
2228 u8 act_mem_cfg[ICE_AQC_MAX_ACTION_MEMORIES];
2231 /* Allocate ACL counters (indirect 0x0C16) */
2232 struct ice_aqc_acl_alloc_counters {
2233 /* Amount of contiguous counters requested. Min value is 1 and
2236 #define ICE_AQC_ACL_ALLOC_CNT_MIN_AMT 0x1
2237 #define ICE_AQC_ACL_ALLOC_CNT_MAX_AMT 0xFF
2240 /* Counter type: 'single counter' which can be configured to count
2241 * either bytes or packets
2243 #define ICE_AQC_ACL_CNT_TYPE_SINGLE 0x0
2245 /* Counter type: 'counter pair' which counts number of bytes and number
2248 #define ICE_AQC_ACL_CNT_TYPE_DUAL 0x1
2249 /* requested counter type, single/dual */
2252 /* counter bank allocation shall be 0-3 for 'byte or packet counter' */
2253 #define ICE_AQC_ACL_MAX_CNT_SINGLE 0x3
2254 /* counter bank allocation shall be 0-1 for 'byte and packet counter dual' */
2255 #define ICE_AQC_ACL_MAX_CNT_DUAL 0x1
2256 /* requested counter bank allocation */
2262 /* Applicable only in case of command */
2266 /* Applicable only in case of response */
2267 #define ICE_AQC_ACL_ALLOC_CNT_INVAL 0xFFFF
2269 /* Index of first allocated counter. 0xFFFF in case
2270 * of unsuccessful allocation
2272 __le16 first_counter;
2273 /* Index of last allocated counter. 0xFFFF in case
2274 * of unsuccessful allocation
2276 __le16 last_counter;
2282 /* De-allocate ACL counters (direct 0x0C17) */
2283 struct ice_aqc_acl_dealloc_counters {
2284 /* first counter being released */
2285 __le16 first_counter;
2286 /* last counter being released */
2287 __le16 last_counter;
2288 /* requested counter type, single/dual */
2290 /* requested counter bank allocation */
2295 /* De-allocate ACL resources (direct 0x0C1A). Used by SW to release all the
2296 * resources allocated for it using a single command
2298 struct ice_aqc_acl_dealloc_res {
2302 /* Program ACL actionpair (indirect 0x0C1C)
2303 * Query ACL actionpair (indirect 0x0C25)
2305 struct ice_aqc_acl_actpair {
2306 /* action mem index to program/update */
2309 /* The entry index in action memory to be programmed/updated */
2310 __le16 act_entry_index;
2316 /* Input buffer format for program/query action-pair admin command */
2317 struct ice_acl_act_entry {
2318 /* Action priority, values must be between 0..7 */
2319 #define ICE_AQC_ACT_PRIO_VALID_MAX 7
2320 #define ICE_AQC_ACT_PRIO_MSK MAKEMASK(0xff, 0)
2322 /* Action meta-data identifier. This field should be set to 0x0
2325 #define ICE_AQC_ACT_MDID_S 8
2326 #define ICE_AQC_ACT_MDID_MSK MAKEMASK(0xff00, ICE_AQC_ACT_MDID_S)
2329 #define ICE_AQC_ACT_VALUE_S 16
2330 #define ICE_AQC_ACT_VALUE_MSK MAKEMASK(0xffff0000, 16)
2334 #define ICE_ACL_NUM_ACT_PER_ACT_PAIR 2
2335 struct ice_aqc_actpair {
2336 struct ice_acl_act_entry act[ICE_ACL_NUM_ACT_PER_ACT_PAIR];
2339 /* Generic format used to describe either input or response buffer
2340 * for admin commands related to ACL profile
2342 struct ice_aqc_acl_prof_generic_frmt {
2343 /* The first byte of the byte selection base is reserved to keep the
2344 * first byte of the field vector where the packet direction info is
2345 * available. Thus we should start at index 1 of the field vector to
2346 * map its entries to the byte selection base.
2348 #define ICE_AQC_ACL_PROF_BYTE_SEL_START_IDX 1
2350 * Bit 0..5 = Byte selection for the byte selection base from the
2351 * extracted fields (expressed as byte offset in extracted fields).
2352 * Applicable values are 0..63
2353 * Bit 6..7 = Reserved
2355 #define ICE_AQC_ACL_PROF_BYTE_SEL_ELEMS 30
2356 u8 byte_selection[ICE_AQC_ACL_PROF_BYTE_SEL_ELEMS];
2358 * Bit 0..4 = Word selection for the word selection base from the
2359 * extracted fields (expressed as word offset in extracted fields).
2360 * Applicable values are 0..31
2361 * Bit 5..7 = Reserved
2363 #define ICE_AQC_ACL_PROF_WORD_SEL_ELEMS 32
2364 u8 word_selection[ICE_AQC_ACL_PROF_WORD_SEL_ELEMS];
2366 * Bit 0..3 = Double word selection for the double-word selection base
2367 * from the extracted fields (expressed as double-word offset in
2368 * extracted fields).
2369 * Applicable values are 0..15
2370 * Bit 4..7 = Reserved
2372 #define ICE_AQC_ACL_PROF_DWORD_SEL_ELEMS 15
2373 u8 dword_selection[ICE_AQC_ACL_PROF_DWORD_SEL_ELEMS];
2374 /* Scenario numbers for individual Physical Function's */
2375 #define ICE_AQC_ACL_PROF_PF_SCEN_NUM_ELEMS 8
2376 u8 pf_scenario_num[ICE_AQC_ACL_PROF_PF_SCEN_NUM_ELEMS];
2379 /* Program ACL profile extraction (indirect 0x0C1D)
2380 * Program ACL profile ranges (indirect 0x0C1E)
2381 * Query ACL profile (indirect 0x0C21)
2382 * Query ACL profile ranges (indirect 0x0C22)
2384 struct ice_aqc_acl_profile {
2385 u8 profile_id; /* Programmed/Updated profile ID */
2391 /* Input buffer format for program profile extraction admin command and
2392 * response buffer format for query profile admin command is as defined
2393 * in struct ice_aqc_acl_prof_generic_frmt
2396 /* Input buffer format for program profile ranges and query profile ranges
2397 * admin commands. Same format is used for response buffer in case of query
2398 * profile ranges command
2400 struct ice_acl_rng_data {
2401 /* The range checker output shall be sent when the value
2402 * related to this range checker is lower than low boundary
2404 __be16 low_boundary;
2405 /* The range checker output shall be sent when the value
2406 * related to this range checker is higher than high boundary
2408 __be16 high_boundary;
2409 /* A value of '0' in bit shall clear the relevant bit input
2410 * to the range checker
2415 struct ice_aqc_acl_profile_ranges {
2416 #define ICE_AQC_ACL_PROF_RANGES_NUM_CFG 8
2417 struct ice_acl_rng_data checker_cfg[ICE_AQC_ACL_PROF_RANGES_NUM_CFG];
2420 /* Program ACL entry (indirect 0x0C20)
2421 * Query ACL entry (indirect 0x0C24)
2423 struct ice_aqc_acl_entry {
2424 u8 tcam_index; /* Updated TCAM block index */
2426 __le16 entry_index; /* Updated entry index */
2432 /* Input buffer format in case of program ACL entry and response buffer format
2433 * in case of query ACL entry
2435 struct ice_aqc_acl_data {
2436 /* Entry key and entry key invert are 40 bits wide.
2437 * Byte 0..4 : entry key and Byte 5..7 are reserved
2438 * Byte 8..12: entry key invert and Byte 13..15 are reserved
2443 } entry_key, entry_key_invert;
2446 /* Query ACL counter (direct 0x0C27) */
2447 struct ice_aqc_acl_query_counter {
2448 /* Queried counter index */
2449 __le16 counter_index;
2450 /* Queried counter bank */
2457 /* Holds counter value/packet counter value */
2464 /* Add Tx LAN Queues (indirect 0x0C30) */
2465 struct ice_aqc_add_txqs {
2473 /* This is the descriptor of each queue entry for the Add Tx LAN Queues
2474 * command (0x0C30). Only used within struct ice_aqc_add_tx_qgrp.
2476 struct ice_aqc_add_txqs_perq {
2482 struct ice_aqc_txsched_elem info;
2485 /* The format of the command buffer for Add Tx LAN Queues (0x0C30)
2486 * is an array of the following structs. Please note that the length of
2487 * each struct ice_aqc_add_tx_qgrp is variable due
2488 * to the variable number of queues in each group!
2490 struct ice_aqc_add_tx_qgrp {
2494 struct ice_aqc_add_txqs_perq txqs[STRUCT_HACK_VAR_LEN];
2497 /* Disable Tx LAN Queues (indirect 0x0C31) */
2498 struct ice_aqc_dis_txqs {
2500 #define ICE_AQC_Q_DIS_CMD_S 0
2501 #define ICE_AQC_Q_DIS_CMD_M (0x3 << ICE_AQC_Q_DIS_CMD_S)
2502 #define ICE_AQC_Q_DIS_CMD_NO_FUNC_RESET (0 << ICE_AQC_Q_DIS_CMD_S)
2503 #define ICE_AQC_Q_DIS_CMD_VM_RESET BIT(ICE_AQC_Q_DIS_CMD_S)
2504 #define ICE_AQC_Q_DIS_CMD_VF_RESET (2 << ICE_AQC_Q_DIS_CMD_S)
2505 #define ICE_AQC_Q_DIS_CMD_PF_RESET (3 << ICE_AQC_Q_DIS_CMD_S)
2506 #define ICE_AQC_Q_DIS_CMD_SUBSEQ_CALL BIT(2)
2507 #define ICE_AQC_Q_DIS_CMD_FLUSH_PIPE BIT(3)
2509 __le16 vmvf_and_timeout;
2510 #define ICE_AQC_Q_DIS_VMVF_NUM_S 0
2511 #define ICE_AQC_Q_DIS_VMVF_NUM_M (0x3FF << ICE_AQC_Q_DIS_VMVF_NUM_S)
2512 #define ICE_AQC_Q_DIS_TIMEOUT_S 10
2513 #define ICE_AQC_Q_DIS_TIMEOUT_M (0x3F << ICE_AQC_Q_DIS_TIMEOUT_S)
2514 __le32 blocked_cgds;
2519 /* The buffer for Disable Tx LAN Queues (indirect 0x0C31)
2520 * contains the following structures, arrayed one after the
2522 * Note: Since the q_id is 16 bits wide, if the
2523 * number of queues is even, then 2 bytes of alignment MUST be
2524 * added before the start of the next group, to allow correct
2525 * alignment of the parent_teid field.
2528 struct ice_aqc_dis_txq_item {
2532 /* The length of the q_id array varies according to num_qs */
2533 #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S 15
2534 #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_LAN_Q \
2535 (0 << ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S)
2536 #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_RDMA_QSET \
2537 (1 << ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S)
2538 __le16 q_id[STRUCT_HACK_VAR_LEN];
2543 /* Tx LAN Queues Cleanup Event (0x0C31) */
2544 struct ice_aqc_txqs_cleanup {
2550 /* Move / Reconfigure Tx Queues (indirect 0x0C32) */
2551 struct ice_aqc_move_txqs {
2553 #define ICE_AQC_Q_CMD_TYPE_S 0
2554 #define ICE_AQC_Q_CMD_TYPE_M (0x3 << ICE_AQC_Q_CMD_TYPE_S)
2555 #define ICE_AQC_Q_CMD_TYPE_MOVE 1
2556 #define ICE_AQC_Q_CMD_TYPE_TC_CHANGE 2
2557 #define ICE_AQC_Q_CMD_TYPE_MOVE_AND_TC 3
2558 #define ICE_AQC_Q_CMD_SUBSEQ_CALL BIT(2)
2559 #define ICE_AQC_Q_CMD_FLUSH_PIPE BIT(3)
2563 #define ICE_AQC_Q_CMD_TIMEOUT_S 2
2564 #define ICE_AQC_Q_CMD_TIMEOUT_M (0x3F << ICE_AQC_Q_CMD_TIMEOUT_S)
2565 __le32 blocked_cgds;
2570 /* Per-queue data buffer for the Move Tx LAN Queues command/response */
2571 struct ice_aqc_move_txqs_elem {
2578 /* Indirect data buffer for the Move Tx LAN Queues command/response */
2579 struct ice_aqc_move_txqs_data {
2582 struct ice_aqc_move_txqs_elem txqs[STRUCT_HACK_VAR_LEN];
2585 /* Download Package (indirect 0x0C40) */
2586 /* Also used for Update Package (indirect 0x0C42 and 0x0C41) */
2587 struct ice_aqc_download_pkg {
2589 #define ICE_AQC_DOWNLOAD_PKG_LAST_BUF 0x01
2596 struct ice_aqc_download_pkg_resp {
2597 __le32 error_offset;
2603 /* Get Package Info List (indirect 0x0C43) */
2604 struct ice_aqc_get_pkg_info_list {
2611 /* Version format for packages */
2612 struct ice_pkg_ver {
2619 #define ICE_PKG_NAME_SIZE 32
2620 #define ICE_SEG_ID_SIZE 28
2621 #define ICE_SEG_NAME_SIZE 28
2623 struct ice_aqc_get_pkg_info {
2624 struct ice_pkg_ver ver;
2625 char name[ICE_SEG_NAME_SIZE];
2629 u8 is_active_at_boot;
2633 /* Get Package Info List response buffer format (0x0C43) */
2634 struct ice_aqc_get_pkg_info_resp {
2636 struct ice_aqc_get_pkg_info pkg_info[STRUCT_HACK_VAR_LEN];
2639 /* Driver Shared Parameters (direct, 0x0C90) */
2640 struct ice_aqc_driver_shared_params {
2642 #define ICE_AQC_DRIVER_PARAM_OP_MASK BIT(0)
2643 #define ICE_AQC_DRIVER_PARAM_SET 0
2644 #define ICE_AQC_DRIVER_PARAM_GET 1
2646 #define ICE_AQC_DRIVER_PARAM_MAX_IDX 15
2653 /* Lan Queue Overflow Event (direct, 0x1001) */
2654 struct ice_aqc_event_lan_overflow {
2655 __le32 prtdcb_ruptq;
2660 /* Set Health Status (direct 0xFF20) */
2661 struct ice_aqc_set_health_status_config {
2663 #define ICE_AQC_HEALTH_STATUS_SET_PF_SPECIFIC_MASK BIT(0)
2664 #define ICE_AQC_HEALTH_STATUS_SET_ALL_PF_MASK BIT(1)
2665 #define ICE_AQC_HEALTH_STATUS_SET_GLOBAL_MASK BIT(2)
2669 #define ICE_AQC_HEALTH_STATUS_ERR_UNKNOWN_MOD_STRICT 0x101
2670 #define ICE_AQC_HEALTH_STATUS_ERR_MOD_TYPE 0x102
2671 #define ICE_AQC_HEALTH_STATUS_ERR_MOD_QUAL 0x103
2672 #define ICE_AQC_HEALTH_STATUS_ERR_MOD_COMM 0x104
2673 #define ICE_AQC_HEALTH_STATUS_ERR_MOD_CONFLICT 0x105
2674 #define ICE_AQC_HEALTH_STATUS_ERR_MOD_NOT_PRESENT 0x106
2675 #define ICE_AQC_HEALTH_STATUS_INFO_MOD_UNDERUTILIZED 0x107
2676 #define ICE_AQC_HEALTH_STATUS_ERR_UNKNOWN_MOD_LENIENT 0x108
2677 #define ICE_AQC_HEALTH_STATUS_ERR_INVALID_LINK_CFG 0x10B
2678 #define ICE_AQC_HEALTH_STATUS_ERR_PORT_ACCESS 0x10C
2679 #define ICE_AQC_HEALTH_STATUS_ERR_PORT_UNREACHABLE 0x10D
2680 #define ICE_AQC_HEALTH_STATUS_INFO_PORT_SPEED_MOD_LIMITED 0x10F
2681 #define ICE_AQC_HEALTH_STATUS_ERR_PARALLEL_FAULT 0x110
2682 #define ICE_AQC_HEALTH_STATUS_INFO_PORT_SPEED_PHY_LIMITED 0x111
2683 #define ICE_AQC_HEALTH_STATUS_ERR_NETLIST_TOPO 0x112
2684 #define ICE_AQC_HEALTH_STATUS_ERR_NETLIST 0x113
2685 #define ICE_AQC_HEALTH_STATUS_ERR_TOPO_CONFLICT 0x114
2686 #define ICE_AQC_HEALTH_STATUS_ERR_LINK_HW_ACCESS 0x115
2687 #define ICE_AQC_HEALTH_STATUS_ERR_LINK_RUNTIME 0x116
2688 #define ICE_AQC_HEALTH_STATUS_ERR_DNL_INIT 0x117
2689 #define ICE_AQC_HEALTH_STATUS_INFO_RECOVERY 0x500
2690 #define ICE_AQC_HEALTH_STATUS_ERR_FLASH_ACCESS 0x501
2691 #define ICE_AQC_HEALTH_STATUS_ERR_NVM_AUTH 0x502
2692 #define ICE_AQC_HEALTH_STATUS_ERR_OROM_AUTH 0x503
2693 #define ICE_AQC_HEALTH_STATUS_ERR_DDP_AUTH 0x504
2694 #define ICE_AQC_HEALTH_STATUS_ERR_NVM_COMPAT 0x505
2695 #define ICE_AQC_HEALTH_STATUS_ERR_OROM_COMPAT 0x506
2696 #define ICE_AQC_HEALTH_STATUS_ERR_DCB_MIB 0x509
2698 /* Get Health Status codes (indirect 0xFF21) */
2699 struct ice_aqc_get_supported_health_status_codes {
2700 __le16 health_code_count;
2706 /* Get Health Status (indirect 0xFF22) */
2707 struct ice_aqc_get_health_status {
2708 __le16 health_status_count;
2714 /* Get Health Status event buffer entry, (0xFF22)
2715 * repeated per reported health status
2717 struct ice_aqc_health_status_elem {
2718 __le16 health_status_code;
2719 __le16 event_source;
2720 #define ICE_AQC_HEALTH_STATUS_PF (0x1)
2721 #define ICE_AQC_HEALTH_STATUS_PORT (0x2)
2722 #define ICE_AQC_HEALTH_STATUS_GLOBAL (0x3)
2723 __le32 internal_data1;
2724 #define ICE_AQC_HEALTH_STATUS_UNDEFINED_DATA (0xDEADBEEF)
2725 __le32 internal_data2;
2728 /* Clear Health Status (direct 0xFF23) */
2729 struct ice_aqc_clear_health_status {
2733 /* Set FW Logging configuration (indirect 0xFF30)
2734 * Register for FW Logging (indirect 0xFF31)
2735 * Query FW Logging (indirect 0xFF32)
2736 * FW Log Event (indirect 0xFF33)
2737 * Get FW Log (indirect 0xFF34)
2738 * Clear FW Log (indirect 0xFF35)
2741 struct ice_aqc_fw_log {
2743 #define ICE_AQC_FW_LOG_CONF_UART_EN BIT(0)
2744 #define ICE_AQC_FW_LOG_CONF_AQ_EN BIT(1)
2745 #define ICE_AQC_FW_LOG_CONF_SET_VALID BIT(3)
2746 #define ICE_AQC_FW_LOG_AQ_REGISTER BIT(0)
2747 #define ICE_AQC_FW_LOG_AQ_QUERY BIT(2)
2748 #define ICE_AQC_FW_LOG_PERSISTENT BIT(0)
2750 #define ICE_AQC_FW_LOG_MORE_DATA BIT(1)
2757 __le16 log_resolution;
2758 #define ICE_AQC_FW_LOG_MIN_RESOLUTION (1)
2759 #define ICE_AQC_FW_LOG_MAX_RESOLUTION (128)
2767 /* Response Buffer for:
2768 * Set Firmware Logging Configuration (0xFF30)
2769 * Query FW Logging (0xFF32)
2771 struct ice_aqc_fw_log_cfg_resp {
2772 __le16 module_identifier;
2778 * struct ice_aq_desc - Admin Queue (AQ) descriptor
2779 * @flags: ICE_AQ_FLAG_* flags
2780 * @opcode: AQ command opcode
2781 * @datalen: length in bytes of indirect/external data buffer
2782 * @retval: return value from firmware
2783 * @cookie_high: opaque data high-half
2784 * @cookie_low: opaque data low-half
2785 * @params: command-specific parameters
2787 * Descriptor format for commands the driver posts on the Admin Transmit Queue
2788 * (ATQ). The firmware writes back onto the command descriptor and returns
2789 * the result of the command. Asynchronous events that are not an immediate
2790 * result of the command are written to the Admin Receive Queue (ARQ) using
2791 * the same descriptor format. Descriptors are in little-endian notation with
2794 struct ice_aq_desc {
2803 struct ice_aqc_generic generic;
2804 struct ice_aqc_get_ver get_ver;
2805 struct ice_aqc_driver_ver driver_ver;
2806 struct ice_aqc_q_shutdown q_shutdown;
2807 struct ice_aqc_req_res res_owner;
2808 struct ice_aqc_manage_mac_read mac_read;
2809 struct ice_aqc_manage_mac_write mac_write;
2810 struct ice_aqc_clear_pxe clear_pxe;
2811 struct ice_aqc_config_no_drop_policy no_drop;
2812 struct ice_aqc_add_update_mir_rule add_update_rule;
2813 struct ice_aqc_delete_mir_rule del_rule;
2814 struct ice_aqc_list_caps get_cap;
2815 struct ice_aqc_get_phy_caps get_phy;
2816 struct ice_aqc_set_phy_cfg set_phy;
2817 struct ice_aqc_restart_an restart_an;
2818 struct ice_aqc_sff_eeprom read_write_sff_param;
2819 struct ice_aqc_set_port_id_led set_port_id_led;
2820 struct ice_aqc_get_sw_cfg get_sw_conf;
2821 struct ice_aqc_set_port_params set_port_params;
2822 struct ice_aqc_sw_rules sw_rules;
2823 struct ice_aqc_storm_cfg storm_conf;
2824 struct ice_aqc_add_get_recipe add_get_recipe;
2825 struct ice_aqc_recipe_to_profile recipe_to_profile;
2826 struct ice_aqc_get_topo get_topo;
2827 struct ice_aqc_sched_elem_cmd sched_elem_cmd;
2828 struct ice_aqc_query_txsched_res query_sched_res;
2829 struct ice_aqc_query_node_to_root query_node_to_root;
2830 struct ice_aqc_cfg_l2_node_cgd cfg_l2_node_cgd;
2831 struct ice_aqc_query_port_ets port_ets;
2832 struct ice_aqc_rl_profile rl_profile;
2833 struct ice_aqc_nvm nvm;
2834 struct ice_aqc_nvm_cfg nvm_cfg;
2835 struct ice_aqc_nvm_checksum nvm_checksum;
2836 struct ice_aqc_pfc_ignore pfc_ignore;
2837 struct ice_aqc_set_query_pfc_mode set_query_pfc_mode;
2838 struct ice_aqc_set_dcb_params set_dcb_params;
2839 struct ice_aqc_lldp_get_mib lldp_get_mib;
2840 struct ice_aqc_lldp_set_mib_change lldp_set_event;
2841 struct ice_aqc_lldp_add_delete_tlv lldp_add_delete_tlv;
2842 struct ice_aqc_lldp_update_tlv lldp_update_tlv;
2843 struct ice_aqc_lldp_stop lldp_stop;
2844 struct ice_aqc_lldp_start lldp_start;
2845 struct ice_aqc_lldp_set_local_mib lldp_set_mib;
2846 struct ice_aqc_lldp_stop_start_specific_agent lldp_agent_ctrl;
2847 struct ice_aqc_lldp_filter_ctrl lldp_filter_ctrl;
2848 struct ice_aqc_get_set_rss_lut get_set_rss_lut;
2849 struct ice_aqc_get_set_rss_key get_set_rss_key;
2850 struct ice_aqc_clear_fd_table clear_fd_table;
2851 struct ice_aqc_acl_alloc_table alloc_table;
2852 struct ice_aqc_acl_tbl_actpair tbl_actpair;
2853 struct ice_aqc_acl_alloc_scen alloc_scen;
2854 struct ice_aqc_acl_dealloc_scen dealloc_scen;
2855 struct ice_aqc_acl_update_query_scen update_query_scen;
2856 struct ice_aqc_acl_alloc_counters alloc_counters;
2857 struct ice_aqc_acl_dealloc_counters dealloc_counters;
2858 struct ice_aqc_acl_dealloc_res dealloc_res;
2859 struct ice_aqc_acl_entry program_query_entry;
2860 struct ice_aqc_acl_actpair program_query_actpair;
2861 struct ice_aqc_acl_profile profile;
2862 struct ice_aqc_acl_query_counter query_counter;
2863 struct ice_aqc_add_txqs add_txqs;
2864 struct ice_aqc_dis_txqs dis_txqs;
2865 struct ice_aqc_move_txqs move_txqs;
2866 struct ice_aqc_txqs_cleanup txqs_cleanup;
2867 struct ice_aqc_add_get_update_free_vsi vsi_cmd;
2868 struct ice_aqc_add_update_free_vsi_resp add_update_free_vsi_res;
2869 struct ice_aqc_get_vsi_resp get_vsi_resp;
2870 struct ice_aqc_download_pkg download_pkg;
2871 struct ice_aqc_get_pkg_info_list get_pkg_info_list;
2872 struct ice_aqc_driver_shared_params drv_shared_params;
2873 struct ice_aqc_set_mac_lb set_mac_lb;
2874 struct ice_aqc_alloc_free_res_cmd sw_res_ctrl;
2875 struct ice_aqc_get_res_alloc get_res;
2876 struct ice_aqc_get_allocd_res_desc get_res_desc;
2877 struct ice_aqc_set_mac_cfg set_mac_cfg;
2878 struct ice_aqc_set_event_mask set_event_mask;
2879 struct ice_aqc_get_link_status get_link_status;
2880 struct ice_aqc_event_lan_overflow lan_overflow;
2881 struct ice_aqc_get_link_topo get_link_topo;
2882 struct ice_aqc_set_health_status_config
2883 set_health_status_config;
2884 struct ice_aqc_get_supported_health_status_codes
2885 get_supported_health_status_codes;
2886 struct ice_aqc_get_health_status get_health_status;
2887 struct ice_aqc_clear_health_status clear_health_status;
2891 /* FW defined boundary for a large buffer, 4k >= Large buffer > 512 bytes */
2892 #define ICE_AQ_LG_BUF 512
2894 /* Flags sub-structure
2895 * |0 |1 |2 |3 |4 |5 |6 |7 |8 |9 |10 |11 |12 |13 |14 |15 |
2896 * |DD |CMP|ERR|VFE| * * RESERVED * * |LB |RD |VFC|BUF|SI |EI |FE |
2899 /* command flags and offsets */
2900 #define ICE_AQ_FLAG_DD_S 0
2901 #define ICE_AQ_FLAG_CMP_S 1
2902 #define ICE_AQ_FLAG_ERR_S 2
2903 #define ICE_AQ_FLAG_VFE_S 3
2904 #define ICE_AQ_FLAG_LB_S 9
2905 #define ICE_AQ_FLAG_RD_S 10
2906 #define ICE_AQ_FLAG_VFC_S 11
2907 #define ICE_AQ_FLAG_BUF_S 12
2908 #define ICE_AQ_FLAG_SI_S 13
2909 #define ICE_AQ_FLAG_EI_S 14
2910 #define ICE_AQ_FLAG_FE_S 15
2912 #define ICE_AQ_FLAG_DD BIT(ICE_AQ_FLAG_DD_S) /* 0x1 */
2913 #define ICE_AQ_FLAG_CMP BIT(ICE_AQ_FLAG_CMP_S) /* 0x2 */
2914 #define ICE_AQ_FLAG_ERR BIT(ICE_AQ_FLAG_ERR_S) /* 0x4 */
2915 #define ICE_AQ_FLAG_VFE BIT(ICE_AQ_FLAG_VFE_S) /* 0x8 */
2916 #define ICE_AQ_FLAG_LB BIT(ICE_AQ_FLAG_LB_S) /* 0x200 */
2917 #define ICE_AQ_FLAG_RD BIT(ICE_AQ_FLAG_RD_S) /* 0x400 */
2918 #define ICE_AQ_FLAG_VFC BIT(ICE_AQ_FLAG_VFC_S) /* 0x800 */
2919 #define ICE_AQ_FLAG_BUF BIT(ICE_AQ_FLAG_BUF_S) /* 0x1000 */
2920 #define ICE_AQ_FLAG_SI BIT(ICE_AQ_FLAG_SI_S) /* 0x2000 */
2921 #define ICE_AQ_FLAG_EI BIT(ICE_AQ_FLAG_EI_S) /* 0x4000 */
2922 #define ICE_AQ_FLAG_FE BIT(ICE_AQ_FLAG_FE_S) /* 0x8000 */
2926 ICE_AQ_RC_OK = 0, /* Success */
2927 ICE_AQ_RC_EPERM = 1, /* Operation not permitted */
2928 ICE_AQ_RC_ENOENT = 2, /* No such element */
2929 ICE_AQ_RC_ESRCH = 3, /* Bad opcode */
2930 ICE_AQ_RC_EINTR = 4, /* Operation interrupted */
2931 ICE_AQ_RC_EIO = 5, /* I/O error */
2932 ICE_AQ_RC_ENXIO = 6, /* No such resource */
2933 ICE_AQ_RC_E2BIG = 7, /* Arg too long */
2934 ICE_AQ_RC_EAGAIN = 8, /* Try again */
2935 ICE_AQ_RC_ENOMEM = 9, /* Out of memory */
2936 ICE_AQ_RC_EACCES = 10, /* Permission denied */
2937 ICE_AQ_RC_EFAULT = 11, /* Bad address */
2938 ICE_AQ_RC_EBUSY = 12, /* Device or resource busy */
2939 ICE_AQ_RC_EEXIST = 13, /* Object already exists */
2940 ICE_AQ_RC_EINVAL = 14, /* Invalid argument */
2941 ICE_AQ_RC_ENOTTY = 15, /* Not a typewriter */
2942 ICE_AQ_RC_ENOSPC = 16, /* No space left or allocation failure */
2943 ICE_AQ_RC_ENOSYS = 17, /* Function not implemented */
2944 ICE_AQ_RC_ERANGE = 18, /* Parameter out of range */
2945 ICE_AQ_RC_EFLUSHED = 19, /* Cmd flushed due to prev cmd error */
2946 ICE_AQ_RC_BAD_ADDR = 20, /* Descriptor contains a bad pointer */
2947 ICE_AQ_RC_EMODE = 21, /* Op not allowed in current dev mode */
2948 ICE_AQ_RC_EFBIG = 22, /* File too big */
2949 ICE_AQ_RC_ESBCOMP = 23, /* SB-IOSF completion unsuccessful */
2950 ICE_AQ_RC_ENOSEC = 24, /* Missing security manifest */
2951 ICE_AQ_RC_EBADSIG = 25, /* Bad RSA signature */
2952 ICE_AQ_RC_ESVN = 26, /* SVN number prohibits this package */
2953 ICE_AQ_RC_EBADMAN = 27, /* Manifest hash mismatch */
2954 ICE_AQ_RC_EBADBUF = 28, /* Buffer hash mismatches manifest */
2955 ICE_AQ_RC_EACCES_BMCU = 29, /* BMC Update in progress */
2958 /* Admin Queue command opcodes */
2959 enum ice_adminq_opc {
2961 ice_aqc_opc_get_ver = 0x0001,
2962 ice_aqc_opc_driver_ver = 0x0002,
2963 ice_aqc_opc_q_shutdown = 0x0003,
2964 ice_aqc_opc_get_exp_err = 0x0005,
2966 /* resource ownership */
2967 ice_aqc_opc_req_res = 0x0008,
2968 ice_aqc_opc_release_res = 0x0009,
2970 /* device/function capabilities */
2971 ice_aqc_opc_list_func_caps = 0x000A,
2972 ice_aqc_opc_list_dev_caps = 0x000B,
2974 /* manage MAC address */
2975 ice_aqc_opc_manage_mac_read = 0x0107,
2976 ice_aqc_opc_manage_mac_write = 0x0108,
2979 ice_aqc_opc_clear_pxe_mode = 0x0110,
2981 ice_aqc_opc_config_no_drop_policy = 0x0112,
2983 /* internal switch commands */
2984 ice_aqc_opc_get_sw_cfg = 0x0200,
2985 ice_aqc_opc_set_port_params = 0x0203,
2987 /* Alloc/Free/Get Resources */
2988 ice_aqc_opc_get_res_alloc = 0x0204,
2989 ice_aqc_opc_alloc_res = 0x0208,
2990 ice_aqc_opc_free_res = 0x0209,
2991 ice_aqc_opc_get_allocd_res_desc = 0x020A,
2992 ice_aqc_opc_set_vlan_mode_parameters = 0x020C,
2993 ice_aqc_opc_get_vlan_mode_parameters = 0x020D,
2996 ice_aqc_opc_add_vsi = 0x0210,
2997 ice_aqc_opc_update_vsi = 0x0211,
2998 ice_aqc_opc_get_vsi_params = 0x0212,
2999 ice_aqc_opc_free_vsi = 0x0213,
3001 /* Mirroring rules - add/update, delete */
3002 ice_aqc_opc_add_update_mir_rule = 0x0260,
3003 ice_aqc_opc_del_mir_rule = 0x0261,
3005 /* storm configuration */
3006 ice_aqc_opc_set_storm_cfg = 0x0280,
3007 ice_aqc_opc_get_storm_cfg = 0x0281,
3009 /* recipe commands */
3010 ice_aqc_opc_add_recipe = 0x0290,
3011 ice_aqc_opc_recipe_to_profile = 0x0291,
3012 ice_aqc_opc_get_recipe = 0x0292,
3013 ice_aqc_opc_get_recipe_to_profile = 0x0293,
3015 /* switch rules population commands */
3016 ice_aqc_opc_add_sw_rules = 0x02A0,
3017 ice_aqc_opc_update_sw_rules = 0x02A1,
3018 ice_aqc_opc_remove_sw_rules = 0x02A2,
3019 ice_aqc_opc_get_sw_rules = 0x02A3,
3020 ice_aqc_opc_clear_pf_cfg = 0x02A4,
3023 ice_aqc_opc_pfc_ignore = 0x0301,
3024 ice_aqc_opc_query_pfc_mode = 0x0302,
3025 ice_aqc_opc_set_pfc_mode = 0x0303,
3026 ice_aqc_opc_set_dcb_params = 0x0306,
3028 /* transmit scheduler commands */
3029 ice_aqc_opc_get_dflt_topo = 0x0400,
3030 ice_aqc_opc_add_sched_elems = 0x0401,
3031 ice_aqc_opc_cfg_sched_elems = 0x0403,
3032 ice_aqc_opc_get_sched_elems = 0x0404,
3033 ice_aqc_opc_move_sched_elems = 0x0408,
3034 ice_aqc_opc_suspend_sched_elems = 0x0409,
3035 ice_aqc_opc_resume_sched_elems = 0x040A,
3036 ice_aqc_opc_query_port_ets = 0x040E,
3037 ice_aqc_opc_delete_sched_elems = 0x040F,
3038 ice_aqc_opc_add_rl_profiles = 0x0410,
3039 ice_aqc_opc_query_rl_profiles = 0x0411,
3040 ice_aqc_opc_query_sched_res = 0x0412,
3041 ice_aqc_opc_query_node_to_root = 0x0413,
3042 ice_aqc_opc_cfg_l2_node_cgd = 0x0414,
3043 ice_aqc_opc_remove_rl_profiles = 0x0415,
3046 ice_aqc_opc_get_phy_caps = 0x0600,
3047 ice_aqc_opc_set_phy_cfg = 0x0601,
3048 ice_aqc_opc_set_mac_cfg = 0x0603,
3049 ice_aqc_opc_restart_an = 0x0605,
3050 ice_aqc_opc_get_link_status = 0x0607,
3051 ice_aqc_opc_set_event_mask = 0x0613,
3052 ice_aqc_opc_set_mac_lb = 0x0620,
3053 ice_aqc_opc_get_link_topo = 0x06E0,
3054 ice_aqc_opc_set_port_id_led = 0x06E9,
3055 ice_aqc_opc_get_port_options = 0x06EA,
3056 ice_aqc_opc_set_port_option = 0x06EB,
3057 ice_aqc_opc_set_gpio = 0x06EC,
3058 ice_aqc_opc_get_gpio = 0x06ED,
3059 ice_aqc_opc_sff_eeprom = 0x06EE,
3060 ice_aqc_opc_sw_set_gpio = 0x06EF,
3061 ice_aqc_opc_sw_get_gpio = 0x06F0,
3064 ice_aqc_opc_nvm_read = 0x0701,
3065 ice_aqc_opc_nvm_erase = 0x0702,
3066 ice_aqc_opc_nvm_write = 0x0703,
3067 ice_aqc_opc_nvm_cfg_read = 0x0704,
3068 ice_aqc_opc_nvm_cfg_write = 0x0705,
3069 ice_aqc_opc_nvm_checksum = 0x0706,
3070 ice_aqc_opc_nvm_write_activate = 0x0707,
3071 ice_aqc_opc_nvm_sr_dump = 0x0707,
3072 ice_aqc_opc_nvm_save_factory_settings = 0x0708,
3073 ice_aqc_opc_nvm_update_empr = 0x0709,
3076 ice_aqc_opc_lldp_get_mib = 0x0A00,
3077 ice_aqc_opc_lldp_set_mib_change = 0x0A01,
3078 ice_aqc_opc_lldp_add_tlv = 0x0A02,
3079 ice_aqc_opc_lldp_update_tlv = 0x0A03,
3080 ice_aqc_opc_lldp_delete_tlv = 0x0A04,
3081 ice_aqc_opc_lldp_stop = 0x0A05,
3082 ice_aqc_opc_lldp_start = 0x0A06,
3083 ice_aqc_opc_get_cee_dcb_cfg = 0x0A07,
3084 ice_aqc_opc_lldp_set_local_mib = 0x0A08,
3085 ice_aqc_opc_lldp_stop_start_specific_agent = 0x0A09,
3086 ice_aqc_opc_lldp_filter_ctrl = 0x0A0A,
3089 ice_aqc_opc_set_rss_key = 0x0B02,
3090 ice_aqc_opc_set_rss_lut = 0x0B03,
3091 ice_aqc_opc_get_rss_key = 0x0B04,
3092 ice_aqc_opc_get_rss_lut = 0x0B05,
3093 ice_aqc_opc_clear_fd_table = 0x0B06,
3095 ice_aqc_opc_alloc_acl_tbl = 0x0C10,
3096 ice_aqc_opc_dealloc_acl_tbl = 0x0C11,
3097 ice_aqc_opc_alloc_acl_actpair = 0x0C12,
3098 ice_aqc_opc_dealloc_acl_actpair = 0x0C13,
3099 ice_aqc_opc_alloc_acl_scen = 0x0C14,
3100 ice_aqc_opc_dealloc_acl_scen = 0x0C15,
3101 ice_aqc_opc_alloc_acl_counters = 0x0C16,
3102 ice_aqc_opc_dealloc_acl_counters = 0x0C17,
3103 ice_aqc_opc_dealloc_acl_res = 0x0C1A,
3104 ice_aqc_opc_update_acl_scen = 0x0C1B,
3105 ice_aqc_opc_program_acl_actpair = 0x0C1C,
3106 ice_aqc_opc_program_acl_prof_extraction = 0x0C1D,
3107 ice_aqc_opc_program_acl_prof_ranges = 0x0C1E,
3108 ice_aqc_opc_program_acl_entry = 0x0C20,
3109 ice_aqc_opc_query_acl_prof = 0x0C21,
3110 ice_aqc_opc_query_acl_prof_ranges = 0x0C22,
3111 ice_aqc_opc_query_acl_scen = 0x0C23,
3112 ice_aqc_opc_query_acl_entry = 0x0C24,
3113 ice_aqc_opc_query_acl_actpair = 0x0C25,
3114 ice_aqc_opc_query_acl_counter = 0x0C27,
3116 /* Tx queue handling commands/events */
3117 ice_aqc_opc_add_txqs = 0x0C30,
3118 ice_aqc_opc_dis_txqs = 0x0C31,
3119 ice_aqc_opc_txqs_cleanup = 0x0C31,
3120 ice_aqc_opc_move_recfg_txqs = 0x0C32,
3122 /* package commands */
3123 ice_aqc_opc_download_pkg = 0x0C40,
3124 ice_aqc_opc_upload_section = 0x0C41,
3125 ice_aqc_opc_update_pkg = 0x0C42,
3126 ice_aqc_opc_get_pkg_info_list = 0x0C43,
3128 ice_aqc_opc_driver_shared_params = 0x0C90,
3130 /* Standalone Commands/Events */
3131 ice_aqc_opc_event_lan_overflow = 0x1001,
3133 /* SystemDiagnostic commands */
3134 ice_aqc_opc_set_health_status_config = 0xFF20,
3135 ice_aqc_opc_get_supported_health_status_codes = 0xFF21,
3136 ice_aqc_opc_get_health_status = 0xFF22,
3137 ice_aqc_opc_clear_health_status = 0xFF23,
3139 /* FW Logging Commands */
3140 ice_aqc_opc_fw_logs_config = 0xFF30,
3141 ice_aqc_opc_fw_logs_register = 0xFF31,
3142 ice_aqc_opc_fw_logs_query = 0xFF32,
3143 ice_aqc_opc_fw_logs_event = 0xFF33,
3144 ice_aqc_opc_fw_logs_get = 0xFF34,
3145 ice_aqc_opc_fw_logs_clear = 0xFF35
3148 #endif /* _ICE_ADMINQ_CMD_H_ */