1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2001-2019
5 #ifndef _ICE_ADMINQ_CMD_H_
6 #define _ICE_ADMINQ_CMD_H_
8 /* This header file defines the Admin Queue commands, error codes and
9 * descriptor format. It is shared between Firmware and Software.
13 #define ICE_MAX_VSI 768
14 #define ICE_AQC_TOPO_MAX_LEVEL_NUM 0x9
15 #define ICE_AQ_SET_MAC_FRAME_SIZE_MAX 9728
18 struct ice_aqc_generic {
26 /* Get version (direct 0x0001) */
27 struct ice_aqc_get_ver {
41 /* Send driver version (indirect 0x0002) */
42 struct ice_aqc_driver_ver {
53 /* Queue Shutdown (direct 0x0003) */
54 struct ice_aqc_q_shutdown {
55 __le32 driver_unloading;
56 #define ICE_AQC_DRIVER_UNLOADING BIT(0)
63 /* Request resource ownership (direct 0x0008)
64 * Release resource ownership (direct 0x0009)
66 struct ice_aqc_req_res {
68 #define ICE_AQC_RES_ID_NVM 1
69 #define ICE_AQC_RES_ID_SDP 2
70 #define ICE_AQC_RES_ID_CHNG_LOCK 3
71 #define ICE_AQC_RES_ID_GLBL_LOCK 4
73 #define ICE_AQC_RES_ACCESS_READ 1
74 #define ICE_AQC_RES_ACCESS_WRITE 2
76 /* Upon successful completion, FW writes this value and driver is
77 * expected to release resource before timeout. This value is provided
81 #define ICE_AQ_RES_NVM_READ_DFLT_TIMEOUT_MS 3000
82 #define ICE_AQ_RES_NVM_WRITE_DFLT_TIMEOUT_MS 180000
83 #define ICE_AQ_RES_CHNG_LOCK_DFLT_TIMEOUT_MS 1000
84 #define ICE_AQ_RES_GLBL_LOCK_DFLT_TIMEOUT_MS 3000
85 /* For SDP: pin ID of the SDP */
87 /* Status is only used for ICE_AQC_RES_ID_GLBL_LOCK */
89 #define ICE_AQ_RES_GLBL_SUCCESS 0
90 #define ICE_AQ_RES_GLBL_IN_PROG 1
91 #define ICE_AQ_RES_GLBL_DONE 2
96 /* Get function capabilities (indirect 0x000A)
97 * Get device capabilities (indirect 0x000B)
99 struct ice_aqc_list_caps {
109 /* Device/Function buffer entry, repeated per reported capability */
110 struct ice_aqc_list_caps_elem {
112 #define ICE_AQC_CAPS_VALID_FUNCTIONS 0x0005
113 #define ICE_AQC_CAPS_VSI 0x0017
114 #define ICE_AQC_CAPS_DCB 0x0018
115 #define ICE_AQC_CAPS_RSS 0x0040
116 #define ICE_AQC_CAPS_RXQS 0x0041
117 #define ICE_AQC_CAPS_TXQS 0x0042
118 #define ICE_AQC_CAPS_MSIX 0x0043
119 #define ICE_AQC_CAPS_FD 0x0045
120 #define ICE_AQC_CAPS_MAX_MTU 0x0047
124 /* Number of resources described by this capability */
126 /* Only meaningful for some types of resources */
128 /* Only meaningful for some types of resources */
135 /* Manage MAC address, read command - indirect (0x0107)
136 * This struct is also used for the response
138 struct ice_aqc_manage_mac_read {
139 __le16 flags; /* Zeroed by device driver */
140 #define ICE_AQC_MAN_MAC_LAN_ADDR_VALID BIT(4)
141 #define ICE_AQC_MAN_MAC_SAN_ADDR_VALID BIT(5)
142 #define ICE_AQC_MAN_MAC_PORT_ADDR_VALID BIT(6)
143 #define ICE_AQC_MAN_MAC_WOL_ADDR_VALID BIT(7)
144 #define ICE_AQC_MAN_MAC_READ_S 4
145 #define ICE_AQC_MAN_MAC_READ_M (0xF << ICE_AQC_MAN_MAC_READ_S)
148 #define ICE_AQC_MAN_MAC_PORT_NUM_IS_VALID BIT(0)
149 u8 num_addr; /* Used in response */
156 /* Response buffer format for manage MAC read command */
157 struct ice_aqc_manage_mac_read_resp {
160 #define ICE_AQC_MAN_MAC_ADDR_TYPE_LAN 0
161 #define ICE_AQC_MAN_MAC_ADDR_TYPE_WOL 1
162 u8 mac_addr[ETH_ALEN];
166 /* Manage MAC address, write command - direct (0x0108) */
167 struct ice_aqc_manage_mac_write {
170 #define ICE_AQC_MAN_MAC_WR_MC_MAG_EN BIT(0)
171 #define ICE_AQC_MAN_MAC_WR_WOL_LAA_PFR_KEEP BIT(1)
172 #define ICE_AQC_MAN_MAC_WR_S 6
173 #define ICE_AQC_MAN_MAC_WR_M (3 << ICE_AQC_MAN_MAC_WR_S)
174 #define ICE_AQC_MAN_MAC_UPDATE_LAA 0
175 #define ICE_AQC_MAN_MAC_UPDATE_LAA_WOL (BIT(0) << ICE_AQC_MAN_MAC_WR_S)
176 /* High 16 bits of MAC address in big endian order */
178 /* Low 32 bits of MAC address in big endian order */
185 /* Clear PXE Command and response (direct 0x0110) */
186 struct ice_aqc_clear_pxe {
188 #define ICE_AQC_CLEAR_PXE_RX_CNT 0x2
193 /* Configure No-Drop Policy Command (direct 0x0112) */
194 struct ice_aqc_config_no_drop_policy {
196 #define ICE_AQC_FORCE_NO_DROP BIT(0)
200 /* Get switch configuration (0x0200) */
201 struct ice_aqc_get_sw_cfg {
202 /* Reserved for command and copy of request flags for response */
204 /* First desc in case of command and next_elem in case of response
205 * In case of response, if it is not zero, means all the configuration
206 * was not returned and new command shall be sent with this value in
207 * the 'first desc' field
210 /* Reserved for command, only used for response */
218 /* Each entry in the response buffer is of the following type: */
219 struct ice_aqc_get_sw_cfg_resp_elem {
220 /* VSI/Port Number */
222 #define ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_S 0
223 #define ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_M \
224 (0x3FF << ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_S)
225 #define ICE_AQC_GET_SW_CONF_RESP_TYPE_S 14
226 #define ICE_AQC_GET_SW_CONF_RESP_TYPE_M (0x3 << ICE_AQC_GET_SW_CONF_RESP_TYPE_S)
227 #define ICE_AQC_GET_SW_CONF_RESP_PHYS_PORT 0
228 #define ICE_AQC_GET_SW_CONF_RESP_VIRT_PORT 1
229 #define ICE_AQC_GET_SW_CONF_RESP_VSI 2
231 /* SWID VSI/Port belongs to */
234 /* Bit 14..0 : PF/VF number VSI belongs to
235 * Bit 15 : VF indication bit
238 #define ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_S 0
239 #define ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_M \
240 (0x7FFF << ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_S)
241 #define ICE_AQC_GET_SW_CONF_RESP_IS_VF BIT(15)
245 /* The response buffer is as follows. Note that the length of the
246 * elements array varies with the length of the command response.
248 struct ice_aqc_get_sw_cfg_resp {
249 struct ice_aqc_get_sw_cfg_resp_elem elements[1];
254 /* These resource type defines are used for all switch resource
255 * commands where a resource type is required, such as:
256 * Get Resource Allocation command (indirect 0x0204)
257 * Allocate Resources command (indirect 0x0208)
258 * Free Resources command (indirect 0x0209)
259 * Get Allocated Resource Descriptors Command (indirect 0x020A)
261 #define ICE_AQC_RES_TYPE_VEB_COUNTER 0x00
262 #define ICE_AQC_RES_TYPE_VLAN_COUNTER 0x01
263 #define ICE_AQC_RES_TYPE_MIRROR_RULE 0x02
264 #define ICE_AQC_RES_TYPE_VSI_LIST_REP 0x03
265 #define ICE_AQC_RES_TYPE_VSI_LIST_PRUNE 0x04
266 #define ICE_AQC_RES_TYPE_RECIPE 0x05
267 #define ICE_AQC_RES_TYPE_PROFILE 0x06
268 #define ICE_AQC_RES_TYPE_SWID 0x07
269 #define ICE_AQC_RES_TYPE_VSI 0x08
270 #define ICE_AQC_RES_TYPE_FLU 0x09
271 #define ICE_AQC_RES_TYPE_WIDE_TABLE_1 0x0A
272 #define ICE_AQC_RES_TYPE_WIDE_TABLE_2 0x0B
273 #define ICE_AQC_RES_TYPE_WIDE_TABLE_4 0x0C
274 #define ICE_AQC_RES_TYPE_GLOBAL_RSS_HASH 0x20
275 #define ICE_AQC_RES_TYPE_FDIR_COUNTER_BLOCK 0x21
276 #define ICE_AQC_RES_TYPE_FDIR_GUARANTEED_ENTRIES 0x22
277 #define ICE_AQC_RES_TYPE_FDIR_SHARED_ENTRIES 0x23
278 #define ICE_AQC_RES_TYPE_FLEX_DESC_PROG 0x30
279 #define ICE_AQC_RES_TYPE_SWITCH_PROF_BLDR_PROFID 0x48
280 #define ICE_AQC_RES_TYPE_SWITCH_PROF_BLDR_TCAM 0x49
281 #define ICE_AQC_RES_TYPE_ACL_PROF_BLDR_PROFID 0x50
282 #define ICE_AQC_RES_TYPE_ACL_PROF_BLDR_TCAM 0x51
283 #define ICE_AQC_RES_TYPE_FD_PROF_BLDR_PROFID 0x58
284 #define ICE_AQC_RES_TYPE_FD_PROF_BLDR_TCAM 0x59
285 #define ICE_AQC_RES_TYPE_HASH_PROF_BLDR_PROFID 0x60
286 #define ICE_AQC_RES_TYPE_HASH_PROF_BLDR_TCAM 0x61
287 /* Resource types 0x62-67 are reserved for Hash profile builder */
288 #define ICE_AQC_RES_TYPE_QHASH_PROF_BLDR_PROFID 0x68
289 #define ICE_AQC_RES_TYPE_QHASH_PROF_BLDR_TCAM 0x69
291 #define ICE_AQC_RES_TYPE_FLAG_SHARED BIT(7)
292 #define ICE_AQC_RES_TYPE_FLAG_SCAN_BOTTOM BIT(12)
293 #define ICE_AQC_RES_TYPE_FLAG_IGNORE_INDEX BIT(13)
295 #define ICE_AQC_RES_TYPE_FLAG_DEDICATED 0x00
297 #define ICE_AQC_RES_TYPE_S 0
298 #define ICE_AQC_RES_TYPE_M (0x07F << ICE_AQC_RES_TYPE_S)
300 /* Get Resource Allocation command (indirect 0x0204) */
301 struct ice_aqc_get_res_alloc {
302 __le16 resp_elem_num; /* Used in response, reserved in command */
308 /* Get Resource Allocation Response Buffer per response */
309 struct ice_aqc_get_res_resp_elem {
310 __le16 res_type; /* Types defined above cmd 0x0204 */
311 __le16 total_capacity; /* Resources available to all PF's */
312 __le16 total_function; /* Resources allocated for a PF */
313 __le16 total_shared; /* Resources allocated as shared */
314 __le16 total_free; /* Resources un-allocated/not reserved by any PF */
317 /* Buffer for Get Resource command */
318 struct ice_aqc_get_res_resp {
319 /* Number of resource entries to be calculated using
320 * datalen/sizeof(struct ice_aqc_cmd_resp)).
321 * Value of 'datalen' gets updated as part of response.
323 struct ice_aqc_get_res_resp_elem elem[1];
327 /* Allocate Resources command (indirect 0x0208)
328 * Free Resources command (indirect 0x0209)
330 struct ice_aqc_alloc_free_res_cmd {
331 __le16 num_entries; /* Number of Resource entries */
338 /* Resource descriptor */
339 struct ice_aqc_res_elem {
347 /* Buffer for Allocate/Free Resources commands */
348 struct ice_aqc_alloc_free_res_elem {
349 __le16 res_type; /* Types defined above cmd 0x0204 */
350 #define ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_S 8
351 #define ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_M \
352 (0xF << ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_S)
354 struct ice_aqc_res_elem elem[1];
358 /* Get Allocated Resource Descriptors Command (indirect 0x020A) */
359 struct ice_aqc_get_allocd_res_desc {
362 __le16 res; /* Types defined above cmd 0x0204 */
377 struct ice_aqc_get_allocd_res_desc_resp {
378 struct ice_aqc_res_elem elem[1];
382 /* Add VSI (indirect 0x0210)
383 * Update VSI (indirect 0x0211)
384 * Get VSI (indirect 0x0212)
385 * Free VSI (indirect 0x0213)
387 struct ice_aqc_add_get_update_free_vsi {
389 #define ICE_AQ_VSI_NUM_S 0
390 #define ICE_AQ_VSI_NUM_M (0x03FF << ICE_AQ_VSI_NUM_S)
391 #define ICE_AQ_VSI_IS_VALID BIT(15)
393 #define ICE_AQ_VSI_KEEP_ALLOC 0x1
397 #define ICE_AQ_VSI_TYPE_S 0
398 #define ICE_AQ_VSI_TYPE_M (0x3 << ICE_AQ_VSI_TYPE_S)
399 #define ICE_AQ_VSI_TYPE_VF 0x0
400 #define ICE_AQ_VSI_TYPE_VMDQ2 0x1
401 #define ICE_AQ_VSI_TYPE_PF 0x2
402 #define ICE_AQ_VSI_TYPE_EMP_MNG 0x3
408 /* Response descriptor for:
409 * Add VSI (indirect 0x0210)
410 * Update VSI (indirect 0x0211)
411 * Free VSI (indirect 0x0213)
413 struct ice_aqc_add_update_free_vsi_resp {
423 struct ice_aqc_get_vsi_resp {
426 /* The vsi_flags field uses the ICE_AQ_VSI_TYPE_* defines for values.
427 * These are found above in struct ice_aqc_add_get_update_free_vsi.
437 struct ice_aqc_vsi_props {
438 __le16 valid_sections;
439 #define ICE_AQ_VSI_PROP_SW_VALID BIT(0)
440 #define ICE_AQ_VSI_PROP_SECURITY_VALID BIT(1)
441 #define ICE_AQ_VSI_PROP_VLAN_VALID BIT(2)
442 #define ICE_AQ_VSI_PROP_OUTER_TAG_VALID BIT(3)
443 #define ICE_AQ_VSI_PROP_INGRESS_UP_VALID BIT(4)
444 #define ICE_AQ_VSI_PROP_EGRESS_UP_VALID BIT(5)
445 #define ICE_AQ_VSI_PROP_RXQ_MAP_VALID BIT(6)
446 #define ICE_AQ_VSI_PROP_Q_OPT_VALID BIT(7)
447 #define ICE_AQ_VSI_PROP_OUTER_UP_VALID BIT(8)
448 #define ICE_AQ_VSI_PROP_FLOW_DIR_VALID BIT(11)
449 #define ICE_AQ_VSI_PROP_PASID_VALID BIT(12)
453 #define ICE_AQ_VSI_SW_FLAG_ALLOW_LB BIT(5)
454 #define ICE_AQ_VSI_SW_FLAG_LOCAL_LB BIT(6)
455 #define ICE_AQ_VSI_SW_FLAG_SRC_PRUNE BIT(7)
457 #define ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_S 0
458 #define ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_M \
459 (0xF << ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_S)
460 #define ICE_AQ_VSI_SW_FLAG_RX_VLAN_PRUNE_ENA BIT(0)
461 #define ICE_AQ_VSI_SW_FLAG_LAN_ENA BIT(4)
463 #define ICE_AQ_VSI_SW_VEB_STAT_ID_S 0
464 #define ICE_AQ_VSI_SW_VEB_STAT_ID_M (0x1F << ICE_AQ_VSI_SW_VEB_STAT_ID_S)
465 #define ICE_AQ_VSI_SW_VEB_STAT_ID_VALID BIT(5)
466 /* security section */
468 #define ICE_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD BIT(0)
469 #define ICE_AQ_VSI_SEC_FLAG_ENA_MAC_ANTI_SPOOF BIT(2)
470 #define ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S 4
471 #define ICE_AQ_VSI_SEC_TX_PRUNE_ENA_M (0xF << ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S)
472 #define ICE_AQ_VSI_SEC_TX_VLAN_PRUNE_ENA BIT(0)
475 __le16 pvid; /* VLANS include priority bits */
476 u8 pvlan_reserved[2];
478 #define ICE_AQ_VSI_VLAN_MODE_S 0
479 #define ICE_AQ_VSI_VLAN_MODE_M (0x3 << ICE_AQ_VSI_VLAN_MODE_S)
480 #define ICE_AQ_VSI_VLAN_MODE_UNTAGGED 0x1
481 #define ICE_AQ_VSI_VLAN_MODE_TAGGED 0x2
482 #define ICE_AQ_VSI_VLAN_MODE_ALL 0x3
483 #define ICE_AQ_VSI_PVLAN_INSERT_PVID BIT(2)
484 #define ICE_AQ_VSI_VLAN_EMOD_S 3
485 #define ICE_AQ_VSI_VLAN_EMOD_M (0x3 << ICE_AQ_VSI_VLAN_EMOD_S)
486 #define ICE_AQ_VSI_VLAN_EMOD_STR_BOTH (0x0 << ICE_AQ_VSI_VLAN_EMOD_S)
487 #define ICE_AQ_VSI_VLAN_EMOD_STR_UP (0x1 << ICE_AQ_VSI_VLAN_EMOD_S)
488 #define ICE_AQ_VSI_VLAN_EMOD_STR (0x2 << ICE_AQ_VSI_VLAN_EMOD_S)
489 #define ICE_AQ_VSI_VLAN_EMOD_NOTHING (0x3 << ICE_AQ_VSI_VLAN_EMOD_S)
490 u8 pvlan_reserved2[3];
491 /* ingress egress up sections */
492 __le32 ingress_table; /* bitmap, 3 bits per up */
493 #define ICE_AQ_VSI_UP_TABLE_UP0_S 0
494 #define ICE_AQ_VSI_UP_TABLE_UP0_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP0_S)
495 #define ICE_AQ_VSI_UP_TABLE_UP1_S 3
496 #define ICE_AQ_VSI_UP_TABLE_UP1_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP1_S)
497 #define ICE_AQ_VSI_UP_TABLE_UP2_S 6
498 #define ICE_AQ_VSI_UP_TABLE_UP2_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP2_S)
499 #define ICE_AQ_VSI_UP_TABLE_UP3_S 9
500 #define ICE_AQ_VSI_UP_TABLE_UP3_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP3_S)
501 #define ICE_AQ_VSI_UP_TABLE_UP4_S 12
502 #define ICE_AQ_VSI_UP_TABLE_UP4_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP4_S)
503 #define ICE_AQ_VSI_UP_TABLE_UP5_S 15
504 #define ICE_AQ_VSI_UP_TABLE_UP5_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP5_S)
505 #define ICE_AQ_VSI_UP_TABLE_UP6_S 18
506 #define ICE_AQ_VSI_UP_TABLE_UP6_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP6_S)
507 #define ICE_AQ_VSI_UP_TABLE_UP7_S 21
508 #define ICE_AQ_VSI_UP_TABLE_UP7_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP7_S)
509 __le32 egress_table; /* same defines as for ingress table */
510 /* outer tags section */
513 #define ICE_AQ_VSI_OUTER_TAG_MODE_S 0
514 #define ICE_AQ_VSI_OUTER_TAG_MODE_M (0x3 << ICE_AQ_VSI_OUTER_TAG_MODE_S)
515 #define ICE_AQ_VSI_OUTER_TAG_NOTHING 0x0
516 #define ICE_AQ_VSI_OUTER_TAG_REMOVE 0x1
517 #define ICE_AQ_VSI_OUTER_TAG_COPY 0x2
518 #define ICE_AQ_VSI_OUTER_TAG_TYPE_S 2
519 #define ICE_AQ_VSI_OUTER_TAG_TYPE_M (0x3 << ICE_AQ_VSI_OUTER_TAG_TYPE_S)
520 #define ICE_AQ_VSI_OUTER_TAG_NONE 0x0
521 #define ICE_AQ_VSI_OUTER_TAG_STAG 0x1
522 #define ICE_AQ_VSI_OUTER_TAG_VLAN_8100 0x2
523 #define ICE_AQ_VSI_OUTER_TAG_VLAN_9100 0x3
524 #define ICE_AQ_VSI_OUTER_TAG_INSERT BIT(4)
525 #define ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST BIT(6)
526 u8 outer_tag_reserved;
527 /* queue mapping section */
528 __le16 mapping_flags;
529 #define ICE_AQ_VSI_Q_MAP_CONTIG 0x0
530 #define ICE_AQ_VSI_Q_MAP_NONCONTIG BIT(0)
531 __le16 q_mapping[16];
532 #define ICE_AQ_VSI_Q_S 0
533 #define ICE_AQ_VSI_Q_M (0x7FF << ICE_AQ_VSI_Q_S)
534 __le16 tc_mapping[8];
535 #define ICE_AQ_VSI_TC_Q_OFFSET_S 0
536 #define ICE_AQ_VSI_TC_Q_OFFSET_M (0x7FF << ICE_AQ_VSI_TC_Q_OFFSET_S)
537 #define ICE_AQ_VSI_TC_Q_NUM_S 11
538 #define ICE_AQ_VSI_TC_Q_NUM_M (0xF << ICE_AQ_VSI_TC_Q_NUM_S)
539 /* queueing option section */
541 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_S 0
542 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_M (0x3 << ICE_AQ_VSI_Q_OPT_RSS_LUT_S)
543 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_VSI 0x0
544 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_PF 0x2
545 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_GBL 0x3
546 #define ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_S 2
547 #define ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_M (0xF << ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_S)
548 #define ICE_AQ_VSI_Q_OPT_RSS_HASH_S 6
549 #define ICE_AQ_VSI_Q_OPT_RSS_HASH_M (0x3 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S)
550 #define ICE_AQ_VSI_Q_OPT_RSS_TPLZ (0x0 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S)
551 #define ICE_AQ_VSI_Q_OPT_RSS_SYM_TPLZ (0x1 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S)
552 #define ICE_AQ_VSI_Q_OPT_RSS_XOR (0x2 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S)
553 #define ICE_AQ_VSI_Q_OPT_RSS_JHASH (0x3 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S)
555 #define ICE_AQ_VSI_Q_OPT_TC_OVR_S 0
556 #define ICE_AQ_VSI_Q_OPT_TC_OVR_M (0x1F << ICE_AQ_VSI_Q_OPT_TC_OVR_S)
557 #define ICE_AQ_VSI_Q_OPT_PROF_TC_OVR BIT(7)
559 #define ICE_AQ_VSI_Q_OPT_PE_FLTR_EN BIT(0)
560 u8 q_opt_reserved[3];
561 /* outer up section */
562 __le32 outer_up_table; /* same structure and defines as ingress tbl */
564 __le16 sect_10_reserved;
565 /* flow director section */
567 #define ICE_AQ_VSI_FD_ENABLE BIT(0)
568 #define ICE_AQ_VSI_FD_TX_AUTO_ENABLE BIT(1)
569 #define ICE_AQ_VSI_FD_PROG_ENABLE BIT(3)
570 __le16 max_fd_fltr_dedicated;
571 __le16 max_fd_fltr_shared;
573 #define ICE_AQ_VSI_FD_DEF_Q_S 0
574 #define ICE_AQ_VSI_FD_DEF_Q_M (0x7FF << ICE_AQ_VSI_FD_DEF_Q_S)
575 #define ICE_AQ_VSI_FD_DEF_GRP_S 12
576 #define ICE_AQ_VSI_FD_DEF_GRP_M (0x7 << ICE_AQ_VSI_FD_DEF_GRP_S)
577 __le16 fd_report_opt;
578 #define ICE_AQ_VSI_FD_REPORT_Q_S 0
579 #define ICE_AQ_VSI_FD_REPORT_Q_M (0x7FF << ICE_AQ_VSI_FD_REPORT_Q_S)
580 #define ICE_AQ_VSI_FD_DEF_PRIORITY_S 12
581 #define ICE_AQ_VSI_FD_DEF_PRIORITY_M (0x7 << ICE_AQ_VSI_FD_DEF_PRIORITY_S)
582 #define ICE_AQ_VSI_FD_DEF_DROP BIT(15)
585 #define ICE_AQ_VSI_PASID_ID_S 0
586 #define ICE_AQ_VSI_PASID_ID_M (0xFFFFF << ICE_AQ_VSI_PASID_ID_S)
587 #define ICE_AQ_VSI_PASID_ID_VALID BIT(31)
592 /* Add/update mirror rule - direct (0x0260) */
593 #define ICE_AQC_RULE_ID_VALID_S 7
594 #define ICE_AQC_RULE_ID_VALID_M (0x1 << ICE_AQC_RULE_ID_VALID_S)
595 #define ICE_AQC_RULE_ID_S 0
596 #define ICE_AQC_RULE_ID_M (0x3F << ICE_AQC_RULE_ID_S)
598 /* Following defines to be used while processing caller specified mirror list
601 /* Action: Byte.bit (1.7)
602 * 0 = Remove VSI from mirror rule
603 * 1 = Add VSI to mirror rule
605 #define ICE_AQC_RULE_ACT_S 15
606 #define ICE_AQC_RULE_ACT_M (0x1 << ICE_AQC_RULE_ACT_S)
607 /* Action: 1.2:0.0 = Mirrored VSI */
608 #define ICE_AQC_RULE_MIRRORED_VSI_S 0
609 #define ICE_AQC_RULE_MIRRORED_VSI_M (0x7FF << ICE_AQC_RULE_MIRRORED_VSI_S)
611 /* This is to be used by add/update mirror rule Admin Queue command.
612 * In case of add mirror rule - if rule ID is specified as
613 * INVAL_MIRROR_RULE_ID, new rule ID is allocated from shared pool.
614 * If specified rule_id is valid, then it is used. If specified rule_id
615 * is in use then new mirroring rule is added.
617 #define ICE_INVAL_MIRROR_RULE_ID 0xFFFF
619 struct ice_aqc_add_update_mir_rule {
623 #define ICE_AQC_RULE_TYPE_S 0
624 #define ICE_AQC_RULE_TYPE_M (0x7 << ICE_AQC_RULE_TYPE_S)
625 /* VPORT ingress/egress */
626 #define ICE_AQC_RULE_TYPE_VPORT_INGRESS 0x1
627 #define ICE_AQC_RULE_TYPE_VPORT_EGRESS 0x2
628 /* Physical port ingress mirroring.
629 * All traffic received by this port
631 #define ICE_AQC_RULE_TYPE_PPORT_INGRESS 0x6
632 /* Physical port egress mirroring. All traffic sent by this port */
633 #define ICE_AQC_RULE_TYPE_PPORT_EGRESS 0x7
635 /* Number of mirrored entries.
636 * The values are in the command buffer
640 /* Destination VSI */
646 /* Delete mirror rule - direct(0x0261) */
647 struct ice_aqc_delete_mir_rule {
651 /* Byte.bit: 20.0 = Keep allocation. If set VSI stays part of
652 * the PF allocated resources, otherwise it is returned to the
655 #define ICE_AQC_FLAG_KEEP_ALLOCD_S 0
656 #define ICE_AQC_FLAG_KEEP_ALLOCD_M (0x1 << ICE_AQC_FLAG_KEEP_ALLOCD_S)
662 /* Set/Get storm config - (direct 0x0280, 0x0281) */
663 /* This structure holds get storm configuration response and same structure
664 * is used to perform set_storm_cfg
666 struct ice_aqc_storm_cfg {
667 __le32 bcast_thresh_size;
668 __le32 mcast_thresh_size;
669 /* Bit 18:0 - Traffic upper threshold size
670 * Bit 31:19 - Reserved
672 #define ICE_AQ_THRESHOLD_S 0
673 #define ICE_AQ_THRESHOLD_M (0x7FFFF << ICE_AQ_THRESHOLD_S)
675 __le32 storm_ctrl_ctrl;
676 /* Bit 0: MDIPW - Drop Multicast packets in previous window
677 * Bit 1: MDICW - Drop multicast packets in current window
678 * Bit 2: BDIPW - Drop broadcast packets in previous window
679 * Bit 3: BDICW - Drop broadcast packets in current window
681 #define ICE_AQ_STORM_CTRL_MDIPW_DROP_MULTICAST BIT(0)
682 #define ICE_AQ_STORM_CTRL_MDICW_DROP_MULTICAST BIT(1)
683 #define ICE_AQ_STORM_CTRL_BDIPW_DROP_MULTICAST BIT(2)
684 #define ICE_AQ_STORM_CTRL_BDICW_DROP_MULTICAST BIT(3)
685 /* Bit 7:5 : Reserved */
686 /* Bit 27:8 : Interval - BSC/MSC Time-interval specification: The
687 * interval size for applying ingress broadcast or multicast storm
690 #define ICE_AQ_STORM_BSC_MSC_TIME_INTERVAL_S 8
691 #define ICE_AQ_STORM_BSC_MSC_TIME_INTERVAL_M \
692 (0xFFFFF << ICE_AQ_STORM_BSC_MSC_TIME_INTERVAL_S)
697 #define ICE_MAX_NUM_RECIPES 64
700 /* Add/Update/Remove/Get switch rules (indirect 0x02A0, 0x02A1, 0x02A2, 0x02A3)
702 struct ice_aqc_sw_rules {
703 /* ops: add switch rules, referring the number of rules.
704 * ops: update switch rules, referring the number of filters
705 * ops: remove switch rules, referring the entry index.
706 * ops: get switch rules, referring to the number of filters.
708 __le16 num_rules_fltr_entry_index;
716 /* Add/Update/Get/Remove lookup Rx/Tx command/response entry
717 * This structures describes the lookup rules and associated actions. "index"
718 * is returned as part of a response to a successful Add command, and can be
719 * used to identify the rule for Update/Get/Remove commands.
721 struct ice_sw_rule_lkup_rx_tx {
723 #define ICE_SW_RECIPE_LOGICAL_PORT_FWD 10
724 /* Source port for LOOKUP_RX and source VSI in case of LOOKUP_TX */
728 /* Bit 0:1 - Action type */
729 #define ICE_SINGLE_ACT_TYPE_S 0x00
730 #define ICE_SINGLE_ACT_TYPE_M (0x3 << ICE_SINGLE_ACT_TYPE_S)
732 /* Bit 2 - Loop back enable
735 #define ICE_SINGLE_ACT_LB_ENABLE BIT(2)
736 #define ICE_SINGLE_ACT_LAN_ENABLE BIT(3)
738 /* Action type = 0 - Forward to VSI or VSI list */
739 #define ICE_SINGLE_ACT_VSI_FORWARDING 0x0
741 #define ICE_SINGLE_ACT_VSI_ID_S 4
742 #define ICE_SINGLE_ACT_VSI_ID_M (0x3FF << ICE_SINGLE_ACT_VSI_ID_S)
743 #define ICE_SINGLE_ACT_VSI_LIST_ID_S 4
744 #define ICE_SINGLE_ACT_VSI_LIST_ID_M (0x3FF << ICE_SINGLE_ACT_VSI_LIST_ID_S)
745 /* This bit needs to be set if action is forward to VSI list */
746 #define ICE_SINGLE_ACT_VSI_LIST BIT(14)
747 #define ICE_SINGLE_ACT_VALID_BIT BIT(17)
748 #define ICE_SINGLE_ACT_DROP BIT(18)
750 /* Action type = 1 - Forward to Queue of Queue group */
751 #define ICE_SINGLE_ACT_TO_Q 0x1
752 #define ICE_SINGLE_ACT_Q_INDEX_S 4
753 #define ICE_SINGLE_ACT_Q_INDEX_M (0x7FF << ICE_SINGLE_ACT_Q_INDEX_S)
754 #define ICE_SINGLE_ACT_Q_REGION_S 15
755 #define ICE_SINGLE_ACT_Q_REGION_M (0x7 << ICE_SINGLE_ACT_Q_REGION_S)
756 #define ICE_SINGLE_ACT_Q_PRIORITY BIT(18)
758 /* Action type = 2 - Prune */
759 #define ICE_SINGLE_ACT_PRUNE 0x2
760 #define ICE_SINGLE_ACT_EGRESS BIT(15)
761 #define ICE_SINGLE_ACT_INGRESS BIT(16)
762 #define ICE_SINGLE_ACT_PRUNET BIT(17)
763 /* Bit 18 should be set to 0 for this action */
765 /* Action type = 2 - Pointer */
766 #define ICE_SINGLE_ACT_PTR 0x2
767 #define ICE_SINGLE_ACT_PTR_VAL_S 4
768 #define ICE_SINGLE_ACT_PTR_VAL_M (0x1FFF << ICE_SINGLE_ACT_PTR_VAL_S)
769 /* Bit 18 should be set to 1 */
770 #define ICE_SINGLE_ACT_PTR_BIT BIT(18)
772 /* Action type = 3 - Other actions. Last two bits
773 * are other action identifier
775 #define ICE_SINGLE_ACT_OTHER_ACTS 0x3
776 #define ICE_SINGLE_OTHER_ACT_IDENTIFIER_S 17
777 #define ICE_SINGLE_OTHER_ACT_IDENTIFIER_M \
778 (0x3 << \ ICE_SINGLE_OTHER_ACT_IDENTIFIER_S)
780 /* Bit 17:18 - Defines other actions */
781 /* Other action = 0 - Mirror VSI */
782 #define ICE_SINGLE_OTHER_ACT_MIRROR 0
783 #define ICE_SINGLE_ACT_MIRROR_VSI_ID_S 4
784 #define ICE_SINGLE_ACT_MIRROR_VSI_ID_M \
785 (0x3FF << ICE_SINGLE_ACT_MIRROR_VSI_ID_S)
787 /* Other action = 3 - Set Stat count */
788 #define ICE_SINGLE_OTHER_ACT_STAT_COUNT 3
789 #define ICE_SINGLE_ACT_STAT_COUNT_INDEX_S 4
790 #define ICE_SINGLE_ACT_STAT_COUNT_INDEX_M \
791 (0x7F << ICE_SINGLE_ACT_STAT_COUNT_INDEX_S)
793 __le16 index; /* The index of the rule in the lookup table */
794 /* Length and values of the header to be matched per recipe or
803 /* Add/Update/Remove large action command/response entry
804 * "index" is returned as part of a response to a successful Add command, and
805 * can be used to identify the action for Update/Get/Remove commands.
807 struct ice_sw_rule_lg_act {
808 __le16 index; /* Index in large action table */
810 __le32 act[1]; /* array of size for actions */
811 /* Max number of large actions */
812 #define ICE_MAX_LG_ACT 4
813 /* Bit 0:1 - Action type */
814 #define ICE_LG_ACT_TYPE_S 0
815 #define ICE_LG_ACT_TYPE_M (0x7 << ICE_LG_ACT_TYPE_S)
817 /* Action type = 0 - Forward to VSI or VSI list */
818 #define ICE_LG_ACT_VSI_FORWARDING 0
819 #define ICE_LG_ACT_VSI_ID_S 3
820 #define ICE_LG_ACT_VSI_ID_M (0x3FF << ICE_LG_ACT_VSI_ID_S)
821 #define ICE_LG_ACT_VSI_LIST_ID_S 3
822 #define ICE_LG_ACT_VSI_LIST_ID_M (0x3FF << ICE_LG_ACT_VSI_LIST_ID_S)
823 /* This bit needs to be set if action is forward to VSI list */
824 #define ICE_LG_ACT_VSI_LIST BIT(13)
826 #define ICE_LG_ACT_VALID_BIT BIT(16)
828 /* Action type = 1 - Forward to Queue of Queue group */
829 #define ICE_LG_ACT_TO_Q 0x1
830 #define ICE_LG_ACT_Q_INDEX_S 3
831 #define ICE_LG_ACT_Q_INDEX_M (0x7FF << ICE_LG_ACT_Q_INDEX_S)
832 #define ICE_LG_ACT_Q_REGION_S 14
833 #define ICE_LG_ACT_Q_REGION_M (0x7 << ICE_LG_ACT_Q_REGION_S)
834 #define ICE_LG_ACT_Q_PRIORITY_SET BIT(17)
836 /* Action type = 2 - Prune */
837 #define ICE_LG_ACT_PRUNE 0x2
838 #define ICE_LG_ACT_EGRESS BIT(14)
839 #define ICE_LG_ACT_INGRESS BIT(15)
840 #define ICE_LG_ACT_PRUNET BIT(16)
842 /* Action type = 3 - Mirror VSI */
843 #define ICE_LG_OTHER_ACT_MIRROR 0x3
844 #define ICE_LG_ACT_MIRROR_VSI_ID_S 3
845 #define ICE_LG_ACT_MIRROR_VSI_ID_M (0x3FF << ICE_LG_ACT_MIRROR_VSI_ID_S)
847 /* Action type = 5 - Generic Value */
848 #define ICE_LG_ACT_GENERIC 0x5
849 #define ICE_LG_ACT_GENERIC_VALUE_S 3
850 #define ICE_LG_ACT_GENERIC_VALUE_M (0xFFFF << ICE_LG_ACT_GENERIC_VALUE_S)
851 #define ICE_LG_ACT_GENERIC_OFFSET_S 19
852 #define ICE_LG_ACT_GENERIC_OFFSET_M (0x7 << ICE_LG_ACT_GENERIC_OFFSET_S)
853 #define ICE_LG_ACT_GENERIC_PRIORITY_S 22
854 #define ICE_LG_ACT_GENERIC_PRIORITY_M (0x7 << ICE_LG_ACT_GENERIC_PRIORITY_S)
855 #define ICE_LG_ACT_GENERIC_OFF_RX_DESC_PROF_IDX 7
857 /* Action = 7 - Set Stat count */
858 #define ICE_LG_ACT_STAT_COUNT 0x7
859 #define ICE_LG_ACT_STAT_COUNT_S 3
860 #define ICE_LG_ACT_STAT_COUNT_M (0x7F << ICE_LG_ACT_STAT_COUNT_S)
864 /* Add/Update/Remove VSI list command/response entry
865 * "index" is returned as part of a response to a successful Add command, and
866 * can be used to identify the VSI list for Update/Get/Remove commands.
868 struct ice_sw_rule_vsi_list {
869 __le16 index; /* Index of VSI/Prune list */
871 __le16 vsi[1]; /* Array of number_vsi VSI numbers */
876 /* Query VSI list command/response entry */
877 struct ice_sw_rule_vsi_list_query {
879 ice_declare_bitmap(vsi_list, ICE_MAX_VSI);
885 /* Add switch rule response:
886 * Content of return buffer is same as the input buffer. The status field and
887 * LUT index are updated as part of the response
889 struct ice_aqc_sw_rules_elem {
890 __le16 type; /* Switch rule type, one of T_... */
891 #define ICE_AQC_SW_RULES_T_LKUP_RX 0x0
892 #define ICE_AQC_SW_RULES_T_LKUP_TX 0x1
893 #define ICE_AQC_SW_RULES_T_LG_ACT 0x2
894 #define ICE_AQC_SW_RULES_T_VSI_LIST_SET 0x3
895 #define ICE_AQC_SW_RULES_T_VSI_LIST_CLEAR 0x4
896 #define ICE_AQC_SW_RULES_T_PRUNE_LIST_SET 0x5
897 #define ICE_AQC_SW_RULES_T_PRUNE_LIST_CLEAR 0x6
900 struct ice_sw_rule_lkup_rx_tx lkup_tx_rx;
901 struct ice_sw_rule_lg_act lg_act;
902 struct ice_sw_rule_vsi_list vsi_list;
903 struct ice_sw_rule_vsi_list_query vsi_list_query;
910 /* PFC Ignore (direct 0x0301)
911 * The command and response use the same descriptor structure
913 struct ice_aqc_pfc_ignore {
915 u8 cmd_flags; /* unused in response */
916 #define ICE_AQC_PFC_IGNORE_SET BIT(7)
917 #define ICE_AQC_PFC_IGNORE_CLEAR 0
921 /* Set PFC Mode (direct 0x0303)
922 * Query PFC Mode (direct 0x0302)
924 struct ice_aqc_set_query_pfc_mode {
926 /* For Set Command response, reserved in all other cases */
927 #define ICE_AQC_PFC_NOT_CONFIGURED 0
928 /* For Query Command response, reserved in all other cases */
929 #define ICE_AQC_DCB_DIS 0
930 #define ICE_AQC_PFC_VLAN_BASED_PFC 1
931 #define ICE_AQC_PFC_DSCP_BASED_PFC 2
935 /* Set DCB Parameters (direct 0x0306) */
936 struct ice_aqc_set_dcb_params {
937 u8 cmd_flags; /* unused in response */
938 #define ICE_AQC_LINK_UP_DCB_CFG BIT(0)
939 u8 valid_flags; /* unused in response */
940 #define ICE_AQC_LINK_UP_DCB_CFG_VALID BIT(0)
945 /* Get Default Topology (indirect 0x0400) */
946 struct ice_aqc_get_topo {
956 /* Update TSE (indirect 0x0403)
957 * Get TSE (indirect 0x0404)
958 * Add TSE (indirect 0x0401)
959 * Delete TSE (indirect 0x040F)
960 * Move TSE (indirect 0x0408)
961 * Suspend Nodes (indirect 0x0409)
962 * Resume Nodes (indirect 0x040A)
964 struct ice_aqc_sched_elem_cmd {
965 __le16 num_elem_req; /* Used by commands */
966 __le16 num_elem_resp; /* Used by responses */
973 /* This is the buffer for:
974 * Suspend Nodes (indirect 0x0409)
975 * Resume Nodes (indirect 0x040A)
977 struct ice_aqc_suspend_resume_elem {
982 struct ice_aqc_txsched_move_grp_info_hdr {
983 __le32 src_parent_teid;
984 __le32 dest_parent_teid;
990 struct ice_aqc_move_elem {
991 struct ice_aqc_txsched_move_grp_info_hdr hdr;
996 struct ice_aqc_elem_info_bw {
997 __le16 bw_profile_idx;
1002 struct ice_aqc_txsched_elem {
1003 u8 elem_type; /* Special field, reserved for some aq calls */
1004 #define ICE_AQC_ELEM_TYPE_UNDEFINED 0x0
1005 #define ICE_AQC_ELEM_TYPE_ROOT_PORT 0x1
1006 #define ICE_AQC_ELEM_TYPE_TC 0x2
1007 #define ICE_AQC_ELEM_TYPE_SE_GENERIC 0x3
1008 #define ICE_AQC_ELEM_TYPE_ENTRY_POINT 0x4
1009 #define ICE_AQC_ELEM_TYPE_LEAF 0x5
1010 #define ICE_AQC_ELEM_TYPE_SE_PADDED 0x6
1012 #define ICE_AQC_ELEM_VALID_GENERIC BIT(0)
1013 #define ICE_AQC_ELEM_VALID_CIR BIT(1)
1014 #define ICE_AQC_ELEM_VALID_EIR BIT(2)
1015 #define ICE_AQC_ELEM_VALID_SHARED BIT(3)
1017 #define ICE_AQC_ELEM_GENERIC_MODE_M 0x1
1018 #define ICE_AQC_ELEM_GENERIC_PRIO_S 0x1
1019 #define ICE_AQC_ELEM_GENERIC_PRIO_M (0x7 << ICE_AQC_ELEM_GENERIC_PRIO_S)
1020 #define ICE_AQC_ELEM_GENERIC_SP_S 0x4
1021 #define ICE_AQC_ELEM_GENERIC_SP_M (0x1 << ICE_AQC_ELEM_GENERIC_SP_S)
1022 #define ICE_AQC_ELEM_GENERIC_ADJUST_VAL_S 0x5
1023 #define ICE_AQC_ELEM_GENERIC_ADJUST_VAL_M \
1024 (0x3 << ICE_AQC_ELEM_GENERIC_ADJUST_VAL_S)
1025 u8 flags; /* Special field, reserved for some aq calls */
1026 #define ICE_AQC_ELEM_FLAG_SUSPEND_M 0x1
1027 struct ice_aqc_elem_info_bw cir_bw;
1028 struct ice_aqc_elem_info_bw eir_bw;
1034 struct ice_aqc_txsched_elem_data {
1037 struct ice_aqc_txsched_elem data;
1041 struct ice_aqc_txsched_topo_grp_info_hdr {
1048 struct ice_aqc_add_elem {
1049 struct ice_aqc_txsched_topo_grp_info_hdr hdr;
1050 struct ice_aqc_txsched_elem_data generic[1];
1054 struct ice_aqc_conf_elem {
1055 struct ice_aqc_txsched_elem_data generic[1];
1059 struct ice_aqc_get_elem {
1060 struct ice_aqc_txsched_elem_data generic[1];
1064 struct ice_aqc_get_topo_elem {
1065 struct ice_aqc_txsched_topo_grp_info_hdr hdr;
1066 struct ice_aqc_txsched_elem_data
1067 generic[ICE_AQC_TOPO_MAX_LEVEL_NUM];
1071 struct ice_aqc_delete_elem {
1072 struct ice_aqc_txsched_topo_grp_info_hdr hdr;
1077 /* Query Port ETS (indirect 0x040E)
1079 * This indirect command is used to query port TC node configuration.
1081 struct ice_aqc_query_port_ets {
1088 struct ice_aqc_port_ets_elem {
1091 /* 3 bits for UP per TC 0-7, 4th byte reserved */
1094 __le32 port_eir_prof_id;
1095 __le32 port_cir_prof_id;
1096 /* 3 bits per Node priority to TC 0-7, 4th byte reserved */
1097 __le32 tc_node_prio;
1098 #define ICE_TC_NODE_PRIO_S 0x4
1100 __le32 tc_node_teid[8]; /* Used for response, reserved in command */
1104 /* Rate limiting profile for
1105 * Add RL profile (indirect 0x0410)
1106 * Query RL profile (indirect 0x0411)
1107 * Remove RL profile (indirect 0x0415)
1108 * These indirect commands acts on single or multiple
1109 * RL profiles with specified data.
1111 struct ice_aqc_rl_profile {
1112 __le16 num_profiles;
1113 __le16 num_processed; /* Only for response. Reserved in Command. */
1120 struct ice_aqc_rl_profile_elem {
1123 #define ICE_AQC_RL_PROFILE_TYPE_S 0x0
1124 #define ICE_AQC_RL_PROFILE_TYPE_M (0x3 << ICE_AQC_RL_PROFILE_TYPE_S)
1125 #define ICE_AQC_RL_PROFILE_TYPE_CIR 0
1126 #define ICE_AQC_RL_PROFILE_TYPE_EIR 1
1127 #define ICE_AQC_RL_PROFILE_TYPE_SRL 2
1128 /* The following flag is used for Query RL Profile Data */
1129 #define ICE_AQC_RL_PROFILE_INVAL_S 0x7
1130 #define ICE_AQC_RL_PROFILE_INVAL_M (0x1 << ICE_AQC_RL_PROFILE_INVAL_S)
1133 __le16 max_burst_size;
1135 __le16 wake_up_calc;
1140 struct ice_aqc_rl_profile_generic_elem {
1141 struct ice_aqc_rl_profile_elem generic[1];
1146 /* Configure L2 Node CGD (indirect 0x0414)
1147 * This indirect command allows configuring a congestion domain for given L2
1148 * node TEIDs in the scheduler topology.
1150 struct ice_aqc_cfg_l2_node_cgd {
1151 __le16 num_l2_nodes;
1158 struct ice_aqc_cfg_l2_node_cgd_elem {
1165 struct ice_aqc_cfg_l2_node_cgd_data {
1166 struct ice_aqc_cfg_l2_node_cgd_elem elem[1];
1170 /* Query Scheduler Resource Allocation (indirect 0x0412)
1171 * This indirect command retrieves the scheduler resources allocated by
1172 * EMP Firmware to the given PF.
1174 struct ice_aqc_query_txsched_res {
1181 struct ice_aqc_generic_sched_props {
1183 __le16 logical_levels;
1184 u8 flattening_bitmap;
1193 struct ice_aqc_layer_props {
1196 __le16 max_device_nodes;
1197 __le16 max_pf_nodes;
1199 __le16 max_sibl_grp_sz;
1200 __le16 max_cir_rl_profiles;
1201 __le16 max_eir_rl_profiles;
1202 __le16 max_srl_profiles;
1207 struct ice_aqc_query_txsched_res_resp {
1208 struct ice_aqc_generic_sched_props sched_props;
1209 struct ice_aqc_layer_props layer_props[ICE_AQC_TOPO_MAX_LEVEL_NUM];
1213 /* Query Node to Root Topology (indirect 0x0413)
1214 * This command uses ice_aqc_get_elem as its data buffer.
1216 struct ice_aqc_query_node_to_root {
1218 __le32 num_nodes; /* Response only */
1224 /* Get PHY capabilities (indirect 0x0600) */
1225 struct ice_aqc_get_phy_caps {
1229 /* 18.0 - Report qualified modules */
1230 #define ICE_AQC_GET_PHY_RQM BIT(0)
1231 /* 18.1 - 18.2 : Report mode
1232 * 00b - Report NVM capabilities
1233 * 01b - Report topology capabilities
1234 * 10b - Report SW configured
1236 #define ICE_AQC_REPORT_MODE_S 1
1237 #define ICE_AQC_REPORT_MODE_M (3 << ICE_AQC_REPORT_MODE_S)
1238 #define ICE_AQC_REPORT_NVM_CAP 0
1239 #define ICE_AQC_REPORT_TOPO_CAP BIT(1)
1240 #define ICE_AQC_REPORT_SW_CFG BIT(2)
1247 /* This is #define of PHY type (Extended):
1248 * The first set of defines is for phy_type_low.
1250 #define ICE_PHY_TYPE_LOW_100BASE_TX BIT_ULL(0)
1251 #define ICE_PHY_TYPE_LOW_100M_SGMII BIT_ULL(1)
1252 #define ICE_PHY_TYPE_LOW_1000BASE_T BIT_ULL(2)
1253 #define ICE_PHY_TYPE_LOW_1000BASE_SX BIT_ULL(3)
1254 #define ICE_PHY_TYPE_LOW_1000BASE_LX BIT_ULL(4)
1255 #define ICE_PHY_TYPE_LOW_1000BASE_KX BIT_ULL(5)
1256 #define ICE_PHY_TYPE_LOW_1G_SGMII BIT_ULL(6)
1257 #define ICE_PHY_TYPE_LOW_2500BASE_T BIT_ULL(7)
1258 #define ICE_PHY_TYPE_LOW_2500BASE_X BIT_ULL(8)
1259 #define ICE_PHY_TYPE_LOW_2500BASE_KX BIT_ULL(9)
1260 #define ICE_PHY_TYPE_LOW_5GBASE_T BIT_ULL(10)
1261 #define ICE_PHY_TYPE_LOW_5GBASE_KR BIT_ULL(11)
1262 #define ICE_PHY_TYPE_LOW_10GBASE_T BIT_ULL(12)
1263 #define ICE_PHY_TYPE_LOW_10G_SFI_DA BIT_ULL(13)
1264 #define ICE_PHY_TYPE_LOW_10GBASE_SR BIT_ULL(14)
1265 #define ICE_PHY_TYPE_LOW_10GBASE_LR BIT_ULL(15)
1266 #define ICE_PHY_TYPE_LOW_10GBASE_KR_CR1 BIT_ULL(16)
1267 #define ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC BIT_ULL(17)
1268 #define ICE_PHY_TYPE_LOW_10G_SFI_C2C BIT_ULL(18)
1269 #define ICE_PHY_TYPE_LOW_25GBASE_T BIT_ULL(19)
1270 #define ICE_PHY_TYPE_LOW_25GBASE_CR BIT_ULL(20)
1271 #define ICE_PHY_TYPE_LOW_25GBASE_CR_S BIT_ULL(21)
1272 #define ICE_PHY_TYPE_LOW_25GBASE_CR1 BIT_ULL(22)
1273 #define ICE_PHY_TYPE_LOW_25GBASE_SR BIT_ULL(23)
1274 #define ICE_PHY_TYPE_LOW_25GBASE_LR BIT_ULL(24)
1275 #define ICE_PHY_TYPE_LOW_25GBASE_KR BIT_ULL(25)
1276 #define ICE_PHY_TYPE_LOW_25GBASE_KR_S BIT_ULL(26)
1277 #define ICE_PHY_TYPE_LOW_25GBASE_KR1 BIT_ULL(27)
1278 #define ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC BIT_ULL(28)
1279 #define ICE_PHY_TYPE_LOW_25G_AUI_C2C BIT_ULL(29)
1280 #define ICE_PHY_TYPE_LOW_40GBASE_CR4 BIT_ULL(30)
1281 #define ICE_PHY_TYPE_LOW_40GBASE_SR4 BIT_ULL(31)
1282 #define ICE_PHY_TYPE_LOW_40GBASE_LR4 BIT_ULL(32)
1283 #define ICE_PHY_TYPE_LOW_40GBASE_KR4 BIT_ULL(33)
1284 #define ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC BIT_ULL(34)
1285 #define ICE_PHY_TYPE_LOW_40G_XLAUI BIT_ULL(35)
1286 #define ICE_PHY_TYPE_LOW_50GBASE_CR2 BIT_ULL(36)
1287 #define ICE_PHY_TYPE_LOW_50GBASE_SR2 BIT_ULL(37)
1288 #define ICE_PHY_TYPE_LOW_50GBASE_LR2 BIT_ULL(38)
1289 #define ICE_PHY_TYPE_LOW_50GBASE_KR2 BIT_ULL(39)
1290 #define ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC BIT_ULL(40)
1291 #define ICE_PHY_TYPE_LOW_50G_LAUI2 BIT_ULL(41)
1292 #define ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC BIT_ULL(42)
1293 #define ICE_PHY_TYPE_LOW_50G_AUI2 BIT_ULL(43)
1294 #define ICE_PHY_TYPE_LOW_50GBASE_CP BIT_ULL(44)
1295 #define ICE_PHY_TYPE_LOW_50GBASE_SR BIT_ULL(45)
1296 #define ICE_PHY_TYPE_LOW_50GBASE_FR BIT_ULL(46)
1297 #define ICE_PHY_TYPE_LOW_50GBASE_LR BIT_ULL(47)
1298 #define ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4 BIT_ULL(48)
1299 #define ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC BIT_ULL(49)
1300 #define ICE_PHY_TYPE_LOW_50G_AUI1 BIT_ULL(50)
1301 #define ICE_PHY_TYPE_LOW_100GBASE_CR4 BIT_ULL(51)
1302 #define ICE_PHY_TYPE_LOW_100GBASE_SR4 BIT_ULL(52)
1303 #define ICE_PHY_TYPE_LOW_100GBASE_LR4 BIT_ULL(53)
1304 #define ICE_PHY_TYPE_LOW_100GBASE_KR4 BIT_ULL(54)
1305 #define ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC BIT_ULL(55)
1306 #define ICE_PHY_TYPE_LOW_100G_CAUI4 BIT_ULL(56)
1307 #define ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC BIT_ULL(57)
1308 #define ICE_PHY_TYPE_LOW_100G_AUI4 BIT_ULL(58)
1309 #define ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4 BIT_ULL(59)
1310 #define ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4 BIT_ULL(60)
1311 #define ICE_PHY_TYPE_LOW_100GBASE_CP2 BIT_ULL(61)
1312 #define ICE_PHY_TYPE_LOW_100GBASE_SR2 BIT_ULL(62)
1313 #define ICE_PHY_TYPE_LOW_100GBASE_DR BIT_ULL(63)
1314 #define ICE_PHY_TYPE_LOW_MAX_INDEX 63
1315 /* The second set of defines is for phy_type_high. */
1316 #define ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4 BIT_ULL(0)
1317 #define ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC BIT_ULL(1)
1318 #define ICE_PHY_TYPE_HIGH_100G_CAUI2 BIT_ULL(2)
1319 #define ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC BIT_ULL(3)
1320 #define ICE_PHY_TYPE_HIGH_100G_AUI2 BIT_ULL(4)
1321 #define ICE_PHY_TYPE_HIGH_MAX_INDEX 19
1323 struct ice_aqc_get_phy_caps_data {
1324 __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */
1325 __le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */
1327 #define ICE_AQC_PHY_EN_TX_LINK_PAUSE BIT(0)
1328 #define ICE_AQC_PHY_EN_RX_LINK_PAUSE BIT(1)
1329 #define ICE_AQC_PHY_LOW_POWER_MODE BIT(2)
1330 #define ICE_AQC_PHY_EN_LINK BIT(3)
1331 #define ICE_AQC_PHY_AN_MODE BIT(4)
1332 #define ICE_AQC_PHY_EN_MOD_QUAL BIT(5)
1333 #define ICE_AQC_PHY_EN_LESM BIT(6)
1334 #define ICE_AQC_PHY_EN_AUTO_FEC BIT(7)
1335 #define ICE_AQC_PHY_CAPS_MASK MAKEMASK(0xff, 0)
1337 #define ICE_AQC_PHY_EN_D3COLD_LOW_POWER_AUTONEG BIT(0)
1339 #define ICE_AQC_PHY_EEE_EN_100BASE_TX BIT(0)
1340 #define ICE_AQC_PHY_EEE_EN_1000BASE_T BIT(1)
1341 #define ICE_AQC_PHY_EEE_EN_10GBASE_T BIT(2)
1342 #define ICE_AQC_PHY_EEE_EN_1000BASE_KX BIT(3)
1343 #define ICE_AQC_PHY_EEE_EN_10GBASE_KR BIT(4)
1344 #define ICE_AQC_PHY_EEE_EN_25GBASE_KR BIT(5)
1345 #define ICE_AQC_PHY_EEE_EN_40GBASE_KR4 BIT(6)
1346 #define ICE_AQC_PHY_EEE_EN_50GBASE_KR2 BIT(7)
1347 #define ICE_AQC_PHY_EEE_EN_50GBASE_KR_PAM4 BIT(8)
1348 #define ICE_AQC_PHY_EEE_EN_100GBASE_KR4 BIT(9)
1349 #define ICE_AQC_PHY_EEE_EN_100GBASE_KR2_PAM4 BIT(10)
1351 u8 phy_id_oui[4]; /* PHY/Module ID connected on the port */
1353 u8 link_fec_options;
1354 #define ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN BIT(0)
1355 #define ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ BIT(1)
1356 #define ICE_AQC_PHY_FEC_25G_RS_528_REQ BIT(2)
1357 #define ICE_AQC_PHY_FEC_25G_KR_REQ BIT(3)
1358 #define ICE_AQC_PHY_FEC_25G_RS_544_REQ BIT(4)
1359 #define ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN BIT(6)
1360 #define ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN BIT(7)
1361 #define ICE_AQC_PHY_FEC_MASK MAKEMASK(0xdf, 0)
1362 u8 extended_compliance_code;
1363 #define ICE_MODULE_TYPE_TOTAL_BYTE 3
1364 u8 module_type[ICE_MODULE_TYPE_TOTAL_BYTE];
1365 #define ICE_AQC_MOD_TYPE_BYTE0_SFP_PLUS 0xA0
1366 #define ICE_AQC_MOD_TYPE_BYTE0_QSFP_PLUS 0x80
1367 #define ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_PASSIVE BIT(0)
1368 #define ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_ACTIVE BIT(1)
1369 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_SR BIT(4)
1370 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_LR BIT(5)
1371 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_LRM BIT(6)
1372 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_ER BIT(7)
1373 #define ICE_AQC_MOD_TYPE_BYTE2_SFP_PLUS 0xA0
1374 #define ICE_AQC_MOD_TYPE_BYTE2_QSFP_PLUS 0x86
1375 u8 qualified_module_count;
1376 #define ICE_AQC_QUAL_MOD_COUNT_MAX 16
1383 } qual_modules[ICE_AQC_QUAL_MOD_COUNT_MAX];
1387 /* Set PHY capabilities (direct 0x0601)
1388 * NOTE: This command must be followed by setup link and restart auto-neg
1390 struct ice_aqc_set_phy_cfg {
1398 /* Set PHY config command data structure */
1399 struct ice_aqc_set_phy_cfg_data {
1400 __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */
1401 __le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */
1403 #define ICE_AQ_PHY_ENA_VALID_MASK MAKEMASK(0xef, 0)
1404 #define ICE_AQ_PHY_ENA_TX_PAUSE_ABILITY BIT(0)
1405 #define ICE_AQ_PHY_ENA_RX_PAUSE_ABILITY BIT(1)
1406 #define ICE_AQ_PHY_ENA_LOW_POWER BIT(2)
1407 #define ICE_AQ_PHY_ENA_LINK BIT(3)
1408 #define ICE_AQ_PHY_ENA_AUTO_LINK_UPDT BIT(5)
1409 #define ICE_AQ_PHY_ENA_LESM BIT(6)
1410 #define ICE_AQ_PHY_ENA_AUTO_FEC BIT(7)
1412 __le16 eee_cap; /* Value from ice_aqc_get_phy_caps */
1414 u8 link_fec_opt; /* Use defines from ice_aqc_get_phy_caps */
1419 /* Set MAC Config command data structure (direct 0x0603) */
1420 struct ice_aqc_set_mac_cfg {
1421 __le16 max_frame_size;
1423 #define ICE_AQ_SET_MAC_PACE_S 3
1424 #define ICE_AQ_SET_MAC_PACE_M (0xF << ICE_AQ_SET_MAC_PACE_S)
1425 #define ICE_AQ_SET_MAC_PACE_TYPE_M BIT(7)
1426 #define ICE_AQ_SET_MAC_PACE_TYPE_RATE 0
1427 #define ICE_AQ_SET_MAC_PACE_TYPE_FIXED ICE_AQ_SET_MAC_PACE_TYPE_M
1429 __le16 tx_tmr_value;
1430 __le16 fc_refresh_threshold;
1432 #define ICE_AQ_SET_MAC_AUTO_DROP_MASK BIT(0)
1433 #define ICE_AQ_SET_MAC_AUTO_DROP_NONE 0
1434 #define ICE_AQ_SET_MAC_AUTO_DROP_BLOCKING_PKTS BIT(0)
1439 /* Restart AN command data structure (direct 0x0605)
1440 * Also used for response, with only the lport_num field present.
1442 struct ice_aqc_restart_an {
1446 #define ICE_AQC_RESTART_AN_LINK_RESTART BIT(1)
1447 #define ICE_AQC_RESTART_AN_LINK_ENABLE BIT(2)
1452 /* Get link status (indirect 0x0607), also used for Link Status Event */
1453 struct ice_aqc_get_link_status {
1457 #define ICE_AQ_LSE_M 0x3
1458 #define ICE_AQ_LSE_NOP 0x0
1459 #define ICE_AQ_LSE_DIS 0x2
1460 #define ICE_AQ_LSE_ENA 0x3
1461 /* only response uses this flag */
1462 #define ICE_AQ_LSE_IS_ENABLED 0x1
1469 /* Get link status response data structure, also used for Link Status Event */
1470 struct ice_aqc_get_link_status_data {
1471 u8 topo_media_conflict;
1472 #define ICE_AQ_LINK_TOPO_CONFLICT BIT(0)
1473 #define ICE_AQ_LINK_MEDIA_CONFLICT BIT(1)
1474 #define ICE_AQ_LINK_TOPO_CORRUPT BIT(2)
1475 #define ICE_AQ_LINK_TOPO_UNREACH_PRT BIT(4)
1476 #define ICE_AQ_LINK_TOPO_UNDRUTIL_PRT BIT(5)
1477 #define ICE_AQ_LINK_TOPO_UNDRUTIL_MEDIA BIT(6)
1478 #define ICE_AQ_LINK_TOPO_UNSUPP_MEDIA BIT(7)
1480 #define ICE_AQ_LINK_CFG_ERR BIT(0)
1482 #define ICE_AQ_LINK_UP BIT(0) /* Link Status */
1483 #define ICE_AQ_LINK_FAULT BIT(1)
1484 #define ICE_AQ_LINK_FAULT_TX BIT(2)
1485 #define ICE_AQ_LINK_FAULT_RX BIT(3)
1486 #define ICE_AQ_LINK_FAULT_REMOTE BIT(4)
1487 #define ICE_AQ_LINK_UP_PORT BIT(5) /* External Port Link Status */
1488 #define ICE_AQ_MEDIA_AVAILABLE BIT(6)
1489 #define ICE_AQ_SIGNAL_DETECT BIT(7)
1491 #define ICE_AQ_AN_COMPLETED BIT(0)
1492 #define ICE_AQ_LP_AN_ABILITY BIT(1)
1493 #define ICE_AQ_PD_FAULT BIT(2) /* Parallel Detection Fault */
1494 #define ICE_AQ_FEC_EN BIT(3)
1495 #define ICE_AQ_PHY_LOW_POWER BIT(4) /* Low Power State */
1496 #define ICE_AQ_LINK_PAUSE_TX BIT(5)
1497 #define ICE_AQ_LINK_PAUSE_RX BIT(6)
1498 #define ICE_AQ_QUALIFIED_MODULE BIT(7)
1500 #define ICE_AQ_LINK_PHY_TEMP_ALARM BIT(0)
1501 #define ICE_AQ_LINK_EXCESSIVE_ERRORS BIT(1) /* Excessive Link Errors */
1502 /* Port Tx Suspended */
1503 #define ICE_AQ_LINK_TX_S 2
1504 #define ICE_AQ_LINK_TX_M (0x03 << ICE_AQ_LINK_TX_S)
1505 #define ICE_AQ_LINK_TX_ACTIVE 0
1506 #define ICE_AQ_LINK_TX_DRAINED 1
1507 #define ICE_AQ_LINK_TX_FLUSHED 3
1509 __le16 max_frame_size;
1511 #define ICE_AQ_LINK_25G_KR_FEC_EN BIT(0)
1512 #define ICE_AQ_LINK_25G_RS_528_FEC_EN BIT(1)
1513 #define ICE_AQ_LINK_25G_RS_544_FEC_EN BIT(2)
1514 #define ICE_AQ_FEC_MASK MAKEMASK(0x7, 0)
1516 #define ICE_AQ_CFG_PACING_S 3
1517 #define ICE_AQ_CFG_PACING_M (0xF << ICE_AQ_CFG_PACING_S)
1518 #define ICE_AQ_CFG_PACING_TYPE_M BIT(7)
1519 #define ICE_AQ_CFG_PACING_TYPE_AVG 0
1520 #define ICE_AQ_CFG_PACING_TYPE_FIXED ICE_AQ_CFG_PACING_TYPE_M
1521 /* External Device Power Ability */
1523 #define ICE_AQ_PWR_CLASS_M 0x3
1524 #define ICE_AQ_LINK_PWR_BASET_LOW_HIGH 0
1525 #define ICE_AQ_LINK_PWR_BASET_HIGH 1
1526 #define ICE_AQ_LINK_PWR_QSFP_CLASS_1 0
1527 #define ICE_AQ_LINK_PWR_QSFP_CLASS_2 1
1528 #define ICE_AQ_LINK_PWR_QSFP_CLASS_3 2
1529 #define ICE_AQ_LINK_PWR_QSFP_CLASS_4 3
1531 #define ICE_AQ_LINK_SPEED_10MB BIT(0)
1532 #define ICE_AQ_LINK_SPEED_100MB BIT(1)
1533 #define ICE_AQ_LINK_SPEED_1000MB BIT(2)
1534 #define ICE_AQ_LINK_SPEED_2500MB BIT(3)
1535 #define ICE_AQ_LINK_SPEED_5GB BIT(4)
1536 #define ICE_AQ_LINK_SPEED_10GB BIT(5)
1537 #define ICE_AQ_LINK_SPEED_20GB BIT(6)
1538 #define ICE_AQ_LINK_SPEED_25GB BIT(7)
1539 #define ICE_AQ_LINK_SPEED_40GB BIT(8)
1540 #define ICE_AQ_LINK_SPEED_50GB BIT(9)
1541 #define ICE_AQ_LINK_SPEED_100GB BIT(10)
1542 #define ICE_AQ_LINK_SPEED_UNKNOWN BIT(15)
1543 __le32 reserved3; /* Aligns next field to 8-byte boundary */
1544 __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */
1545 __le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */
1549 /* Set event mask command (direct 0x0613) */
1550 struct ice_aqc_set_event_mask {
1554 #define ICE_AQ_LINK_EVENT_UPDOWN BIT(1)
1555 #define ICE_AQ_LINK_EVENT_MEDIA_NA BIT(2)
1556 #define ICE_AQ_LINK_EVENT_LINK_FAULT BIT(3)
1557 #define ICE_AQ_LINK_EVENT_PHY_TEMP_ALARM BIT(4)
1558 #define ICE_AQ_LINK_EVENT_EXCESSIVE_ERRORS BIT(5)
1559 #define ICE_AQ_LINK_EVENT_SIGNAL_DETECT BIT(6)
1560 #define ICE_AQ_LINK_EVENT_AN_COMPLETED BIT(7)
1561 #define ICE_AQ_LINK_EVENT_MODULE_QUAL_FAIL BIT(8)
1562 #define ICE_AQ_LINK_EVENT_PORT_TX_SUSPENDED BIT(9)
1568 /* Set MAC Loopback command (direct 0x0620) */
1569 struct ice_aqc_set_mac_lb {
1571 #define ICE_AQ_MAC_LB_EN BIT(0)
1572 #define ICE_AQ_MAC_LB_OSC_CLK BIT(1)
1580 /* Set Port Identification LED (direct, 0x06E9) */
1581 struct ice_aqc_set_port_id_led {
1584 #define ICE_AQC_PORT_ID_PORT_NUM_VALID BIT(0)
1586 #define ICE_AQC_PORT_IDENT_LED_BLINK BIT(0)
1587 #define ICE_AQC_PORT_IDENT_LED_ORIG 0
1593 /* NVM Read command (indirect 0x0701)
1594 * NVM Erase commands (direct 0x0702)
1595 * NVM Update commands (indirect 0x0703)
1597 struct ice_aqc_nvm {
1601 #define ICE_AQC_NVM_LAST_CMD BIT(0)
1602 #define ICE_AQC_NVM_PCIR_REQ BIT(0) /* Used by NVM Update reply */
1603 #define ICE_AQC_NVM_PRESERVATION_S 1
1604 #define ICE_AQC_NVM_PRESERVATION_M (3 << ICE_AQC_NVM_PRESERVATION_S)
1605 #define ICE_AQC_NVM_NO_PRESERVATION (0 << ICE_AQC_NVM_PRESERVATION_S)
1606 #define ICE_AQC_NVM_PRESERVE_ALL BIT(1)
1607 #define ICE_AQC_NVM_FACTORY_DEFAULT (2 << ICE_AQC_NVM_PRESERVATION_S)
1608 #define ICE_AQC_NVM_PRESERVE_SELECTED (3 << ICE_AQC_NVM_PRESERVATION_S)
1609 #define ICE_AQC_NVM_FLASH_ONLY BIT(7)
1610 __le16 module_typeid;
1612 #define ICE_AQC_NVM_ERASE_LEN 0xFFFF
1618 /* Used for 0x0704 as well as for 0x0705 commands */
1619 struct ice_aqc_nvm_cfg {
1621 #define ICE_AQC_ANVM_MULTIPLE_ELEMS BIT(0)
1622 #define ICE_AQC_ANVM_IMMEDIATE_FIELD BIT(1)
1623 #define ICE_AQC_ANVM_NEW_CFG BIT(2)
1633 struct ice_aqc_nvm_cfg_data {
1635 __le16 field_options;
1640 /* NVM Checksum Command (direct, 0x0706) */
1641 struct ice_aqc_nvm_checksum {
1643 #define ICE_AQC_NVM_CHECKSUM_VERIFY BIT(0)
1644 #define ICE_AQC_NVM_CHECKSUM_RECALC BIT(1)
1646 __le16 checksum; /* Used only by response */
1647 #define ICE_AQC_NVM_CHECKSUM_CORRECT 0xBABA
1654 /* Get LLDP MIB (indirect 0x0A00)
1655 * Note: This is also used by the LLDP MIB Change Event (0x0A01)
1656 * as the format is the same.
1658 struct ice_aqc_lldp_get_mib {
1660 #define ICE_AQ_LLDP_MIB_TYPE_S 0
1661 #define ICE_AQ_LLDP_MIB_TYPE_M (0x3 << ICE_AQ_LLDP_MIB_TYPE_S)
1662 #define ICE_AQ_LLDP_MIB_LOCAL 0
1663 #define ICE_AQ_LLDP_MIB_REMOTE 1
1664 #define ICE_AQ_LLDP_MIB_LOCAL_AND_REMOTE 2
1665 #define ICE_AQ_LLDP_BRID_TYPE_S 2
1666 #define ICE_AQ_LLDP_BRID_TYPE_M (0x3 << ICE_AQ_LLDP_BRID_TYPE_S)
1667 #define ICE_AQ_LLDP_BRID_TYPE_NEAREST_BRID 0
1668 #define ICE_AQ_LLDP_BRID_TYPE_NON_TPMR 1
1669 /* Tx pause flags in the 0xA01 event use ICE_AQ_LLDP_TX_* */
1670 #define ICE_AQ_LLDP_TX_S 0x4
1671 #define ICE_AQ_LLDP_TX_M (0x03 << ICE_AQ_LLDP_TX_S)
1672 #define ICE_AQ_LLDP_TX_ACTIVE 0
1673 #define ICE_AQ_LLDP_TX_SUSPENDED 1
1674 #define ICE_AQ_LLDP_TX_FLUSHED 3
1675 /* The following bytes are reserved for the Get LLDP MIB command (0x0A00)
1676 * and in the LLDP MIB Change Event (0x0A01). They are valid for the
1677 * Get LLDP MIB (0x0A00) response only.
1687 /* Configure LLDP MIB Change Event (direct 0x0A01) */
1688 /* For MIB Change Event use ice_aqc_lldp_get_mib structure above */
1689 struct ice_aqc_lldp_set_mib_change {
1691 #define ICE_AQ_LLDP_MIB_UPDATE_ENABLE 0x0
1692 #define ICE_AQ_LLDP_MIB_UPDATE_DIS 0x1
1696 /* Add LLDP TLV (indirect 0x0A02)
1697 * Delete LLDP TLV (indirect 0x0A04)
1699 struct ice_aqc_lldp_add_delete_tlv {
1700 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */
1708 /* Update LLDP TLV (indirect 0x0A03) */
1709 struct ice_aqc_lldp_update_tlv {
1710 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */
1719 /* Stop LLDP (direct 0x0A05) */
1720 struct ice_aqc_lldp_stop {
1722 #define ICE_AQ_LLDP_AGENT_STATE_MASK BIT(0)
1723 #define ICE_AQ_LLDP_AGENT_STOP 0x0
1724 #define ICE_AQ_LLDP_AGENT_SHUTDOWN ICE_AQ_LLDP_AGENT_STATE_MASK
1725 #define ICE_AQ_LLDP_AGENT_PERSIST_DIS BIT(1)
1729 /* Start LLDP (direct 0x0A06) */
1730 struct ice_aqc_lldp_start {
1732 #define ICE_AQ_LLDP_AGENT_START BIT(0)
1733 #define ICE_AQ_LLDP_AGENT_PERSIST_ENA BIT(1)
1737 /* Get CEE DCBX Oper Config (0x0A07)
1738 * The command uses the generic descriptor struct and
1739 * returns the struct below as an indirect response.
1741 struct ice_aqc_get_cee_dcb_cfg_resp {
1746 __le16 oper_app_prio;
1747 #define ICE_AQC_CEE_APP_FCOE_S 0
1748 #define ICE_AQC_CEE_APP_FCOE_M (0x7 << ICE_AQC_CEE_APP_FCOE_S)
1749 #define ICE_AQC_CEE_APP_ISCSI_S 3
1750 #define ICE_AQC_CEE_APP_ISCSI_M (0x7 << ICE_AQC_CEE_APP_ISCSI_S)
1751 #define ICE_AQC_CEE_APP_FIP_S 8
1752 #define ICE_AQC_CEE_APP_FIP_M (0x7 << ICE_AQC_CEE_APP_FIP_S)
1754 #define ICE_AQC_CEE_PG_STATUS_S 0
1755 #define ICE_AQC_CEE_PG_STATUS_M (0x7 << ICE_AQC_CEE_PG_STATUS_S)
1756 #define ICE_AQC_CEE_PFC_STATUS_S 3
1757 #define ICE_AQC_CEE_PFC_STATUS_M (0x7 << ICE_AQC_CEE_PFC_STATUS_S)
1758 #define ICE_AQC_CEE_FCOE_STATUS_S 8
1759 #define ICE_AQC_CEE_FCOE_STATUS_M (0x7 << ICE_AQC_CEE_FCOE_STATUS_S)
1760 #define ICE_AQC_CEE_ISCSI_STATUS_S 11
1761 #define ICE_AQC_CEE_ISCSI_STATUS_M (0x7 << ICE_AQC_CEE_ISCSI_STATUS_S)
1762 #define ICE_AQC_CEE_FIP_STATUS_S 16
1763 #define ICE_AQC_CEE_FIP_STATUS_M (0x7 << ICE_AQC_CEE_FIP_STATUS_S)
1767 /* Set Local LLDP MIB (indirect 0x0A08)
1768 * Used to replace the local MIB of a given LLDP agent. e.g. DCBx
1770 struct ice_aqc_lldp_set_local_mib {
1772 #define SET_LOCAL_MIB_TYPE_DCBX_M BIT(0)
1773 #define SET_LOCAL_MIB_TYPE_LOCAL_MIB 0
1774 #define SET_LOCAL_MIB_TYPE_CEE_M BIT(1)
1775 #define SET_LOCAL_MIB_TYPE_CEE_WILLING 0
1776 #define SET_LOCAL_MIB_TYPE_CEE_NON_WILLING SET_LOCAL_MIB_TYPE_CEE_M
1784 struct ice_aqc_lldp_set_local_mib_resp {
1786 #define SET_LOCAL_MIB_RESP_EVENT_M BIT(0)
1787 #define SET_LOCAL_MIB_RESP_MIB_CHANGE_SILENT 0
1788 #define SET_LOCAL_MIB_RESP_MIB_CHANGE_EVENT SET_LOCAL_MIB_RESP_EVENT_M
1792 /* Stop/Start LLDP Agent (direct 0x0A09)
1793 * Used for stopping/starting specific LLDP agent. e.g. DCBx.
1794 * The same structure is used for the response, with the command field
1795 * being used as the status field.
1797 struct ice_aqc_lldp_stop_start_specific_agent {
1799 #define ICE_AQC_START_STOP_AGENT_M BIT(0)
1800 #define ICE_AQC_START_STOP_AGENT_STOP_DCBX 0
1801 #define ICE_AQC_START_STOP_AGENT_START_DCBX ICE_AQC_START_STOP_AGENT_M
1806 /* Get/Set RSS key (indirect 0x0B04/0x0B02) */
1807 struct ice_aqc_get_set_rss_key {
1808 #define ICE_AQC_GSET_RSS_KEY_VSI_VALID BIT(15)
1809 #define ICE_AQC_GSET_RSS_KEY_VSI_ID_S 0
1810 #define ICE_AQC_GSET_RSS_KEY_VSI_ID_M (0x3FF << ICE_AQC_GSET_RSS_KEY_VSI_ID_S)
1818 #define ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE 0x28
1819 #define ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE 0xC
1820 #define ICE_GET_SET_RSS_KEY_EXTEND_KEY_SIZE \
1821 (ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE + \
1822 ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE)
1825 * struct ice_aqc_get_set_rss_keys - Get/Set RSS hash key command buffer
1826 * @standard_rss_key: 40 most significant bytes of hash key
1827 * @extended_hash_key: 12 least significant bytes of hash key
1829 * Set/Get 40 byte hash key using standard_rss_key field, and set
1830 * extended_hash_key field to zero. Set/Get 52 byte hash key using
1831 * standard_rss_key field for 40 most significant bytes and the
1832 * extended_hash_key field for the 12 least significant bytes of hash key.
1834 struct ice_aqc_get_set_rss_keys {
1835 u8 standard_rss_key[ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE];
1836 u8 extended_hash_key[ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE];
1840 /* Get/Set RSS LUT (indirect 0x0B05/0x0B03) */
1841 struct ice_aqc_get_set_rss_lut {
1842 #define ICE_AQC_GSET_RSS_LUT_VSI_VALID BIT(15)
1843 #define ICE_AQC_GSET_RSS_LUT_VSI_ID_S 0
1844 #define ICE_AQC_GSET_RSS_LUT_VSI_ID_M (0x1FF << ICE_AQC_GSET_RSS_LUT_VSI_ID_S)
1846 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S 0
1847 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_M \
1848 (0x3 << ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S)
1850 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_VSI 0
1851 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF 1
1852 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL 2
1854 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S 2
1855 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M \
1856 (0x3 << ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S)
1858 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128 128
1859 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128_FLAG 0
1860 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512 512
1861 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512_FLAG 1
1862 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K 2048
1863 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K_FLAG 2
1865 #define ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S 4
1866 #define ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_M \
1867 (0xF << ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S)
1876 /* Clear FD Table Command (direct, 0x0B06) */
1877 struct ice_aqc_clear_fd_table {
1879 #define CL_FD_VM_VF_TYPE_VSI_IDX 1
1880 #define CL_FD_VM_VF_TYPE_PF_IDX 2
1889 /* Add Tx LAN Queues (indirect 0x0C30) */
1890 struct ice_aqc_add_txqs {
1899 /* This is the descriptor of each queue entry for the Add Tx LAN Queues
1900 * command (0x0C30). Only used within struct ice_aqc_add_tx_qgrp.
1902 struct ice_aqc_add_txqs_perq {
1908 struct ice_aqc_txsched_elem info;
1912 /* The format of the command buffer for Add Tx LAN Queues (0x0C30)
1913 * is an array of the following structs. Please note that the length of
1914 * each struct ice_aqc_add_tx_qgrp is variable due
1915 * to the variable number of queues in each group!
1917 struct ice_aqc_add_tx_qgrp {
1921 struct ice_aqc_add_txqs_perq txqs[1];
1925 /* Disable Tx LAN Queues (indirect 0x0C31) */
1926 struct ice_aqc_dis_txqs {
1928 #define ICE_AQC_Q_DIS_CMD_S 0
1929 #define ICE_AQC_Q_DIS_CMD_M (0x3 << ICE_AQC_Q_DIS_CMD_S)
1930 #define ICE_AQC_Q_DIS_CMD_NO_FUNC_RESET (0 << ICE_AQC_Q_DIS_CMD_S)
1931 #define ICE_AQC_Q_DIS_CMD_VM_RESET BIT(ICE_AQC_Q_DIS_CMD_S)
1932 #define ICE_AQC_Q_DIS_CMD_VF_RESET (2 << ICE_AQC_Q_DIS_CMD_S)
1933 #define ICE_AQC_Q_DIS_CMD_PF_RESET (3 << ICE_AQC_Q_DIS_CMD_S)
1934 #define ICE_AQC_Q_DIS_CMD_SUBSEQ_CALL BIT(2)
1935 #define ICE_AQC_Q_DIS_CMD_FLUSH_PIPE BIT(3)
1937 __le16 vmvf_and_timeout;
1938 #define ICE_AQC_Q_DIS_VMVF_NUM_S 0
1939 #define ICE_AQC_Q_DIS_VMVF_NUM_M (0x3FF << ICE_AQC_Q_DIS_VMVF_NUM_S)
1940 #define ICE_AQC_Q_DIS_TIMEOUT_S 10
1941 #define ICE_AQC_Q_DIS_TIMEOUT_M (0x3F << ICE_AQC_Q_DIS_TIMEOUT_S)
1942 __le32 blocked_cgds;
1948 /* The buffer for Disable Tx LAN Queues (indirect 0x0C31)
1949 * contains the following structures, arrayed one after the
1951 * Note: Since the q_id is 16 bits wide, if the
1952 * number of queues is even, then 2 bytes of alignment MUST be
1953 * added before the start of the next group, to allow correct
1954 * alignment of the parent_teid field.
1956 struct ice_aqc_dis_txq_item {
1960 /* The length of the q_id array varies according to num_qs */
1962 /* This only applies from F8 onward */
1963 #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S 15
1964 #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_LAN_Q \
1965 (0 << ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S)
1966 #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_RDMA_QSET \
1967 (1 << ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S)
1971 struct ice_aqc_dis_txq {
1972 struct ice_aqc_dis_txq_item qgrps[1];
1976 /* Tx LAN Queues Cleanup Event (0x0C31) */
1977 struct ice_aqc_txqs_cleanup {
1984 /* Move / Reconfigure Tx Queues (indirect 0x0C32) */
1985 struct ice_aqc_move_txqs {
1987 #define ICE_AQC_Q_CMD_TYPE_S 0
1988 #define ICE_AQC_Q_CMD_TYPE_M (0x3 << ICE_AQC_Q_CMD_TYPE_S)
1989 #define ICE_AQC_Q_CMD_TYPE_MOVE 1
1990 #define ICE_AQC_Q_CMD_TYPE_TC_CHANGE 2
1991 #define ICE_AQC_Q_CMD_TYPE_MOVE_AND_TC 3
1992 #define ICE_AQC_Q_CMD_SUBSEQ_CALL BIT(2)
1993 #define ICE_AQC_Q_CMD_FLUSH_PIPE BIT(3)
1997 #define ICE_AQC_Q_CMD_TIMEOUT_S 2
1998 #define ICE_AQC_Q_CMD_TIMEOUT_M (0x3F << ICE_AQC_Q_CMD_TIMEOUT_S)
1999 __le32 blocked_cgds;
2005 /* This is the descriptor of each queue entry for the move Tx LAN Queues
2008 struct ice_aqc_move_txqs_elem {
2016 struct ice_aqc_move_txqs_data {
2019 struct ice_aqc_move_txqs_elem txqs[1];
2024 /* Download Package (indirect 0x0C40) */
2025 /* Also used for Update Package (indirect 0x0C42) */
2026 struct ice_aqc_download_pkg {
2028 #define ICE_AQC_DOWNLOAD_PKG_LAST_BUF 0x01
2035 struct ice_aqc_download_pkg_resp {
2036 __le32 error_offset;
2042 /* Get Package Info List (indirect 0x0C43) */
2043 struct ice_aqc_get_pkg_info_list {
2050 /* Version format for packages */
2051 struct ice_pkg_ver {
2058 #define ICE_PKG_NAME_SIZE 32
2060 struct ice_aqc_get_pkg_info {
2061 struct ice_pkg_ver ver;
2062 char name[ICE_PKG_NAME_SIZE];
2065 u8 is_active_at_boot;
2069 /* Get Package Info List response buffer format (0x0C43) */
2070 struct ice_aqc_get_pkg_info_resp {
2072 struct ice_aqc_get_pkg_info pkg_info[1];
2078 /* Lan Queue Overflow Event (direct, 0x1001) */
2079 struct ice_aqc_event_lan_overflow {
2080 __le32 prtdcb_ruptq;
2087 /* Configure Firmware Logging Command (indirect 0xFF09)
2088 * Logging Information Read Response (indirect 0xFF10)
2089 * Note: The 0xFF10 command has no input parameters.
2091 struct ice_aqc_fw_logging {
2093 #define ICE_AQC_FW_LOG_AQ_EN BIT(0)
2094 #define ICE_AQC_FW_LOG_UART_EN BIT(1)
2096 u8 log_ctrl_valid; /* Not used by 0xFF10 Response */
2097 #define ICE_AQC_FW_LOG_AQ_VALID BIT(0)
2098 #define ICE_AQC_FW_LOG_UART_VALID BIT(1)
2105 enum ice_aqc_fw_logging_mod {
2106 ICE_AQC_FW_LOG_ID_GENERAL = 0,
2107 ICE_AQC_FW_LOG_ID_CTRL,
2108 ICE_AQC_FW_LOG_ID_LINK,
2109 ICE_AQC_FW_LOG_ID_LINK_TOPO,
2110 ICE_AQC_FW_LOG_ID_DNL,
2111 ICE_AQC_FW_LOG_ID_I2C,
2112 ICE_AQC_FW_LOG_ID_SDP,
2113 ICE_AQC_FW_LOG_ID_MDIO,
2114 ICE_AQC_FW_LOG_ID_ADMINQ,
2115 ICE_AQC_FW_LOG_ID_HDMA,
2116 ICE_AQC_FW_LOG_ID_LLDP,
2117 ICE_AQC_FW_LOG_ID_DCBX,
2118 ICE_AQC_FW_LOG_ID_DCB,
2119 ICE_AQC_FW_LOG_ID_NETPROXY,
2120 ICE_AQC_FW_LOG_ID_NVM,
2121 ICE_AQC_FW_LOG_ID_AUTH,
2122 ICE_AQC_FW_LOG_ID_VPD,
2123 ICE_AQC_FW_LOG_ID_IOSF,
2124 ICE_AQC_FW_LOG_ID_PARSER,
2125 ICE_AQC_FW_LOG_ID_SW,
2126 ICE_AQC_FW_LOG_ID_SCHEDULER,
2127 ICE_AQC_FW_LOG_ID_TXQ,
2128 ICE_AQC_FW_LOG_ID_RSVD,
2129 ICE_AQC_FW_LOG_ID_POST,
2130 ICE_AQC_FW_LOG_ID_WATCHDOG,
2131 ICE_AQC_FW_LOG_ID_TASK_DISPATCH,
2132 ICE_AQC_FW_LOG_ID_MNG,
2133 ICE_AQC_FW_LOG_ID_MAX,
2136 /* This is the buffer for both of the logging commands.
2137 * The entry array size depends on the datalen parameter in the descriptor.
2138 * There will be a total of datalen / 2 entries.
2140 struct ice_aqc_fw_logging_data {
2142 #define ICE_AQC_FW_LOG_ID_S 0
2143 #define ICE_AQC_FW_LOG_ID_M (0xFFF << ICE_AQC_FW_LOG_ID_S)
2145 #define ICE_AQC_FW_LOG_CONF_SUCCESS 0 /* Used by response */
2146 #define ICE_AQC_FW_LOG_CONF_BAD_INDX BIT(12) /* Used by response */
2148 #define ICE_AQC_FW_LOG_EN_S 12
2149 #define ICE_AQC_FW_LOG_EN_M (0xF << ICE_AQC_FW_LOG_EN_S)
2150 #define ICE_AQC_FW_LOG_INFO_EN BIT(12) /* Used by command */
2151 #define ICE_AQC_FW_LOG_INIT_EN BIT(13) /* Used by command */
2152 #define ICE_AQC_FW_LOG_FLOW_EN BIT(14) /* Used by command */
2153 #define ICE_AQC_FW_LOG_ERR_EN BIT(15) /* Used by command */
2157 /* Get/Clear FW Log (indirect 0xFF11) */
2158 struct ice_aqc_get_clear_fw_log {
2160 #define ICE_AQC_FW_LOG_CLEAR BIT(0)
2161 #define ICE_AQC_FW_LOG_MORE_DATA_AVAIL BIT(1)
2169 * struct ice_aq_desc - Admin Queue (AQ) descriptor
2170 * @flags: ICE_AQ_FLAG_* flags
2171 * @opcode: AQ command opcode
2172 * @datalen: length in bytes of indirect/external data buffer
2173 * @retval: return value from firmware
2174 * @cookie_h: opaque data high-half
2175 * @cookie_l: opaque data low-half
2176 * @params: command-specific parameters
2178 * Descriptor format for commands the driver posts on the Admin Transmit Queue
2179 * (ATQ). The firmware writes back onto the command descriptor and returns
2180 * the result of the command. Asynchronous events that are not an immediate
2181 * result of the command are written to the Admin Receive Queue (ARQ) using
2182 * the same descriptor format. Descriptors are in little-endian notation with
2185 struct ice_aq_desc {
2194 struct ice_aqc_generic generic;
2195 struct ice_aqc_get_ver get_ver;
2196 struct ice_aqc_driver_ver driver_ver;
2197 struct ice_aqc_q_shutdown q_shutdown;
2198 struct ice_aqc_req_res res_owner;
2199 struct ice_aqc_manage_mac_read mac_read;
2200 struct ice_aqc_manage_mac_write mac_write;
2201 struct ice_aqc_clear_pxe clear_pxe;
2202 struct ice_aqc_config_no_drop_policy no_drop;
2203 struct ice_aqc_add_update_mir_rule add_update_rule;
2204 struct ice_aqc_delete_mir_rule del_rule;
2205 struct ice_aqc_list_caps get_cap;
2206 struct ice_aqc_get_phy_caps get_phy;
2207 struct ice_aqc_set_phy_cfg set_phy;
2208 struct ice_aqc_restart_an restart_an;
2209 struct ice_aqc_set_port_id_led set_port_id_led;
2210 struct ice_aqc_get_sw_cfg get_sw_conf;
2211 struct ice_aqc_sw_rules sw_rules;
2212 struct ice_aqc_storm_cfg storm_conf;
2213 struct ice_aqc_get_topo get_topo;
2214 struct ice_aqc_sched_elem_cmd sched_elem_cmd;
2215 struct ice_aqc_query_txsched_res query_sched_res;
2216 struct ice_aqc_query_node_to_root query_node_to_root;
2217 struct ice_aqc_cfg_l2_node_cgd cfg_l2_node_cgd;
2218 struct ice_aqc_query_port_ets port_ets;
2219 struct ice_aqc_rl_profile rl_profile;
2220 struct ice_aqc_nvm nvm;
2221 struct ice_aqc_nvm_cfg nvm_cfg;
2222 struct ice_aqc_nvm_checksum nvm_checksum;
2223 struct ice_aqc_pfc_ignore pfc_ignore;
2224 struct ice_aqc_set_query_pfc_mode set_query_pfc_mode;
2225 struct ice_aqc_set_dcb_params set_dcb_params;
2226 struct ice_aqc_lldp_get_mib lldp_get_mib;
2227 struct ice_aqc_lldp_set_mib_change lldp_set_event;
2228 struct ice_aqc_lldp_add_delete_tlv lldp_add_delete_tlv;
2229 struct ice_aqc_lldp_update_tlv lldp_update_tlv;
2230 struct ice_aqc_lldp_stop lldp_stop;
2231 struct ice_aqc_lldp_start lldp_start;
2232 struct ice_aqc_lldp_set_local_mib lldp_set_mib;
2233 struct ice_aqc_lldp_stop_start_specific_agent lldp_agent_ctrl;
2234 struct ice_aqc_get_set_rss_lut get_set_rss_lut;
2235 struct ice_aqc_get_set_rss_key get_set_rss_key;
2236 struct ice_aqc_clear_fd_table clear_fd_table;
2237 struct ice_aqc_add_txqs add_txqs;
2238 struct ice_aqc_dis_txqs dis_txqs;
2239 struct ice_aqc_txqs_cleanup txqs_cleanup;
2240 struct ice_aqc_add_get_update_free_vsi vsi_cmd;
2241 struct ice_aqc_add_update_free_vsi_resp add_update_free_vsi_res;
2242 struct ice_aqc_get_vsi_resp get_vsi_resp;
2243 struct ice_aqc_download_pkg download_pkg;
2244 struct ice_aqc_get_pkg_info_list get_pkg_info_list;
2245 struct ice_aqc_fw_logging fw_logging;
2246 struct ice_aqc_get_clear_fw_log get_clear_fw_log;
2247 struct ice_aqc_set_mac_lb set_mac_lb;
2248 struct ice_aqc_alloc_free_res_cmd sw_res_ctrl;
2249 struct ice_aqc_get_res_alloc get_res;
2250 struct ice_aqc_get_allocd_res_desc get_res_desc;
2251 struct ice_aqc_set_mac_cfg set_mac_cfg;
2252 struct ice_aqc_set_event_mask set_event_mask;
2253 struct ice_aqc_get_link_status get_link_status;
2258 /* FW defined boundary for a large buffer, 4k >= Large buffer > 512 bytes */
2259 #define ICE_AQ_LG_BUF 512
2261 /* Flags sub-structure
2262 * |0 |1 |2 |3 |4 |5 |6 |7 |8 |9 |10 |11 |12 |13 |14 |15 |
2263 * |DD |CMP|ERR|VFE| * * RESERVED * * |LB |RD |VFC|BUF|SI |EI |FE |
2266 /* command flags and offsets */
2267 #define ICE_AQ_FLAG_DD_S 0
2268 #define ICE_AQ_FLAG_CMP_S 1
2269 #define ICE_AQ_FLAG_ERR_S 2
2270 #define ICE_AQ_FLAG_VFE_S 3
2271 #define ICE_AQ_FLAG_LB_S 9
2272 #define ICE_AQ_FLAG_RD_S 10
2273 #define ICE_AQ_FLAG_VFC_S 11
2274 #define ICE_AQ_FLAG_BUF_S 12
2275 #define ICE_AQ_FLAG_SI_S 13
2276 #define ICE_AQ_FLAG_EI_S 14
2277 #define ICE_AQ_FLAG_FE_S 15
2279 #define ICE_AQ_FLAG_DD BIT(ICE_AQ_FLAG_DD_S) /* 0x1 */
2280 #define ICE_AQ_FLAG_CMP BIT(ICE_AQ_FLAG_CMP_S) /* 0x2 */
2281 #define ICE_AQ_FLAG_ERR BIT(ICE_AQ_FLAG_ERR_S) /* 0x4 */
2282 #define ICE_AQ_FLAG_VFE BIT(ICE_AQ_FLAG_VFE_S) /* 0x8 */
2283 #define ICE_AQ_FLAG_LB BIT(ICE_AQ_FLAG_LB_S) /* 0x200 */
2284 #define ICE_AQ_FLAG_RD BIT(ICE_AQ_FLAG_RD_S) /* 0x400 */
2285 #define ICE_AQ_FLAG_VFC BIT(ICE_AQ_FLAG_VFC_S) /* 0x800 */
2286 #define ICE_AQ_FLAG_BUF BIT(ICE_AQ_FLAG_BUF_S) /* 0x1000 */
2287 #define ICE_AQ_FLAG_SI BIT(ICE_AQ_FLAG_SI_S) /* 0x2000 */
2288 #define ICE_AQ_FLAG_EI BIT(ICE_AQ_FLAG_EI_S) /* 0x4000 */
2289 #define ICE_AQ_FLAG_FE BIT(ICE_AQ_FLAG_FE_S) /* 0x8000 */
2293 ICE_AQ_RC_OK = 0, /* Success */
2294 ICE_AQ_RC_EPERM = 1, /* Operation not permitted */
2295 ICE_AQ_RC_ENOENT = 2, /* No such element */
2296 ICE_AQ_RC_ESRCH = 3, /* Bad opcode */
2297 ICE_AQ_RC_EINTR = 4, /* Operation interrupted */
2298 ICE_AQ_RC_EIO = 5, /* I/O error */
2299 ICE_AQ_RC_ENXIO = 6, /* No such resource */
2300 ICE_AQ_RC_E2BIG = 7, /* Arg too long */
2301 ICE_AQ_RC_EAGAIN = 8, /* Try again */
2302 ICE_AQ_RC_ENOMEM = 9, /* Out of memory */
2303 ICE_AQ_RC_EACCES = 10, /* Permission denied */
2304 ICE_AQ_RC_EFAULT = 11, /* Bad address */
2305 ICE_AQ_RC_EBUSY = 12, /* Device or resource busy */
2306 ICE_AQ_RC_EEXIST = 13, /* Object already exists */
2307 ICE_AQ_RC_EINVAL = 14, /* Invalid argument */
2308 ICE_AQ_RC_ENOTTY = 15, /* Not a typewriter */
2309 ICE_AQ_RC_ENOSPC = 16, /* No space left or allocation failure */
2310 ICE_AQ_RC_ENOSYS = 17, /* Function not implemented */
2311 ICE_AQ_RC_ERANGE = 18, /* Parameter out of range */
2312 ICE_AQ_RC_EFLUSHED = 19, /* Cmd flushed due to prev cmd error */
2313 ICE_AQ_RC_BAD_ADDR = 20, /* Descriptor contains a bad pointer */
2314 ICE_AQ_RC_EMODE = 21, /* Op not allowed in current dev mode */
2315 ICE_AQ_RC_EFBIG = 22, /* File too big */
2316 ICE_AQ_RC_ESBCOMP = 23, /* SB-IOSF completion unsuccessful */
2317 ICE_AQ_RC_ENOSEC = 24, /* Missing security manifest */
2318 ICE_AQ_RC_EBADSIG = 25, /* Bad RSA signature */
2319 ICE_AQ_RC_ESVN = 26, /* SVN number prohibits this package */
2320 ICE_AQ_RC_EBADMAN = 27, /* Manifest hash mismatch */
2321 ICE_AQ_RC_EBADBUF = 28, /* Buffer hash mismatches manifest */
2324 /* Admin Queue command opcodes */
2325 enum ice_adminq_opc {
2327 ice_aqc_opc_get_ver = 0x0001,
2328 ice_aqc_opc_driver_ver = 0x0002,
2329 ice_aqc_opc_q_shutdown = 0x0003,
2330 ice_aqc_opc_get_exp_err = 0x0005,
2332 /* resource ownership */
2333 ice_aqc_opc_req_res = 0x0008,
2334 ice_aqc_opc_release_res = 0x0009,
2336 /* device/function capabilities */
2337 ice_aqc_opc_list_func_caps = 0x000A,
2338 ice_aqc_opc_list_dev_caps = 0x000B,
2340 /* manage MAC address */
2341 ice_aqc_opc_manage_mac_read = 0x0107,
2342 ice_aqc_opc_manage_mac_write = 0x0108,
2345 ice_aqc_opc_clear_pxe_mode = 0x0110,
2347 ice_aqc_opc_config_no_drop_policy = 0x0112,
2349 /* internal switch commands */
2350 ice_aqc_opc_get_sw_cfg = 0x0200,
2352 /* Alloc/Free/Get Resources */
2353 ice_aqc_opc_get_res_alloc = 0x0204,
2354 ice_aqc_opc_alloc_res = 0x0208,
2355 ice_aqc_opc_free_res = 0x0209,
2356 ice_aqc_opc_get_allocd_res_desc = 0x020A,
2359 ice_aqc_opc_add_vsi = 0x0210,
2360 ice_aqc_opc_update_vsi = 0x0211,
2361 ice_aqc_opc_get_vsi_params = 0x0212,
2362 ice_aqc_opc_free_vsi = 0x0213,
2364 /* Mirroring rules - add/update, delete */
2365 ice_aqc_opc_add_update_mir_rule = 0x0260,
2366 ice_aqc_opc_del_mir_rule = 0x0261,
2368 /* storm configuration */
2369 ice_aqc_opc_set_storm_cfg = 0x0280,
2370 ice_aqc_opc_get_storm_cfg = 0x0281,
2373 /* switch rules population commands */
2374 ice_aqc_opc_add_sw_rules = 0x02A0,
2375 ice_aqc_opc_update_sw_rules = 0x02A1,
2376 ice_aqc_opc_remove_sw_rules = 0x02A2,
2377 ice_aqc_opc_get_sw_rules = 0x02A3,
2378 ice_aqc_opc_clear_pf_cfg = 0x02A4,
2381 ice_aqc_opc_pfc_ignore = 0x0301,
2382 ice_aqc_opc_query_pfc_mode = 0x0302,
2383 ice_aqc_opc_set_pfc_mode = 0x0303,
2384 ice_aqc_opc_set_dcb_params = 0x0306,
2386 /* transmit scheduler commands */
2387 ice_aqc_opc_get_dflt_topo = 0x0400,
2388 ice_aqc_opc_add_sched_elems = 0x0401,
2389 ice_aqc_opc_cfg_sched_elems = 0x0403,
2390 ice_aqc_opc_get_sched_elems = 0x0404,
2391 ice_aqc_opc_move_sched_elems = 0x0408,
2392 ice_aqc_opc_suspend_sched_elems = 0x0409,
2393 ice_aqc_opc_resume_sched_elems = 0x040A,
2394 ice_aqc_opc_query_port_ets = 0x040E,
2395 ice_aqc_opc_delete_sched_elems = 0x040F,
2396 ice_aqc_opc_add_rl_profiles = 0x0410,
2397 ice_aqc_opc_query_rl_profiles = 0x0411,
2398 ice_aqc_opc_query_sched_res = 0x0412,
2399 ice_aqc_opc_query_node_to_root = 0x0413,
2400 ice_aqc_opc_cfg_l2_node_cgd = 0x0414,
2401 ice_aqc_opc_remove_rl_profiles = 0x0415,
2404 ice_aqc_opc_get_phy_caps = 0x0600,
2405 ice_aqc_opc_set_phy_cfg = 0x0601,
2406 ice_aqc_opc_set_mac_cfg = 0x0603,
2407 ice_aqc_opc_restart_an = 0x0605,
2408 ice_aqc_opc_get_link_status = 0x0607,
2409 ice_aqc_opc_set_event_mask = 0x0613,
2410 ice_aqc_opc_set_mac_lb = 0x0620,
2411 ice_aqc_opc_set_port_id_led = 0x06E9,
2412 ice_aqc_opc_get_port_options = 0x06EA,
2413 ice_aqc_opc_set_port_option = 0x06EB,
2414 ice_aqc_opc_set_gpio = 0x06EC,
2415 ice_aqc_opc_get_gpio = 0x06ED,
2418 ice_aqc_opc_nvm_read = 0x0701,
2419 ice_aqc_opc_nvm_erase = 0x0702,
2420 ice_aqc_opc_nvm_update = 0x0703,
2421 ice_aqc_opc_nvm_cfg_read = 0x0704,
2422 ice_aqc_opc_nvm_cfg_write = 0x0705,
2423 ice_aqc_opc_nvm_checksum = 0x0706,
2426 ice_aqc_opc_lldp_get_mib = 0x0A00,
2427 ice_aqc_opc_lldp_set_mib_change = 0x0A01,
2428 ice_aqc_opc_lldp_add_tlv = 0x0A02,
2429 ice_aqc_opc_lldp_update_tlv = 0x0A03,
2430 ice_aqc_opc_lldp_delete_tlv = 0x0A04,
2431 ice_aqc_opc_lldp_stop = 0x0A05,
2432 ice_aqc_opc_lldp_start = 0x0A06,
2433 ice_aqc_opc_get_cee_dcb_cfg = 0x0A07,
2434 ice_aqc_opc_lldp_set_local_mib = 0x0A08,
2435 ice_aqc_opc_lldp_stop_start_specific_agent = 0x0A09,
2438 ice_aqc_opc_set_rss_key = 0x0B02,
2439 ice_aqc_opc_set_rss_lut = 0x0B03,
2440 ice_aqc_opc_get_rss_key = 0x0B04,
2441 ice_aqc_opc_get_rss_lut = 0x0B05,
2442 ice_aqc_opc_clear_fd_table = 0x0B06,
2444 /* Tx queue handling commands/events */
2445 ice_aqc_opc_add_txqs = 0x0C30,
2446 ice_aqc_opc_dis_txqs = 0x0C31,
2447 ice_aqc_opc_txqs_cleanup = 0x0C31,
2448 ice_aqc_opc_move_recfg_txqs = 0x0C32,
2450 /* package commands */
2451 ice_aqc_opc_download_pkg = 0x0C40,
2452 ice_aqc_opc_upload_section = 0x0C41,
2453 ice_aqc_opc_update_pkg = 0x0C42,
2454 ice_aqc_opc_get_pkg_info_list = 0x0C43,
2458 /* Standalone Commands/Events */
2459 ice_aqc_opc_event_lan_overflow = 0x1001,
2461 /* debug commands */
2462 ice_aqc_opc_fw_logging = 0xFF09,
2463 ice_aqc_opc_fw_logging_info = 0xFF10,
2464 ice_aqc_opc_get_clear_fw_log = 0xFF11
2467 #endif /* _ICE_ADMINQ_CMD_H_ */