1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2001-2020 Intel Corporation
5 #ifndef _ICE_ADMINQ_CMD_H_
6 #define _ICE_ADMINQ_CMD_H_
8 /* This header file defines the Admin Queue commands, error codes and
9 * descriptor format. It is shared between Firmware and Software.
12 #define ICE_MAX_VSI 768
13 #define ICE_AQC_TOPO_MAX_LEVEL_NUM 0x9
14 #define ICE_AQ_SET_MAC_FRAME_SIZE_MAX 9728
16 struct ice_aqc_generic {
23 /* Get version (direct 0x0001) */
24 struct ice_aqc_get_ver {
37 /* Send driver version (indirect 0x0002) */
38 struct ice_aqc_driver_ver {
48 /* Queue Shutdown (direct 0x0003) */
49 struct ice_aqc_q_shutdown {
51 #define ICE_AQC_DRIVER_UNLOADING BIT(0)
55 /* Request resource ownership (direct 0x0008)
56 * Release resource ownership (direct 0x0009)
58 struct ice_aqc_req_res {
60 #define ICE_AQC_RES_ID_NVM 1
61 #define ICE_AQC_RES_ID_SDP 2
62 #define ICE_AQC_RES_ID_CHNG_LOCK 3
63 #define ICE_AQC_RES_ID_GLBL_LOCK 4
65 #define ICE_AQC_RES_ACCESS_READ 1
66 #define ICE_AQC_RES_ACCESS_WRITE 2
68 /* Upon successful completion, FW writes this value and driver is
69 * expected to release resource before timeout. This value is provided
73 #define ICE_AQ_RES_NVM_READ_DFLT_TIMEOUT_MS 3000
74 #define ICE_AQ_RES_NVM_WRITE_DFLT_TIMEOUT_MS 180000
75 #define ICE_AQ_RES_CHNG_LOCK_DFLT_TIMEOUT_MS 1000
76 #define ICE_AQ_RES_GLBL_LOCK_DFLT_TIMEOUT_MS 3000
77 /* For SDP: pin ID of the SDP */
79 /* Status is only used for ICE_AQC_RES_ID_GLBL_LOCK */
81 #define ICE_AQ_RES_GLBL_SUCCESS 0
82 #define ICE_AQ_RES_GLBL_IN_PROG 1
83 #define ICE_AQ_RES_GLBL_DONE 2
87 /* Get function capabilities (indirect 0x000A)
88 * Get device capabilities (indirect 0x000B)
90 struct ice_aqc_list_caps {
99 /* Device/Function buffer entry, repeated per reported capability */
100 struct ice_aqc_list_caps_elem {
102 #define ICE_AQC_CAPS_VALID_FUNCTIONS 0x0005
103 #define ICE_AQC_MAX_VALID_FUNCTIONS 0x8
104 #define ICE_AQC_CAPS_VSI 0x0017
105 #define ICE_AQC_CAPS_DCB 0x0018
106 #define ICE_AQC_CAPS_RSS 0x0040
107 #define ICE_AQC_CAPS_RXQS 0x0041
108 #define ICE_AQC_CAPS_TXQS 0x0042
109 #define ICE_AQC_CAPS_MSIX 0x0043
110 #define ICE_AQC_CAPS_FD 0x0045
111 #define ICE_AQC_CAPS_MAX_MTU 0x0047
115 /* Number of resources described by this capability */
117 /* Only meaningful for some types of resources */
119 /* Only meaningful for some types of resources */
125 /* Manage MAC address, read command - indirect (0x0107)
126 * This struct is also used for the response
128 struct ice_aqc_manage_mac_read {
129 __le16 flags; /* Zeroed by device driver */
130 #define ICE_AQC_MAN_MAC_LAN_ADDR_VALID BIT(4)
131 #define ICE_AQC_MAN_MAC_SAN_ADDR_VALID BIT(5)
132 #define ICE_AQC_MAN_MAC_PORT_ADDR_VALID BIT(6)
133 #define ICE_AQC_MAN_MAC_WOL_ADDR_VALID BIT(7)
134 #define ICE_AQC_MAN_MAC_MC_MAG_EN BIT(8)
135 #define ICE_AQC_MAN_MAC_WOL_PRESERVE_ON_PFR BIT(9)
136 #define ICE_AQC_MAN_MAC_READ_S 4
137 #define ICE_AQC_MAN_MAC_READ_M (0xF << ICE_AQC_MAN_MAC_READ_S)
139 u8 num_addr; /* Used in response */
145 /* Response buffer format for manage MAC read command */
146 struct ice_aqc_manage_mac_read_resp {
149 #define ICE_AQC_MAN_MAC_ADDR_TYPE_LAN 0
150 #define ICE_AQC_MAN_MAC_ADDR_TYPE_WOL 1
151 u8 mac_addr[ETH_ALEN];
154 /* Manage MAC address, write command - direct (0x0108) */
155 struct ice_aqc_manage_mac_write {
158 #define ICE_AQC_MAN_MAC_WR_MC_MAG_EN BIT(0)
159 #define ICE_AQC_MAN_MAC_WR_WOL_LAA_PFR_KEEP BIT(1)
160 #define ICE_AQC_MAN_MAC_WR_S 6
161 #define ICE_AQC_MAN_MAC_WR_M MAKEMASK(3, ICE_AQC_MAN_MAC_WR_S)
162 #define ICE_AQC_MAN_MAC_UPDATE_LAA 0
163 #define ICE_AQC_MAN_MAC_UPDATE_LAA_WOL BIT(ICE_AQC_MAN_MAC_WR_S)
164 /* byte stream in network order */
165 u8 mac_addr[ETH_ALEN];
170 /* Clear PXE Command and response (direct 0x0110) */
171 struct ice_aqc_clear_pxe {
173 #define ICE_AQC_CLEAR_PXE_RX_CNT 0x2
177 /* Configure No-Drop Policy Command (direct 0x0112) */
178 struct ice_aqc_config_no_drop_policy {
180 #define ICE_AQC_FORCE_NO_DROP BIT(0)
184 /* Get switch configuration (0x0200) */
185 struct ice_aqc_get_sw_cfg {
186 /* Reserved for command and copy of request flags for response */
188 /* First desc in case of command and next_elem in case of response
189 * In case of response, if it is not zero, means all the configuration
190 * was not returned and new command shall be sent with this value in
191 * the 'first desc' field
194 /* Reserved for command, only used for response */
201 /* Each entry in the response buffer is of the following type: */
202 struct ice_aqc_get_sw_cfg_resp_elem {
203 /* VSI/Port Number */
205 #define ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_S 0
206 #define ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_M \
207 (0x3FF << ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_S)
208 #define ICE_AQC_GET_SW_CONF_RESP_TYPE_S 14
209 #define ICE_AQC_GET_SW_CONF_RESP_TYPE_M (0x3 << ICE_AQC_GET_SW_CONF_RESP_TYPE_S)
210 #define ICE_AQC_GET_SW_CONF_RESP_PHYS_PORT 0
211 #define ICE_AQC_GET_SW_CONF_RESP_VIRT_PORT 1
212 #define ICE_AQC_GET_SW_CONF_RESP_VSI 2
214 /* SWID VSI/Port belongs to */
217 /* Bit 14..0 : PF/VF number VSI belongs to
218 * Bit 15 : VF indication bit
221 #define ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_S 0
222 #define ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_M \
223 (0x7FFF << ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_S)
224 #define ICE_AQC_GET_SW_CONF_RESP_IS_VF BIT(15)
227 /* The response buffer is as follows. Note that the length of the
228 * elements array varies with the length of the command response.
230 struct ice_aqc_get_sw_cfg_resp {
231 struct ice_aqc_get_sw_cfg_resp_elem elements[1];
234 /* These resource type defines are used for all switch resource
235 * commands where a resource type is required, such as:
236 * Get Resource Allocation command (indirect 0x0204)
237 * Allocate Resources command (indirect 0x0208)
238 * Free Resources command (indirect 0x0209)
239 * Get Allocated Resource Descriptors Command (indirect 0x020A)
241 #define ICE_AQC_RES_TYPE_VEB_COUNTER 0x00
242 #define ICE_AQC_RES_TYPE_VLAN_COUNTER 0x01
243 #define ICE_AQC_RES_TYPE_MIRROR_RULE 0x02
244 #define ICE_AQC_RES_TYPE_VSI_LIST_REP 0x03
245 #define ICE_AQC_RES_TYPE_VSI_LIST_PRUNE 0x04
246 #define ICE_AQC_RES_TYPE_RECIPE 0x05
247 #define ICE_AQC_RES_TYPE_PROFILE 0x06
248 #define ICE_AQC_RES_TYPE_SWID 0x07
249 #define ICE_AQC_RES_TYPE_VSI 0x08
250 #define ICE_AQC_RES_TYPE_FLU 0x09
251 #define ICE_AQC_RES_TYPE_WIDE_TABLE_1 0x0A
252 #define ICE_AQC_RES_TYPE_WIDE_TABLE_2 0x0B
253 #define ICE_AQC_RES_TYPE_WIDE_TABLE_4 0x0C
254 #define ICE_AQC_RES_TYPE_GLOBAL_RSS_HASH 0x20
255 #define ICE_AQC_RES_TYPE_FDIR_COUNTER_BLOCK 0x21
256 #define ICE_AQC_RES_TYPE_FDIR_GUARANTEED_ENTRIES 0x22
257 #define ICE_AQC_RES_TYPE_FDIR_SHARED_ENTRIES 0x23
258 #define ICE_AQC_RES_TYPE_FLEX_DESC_PROG 0x30
259 #define ICE_AQC_RES_TYPE_SWITCH_PROF_BLDR_PROFID 0x48
260 #define ICE_AQC_RES_TYPE_SWITCH_PROF_BLDR_TCAM 0x49
261 #define ICE_AQC_RES_TYPE_ACL_PROF_BLDR_PROFID 0x50
262 #define ICE_AQC_RES_TYPE_ACL_PROF_BLDR_TCAM 0x51
263 #define ICE_AQC_RES_TYPE_FD_PROF_BLDR_PROFID 0x58
264 #define ICE_AQC_RES_TYPE_FD_PROF_BLDR_TCAM 0x59
265 #define ICE_AQC_RES_TYPE_HASH_PROF_BLDR_PROFID 0x60
266 #define ICE_AQC_RES_TYPE_HASH_PROF_BLDR_TCAM 0x61
267 /* Resource types 0x62-67 are reserved for Hash profile builder */
268 #define ICE_AQC_RES_TYPE_QHASH_PROF_BLDR_PROFID 0x68
269 #define ICE_AQC_RES_TYPE_QHASH_PROF_BLDR_TCAM 0x69
271 #define ICE_AQC_RES_TYPE_FLAG_SHARED BIT(7)
272 #define ICE_AQC_RES_TYPE_FLAG_SCAN_BOTTOM BIT(12)
273 #define ICE_AQC_RES_TYPE_FLAG_IGNORE_INDEX BIT(13)
275 #define ICE_AQC_RES_TYPE_FLAG_DEDICATED 0x00
277 #define ICE_AQC_RES_TYPE_S 0
278 #define ICE_AQC_RES_TYPE_M (0x07F << ICE_AQC_RES_TYPE_S)
280 /* Get Resource Allocation command (indirect 0x0204) */
281 struct ice_aqc_get_res_alloc {
282 __le16 resp_elem_num; /* Used in response, reserved in command */
288 /* Get Resource Allocation Response Buffer per response */
289 struct ice_aqc_get_res_resp_elem {
290 __le16 res_type; /* Types defined above cmd 0x0204 */
291 __le16 total_capacity; /* Resources available to all PF's */
292 __le16 total_function; /* Resources allocated for a PF */
293 __le16 total_shared; /* Resources allocated as shared */
294 __le16 total_free; /* Resources un-allocated/not reserved by any PF */
297 /* Buffer for Get Resource command */
298 struct ice_aqc_get_res_resp {
299 /* Number of resource entries to be calculated using
300 * datalen/sizeof(struct ice_aqc_cmd_resp)).
301 * Value of 'datalen' gets updated as part of response.
303 struct ice_aqc_get_res_resp_elem elem[1];
306 /* Allocate Resources command (indirect 0x0208)
307 * Free Resources command (indirect 0x0209)
309 struct ice_aqc_alloc_free_res_cmd {
310 __le16 num_entries; /* Number of Resource entries */
316 /* Resource descriptor */
317 struct ice_aqc_res_elem {
324 /* Buffer for Allocate/Free Resources commands */
325 struct ice_aqc_alloc_free_res_elem {
326 __le16 res_type; /* Types defined above cmd 0x0204 */
327 #define ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_S 8
328 #define ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_M \
329 (0xF << ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_S)
331 struct ice_aqc_res_elem elem[1];
334 /* Get Allocated Resource Descriptors Command (indirect 0x020A) */
335 struct ice_aqc_get_allocd_res_desc {
338 __le16 res; /* Types defined above cmd 0x0204 */
353 struct ice_aqc_get_allocd_res_desc_resp {
354 struct ice_aqc_res_elem elem[1];
357 /* Add VSI (indirect 0x0210)
358 * Update VSI (indirect 0x0211)
359 * Get VSI (indirect 0x0212)
360 * Free VSI (indirect 0x0213)
362 struct ice_aqc_add_get_update_free_vsi {
364 #define ICE_AQ_VSI_NUM_S 0
365 #define ICE_AQ_VSI_NUM_M (0x03FF << ICE_AQ_VSI_NUM_S)
366 #define ICE_AQ_VSI_IS_VALID BIT(15)
368 #define ICE_AQ_VSI_KEEP_ALLOC 0x1
372 #define ICE_AQ_VSI_TYPE_S 0
373 #define ICE_AQ_VSI_TYPE_M (0x3 << ICE_AQ_VSI_TYPE_S)
374 #define ICE_AQ_VSI_TYPE_VF 0x0
375 #define ICE_AQ_VSI_TYPE_VMDQ2 0x1
376 #define ICE_AQ_VSI_TYPE_PF 0x2
377 #define ICE_AQ_VSI_TYPE_EMP_MNG 0x3
382 /* Response descriptor for:
383 * Add VSI (indirect 0x0210)
384 * Update VSI (indirect 0x0211)
385 * Free VSI (indirect 0x0213)
387 struct ice_aqc_add_update_free_vsi_resp {
396 struct ice_aqc_get_vsi_resp {
399 /* The vsi_flags field uses the ICE_AQ_VSI_TYPE_* defines for values.
400 * These are found above in struct ice_aqc_add_get_update_free_vsi.
409 struct ice_aqc_vsi_props {
410 __le16 valid_sections;
411 #define ICE_AQ_VSI_PROP_SW_VALID BIT(0)
412 #define ICE_AQ_VSI_PROP_SECURITY_VALID BIT(1)
413 #define ICE_AQ_VSI_PROP_VLAN_VALID BIT(2)
414 #define ICE_AQ_VSI_PROP_OUTER_TAG_VALID BIT(3)
415 #define ICE_AQ_VSI_PROP_INGRESS_UP_VALID BIT(4)
416 #define ICE_AQ_VSI_PROP_EGRESS_UP_VALID BIT(5)
417 #define ICE_AQ_VSI_PROP_RXQ_MAP_VALID BIT(6)
418 #define ICE_AQ_VSI_PROP_Q_OPT_VALID BIT(7)
419 #define ICE_AQ_VSI_PROP_OUTER_UP_VALID BIT(8)
420 #define ICE_AQ_VSI_PROP_ACL_VALID BIT(10)
421 #define ICE_AQ_VSI_PROP_FLOW_DIR_VALID BIT(11)
422 #define ICE_AQ_VSI_PROP_PASID_VALID BIT(12)
426 #define ICE_AQ_VSI_SW_FLAG_ALLOW_LB BIT(5)
427 #define ICE_AQ_VSI_SW_FLAG_LOCAL_LB BIT(6)
428 #define ICE_AQ_VSI_SW_FLAG_SRC_PRUNE BIT(7)
430 #define ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_S 0
431 #define ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_M \
432 (0xF << ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_S)
433 #define ICE_AQ_VSI_SW_FLAG_RX_VLAN_PRUNE_ENA BIT(0)
434 #define ICE_AQ_VSI_SW_FLAG_LAN_ENA BIT(4)
436 #define ICE_AQ_VSI_SW_VEB_STAT_ID_S 0
437 #define ICE_AQ_VSI_SW_VEB_STAT_ID_M (0x1F << ICE_AQ_VSI_SW_VEB_STAT_ID_S)
438 #define ICE_AQ_VSI_SW_VEB_STAT_ID_VALID BIT(5)
439 /* security section */
441 #define ICE_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD BIT(0)
442 #define ICE_AQ_VSI_SEC_FLAG_ENA_MAC_ANTI_SPOOF BIT(2)
443 #define ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S 4
444 #define ICE_AQ_VSI_SEC_TX_PRUNE_ENA_M (0xF << ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S)
445 #define ICE_AQ_VSI_SEC_TX_VLAN_PRUNE_ENA BIT(0)
448 __le16 pvid; /* VLANS include priority bits */
449 u8 pvlan_reserved[2];
451 #define ICE_AQ_VSI_VLAN_MODE_S 0
452 #define ICE_AQ_VSI_VLAN_MODE_M (0x3 << ICE_AQ_VSI_VLAN_MODE_S)
453 #define ICE_AQ_VSI_VLAN_MODE_UNTAGGED 0x1
454 #define ICE_AQ_VSI_VLAN_MODE_TAGGED 0x2
455 #define ICE_AQ_VSI_VLAN_MODE_ALL 0x3
456 #define ICE_AQ_VSI_PVLAN_INSERT_PVID BIT(2)
457 #define ICE_AQ_VSI_VLAN_EMOD_S 3
458 #define ICE_AQ_VSI_VLAN_EMOD_M (0x3 << ICE_AQ_VSI_VLAN_EMOD_S)
459 #define ICE_AQ_VSI_VLAN_EMOD_STR_BOTH (0x0 << ICE_AQ_VSI_VLAN_EMOD_S)
460 #define ICE_AQ_VSI_VLAN_EMOD_STR_UP (0x1 << ICE_AQ_VSI_VLAN_EMOD_S)
461 #define ICE_AQ_VSI_VLAN_EMOD_STR (0x2 << ICE_AQ_VSI_VLAN_EMOD_S)
462 #define ICE_AQ_VSI_VLAN_EMOD_NOTHING (0x3 << ICE_AQ_VSI_VLAN_EMOD_S)
463 u8 pvlan_reserved2[3];
464 /* ingress egress up sections */
465 __le32 ingress_table; /* bitmap, 3 bits per up */
466 #define ICE_AQ_VSI_UP_TABLE_UP0_S 0
467 #define ICE_AQ_VSI_UP_TABLE_UP0_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP0_S)
468 #define ICE_AQ_VSI_UP_TABLE_UP1_S 3
469 #define ICE_AQ_VSI_UP_TABLE_UP1_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP1_S)
470 #define ICE_AQ_VSI_UP_TABLE_UP2_S 6
471 #define ICE_AQ_VSI_UP_TABLE_UP2_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP2_S)
472 #define ICE_AQ_VSI_UP_TABLE_UP3_S 9
473 #define ICE_AQ_VSI_UP_TABLE_UP3_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP3_S)
474 #define ICE_AQ_VSI_UP_TABLE_UP4_S 12
475 #define ICE_AQ_VSI_UP_TABLE_UP4_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP4_S)
476 #define ICE_AQ_VSI_UP_TABLE_UP5_S 15
477 #define ICE_AQ_VSI_UP_TABLE_UP5_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP5_S)
478 #define ICE_AQ_VSI_UP_TABLE_UP6_S 18
479 #define ICE_AQ_VSI_UP_TABLE_UP6_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP6_S)
480 #define ICE_AQ_VSI_UP_TABLE_UP7_S 21
481 #define ICE_AQ_VSI_UP_TABLE_UP7_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP7_S)
482 __le32 egress_table; /* same defines as for ingress table */
483 /* outer tags section */
486 #define ICE_AQ_VSI_OUTER_TAG_MODE_S 0
487 #define ICE_AQ_VSI_OUTER_TAG_MODE_M (0x3 << ICE_AQ_VSI_OUTER_TAG_MODE_S)
488 #define ICE_AQ_VSI_OUTER_TAG_NOTHING 0x0
489 #define ICE_AQ_VSI_OUTER_TAG_REMOVE 0x1
490 #define ICE_AQ_VSI_OUTER_TAG_COPY 0x2
491 #define ICE_AQ_VSI_OUTER_TAG_TYPE_S 2
492 #define ICE_AQ_VSI_OUTER_TAG_TYPE_M (0x3 << ICE_AQ_VSI_OUTER_TAG_TYPE_S)
493 #define ICE_AQ_VSI_OUTER_TAG_NONE 0x0
494 #define ICE_AQ_VSI_OUTER_TAG_STAG 0x1
495 #define ICE_AQ_VSI_OUTER_TAG_VLAN_8100 0x2
496 #define ICE_AQ_VSI_OUTER_TAG_VLAN_9100 0x3
497 #define ICE_AQ_VSI_OUTER_TAG_INSERT BIT(4)
498 #define ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST BIT(6)
499 u8 outer_tag_reserved;
500 /* queue mapping section */
501 __le16 mapping_flags;
502 #define ICE_AQ_VSI_Q_MAP_CONTIG 0x0
503 #define ICE_AQ_VSI_Q_MAP_NONCONTIG BIT(0)
504 __le16 q_mapping[16];
505 #define ICE_AQ_VSI_Q_S 0
506 #define ICE_AQ_VSI_Q_M (0x7FF << ICE_AQ_VSI_Q_S)
507 __le16 tc_mapping[8];
508 #define ICE_AQ_VSI_TC_Q_OFFSET_S 0
509 #define ICE_AQ_VSI_TC_Q_OFFSET_M (0x7FF << ICE_AQ_VSI_TC_Q_OFFSET_S)
510 #define ICE_AQ_VSI_TC_Q_NUM_S 11
511 #define ICE_AQ_VSI_TC_Q_NUM_M (0xF << ICE_AQ_VSI_TC_Q_NUM_S)
512 /* queueing option section */
514 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_S 0
515 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_M (0x3 << ICE_AQ_VSI_Q_OPT_RSS_LUT_S)
516 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_VSI 0x0
517 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_PF 0x2
518 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_GBL 0x3
519 #define ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_S 2
520 #define ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_M (0xF << ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_S)
521 #define ICE_AQ_VSI_Q_OPT_RSS_HASH_S 6
522 #define ICE_AQ_VSI_Q_OPT_RSS_HASH_M (0x3 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S)
523 #define ICE_AQ_VSI_Q_OPT_RSS_TPLZ (0x0 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S)
524 #define ICE_AQ_VSI_Q_OPT_RSS_SYM_TPLZ (0x1 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S)
525 #define ICE_AQ_VSI_Q_OPT_RSS_XOR (0x2 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S)
526 #define ICE_AQ_VSI_Q_OPT_RSS_JHASH (0x3 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S)
528 #define ICE_AQ_VSI_Q_OPT_TC_OVR_S 0
529 #define ICE_AQ_VSI_Q_OPT_TC_OVR_M (0x1F << ICE_AQ_VSI_Q_OPT_TC_OVR_S)
530 #define ICE_AQ_VSI_Q_OPT_PROF_TC_OVR BIT(7)
532 #define ICE_AQ_VSI_Q_OPT_PE_FLTR_EN BIT(0)
533 u8 q_opt_reserved[3];
534 /* outer up section */
535 __le32 outer_up_table; /* same structure and defines as ingress tbl */
538 #define ICE_AQ_VSI_ACL_DEF_RX_PROF_S 0
539 #define ICE_AQ_VSI_ACL_DEF_RX_PROF_M (0xF << ICE_AQ_VSI_ACL_DEF_RX_PROF_S)
540 #define ICE_AQ_VSI_ACL_DEF_RX_TABLE_S 4
541 #define ICE_AQ_VSI_ACL_DEF_RX_TABLE_M (0xF << ICE_AQ_VSI_ACL_DEF_RX_TABLE_S)
542 #define ICE_AQ_VSI_ACL_DEF_TX_PROF_S 8
543 #define ICE_AQ_VSI_ACL_DEF_TX_PROF_M (0xF << ICE_AQ_VSI_ACL_DEF_TX_PROF_S)
544 #define ICE_AQ_VSI_ACL_DEF_TX_TABLE_S 12
545 #define ICE_AQ_VSI_ACL_DEF_TX_TABLE_M (0xF << ICE_AQ_VSI_ACL_DEF_TX_TABLE_S)
546 /* flow director section */
548 #define ICE_AQ_VSI_FD_ENABLE BIT(0)
549 #define ICE_AQ_VSI_FD_TX_AUTO_ENABLE BIT(1)
550 #define ICE_AQ_VSI_FD_PROG_ENABLE BIT(3)
551 __le16 max_fd_fltr_dedicated;
552 __le16 max_fd_fltr_shared;
554 #define ICE_AQ_VSI_FD_DEF_Q_S 0
555 #define ICE_AQ_VSI_FD_DEF_Q_M (0x7FF << ICE_AQ_VSI_FD_DEF_Q_S)
556 #define ICE_AQ_VSI_FD_DEF_GRP_S 12
557 #define ICE_AQ_VSI_FD_DEF_GRP_M (0x7 << ICE_AQ_VSI_FD_DEF_GRP_S)
558 __le16 fd_report_opt;
559 #define ICE_AQ_VSI_FD_REPORT_Q_S 0
560 #define ICE_AQ_VSI_FD_REPORT_Q_M (0x7FF << ICE_AQ_VSI_FD_REPORT_Q_S)
561 #define ICE_AQ_VSI_FD_DEF_PRIORITY_S 12
562 #define ICE_AQ_VSI_FD_DEF_PRIORITY_M (0x7 << ICE_AQ_VSI_FD_DEF_PRIORITY_S)
563 #define ICE_AQ_VSI_FD_DEF_DROP BIT(15)
566 #define ICE_AQ_VSI_PASID_ID_S 0
567 #define ICE_AQ_VSI_PASID_ID_M (0xFFFFF << ICE_AQ_VSI_PASID_ID_S)
568 #define ICE_AQ_VSI_PASID_ID_VALID BIT(31)
572 /* Add/update mirror rule - direct (0x0260) */
573 #define ICE_AQC_RULE_ID_VALID_S 7
574 #define ICE_AQC_RULE_ID_VALID_M (0x1 << ICE_AQC_RULE_ID_VALID_S)
575 #define ICE_AQC_RULE_ID_S 0
576 #define ICE_AQC_RULE_ID_M (0x3F << ICE_AQC_RULE_ID_S)
578 /* Following defines to be used while processing caller specified mirror list
581 /* Action: Byte.bit (1.7)
582 * 0 = Remove VSI from mirror rule
583 * 1 = Add VSI to mirror rule
585 #define ICE_AQC_RULE_ACT_S 15
586 #define ICE_AQC_RULE_ACT_M (0x1 << ICE_AQC_RULE_ACT_S)
587 /* Action: 1.2:0.0 = Mirrored VSI */
588 #define ICE_AQC_RULE_MIRRORED_VSI_S 0
589 #define ICE_AQC_RULE_MIRRORED_VSI_M (0x7FF << ICE_AQC_RULE_MIRRORED_VSI_S)
591 /* This is to be used by add/update mirror rule Admin Queue command.
592 * In case of add mirror rule - if rule ID is specified as
593 * INVAL_MIRROR_RULE_ID, new rule ID is allocated from shared pool.
594 * If specified rule_id is valid, then it is used. If specified rule_id
595 * is in use then new mirroring rule is added.
597 #define ICE_INVAL_MIRROR_RULE_ID 0xFFFF
599 struct ice_aqc_add_update_mir_rule {
603 #define ICE_AQC_RULE_TYPE_S 0
604 #define ICE_AQC_RULE_TYPE_M (0x7 << ICE_AQC_RULE_TYPE_S)
605 /* VPORT ingress/egress */
606 #define ICE_AQC_RULE_TYPE_VPORT_INGRESS 0x1
607 #define ICE_AQC_RULE_TYPE_VPORT_EGRESS 0x2
608 /* Physical port ingress mirroring.
609 * All traffic received by this port
611 #define ICE_AQC_RULE_TYPE_PPORT_INGRESS 0x6
612 /* Physical port egress mirroring. All traffic sent by this port */
613 #define ICE_AQC_RULE_TYPE_PPORT_EGRESS 0x7
615 /* Number of mirrored entries.
616 * The values are in the command buffer
620 /* Destination VSI */
626 /* Delete mirror rule - direct(0x0261) */
627 struct ice_aqc_delete_mir_rule {
631 /* Byte.bit: 20.0 = Keep allocation. If set VSI stays part of
632 * the PF allocated resources, otherwise it is returned to the
635 #define ICE_AQC_FLAG_KEEP_ALLOCD_S 0
636 #define ICE_AQC_FLAG_KEEP_ALLOCD_M (0x1 << ICE_AQC_FLAG_KEEP_ALLOCD_S)
642 /* Set/Get storm config - (direct 0x0280, 0x0281) */
643 /* This structure holds get storm configuration response and same structure
644 * is used to perform set_storm_cfg
646 struct ice_aqc_storm_cfg {
647 __le32 bcast_thresh_size;
648 __le32 mcast_thresh_size;
649 /* Bit 18:0 - Traffic upper threshold size
650 * Bit 31:19 - Reserved
652 #define ICE_AQ_THRESHOLD_S 0
653 #define ICE_AQ_THRESHOLD_M (0x7FFFF << ICE_AQ_THRESHOLD_S)
655 __le32 storm_ctrl_ctrl;
656 /* Bit 0: MDIPW - Drop Multicast packets in previous window
657 * Bit 1: MDICW - Drop multicast packets in current window
658 * Bit 2: BDIPW - Drop broadcast packets in previous window
659 * Bit 3: BDICW - Drop broadcast packets in current window
661 #define ICE_AQ_STORM_CTRL_MDIPW_DROP_MULTICAST BIT(0)
662 #define ICE_AQ_STORM_CTRL_MDICW_DROP_MULTICAST BIT(1)
663 #define ICE_AQ_STORM_CTRL_BDIPW_DROP_MULTICAST BIT(2)
664 #define ICE_AQ_STORM_CTRL_BDICW_DROP_MULTICAST BIT(3)
665 /* Bit 7:5 : Reserved */
666 /* Bit 27:8 : Interval - BSC/MSC Time-interval specification: The
667 * interval size for applying ingress broadcast or multicast storm
670 #define ICE_AQ_STORM_BSC_MSC_TIME_INTERVAL_S 8
671 #define ICE_AQ_STORM_BSC_MSC_TIME_INTERVAL_M \
672 (0xFFFFF << ICE_AQ_STORM_BSC_MSC_TIME_INTERVAL_S)
676 #define ICE_MAX_NUM_RECIPES 64
678 /* Add/Get Recipe (indirect 0x0290/0x0292) */
679 struct ice_aqc_add_get_recipe {
680 __le16 num_sub_recipes; /* Input in Add cmd, Output in Get cmd */
681 __le16 return_index; /* Input, used for Get cmd only */
687 struct ice_aqc_recipe_content {
689 #define ICE_AQ_RECIPE_ID_S 0
690 #define ICE_AQ_RECIPE_ID_M (0x3F << ICE_AQ_RECIPE_ID_S)
691 #define ICE_AQ_RECIPE_ID_IS_ROOT BIT(7)
692 #define ICE_AQ_SW_ID_LKUP_IDX 0
694 #define ICE_AQ_RECIPE_LKUP_DATA_S 0
695 #define ICE_AQ_RECIPE_LKUP_DATA_M (0x3F << ICE_AQ_RECIPE_LKUP_DATA_S)
696 #define ICE_AQ_RECIPE_LKUP_IGNORE BIT(7)
697 #define ICE_AQ_SW_ID_LKUP_MASK 0x00FF
700 #define ICE_AQ_RECIPE_RESULT_DATA_S 0
701 #define ICE_AQ_RECIPE_RESULT_DATA_M (0x3F << ICE_AQ_RECIPE_RESULT_DATA_S)
702 #define ICE_AQ_RECIPE_RESULT_EN BIT(7)
704 u8 act_ctrl_join_priority;
705 u8 act_ctrl_fwd_priority;
706 #define ICE_AQ_RECIPE_FWD_PRIORITY_S 0
707 #define ICE_AQ_RECIPE_FWD_PRIORITY_M (0xF << ICE_AQ_RECIPE_FWD_PRIORITY_S)
709 #define ICE_AQ_RECIPE_ACT_NEED_PASS_L2 BIT(0)
710 #define ICE_AQ_RECIPE_ACT_ALLOW_PASS_L2 BIT(1)
711 #define ICE_AQ_RECIPE_ACT_INV_ACT BIT(2)
712 #define ICE_AQ_RECIPE_ACT_PRUNE_INDX_S 4
713 #define ICE_AQ_RECIPE_ACT_PRUNE_INDX_M (0x3 << ICE_AQ_RECIPE_ACT_PRUNE_INDX_S)
716 #define ICE_AQ_RECIPE_DFLT_ACT_S 0
717 #define ICE_AQ_RECIPE_DFLT_ACT_M (0x7FFFF << ICE_AQ_RECIPE_DFLT_ACT_S)
718 #define ICE_AQ_RECIPE_DFLT_ACT_VALID BIT(31)
721 struct ice_aqc_recipe_data_elem {
724 #define ICE_AQ_RECIPE_WAS_UPDATED BIT(0)
728 struct ice_aqc_recipe_content content;
732 /* This struct contains a number of entries as per the
733 * num_sub_recipes in the command
735 struct ice_aqc_add_get_recipe_data {
736 struct ice_aqc_recipe_data_elem recipe[1];
739 /* Set/Get Recipes to Profile Association (direct 0x0291/0x0293) */
740 struct ice_aqc_recipe_to_profile {
743 ice_declare_bitmap(recipe_assoc, ICE_MAX_NUM_RECIPES);
746 /* Add/Update/Remove/Get switch rules (indirect 0x02A0, 0x02A1, 0x02A2, 0x02A3)
748 struct ice_aqc_sw_rules {
749 /* ops: add switch rules, referring the number of rules.
750 * ops: update switch rules, referring the number of filters
751 * ops: remove switch rules, referring the entry index.
752 * ops: get switch rules, referring to the number of filters.
754 __le16 num_rules_fltr_entry_index;
761 /* Add/Update/Get/Remove lookup Rx/Tx command/response entry
762 * This structures describes the lookup rules and associated actions. "index"
763 * is returned as part of a response to a successful Add command, and can be
764 * used to identify the rule for Update/Get/Remove commands.
766 struct ice_sw_rule_lkup_rx_tx {
768 #define ICE_SW_RECIPE_LOGICAL_PORT_FWD 10
769 /* Source port for LOOKUP_RX and source VSI in case of LOOKUP_TX */
773 /* Bit 0:1 - Action type */
774 #define ICE_SINGLE_ACT_TYPE_S 0x00
775 #define ICE_SINGLE_ACT_TYPE_M (0x3 << ICE_SINGLE_ACT_TYPE_S)
777 /* Bit 2 - Loop back enable
780 #define ICE_SINGLE_ACT_LB_ENABLE BIT(2)
781 #define ICE_SINGLE_ACT_LAN_ENABLE BIT(3)
783 /* Action type = 0 - Forward to VSI or VSI list */
784 #define ICE_SINGLE_ACT_VSI_FORWARDING 0x0
786 #define ICE_SINGLE_ACT_VSI_ID_S 4
787 #define ICE_SINGLE_ACT_VSI_ID_M (0x3FF << ICE_SINGLE_ACT_VSI_ID_S)
788 #define ICE_SINGLE_ACT_VSI_LIST_ID_S 4
789 #define ICE_SINGLE_ACT_VSI_LIST_ID_M (0x3FF << ICE_SINGLE_ACT_VSI_LIST_ID_S)
790 /* This bit needs to be set if action is forward to VSI list */
791 #define ICE_SINGLE_ACT_VSI_LIST BIT(14)
792 #define ICE_SINGLE_ACT_VALID_BIT BIT(17)
793 #define ICE_SINGLE_ACT_DROP BIT(18)
795 /* Action type = 1 - Forward to Queue of Queue group */
796 #define ICE_SINGLE_ACT_TO_Q 0x1
797 #define ICE_SINGLE_ACT_Q_INDEX_S 4
798 #define ICE_SINGLE_ACT_Q_INDEX_M (0x7FF << ICE_SINGLE_ACT_Q_INDEX_S)
799 #define ICE_SINGLE_ACT_Q_REGION_S 15
800 #define ICE_SINGLE_ACT_Q_REGION_M (0x7 << ICE_SINGLE_ACT_Q_REGION_S)
801 #define ICE_SINGLE_ACT_Q_PRIORITY BIT(18)
803 /* Action type = 2 - Prune */
804 #define ICE_SINGLE_ACT_PRUNE 0x2
805 #define ICE_SINGLE_ACT_EGRESS BIT(15)
806 #define ICE_SINGLE_ACT_INGRESS BIT(16)
807 #define ICE_SINGLE_ACT_PRUNET BIT(17)
808 /* Bit 18 should be set to 0 for this action */
810 /* Action type = 2 - Pointer */
811 #define ICE_SINGLE_ACT_PTR 0x2
812 #define ICE_SINGLE_ACT_PTR_VAL_S 4
813 #define ICE_SINGLE_ACT_PTR_VAL_M (0x1FFF << ICE_SINGLE_ACT_PTR_VAL_S)
814 /* Bit 18 should be set to 1 */
815 #define ICE_SINGLE_ACT_PTR_BIT BIT(18)
817 /* Action type = 3 - Other actions. Last two bits
818 * are other action identifier
820 #define ICE_SINGLE_ACT_OTHER_ACTS 0x3
821 #define ICE_SINGLE_OTHER_ACT_IDENTIFIER_S 17
822 #define ICE_SINGLE_OTHER_ACT_IDENTIFIER_M \
823 (0x3 << ICE_SINGLE_OTHER_ACT_IDENTIFIER_S)
825 /* Bit 17:18 - Defines other actions */
826 /* Other action = 0 - Mirror VSI */
827 #define ICE_SINGLE_OTHER_ACT_MIRROR 0
828 #define ICE_SINGLE_ACT_MIRROR_VSI_ID_S 4
829 #define ICE_SINGLE_ACT_MIRROR_VSI_ID_M \
830 (0x3FF << ICE_SINGLE_ACT_MIRROR_VSI_ID_S)
832 /* Other action = 3 - Set Stat count */
833 #define ICE_SINGLE_OTHER_ACT_STAT_COUNT 3
834 #define ICE_SINGLE_ACT_STAT_COUNT_INDEX_S 4
835 #define ICE_SINGLE_ACT_STAT_COUNT_INDEX_M \
836 (0x7F << ICE_SINGLE_ACT_STAT_COUNT_INDEX_S)
838 __le16 index; /* The index of the rule in the lookup table */
839 /* Length and values of the header to be matched per recipe or
847 /* Add/Update/Remove large action command/response entry
848 * "index" is returned as part of a response to a successful Add command, and
849 * can be used to identify the action for Update/Get/Remove commands.
851 struct ice_sw_rule_lg_act {
852 __le16 index; /* Index in large action table */
854 __le32 act[1]; /* array of size for actions */
855 /* Max number of large actions */
856 #define ICE_MAX_LG_ACT 4
857 /* Bit 0:1 - Action type */
858 #define ICE_LG_ACT_TYPE_S 0
859 #define ICE_LG_ACT_TYPE_M (0x7 << ICE_LG_ACT_TYPE_S)
861 /* Action type = 0 - Forward to VSI or VSI list */
862 #define ICE_LG_ACT_VSI_FORWARDING 0
863 #define ICE_LG_ACT_VSI_ID_S 3
864 #define ICE_LG_ACT_VSI_ID_M (0x3FF << ICE_LG_ACT_VSI_ID_S)
865 #define ICE_LG_ACT_VSI_LIST_ID_S 3
866 #define ICE_LG_ACT_VSI_LIST_ID_M (0x3FF << ICE_LG_ACT_VSI_LIST_ID_S)
867 /* This bit needs to be set if action is forward to VSI list */
868 #define ICE_LG_ACT_VSI_LIST BIT(13)
870 #define ICE_LG_ACT_VALID_BIT BIT(16)
872 /* Action type = 1 - Forward to Queue of Queue group */
873 #define ICE_LG_ACT_TO_Q 0x1
874 #define ICE_LG_ACT_Q_INDEX_S 3
875 #define ICE_LG_ACT_Q_INDEX_M (0x7FF << ICE_LG_ACT_Q_INDEX_S)
876 #define ICE_LG_ACT_Q_REGION_S 14
877 #define ICE_LG_ACT_Q_REGION_M (0x7 << ICE_LG_ACT_Q_REGION_S)
878 #define ICE_LG_ACT_Q_PRIORITY_SET BIT(17)
880 /* Action type = 2 - Prune */
881 #define ICE_LG_ACT_PRUNE 0x2
882 #define ICE_LG_ACT_EGRESS BIT(14)
883 #define ICE_LG_ACT_INGRESS BIT(15)
884 #define ICE_LG_ACT_PRUNET BIT(16)
886 /* Action type = 3 - Mirror VSI */
887 #define ICE_LG_OTHER_ACT_MIRROR 0x3
888 #define ICE_LG_ACT_MIRROR_VSI_ID_S 3
889 #define ICE_LG_ACT_MIRROR_VSI_ID_M (0x3FF << ICE_LG_ACT_MIRROR_VSI_ID_S)
891 /* Action type = 5 - Generic Value */
892 #define ICE_LG_ACT_GENERIC 0x5
893 #define ICE_LG_ACT_GENERIC_VALUE_S 3
894 #define ICE_LG_ACT_GENERIC_VALUE_M (0xFFFF << ICE_LG_ACT_GENERIC_VALUE_S)
895 #define ICE_LG_ACT_GENERIC_OFFSET_S 19
896 #define ICE_LG_ACT_GENERIC_OFFSET_M (0x7 << ICE_LG_ACT_GENERIC_OFFSET_S)
897 #define ICE_LG_ACT_GENERIC_PRIORITY_S 22
898 #define ICE_LG_ACT_GENERIC_PRIORITY_M (0x7 << ICE_LG_ACT_GENERIC_PRIORITY_S)
899 #define ICE_LG_ACT_GENERIC_OFF_RX_DESC_PROF_IDX 7
901 /* Action = 7 - Set Stat count */
902 #define ICE_LG_ACT_STAT_COUNT 0x7
903 #define ICE_LG_ACT_STAT_COUNT_S 3
904 #define ICE_LG_ACT_STAT_COUNT_M (0x7F << ICE_LG_ACT_STAT_COUNT_S)
907 /* Add/Update/Remove VSI list command/response entry
908 * "index" is returned as part of a response to a successful Add command, and
909 * can be used to identify the VSI list for Update/Get/Remove commands.
911 struct ice_sw_rule_vsi_list {
912 __le16 index; /* Index of VSI/Prune list */
914 __le16 vsi[1]; /* Array of number_vsi VSI numbers */
918 /* Query VSI list command/response entry */
919 struct ice_sw_rule_vsi_list_query {
921 ice_declare_bitmap(vsi_list, ICE_MAX_VSI);
926 /* Add switch rule response:
927 * Content of return buffer is same as the input buffer. The status field and
928 * LUT index are updated as part of the response
930 struct ice_aqc_sw_rules_elem {
931 __le16 type; /* Switch rule type, one of T_... */
932 #define ICE_AQC_SW_RULES_T_LKUP_RX 0x0
933 #define ICE_AQC_SW_RULES_T_LKUP_TX 0x1
934 #define ICE_AQC_SW_RULES_T_LG_ACT 0x2
935 #define ICE_AQC_SW_RULES_T_VSI_LIST_SET 0x3
936 #define ICE_AQC_SW_RULES_T_VSI_LIST_CLEAR 0x4
937 #define ICE_AQC_SW_RULES_T_PRUNE_LIST_SET 0x5
938 #define ICE_AQC_SW_RULES_T_PRUNE_LIST_CLEAR 0x6
941 struct ice_sw_rule_lkup_rx_tx lkup_tx_rx;
942 struct ice_sw_rule_lg_act lg_act;
943 struct ice_sw_rule_vsi_list vsi_list;
944 struct ice_sw_rule_vsi_list_query vsi_list_query;
950 /* PFC Ignore (direct 0x0301)
951 * The command and response use the same descriptor structure
953 struct ice_aqc_pfc_ignore {
955 u8 cmd_flags; /* unused in response */
956 #define ICE_AQC_PFC_IGNORE_SET BIT(7)
957 #define ICE_AQC_PFC_IGNORE_CLEAR 0
961 /* Set PFC Mode (direct 0x0303)
962 * Query PFC Mode (direct 0x0302)
964 struct ice_aqc_set_query_pfc_mode {
966 /* For Set Command response, reserved in all other cases */
967 #define ICE_AQC_PFC_NOT_CONFIGURED 0
968 /* For Query Command response, reserved in all other cases */
969 #define ICE_AQC_DCB_DIS 0
970 #define ICE_AQC_PFC_VLAN_BASED_PFC 1
971 #define ICE_AQC_PFC_DSCP_BASED_PFC 2
975 /* Set DCB Parameters (direct 0x0306) */
976 struct ice_aqc_set_dcb_params {
977 u8 cmd_flags; /* unused in response */
978 #define ICE_AQC_LINK_UP_DCB_CFG BIT(0)
979 #define ICE_AQC_PERSIST_DCB_CFG BIT(1)
980 u8 valid_flags; /* unused in response */
981 #define ICE_AQC_LINK_UP_DCB_CFG_VALID BIT(0)
982 #define ICE_AQC_PERSIST_DCB_CFG_VALID BIT(1)
986 /* Get Default Topology (indirect 0x0400) */
987 struct ice_aqc_get_topo {
996 /* Update TSE (indirect 0x0403)
997 * Get TSE (indirect 0x0404)
998 * Add TSE (indirect 0x0401)
999 * Delete TSE (indirect 0x040F)
1000 * Move TSE (indirect 0x0408)
1001 * Suspend Nodes (indirect 0x0409)
1002 * Resume Nodes (indirect 0x040A)
1004 struct ice_aqc_sched_elem_cmd {
1005 __le16 num_elem_req; /* Used by commands */
1006 __le16 num_elem_resp; /* Used by responses */
1012 /* This is the buffer for:
1013 * Suspend Nodes (indirect 0x0409)
1014 * Resume Nodes (indirect 0x040A)
1016 struct ice_aqc_suspend_resume_elem {
1020 struct ice_aqc_txsched_move_grp_info_hdr {
1021 __le32 src_parent_teid;
1022 __le32 dest_parent_teid;
1027 struct ice_aqc_move_elem {
1028 struct ice_aqc_txsched_move_grp_info_hdr hdr;
1032 struct ice_aqc_elem_info_bw {
1033 __le16 bw_profile_idx;
1037 struct ice_aqc_txsched_elem {
1038 u8 elem_type; /* Special field, reserved for some aq calls */
1039 #define ICE_AQC_ELEM_TYPE_UNDEFINED 0x0
1040 #define ICE_AQC_ELEM_TYPE_ROOT_PORT 0x1
1041 #define ICE_AQC_ELEM_TYPE_TC 0x2
1042 #define ICE_AQC_ELEM_TYPE_SE_GENERIC 0x3
1043 #define ICE_AQC_ELEM_TYPE_ENTRY_POINT 0x4
1044 #define ICE_AQC_ELEM_TYPE_LEAF 0x5
1045 #define ICE_AQC_ELEM_TYPE_SE_PADDED 0x6
1047 #define ICE_AQC_ELEM_VALID_GENERIC BIT(0)
1048 #define ICE_AQC_ELEM_VALID_CIR BIT(1)
1049 #define ICE_AQC_ELEM_VALID_EIR BIT(2)
1050 #define ICE_AQC_ELEM_VALID_SHARED BIT(3)
1052 #define ICE_AQC_ELEM_GENERIC_MODE_M 0x1
1053 #define ICE_AQC_ELEM_GENERIC_PRIO_S 0x1
1054 #define ICE_AQC_ELEM_GENERIC_PRIO_M (0x7 << ICE_AQC_ELEM_GENERIC_PRIO_S)
1055 #define ICE_AQC_ELEM_GENERIC_SP_S 0x4
1056 #define ICE_AQC_ELEM_GENERIC_SP_M (0x1 << ICE_AQC_ELEM_GENERIC_SP_S)
1057 #define ICE_AQC_ELEM_GENERIC_ADJUST_VAL_S 0x5
1058 #define ICE_AQC_ELEM_GENERIC_ADJUST_VAL_M \
1059 (0x3 << ICE_AQC_ELEM_GENERIC_ADJUST_VAL_S)
1060 u8 flags; /* Special field, reserved for some aq calls */
1061 #define ICE_AQC_ELEM_FLAG_SUSPEND_M 0x1
1062 struct ice_aqc_elem_info_bw cir_bw;
1063 struct ice_aqc_elem_info_bw eir_bw;
1068 struct ice_aqc_txsched_elem_data {
1071 struct ice_aqc_txsched_elem data;
1074 struct ice_aqc_txsched_topo_grp_info_hdr {
1080 struct ice_aqc_add_elem {
1081 struct ice_aqc_txsched_topo_grp_info_hdr hdr;
1082 struct ice_aqc_txsched_elem_data generic[1];
1085 struct ice_aqc_conf_elem {
1086 struct ice_aqc_txsched_elem_data generic[1];
1089 struct ice_aqc_get_elem {
1090 struct ice_aqc_txsched_elem_data generic[1];
1093 struct ice_aqc_get_topo_elem {
1094 struct ice_aqc_txsched_topo_grp_info_hdr hdr;
1095 struct ice_aqc_txsched_elem_data
1096 generic[ICE_AQC_TOPO_MAX_LEVEL_NUM];
1099 struct ice_aqc_delete_elem {
1100 struct ice_aqc_txsched_topo_grp_info_hdr hdr;
1104 /* Query Port ETS (indirect 0x040E)
1106 * This indirect command is used to query port TC node configuration.
1108 struct ice_aqc_query_port_ets {
1115 struct ice_aqc_port_ets_elem {
1118 /* 3 bits for UP per TC 0-7, 4th byte reserved */
1121 __le32 port_eir_prof_id;
1122 __le32 port_cir_prof_id;
1123 /* 3 bits per Node priority to TC 0-7, 4th byte reserved */
1124 __le32 tc_node_prio;
1125 #define ICE_TC_NODE_PRIO_S 0x4
1127 __le32 tc_node_teid[8]; /* Used for response, reserved in command */
1130 /* Rate limiting profile for
1131 * Add RL profile (indirect 0x0410)
1132 * Query RL profile (indirect 0x0411)
1133 * Remove RL profile (indirect 0x0415)
1134 * These indirect commands acts on single or multiple
1135 * RL profiles with specified data.
1137 struct ice_aqc_rl_profile {
1138 __le16 num_profiles;
1139 __le16 num_processed; /* Only for response. Reserved in Command. */
1145 struct ice_aqc_rl_profile_elem {
1148 #define ICE_AQC_RL_PROFILE_TYPE_S 0x0
1149 #define ICE_AQC_RL_PROFILE_TYPE_M (0x3 << ICE_AQC_RL_PROFILE_TYPE_S)
1150 #define ICE_AQC_RL_PROFILE_TYPE_CIR 0
1151 #define ICE_AQC_RL_PROFILE_TYPE_EIR 1
1152 #define ICE_AQC_RL_PROFILE_TYPE_SRL 2
1153 /* The following flag is used for Query RL Profile Data */
1154 #define ICE_AQC_RL_PROFILE_INVAL_S 0x7
1155 #define ICE_AQC_RL_PROFILE_INVAL_M (0x1 << ICE_AQC_RL_PROFILE_INVAL_S)
1158 __le16 max_burst_size;
1160 __le16 wake_up_calc;
1164 struct ice_aqc_rl_profile_generic_elem {
1165 struct ice_aqc_rl_profile_elem generic[1];
1168 /* Configure L2 Node CGD (indirect 0x0414)
1169 * This indirect command allows configuring a congestion domain for given L2
1170 * node TEIDs in the scheduler topology.
1172 struct ice_aqc_cfg_l2_node_cgd {
1173 __le16 num_l2_nodes;
1179 struct ice_aqc_cfg_l2_node_cgd_elem {
1185 struct ice_aqc_cfg_l2_node_cgd_data {
1186 struct ice_aqc_cfg_l2_node_cgd_elem elem[1];
1189 /* Query Scheduler Resource Allocation (indirect 0x0412)
1190 * This indirect command retrieves the scheduler resources allocated by
1191 * EMP Firmware to the given PF.
1193 struct ice_aqc_query_txsched_res {
1199 struct ice_aqc_generic_sched_props {
1201 __le16 logical_levels;
1202 u8 flattening_bitmap;
1210 struct ice_aqc_layer_props {
1213 __le16 max_device_nodes;
1214 __le16 max_pf_nodes;
1216 __le16 max_sibl_grp_sz;
1217 __le16 max_cir_rl_profiles;
1218 __le16 max_eir_rl_profiles;
1219 __le16 max_srl_profiles;
1223 struct ice_aqc_query_txsched_res_resp {
1224 struct ice_aqc_generic_sched_props sched_props;
1225 struct ice_aqc_layer_props layer_props[ICE_AQC_TOPO_MAX_LEVEL_NUM];
1228 /* Query Node to Root Topology (indirect 0x0413)
1229 * This command uses ice_aqc_get_elem as its data buffer.
1231 struct ice_aqc_query_node_to_root {
1233 __le32 num_nodes; /* Response only */
1238 /* Get PHY capabilities (indirect 0x0600) */
1239 struct ice_aqc_get_phy_caps {
1243 /* 18.0 - Report qualified modules */
1244 #define ICE_AQC_GET_PHY_RQM BIT(0)
1245 /* 18.1 - 18.2 : Report mode
1246 * 00b - Report NVM capabilities
1247 * 01b - Report topology capabilities
1248 * 10b - Report SW configured
1250 #define ICE_AQC_REPORT_MODE_S 1
1251 #define ICE_AQC_REPORT_MODE_M (3 << ICE_AQC_REPORT_MODE_S)
1252 #define ICE_AQC_REPORT_NVM_CAP 0
1253 #define ICE_AQC_REPORT_TOPO_CAP BIT(1)
1254 #define ICE_AQC_REPORT_SW_CFG BIT(2)
1260 /* This is #define of PHY type (Extended):
1261 * The first set of defines is for phy_type_low.
1263 #define ICE_PHY_TYPE_LOW_100BASE_TX BIT_ULL(0)
1264 #define ICE_PHY_TYPE_LOW_100M_SGMII BIT_ULL(1)
1265 #define ICE_PHY_TYPE_LOW_1000BASE_T BIT_ULL(2)
1266 #define ICE_PHY_TYPE_LOW_1000BASE_SX BIT_ULL(3)
1267 #define ICE_PHY_TYPE_LOW_1000BASE_LX BIT_ULL(4)
1268 #define ICE_PHY_TYPE_LOW_1000BASE_KX BIT_ULL(5)
1269 #define ICE_PHY_TYPE_LOW_1G_SGMII BIT_ULL(6)
1270 #define ICE_PHY_TYPE_LOW_2500BASE_T BIT_ULL(7)
1271 #define ICE_PHY_TYPE_LOW_2500BASE_X BIT_ULL(8)
1272 #define ICE_PHY_TYPE_LOW_2500BASE_KX BIT_ULL(9)
1273 #define ICE_PHY_TYPE_LOW_5GBASE_T BIT_ULL(10)
1274 #define ICE_PHY_TYPE_LOW_5GBASE_KR BIT_ULL(11)
1275 #define ICE_PHY_TYPE_LOW_10GBASE_T BIT_ULL(12)
1276 #define ICE_PHY_TYPE_LOW_10G_SFI_DA BIT_ULL(13)
1277 #define ICE_PHY_TYPE_LOW_10GBASE_SR BIT_ULL(14)
1278 #define ICE_PHY_TYPE_LOW_10GBASE_LR BIT_ULL(15)
1279 #define ICE_PHY_TYPE_LOW_10GBASE_KR_CR1 BIT_ULL(16)
1280 #define ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC BIT_ULL(17)
1281 #define ICE_PHY_TYPE_LOW_10G_SFI_C2C BIT_ULL(18)
1282 #define ICE_PHY_TYPE_LOW_25GBASE_T BIT_ULL(19)
1283 #define ICE_PHY_TYPE_LOW_25GBASE_CR BIT_ULL(20)
1284 #define ICE_PHY_TYPE_LOW_25GBASE_CR_S BIT_ULL(21)
1285 #define ICE_PHY_TYPE_LOW_25GBASE_CR1 BIT_ULL(22)
1286 #define ICE_PHY_TYPE_LOW_25GBASE_SR BIT_ULL(23)
1287 #define ICE_PHY_TYPE_LOW_25GBASE_LR BIT_ULL(24)
1288 #define ICE_PHY_TYPE_LOW_25GBASE_KR BIT_ULL(25)
1289 #define ICE_PHY_TYPE_LOW_25GBASE_KR_S BIT_ULL(26)
1290 #define ICE_PHY_TYPE_LOW_25GBASE_KR1 BIT_ULL(27)
1291 #define ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC BIT_ULL(28)
1292 #define ICE_PHY_TYPE_LOW_25G_AUI_C2C BIT_ULL(29)
1293 #define ICE_PHY_TYPE_LOW_40GBASE_CR4 BIT_ULL(30)
1294 #define ICE_PHY_TYPE_LOW_40GBASE_SR4 BIT_ULL(31)
1295 #define ICE_PHY_TYPE_LOW_40GBASE_LR4 BIT_ULL(32)
1296 #define ICE_PHY_TYPE_LOW_40GBASE_KR4 BIT_ULL(33)
1297 #define ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC BIT_ULL(34)
1298 #define ICE_PHY_TYPE_LOW_40G_XLAUI BIT_ULL(35)
1299 #define ICE_PHY_TYPE_LOW_50GBASE_CR2 BIT_ULL(36)
1300 #define ICE_PHY_TYPE_LOW_50GBASE_SR2 BIT_ULL(37)
1301 #define ICE_PHY_TYPE_LOW_50GBASE_LR2 BIT_ULL(38)
1302 #define ICE_PHY_TYPE_LOW_50GBASE_KR2 BIT_ULL(39)
1303 #define ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC BIT_ULL(40)
1304 #define ICE_PHY_TYPE_LOW_50G_LAUI2 BIT_ULL(41)
1305 #define ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC BIT_ULL(42)
1306 #define ICE_PHY_TYPE_LOW_50G_AUI2 BIT_ULL(43)
1307 #define ICE_PHY_TYPE_LOW_50GBASE_CP BIT_ULL(44)
1308 #define ICE_PHY_TYPE_LOW_50GBASE_SR BIT_ULL(45)
1309 #define ICE_PHY_TYPE_LOW_50GBASE_FR BIT_ULL(46)
1310 #define ICE_PHY_TYPE_LOW_50GBASE_LR BIT_ULL(47)
1311 #define ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4 BIT_ULL(48)
1312 #define ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC BIT_ULL(49)
1313 #define ICE_PHY_TYPE_LOW_50G_AUI1 BIT_ULL(50)
1314 #define ICE_PHY_TYPE_LOW_100GBASE_CR4 BIT_ULL(51)
1315 #define ICE_PHY_TYPE_LOW_100GBASE_SR4 BIT_ULL(52)
1316 #define ICE_PHY_TYPE_LOW_100GBASE_LR4 BIT_ULL(53)
1317 #define ICE_PHY_TYPE_LOW_100GBASE_KR4 BIT_ULL(54)
1318 #define ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC BIT_ULL(55)
1319 #define ICE_PHY_TYPE_LOW_100G_CAUI4 BIT_ULL(56)
1320 #define ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC BIT_ULL(57)
1321 #define ICE_PHY_TYPE_LOW_100G_AUI4 BIT_ULL(58)
1322 #define ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4 BIT_ULL(59)
1323 #define ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4 BIT_ULL(60)
1324 #define ICE_PHY_TYPE_LOW_100GBASE_CP2 BIT_ULL(61)
1325 #define ICE_PHY_TYPE_LOW_100GBASE_SR2 BIT_ULL(62)
1326 #define ICE_PHY_TYPE_LOW_100GBASE_DR BIT_ULL(63)
1327 #define ICE_PHY_TYPE_LOW_MAX_INDEX 63
1328 /* The second set of defines is for phy_type_high. */
1329 #define ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4 BIT_ULL(0)
1330 #define ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC BIT_ULL(1)
1331 #define ICE_PHY_TYPE_HIGH_100G_CAUI2 BIT_ULL(2)
1332 #define ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC BIT_ULL(3)
1333 #define ICE_PHY_TYPE_HIGH_100G_AUI2 BIT_ULL(4)
1334 #define ICE_PHY_TYPE_HIGH_MAX_INDEX 5
1336 struct ice_aqc_get_phy_caps_data {
1337 __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */
1338 __le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */
1340 #define ICE_AQC_PHY_EN_TX_LINK_PAUSE BIT(0)
1341 #define ICE_AQC_PHY_EN_RX_LINK_PAUSE BIT(1)
1342 #define ICE_AQC_PHY_LOW_POWER_MODE BIT(2)
1343 #define ICE_AQC_PHY_EN_LINK BIT(3)
1344 #define ICE_AQC_PHY_AN_MODE BIT(4)
1345 #define ICE_AQC_PHY_EN_MOD_QUAL BIT(5)
1346 #define ICE_AQC_PHY_EN_LESM BIT(6)
1347 #define ICE_AQC_PHY_EN_AUTO_FEC BIT(7)
1348 #define ICE_AQC_PHY_CAPS_MASK MAKEMASK(0xff, 0)
1349 u8 low_power_ctrl_an;
1350 #define ICE_AQC_PHY_EN_D3COLD_LOW_POWER_AUTONEG BIT(0)
1351 #define ICE_AQC_PHY_AN_EN_CLAUSE28 BIT(1)
1352 #define ICE_AQC_PHY_AN_EN_CLAUSE73 BIT(2)
1353 #define ICE_AQC_PHY_AN_EN_CLAUSE37 BIT(3)
1355 #define ICE_AQC_PHY_EEE_EN_100BASE_TX BIT(0)
1356 #define ICE_AQC_PHY_EEE_EN_1000BASE_T BIT(1)
1357 #define ICE_AQC_PHY_EEE_EN_10GBASE_T BIT(2)
1358 #define ICE_AQC_PHY_EEE_EN_1000BASE_KX BIT(3)
1359 #define ICE_AQC_PHY_EEE_EN_10GBASE_KR BIT(4)
1360 #define ICE_AQC_PHY_EEE_EN_25GBASE_KR BIT(5)
1361 #define ICE_AQC_PHY_EEE_EN_40GBASE_KR4 BIT(6)
1362 #define ICE_AQC_PHY_EEE_EN_50GBASE_KR2 BIT(7)
1363 #define ICE_AQC_PHY_EEE_EN_50GBASE_KR_PAM4 BIT(8)
1364 #define ICE_AQC_PHY_EEE_EN_100GBASE_KR4 BIT(9)
1365 #define ICE_AQC_PHY_EEE_EN_100GBASE_KR2_PAM4 BIT(10)
1367 u8 phy_id_oui[4]; /* PHY/Module ID connected on the port */
1369 u8 link_fec_options;
1370 #define ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN BIT(0)
1371 #define ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ BIT(1)
1372 #define ICE_AQC_PHY_FEC_25G_RS_528_REQ BIT(2)
1373 #define ICE_AQC_PHY_FEC_25G_KR_REQ BIT(3)
1374 #define ICE_AQC_PHY_FEC_25G_RS_544_REQ BIT(4)
1375 #define ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN BIT(6)
1376 #define ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN BIT(7)
1377 #define ICE_AQC_PHY_FEC_MASK MAKEMASK(0xdf, 0)
1378 u8 module_compliance_enforcement;
1379 #define ICE_AQC_MOD_ENFORCE_STRICT_MODE BIT(0)
1380 u8 extended_compliance_code;
1381 #define ICE_MODULE_TYPE_TOTAL_BYTE 3
1382 u8 module_type[ICE_MODULE_TYPE_TOTAL_BYTE];
1383 #define ICE_AQC_MOD_TYPE_BYTE0_SFP_PLUS 0xA0
1384 #define ICE_AQC_MOD_TYPE_BYTE0_QSFP_PLUS 0x80
1385 #define ICE_AQC_MOD_TYPE_IDENT 1
1386 #define ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_PASSIVE BIT(0)
1387 #define ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_ACTIVE BIT(1)
1388 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_SR BIT(4)
1389 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_LR BIT(5)
1390 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_LRM BIT(6)
1391 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_ER BIT(7)
1392 #define ICE_AQC_MOD_TYPE_BYTE2_SFP_PLUS 0xA0
1393 #define ICE_AQC_MOD_TYPE_BYTE2_QSFP_PLUS 0x86
1394 u8 qualified_module_count;
1395 u8 rsvd2[7]; /* Bytes 47:41 reserved */
1396 #define ICE_AQC_QUAL_MOD_COUNT_MAX 16
1403 } qual_modules[ICE_AQC_QUAL_MOD_COUNT_MAX];
1406 /* Set PHY capabilities (direct 0x0601)
1407 * NOTE: This command must be followed by setup link and restart auto-neg
1409 struct ice_aqc_set_phy_cfg {
1416 /* Set PHY config command data structure */
1417 struct ice_aqc_set_phy_cfg_data {
1418 __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */
1419 __le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */
1421 #define ICE_AQ_PHY_ENA_VALID_MASK MAKEMASK(0xef, 0)
1422 #define ICE_AQ_PHY_ENA_TX_PAUSE_ABILITY BIT(0)
1423 #define ICE_AQ_PHY_ENA_RX_PAUSE_ABILITY BIT(1)
1424 #define ICE_AQ_PHY_ENA_LOW_POWER BIT(2)
1425 #define ICE_AQ_PHY_ENA_LINK BIT(3)
1426 #define ICE_AQ_PHY_ENA_AUTO_LINK_UPDT BIT(5)
1427 #define ICE_AQ_PHY_ENA_LESM BIT(6)
1428 #define ICE_AQ_PHY_ENA_AUTO_FEC BIT(7)
1429 u8 low_power_ctrl_an;
1430 __le16 eee_cap; /* Value from ice_aqc_get_phy_caps */
1432 u8 link_fec_opt; /* Use defines from ice_aqc_get_phy_caps */
1433 u8 module_compliance_enforcement;
1436 /* Set MAC Config command data structure (direct 0x0603) */
1437 struct ice_aqc_set_mac_cfg {
1438 __le16 max_frame_size;
1440 #define ICE_AQ_SET_MAC_PACE_S 3
1441 #define ICE_AQ_SET_MAC_PACE_M (0xF << ICE_AQ_SET_MAC_PACE_S)
1442 #define ICE_AQ_SET_MAC_PACE_TYPE_M BIT(7)
1443 #define ICE_AQ_SET_MAC_PACE_TYPE_RATE 0
1444 #define ICE_AQ_SET_MAC_PACE_TYPE_FIXED ICE_AQ_SET_MAC_PACE_TYPE_M
1446 __le16 tx_tmr_value;
1447 __le16 fc_refresh_threshold;
1449 #define ICE_AQ_SET_MAC_AUTO_DROP_MASK BIT(0)
1450 #define ICE_AQ_SET_MAC_AUTO_DROP_NONE 0
1451 #define ICE_AQ_SET_MAC_AUTO_DROP_BLOCKING_PKTS BIT(0)
1455 /* Restart AN command data structure (direct 0x0605)
1456 * Also used for response, with only the lport_num field present.
1458 struct ice_aqc_restart_an {
1462 #define ICE_AQC_RESTART_AN_LINK_RESTART BIT(1)
1463 #define ICE_AQC_RESTART_AN_LINK_ENABLE BIT(2)
1467 /* Get link status (indirect 0x0607), also used for Link Status Event */
1468 struct ice_aqc_get_link_status {
1472 #define ICE_AQ_LSE_M 0x3
1473 #define ICE_AQ_LSE_NOP 0x0
1474 #define ICE_AQ_LSE_DIS 0x2
1475 #define ICE_AQ_LSE_ENA 0x3
1476 /* only response uses this flag */
1477 #define ICE_AQ_LSE_IS_ENABLED 0x1
1483 /* Get link status response data structure, also used for Link Status Event */
1484 struct ice_aqc_get_link_status_data {
1485 u8 topo_media_conflict;
1486 #define ICE_AQ_LINK_TOPO_CONFLICT BIT(0)
1487 #define ICE_AQ_LINK_MEDIA_CONFLICT BIT(1)
1488 #define ICE_AQ_LINK_TOPO_CORRUPT BIT(2)
1489 #define ICE_AQ_LINK_TOPO_UNREACH_PRT BIT(4)
1490 #define ICE_AQ_LINK_TOPO_UNDRUTIL_PRT BIT(5)
1491 #define ICE_AQ_LINK_TOPO_UNDRUTIL_MEDIA BIT(6)
1492 #define ICE_AQ_LINK_TOPO_UNSUPP_MEDIA BIT(7)
1494 #define ICE_AQ_LINK_CFG_ERR BIT(0)
1496 #define ICE_AQ_LINK_UP BIT(0) /* Link Status */
1497 #define ICE_AQ_LINK_FAULT BIT(1)
1498 #define ICE_AQ_LINK_FAULT_TX BIT(2)
1499 #define ICE_AQ_LINK_FAULT_RX BIT(3)
1500 #define ICE_AQ_LINK_FAULT_REMOTE BIT(4)
1501 #define ICE_AQ_LINK_UP_PORT BIT(5) /* External Port Link Status */
1502 #define ICE_AQ_MEDIA_AVAILABLE BIT(6)
1503 #define ICE_AQ_SIGNAL_DETECT BIT(7)
1505 #define ICE_AQ_AN_COMPLETED BIT(0)
1506 #define ICE_AQ_LP_AN_ABILITY BIT(1)
1507 #define ICE_AQ_PD_FAULT BIT(2) /* Parallel Detection Fault */
1508 #define ICE_AQ_FEC_EN BIT(3)
1509 #define ICE_AQ_PHY_LOW_POWER BIT(4) /* Low Power State */
1510 #define ICE_AQ_LINK_PAUSE_TX BIT(5)
1511 #define ICE_AQ_LINK_PAUSE_RX BIT(6)
1512 #define ICE_AQ_QUALIFIED_MODULE BIT(7)
1514 #define ICE_AQ_LINK_PHY_TEMP_ALARM BIT(0)
1515 #define ICE_AQ_LINK_EXCESSIVE_ERRORS BIT(1) /* Excessive Link Errors */
1516 /* Port Tx Suspended */
1517 #define ICE_AQ_LINK_TX_S 2
1518 #define ICE_AQ_LINK_TX_M (0x03 << ICE_AQ_LINK_TX_S)
1519 #define ICE_AQ_LINK_TX_ACTIVE 0
1520 #define ICE_AQ_LINK_TX_DRAINED 1
1521 #define ICE_AQ_LINK_TX_FLUSHED 3
1523 #define ICE_AQ_LINK_LB_PHY_LCL BIT(0)
1524 #define ICE_AQ_LINK_LB_PHY_RMT BIT(1)
1525 #define ICE_AQ_LINK_LB_MAC_LCL BIT(2)
1526 #define ICE_AQ_LINK_LB_PHY_IDX_S 3
1527 #define ICE_AQ_LINK_LB_PHY_IDX_M (0x7 << ICE_AQ_LB_PHY_IDX_S)
1528 __le16 max_frame_size;
1530 #define ICE_AQ_LINK_25G_KR_FEC_EN BIT(0)
1531 #define ICE_AQ_LINK_25G_RS_528_FEC_EN BIT(1)
1532 #define ICE_AQ_LINK_25G_RS_544_FEC_EN BIT(2)
1533 #define ICE_AQ_FEC_MASK MAKEMASK(0x7, 0)
1535 #define ICE_AQ_CFG_PACING_S 3
1536 #define ICE_AQ_CFG_PACING_M (0xF << ICE_AQ_CFG_PACING_S)
1537 #define ICE_AQ_CFG_PACING_TYPE_M BIT(7)
1538 #define ICE_AQ_CFG_PACING_TYPE_AVG 0
1539 #define ICE_AQ_CFG_PACING_TYPE_FIXED ICE_AQ_CFG_PACING_TYPE_M
1540 /* External Device Power Ability */
1542 #define ICE_AQ_PWR_CLASS_M 0x3
1543 #define ICE_AQ_LINK_PWR_BASET_LOW_HIGH 0
1544 #define ICE_AQ_LINK_PWR_BASET_HIGH 1
1545 #define ICE_AQ_LINK_PWR_QSFP_CLASS_1 0
1546 #define ICE_AQ_LINK_PWR_QSFP_CLASS_2 1
1547 #define ICE_AQ_LINK_PWR_QSFP_CLASS_3 2
1548 #define ICE_AQ_LINK_PWR_QSFP_CLASS_4 3
1550 #define ICE_AQ_LINK_SPEED_M 0x7FF
1551 #define ICE_AQ_LINK_SPEED_10MB BIT(0)
1552 #define ICE_AQ_LINK_SPEED_100MB BIT(1)
1553 #define ICE_AQ_LINK_SPEED_1000MB BIT(2)
1554 #define ICE_AQ_LINK_SPEED_2500MB BIT(3)
1555 #define ICE_AQ_LINK_SPEED_5GB BIT(4)
1556 #define ICE_AQ_LINK_SPEED_10GB BIT(5)
1557 #define ICE_AQ_LINK_SPEED_20GB BIT(6)
1558 #define ICE_AQ_LINK_SPEED_25GB BIT(7)
1559 #define ICE_AQ_LINK_SPEED_40GB BIT(8)
1560 #define ICE_AQ_LINK_SPEED_50GB BIT(9)
1561 #define ICE_AQ_LINK_SPEED_100GB BIT(10)
1562 #define ICE_AQ_LINK_SPEED_UNKNOWN BIT(15)
1563 __le32 reserved3; /* Aligns next field to 8-byte boundary */
1564 __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */
1565 __le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */
1568 /* Set event mask command (direct 0x0613) */
1569 struct ice_aqc_set_event_mask {
1573 #define ICE_AQ_LINK_EVENT_UPDOWN BIT(1)
1574 #define ICE_AQ_LINK_EVENT_MEDIA_NA BIT(2)
1575 #define ICE_AQ_LINK_EVENT_LINK_FAULT BIT(3)
1576 #define ICE_AQ_LINK_EVENT_PHY_TEMP_ALARM BIT(4)
1577 #define ICE_AQ_LINK_EVENT_EXCESSIVE_ERRORS BIT(5)
1578 #define ICE_AQ_LINK_EVENT_SIGNAL_DETECT BIT(6)
1579 #define ICE_AQ_LINK_EVENT_AN_COMPLETED BIT(7)
1580 #define ICE_AQ_LINK_EVENT_MODULE_QUAL_FAIL BIT(8)
1581 #define ICE_AQ_LINK_EVENT_PORT_TX_SUSPENDED BIT(9)
1582 #define ICE_AQ_LINK_EVENT_TOPO_CONFLICT BIT(10)
1583 #define ICE_AQ_LINK_EVENT_MEDIA_CONFLICT BIT(11)
1587 /* Set MAC Loopback command (direct 0x0620) */
1588 struct ice_aqc_set_mac_lb {
1590 #define ICE_AQ_MAC_LB_EN BIT(0)
1591 #define ICE_AQ_MAC_LB_OSC_CLK BIT(1)
1595 struct ice_aqc_link_topo_addr {
1598 #define ICE_AQC_LINK_TOPO_PORT_NUM_VALID BIT(0)
1600 #define ICE_AQC_LINK_TOPO_NODE_TYPE_S 0
1601 #define ICE_AQC_LINK_TOPO_NODE_TYPE_M (0xF << ICE_AQC_LINK_TOPO_NODE_TYPE_S)
1602 #define ICE_AQC_LINK_TOPO_NODE_TYPE_PHY 0
1603 #define ICE_AQC_LINK_TOPO_NODE_TYPE_GPIO_CTRL 1
1604 #define ICE_AQC_LINK_TOPO_NODE_TYPE_MUX_CTRL 2
1605 #define ICE_AQC_LINK_TOPO_NODE_TYPE_LED_CTRL 3
1606 #define ICE_AQC_LINK_TOPO_NODE_TYPE_LED 4
1607 #define ICE_AQC_LINK_TOPO_NODE_TYPE_THERMAL 5
1608 #define ICE_AQC_LINK_TOPO_NODE_TYPE_CAGE 6
1609 #define ICE_AQC_LINK_TOPO_NODE_TYPE_MEZZ 7
1610 #define ICE_AQC_LINK_TOPO_NODE_TYPE_ID_EEPROM 8
1611 #define ICE_AQC_LINK_TOPO_NODE_CTX_S 4
1612 #define ICE_AQC_LINK_TOPO_NODE_CTX_M \
1613 (0xF << ICE_AQC_LINK_TOPO_NODE_CTX_S)
1614 #define ICE_AQC_LINK_TOPO_NODE_CTX_GLOBAL 0
1615 #define ICE_AQC_LINK_TOPO_NODE_CTX_BOARD 1
1616 #define ICE_AQC_LINK_TOPO_NODE_CTX_PORT 2
1617 #define ICE_AQC_LINK_TOPO_NODE_CTX_NODE 3
1618 #define ICE_AQC_LINK_TOPO_NODE_CTX_PROVIDED 4
1619 #define ICE_AQC_LINK_TOPO_NODE_CTX_OVERRIDE 5
1622 #define ICE_AQC_LINK_TOPO_HANDLE_S 0
1623 #define ICE_AQC_LINK_TOPO_HANDLE_M (0x3FF << ICE_AQC_LINK_TOPO_HANDLE_S)
1624 /* Used to decode the handle field */
1625 #define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_M BIT(9)
1626 #define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_LOM BIT(9)
1627 #define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_MEZZ 0
1628 #define ICE_AQC_LINK_TOPO_HANDLE_NODE_S 0
1629 /* In case of a Mezzanine type */
1630 #define ICE_AQC_LINK_TOPO_HANDLE_MEZZ_NODE_M \
1631 (0x3F << ICE_AQC_LINK_TOPO_HANDLE_NODE_S)
1632 #define ICE_AQC_LINK_TOPO_HANDLE_MEZZ_S 6
1633 #define ICE_AQC_LINK_TOPO_HANDLE_MEZZ_M (0x7 << ICE_AQC_LINK_TOPO_HANDLE_MEZZ_S)
1634 /* In case of a LOM type */
1635 #define ICE_AQC_LINK_TOPO_HANDLE_LOM_NODE_M \
1636 (0x1FF << ICE_AQC_LINK_TOPO_HANDLE_NODE_S)
1639 /* Get Link Topology Handle (direct, 0x06E0) */
1640 struct ice_aqc_get_link_topo {
1641 struct ice_aqc_link_topo_addr addr;
1646 /* Set Port Identification LED (direct, 0x06E9) */
1647 struct ice_aqc_set_port_id_led {
1650 #define ICE_AQC_PORT_ID_PORT_NUM_VALID BIT(0)
1652 #define ICE_AQC_PORT_IDENT_LED_BLINK BIT(0)
1653 #define ICE_AQC_PORT_IDENT_LED_ORIG 0
1657 /* Read/Write SFF EEPROM command (indirect 0x06EE) */
1658 struct ice_aqc_sff_eeprom {
1661 #define ICE_AQC_SFF_PORT_NUM_VALID BIT(0)
1662 __le16 i2c_bus_addr;
1663 #define ICE_AQC_SFF_I2CBUS_7BIT_M 0x7F
1664 #define ICE_AQC_SFF_I2CBUS_10BIT_M 0x3FF
1665 #define ICE_AQC_SFF_I2CBUS_TYPE_M BIT(10)
1666 #define ICE_AQC_SFF_I2CBUS_TYPE_7BIT 0
1667 #define ICE_AQC_SFF_I2CBUS_TYPE_10BIT ICE_AQC_SFF_I2CBUS_TYPE_M
1668 #define ICE_AQC_SFF_SET_EEPROM_PAGE_S 11
1669 #define ICE_AQC_SFF_SET_EEPROM_PAGE_M (0x3 << ICE_AQC_SFF_SET_EEPROM_PAGE_S)
1670 #define ICE_AQC_SFF_NO_PAGE_CHANGE 0
1671 #define ICE_AQC_SFF_SET_23_ON_MISMATCH 1
1672 #define ICE_AQC_SFF_SET_22_ON_MISMATCH 2
1673 #define ICE_AQC_SFF_IS_WRITE BIT(15)
1674 __le16 i2c_mem_addr;
1676 #define ICE_AQC_SFF_EEPROM_BANK_S 0
1677 #define ICE_AQC_SFF_EEPROM_BANK_M (0xFF << ICE_AQC_SFF_EEPROM_BANK_S)
1678 #define ICE_AQC_SFF_EEPROM_PAGE_S 8
1679 #define ICE_AQC_SFF_EEPROM_PAGE_M (0xFF << ICE_AQC_SFF_EEPROM_PAGE_S)
1684 /* NVM Read command (indirect 0x0701)
1685 * NVM Erase commands (direct 0x0702)
1686 * NVM Write commands (indirect 0x0703)
1687 * NVM Write Activate commands (direct 0x0707)
1688 * NVM Shadow RAM Dump commands (direct 0x0707)
1690 struct ice_aqc_nvm {
1691 #define ICE_AQC_NVM_MAX_OFFSET 0xFFFFFF
1693 u8 offset_high; /* For Write Activate offset_high is used as flags2 */
1695 #define ICE_AQC_NVM_LAST_CMD BIT(0)
1696 #define ICE_AQC_NVM_PCIR_REQ BIT(0) /* Used by NVM Write reply */
1697 #define ICE_AQC_NVM_PRESERVATION_S 1 /* Used by NVM Write Activate only */
1698 #define ICE_AQC_NVM_PRESERVATION_M (3 << ICE_AQC_NVM_PRESERVATION_S)
1699 #define ICE_AQC_NVM_NO_PRESERVATION (0 << ICE_AQC_NVM_PRESERVATION_S)
1700 #define ICE_AQC_NVM_PRESERVE_ALL BIT(1)
1701 #define ICE_AQC_NVM_FACTORY_DEFAULT (2 << ICE_AQC_NVM_PRESERVATION_S)
1702 #define ICE_AQC_NVM_PRESERVE_SELECTED (3 << ICE_AQC_NVM_PRESERVATION_S)
1703 #define ICE_AQC_NVM_ACTIV_SEL_NVM BIT(3) /* Write Activate/SR Dump only */
1704 #define ICE_AQC_NVM_ACTIV_SEL_OROM BIT(4)
1705 #define ICE_AQC_NVM_ACTIV_SEL_NETLIST BIT(5)
1706 #define ICE_AQC_NVM_SPECIAL_UPDATE BIT(6)
1707 #define ICE_AQC_NVM_REVERT_LAST_ACTIV BIT(6) /* Write Activate only */
1708 #define ICE_AQC_NVM_ACTIV_SEL_MASK MAKEMASK(0x7, 3)
1709 #define ICE_AQC_NVM_FLASH_ONLY BIT(7)
1710 __le16 module_typeid;
1712 #define ICE_AQC_NVM_ERASE_LEN 0xFFFF
1717 /* NVM Module_Type ID, needed offset and read_len for struct ice_aqc_nvm. */
1718 #define ICE_AQC_NVM_SECTOR_UNIT 4096 /* In Bytes */
1719 #define ICE_AQC_NVM_WORD_UNIT 2 /* In Bytes */
1721 #define ICE_AQC_NVM_START_POINT 0
1722 #define ICE_AQC_NVM_EMP_SR_PTR_OFFSET 0x90
1723 #define ICE_AQC_NVM_EMP_SR_PTR_RD_LEN 2 /* In Bytes */
1724 #define ICE_AQC_NVM_EMP_SR_PTR_M MAKEMASK(0x7FFF, 0)
1725 #define ICE_AQC_NVM_EMP_SR_PTR_TYPE_S 15
1726 #define ICE_AQC_NVM_EMP_SR_PTR_TYPE_M BIT(15)
1727 #define ICE_AQC_NVM_EMP_SR_PTR_TYPE_SECTOR 1
1729 #define ICE_AQC_NVM_LLDP_CFG_PTR_OFFSET 0x46
1730 #define ICE_AQC_NVM_LLDP_CFG_HEADER_LEN 2 /* In Bytes */
1731 #define ICE_AQC_NVM_LLDP_CFG_PTR_RD_LEN 2 /* In Bytes */
1733 #define ICE_AQC_NVM_LLDP_PRESERVED_MOD_ID 0x129
1734 #define ICE_AQC_NVM_CUR_LLDP_PERSIST_RD_OFFSET 2 /* In Bytes */
1735 #define ICE_AQC_NVM_LLDP_STATUS_M MAKEMASK(0xF, 0)
1736 #define ICE_AQC_NVM_LLDP_STATUS_M_LEN 4 /* In Bits */
1737 #define ICE_AQC_NVM_LLDP_STATUS_RD_LEN 4 /* In Bytes */
1739 /* The result of netlist NVM read comes in a TLV format. The actual data
1740 * (netlist header) starts from word offset 1 (byte 2). The FW strips
1741 * out the type field from the TLV header so all the netlist fields
1742 * should adjust their offset value by 1 word (2 bytes) in order to map
1743 * their correct location.
1745 #define ICE_AQC_NVM_LINK_TOPO_NETLIST_MOD_ID 0x11B
1746 #define ICE_AQC_NVM_LINK_TOPO_NETLIST_LEN_OFFSET 1
1747 #define ICE_AQC_NVM_LINK_TOPO_NETLIST_LEN 2 /* In bytes */
1748 #define ICE_AQC_NVM_NETLIST_NODE_COUNT_OFFSET 2
1749 #define ICE_AQC_NVM_NETLIST_NODE_COUNT_LEN 2 /* In bytes */
1750 #define ICE_AQC_NVM_NETLIST_ID_BLK_START_OFFSET 5
1751 #define ICE_AQC_NVM_NETLIST_ID_BLK_LEN 0x30 /* In words */
1753 /* netlist ID block field offsets (word offsets) */
1754 #define ICE_AQC_NVM_NETLIST_ID_BLK_MAJOR_VER_LOW 2
1755 #define ICE_AQC_NVM_NETLIST_ID_BLK_MAJOR_VER_HIGH 3
1756 #define ICE_AQC_NVM_NETLIST_ID_BLK_MINOR_VER_LOW 4
1757 #define ICE_AQC_NVM_NETLIST_ID_BLK_MINOR_VER_HIGH 5
1758 #define ICE_AQC_NVM_NETLIST_ID_BLK_TYPE_LOW 6
1759 #define ICE_AQC_NVM_NETLIST_ID_BLK_TYPE_HIGH 7
1760 #define ICE_AQC_NVM_NETLIST_ID_BLK_REV_LOW 8
1761 #define ICE_AQC_NVM_NETLIST_ID_BLK_REV_HIGH 9
1762 #define ICE_AQC_NVM_NETLIST_ID_BLK_SHA_HASH 0xA
1763 #define ICE_AQC_NVM_NETLIST_ID_BLK_CUST_VER 0x2F
1765 /* Used for 0x0704 as well as for 0x0705 commands */
1766 struct ice_aqc_nvm_cfg {
1768 #define ICE_AQC_ANVM_MULTIPLE_ELEMS BIT(0)
1769 #define ICE_AQC_ANVM_IMMEDIATE_FIELD BIT(1)
1770 #define ICE_AQC_ANVM_NEW_CFG BIT(2)
1779 struct ice_aqc_nvm_cfg_data {
1781 __le16 field_options;
1785 /* NVM Checksum Command (direct, 0x0706) */
1786 struct ice_aqc_nvm_checksum {
1788 #define ICE_AQC_NVM_CHECKSUM_VERIFY BIT(0)
1789 #define ICE_AQC_NVM_CHECKSUM_RECALC BIT(1)
1791 __le16 checksum; /* Used only by response */
1792 #define ICE_AQC_NVM_CHECKSUM_CORRECT 0xBABA
1796 /* Get LLDP MIB (indirect 0x0A00)
1797 * Note: This is also used by the LLDP MIB Change Event (0x0A01)
1798 * as the format is the same.
1800 struct ice_aqc_lldp_get_mib {
1802 #define ICE_AQ_LLDP_MIB_TYPE_S 0
1803 #define ICE_AQ_LLDP_MIB_TYPE_M (0x3 << ICE_AQ_LLDP_MIB_TYPE_S)
1804 #define ICE_AQ_LLDP_MIB_LOCAL 0
1805 #define ICE_AQ_LLDP_MIB_REMOTE 1
1806 #define ICE_AQ_LLDP_MIB_LOCAL_AND_REMOTE 2
1807 #define ICE_AQ_LLDP_BRID_TYPE_S 2
1808 #define ICE_AQ_LLDP_BRID_TYPE_M (0x3 << ICE_AQ_LLDP_BRID_TYPE_S)
1809 #define ICE_AQ_LLDP_BRID_TYPE_NEAREST_BRID 0
1810 #define ICE_AQ_LLDP_BRID_TYPE_NON_TPMR 1
1811 /* Tx pause flags in the 0xA01 event use ICE_AQ_LLDP_TX_* */
1812 #define ICE_AQ_LLDP_TX_S 0x4
1813 #define ICE_AQ_LLDP_TX_M (0x03 << ICE_AQ_LLDP_TX_S)
1814 #define ICE_AQ_LLDP_TX_ACTIVE 0
1815 #define ICE_AQ_LLDP_TX_SUSPENDED 1
1816 #define ICE_AQ_LLDP_TX_FLUSHED 3
1817 /* The following bytes are reserved for the Get LLDP MIB command (0x0A00)
1818 * and in the LLDP MIB Change Event (0x0A01). They are valid for the
1819 * Get LLDP MIB (0x0A00) response only.
1829 /* Configure LLDP MIB Change Event (direct 0x0A01) */
1830 /* For MIB Change Event use ice_aqc_lldp_get_mib structure above */
1831 struct ice_aqc_lldp_set_mib_change {
1833 #define ICE_AQ_LLDP_MIB_UPDATE_ENABLE 0x0
1834 #define ICE_AQ_LLDP_MIB_UPDATE_DIS 0x1
1838 /* Add LLDP TLV (indirect 0x0A02)
1839 * Delete LLDP TLV (indirect 0x0A04)
1841 struct ice_aqc_lldp_add_delete_tlv {
1842 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */
1850 /* Update LLDP TLV (indirect 0x0A03) */
1851 struct ice_aqc_lldp_update_tlv {
1852 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */
1861 /* Stop LLDP (direct 0x0A05) */
1862 struct ice_aqc_lldp_stop {
1864 #define ICE_AQ_LLDP_AGENT_STATE_MASK BIT(0)
1865 #define ICE_AQ_LLDP_AGENT_STOP 0x0
1866 #define ICE_AQ_LLDP_AGENT_SHUTDOWN ICE_AQ_LLDP_AGENT_STATE_MASK
1867 #define ICE_AQ_LLDP_AGENT_PERSIST_DIS BIT(1)
1871 /* Start LLDP (direct 0x0A06) */
1872 struct ice_aqc_lldp_start {
1874 #define ICE_AQ_LLDP_AGENT_START BIT(0)
1875 #define ICE_AQ_LLDP_AGENT_PERSIST_ENA BIT(1)
1879 /* Get CEE DCBX Oper Config (0x0A07)
1880 * The command uses the generic descriptor struct and
1881 * returns the struct below as an indirect response.
1883 struct ice_aqc_get_cee_dcb_cfg_resp {
1888 __le16 oper_app_prio;
1889 #define ICE_AQC_CEE_APP_FCOE_S 0
1890 #define ICE_AQC_CEE_APP_FCOE_M (0x7 << ICE_AQC_CEE_APP_FCOE_S)
1891 #define ICE_AQC_CEE_APP_ISCSI_S 3
1892 #define ICE_AQC_CEE_APP_ISCSI_M (0x7 << ICE_AQC_CEE_APP_ISCSI_S)
1893 #define ICE_AQC_CEE_APP_FIP_S 8
1894 #define ICE_AQC_CEE_APP_FIP_M (0x7 << ICE_AQC_CEE_APP_FIP_S)
1896 #define ICE_AQC_CEE_PG_STATUS_S 0
1897 #define ICE_AQC_CEE_PG_STATUS_M (0x7 << ICE_AQC_CEE_PG_STATUS_S)
1898 #define ICE_AQC_CEE_PFC_STATUS_S 3
1899 #define ICE_AQC_CEE_PFC_STATUS_M (0x7 << ICE_AQC_CEE_PFC_STATUS_S)
1900 #define ICE_AQC_CEE_FCOE_STATUS_S 8
1901 #define ICE_AQC_CEE_FCOE_STATUS_M (0x7 << ICE_AQC_CEE_FCOE_STATUS_S)
1902 #define ICE_AQC_CEE_ISCSI_STATUS_S 11
1903 #define ICE_AQC_CEE_ISCSI_STATUS_M (0x7 << ICE_AQC_CEE_ISCSI_STATUS_S)
1904 #define ICE_AQC_CEE_FIP_STATUS_S 16
1905 #define ICE_AQC_CEE_FIP_STATUS_M (0x7 << ICE_AQC_CEE_FIP_STATUS_S)
1909 /* Set Local LLDP MIB (indirect 0x0A08)
1910 * Used to replace the local MIB of a given LLDP agent. e.g. DCBX
1912 struct ice_aqc_lldp_set_local_mib {
1914 #define SET_LOCAL_MIB_TYPE_DCBX_M BIT(0)
1915 #define SET_LOCAL_MIB_TYPE_LOCAL_MIB 0
1916 #define SET_LOCAL_MIB_TYPE_CEE_M BIT(1)
1917 #define SET_LOCAL_MIB_TYPE_CEE_WILLING 0
1918 #define SET_LOCAL_MIB_TYPE_CEE_NON_WILLING SET_LOCAL_MIB_TYPE_CEE_M
1926 struct ice_aqc_lldp_set_local_mib_resp {
1928 #define SET_LOCAL_MIB_RESP_EVENT_M BIT(0)
1929 #define SET_LOCAL_MIB_RESP_MIB_CHANGE_SILENT 0
1930 #define SET_LOCAL_MIB_RESP_MIB_CHANGE_EVENT SET_LOCAL_MIB_RESP_EVENT_M
1934 /* Stop/Start LLDP Agent (direct 0x0A09)
1935 * Used for stopping/starting specific LLDP agent. e.g. DCBX.
1936 * The same structure is used for the response, with the command field
1937 * being used as the status field.
1939 struct ice_aqc_lldp_stop_start_specific_agent {
1941 #define ICE_AQC_START_STOP_AGENT_M BIT(0)
1942 #define ICE_AQC_START_STOP_AGENT_STOP_DCBX 0
1943 #define ICE_AQC_START_STOP_AGENT_START_DCBX ICE_AQC_START_STOP_AGENT_M
1947 /* LLDP Filter Control (direct 0x0A0A) */
1948 struct ice_aqc_lldp_filter_ctrl {
1950 #define ICE_AQC_LLDP_FILTER_ACTION_M MAKEMASK(3, 0)
1951 #define ICE_AQC_LLDP_FILTER_ACTION_ADD 0x0
1952 #define ICE_AQC_LLDP_FILTER_ACTION_DELETE 0x1
1953 #define ICE_AQC_LLDP_FILTER_ACTION_UPDATE 0x2
1959 /* Get/Set RSS key (indirect 0x0B04/0x0B02) */
1960 struct ice_aqc_get_set_rss_key {
1961 #define ICE_AQC_GSET_RSS_KEY_VSI_VALID BIT(15)
1962 #define ICE_AQC_GSET_RSS_KEY_VSI_ID_S 0
1963 #define ICE_AQC_GSET_RSS_KEY_VSI_ID_M (0x3FF << ICE_AQC_GSET_RSS_KEY_VSI_ID_S)
1970 #define ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE 0x28
1971 #define ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE 0xC
1972 #define ICE_GET_SET_RSS_KEY_EXTEND_KEY_SIZE \
1973 (ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE + \
1974 ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE)
1977 * struct ice_aqc_get_set_rss_keys - Get/Set RSS hash key command buffer
1978 * @standard_rss_key: 40 most significant bytes of hash key
1979 * @extended_hash_key: 12 least significant bytes of hash key
1981 * Set/Get 40 byte hash key using standard_rss_key field, and set
1982 * extended_hash_key field to zero. Set/Get 52 byte hash key using
1983 * standard_rss_key field for 40 most significant bytes and the
1984 * extended_hash_key field for the 12 least significant bytes of hash key.
1986 struct ice_aqc_get_set_rss_keys {
1987 u8 standard_rss_key[ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE];
1988 u8 extended_hash_key[ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE];
1991 /* Get/Set RSS LUT (indirect 0x0B05/0x0B03) */
1992 struct ice_aqc_get_set_rss_lut {
1993 #define ICE_AQC_GSET_RSS_LUT_VSI_VALID BIT(15)
1994 #define ICE_AQC_GSET_RSS_LUT_VSI_ID_S 0
1995 #define ICE_AQC_GSET_RSS_LUT_VSI_ID_M (0x3FF << ICE_AQC_GSET_RSS_LUT_VSI_ID_S)
1997 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S 0
1998 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_M \
1999 (0x3 << ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S)
2001 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_VSI 0
2002 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF 1
2003 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL 2
2005 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S 2
2006 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M \
2007 (0x3 << ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S)
2009 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128 128
2010 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128_FLAG 0
2011 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512 512
2012 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512_FLAG 1
2013 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K 2048
2014 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K_FLAG 2
2016 #define ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S 4
2017 #define ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_M \
2018 (0xF << ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S)
2026 /* Clear FD Table Command (direct, 0x0B06) */
2027 struct ice_aqc_clear_fd_table {
2029 #define CL_FD_VM_VF_TYPE_VSI_IDX 1
2030 #define CL_FD_VM_VF_TYPE_PF_IDX 2
2036 /* Allocate ACL table (indirect 0x0C10) */
2037 #define ICE_AQC_ACL_KEY_WIDTH 40
2038 #define ICE_AQC_ACL_KEY_WIDTH_BYTES 5
2039 #define ICE_AQC_ACL_TCAM_DEPTH 512
2040 #define ICE_ACL_ENTRY_ALLOC_UNIT 64
2041 #define ICE_AQC_MAX_CONCURRENT_ACL_TBL 15
2042 #define ICE_AQC_MAX_ACTION_MEMORIES 20
2043 #define ICE_AQC_MAX_ACTION_ENTRIES 512
2044 #define ICE_AQC_ACL_SLICES 16
2045 #define ICE_AQC_ALLOC_ID_LESS_THAN_4K 0x1000
2046 /* The ACL block supports up to 8 actions per a single output. */
2047 #define ICE_AQC_TBL_MAX_ACTION_PAIRS 4
2049 #define ICE_AQC_MAX_TCAM_ALLOC_UNITS (ICE_AQC_ACL_TCAM_DEPTH / \
2050 ICE_ACL_ENTRY_ALLOC_UNIT)
2051 #define ICE_AQC_ACL_ALLOC_UNITS (ICE_AQC_ACL_SLICES * \
2052 ICE_AQC_MAX_TCAM_ALLOC_UNITS)
2054 struct ice_aqc_acl_alloc_table {
2057 u8 act_pairs_per_entry;
2058 /* For non-concurrent table allocation, this field needs
2059 * to be set to zero(0) otherwise it shall specify the
2060 * amount of concurrent tables whose AllocIDs are
2061 * specified in buffer. Thus the newly allocated table
2062 * is concurrent with table IDs specified in AllocIDs.
2064 #define ICE_AQC_ACL_ALLOC_TABLE_TYPE_NONCONCURR 0
2071 /* Allocate ACL table command buffer format */
2072 struct ice_aqc_acl_alloc_table_data {
2073 /* Dependent table AllocIDs. Each word in this 15 word array specifies
2074 * a dependent table AllocID according to the amount specified in the
2075 * "table_type" field. All unused words shall be set to 0xFFFF
2077 #define ICE_AQC_CONCURR_ID_INVALID 0xffff
2078 __le16 alloc_ids[ICE_AQC_MAX_CONCURRENT_ACL_TBL];
2081 /* Deallocate ACL table (indirect 0x0C11)
2082 * Allocate ACL action-pair (indirect 0x0C12)
2083 * Deallocate ACL action-pair (indirect 0x0C13)
2086 /* Following structure is common and used in case of deallocation
2087 * of ACL table and action-pair
2089 struct ice_aqc_acl_tbl_actpair {
2090 /* Alloc ID of the table being released */
2097 /* This response structure is same in case of alloc/dealloc table,
2098 * alloc/dealloc action-pair
2100 struct ice_aqc_acl_generic {
2101 /* if alloc_id is below 0x1000 then alllocation failed due to
2102 * unavailable resources, else this is set by FW to identify
2108 /* to be used only in case of alloc/dealloc table */
2110 /* Index of the first TCAM block, otherwise set to 0xFF
2111 * for a failed allocation
2114 /* Index of the last TCAM block. This index shall be
2115 * set to the value of first_tcam for single TCAM block
2116 * allocation, otherwise set to 0xFF for a failed
2121 /* reserved in case of alloc/dealloc action-pair */
2127 /* index of first entry (in both TCAM and action memories),
2128 * otherwise set to 0xFF for a failed allocation
2131 /* index of last entry (in both TCAM and action memories),
2132 * otherwise set to 0xFF for a failed allocation
2136 /* Each act_mem element specifies the order of the memory
2139 u8 act_mem[ICE_AQC_MAX_ACTION_MEMORIES];
2142 /* Allocate ACL scenario (indirect 0x0C14). This command doesn't have separate
2143 * response buffer since original command buffer gets updated with
2144 * 'scen_id' in case of success
2146 struct ice_aqc_acl_alloc_scen {
2160 /* De-allocate ACL scenario (direct 0x0C15). This command doesn't need
2161 * separate response buffer since nothing to be returned as a response
2164 struct ice_aqc_acl_dealloc_scen {
2169 /* Update ACL scenario (direct 0x0C1B)
2170 * Query ACL scenario (direct 0x0C23)
2172 struct ice_aqc_acl_update_query_scen {
2179 /* Input buffer format in case allocate/update ACL scenario and same format
2180 * is used for response buffer in case of query ACL scenario.
2181 * NOTE: de-allocate ACL scenario is direct command and doesn't require
2182 * "buffer", hence no buffer format.
2184 struct ice_aqc_acl_scen {
2186 /* Byte [x] selection for the TCAM key. This value must be set
2187 * set to 0x0 for unusued TCAM.
2188 * Only Bit 6..0 is used in each byte and MSB is reserved
2190 #define ICE_AQC_ACL_ALLOC_SCE_SELECT_M 0x7F
2191 #define ICE_AQC_ACL_BYTE_SEL_BASE 0x20
2192 #define ICE_AQC_ACL_BYTE_SEL_BASE_PID 0x3E
2193 #define ICE_AQC_ACL_BYTE_SEL_BASE_PKT_DIR ICE_AQC_ACL_BYTE_SEL_BASE
2194 #define ICE_AQC_ACL_BYTE_SEL_BASE_RNG_CHK 0x3F
2196 /* TCAM Block entry masking. This value should be set to 0x0 for
2200 /* Bit 0 : masks TCAM entries 0-63
2201 * Bit 1 : masks TCAM entries 64-127
2202 * Bit 2 to 7 : follow the pattern of bit 0 and 1
2204 #define ICE_AQC_ACL_ALLOC_SCE_START_CMP BIT(0)
2205 #define ICE_AQC_ACL_ALLOC_SCE_START_SET BIT(1)
2208 } tcam_cfg[ICE_AQC_ACL_SLICES];
2210 /* Each byte, Bit 6..0: Action memory association to a TCAM block,
2211 * otherwise it shall be set to 0x0 for disabled memory action.
2212 * Bit 7 : Action memory enable for this scenario
2214 #define ICE_AQC_ACL_SCE_ACT_MEM_TCAM_ASSOC_M 0x7F
2215 #define ICE_AQC_ACL_SCE_ACT_MEM_EN BIT(7)
2216 u8 act_mem_cfg[ICE_AQC_MAX_ACTION_MEMORIES];
2219 /* Allocate ACL counters (indirect 0x0C16) */
2220 struct ice_aqc_acl_alloc_counters {
2221 /* Amount of contiguous counters requested. Min value is 1 and
2224 #define ICE_AQC_ACL_ALLOC_CNT_MIN_AMT 0x1
2225 #define ICE_AQC_ACL_ALLOC_CNT_MAX_AMT 0xFF
2228 /* Counter type: 'single counter' which can be configured to count
2229 * either bytes or packets
2231 #define ICE_AQC_ACL_CNT_TYPE_SINGLE 0x0
2233 /* Counter type: 'counter pair' which counts number of bytes and number
2236 #define ICE_AQC_ACL_CNT_TYPE_DUAL 0x1
2237 /* requested counter type, single/dual */
2240 /* counter bank allocation shall be 0-3 for 'byte or packet counter' */
2241 #define ICE_AQC_ACL_MAX_CNT_SINGLE 0x3
2242 /* counter bank allocation shall be 0-1 for 'byte and packet counter dual' */
2243 #define ICE_AQC_ACL_MAX_CNT_DUAL 0x1
2244 /* requested counter bank allocation */
2250 /* Applicable only in case of command */
2254 /* Applicable only in case of response */
2255 #define ICE_AQC_ACL_ALLOC_CNT_INVAL 0xFFFF
2257 /* Index of first allocated counter. 0xFFFF in case
2258 * of unsuccessful allocation
2260 __le16 first_counter;
2261 /* Index of last allocated counter. 0xFFFF in case
2262 * of unsuccessful allocation
2264 __le16 last_counter;
2270 /* De-allocate ACL counters (direct 0x0C17) */
2271 struct ice_aqc_acl_dealloc_counters {
2272 /* first counter being released */
2273 __le16 first_counter;
2274 /* last counter being released */
2275 __le16 last_counter;
2276 /* requested counter type, single/dual */
2278 /* requested counter bank allocation */
2283 /* De-allocate ACL resources (direct 0x0C1A). Used by SW to release all the
2284 * resources allocated for it using a single command
2286 struct ice_aqc_acl_dealloc_res {
2290 /* Program ACL actionpair (indirect 0x0C1C)
2291 * Query ACL actionpair (indirect 0x0C25)
2293 struct ice_aqc_acl_actpair {
2294 /* action mem index to program/update */
2297 /* The entry index in action memory to be programmed/updated */
2298 __le16 act_entry_index;
2304 /* Input buffer format for program/query action-pair admin command */
2305 struct ice_acl_act_entry {
2306 /* Action priority, values must be between 0..7 */
2307 #define ICE_AQC_ACT_PRIO_VALID_MAX 7
2308 #define ICE_AQC_ACT_PRIO_MSK MAKEMASK(0xff, 0)
2310 /* Action meta-data identifier. This field should be set to 0x0
2313 #define ICE_AQC_ACT_MDID_S 8
2314 #define ICE_AQC_ACT_MDID_MSK MAKEMASK(0xff00, ICE_AQC_ACT_MDID_S)
2317 #define ICE_AQC_ACT_VALUE_S 16
2318 #define ICE_AQC_ACT_VALUE_MSK MAKEMASK(0xffff0000, 16)
2322 #define ICE_ACL_NUM_ACT_PER_ACT_PAIR 2
2323 struct ice_aqc_actpair {
2324 struct ice_acl_act_entry act[ICE_ACL_NUM_ACT_PER_ACT_PAIR];
2327 /* Generic format used to describe either input or response buffer
2328 * for admin commands related to ACL profile
2330 struct ice_aqc_acl_prof_generic_frmt {
2331 /* The first byte of the byte selection base is reserved to keep the
2332 * first byte of the field vector where the packet direction info is
2333 * available. Thus we should start at index 1 of the field vector to
2334 * map its entries to the byte selection base.
2336 #define ICE_AQC_ACL_PROF_BYTE_SEL_START_IDX 1
2338 * Bit 0..5 = Byte selection for the byte selection base from the
2339 * extracted fields (expressed as byte offset in extracted fields).
2340 * Applicable values are 0..63
2341 * Bit 6..7 = Reserved
2343 #define ICE_AQC_ACL_PROF_BYTE_SEL_ELEMS 30
2344 u8 byte_selection[ICE_AQC_ACL_PROF_BYTE_SEL_ELEMS];
2346 * Bit 0..4 = Word selection for the word selection base from the
2347 * extracted fields (expressed as word offset in extracted fields).
2348 * Applicable values are 0..31
2349 * Bit 5..7 = Reserved
2351 #define ICE_AQC_ACL_PROF_WORD_SEL_ELEMS 32
2352 u8 word_selection[ICE_AQC_ACL_PROF_WORD_SEL_ELEMS];
2354 * Bit 0..3 = Double word selection for the double-word selection base
2355 * from the extracted fields (expressed as double-word offset in
2356 * extracted fields).
2357 * Applicable values are 0..15
2358 * Bit 4..7 = Reserved
2360 #define ICE_AQC_ACL_PROF_DWORD_SEL_ELEMS 15
2361 u8 dword_selection[ICE_AQC_ACL_PROF_DWORD_SEL_ELEMS];
2362 /* Scenario numbers for individual Physical Function's */
2363 #define ICE_AQC_ACL_PROF_PF_SCEN_NUM_ELEMS 8
2364 u8 pf_scenario_num[ICE_AQC_ACL_PROF_PF_SCEN_NUM_ELEMS];
2367 /* Program ACL profile extraction (indirect 0x0C1D)
2368 * Program ACL profile ranges (indirect 0x0C1E)
2369 * Query ACL profile (indirect 0x0C21)
2370 * Query ACL profile ranges (indirect 0x0C22)
2372 struct ice_aqc_acl_profile {
2373 u8 profile_id; /* Programmed/Updated profile ID */
2379 /* Input buffer format for program profile extraction admin command and
2380 * response buffer format for query profile admin command is as defined
2381 * in struct ice_aqc_acl_prof_generic_frmt
2384 /* Input buffer format for program profile ranges and query profile ranges
2385 * admin commands. Same format is used for response buffer in case of query
2386 * profile ranges command
2388 struct ice_acl_rng_data {
2389 /* The range checker output shall be sent when the value
2390 * related to this range checker is lower than low boundary
2392 __be16 low_boundary;
2393 /* The range checker output shall be sent when the value
2394 * related to this range checker is higher than high boundary
2396 __be16 high_boundary;
2397 /* A value of '0' in bit shall clear the relevant bit input
2398 * to the range checker
2403 struct ice_aqc_acl_profile_ranges {
2404 #define ICE_AQC_ACL_PROF_RANGES_NUM_CFG 8
2405 struct ice_acl_rng_data checker_cfg[ICE_AQC_ACL_PROF_RANGES_NUM_CFG];
2408 /* Program ACL entry (indirect 0x0C20)
2409 * Query ACL entry (indirect 0x0C24)
2411 struct ice_aqc_acl_entry {
2412 u8 tcam_index; /* Updated TCAM block index */
2414 __le16 entry_index; /* Updated entry index */
2420 /* Input buffer format in case of program ACL entry and response buffer format
2421 * in case of query ACL entry
2423 struct ice_aqc_acl_data {
2424 /* Entry key and entry key invert are 40 bits wide.
2425 * Byte 0..4 : entry key and Byte 5..7 are reserved
2426 * Byte 8..12: entry key invert and Byte 13..15 are reserved
2431 } entry_key, entry_key_invert;
2434 /* Query ACL counter (direct 0x0C27) */
2435 struct ice_aqc_acl_query_counter {
2436 /* Queried counter index */
2437 __le16 counter_index;
2438 /* Queried counter bank */
2445 /* Holds counter value/packet counter value */
2452 /* Add Tx LAN Queues (indirect 0x0C30) */
2453 struct ice_aqc_add_txqs {
2461 /* This is the descriptor of each queue entry for the Add Tx LAN Queues
2462 * command (0x0C30). Only used within struct ice_aqc_add_tx_qgrp.
2464 struct ice_aqc_add_txqs_perq {
2470 struct ice_aqc_txsched_elem info;
2473 /* The format of the command buffer for Add Tx LAN Queues (0x0C30)
2474 * is an array of the following structs. Please note that the length of
2475 * each struct ice_aqc_add_tx_qgrp is variable due
2476 * to the variable number of queues in each group!
2478 struct ice_aqc_add_tx_qgrp {
2482 struct ice_aqc_add_txqs_perq txqs[1];
2485 /* Disable Tx LAN Queues (indirect 0x0C31) */
2486 struct ice_aqc_dis_txqs {
2488 #define ICE_AQC_Q_DIS_CMD_S 0
2489 #define ICE_AQC_Q_DIS_CMD_M (0x3 << ICE_AQC_Q_DIS_CMD_S)
2490 #define ICE_AQC_Q_DIS_CMD_NO_FUNC_RESET (0 << ICE_AQC_Q_DIS_CMD_S)
2491 #define ICE_AQC_Q_DIS_CMD_VM_RESET BIT(ICE_AQC_Q_DIS_CMD_S)
2492 #define ICE_AQC_Q_DIS_CMD_VF_RESET (2 << ICE_AQC_Q_DIS_CMD_S)
2493 #define ICE_AQC_Q_DIS_CMD_PF_RESET (3 << ICE_AQC_Q_DIS_CMD_S)
2494 #define ICE_AQC_Q_DIS_CMD_SUBSEQ_CALL BIT(2)
2495 #define ICE_AQC_Q_DIS_CMD_FLUSH_PIPE BIT(3)
2497 __le16 vmvf_and_timeout;
2498 #define ICE_AQC_Q_DIS_VMVF_NUM_S 0
2499 #define ICE_AQC_Q_DIS_VMVF_NUM_M (0x3FF << ICE_AQC_Q_DIS_VMVF_NUM_S)
2500 #define ICE_AQC_Q_DIS_TIMEOUT_S 10
2501 #define ICE_AQC_Q_DIS_TIMEOUT_M (0x3F << ICE_AQC_Q_DIS_TIMEOUT_S)
2502 __le32 blocked_cgds;
2507 /* The buffer for Disable Tx LAN Queues (indirect 0x0C31)
2508 * contains the following structures, arrayed one after the
2510 * Note: Since the q_id is 16 bits wide, if the
2511 * number of queues is even, then 2 bytes of alignment MUST be
2512 * added before the start of the next group, to allow correct
2513 * alignment of the parent_teid field.
2515 struct ice_aqc_dis_txq_item {
2519 /* The length of the q_id array varies according to num_qs */
2521 /* This only applies from F8 onward */
2522 #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S 15
2523 #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_LAN_Q \
2524 (0 << ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S)
2525 #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_RDMA_QSET \
2526 (1 << ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S)
2529 struct ice_aqc_dis_txq {
2530 struct ice_aqc_dis_txq_item qgrps[1];
2533 /* Tx LAN Queues Cleanup Event (0x0C31) */
2534 struct ice_aqc_txqs_cleanup {
2540 /* Move / Reconfigure Tx Queues (indirect 0x0C32) */
2541 struct ice_aqc_move_txqs {
2543 #define ICE_AQC_Q_CMD_TYPE_S 0
2544 #define ICE_AQC_Q_CMD_TYPE_M (0x3 << ICE_AQC_Q_CMD_TYPE_S)
2545 #define ICE_AQC_Q_CMD_TYPE_MOVE 1
2546 #define ICE_AQC_Q_CMD_TYPE_TC_CHANGE 2
2547 #define ICE_AQC_Q_CMD_TYPE_MOVE_AND_TC 3
2548 #define ICE_AQC_Q_CMD_SUBSEQ_CALL BIT(2)
2549 #define ICE_AQC_Q_CMD_FLUSH_PIPE BIT(3)
2553 #define ICE_AQC_Q_CMD_TIMEOUT_S 2
2554 #define ICE_AQC_Q_CMD_TIMEOUT_M (0x3F << ICE_AQC_Q_CMD_TIMEOUT_S)
2555 __le32 blocked_cgds;
2560 /* Per-queue data buffer for the Move Tx LAN Queues command/response */
2561 struct ice_aqc_move_txqs_elem {
2568 /* Indirect data buffer for the Move Tx LAN Queues command/response */
2569 struct ice_aqc_move_txqs_data {
2572 struct ice_aqc_move_txqs_elem txqs[1];
2575 /* Download Package (indirect 0x0C40) */
2576 /* Also used for Update Package (indirect 0x0C42 and 0x0C41) */
2577 struct ice_aqc_download_pkg {
2579 #define ICE_AQC_DOWNLOAD_PKG_LAST_BUF 0x01
2586 struct ice_aqc_download_pkg_resp {
2587 __le32 error_offset;
2593 /* Get Package Info List (indirect 0x0C43) */
2594 struct ice_aqc_get_pkg_info_list {
2601 /* Version format for packages */
2602 struct ice_pkg_ver {
2609 #define ICE_PKG_NAME_SIZE 32
2610 #define ICE_SEG_NAME_SIZE 28
2612 struct ice_aqc_get_pkg_info {
2613 struct ice_pkg_ver ver;
2614 char name[ICE_SEG_NAME_SIZE];
2618 u8 is_active_at_boot;
2622 /* Get Package Info List response buffer format (0x0C43) */
2623 struct ice_aqc_get_pkg_info_resp {
2625 struct ice_aqc_get_pkg_info pkg_info[1];
2628 /* Driver Shared Parameters (direct, 0x0C90) */
2629 struct ice_aqc_driver_shared_params {
2631 #define ICE_AQC_DRIVER_PARAM_OP_MASK BIT(0)
2632 #define ICE_AQC_DRIVER_PARAM_SET 0
2633 #define ICE_AQC_DRIVER_PARAM_GET 1
2635 #define ICE_AQC_DRIVER_PARAM_MAX_IDX 15
2642 /* Lan Queue Overflow Event (direct, 0x1001) */
2643 struct ice_aqc_event_lan_overflow {
2644 __le32 prtdcb_ruptq;
2649 /* Set Health Status (direct 0xFF20) */
2650 struct ice_aqc_set_health_status_config {
2652 #define ICE_AQC_HEALTH_STATUS_SET_PF_SPECIFIC_MASK BIT(0)
2653 #define ICE_AQC_HEALTH_STATUS_SET_ALL_PF_MASK BIT(1)
2654 #define ICE_AQC_HEALTH_STATUS_SET_GLOBAL_MASK BIT(2)
2658 /* Get Health Status codes (indirect 0xFF21) */
2659 struct ice_aqc_get_supported_health_status_codes {
2660 __le16 health_code_count;
2666 /* Get Health Status (indirect 0xFF22) */
2667 struct ice_aqc_get_health_status {
2668 __le16 health_status_count;
2674 /* Get Health Status event buffer entry, (0xFF22)
2675 * repeated per reported health status
2677 struct ice_aqc_health_status_elem {
2678 __le16 health_status_code;
2679 __le16 event_source;
2680 #define ICE_AQC_HEALTH_STATUS_PF (0x1)
2681 #define ICE_AQC_HEALTH_STATUS_PORT (0x2)
2682 #define ICE_AQC_HEALTH_STATUS_GLOBAL (0x3)
2683 __le32 internal_data1;
2684 #define ICE_AQC_HEALTH_STATUS_UNDEFINED_DATA (0xDEADBEEF)
2685 __le32 internal_data2;
2688 /* Clear Health Status (direct 0xFF23) */
2689 struct ice_aqc_clear_health_status {
2694 * struct ice_aq_desc - Admin Queue (AQ) descriptor
2695 * @flags: ICE_AQ_FLAG_* flags
2696 * @opcode: AQ command opcode
2697 * @datalen: length in bytes of indirect/external data buffer
2698 * @retval: return value from firmware
2699 * @cookie_h: opaque data high-half
2700 * @cookie_l: opaque data low-half
2701 * @params: command-specific parameters
2703 * Descriptor format for commands the driver posts on the Admin Transmit Queue
2704 * (ATQ). The firmware writes back onto the command descriptor and returns
2705 * the result of the command. Asynchronous events that are not an immediate
2706 * result of the command are written to the Admin Receive Queue (ARQ) using
2707 * the same descriptor format. Descriptors are in little-endian notation with
2710 struct ice_aq_desc {
2719 struct ice_aqc_generic generic;
2720 struct ice_aqc_get_ver get_ver;
2721 struct ice_aqc_driver_ver driver_ver;
2722 struct ice_aqc_q_shutdown q_shutdown;
2723 struct ice_aqc_req_res res_owner;
2724 struct ice_aqc_manage_mac_read mac_read;
2725 struct ice_aqc_manage_mac_write mac_write;
2726 struct ice_aqc_clear_pxe clear_pxe;
2727 struct ice_aqc_config_no_drop_policy no_drop;
2728 struct ice_aqc_add_update_mir_rule add_update_rule;
2729 struct ice_aqc_delete_mir_rule del_rule;
2730 struct ice_aqc_list_caps get_cap;
2731 struct ice_aqc_get_phy_caps get_phy;
2732 struct ice_aqc_set_phy_cfg set_phy;
2733 struct ice_aqc_restart_an restart_an;
2734 struct ice_aqc_sff_eeprom read_write_sff_param;
2735 struct ice_aqc_set_port_id_led set_port_id_led;
2736 struct ice_aqc_get_sw_cfg get_sw_conf;
2737 struct ice_aqc_sw_rules sw_rules;
2738 struct ice_aqc_storm_cfg storm_conf;
2739 struct ice_aqc_add_get_recipe add_get_recipe;
2740 struct ice_aqc_recipe_to_profile recipe_to_profile;
2741 struct ice_aqc_get_topo get_topo;
2742 struct ice_aqc_sched_elem_cmd sched_elem_cmd;
2743 struct ice_aqc_query_txsched_res query_sched_res;
2744 struct ice_aqc_query_node_to_root query_node_to_root;
2745 struct ice_aqc_cfg_l2_node_cgd cfg_l2_node_cgd;
2746 struct ice_aqc_query_port_ets port_ets;
2747 struct ice_aqc_rl_profile rl_profile;
2748 struct ice_aqc_nvm nvm;
2749 struct ice_aqc_nvm_cfg nvm_cfg;
2750 struct ice_aqc_nvm_checksum nvm_checksum;
2751 struct ice_aqc_pfc_ignore pfc_ignore;
2752 struct ice_aqc_set_query_pfc_mode set_query_pfc_mode;
2753 struct ice_aqc_set_dcb_params set_dcb_params;
2754 struct ice_aqc_lldp_get_mib lldp_get_mib;
2755 struct ice_aqc_lldp_set_mib_change lldp_set_event;
2756 struct ice_aqc_lldp_add_delete_tlv lldp_add_delete_tlv;
2757 struct ice_aqc_lldp_update_tlv lldp_update_tlv;
2758 struct ice_aqc_lldp_stop lldp_stop;
2759 struct ice_aqc_lldp_start lldp_start;
2760 struct ice_aqc_lldp_set_local_mib lldp_set_mib;
2761 struct ice_aqc_lldp_stop_start_specific_agent lldp_agent_ctrl;
2762 struct ice_aqc_lldp_filter_ctrl lldp_filter_ctrl;
2763 struct ice_aqc_get_set_rss_lut get_set_rss_lut;
2764 struct ice_aqc_get_set_rss_key get_set_rss_key;
2765 struct ice_aqc_clear_fd_table clear_fd_table;
2766 struct ice_aqc_acl_alloc_table alloc_table;
2767 struct ice_aqc_acl_tbl_actpair tbl_actpair;
2768 struct ice_aqc_acl_alloc_scen alloc_scen;
2769 struct ice_aqc_acl_dealloc_scen dealloc_scen;
2770 struct ice_aqc_acl_update_query_scen update_query_scen;
2771 struct ice_aqc_acl_alloc_counters alloc_counters;
2772 struct ice_aqc_acl_dealloc_counters dealloc_counters;
2773 struct ice_aqc_acl_dealloc_res dealloc_res;
2774 struct ice_aqc_acl_entry program_query_entry;
2775 struct ice_aqc_acl_actpair program_query_actpair;
2776 struct ice_aqc_acl_profile profile;
2777 struct ice_aqc_acl_query_counter query_counter;
2778 struct ice_aqc_add_txqs add_txqs;
2779 struct ice_aqc_dis_txqs dis_txqs;
2780 struct ice_aqc_move_txqs move_txqs;
2781 struct ice_aqc_txqs_cleanup txqs_cleanup;
2782 struct ice_aqc_add_get_update_free_vsi vsi_cmd;
2783 struct ice_aqc_add_update_free_vsi_resp add_update_free_vsi_res;
2784 struct ice_aqc_get_vsi_resp get_vsi_resp;
2785 struct ice_aqc_download_pkg download_pkg;
2786 struct ice_aqc_get_pkg_info_list get_pkg_info_list;
2787 struct ice_aqc_driver_shared_params drv_shared_params;
2788 struct ice_aqc_set_mac_lb set_mac_lb;
2789 struct ice_aqc_alloc_free_res_cmd sw_res_ctrl;
2790 struct ice_aqc_get_res_alloc get_res;
2791 struct ice_aqc_get_allocd_res_desc get_res_desc;
2792 struct ice_aqc_set_mac_cfg set_mac_cfg;
2793 struct ice_aqc_set_event_mask set_event_mask;
2794 struct ice_aqc_get_link_status get_link_status;
2795 struct ice_aqc_event_lan_overflow lan_overflow;
2796 struct ice_aqc_get_link_topo get_link_topo;
2797 struct ice_aqc_set_health_status_config
2798 set_health_status_config;
2799 struct ice_aqc_get_supported_health_status_codes
2800 get_supported_health_status_codes;
2801 struct ice_aqc_get_health_status get_health_status;
2802 struct ice_aqc_clear_health_status clear_health_status;
2806 /* FW defined boundary for a large buffer, 4k >= Large buffer > 512 bytes */
2807 #define ICE_AQ_LG_BUF 512
2809 /* Flags sub-structure
2810 * |0 |1 |2 |3 |4 |5 |6 |7 |8 |9 |10 |11 |12 |13 |14 |15 |
2811 * |DD |CMP|ERR|VFE| * * RESERVED * * |LB |RD |VFC|BUF|SI |EI |FE |
2814 /* command flags and offsets */
2815 #define ICE_AQ_FLAG_DD_S 0
2816 #define ICE_AQ_FLAG_CMP_S 1
2817 #define ICE_AQ_FLAG_ERR_S 2
2818 #define ICE_AQ_FLAG_VFE_S 3
2819 #define ICE_AQ_FLAG_LB_S 9
2820 #define ICE_AQ_FLAG_RD_S 10
2821 #define ICE_AQ_FLAG_VFC_S 11
2822 #define ICE_AQ_FLAG_BUF_S 12
2823 #define ICE_AQ_FLAG_SI_S 13
2824 #define ICE_AQ_FLAG_EI_S 14
2825 #define ICE_AQ_FLAG_FE_S 15
2827 #define ICE_AQ_FLAG_DD BIT(ICE_AQ_FLAG_DD_S) /* 0x1 */
2828 #define ICE_AQ_FLAG_CMP BIT(ICE_AQ_FLAG_CMP_S) /* 0x2 */
2829 #define ICE_AQ_FLAG_ERR BIT(ICE_AQ_FLAG_ERR_S) /* 0x4 */
2830 #define ICE_AQ_FLAG_VFE BIT(ICE_AQ_FLAG_VFE_S) /* 0x8 */
2831 #define ICE_AQ_FLAG_LB BIT(ICE_AQ_FLAG_LB_S) /* 0x200 */
2832 #define ICE_AQ_FLAG_RD BIT(ICE_AQ_FLAG_RD_S) /* 0x400 */
2833 #define ICE_AQ_FLAG_VFC BIT(ICE_AQ_FLAG_VFC_S) /* 0x800 */
2834 #define ICE_AQ_FLAG_BUF BIT(ICE_AQ_FLAG_BUF_S) /* 0x1000 */
2835 #define ICE_AQ_FLAG_SI BIT(ICE_AQ_FLAG_SI_S) /* 0x2000 */
2836 #define ICE_AQ_FLAG_EI BIT(ICE_AQ_FLAG_EI_S) /* 0x4000 */
2837 #define ICE_AQ_FLAG_FE BIT(ICE_AQ_FLAG_FE_S) /* 0x8000 */
2841 ICE_AQ_RC_OK = 0, /* Success */
2842 ICE_AQ_RC_EPERM = 1, /* Operation not permitted */
2843 ICE_AQ_RC_ENOENT = 2, /* No such element */
2844 ICE_AQ_RC_ESRCH = 3, /* Bad opcode */
2845 ICE_AQ_RC_EINTR = 4, /* Operation interrupted */
2846 ICE_AQ_RC_EIO = 5, /* I/O error */
2847 ICE_AQ_RC_ENXIO = 6, /* No such resource */
2848 ICE_AQ_RC_E2BIG = 7, /* Arg too long */
2849 ICE_AQ_RC_EAGAIN = 8, /* Try again */
2850 ICE_AQ_RC_ENOMEM = 9, /* Out of memory */
2851 ICE_AQ_RC_EACCES = 10, /* Permission denied */
2852 ICE_AQ_RC_EFAULT = 11, /* Bad address */
2853 ICE_AQ_RC_EBUSY = 12, /* Device or resource busy */
2854 ICE_AQ_RC_EEXIST = 13, /* Object already exists */
2855 ICE_AQ_RC_EINVAL = 14, /* Invalid argument */
2856 ICE_AQ_RC_ENOTTY = 15, /* Not a typewriter */
2857 ICE_AQ_RC_ENOSPC = 16, /* No space left or allocation failure */
2858 ICE_AQ_RC_ENOSYS = 17, /* Function not implemented */
2859 ICE_AQ_RC_ERANGE = 18, /* Parameter out of range */
2860 ICE_AQ_RC_EFLUSHED = 19, /* Cmd flushed due to prev cmd error */
2861 ICE_AQ_RC_BAD_ADDR = 20, /* Descriptor contains a bad pointer */
2862 ICE_AQ_RC_EMODE = 21, /* Op not allowed in current dev mode */
2863 ICE_AQ_RC_EFBIG = 22, /* File too big */
2864 ICE_AQ_RC_ESBCOMP = 23, /* SB-IOSF completion unsuccessful */
2865 ICE_AQ_RC_ENOSEC = 24, /* Missing security manifest */
2866 ICE_AQ_RC_EBADSIG = 25, /* Bad RSA signature */
2867 ICE_AQ_RC_ESVN = 26, /* SVN number prohibits this package */
2868 ICE_AQ_RC_EBADMAN = 27, /* Manifest hash mismatch */
2869 ICE_AQ_RC_EBADBUF = 28, /* Buffer hash mismatches manifest */
2870 ICE_AQ_RC_EACCES_BMCU = 29, /* BMC Update in progress */
2873 /* Admin Queue command opcodes */
2874 enum ice_adminq_opc {
2876 ice_aqc_opc_get_ver = 0x0001,
2877 ice_aqc_opc_driver_ver = 0x0002,
2878 ice_aqc_opc_q_shutdown = 0x0003,
2879 ice_aqc_opc_get_exp_err = 0x0005,
2881 /* resource ownership */
2882 ice_aqc_opc_req_res = 0x0008,
2883 ice_aqc_opc_release_res = 0x0009,
2885 /* device/function capabilities */
2886 ice_aqc_opc_list_func_caps = 0x000A,
2887 ice_aqc_opc_list_dev_caps = 0x000B,
2889 /* manage MAC address */
2890 ice_aqc_opc_manage_mac_read = 0x0107,
2891 ice_aqc_opc_manage_mac_write = 0x0108,
2894 ice_aqc_opc_clear_pxe_mode = 0x0110,
2896 ice_aqc_opc_config_no_drop_policy = 0x0112,
2898 /* internal switch commands */
2899 ice_aqc_opc_get_sw_cfg = 0x0200,
2901 /* Alloc/Free/Get Resources */
2902 ice_aqc_opc_get_res_alloc = 0x0204,
2903 ice_aqc_opc_alloc_res = 0x0208,
2904 ice_aqc_opc_free_res = 0x0209,
2905 ice_aqc_opc_get_allocd_res_desc = 0x020A,
2908 ice_aqc_opc_add_vsi = 0x0210,
2909 ice_aqc_opc_update_vsi = 0x0211,
2910 ice_aqc_opc_get_vsi_params = 0x0212,
2911 ice_aqc_opc_free_vsi = 0x0213,
2913 /* Mirroring rules - add/update, delete */
2914 ice_aqc_opc_add_update_mir_rule = 0x0260,
2915 ice_aqc_opc_del_mir_rule = 0x0261,
2917 /* storm configuration */
2918 ice_aqc_opc_set_storm_cfg = 0x0280,
2919 ice_aqc_opc_get_storm_cfg = 0x0281,
2921 /* recipe commands */
2922 ice_aqc_opc_add_recipe = 0x0290,
2923 ice_aqc_opc_recipe_to_profile = 0x0291,
2924 ice_aqc_opc_get_recipe = 0x0292,
2925 ice_aqc_opc_get_recipe_to_profile = 0x0293,
2927 /* switch rules population commands */
2928 ice_aqc_opc_add_sw_rules = 0x02A0,
2929 ice_aqc_opc_update_sw_rules = 0x02A1,
2930 ice_aqc_opc_remove_sw_rules = 0x02A2,
2931 ice_aqc_opc_get_sw_rules = 0x02A3,
2932 ice_aqc_opc_clear_pf_cfg = 0x02A4,
2935 ice_aqc_opc_pfc_ignore = 0x0301,
2936 ice_aqc_opc_query_pfc_mode = 0x0302,
2937 ice_aqc_opc_set_pfc_mode = 0x0303,
2938 ice_aqc_opc_set_dcb_params = 0x0306,
2940 /* transmit scheduler commands */
2941 ice_aqc_opc_get_dflt_topo = 0x0400,
2942 ice_aqc_opc_add_sched_elems = 0x0401,
2943 ice_aqc_opc_cfg_sched_elems = 0x0403,
2944 ice_aqc_opc_get_sched_elems = 0x0404,
2945 ice_aqc_opc_move_sched_elems = 0x0408,
2946 ice_aqc_opc_suspend_sched_elems = 0x0409,
2947 ice_aqc_opc_resume_sched_elems = 0x040A,
2948 ice_aqc_opc_query_port_ets = 0x040E,
2949 ice_aqc_opc_delete_sched_elems = 0x040F,
2950 ice_aqc_opc_add_rl_profiles = 0x0410,
2951 ice_aqc_opc_query_rl_profiles = 0x0411,
2952 ice_aqc_opc_query_sched_res = 0x0412,
2953 ice_aqc_opc_query_node_to_root = 0x0413,
2954 ice_aqc_opc_cfg_l2_node_cgd = 0x0414,
2955 ice_aqc_opc_remove_rl_profiles = 0x0415,
2958 ice_aqc_opc_get_phy_caps = 0x0600,
2959 ice_aqc_opc_set_phy_cfg = 0x0601,
2960 ice_aqc_opc_set_mac_cfg = 0x0603,
2961 ice_aqc_opc_restart_an = 0x0605,
2962 ice_aqc_opc_get_link_status = 0x0607,
2963 ice_aqc_opc_set_event_mask = 0x0613,
2964 ice_aqc_opc_set_mac_lb = 0x0620,
2965 ice_aqc_opc_get_link_topo = 0x06E0,
2966 ice_aqc_opc_set_port_id_led = 0x06E9,
2967 ice_aqc_opc_get_port_options = 0x06EA,
2968 ice_aqc_opc_set_port_option = 0x06EB,
2969 ice_aqc_opc_set_gpio = 0x06EC,
2970 ice_aqc_opc_get_gpio = 0x06ED,
2971 ice_aqc_opc_sff_eeprom = 0x06EE,
2974 ice_aqc_opc_nvm_read = 0x0701,
2975 ice_aqc_opc_nvm_erase = 0x0702,
2976 ice_aqc_opc_nvm_write = 0x0703,
2977 ice_aqc_opc_nvm_cfg_read = 0x0704,
2978 ice_aqc_opc_nvm_cfg_write = 0x0705,
2979 ice_aqc_opc_nvm_checksum = 0x0706,
2980 ice_aqc_opc_nvm_write_activate = 0x0707,
2981 ice_aqc_opc_nvm_sr_dump = 0x0707,
2982 ice_aqc_opc_nvm_save_factory_settings = 0x0708,
2983 ice_aqc_opc_nvm_update_empr = 0x0709,
2986 ice_aqc_opc_lldp_get_mib = 0x0A00,
2987 ice_aqc_opc_lldp_set_mib_change = 0x0A01,
2988 ice_aqc_opc_lldp_add_tlv = 0x0A02,
2989 ice_aqc_opc_lldp_update_tlv = 0x0A03,
2990 ice_aqc_opc_lldp_delete_tlv = 0x0A04,
2991 ice_aqc_opc_lldp_stop = 0x0A05,
2992 ice_aqc_opc_lldp_start = 0x0A06,
2993 ice_aqc_opc_get_cee_dcb_cfg = 0x0A07,
2994 ice_aqc_opc_lldp_set_local_mib = 0x0A08,
2995 ice_aqc_opc_lldp_stop_start_specific_agent = 0x0A09,
2996 ice_aqc_opc_lldp_filter_ctrl = 0x0A0A,
2999 ice_aqc_opc_set_rss_key = 0x0B02,
3000 ice_aqc_opc_set_rss_lut = 0x0B03,
3001 ice_aqc_opc_get_rss_key = 0x0B04,
3002 ice_aqc_opc_get_rss_lut = 0x0B05,
3003 ice_aqc_opc_clear_fd_table = 0x0B06,
3005 ice_aqc_opc_alloc_acl_tbl = 0x0C10,
3006 ice_aqc_opc_dealloc_acl_tbl = 0x0C11,
3007 ice_aqc_opc_alloc_acl_actpair = 0x0C12,
3008 ice_aqc_opc_dealloc_acl_actpair = 0x0C13,
3009 ice_aqc_opc_alloc_acl_scen = 0x0C14,
3010 ice_aqc_opc_dealloc_acl_scen = 0x0C15,
3011 ice_aqc_opc_alloc_acl_counters = 0x0C16,
3012 ice_aqc_opc_dealloc_acl_counters = 0x0C17,
3013 ice_aqc_opc_dealloc_acl_res = 0x0C1A,
3014 ice_aqc_opc_update_acl_scen = 0x0C1B,
3015 ice_aqc_opc_program_acl_actpair = 0x0C1C,
3016 ice_aqc_opc_program_acl_prof_extraction = 0x0C1D,
3017 ice_aqc_opc_program_acl_prof_ranges = 0x0C1E,
3018 ice_aqc_opc_program_acl_entry = 0x0C20,
3019 ice_aqc_opc_query_acl_prof = 0x0C21,
3020 ice_aqc_opc_query_acl_prof_ranges = 0x0C22,
3021 ice_aqc_opc_query_acl_scen = 0x0C23,
3022 ice_aqc_opc_query_acl_entry = 0x0C24,
3023 ice_aqc_opc_query_acl_actpair = 0x0C25,
3024 ice_aqc_opc_query_acl_counter = 0x0C27,
3026 /* Tx queue handling commands/events */
3027 ice_aqc_opc_add_txqs = 0x0C30,
3028 ice_aqc_opc_dis_txqs = 0x0C31,
3029 ice_aqc_opc_txqs_cleanup = 0x0C31,
3030 ice_aqc_opc_move_recfg_txqs = 0x0C32,
3032 /* package commands */
3033 ice_aqc_opc_download_pkg = 0x0C40,
3034 ice_aqc_opc_upload_section = 0x0C41,
3035 ice_aqc_opc_update_pkg = 0x0C42,
3036 ice_aqc_opc_get_pkg_info_list = 0x0C43,
3038 ice_aqc_opc_driver_shared_params = 0x0C90,
3040 /* Standalone Commands/Events */
3041 ice_aqc_opc_event_lan_overflow = 0x1001,
3043 /* SystemDiagnostic commands */
3044 ice_aqc_opc_set_health_status_config = 0xFF20,
3045 ice_aqc_opc_get_supported_health_status_codes = 0xFF21,
3046 ice_aqc_opc_get_health_status = 0xFF22,
3047 ice_aqc_opc_clear_health_status = 0xFF23
3050 #endif /* _ICE_ADMINQ_CMD_H_ */