1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2001-2021 Intel Corporation
5 #ifndef _ICE_ADMINQ_CMD_H_
6 #define _ICE_ADMINQ_CMD_H_
8 /* This header file defines the Admin Queue commands, error codes and
9 * descriptor format. It is shared between Firmware and Software.
12 #define ICE_MAX_VSI 768
13 #define ICE_AQC_TOPO_MAX_LEVEL_NUM 0x9
14 #define ICE_AQ_SET_MAC_FRAME_SIZE_MAX 9728
16 struct ice_aqc_generic {
23 /* Get version (direct 0x0001) */
24 struct ice_aqc_get_ver {
37 /* Send driver version (indirect 0x0002) */
38 struct ice_aqc_driver_ver {
48 /* Queue Shutdown (direct 0x0003) */
49 struct ice_aqc_q_shutdown {
51 #define ICE_AQC_DRIVER_UNLOADING BIT(0)
55 /* Request resource ownership (direct 0x0008)
56 * Release resource ownership (direct 0x0009)
58 struct ice_aqc_req_res {
60 #define ICE_AQC_RES_ID_NVM 1
61 #define ICE_AQC_RES_ID_SDP 2
62 #define ICE_AQC_RES_ID_CHNG_LOCK 3
63 #define ICE_AQC_RES_ID_GLBL_LOCK 4
65 #define ICE_AQC_RES_ACCESS_READ 1
66 #define ICE_AQC_RES_ACCESS_WRITE 2
68 /* Upon successful completion, FW writes this value and driver is
69 * expected to release resource before timeout. This value is provided
73 #define ICE_AQ_RES_NVM_READ_DFLT_TIMEOUT_MS 3000
74 #define ICE_AQ_RES_NVM_WRITE_DFLT_TIMEOUT_MS 180000
75 #define ICE_AQ_RES_CHNG_LOCK_DFLT_TIMEOUT_MS 1000
76 #define ICE_AQ_RES_GLBL_LOCK_DFLT_TIMEOUT_MS 3000
77 /* For SDP: pin ID of the SDP */
79 /* Status is only used for ICE_AQC_RES_ID_GLBL_LOCK */
81 #define ICE_AQ_RES_GLBL_SUCCESS 0
82 #define ICE_AQ_RES_GLBL_IN_PROG 1
83 #define ICE_AQ_RES_GLBL_DONE 2
87 /* Get function capabilities (indirect 0x000A)
88 * Get device capabilities (indirect 0x000B)
90 struct ice_aqc_list_caps {
99 /* Device/Function buffer entry, repeated per reported capability */
100 struct ice_aqc_list_caps_elem {
102 #define ICE_AQC_CAPS_VALID_FUNCTIONS 0x0005
103 #define ICE_AQC_MAX_VALID_FUNCTIONS 0x8
104 #define ICE_AQC_CAPS_VSI 0x0017
105 #define ICE_AQC_CAPS_DCB 0x0018
106 #define ICE_AQC_CAPS_RSS 0x0040
107 #define ICE_AQC_CAPS_RXQS 0x0041
108 #define ICE_AQC_CAPS_TXQS 0x0042
109 #define ICE_AQC_CAPS_MSIX 0x0043
110 #define ICE_AQC_CAPS_FD 0x0045
111 #define ICE_AQC_CAPS_1588 0x0046
112 #define ICE_AQC_CAPS_MAX_MTU 0x0047
113 #define ICE_AQC_CAPS_IWARP 0x0051
114 #define ICE_AQC_CAPS_PCIE_RESET_AVOIDANCE 0x0076
115 #define ICE_AQC_CAPS_POST_UPDATE_RESET_RESTRICT 0x0077
116 #define ICE_AQC_CAPS_NVM_MGMT 0x0080
117 #define ICE_AQC_CAPS_EXT_TOPO_DEV_IMG0 0x0081
118 #define ICE_AQC_CAPS_EXT_TOPO_DEV_IMG1 0x0082
119 #define ICE_AQC_CAPS_EXT_TOPO_DEV_IMG2 0x0083
120 #define ICE_AQC_CAPS_EXT_TOPO_DEV_IMG3 0x0084
124 /* Number of resources described by this capability */
126 /* Only meaningful for some types of resources */
128 /* Only meaningful for some types of resources */
134 /* Manage MAC address, read command - indirect (0x0107)
135 * This struct is also used for the response
137 struct ice_aqc_manage_mac_read {
138 __le16 flags; /* Zeroed by device driver */
139 #define ICE_AQC_MAN_MAC_LAN_ADDR_VALID BIT(4)
140 #define ICE_AQC_MAN_MAC_SAN_ADDR_VALID BIT(5)
141 #define ICE_AQC_MAN_MAC_PORT_ADDR_VALID BIT(6)
142 #define ICE_AQC_MAN_MAC_WOL_ADDR_VALID BIT(7)
143 #define ICE_AQC_MAN_MAC_MC_MAG_EN BIT(8)
144 #define ICE_AQC_MAN_MAC_WOL_PRESERVE_ON_PFR BIT(9)
145 #define ICE_AQC_MAN_MAC_READ_S 4
146 #define ICE_AQC_MAN_MAC_READ_M (0xF << ICE_AQC_MAN_MAC_READ_S)
148 u8 num_addr; /* Used in response */
154 /* Response buffer format for manage MAC read command */
155 struct ice_aqc_manage_mac_read_resp {
158 #define ICE_AQC_MAN_MAC_ADDR_TYPE_LAN 0
159 #define ICE_AQC_MAN_MAC_ADDR_TYPE_WOL 1
160 u8 mac_addr[ETH_ALEN];
163 /* Manage MAC address, write command - direct (0x0108) */
164 struct ice_aqc_manage_mac_write {
167 #define ICE_AQC_MAN_MAC_WR_MC_MAG_EN BIT(0)
168 #define ICE_AQC_MAN_MAC_WR_WOL_LAA_PFR_KEEP BIT(1)
169 #define ICE_AQC_MAN_MAC_WR_S 6
170 #define ICE_AQC_MAN_MAC_WR_M MAKEMASK(3, ICE_AQC_MAN_MAC_WR_S)
171 #define ICE_AQC_MAN_MAC_UPDATE_LAA 0
172 #define ICE_AQC_MAN_MAC_UPDATE_LAA_WOL BIT(ICE_AQC_MAN_MAC_WR_S)
173 /* byte stream in network order */
174 u8 mac_addr[ETH_ALEN];
179 /* Clear PXE Command and response (direct 0x0110) */
180 struct ice_aqc_clear_pxe {
182 #define ICE_AQC_CLEAR_PXE_RX_CNT 0x2
186 /* Configure No-Drop Policy Command (direct 0x0112) */
187 struct ice_aqc_config_no_drop_policy {
189 #define ICE_AQC_FORCE_NO_DROP BIT(0)
193 /* Get switch configuration (0x0200) */
194 struct ice_aqc_get_sw_cfg {
195 /* Reserved for command and copy of request flags for response */
197 /* First desc in case of command and next_elem in case of response
198 * In case of response, if it is not zero, means all the configuration
199 * was not returned and new command shall be sent with this value in
200 * the 'first desc' field
203 /* Reserved for command, only used for response */
210 /* Each entry in the response buffer is of the following type: */
211 struct ice_aqc_get_sw_cfg_resp_elem {
212 /* VSI/Port Number */
214 #define ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_S 0
215 #define ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_M \
216 (0x3FF << ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_S)
217 #define ICE_AQC_GET_SW_CONF_RESP_TYPE_S 14
218 #define ICE_AQC_GET_SW_CONF_RESP_TYPE_M (0x3 << ICE_AQC_GET_SW_CONF_RESP_TYPE_S)
219 #define ICE_AQC_GET_SW_CONF_RESP_PHYS_PORT 0
220 #define ICE_AQC_GET_SW_CONF_RESP_VIRT_PORT 1
221 #define ICE_AQC_GET_SW_CONF_RESP_VSI 2
223 /* SWID VSI/Port belongs to */
226 /* Bit 14..0 : PF/VF number VSI belongs to
227 * Bit 15 : VF indication bit
230 #define ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_S 0
231 #define ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_M \
232 (0x7FFF << ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_S)
233 #define ICE_AQC_GET_SW_CONF_RESP_IS_VF BIT(15)
236 /* Set Port parameters, (direct, 0x0203) */
237 struct ice_aqc_set_port_params {
239 #define ICE_AQC_SET_P_PARAMS_SAVE_BAD_PACKETS BIT(0)
240 #define ICE_AQC_SET_P_PARAMS_PAD_SHORT_PACKETS BIT(1)
241 #define ICE_AQC_SET_P_PARAMS_DOUBLE_VLAN_ENA BIT(2)
242 __le16 bad_frame_vsi;
243 #define ICE_AQC_SET_P_PARAMS_VSI_S 0
244 #define ICE_AQC_SET_P_PARAMS_VSI_M (0x3FF << ICE_AQC_SET_P_PARAMS_VSI_S)
245 #define ICE_AQC_SET_P_PARAMS_VSI_VALID BIT(15)
247 #define ICE_AQC_SET_P_PARAMS_SWID_S 0
248 #define ICE_AQC_SET_P_PARAMS_SWID_M (0xFF << ICE_AQC_SET_P_PARAMS_SWID_S)
249 #define ICE_AQC_SET_P_PARAMS_LOGI_PORT_ID_S 8
250 #define ICE_AQC_SET_P_PARAMS_LOGI_PORT_ID_M \
251 (0x3F << ICE_AQC_SET_P_PARAMS_LOGI_PORT_ID_S)
252 #define ICE_AQC_SET_P_PARAMS_IS_LOGI_PORT BIT(14)
253 #define ICE_AQC_SET_P_PARAMS_SWID_VALID BIT(15)
257 /* These resource type defines are used for all switch resource
258 * commands where a resource type is required, such as:
259 * Get Resource Allocation command (indirect 0x0204)
260 * Allocate Resources command (indirect 0x0208)
261 * Free Resources command (indirect 0x0209)
262 * Get Allocated Resource Descriptors Command (indirect 0x020A)
264 #define ICE_AQC_RES_TYPE_VEB_COUNTER 0x00
265 #define ICE_AQC_RES_TYPE_VLAN_COUNTER 0x01
266 #define ICE_AQC_RES_TYPE_MIRROR_RULE 0x02
267 #define ICE_AQC_RES_TYPE_VSI_LIST_REP 0x03
268 #define ICE_AQC_RES_TYPE_VSI_LIST_PRUNE 0x04
269 #define ICE_AQC_RES_TYPE_RECIPE 0x05
270 #define ICE_AQC_RES_TYPE_PROFILE 0x06
271 #define ICE_AQC_RES_TYPE_SWID 0x07
272 #define ICE_AQC_RES_TYPE_VSI 0x08
273 #define ICE_AQC_RES_TYPE_FLU 0x09
274 #define ICE_AQC_RES_TYPE_WIDE_TABLE_1 0x0A
275 #define ICE_AQC_RES_TYPE_WIDE_TABLE_2 0x0B
276 #define ICE_AQC_RES_TYPE_WIDE_TABLE_4 0x0C
277 #define ICE_AQC_RES_TYPE_GLOBAL_RSS_HASH 0x20
278 #define ICE_AQC_RES_TYPE_FDIR_COUNTER_BLOCK 0x21
279 #define ICE_AQC_RES_TYPE_FDIR_GUARANTEED_ENTRIES 0x22
280 #define ICE_AQC_RES_TYPE_FDIR_SHARED_ENTRIES 0x23
281 #define ICE_AQC_RES_TYPE_FLEX_DESC_PROG 0x30
282 #define ICE_AQC_RES_TYPE_SWITCH_PROF_BLDR_PROFID 0x48
283 #define ICE_AQC_RES_TYPE_SWITCH_PROF_BLDR_TCAM 0x49
284 #define ICE_AQC_RES_TYPE_ACL_PROF_BLDR_PROFID 0x50
285 #define ICE_AQC_RES_TYPE_ACL_PROF_BLDR_TCAM 0x51
286 #define ICE_AQC_RES_TYPE_FD_PROF_BLDR_PROFID 0x58
287 #define ICE_AQC_RES_TYPE_FD_PROF_BLDR_TCAM 0x59
288 #define ICE_AQC_RES_TYPE_HASH_PROF_BLDR_PROFID 0x60
289 #define ICE_AQC_RES_TYPE_HASH_PROF_BLDR_TCAM 0x61
290 /* Resource types 0x62-67 are reserved for Hash profile builder */
291 #define ICE_AQC_RES_TYPE_QHASH_PROF_BLDR_PROFID 0x68
292 #define ICE_AQC_RES_TYPE_QHASH_PROF_BLDR_TCAM 0x69
294 #define ICE_AQC_RES_TYPE_FLAG_SHARED BIT(7)
295 #define ICE_AQC_RES_TYPE_FLAG_SCAN_BOTTOM BIT(12)
296 #define ICE_AQC_RES_TYPE_FLAG_IGNORE_INDEX BIT(13)
298 #define ICE_AQC_RES_TYPE_FLAG_DEDICATED 0x00
300 #define ICE_AQC_RES_TYPE_S 0
301 #define ICE_AQC_RES_TYPE_M (0x07F << ICE_AQC_RES_TYPE_S)
303 /* Get Resource Allocation command (indirect 0x0204) */
304 struct ice_aqc_get_res_alloc {
305 __le16 resp_elem_num; /* Used in response, reserved in command */
311 /* Get Resource Allocation Response Buffer per response */
312 struct ice_aqc_get_res_resp_elem {
313 __le16 res_type; /* Types defined above cmd 0x0204 */
314 __le16 total_capacity; /* Resources available to all PF's */
315 __le16 total_function; /* Resources allocated for a PF */
316 __le16 total_shared; /* Resources allocated as shared */
317 __le16 total_free; /* Resources un-allocated/not reserved by any PF */
320 /* Allocate Resources command (indirect 0x0208)
321 * Free Resources command (indirect 0x0209)
323 struct ice_aqc_alloc_free_res_cmd {
324 __le16 num_entries; /* Number of Resource entries */
330 /* Resource descriptor */
331 struct ice_aqc_res_elem {
338 /* Buffer for Allocate/Free Resources commands */
339 struct ice_aqc_alloc_free_res_elem {
340 __le16 res_type; /* Types defined above cmd 0x0204 */
341 #define ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_S 8
342 #define ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_M \
343 (0xF << ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_S)
345 struct ice_aqc_res_elem elem[STRUCT_HACK_VAR_LEN];
348 /* Get Allocated Resource Descriptors Command (indirect 0x020A) */
349 struct ice_aqc_get_allocd_res_desc {
352 __le16 res; /* Types defined above cmd 0x0204 */
367 /* Request buffer for Set VLAN Mode AQ command (indirect 0x020C) */
368 struct ice_aqc_set_vlan_mode {
370 u8 l2tag_prio_tagging;
371 #define ICE_AQ_VLAN_PRIO_TAG_S 0
372 #define ICE_AQ_VLAN_PRIO_TAG_M (0x7 << ICE_AQ_VLAN_PRIO_TAG_S)
373 #define ICE_AQ_VLAN_PRIO_TAG_NOT_SUPPORTED 0x0
374 #define ICE_AQ_VLAN_PRIO_TAG_STAG 0x1
375 #define ICE_AQ_VLAN_PRIO_TAG_OUTER_CTAG 0x2
376 #define ICE_AQ_VLAN_PRIO_TAG_OUTER_VLAN 0x3
377 #define ICE_AQ_VLAN_PRIO_TAG_INNER_CTAG 0x4
378 #define ICE_AQ_VLAN_PRIO_TAG_MAX 0x4
379 #define ICE_AQ_VLAN_PRIO_TAG_ERROR 0x7
380 u8 l2tag_reserved[64];
382 #define ICE_AQ_VLAN_RDMA_TAG_S 0
383 #define ICE_AQ_VLAN_RDMA_TAG_M (0x3F << ICE_AQ_VLAN_RDMA_TAG_S)
384 #define ICE_AQ_SVM_VLAN_RDMA_PKT_FLAG_SETTING 0x10
385 #define ICE_AQ_DVM_VLAN_RDMA_PKT_FLAG_SETTING 0x1A
388 #define ICE_AQ_VLAN_MNG_PROTOCOL_ID_OUTER 0x10
389 #define ICE_AQ_VLAN_MNG_PROTOCOL_ID_INNER 0x11
390 u8 prot_id_reserved[30];
393 /* Response buffer for Get VLAN Mode AQ command (indirect 0x020D) */
394 struct ice_aqc_get_vlan_mode {
396 #define ICE_AQ_VLAN_MODE_DVM_ENA BIT(0)
397 u8 l2tag_prio_tagging;
401 /* Add VSI (indirect 0x0210)
402 * Update VSI (indirect 0x0211)
403 * Get VSI (indirect 0x0212)
404 * Free VSI (indirect 0x0213)
406 struct ice_aqc_add_get_update_free_vsi {
408 #define ICE_AQ_VSI_NUM_S 0
409 #define ICE_AQ_VSI_NUM_M (0x03FF << ICE_AQ_VSI_NUM_S)
410 #define ICE_AQ_VSI_IS_VALID BIT(15)
412 #define ICE_AQ_VSI_KEEP_ALLOC 0x1
416 #define ICE_AQ_VSI_TYPE_S 0
417 #define ICE_AQ_VSI_TYPE_M (0x3 << ICE_AQ_VSI_TYPE_S)
418 #define ICE_AQ_VSI_TYPE_VF 0x0
419 #define ICE_AQ_VSI_TYPE_VMDQ2 0x1
420 #define ICE_AQ_VSI_TYPE_PF 0x2
421 #define ICE_AQ_VSI_TYPE_EMP_MNG 0x3
426 /* Response descriptor for:
427 * Add VSI (indirect 0x0210)
428 * Update VSI (indirect 0x0211)
429 * Free VSI (indirect 0x0213)
431 struct ice_aqc_add_update_free_vsi_resp {
440 struct ice_aqc_get_vsi_resp {
443 /* The vsi_flags field uses the ICE_AQ_VSI_TYPE_* defines for values.
444 * These are found above in struct ice_aqc_add_get_update_free_vsi.
453 struct ice_aqc_vsi_props {
454 __le16 valid_sections;
455 #define ICE_AQ_VSI_PROP_SW_VALID BIT(0)
456 #define ICE_AQ_VSI_PROP_SECURITY_VALID BIT(1)
457 #define ICE_AQ_VSI_PROP_VLAN_VALID BIT(2)
458 #define ICE_AQ_VSI_PROP_OUTER_TAG_VALID BIT(3)
459 #define ICE_AQ_VSI_PROP_INGRESS_UP_VALID BIT(4)
460 #define ICE_AQ_VSI_PROP_EGRESS_UP_VALID BIT(5)
461 #define ICE_AQ_VSI_PROP_RXQ_MAP_VALID BIT(6)
462 #define ICE_AQ_VSI_PROP_Q_OPT_VALID BIT(7)
463 #define ICE_AQ_VSI_PROP_OUTER_UP_VALID BIT(8)
464 #define ICE_AQ_VSI_PROP_ACL_VALID BIT(10)
465 #define ICE_AQ_VSI_PROP_FLOW_DIR_VALID BIT(11)
466 #define ICE_AQ_VSI_PROP_PASID_VALID BIT(12)
470 #define ICE_AQ_VSI_SW_FLAG_ALLOW_LB BIT(5)
471 #define ICE_AQ_VSI_SW_FLAG_LOCAL_LB BIT(6)
472 #define ICE_AQ_VSI_SW_FLAG_SRC_PRUNE BIT(7)
474 #define ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_S 0
475 #define ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_M (0xF << ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_S)
476 #define ICE_AQ_VSI_SW_FLAG_RX_VLAN_PRUNE_ENA BIT(0)
477 #define ICE_AQ_VSI_SW_FLAG_LAN_ENA BIT(4)
479 #define ICE_AQ_VSI_SW_VEB_STAT_ID_S 0
480 #define ICE_AQ_VSI_SW_VEB_STAT_ID_M (0x1F << ICE_AQ_VSI_SW_VEB_STAT_ID_S)
481 #define ICE_AQ_VSI_SW_VEB_STAT_ID_VALID BIT(5)
482 /* security section */
484 #define ICE_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD BIT(0)
485 #define ICE_AQ_VSI_SEC_FLAG_ENA_MAC_ANTI_SPOOF BIT(2)
486 #define ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S 4
487 #define ICE_AQ_VSI_SEC_TX_PRUNE_ENA_M (0xF << ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S)
488 #define ICE_AQ_VSI_SEC_TX_VLAN_PRUNE_ENA BIT(0)
491 __le16 port_based_inner_vlan; /* VLANS include priority bits */
492 u8 inner_vlan_reserved[2];
494 #define ICE_AQ_VSI_INNER_VLAN_TX_MODE_S 0
495 #define ICE_AQ_VSI_INNER_VLAN_TX_MODE_M (0x3 << ICE_AQ_VSI_INNER_VLAN_TX_MODE_S)
496 #define ICE_AQ_VSI_INNER_VLAN_TX_MODE_ACCEPTUNTAGGED 0x1
497 #define ICE_AQ_VSI_INNER_VLAN_TX_MODE_ACCEPTTAGGED 0x2
498 #define ICE_AQ_VSI_INNER_VLAN_TX_MODE_ALL 0x3
499 #define ICE_AQ_VSI_INNER_VLAN_INSERT_PVID BIT(2)
500 #define ICE_AQ_VSI_INNER_VLAN_EMODE_S 3
501 #define ICE_AQ_VSI_INNER_VLAN_EMODE_M (0x3 << ICE_AQ_VSI_INNER_VLAN_EMODE_S)
502 #define ICE_AQ_VSI_INNER_VLAN_EMODE_STR_BOTH (0x0 << ICE_AQ_VSI_INNER_VLAN_EMODE_S)
503 #define ICE_AQ_VSI_INNER_VLAN_EMODE_STR_UP (0x1 << ICE_AQ_VSI_INNER_VLAN_EMODE_S)
504 #define ICE_AQ_VSI_INNER_VLAN_EMODE_STR (0x2 << ICE_AQ_VSI_INNER_VLAN_EMODE_S)
505 #define ICE_AQ_VSI_INNER_VLAN_EMODE_NOTHING (0x3 << ICE_AQ_VSI_INNER_VLAN_EMODE_S)
506 #define ICE_AQ_VSI_INNER_VLAN_BLOCK_TX_DESC BIT(5)
507 u8 inner_vlan_reserved2[3];
508 /* ingress egress up sections */
509 __le32 ingress_table; /* bitmap, 3 bits per up */
510 #define ICE_AQ_VSI_UP_TABLE_UP0_S 0
511 #define ICE_AQ_VSI_UP_TABLE_UP0_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP0_S)
512 #define ICE_AQ_VSI_UP_TABLE_UP1_S 3
513 #define ICE_AQ_VSI_UP_TABLE_UP1_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP1_S)
514 #define ICE_AQ_VSI_UP_TABLE_UP2_S 6
515 #define ICE_AQ_VSI_UP_TABLE_UP2_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP2_S)
516 #define ICE_AQ_VSI_UP_TABLE_UP3_S 9
517 #define ICE_AQ_VSI_UP_TABLE_UP3_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP3_S)
518 #define ICE_AQ_VSI_UP_TABLE_UP4_S 12
519 #define ICE_AQ_VSI_UP_TABLE_UP4_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP4_S)
520 #define ICE_AQ_VSI_UP_TABLE_UP5_S 15
521 #define ICE_AQ_VSI_UP_TABLE_UP5_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP5_S)
522 #define ICE_AQ_VSI_UP_TABLE_UP6_S 18
523 #define ICE_AQ_VSI_UP_TABLE_UP6_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP6_S)
524 #define ICE_AQ_VSI_UP_TABLE_UP7_S 21
525 #define ICE_AQ_VSI_UP_TABLE_UP7_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP7_S)
526 __le32 egress_table; /* same defines as for ingress table */
527 /* outer tags section */
528 __le16 port_based_outer_vlan;
530 #define ICE_AQ_VSI_OUTER_VLAN_EMODE_S 0
531 #define ICE_AQ_VSI_OUTER_VLAN_EMODE_M (0x3 << ICE_AQ_VSI_OUTER_VLAN_EMODE_S)
532 #define ICE_AQ_VSI_OUTER_VLAN_EMODE_SHOW_BOTH 0x0
533 #define ICE_AQ_VSI_OUTER_VLAN_EMODE_SHOW_UP 0x1
534 #define ICE_AQ_VSI_OUTER_VLAN_EMODE_SHOW 0x2
535 #define ICE_AQ_VSI_OUTER_VLAN_EMODE_NOTHING 0x3
536 #define ICE_AQ_VSI_OUTER_TAG_TYPE_S 2
537 #define ICE_AQ_VSI_OUTER_TAG_TYPE_M (0x3 << ICE_AQ_VSI_OUTER_TAG_TYPE_S)
538 #define ICE_AQ_VSI_OUTER_TAG_NONE 0x0
539 #define ICE_AQ_VSI_OUTER_TAG_STAG 0x1
540 #define ICE_AQ_VSI_OUTER_TAG_VLAN_8100 0x2
541 #define ICE_AQ_VSI_OUTER_TAG_VLAN_9100 0x3
542 #define ICE_AQ_VSI_OUTER_VLAN_PORT_BASED_INSERT BIT(4)
543 #define ICE_AQ_VSI_OUTER_VLAN_PORT_BASED_ACCEPT_HOST BIT(6)
544 #define ICE_AQ_VSI_OUTER_VLAN_TX_MODE_S 5
545 #define ICE_AQ_VSI_OUTER_VLAN_TX_MODE_M (0x3 << ICE_AQ_VSI_OUTER_VLAN_TX_MODE_S)
546 #define ICE_AQ_VSI_OUTER_VLAN_TX_MODE_ACCEPTUNTAGGED 0x1
547 #define ICE_AQ_VSI_OUTER_VLAN_TX_MODE_ACCEPTTAGGED 0x2
548 #define ICE_AQ_VSI_OUTER_VLAN_TX_MODE_ALL 0x3
549 #define ICE_AQ_VSI_OUTER_VLAN_BLOCK_TX_DESC BIT(7)
550 u8 outer_vlan_reserved;
551 /* queue mapping section */
552 __le16 mapping_flags;
553 #define ICE_AQ_VSI_Q_MAP_CONTIG 0x0
554 #define ICE_AQ_VSI_Q_MAP_NONCONTIG BIT(0)
555 __le16 q_mapping[16];
556 #define ICE_AQ_VSI_Q_S 0
557 #define ICE_AQ_VSI_Q_M (0x7FF << ICE_AQ_VSI_Q_S)
558 __le16 tc_mapping[8];
559 #define ICE_AQ_VSI_TC_Q_OFFSET_S 0
560 #define ICE_AQ_VSI_TC_Q_OFFSET_M (0x7FF << ICE_AQ_VSI_TC_Q_OFFSET_S)
561 #define ICE_AQ_VSI_TC_Q_NUM_S 11
562 #define ICE_AQ_VSI_TC_Q_NUM_M (0xF << ICE_AQ_VSI_TC_Q_NUM_S)
563 /* queueing option section */
565 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_S 0
566 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_M (0x3 << ICE_AQ_VSI_Q_OPT_RSS_LUT_S)
567 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_VSI 0x0
568 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_PF 0x2
569 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_GBL 0x3
570 #define ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_S 2
571 #define ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_M (0xF << ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_S)
572 #define ICE_AQ_VSI_Q_OPT_RSS_HASH_S 6
573 #define ICE_AQ_VSI_Q_OPT_RSS_HASH_M (0x3 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S)
574 #define ICE_AQ_VSI_Q_OPT_RSS_TPLZ (0x0 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S)
575 #define ICE_AQ_VSI_Q_OPT_RSS_SYM_TPLZ (0x1 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S)
576 #define ICE_AQ_VSI_Q_OPT_RSS_XOR (0x2 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S)
577 #define ICE_AQ_VSI_Q_OPT_RSS_JHASH (0x3 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S)
579 #define ICE_AQ_VSI_Q_OPT_TC_OVR_S 0
580 #define ICE_AQ_VSI_Q_OPT_TC_OVR_M (0x1F << ICE_AQ_VSI_Q_OPT_TC_OVR_S)
581 #define ICE_AQ_VSI_Q_OPT_PROF_TC_OVR BIT(7)
583 #define ICE_AQ_VSI_Q_OPT_PE_FLTR_EN BIT(0)
584 u8 q_opt_reserved[3];
585 /* outer up section */
586 __le32 outer_up_table; /* same structure and defines as ingress tbl */
589 #define ICE_AQ_VSI_ACL_DEF_RX_PROF_S 0
590 #define ICE_AQ_VSI_ACL_DEF_RX_PROF_M (0xF << ICE_AQ_VSI_ACL_DEF_RX_PROF_S)
591 #define ICE_AQ_VSI_ACL_DEF_RX_TABLE_S 4
592 #define ICE_AQ_VSI_ACL_DEF_RX_TABLE_M (0xF << ICE_AQ_VSI_ACL_DEF_RX_TABLE_S)
593 #define ICE_AQ_VSI_ACL_DEF_TX_PROF_S 8
594 #define ICE_AQ_VSI_ACL_DEF_TX_PROF_M (0xF << ICE_AQ_VSI_ACL_DEF_TX_PROF_S)
595 #define ICE_AQ_VSI_ACL_DEF_TX_TABLE_S 12
596 #define ICE_AQ_VSI_ACL_DEF_TX_TABLE_M (0xF << ICE_AQ_VSI_ACL_DEF_TX_TABLE_S)
597 /* flow director section */
599 #define ICE_AQ_VSI_FD_ENABLE BIT(0)
600 #define ICE_AQ_VSI_FD_TX_AUTO_ENABLE BIT(1)
601 #define ICE_AQ_VSI_FD_PROG_ENABLE BIT(3)
602 __le16 max_fd_fltr_dedicated;
603 __le16 max_fd_fltr_shared;
605 #define ICE_AQ_VSI_FD_DEF_Q_S 0
606 #define ICE_AQ_VSI_FD_DEF_Q_M (0x7FF << ICE_AQ_VSI_FD_DEF_Q_S)
607 #define ICE_AQ_VSI_FD_DEF_GRP_S 12
608 #define ICE_AQ_VSI_FD_DEF_GRP_M (0x7 << ICE_AQ_VSI_FD_DEF_GRP_S)
609 __le16 fd_report_opt;
610 #define ICE_AQ_VSI_FD_REPORT_Q_S 0
611 #define ICE_AQ_VSI_FD_REPORT_Q_M (0x7FF << ICE_AQ_VSI_FD_REPORT_Q_S)
612 #define ICE_AQ_VSI_FD_DEF_PRIORITY_S 12
613 #define ICE_AQ_VSI_FD_DEF_PRIORITY_M (0x7 << ICE_AQ_VSI_FD_DEF_PRIORITY_S)
614 #define ICE_AQ_VSI_FD_DEF_DROP BIT(15)
617 #define ICE_AQ_VSI_PASID_ID_S 0
618 #define ICE_AQ_VSI_PASID_ID_M (0xFFFFF << ICE_AQ_VSI_PASID_ID_S)
619 #define ICE_AQ_VSI_PASID_ID_VALID BIT(31)
623 /* Add/update mirror rule - direct (0x0260) */
624 #define ICE_AQC_RULE_ID_VALID_S 7
625 #define ICE_AQC_RULE_ID_VALID_M (0x1 << ICE_AQC_RULE_ID_VALID_S)
626 #define ICE_AQC_RULE_ID_S 0
627 #define ICE_AQC_RULE_ID_M (0x3F << ICE_AQC_RULE_ID_S)
629 /* Following defines to be used while processing caller specified mirror list
632 /* Action: Byte.bit (1.7)
633 * 0 = Remove VSI from mirror rule
634 * 1 = Add VSI to mirror rule
636 #define ICE_AQC_RULE_ACT_S 15
637 #define ICE_AQC_RULE_ACT_M (0x1 << ICE_AQC_RULE_ACT_S)
638 /* Action: 1.2:0.0 = Mirrored VSI */
639 #define ICE_AQC_RULE_MIRRORED_VSI_S 0
640 #define ICE_AQC_RULE_MIRRORED_VSI_M (0x7FF << ICE_AQC_RULE_MIRRORED_VSI_S)
642 /* This is to be used by add/update mirror rule Admin Queue command.
643 * In case of add mirror rule - if rule ID is specified as
644 * INVAL_MIRROR_RULE_ID, new rule ID is allocated from shared pool.
645 * If specified rule_id is valid, then it is used. If specified rule_id
646 * is in use then new mirroring rule is added.
648 #define ICE_INVAL_MIRROR_RULE_ID 0xFFFF
650 struct ice_aqc_add_update_mir_rule {
654 #define ICE_AQC_RULE_TYPE_S 0
655 #define ICE_AQC_RULE_TYPE_M (0x7 << ICE_AQC_RULE_TYPE_S)
656 /* VPORT ingress/egress */
657 #define ICE_AQC_RULE_TYPE_VPORT_INGRESS 0x1
658 #define ICE_AQC_RULE_TYPE_VPORT_EGRESS 0x2
659 /* Physical port ingress mirroring.
660 * All traffic received by this port
662 #define ICE_AQC_RULE_TYPE_PPORT_INGRESS 0x6
663 /* Physical port egress mirroring. All traffic sent by this port */
664 #define ICE_AQC_RULE_TYPE_PPORT_EGRESS 0x7
666 /* Number of mirrored entries.
667 * The values are in the command buffer
671 /* Destination VSI */
677 /* Delete mirror rule - direct(0x0261) */
678 struct ice_aqc_delete_mir_rule {
682 /* Byte.bit: 20.0 = Keep allocation. If set VSI stays part of
683 * the PF allocated resources, otherwise it is returned to the
686 #define ICE_AQC_FLAG_KEEP_ALLOCD_S 0
687 #define ICE_AQC_FLAG_KEEP_ALLOCD_M (0x1 << ICE_AQC_FLAG_KEEP_ALLOCD_S)
693 /* Set/Get storm config - (direct 0x0280, 0x0281) */
694 /* This structure holds get storm configuration response and same structure
695 * is used to perform set_storm_cfg
697 struct ice_aqc_storm_cfg {
698 __le32 bcast_thresh_size;
699 __le32 mcast_thresh_size;
700 /* Bit 18:0 - Traffic upper threshold size
701 * Bit 31:19 - Reserved
703 #define ICE_AQ_THRESHOLD_S 0
704 #define ICE_AQ_THRESHOLD_M (0x7FFFF << ICE_AQ_THRESHOLD_S)
706 __le32 storm_ctrl_ctrl;
707 /* Bit 0: MDIPW - Drop Multicast packets in previous window
708 * Bit 1: MDICW - Drop multicast packets in current window
709 * Bit 2: BDIPW - Drop broadcast packets in previous window
710 * Bit 3: BDICW - Drop broadcast packets in current window
712 #define ICE_AQ_STORM_CTRL_MDIPW_DROP_MULTICAST BIT(0)
713 #define ICE_AQ_STORM_CTRL_MDICW_DROP_MULTICAST BIT(1)
714 #define ICE_AQ_STORM_CTRL_BDIPW_DROP_MULTICAST BIT(2)
715 #define ICE_AQ_STORM_CTRL_BDICW_DROP_MULTICAST BIT(3)
716 /* Bit 7:5 : Reserved */
717 /* Bit 27:8 : Interval - BSC/MSC Time-interval specification: The
718 * interval size for applying ingress broadcast or multicast storm
721 #define ICE_AQ_STORM_BSC_MSC_TIME_INTERVAL_S 8
722 #define ICE_AQ_STORM_BSC_MSC_TIME_INTERVAL_M \
723 (0xFFFFF << ICE_AQ_STORM_BSC_MSC_TIME_INTERVAL_S)
727 #define ICE_MAX_NUM_RECIPES 64
729 /* Add/Get Recipe (indirect 0x0290/0x0292) */
730 struct ice_aqc_add_get_recipe {
731 __le16 num_sub_recipes; /* Input in Add cmd, Output in Get cmd */
732 __le16 return_index; /* Input, used for Get cmd only */
738 struct ice_aqc_recipe_content {
740 #define ICE_AQ_RECIPE_ID_S 0
741 #define ICE_AQ_RECIPE_ID_M (0x3F << ICE_AQ_RECIPE_ID_S)
742 #define ICE_AQ_RECIPE_ID_IS_ROOT BIT(7)
743 #define ICE_AQ_SW_ID_LKUP_IDX 0
745 #define ICE_AQ_RECIPE_LKUP_DATA_S 0
746 #define ICE_AQ_RECIPE_LKUP_DATA_M (0x3F << ICE_AQ_RECIPE_LKUP_DATA_S)
747 #define ICE_AQ_RECIPE_LKUP_IGNORE BIT(7)
748 #define ICE_AQ_SW_ID_LKUP_MASK 0x00FF
751 #define ICE_AQ_RECIPE_RESULT_DATA_S 0
752 #define ICE_AQ_RECIPE_RESULT_DATA_M (0x3F << ICE_AQ_RECIPE_RESULT_DATA_S)
753 #define ICE_AQ_RECIPE_RESULT_EN BIT(7)
755 u8 act_ctrl_join_priority;
756 u8 act_ctrl_fwd_priority;
757 #define ICE_AQ_RECIPE_FWD_PRIORITY_S 0
758 #define ICE_AQ_RECIPE_FWD_PRIORITY_M (0xF << ICE_AQ_RECIPE_FWD_PRIORITY_S)
760 #define ICE_AQ_RECIPE_ACT_NEED_PASS_L2 BIT(0)
761 #define ICE_AQ_RECIPE_ACT_ALLOW_PASS_L2 BIT(1)
762 #define ICE_AQ_RECIPE_ACT_INV_ACT BIT(2)
763 #define ICE_AQ_RECIPE_ACT_PRUNE_INDX_S 4
764 #define ICE_AQ_RECIPE_ACT_PRUNE_INDX_M (0x3 << ICE_AQ_RECIPE_ACT_PRUNE_INDX_S)
767 #define ICE_AQ_RECIPE_DFLT_ACT_S 0
768 #define ICE_AQ_RECIPE_DFLT_ACT_M (0x7FFFF << ICE_AQ_RECIPE_DFLT_ACT_S)
769 #define ICE_AQ_RECIPE_DFLT_ACT_VALID BIT(31)
772 struct ice_aqc_recipe_data_elem {
775 #define ICE_AQ_RECIPE_WAS_UPDATED BIT(0)
779 struct ice_aqc_recipe_content content;
783 /* Set/Get Recipes to Profile Association (direct 0x0291/0x0293) */
784 struct ice_aqc_recipe_to_profile {
787 ice_declare_bitmap(recipe_assoc, ICE_MAX_NUM_RECIPES);
790 /* Add/Update/Remove/Get switch rules (indirect 0x02A0, 0x02A1, 0x02A2, 0x02A3)
792 struct ice_aqc_sw_rules {
793 /* ops: add switch rules, referring the number of rules.
794 * ops: update switch rules, referring the number of filters
795 * ops: remove switch rules, referring the entry index.
796 * ops: get switch rules, referring to the number of filters.
798 __le16 num_rules_fltr_entry_index;
804 /* Add/Update/Get/Remove lookup Rx/Tx command/response entry
805 * This structures describes the lookup rules and associated actions. "index"
806 * is returned as part of a response to a successful Add command, and can be
807 * used to identify the rule for Update/Get/Remove commands.
809 struct ice_sw_rule_lkup_rx_tx {
811 #define ICE_SW_RECIPE_LOGICAL_PORT_FWD 10
812 /* Source port for LOOKUP_RX and source VSI in case of LOOKUP_TX */
816 /* Bit 0:1 - Action type */
817 #define ICE_SINGLE_ACT_TYPE_S 0x00
818 #define ICE_SINGLE_ACT_TYPE_M (0x3 << ICE_SINGLE_ACT_TYPE_S)
820 /* Bit 2 - Loop back enable
823 #define ICE_SINGLE_ACT_LB_ENABLE BIT(2)
824 #define ICE_SINGLE_ACT_LAN_ENABLE BIT(3)
826 /* Action type = 0 - Forward to VSI or VSI list */
827 #define ICE_SINGLE_ACT_VSI_FORWARDING 0x0
829 #define ICE_SINGLE_ACT_VSI_ID_S 4
830 #define ICE_SINGLE_ACT_VSI_ID_M (0x3FF << ICE_SINGLE_ACT_VSI_ID_S)
831 #define ICE_SINGLE_ACT_VSI_LIST_ID_S 4
832 #define ICE_SINGLE_ACT_VSI_LIST_ID_M (0x3FF << ICE_SINGLE_ACT_VSI_LIST_ID_S)
833 /* This bit needs to be set if action is forward to VSI list */
834 #define ICE_SINGLE_ACT_VSI_LIST BIT(14)
835 #define ICE_SINGLE_ACT_VALID_BIT BIT(17)
836 #define ICE_SINGLE_ACT_DROP BIT(18)
838 /* Action type = 1 - Forward to Queue of Queue group */
839 #define ICE_SINGLE_ACT_TO_Q 0x1
840 #define ICE_SINGLE_ACT_Q_INDEX_S 4
841 #define ICE_SINGLE_ACT_Q_INDEX_M (0x7FF << ICE_SINGLE_ACT_Q_INDEX_S)
842 #define ICE_SINGLE_ACT_Q_REGION_S 15
843 #define ICE_SINGLE_ACT_Q_REGION_M (0x7 << ICE_SINGLE_ACT_Q_REGION_S)
844 #define ICE_SINGLE_ACT_Q_PRIORITY BIT(18)
846 /* Action type = 2 - Prune */
847 #define ICE_SINGLE_ACT_PRUNE 0x2
848 #define ICE_SINGLE_ACT_EGRESS BIT(15)
849 #define ICE_SINGLE_ACT_INGRESS BIT(16)
850 #define ICE_SINGLE_ACT_PRUNET BIT(17)
851 /* Bit 18 should be set to 0 for this action */
853 /* Action type = 2 - Pointer */
854 #define ICE_SINGLE_ACT_PTR 0x2
855 #define ICE_SINGLE_ACT_PTR_VAL_S 4
856 #define ICE_SINGLE_ACT_PTR_VAL_M (0x1FFF << ICE_SINGLE_ACT_PTR_VAL_S)
857 /* Bit 18 should be set to 1 */
858 #define ICE_SINGLE_ACT_PTR_BIT BIT(18)
860 /* Action type = 3 - Other actions. Last two bits
861 * are other action identifier
863 #define ICE_SINGLE_ACT_OTHER_ACTS 0x3
864 #define ICE_SINGLE_OTHER_ACT_IDENTIFIER_S 17
865 #define ICE_SINGLE_OTHER_ACT_IDENTIFIER_M \
866 (0x3 << ICE_SINGLE_OTHER_ACT_IDENTIFIER_S)
868 /* Bit 17:18 - Defines other actions */
869 /* Other action = 0 - Mirror VSI */
870 #define ICE_SINGLE_OTHER_ACT_MIRROR 0
871 #define ICE_SINGLE_ACT_MIRROR_VSI_ID_S 4
872 #define ICE_SINGLE_ACT_MIRROR_VSI_ID_M \
873 (0x3FF << ICE_SINGLE_ACT_MIRROR_VSI_ID_S)
875 /* Other action = 3 - Set Stat count */
876 #define ICE_SINGLE_OTHER_ACT_STAT_COUNT 3
877 #define ICE_SINGLE_ACT_STAT_COUNT_INDEX_S 4
878 #define ICE_SINGLE_ACT_STAT_COUNT_INDEX_M \
879 (0x7F << ICE_SINGLE_ACT_STAT_COUNT_INDEX_S)
881 __le16 index; /* The index of the rule in the lookup table */
882 /* Length and values of the header to be matched per recipe or
886 u8 hdr[STRUCT_HACK_VAR_LEN];
889 /* Add/Update/Remove large action command/response entry
890 * "index" is returned as part of a response to a successful Add command, and
891 * can be used to identify the action for Update/Get/Remove commands.
893 struct ice_sw_rule_lg_act {
894 __le16 index; /* Index in large action table */
896 /* Max number of large actions */
897 #define ICE_MAX_LG_ACT 4
898 /* Bit 0:1 - Action type */
899 #define ICE_LG_ACT_TYPE_S 0
900 #define ICE_LG_ACT_TYPE_M (0x7 << ICE_LG_ACT_TYPE_S)
902 /* Action type = 0 - Forward to VSI or VSI list */
903 #define ICE_LG_ACT_VSI_FORWARDING 0
904 #define ICE_LG_ACT_VSI_ID_S 3
905 #define ICE_LG_ACT_VSI_ID_M (0x3FF << ICE_LG_ACT_VSI_ID_S)
906 #define ICE_LG_ACT_VSI_LIST_ID_S 3
907 #define ICE_LG_ACT_VSI_LIST_ID_M (0x3FF << ICE_LG_ACT_VSI_LIST_ID_S)
908 /* This bit needs to be set if action is forward to VSI list */
909 #define ICE_LG_ACT_VSI_LIST BIT(13)
911 #define ICE_LG_ACT_VALID_BIT BIT(16)
913 /* Action type = 1 - Forward to Queue of Queue group */
914 #define ICE_LG_ACT_TO_Q 0x1
915 #define ICE_LG_ACT_Q_INDEX_S 3
916 #define ICE_LG_ACT_Q_INDEX_M (0x7FF << ICE_LG_ACT_Q_INDEX_S)
917 #define ICE_LG_ACT_Q_REGION_S 14
918 #define ICE_LG_ACT_Q_REGION_M (0x7 << ICE_LG_ACT_Q_REGION_S)
919 #define ICE_LG_ACT_Q_PRIORITY_SET BIT(17)
921 /* Action type = 2 - Prune */
922 #define ICE_LG_ACT_PRUNE 0x2
923 #define ICE_LG_ACT_EGRESS BIT(14)
924 #define ICE_LG_ACT_INGRESS BIT(15)
925 #define ICE_LG_ACT_PRUNET BIT(16)
927 /* Action type = 3 - Mirror VSI */
928 #define ICE_LG_OTHER_ACT_MIRROR 0x3
929 #define ICE_LG_ACT_MIRROR_VSI_ID_S 3
930 #define ICE_LG_ACT_MIRROR_VSI_ID_M (0x3FF << ICE_LG_ACT_MIRROR_VSI_ID_S)
932 /* Action type = 5 - Generic Value */
933 #define ICE_LG_ACT_GENERIC 0x5
934 #define ICE_LG_ACT_GENERIC_VALUE_S 3
935 #define ICE_LG_ACT_GENERIC_VALUE_M (0xFFFF << ICE_LG_ACT_GENERIC_VALUE_S)
936 #define ICE_LG_ACT_GENERIC_OFFSET_S 19
937 #define ICE_LG_ACT_GENERIC_OFFSET_M (0x7 << ICE_LG_ACT_GENERIC_OFFSET_S)
938 #define ICE_LG_ACT_GENERIC_PRIORITY_S 22
939 #define ICE_LG_ACT_GENERIC_PRIORITY_M (0x7 << ICE_LG_ACT_GENERIC_PRIORITY_S)
940 #define ICE_LG_ACT_GENERIC_OFF_RX_DESC_PROF_IDX 7
942 /* Action = 7 - Set Stat count */
943 #define ICE_LG_ACT_STAT_COUNT 0x7
944 #define ICE_LG_ACT_STAT_COUNT_S 3
945 #define ICE_LG_ACT_STAT_COUNT_M (0x7F << ICE_LG_ACT_STAT_COUNT_S)
946 __le32 act[STRUCT_HACK_VAR_LEN]; /* array of size for actions */
949 /* Add/Update/Remove VSI list command/response entry
950 * "index" is returned as part of a response to a successful Add command, and
951 * can be used to identify the VSI list for Update/Get/Remove commands.
953 struct ice_sw_rule_vsi_list {
954 __le16 index; /* Index of VSI/Prune list */
956 __le16 vsi[STRUCT_HACK_VAR_LEN]; /* Array of number_vsi VSI numbers */
960 /* Query VSI list command/response entry */
961 struct ice_sw_rule_vsi_list_query {
963 ice_declare_bitmap(vsi_list, ICE_MAX_VSI);
968 /* Add switch rule response:
969 * Content of return buffer is same as the input buffer. The status field and
970 * LUT index are updated as part of the response
972 struct ice_aqc_sw_rules_elem {
973 __le16 type; /* Switch rule type, one of T_... */
974 #define ICE_AQC_SW_RULES_T_LKUP_RX 0x0
975 #define ICE_AQC_SW_RULES_T_LKUP_TX 0x1
976 #define ICE_AQC_SW_RULES_T_LG_ACT 0x2
977 #define ICE_AQC_SW_RULES_T_VSI_LIST_SET 0x3
978 #define ICE_AQC_SW_RULES_T_VSI_LIST_CLEAR 0x4
979 #define ICE_AQC_SW_RULES_T_PRUNE_LIST_SET 0x5
980 #define ICE_AQC_SW_RULES_T_PRUNE_LIST_CLEAR 0x6
983 struct ice_sw_rule_lkup_rx_tx lkup_tx_rx;
984 struct ice_sw_rule_lg_act lg_act;
985 struct ice_sw_rule_vsi_list vsi_list;
986 struct ice_sw_rule_vsi_list_query vsi_list_query;
992 /* PFC Ignore (direct 0x0301)
993 * The command and response use the same descriptor structure
995 struct ice_aqc_pfc_ignore {
997 u8 cmd_flags; /* unused in response */
998 #define ICE_AQC_PFC_IGNORE_SET BIT(7)
999 #define ICE_AQC_PFC_IGNORE_CLEAR 0
1003 /* Set PFC Mode (direct 0x0303)
1004 * Query PFC Mode (direct 0x0302)
1006 struct ice_aqc_set_query_pfc_mode {
1008 /* For Set Command response, reserved in all other cases */
1009 #define ICE_AQC_PFC_NOT_CONFIGURED 0
1010 /* For Query Command response, reserved in all other cases */
1011 #define ICE_AQC_DCB_DIS 0
1012 #define ICE_AQC_PFC_VLAN_BASED_PFC 1
1013 #define ICE_AQC_PFC_DSCP_BASED_PFC 2
1017 /* Set DCB Parameters (direct 0x0306) */
1018 struct ice_aqc_set_dcb_params {
1019 u8 cmd_flags; /* unused in response */
1020 #define ICE_AQC_LINK_UP_DCB_CFG BIT(0)
1021 #define ICE_AQC_PERSIST_DCB_CFG BIT(1)
1022 u8 valid_flags; /* unused in response */
1023 #define ICE_AQC_LINK_UP_DCB_CFG_VALID BIT(0)
1024 #define ICE_AQC_PERSIST_DCB_CFG_VALID BIT(1)
1028 /* Get Default Topology (indirect 0x0400) */
1029 struct ice_aqc_get_topo {
1038 /* Update TSE (indirect 0x0403)
1039 * Get TSE (indirect 0x0404)
1040 * Add TSE (indirect 0x0401)
1041 * Delete TSE (indirect 0x040F)
1042 * Move TSE (indirect 0x0408)
1043 * Suspend Nodes (indirect 0x0409)
1044 * Resume Nodes (indirect 0x040A)
1046 struct ice_aqc_sched_elem_cmd {
1047 __le16 num_elem_req; /* Used by commands */
1048 __le16 num_elem_resp; /* Used by responses */
1054 struct ice_aqc_txsched_move_grp_info_hdr {
1055 __le32 src_parent_teid;
1056 __le32 dest_parent_teid;
1062 struct ice_aqc_move_elem {
1063 struct ice_aqc_txsched_move_grp_info_hdr hdr;
1064 __le32 teid[STRUCT_HACK_VAR_LEN];
1067 struct ice_aqc_elem_info_bw {
1068 __le16 bw_profile_idx;
1072 struct ice_aqc_txsched_elem {
1073 u8 elem_type; /* Special field, reserved for some aq calls */
1074 #define ICE_AQC_ELEM_TYPE_UNDEFINED 0x0
1075 #define ICE_AQC_ELEM_TYPE_ROOT_PORT 0x1
1076 #define ICE_AQC_ELEM_TYPE_TC 0x2
1077 #define ICE_AQC_ELEM_TYPE_SE_GENERIC 0x3
1078 #define ICE_AQC_ELEM_TYPE_ENTRY_POINT 0x4
1079 #define ICE_AQC_ELEM_TYPE_LEAF 0x5
1080 #define ICE_AQC_ELEM_TYPE_SE_PADDED 0x6
1082 #define ICE_AQC_ELEM_VALID_GENERIC BIT(0)
1083 #define ICE_AQC_ELEM_VALID_CIR BIT(1)
1084 #define ICE_AQC_ELEM_VALID_EIR BIT(2)
1085 #define ICE_AQC_ELEM_VALID_SHARED BIT(3)
1087 #define ICE_AQC_ELEM_GENERIC_MODE_M 0x1
1088 #define ICE_AQC_ELEM_GENERIC_PRIO_S 0x1
1089 #define ICE_AQC_ELEM_GENERIC_PRIO_M (0x7 << ICE_AQC_ELEM_GENERIC_PRIO_S)
1090 #define ICE_AQC_ELEM_GENERIC_SP_S 0x4
1091 #define ICE_AQC_ELEM_GENERIC_SP_M (0x1 << ICE_AQC_ELEM_GENERIC_SP_S)
1092 #define ICE_AQC_ELEM_GENERIC_ADJUST_VAL_S 0x5
1093 #define ICE_AQC_ELEM_GENERIC_ADJUST_VAL_M \
1094 (0x3 << ICE_AQC_ELEM_GENERIC_ADJUST_VAL_S)
1095 u8 flags; /* Special field, reserved for some aq calls */
1096 #define ICE_AQC_ELEM_FLAG_SUSPEND_M 0x1
1097 struct ice_aqc_elem_info_bw cir_bw;
1098 struct ice_aqc_elem_info_bw eir_bw;
1103 struct ice_aqc_txsched_elem_data {
1106 struct ice_aqc_txsched_elem data;
1109 struct ice_aqc_txsched_topo_grp_info_hdr {
1115 struct ice_aqc_add_elem {
1116 struct ice_aqc_txsched_topo_grp_info_hdr hdr;
1117 struct ice_aqc_txsched_elem_data generic[STRUCT_HACK_VAR_LEN];
1120 struct ice_aqc_get_topo_elem {
1121 struct ice_aqc_txsched_topo_grp_info_hdr hdr;
1122 struct ice_aqc_txsched_elem_data
1123 generic[ICE_AQC_TOPO_MAX_LEVEL_NUM];
1126 struct ice_aqc_delete_elem {
1127 struct ice_aqc_txsched_topo_grp_info_hdr hdr;
1128 __le32 teid[STRUCT_HACK_VAR_LEN];
1131 /* Query Port ETS (indirect 0x040E)
1133 * This indirect command is used to query port TC node configuration.
1135 struct ice_aqc_query_port_ets {
1142 struct ice_aqc_port_ets_elem {
1145 /* 3 bits for UP per TC 0-7, 4th byte reserved */
1148 __le32 port_eir_prof_id;
1149 __le32 port_cir_prof_id;
1150 /* 3 bits per Node priority to TC 0-7, 4th byte reserved */
1151 __le32 tc_node_prio;
1152 #define ICE_TC_NODE_PRIO_S 0x4
1154 __le32 tc_node_teid[8]; /* Used for response, reserved in command */
1157 /* Rate limiting profile for
1158 * Add RL profile (indirect 0x0410)
1159 * Query RL profile (indirect 0x0411)
1160 * Remove RL profile (indirect 0x0415)
1161 * These indirect commands acts on single or multiple
1162 * RL profiles with specified data.
1164 struct ice_aqc_rl_profile {
1165 __le16 num_profiles;
1166 __le16 num_processed; /* Only for response. Reserved in Command. */
1172 struct ice_aqc_rl_profile_elem {
1175 #define ICE_AQC_RL_PROFILE_TYPE_S 0x0
1176 #define ICE_AQC_RL_PROFILE_TYPE_M (0x3 << ICE_AQC_RL_PROFILE_TYPE_S)
1177 #define ICE_AQC_RL_PROFILE_TYPE_CIR 0
1178 #define ICE_AQC_RL_PROFILE_TYPE_EIR 1
1179 #define ICE_AQC_RL_PROFILE_TYPE_SRL 2
1180 /* The following flag is used for Query RL Profile Data */
1181 #define ICE_AQC_RL_PROFILE_INVAL_S 0x7
1182 #define ICE_AQC_RL_PROFILE_INVAL_M (0x1 << ICE_AQC_RL_PROFILE_INVAL_S)
1185 __le16 max_burst_size;
1187 __le16 wake_up_calc;
1191 /* Configure L2 Node CGD (indirect 0x0414)
1192 * This indirect command allows configuring a congestion domain for given L2
1193 * node TEIDs in the scheduler topology.
1195 struct ice_aqc_cfg_l2_node_cgd {
1196 __le16 num_l2_nodes;
1202 struct ice_aqc_cfg_l2_node_cgd_elem {
1208 /* Query Scheduler Resource Allocation (indirect 0x0412)
1209 * This indirect command retrieves the scheduler resources allocated by
1210 * EMP Firmware to the given PF.
1212 struct ice_aqc_query_txsched_res {
1218 struct ice_aqc_generic_sched_props {
1220 __le16 logical_levels;
1221 u8 flattening_bitmap;
1229 struct ice_aqc_layer_props {
1232 __le16 max_device_nodes;
1233 __le16 max_pf_nodes;
1235 __le16 max_sibl_grp_sz;
1236 __le16 max_cir_rl_profiles;
1237 __le16 max_eir_rl_profiles;
1238 __le16 max_srl_profiles;
1242 struct ice_aqc_query_txsched_res_resp {
1243 struct ice_aqc_generic_sched_props sched_props;
1244 struct ice_aqc_layer_props layer_props[ICE_AQC_TOPO_MAX_LEVEL_NUM];
1247 /* Query Node to Root Topology (indirect 0x0413)
1248 * This command uses ice_aqc_get_elem as its data buffer.
1250 struct ice_aqc_query_node_to_root {
1252 __le32 num_nodes; /* Response only */
1257 /* Get PHY capabilities (indirect 0x0600) */
1258 struct ice_aqc_get_phy_caps {
1262 /* 18.0 - Report qualified modules */
1263 #define ICE_AQC_GET_PHY_RQM BIT(0)
1264 /* 18.1 - 18.3 : Report mode
1265 * 000b - Report NVM capabilities
1266 * 001b - Report topology capabilities
1267 * 010b - Report SW configured
1268 * 100b - Report default capabilities
1270 #define ICE_AQC_REPORT_MODE_S 1
1271 #define ICE_AQC_REPORT_MODE_M (7 << ICE_AQC_REPORT_MODE_S)
1272 #define ICE_AQC_REPORT_TOPO_CAP_NO_MEDIA 0
1273 #define ICE_AQC_REPORT_TOPO_CAP_MEDIA BIT(1)
1274 #define ICE_AQC_REPORT_ACTIVE_CFG BIT(2)
1275 #define ICE_AQC_REPORT_DFLT_CFG BIT(3)
1281 /* This is #define of PHY type (Extended):
1282 * The first set of defines is for phy_type_low.
1284 #define ICE_PHY_TYPE_LOW_100BASE_TX BIT_ULL(0)
1285 #define ICE_PHY_TYPE_LOW_100M_SGMII BIT_ULL(1)
1286 #define ICE_PHY_TYPE_LOW_1000BASE_T BIT_ULL(2)
1287 #define ICE_PHY_TYPE_LOW_1000BASE_SX BIT_ULL(3)
1288 #define ICE_PHY_TYPE_LOW_1000BASE_LX BIT_ULL(4)
1289 #define ICE_PHY_TYPE_LOW_1000BASE_KX BIT_ULL(5)
1290 #define ICE_PHY_TYPE_LOW_1G_SGMII BIT_ULL(6)
1291 #define ICE_PHY_TYPE_LOW_2500BASE_T BIT_ULL(7)
1292 #define ICE_PHY_TYPE_LOW_2500BASE_X BIT_ULL(8)
1293 #define ICE_PHY_TYPE_LOW_2500BASE_KX BIT_ULL(9)
1294 #define ICE_PHY_TYPE_LOW_5GBASE_T BIT_ULL(10)
1295 #define ICE_PHY_TYPE_LOW_5GBASE_KR BIT_ULL(11)
1296 #define ICE_PHY_TYPE_LOW_10GBASE_T BIT_ULL(12)
1297 #define ICE_PHY_TYPE_LOW_10G_SFI_DA BIT_ULL(13)
1298 #define ICE_PHY_TYPE_LOW_10GBASE_SR BIT_ULL(14)
1299 #define ICE_PHY_TYPE_LOW_10GBASE_LR BIT_ULL(15)
1300 #define ICE_PHY_TYPE_LOW_10GBASE_KR_CR1 BIT_ULL(16)
1301 #define ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC BIT_ULL(17)
1302 #define ICE_PHY_TYPE_LOW_10G_SFI_C2C BIT_ULL(18)
1303 #define ICE_PHY_TYPE_LOW_25GBASE_T BIT_ULL(19)
1304 #define ICE_PHY_TYPE_LOW_25GBASE_CR BIT_ULL(20)
1305 #define ICE_PHY_TYPE_LOW_25GBASE_CR_S BIT_ULL(21)
1306 #define ICE_PHY_TYPE_LOW_25GBASE_CR1 BIT_ULL(22)
1307 #define ICE_PHY_TYPE_LOW_25GBASE_SR BIT_ULL(23)
1308 #define ICE_PHY_TYPE_LOW_25GBASE_LR BIT_ULL(24)
1309 #define ICE_PHY_TYPE_LOW_25GBASE_KR BIT_ULL(25)
1310 #define ICE_PHY_TYPE_LOW_25GBASE_KR_S BIT_ULL(26)
1311 #define ICE_PHY_TYPE_LOW_25GBASE_KR1 BIT_ULL(27)
1312 #define ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC BIT_ULL(28)
1313 #define ICE_PHY_TYPE_LOW_25G_AUI_C2C BIT_ULL(29)
1314 #define ICE_PHY_TYPE_LOW_40GBASE_CR4 BIT_ULL(30)
1315 #define ICE_PHY_TYPE_LOW_40GBASE_SR4 BIT_ULL(31)
1316 #define ICE_PHY_TYPE_LOW_40GBASE_LR4 BIT_ULL(32)
1317 #define ICE_PHY_TYPE_LOW_40GBASE_KR4 BIT_ULL(33)
1318 #define ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC BIT_ULL(34)
1319 #define ICE_PHY_TYPE_LOW_40G_XLAUI BIT_ULL(35)
1320 #define ICE_PHY_TYPE_LOW_50GBASE_CR2 BIT_ULL(36)
1321 #define ICE_PHY_TYPE_LOW_50GBASE_SR2 BIT_ULL(37)
1322 #define ICE_PHY_TYPE_LOW_50GBASE_LR2 BIT_ULL(38)
1323 #define ICE_PHY_TYPE_LOW_50GBASE_KR2 BIT_ULL(39)
1324 #define ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC BIT_ULL(40)
1325 #define ICE_PHY_TYPE_LOW_50G_LAUI2 BIT_ULL(41)
1326 #define ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC BIT_ULL(42)
1327 #define ICE_PHY_TYPE_LOW_50G_AUI2 BIT_ULL(43)
1328 #define ICE_PHY_TYPE_LOW_50GBASE_CP BIT_ULL(44)
1329 #define ICE_PHY_TYPE_LOW_50GBASE_SR BIT_ULL(45)
1330 #define ICE_PHY_TYPE_LOW_50GBASE_FR BIT_ULL(46)
1331 #define ICE_PHY_TYPE_LOW_50GBASE_LR BIT_ULL(47)
1332 #define ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4 BIT_ULL(48)
1333 #define ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC BIT_ULL(49)
1334 #define ICE_PHY_TYPE_LOW_50G_AUI1 BIT_ULL(50)
1335 #define ICE_PHY_TYPE_LOW_100GBASE_CR4 BIT_ULL(51)
1336 #define ICE_PHY_TYPE_LOW_100GBASE_SR4 BIT_ULL(52)
1337 #define ICE_PHY_TYPE_LOW_100GBASE_LR4 BIT_ULL(53)
1338 #define ICE_PHY_TYPE_LOW_100GBASE_KR4 BIT_ULL(54)
1339 #define ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC BIT_ULL(55)
1340 #define ICE_PHY_TYPE_LOW_100G_CAUI4 BIT_ULL(56)
1341 #define ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC BIT_ULL(57)
1342 #define ICE_PHY_TYPE_LOW_100G_AUI4 BIT_ULL(58)
1343 #define ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4 BIT_ULL(59)
1344 #define ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4 BIT_ULL(60)
1345 #define ICE_PHY_TYPE_LOW_100GBASE_CP2 BIT_ULL(61)
1346 #define ICE_PHY_TYPE_LOW_100GBASE_SR2 BIT_ULL(62)
1347 #define ICE_PHY_TYPE_LOW_100GBASE_DR BIT_ULL(63)
1348 #define ICE_PHY_TYPE_LOW_MAX_INDEX 63
1349 /* The second set of defines is for phy_type_high. */
1350 #define ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4 BIT_ULL(0)
1351 #define ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC BIT_ULL(1)
1352 #define ICE_PHY_TYPE_HIGH_100G_CAUI2 BIT_ULL(2)
1353 #define ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC BIT_ULL(3)
1354 #define ICE_PHY_TYPE_HIGH_100G_AUI2 BIT_ULL(4)
1355 #define ICE_PHY_TYPE_HIGH_MAX_INDEX 5
1357 struct ice_aqc_get_phy_caps_data {
1358 __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */
1359 __le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */
1361 #define ICE_AQC_PHY_EN_TX_LINK_PAUSE BIT(0)
1362 #define ICE_AQC_PHY_EN_RX_LINK_PAUSE BIT(1)
1363 #define ICE_AQC_PHY_LOW_POWER_MODE BIT(2)
1364 #define ICE_AQC_PHY_EN_LINK BIT(3)
1365 #define ICE_AQC_PHY_AN_MODE BIT(4)
1366 #define ICE_AQC_PHY_EN_MOD_QUAL BIT(5)
1367 #define ICE_AQC_PHY_EN_LESM BIT(6)
1368 #define ICE_AQC_PHY_EN_AUTO_FEC BIT(7)
1369 #define ICE_AQC_PHY_CAPS_MASK MAKEMASK(0xff, 0)
1370 u8 low_power_ctrl_an;
1371 #define ICE_AQC_PHY_EN_D3COLD_LOW_POWER_AUTONEG BIT(0)
1372 #define ICE_AQC_PHY_AN_EN_CLAUSE28 BIT(1)
1373 #define ICE_AQC_PHY_AN_EN_CLAUSE73 BIT(2)
1374 #define ICE_AQC_PHY_AN_EN_CLAUSE37 BIT(3)
1376 #define ICE_AQC_PHY_EEE_EN_100BASE_TX BIT(0)
1377 #define ICE_AQC_PHY_EEE_EN_1000BASE_T BIT(1)
1378 #define ICE_AQC_PHY_EEE_EN_10GBASE_T BIT(2)
1379 #define ICE_AQC_PHY_EEE_EN_1000BASE_KX BIT(3)
1380 #define ICE_AQC_PHY_EEE_EN_10GBASE_KR BIT(4)
1381 #define ICE_AQC_PHY_EEE_EN_25GBASE_KR BIT(5)
1382 #define ICE_AQC_PHY_EEE_EN_40GBASE_KR4 BIT(6)
1383 #define ICE_AQC_PHY_EEE_EN_50GBASE_KR2 BIT(7)
1384 #define ICE_AQC_PHY_EEE_EN_50GBASE_KR_PAM4 BIT(8)
1385 #define ICE_AQC_PHY_EEE_EN_100GBASE_KR4 BIT(9)
1386 #define ICE_AQC_PHY_EEE_EN_100GBASE_KR2_PAM4 BIT(10)
1388 u8 phy_id_oui[4]; /* PHY/Module ID connected on the port */
1390 u8 link_fec_options;
1391 #define ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN BIT(0)
1392 #define ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ BIT(1)
1393 #define ICE_AQC_PHY_FEC_25G_RS_528_REQ BIT(2)
1394 #define ICE_AQC_PHY_FEC_25G_KR_REQ BIT(3)
1395 #define ICE_AQC_PHY_FEC_25G_RS_544_REQ BIT(4)
1396 #define ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN BIT(6)
1397 #define ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN BIT(7)
1398 #define ICE_AQC_PHY_FEC_MASK MAKEMASK(0xdf, 0)
1399 u8 module_compliance_enforcement;
1400 #define ICE_AQC_MOD_ENFORCE_STRICT_MODE BIT(0)
1401 u8 extended_compliance_code;
1402 #define ICE_MODULE_TYPE_TOTAL_BYTE 3
1403 u8 module_type[ICE_MODULE_TYPE_TOTAL_BYTE];
1404 #define ICE_AQC_MOD_TYPE_BYTE0_SFP_PLUS 0xA0
1405 #define ICE_AQC_MOD_TYPE_BYTE0_QSFP_PLUS 0x80
1406 #define ICE_AQC_MOD_TYPE_IDENT 1
1407 #define ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_PASSIVE BIT(0)
1408 #define ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_ACTIVE BIT(1)
1409 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_SR BIT(4)
1410 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_LR BIT(5)
1411 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_LRM BIT(6)
1412 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_ER BIT(7)
1413 #define ICE_AQC_MOD_TYPE_BYTE2_SFP_PLUS 0xA0
1414 #define ICE_AQC_MOD_TYPE_BYTE2_QSFP_PLUS 0x86
1415 u8 qualified_module_count;
1416 u8 rsvd2[7]; /* Bytes 47:41 reserved */
1417 #define ICE_AQC_QUAL_MOD_COUNT_MAX 16
1424 } qual_modules[ICE_AQC_QUAL_MOD_COUNT_MAX];
1427 /* Set PHY capabilities (direct 0x0601)
1428 * NOTE: This command must be followed by setup link and restart auto-neg
1430 struct ice_aqc_set_phy_cfg {
1437 /* Set PHY config command data structure */
1438 struct ice_aqc_set_phy_cfg_data {
1439 __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */
1440 __le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */
1442 #define ICE_AQ_PHY_ENA_VALID_MASK MAKEMASK(0xef, 0)
1443 #define ICE_AQ_PHY_ENA_TX_PAUSE_ABILITY BIT(0)
1444 #define ICE_AQ_PHY_ENA_RX_PAUSE_ABILITY BIT(1)
1445 #define ICE_AQ_PHY_ENA_LOW_POWER BIT(2)
1446 #define ICE_AQ_PHY_ENA_LINK BIT(3)
1447 #define ICE_AQ_PHY_ENA_AUTO_LINK_UPDT BIT(5)
1448 #define ICE_AQ_PHY_ENA_LESM BIT(6)
1449 #define ICE_AQ_PHY_ENA_AUTO_FEC BIT(7)
1450 u8 low_power_ctrl_an;
1451 __le16 eee_cap; /* Value from ice_aqc_get_phy_caps */
1453 u8 link_fec_opt; /* Use defines from ice_aqc_get_phy_caps */
1454 u8 module_compliance_enforcement;
1457 /* Set MAC Config command data structure (direct 0x0603) */
1458 struct ice_aqc_set_mac_cfg {
1459 __le16 max_frame_size;
1461 #define ICE_AQ_SET_MAC_PACE_S 3
1462 #define ICE_AQ_SET_MAC_PACE_M (0xF << ICE_AQ_SET_MAC_PACE_S)
1463 #define ICE_AQ_SET_MAC_PACE_TYPE_M BIT(7)
1464 #define ICE_AQ_SET_MAC_PACE_TYPE_RATE 0
1465 #define ICE_AQ_SET_MAC_PACE_TYPE_FIXED ICE_AQ_SET_MAC_PACE_TYPE_M
1467 __le16 tx_tmr_value;
1468 __le16 fc_refresh_threshold;
1470 #define ICE_AQ_SET_MAC_AUTO_DROP_MASK BIT(0)
1471 #define ICE_AQ_SET_MAC_AUTO_DROP_NONE 0
1472 #define ICE_AQ_SET_MAC_AUTO_DROP_BLOCKING_PKTS BIT(0)
1476 /* Restart AN command data structure (direct 0x0605)
1477 * Also used for response, with only the lport_num field present.
1479 struct ice_aqc_restart_an {
1483 #define ICE_AQC_RESTART_AN_LINK_RESTART BIT(1)
1484 #define ICE_AQC_RESTART_AN_LINK_ENABLE BIT(2)
1488 /* Get link status (indirect 0x0607), also used for Link Status Event */
1489 struct ice_aqc_get_link_status {
1493 #define ICE_AQ_LSE_M 0x3
1494 #define ICE_AQ_LSE_NOP 0x0
1495 #define ICE_AQ_LSE_DIS 0x2
1496 #define ICE_AQ_LSE_ENA 0x3
1497 /* only response uses this flag */
1498 #define ICE_AQ_LSE_IS_ENABLED 0x1
1504 /* Get link status response data structure, also used for Link Status Event */
1505 struct ice_aqc_get_link_status_data {
1506 u8 topo_media_conflict;
1507 #define ICE_AQ_LINK_TOPO_CONFLICT BIT(0)
1508 #define ICE_AQ_LINK_MEDIA_CONFLICT BIT(1)
1509 #define ICE_AQ_LINK_TOPO_CORRUPT BIT(2)
1510 #define ICE_AQ_LINK_TOPO_UNREACH_PRT BIT(4)
1511 #define ICE_AQ_LINK_TOPO_UNDRUTIL_PRT BIT(5)
1512 #define ICE_AQ_LINK_TOPO_UNDRUTIL_MEDIA BIT(6)
1513 #define ICE_AQ_LINK_TOPO_UNSUPP_MEDIA BIT(7)
1515 #define ICE_AQ_LINK_CFG_ERR BIT(0)
1516 #define ICE_AQ_LINK_ACT_PORT_OPT_INVAL BIT(2)
1517 #define ICE_AQ_LINK_FEAT_ID_OR_CONFIG_ID_INVAL BIT(3)
1518 #define ICE_AQ_LINK_TOPO_CRITICAL_SDP_ERR BIT(4)
1519 #define ICE_AQ_LINK_MODULE_POWER_UNSUPPORTED BIT(5)
1520 #define ICE_AQ_LINK_EXTERNAL_PHY_LOAD_FAILURE BIT(6)
1521 #define ICE_AQ_LINK_INVAL_MAX_POWER_LIMIT BIT(7)
1523 #define ICE_AQ_LINK_UP BIT(0) /* Link Status */
1524 #define ICE_AQ_LINK_FAULT BIT(1)
1525 #define ICE_AQ_LINK_FAULT_TX BIT(2)
1526 #define ICE_AQ_LINK_FAULT_RX BIT(3)
1527 #define ICE_AQ_LINK_FAULT_REMOTE BIT(4)
1528 #define ICE_AQ_LINK_UP_PORT BIT(5) /* External Port Link Status */
1529 #define ICE_AQ_MEDIA_AVAILABLE BIT(6)
1530 #define ICE_AQ_SIGNAL_DETECT BIT(7)
1532 #define ICE_AQ_AN_COMPLETED BIT(0)
1533 #define ICE_AQ_LP_AN_ABILITY BIT(1)
1534 #define ICE_AQ_PD_FAULT BIT(2) /* Parallel Detection Fault */
1535 #define ICE_AQ_FEC_EN BIT(3)
1536 #define ICE_AQ_PHY_LOW_POWER BIT(4) /* Low Power State */
1537 #define ICE_AQ_LINK_PAUSE_TX BIT(5)
1538 #define ICE_AQ_LINK_PAUSE_RX BIT(6)
1539 #define ICE_AQ_QUALIFIED_MODULE BIT(7)
1541 #define ICE_AQ_LINK_PHY_TEMP_ALARM BIT(0)
1542 #define ICE_AQ_LINK_EXCESSIVE_ERRORS BIT(1) /* Excessive Link Errors */
1543 /* Port Tx Suspended */
1544 #define ICE_AQ_LINK_TX_S 2
1545 #define ICE_AQ_LINK_TX_M (0x03 << ICE_AQ_LINK_TX_S)
1546 #define ICE_AQ_LINK_TX_ACTIVE 0
1547 #define ICE_AQ_LINK_TX_DRAINED 1
1548 #define ICE_AQ_LINK_TX_FLUSHED 3
1550 #define ICE_AQ_LINK_LB_PHY_LCL BIT(0)
1551 #define ICE_AQ_LINK_LB_PHY_RMT BIT(1)
1552 #define ICE_AQ_LINK_LB_MAC_LCL BIT(2)
1553 #define ICE_AQ_LINK_LB_PHY_IDX_S 3
1554 #define ICE_AQ_LINK_LB_PHY_IDX_M (0x7 << ICE_AQ_LB_PHY_IDX_S)
1555 __le16 max_frame_size;
1557 #define ICE_AQ_LINK_25G_KR_FEC_EN BIT(0)
1558 #define ICE_AQ_LINK_25G_RS_528_FEC_EN BIT(1)
1559 #define ICE_AQ_LINK_25G_RS_544_FEC_EN BIT(2)
1560 #define ICE_AQ_FEC_MASK MAKEMASK(0x7, 0)
1562 #define ICE_AQ_CFG_PACING_S 3
1563 #define ICE_AQ_CFG_PACING_M (0xF << ICE_AQ_CFG_PACING_S)
1564 #define ICE_AQ_CFG_PACING_TYPE_M BIT(7)
1565 #define ICE_AQ_CFG_PACING_TYPE_AVG 0
1566 #define ICE_AQ_CFG_PACING_TYPE_FIXED ICE_AQ_CFG_PACING_TYPE_M
1567 /* External Device Power Ability */
1569 #define ICE_AQ_PWR_CLASS_M 0x3F
1570 #define ICE_AQ_LINK_PWR_BASET_LOW_HIGH 0
1571 #define ICE_AQ_LINK_PWR_BASET_HIGH 1
1572 #define ICE_AQ_LINK_PWR_QSFP_CLASS_1 0
1573 #define ICE_AQ_LINK_PWR_QSFP_CLASS_2 1
1574 #define ICE_AQ_LINK_PWR_QSFP_CLASS_3 2
1575 #define ICE_AQ_LINK_PWR_QSFP_CLASS_4 3
1577 #define ICE_AQ_LINK_SPEED_M 0x7FF
1578 #define ICE_AQ_LINK_SPEED_10MB BIT(0)
1579 #define ICE_AQ_LINK_SPEED_100MB BIT(1)
1580 #define ICE_AQ_LINK_SPEED_1000MB BIT(2)
1581 #define ICE_AQ_LINK_SPEED_2500MB BIT(3)
1582 #define ICE_AQ_LINK_SPEED_5GB BIT(4)
1583 #define ICE_AQ_LINK_SPEED_10GB BIT(5)
1584 #define ICE_AQ_LINK_SPEED_20GB BIT(6)
1585 #define ICE_AQ_LINK_SPEED_25GB BIT(7)
1586 #define ICE_AQ_LINK_SPEED_40GB BIT(8)
1587 #define ICE_AQ_LINK_SPEED_50GB BIT(9)
1588 #define ICE_AQ_LINK_SPEED_100GB BIT(10)
1589 #define ICE_AQ_LINK_SPEED_UNKNOWN BIT(15)
1590 __le32 reserved3; /* Aligns next field to 8-byte boundary */
1591 __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */
1592 __le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */
1595 /* Set event mask command (direct 0x0613) */
1596 struct ice_aqc_set_event_mask {
1600 #define ICE_AQ_LINK_EVENT_UPDOWN BIT(1)
1601 #define ICE_AQ_LINK_EVENT_MEDIA_NA BIT(2)
1602 #define ICE_AQ_LINK_EVENT_LINK_FAULT BIT(3)
1603 #define ICE_AQ_LINK_EVENT_PHY_TEMP_ALARM BIT(4)
1604 #define ICE_AQ_LINK_EVENT_EXCESSIVE_ERRORS BIT(5)
1605 #define ICE_AQ_LINK_EVENT_SIGNAL_DETECT BIT(6)
1606 #define ICE_AQ_LINK_EVENT_AN_COMPLETED BIT(7)
1607 #define ICE_AQ_LINK_EVENT_MODULE_QUAL_FAIL BIT(8)
1608 #define ICE_AQ_LINK_EVENT_PORT_TX_SUSPENDED BIT(9)
1609 #define ICE_AQ_LINK_EVENT_TOPO_CONFLICT BIT(10)
1610 #define ICE_AQ_LINK_EVENT_MEDIA_CONFLICT BIT(11)
1614 /* Set MAC Loopback command (direct 0x0620) */
1615 struct ice_aqc_set_mac_lb {
1617 #define ICE_AQ_MAC_LB_EN BIT(0)
1618 #define ICE_AQ_MAC_LB_OSC_CLK BIT(1)
1622 struct ice_aqc_link_topo_params {
1625 #define ICE_AQC_LINK_TOPO_PORT_NUM_VALID BIT(0)
1627 #define ICE_AQC_LINK_TOPO_NODE_TYPE_S 0
1628 #define ICE_AQC_LINK_TOPO_NODE_TYPE_M (0xF << ICE_AQC_LINK_TOPO_NODE_TYPE_S)
1629 #define ICE_AQC_LINK_TOPO_NODE_TYPE_PHY 0
1630 #define ICE_AQC_LINK_TOPO_NODE_TYPE_GPIO_CTRL 1
1631 #define ICE_AQC_LINK_TOPO_NODE_TYPE_MUX_CTRL 2
1632 #define ICE_AQC_LINK_TOPO_NODE_TYPE_LED_CTRL 3
1633 #define ICE_AQC_LINK_TOPO_NODE_TYPE_LED 4
1634 #define ICE_AQC_LINK_TOPO_NODE_TYPE_THERMAL 5
1635 #define ICE_AQC_LINK_TOPO_NODE_TYPE_CAGE 6
1636 #define ICE_AQC_LINK_TOPO_NODE_TYPE_MEZZ 7
1637 #define ICE_AQC_LINK_TOPO_NODE_TYPE_ID_EEPROM 8
1638 #define ICE_AQC_LINK_TOPO_NODE_CTX_S 4
1639 #define ICE_AQC_LINK_TOPO_NODE_CTX_M \
1640 (0xF << ICE_AQC_LINK_TOPO_NODE_CTX_S)
1641 #define ICE_AQC_LINK_TOPO_NODE_CTX_GLOBAL 0
1642 #define ICE_AQC_LINK_TOPO_NODE_CTX_BOARD 1
1643 #define ICE_AQC_LINK_TOPO_NODE_CTX_PORT 2
1644 #define ICE_AQC_LINK_TOPO_NODE_CTX_NODE 3
1645 #define ICE_AQC_LINK_TOPO_NODE_CTX_PROVIDED 4
1646 #define ICE_AQC_LINK_TOPO_NODE_CTX_OVERRIDE 5
1650 struct ice_aqc_link_topo_addr {
1651 struct ice_aqc_link_topo_params topo_params;
1653 #define ICE_AQC_LINK_TOPO_HANDLE_S 0
1654 #define ICE_AQC_LINK_TOPO_HANDLE_M (0x3FF << ICE_AQC_LINK_TOPO_HANDLE_S)
1655 /* Used to decode the handle field */
1656 #define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_M BIT(9)
1657 #define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_LOM BIT(9)
1658 #define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_MEZZ 0
1659 #define ICE_AQC_LINK_TOPO_HANDLE_NODE_S 0
1660 /* In case of a Mezzanine type */
1661 #define ICE_AQC_LINK_TOPO_HANDLE_MEZZ_NODE_M \
1662 (0x3F << ICE_AQC_LINK_TOPO_HANDLE_NODE_S)
1663 #define ICE_AQC_LINK_TOPO_HANDLE_MEZZ_S 6
1664 #define ICE_AQC_LINK_TOPO_HANDLE_MEZZ_M (0x7 << ICE_AQC_LINK_TOPO_HANDLE_MEZZ_S)
1665 /* In case of a LOM type */
1666 #define ICE_AQC_LINK_TOPO_HANDLE_LOM_NODE_M \
1667 (0x1FF << ICE_AQC_LINK_TOPO_HANDLE_NODE_S)
1670 /* Get Link Topology Handle (direct, 0x06E0) */
1671 struct ice_aqc_get_link_topo {
1672 struct ice_aqc_link_topo_addr addr;
1674 #define ICE_ACQ_GET_LINK_TOPO_NODE_NR_PCA9575 0x21
1678 /* Read/Write I2C (direct, 0x06E2/0x06E3) */
1679 struct ice_aqc_i2c {
1680 struct ice_aqc_link_topo_addr topo_addr;
1683 #define ICE_AQC_I2C_DATA_SIZE_S 0
1684 #define ICE_AQC_I2C_DATA_SIZE_M (0xF << ICE_AQC_I2C_DATA_SIZE_S)
1685 #define ICE_AQC_I2C_ADDR_TYPE_M BIT(4)
1686 #define ICE_AQC_I2C_ADDR_TYPE_7BIT 0
1687 #define ICE_AQC_I2C_ADDR_TYPE_10BIT ICE_AQC_I2C_ADDR_TYPE_M
1688 #define ICE_AQC_I2C_DATA_OFFSET_S 5
1689 #define ICE_AQC_I2C_DATA_OFFSET_M (0x3 << ICE_AQC_I2C_DATA_OFFSET_S)
1690 #define ICE_AQC_I2C_USE_REPEATED_START BIT(7)
1692 __le16 i2c_bus_addr;
1693 #define ICE_AQC_I2C_ADDR_7BIT_MASK 0x7F
1694 #define ICE_AQC_I2C_ADDR_10BIT_MASK 0x3FF
1695 u8 i2c_data[4]; /* Used only by write command, reserved in read. */
1698 /* Read I2C Response (direct, 0x06E2) */
1699 struct ice_aqc_read_i2c_resp {
1703 /* Set Port Identification LED (direct, 0x06E9) */
1704 struct ice_aqc_set_port_id_led {
1707 #define ICE_AQC_PORT_ID_PORT_NUM_VALID BIT(0)
1709 #define ICE_AQC_PORT_IDENT_LED_BLINK BIT(0)
1710 #define ICE_AQC_PORT_IDENT_LED_ORIG 0
1714 /* Set/Get GPIO (direct, 0x06EC/0x06ED) */
1715 struct ice_aqc_gpio {
1716 __le16 gpio_ctrl_handle;
1717 #define ICE_AQC_GPIO_HANDLE_S 0
1718 #define ICE_AQC_GPIO_HANDLE_M (0x3FF << ICE_AQC_GPIO_HANDLE_S)
1724 /* Read/Write SFF EEPROM command (indirect 0x06EE) */
1725 struct ice_aqc_sff_eeprom {
1728 #define ICE_AQC_SFF_PORT_NUM_VALID BIT(0)
1729 __le16 i2c_bus_addr;
1730 #define ICE_AQC_SFF_I2CBUS_7BIT_M 0x7F
1731 #define ICE_AQC_SFF_I2CBUS_10BIT_M 0x3FF
1732 #define ICE_AQC_SFF_I2CBUS_TYPE_M BIT(10)
1733 #define ICE_AQC_SFF_I2CBUS_TYPE_7BIT 0
1734 #define ICE_AQC_SFF_I2CBUS_TYPE_10BIT ICE_AQC_SFF_I2CBUS_TYPE_M
1735 #define ICE_AQC_SFF_SET_EEPROM_PAGE_S 11
1736 #define ICE_AQC_SFF_SET_EEPROM_PAGE_M (0x3 << ICE_AQC_SFF_SET_EEPROM_PAGE_S)
1737 #define ICE_AQC_SFF_NO_PAGE_CHANGE 0
1738 #define ICE_AQC_SFF_SET_23_ON_MISMATCH 1
1739 #define ICE_AQC_SFF_SET_22_ON_MISMATCH 2
1740 #define ICE_AQC_SFF_IS_WRITE BIT(15)
1741 __le16 i2c_mem_addr;
1743 #define ICE_AQC_SFF_EEPROM_BANK_S 0
1744 #define ICE_AQC_SFF_EEPROM_BANK_M (0xFF << ICE_AQC_SFF_EEPROM_BANK_S)
1745 #define ICE_AQC_SFF_EEPROM_PAGE_S 8
1746 #define ICE_AQC_SFF_EEPROM_PAGE_M (0xFF << ICE_AQC_SFF_EEPROM_PAGE_S)
1751 /* SW Set GPIO command (indirect 0x6EF)
1752 * SW Get GPIO command (indirect 0x6F0)
1754 struct ice_aqc_sw_gpio {
1755 __le16 gpio_ctrl_handle;
1756 #define ICE_AQC_SW_GPIO_CONTROLLER_HANDLE_S 0
1757 #define ICE_AQC_SW_GPIO_CONTROLLER_HANDLE_M (0x3FF << ICE_AQC_SW_GPIO_CONTROLLER_HANDLE_S)
1759 #define ICE_AQC_SW_GPIO_NUMBER_S 0
1760 #define ICE_AQC_SW_GPIO_NUMBER_M (0x1F << ICE_AQC_SW_GPIO_NUMBER_S)
1762 #define ICE_AQC_SW_GPIO_PARAMS_DIRECTION BIT(1)
1763 #define ICE_AQC_SW_GPIO_PARAMS_VALUE BIT(0)
1767 /* Program Topology Device NVM (direct, 0x06F2) */
1768 struct ice_aqc_prog_topo_dev_nvm {
1769 struct ice_aqc_link_topo_params topo_params;
1773 /* Read Topology Device NVM (direct, 0x06F3) */
1774 struct ice_aqc_read_topo_dev_nvm {
1775 struct ice_aqc_link_topo_params topo_params;
1776 __le32 start_address;
1777 #define ICE_AQC_READ_TOPO_DEV_NVM_DATA_READ_SIZE 8
1778 u8 data_read[ICE_AQC_READ_TOPO_DEV_NVM_DATA_READ_SIZE];
1781 /* NVM Read command (indirect 0x0701)
1782 * NVM Erase commands (direct 0x0702)
1783 * NVM Write commands (indirect 0x0703)
1784 * NVM Write Activate commands (direct 0x0707)
1785 * NVM Shadow RAM Dump commands (direct 0x0707)
1787 struct ice_aqc_nvm {
1788 #define ICE_AQC_NVM_MAX_OFFSET 0xFFFFFF
1790 u8 offset_high; /* For Write Activate offset_high is used as flags2 */
1792 #define ICE_AQC_NVM_LAST_CMD BIT(0)
1793 #define ICE_AQC_NVM_PCIR_REQ BIT(0) /* Used by NVM Write reply */
1794 #define ICE_AQC_NVM_PRESERVATION_S 1 /* Used by NVM Write Activate only */
1795 #define ICE_AQC_NVM_PRESERVATION_M (3 << ICE_AQC_NVM_PRESERVATION_S)
1796 #define ICE_AQC_NVM_NO_PRESERVATION (0 << ICE_AQC_NVM_PRESERVATION_S)
1797 #define ICE_AQC_NVM_PRESERVE_ALL BIT(1)
1798 #define ICE_AQC_NVM_FACTORY_DEFAULT (2 << ICE_AQC_NVM_PRESERVATION_S)
1799 #define ICE_AQC_NVM_PRESERVE_SELECTED (3 << ICE_AQC_NVM_PRESERVATION_S)
1800 #define ICE_AQC_NVM_ACTIV_SEL_NVM BIT(3) /* Write Activate/SR Dump only */
1801 #define ICE_AQC_NVM_ACTIV_SEL_OROM BIT(4)
1802 #define ICE_AQC_NVM_ACTIV_SEL_NETLIST BIT(5)
1803 #define ICE_AQC_NVM_SPECIAL_UPDATE BIT(6)
1804 #define ICE_AQC_NVM_REVERT_LAST_ACTIV BIT(6) /* Write Activate only */
1805 #define ICE_AQC_NVM_ACTIV_SEL_MASK MAKEMASK(0x7, 3)
1806 #define ICE_AQC_NVM_FLASH_ONLY BIT(7)
1807 #define ICE_AQC_NVM_POR_FLAG 0 /* Used by NVM Write completion on ARQ */
1808 #define ICE_AQC_NVM_PERST_FLAG 1
1809 #define ICE_AQC_NVM_EMPR_FLAG 2
1810 #define ICE_AQC_NVM_EMPR_ENA BIT(0)
1811 __le16 module_typeid;
1813 #define ICE_AQC_NVM_ERASE_LEN 0xFFFF
1818 /* NVM Module_Type ID, needed offset and read_len for struct ice_aqc_nvm. */
1819 #define ICE_AQC_NVM_SECTOR_UNIT 4096 /* In Bytes */
1820 #define ICE_AQC_NVM_WORD_UNIT 2 /* In Bytes */
1822 #define ICE_AQC_NVM_START_POINT 0
1823 #define ICE_AQC_NVM_EMP_SR_PTR_OFFSET 0x90
1824 #define ICE_AQC_NVM_EMP_SR_PTR_RD_LEN 2 /* In Bytes */
1825 #define ICE_AQC_NVM_EMP_SR_PTR_M MAKEMASK(0x7FFF, 0)
1826 #define ICE_AQC_NVM_EMP_SR_PTR_TYPE_S 15
1827 #define ICE_AQC_NVM_EMP_SR_PTR_TYPE_M BIT(15)
1828 #define ICE_AQC_NVM_EMP_SR_PTR_TYPE_SECTOR 1
1830 #define ICE_AQC_NVM_LLDP_CFG_PTR_OFFSET 0x46
1831 #define ICE_AQC_NVM_LLDP_CFG_HEADER_LEN 2 /* In Bytes */
1832 #define ICE_AQC_NVM_LLDP_CFG_PTR_RD_LEN 2 /* In Bytes */
1834 #define ICE_AQC_NVM_LLDP_PRESERVED_MOD_ID 0x129
1835 #define ICE_AQC_NVM_CUR_LLDP_PERSIST_RD_OFFSET 2 /* In Bytes */
1836 #define ICE_AQC_NVM_LLDP_STATUS_M MAKEMASK(0xF, 0)
1837 #define ICE_AQC_NVM_LLDP_STATUS_M_LEN 4 /* In Bits */
1838 #define ICE_AQC_NVM_LLDP_STATUS_RD_LEN 4 /* In Bytes */
1840 /* Used for 0x0704 as well as for 0x0705 commands */
1841 struct ice_aqc_nvm_cfg {
1843 #define ICE_AQC_ANVM_MULTIPLE_ELEMS BIT(0)
1844 #define ICE_AQC_ANVM_IMMEDIATE_FIELD BIT(1)
1845 #define ICE_AQC_ANVM_NEW_CFG BIT(2)
1854 struct ice_aqc_nvm_cfg_data {
1856 __le16 field_options;
1860 /* NVM Checksum Command (direct, 0x0706) */
1861 struct ice_aqc_nvm_checksum {
1863 #define ICE_AQC_NVM_CHECKSUM_VERIFY BIT(0)
1864 #define ICE_AQC_NVM_CHECKSUM_RECALC BIT(1)
1866 __le16 checksum; /* Used only by response */
1867 #define ICE_AQC_NVM_CHECKSUM_CORRECT 0xBABA
1871 /* Get LLDP MIB (indirect 0x0A00)
1872 * Note: This is also used by the LLDP MIB Change Event (0x0A01)
1873 * as the format is the same.
1875 struct ice_aqc_lldp_get_mib {
1877 #define ICE_AQ_LLDP_MIB_TYPE_S 0
1878 #define ICE_AQ_LLDP_MIB_TYPE_M (0x3 << ICE_AQ_LLDP_MIB_TYPE_S)
1879 #define ICE_AQ_LLDP_MIB_LOCAL 0
1880 #define ICE_AQ_LLDP_MIB_REMOTE 1
1881 #define ICE_AQ_LLDP_MIB_LOCAL_AND_REMOTE 2
1882 #define ICE_AQ_LLDP_BRID_TYPE_S 2
1883 #define ICE_AQ_LLDP_BRID_TYPE_M (0x3 << ICE_AQ_LLDP_BRID_TYPE_S)
1884 #define ICE_AQ_LLDP_BRID_TYPE_NEAREST_BRID 0
1885 #define ICE_AQ_LLDP_BRID_TYPE_NON_TPMR 1
1886 /* Tx pause flags in the 0xA01 event use ICE_AQ_LLDP_TX_* */
1887 #define ICE_AQ_LLDP_TX_S 0x4
1888 #define ICE_AQ_LLDP_TX_M (0x03 << ICE_AQ_LLDP_TX_S)
1889 #define ICE_AQ_LLDP_TX_ACTIVE 0
1890 #define ICE_AQ_LLDP_TX_SUSPENDED 1
1891 #define ICE_AQ_LLDP_TX_FLUSHED 3
1892 /* The following bytes are reserved for the Get LLDP MIB command (0x0A00)
1893 * and in the LLDP MIB Change Event (0x0A01). They are valid for the
1894 * Get LLDP MIB (0x0A00) response only.
1904 /* Configure LLDP MIB Change Event (direct 0x0A01) */
1905 /* For MIB Change Event use ice_aqc_lldp_get_mib structure above */
1906 struct ice_aqc_lldp_set_mib_change {
1908 #define ICE_AQ_LLDP_MIB_UPDATE_ENABLE 0x0
1909 #define ICE_AQ_LLDP_MIB_UPDATE_DIS 0x1
1913 /* Add LLDP TLV (indirect 0x0A02)
1914 * Delete LLDP TLV (indirect 0x0A04)
1916 struct ice_aqc_lldp_add_delete_tlv {
1917 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */
1925 /* Update LLDP TLV (indirect 0x0A03) */
1926 struct ice_aqc_lldp_update_tlv {
1927 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */
1936 /* Stop LLDP (direct 0x0A05) */
1937 struct ice_aqc_lldp_stop {
1939 #define ICE_AQ_LLDP_AGENT_STATE_MASK BIT(0)
1940 #define ICE_AQ_LLDP_AGENT_STOP 0x0
1941 #define ICE_AQ_LLDP_AGENT_SHUTDOWN ICE_AQ_LLDP_AGENT_STATE_MASK
1942 #define ICE_AQ_LLDP_AGENT_PERSIST_DIS BIT(1)
1946 /* Start LLDP (direct 0x0A06) */
1947 struct ice_aqc_lldp_start {
1949 #define ICE_AQ_LLDP_AGENT_START BIT(0)
1950 #define ICE_AQ_LLDP_AGENT_PERSIST_ENA BIT(1)
1954 /* Get CEE DCBX Oper Config (0x0A07)
1955 * The command uses the generic descriptor struct and
1956 * returns the struct below as an indirect response.
1958 struct ice_aqc_get_cee_dcb_cfg_resp {
1963 __le16 oper_app_prio;
1964 #define ICE_AQC_CEE_APP_FCOE_S 0
1965 #define ICE_AQC_CEE_APP_FCOE_M (0x7 << ICE_AQC_CEE_APP_FCOE_S)
1966 #define ICE_AQC_CEE_APP_ISCSI_S 3
1967 #define ICE_AQC_CEE_APP_ISCSI_M (0x7 << ICE_AQC_CEE_APP_ISCSI_S)
1968 #define ICE_AQC_CEE_APP_FIP_S 8
1969 #define ICE_AQC_CEE_APP_FIP_M (0x7 << ICE_AQC_CEE_APP_FIP_S)
1971 #define ICE_AQC_CEE_PG_STATUS_S 0
1972 #define ICE_AQC_CEE_PG_STATUS_M (0x7 << ICE_AQC_CEE_PG_STATUS_S)
1973 #define ICE_AQC_CEE_PFC_STATUS_S 3
1974 #define ICE_AQC_CEE_PFC_STATUS_M (0x7 << ICE_AQC_CEE_PFC_STATUS_S)
1975 #define ICE_AQC_CEE_FCOE_STATUS_S 8
1976 #define ICE_AQC_CEE_FCOE_STATUS_M (0x7 << ICE_AQC_CEE_FCOE_STATUS_S)
1977 #define ICE_AQC_CEE_ISCSI_STATUS_S 11
1978 #define ICE_AQC_CEE_ISCSI_STATUS_M (0x7 << ICE_AQC_CEE_ISCSI_STATUS_S)
1979 #define ICE_AQC_CEE_FIP_STATUS_S 16
1980 #define ICE_AQC_CEE_FIP_STATUS_M (0x7 << ICE_AQC_CEE_FIP_STATUS_S)
1984 /* Set Local LLDP MIB (indirect 0x0A08)
1985 * Used to replace the local MIB of a given LLDP agent. e.g. DCBX
1987 struct ice_aqc_lldp_set_local_mib {
1989 #define SET_LOCAL_MIB_TYPE_DCBX_M BIT(0)
1990 #define SET_LOCAL_MIB_TYPE_LOCAL_MIB 0
1991 #define SET_LOCAL_MIB_TYPE_CEE_M BIT(1)
1992 #define SET_LOCAL_MIB_TYPE_CEE_WILLING 0
1993 #define SET_LOCAL_MIB_TYPE_CEE_NON_WILLING SET_LOCAL_MIB_TYPE_CEE_M
2001 struct ice_aqc_lldp_set_local_mib_resp {
2003 #define SET_LOCAL_MIB_RESP_EVENT_M BIT(0)
2004 #define SET_LOCAL_MIB_RESP_MIB_CHANGE_SILENT 0
2005 #define SET_LOCAL_MIB_RESP_MIB_CHANGE_EVENT SET_LOCAL_MIB_RESP_EVENT_M
2009 /* Stop/Start LLDP Agent (direct 0x0A09)
2010 * Used for stopping/starting specific LLDP agent. e.g. DCBX.
2011 * The same structure is used for the response, with the command field
2012 * being used as the status field.
2014 struct ice_aqc_lldp_stop_start_specific_agent {
2016 #define ICE_AQC_START_STOP_AGENT_M BIT(0)
2017 #define ICE_AQC_START_STOP_AGENT_STOP_DCBX 0
2018 #define ICE_AQC_START_STOP_AGENT_START_DCBX ICE_AQC_START_STOP_AGENT_M
2022 /* LLDP Filter Control (direct 0x0A0A) */
2023 struct ice_aqc_lldp_filter_ctrl {
2025 #define ICE_AQC_LLDP_FILTER_ACTION_M MAKEMASK(3, 0)
2026 #define ICE_AQC_LLDP_FILTER_ACTION_ADD 0x0
2027 #define ICE_AQC_LLDP_FILTER_ACTION_DELETE 0x1
2028 #define ICE_AQC_LLDP_FILTER_ACTION_UPDATE 0x2
2034 /* Get/Set RSS key (indirect 0x0B04/0x0B02) */
2035 struct ice_aqc_get_set_rss_key {
2036 #define ICE_AQC_GSET_RSS_KEY_VSI_VALID BIT(15)
2037 #define ICE_AQC_GSET_RSS_KEY_VSI_ID_S 0
2038 #define ICE_AQC_GSET_RSS_KEY_VSI_ID_M (0x3FF << ICE_AQC_GSET_RSS_KEY_VSI_ID_S)
2045 #define ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE 0x28
2046 #define ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE 0xC
2047 #define ICE_GET_SET_RSS_KEY_EXTEND_KEY_SIZE \
2048 (ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE + \
2049 ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE)
2052 * struct ice_aqc_get_set_rss_keys - Get/Set RSS hash key command buffer
2053 * @standard_rss_key: 40 most significant bytes of hash key
2054 * @extended_hash_key: 12 least significant bytes of hash key
2056 * Set/Get 40 byte hash key using standard_rss_key field, and set
2057 * extended_hash_key field to zero. Set/Get 52 byte hash key using
2058 * standard_rss_key field for 40 most significant bytes and the
2059 * extended_hash_key field for the 12 least significant bytes of hash key.
2061 struct ice_aqc_get_set_rss_keys {
2062 u8 standard_rss_key[ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE];
2063 u8 extended_hash_key[ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE];
2066 /* Get/Set RSS LUT (indirect 0x0B05/0x0B03) */
2067 struct ice_aqc_get_set_rss_lut {
2068 #define ICE_AQC_GSET_RSS_LUT_VSI_VALID BIT(15)
2069 #define ICE_AQC_GSET_RSS_LUT_VSI_ID_S 0
2070 #define ICE_AQC_GSET_RSS_LUT_VSI_ID_M (0x3FF << ICE_AQC_GSET_RSS_LUT_VSI_ID_S)
2072 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S 0
2073 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_M \
2074 (0x3 << ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S)
2076 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_VSI 0
2077 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF 1
2078 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL 2
2080 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S 2
2081 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M \
2082 (0x3 << ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S)
2084 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128 128
2085 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128_FLAG 0
2086 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512 512
2087 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512_FLAG 1
2088 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K 2048
2089 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K_FLAG 2
2091 #define ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S 4
2092 #define ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_M \
2093 (0xF << ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S)
2101 /* Clear FD Table Command (direct, 0x0B06) */
2102 struct ice_aqc_clear_fd_table {
2104 #define CL_FD_VM_VF_TYPE_VSI_IDX 1
2105 #define CL_FD_VM_VF_TYPE_PF_IDX 2
2111 /* Allocate ACL table (indirect 0x0C10) */
2112 #define ICE_AQC_ACL_KEY_WIDTH 40
2113 #define ICE_AQC_ACL_KEY_WIDTH_BYTES 5
2114 #define ICE_AQC_ACL_TCAM_DEPTH 512
2115 #define ICE_ACL_ENTRY_ALLOC_UNIT 64
2116 #define ICE_AQC_MAX_CONCURRENT_ACL_TBL 15
2117 #define ICE_AQC_MAX_ACTION_MEMORIES 20
2118 #define ICE_AQC_MAX_ACTION_ENTRIES 512
2119 #define ICE_AQC_ACL_SLICES 16
2120 #define ICE_AQC_ALLOC_ID_LESS_THAN_4K 0x1000
2121 /* The ACL block supports up to 8 actions per a single output. */
2122 #define ICE_AQC_TBL_MAX_ACTION_PAIRS 4
2124 #define ICE_AQC_MAX_TCAM_ALLOC_UNITS (ICE_AQC_ACL_TCAM_DEPTH / \
2125 ICE_ACL_ENTRY_ALLOC_UNIT)
2126 #define ICE_AQC_ACL_ALLOC_UNITS (ICE_AQC_ACL_SLICES * \
2127 ICE_AQC_MAX_TCAM_ALLOC_UNITS)
2129 struct ice_aqc_acl_alloc_table {
2132 u8 act_pairs_per_entry;
2133 /* For non-concurrent table allocation, this field needs
2134 * to be set to zero(0) otherwise it shall specify the
2135 * amount of concurrent tables whose AllocIDs are
2136 * specified in buffer. Thus the newly allocated table
2137 * is concurrent with table IDs specified in AllocIDs.
2139 #define ICE_AQC_ACL_ALLOC_TABLE_TYPE_NONCONCURR 0
2146 /* Allocate ACL table command buffer format */
2147 struct ice_aqc_acl_alloc_table_data {
2148 /* Dependent table AllocIDs. Each word in this 15 word array specifies
2149 * a dependent table AllocID according to the amount specified in the
2150 * "table_type" field. All unused words shall be set to 0xFFFF
2152 #define ICE_AQC_CONCURR_ID_INVALID 0xffff
2153 __le16 alloc_ids[ICE_AQC_MAX_CONCURRENT_ACL_TBL];
2156 /* Deallocate ACL table (indirect 0x0C11)
2157 * Allocate ACL action-pair (indirect 0x0C12)
2158 * Deallocate ACL action-pair (indirect 0x0C13)
2161 /* Following structure is common and used in case of deallocation
2162 * of ACL table and action-pair
2164 struct ice_aqc_acl_tbl_actpair {
2165 /* Alloc ID of the table being released */
2172 /* This response structure is same in case of alloc/dealloc table,
2173 * alloc/dealloc action-pair
2175 struct ice_aqc_acl_generic {
2176 /* if alloc_id is below 0x1000 then alllocation failed due to
2177 * unavailable resources, else this is set by FW to identify
2183 /* to be used only in case of alloc/dealloc table */
2185 /* Index of the first TCAM block, otherwise set to 0xFF
2186 * for a failed allocation
2189 /* Index of the last TCAM block. This index shall be
2190 * set to the value of first_tcam for single TCAM block
2191 * allocation, otherwise set to 0xFF for a failed
2196 /* reserved in case of alloc/dealloc action-pair */
2202 /* index of first entry (in both TCAM and action memories),
2203 * otherwise set to 0xFF for a failed allocation
2206 /* index of last entry (in both TCAM and action memories),
2207 * otherwise set to 0xFF for a failed allocation
2211 /* Each act_mem element specifies the order of the memory
2214 u8 act_mem[ICE_AQC_MAX_ACTION_MEMORIES];
2217 /* Allocate ACL scenario (indirect 0x0C14). This command doesn't have separate
2218 * response buffer since original command buffer gets updated with
2219 * 'scen_id' in case of success
2221 struct ice_aqc_acl_alloc_scen {
2235 /* De-allocate ACL scenario (direct 0x0C15). This command doesn't need
2236 * separate response buffer since nothing to be returned as a response
2239 struct ice_aqc_acl_dealloc_scen {
2244 /* Update ACL scenario (direct 0x0C1B)
2245 * Query ACL scenario (direct 0x0C23)
2247 struct ice_aqc_acl_update_query_scen {
2254 /* Input buffer format in case allocate/update ACL scenario and same format
2255 * is used for response buffer in case of query ACL scenario.
2256 * NOTE: de-allocate ACL scenario is direct command and doesn't require
2257 * "buffer", hence no buffer format.
2259 struct ice_aqc_acl_scen {
2261 /* Byte [x] selection for the TCAM key. This value must be
2262 * set to 0x0 for unusued TCAM.
2263 * Only Bit 6..0 is used in each byte and MSB is reserved
2265 #define ICE_AQC_ACL_ALLOC_SCE_SELECT_M 0x7F
2266 #define ICE_AQC_ACL_BYTE_SEL_BASE 0x20
2267 #define ICE_AQC_ACL_BYTE_SEL_BASE_PID 0x3E
2268 #define ICE_AQC_ACL_BYTE_SEL_BASE_PKT_DIR ICE_AQC_ACL_BYTE_SEL_BASE
2269 #define ICE_AQC_ACL_BYTE_SEL_BASE_RNG_CHK 0x3F
2271 /* TCAM Block entry masking. This value should be set to 0x0 for
2275 /* Bit 0 : masks TCAM entries 0-63
2276 * Bit 1 : masks TCAM entries 64-127
2277 * Bit 2 to 7 : follow the pattern of bit 0 and 1
2279 #define ICE_AQC_ACL_ALLOC_SCE_START_CMP BIT(0)
2280 #define ICE_AQC_ACL_ALLOC_SCE_START_SET BIT(1)
2283 } tcam_cfg[ICE_AQC_ACL_SLICES];
2285 /* Each byte, Bit 6..0: Action memory association to a TCAM block,
2286 * otherwise it shall be set to 0x0 for disabled memory action.
2287 * Bit 7 : Action memory enable for this scenario
2289 #define ICE_AQC_ACL_SCE_ACT_MEM_TCAM_ASSOC_M 0x7F
2290 #define ICE_AQC_ACL_SCE_ACT_MEM_EN BIT(7)
2291 u8 act_mem_cfg[ICE_AQC_MAX_ACTION_MEMORIES];
2294 /* Allocate ACL counters (indirect 0x0C16) */
2295 struct ice_aqc_acl_alloc_counters {
2296 /* Amount of contiguous counters requested. Min value is 1 and
2299 #define ICE_AQC_ACL_ALLOC_CNT_MIN_AMT 0x1
2300 #define ICE_AQC_ACL_ALLOC_CNT_MAX_AMT 0xFF
2303 /* Counter type: 'single counter' which can be configured to count
2304 * either bytes or packets
2306 #define ICE_AQC_ACL_CNT_TYPE_SINGLE 0x0
2308 /* Counter type: 'counter pair' which counts number of bytes and number
2311 #define ICE_AQC_ACL_CNT_TYPE_DUAL 0x1
2312 /* requested counter type, single/dual */
2315 /* counter bank allocation shall be 0-3 for 'byte or packet counter' */
2316 #define ICE_AQC_ACL_MAX_CNT_SINGLE 0x3
2317 /* counter bank allocation shall be 0-1 for 'byte and packet counter dual' */
2318 #define ICE_AQC_ACL_MAX_CNT_DUAL 0x1
2319 /* requested counter bank allocation */
2325 /* Applicable only in case of command */
2329 /* Applicable only in case of response */
2330 #define ICE_AQC_ACL_ALLOC_CNT_INVAL 0xFFFF
2332 /* Index of first allocated counter. 0xFFFF in case
2333 * of unsuccessful allocation
2335 __le16 first_counter;
2336 /* Index of last allocated counter. 0xFFFF in case
2337 * of unsuccessful allocation
2339 __le16 last_counter;
2345 /* De-allocate ACL counters (direct 0x0C17) */
2346 struct ice_aqc_acl_dealloc_counters {
2347 /* first counter being released */
2348 __le16 first_counter;
2349 /* last counter being released */
2350 __le16 last_counter;
2351 /* requested counter type, single/dual */
2353 /* requested counter bank allocation */
2358 /* De-allocate ACL resources (direct 0x0C1A). Used by SW to release all the
2359 * resources allocated for it using a single command
2361 struct ice_aqc_acl_dealloc_res {
2365 /* Program ACL actionpair (indirect 0x0C1C)
2366 * Query ACL actionpair (indirect 0x0C25)
2368 struct ice_aqc_acl_actpair {
2369 /* action mem index to program/update */
2372 /* The entry index in action memory to be programmed/updated */
2373 __le16 act_entry_index;
2379 /* Input buffer format for program/query action-pair admin command */
2380 struct ice_acl_act_entry {
2381 /* Action priority, values must be between 0..7 */
2382 #define ICE_AQC_ACT_PRIO_VALID_MAX 7
2383 #define ICE_AQC_ACT_PRIO_MSK MAKEMASK(0xff, 0)
2385 /* Action meta-data identifier. This field should be set to 0x0
2388 #define ICE_AQC_ACT_MDID_S 8
2389 #define ICE_AQC_ACT_MDID_MSK MAKEMASK(0xff00, ICE_AQC_ACT_MDID_S)
2392 #define ICE_AQC_ACT_VALUE_S 16
2393 #define ICE_AQC_ACT_VALUE_MSK MAKEMASK(0xffff0000, 16)
2397 #define ICE_ACL_NUM_ACT_PER_ACT_PAIR 2
2398 struct ice_aqc_actpair {
2399 struct ice_acl_act_entry act[ICE_ACL_NUM_ACT_PER_ACT_PAIR];
2402 /* Generic format used to describe either input or response buffer
2403 * for admin commands related to ACL profile
2405 struct ice_aqc_acl_prof_generic_frmt {
2406 /* The first byte of the byte selection base is reserved to keep the
2407 * first byte of the field vector where the packet direction info is
2408 * available. Thus we should start at index 1 of the field vector to
2409 * map its entries to the byte selection base.
2411 #define ICE_AQC_ACL_PROF_BYTE_SEL_START_IDX 1
2413 * Bit 0..5 = Byte selection for the byte selection base from the
2414 * extracted fields (expressed as byte offset in extracted fields).
2415 * Applicable values are 0..63
2416 * Bit 6..7 = Reserved
2418 #define ICE_AQC_ACL_PROF_BYTE_SEL_ELEMS 30
2419 u8 byte_selection[ICE_AQC_ACL_PROF_BYTE_SEL_ELEMS];
2421 * Bit 0..4 = Word selection for the word selection base from the
2422 * extracted fields (expressed as word offset in extracted fields).
2423 * Applicable values are 0..31
2424 * Bit 5..7 = Reserved
2426 #define ICE_AQC_ACL_PROF_WORD_SEL_ELEMS 32
2427 u8 word_selection[ICE_AQC_ACL_PROF_WORD_SEL_ELEMS];
2429 * Bit 0..3 = Double word selection for the double-word selection base
2430 * from the extracted fields (expressed as double-word offset in
2431 * extracted fields).
2432 * Applicable values are 0..15
2433 * Bit 4..7 = Reserved
2435 #define ICE_AQC_ACL_PROF_DWORD_SEL_ELEMS 15
2436 u8 dword_selection[ICE_AQC_ACL_PROF_DWORD_SEL_ELEMS];
2437 /* Scenario numbers for individual Physical Function's */
2438 #define ICE_AQC_ACL_PROF_PF_SCEN_NUM_ELEMS 8
2439 u8 pf_scenario_num[ICE_AQC_ACL_PROF_PF_SCEN_NUM_ELEMS];
2442 /* Program ACL profile extraction (indirect 0x0C1D)
2443 * Program ACL profile ranges (indirect 0x0C1E)
2444 * Query ACL profile (indirect 0x0C21)
2445 * Query ACL profile ranges (indirect 0x0C22)
2447 struct ice_aqc_acl_profile {
2448 u8 profile_id; /* Programmed/Updated profile ID */
2454 /* Input buffer format for program profile extraction admin command and
2455 * response buffer format for query profile admin command is as defined
2456 * in struct ice_aqc_acl_prof_generic_frmt
2459 /* Input buffer format for program profile ranges and query profile ranges
2460 * admin commands. Same format is used for response buffer in case of query
2461 * profile ranges command
2463 struct ice_acl_rng_data {
2464 /* The range checker output shall be sent when the value
2465 * related to this range checker is lower than low boundary
2467 __be16 low_boundary;
2468 /* The range checker output shall be sent when the value
2469 * related to this range checker is higher than high boundary
2471 __be16 high_boundary;
2472 /* A value of '0' in bit shall clear the relevant bit input
2473 * to the range checker
2478 struct ice_aqc_acl_profile_ranges {
2479 #define ICE_AQC_ACL_PROF_RANGES_NUM_CFG 8
2480 struct ice_acl_rng_data checker_cfg[ICE_AQC_ACL_PROF_RANGES_NUM_CFG];
2483 /* Program ACL entry (indirect 0x0C20)
2484 * Query ACL entry (indirect 0x0C24)
2486 struct ice_aqc_acl_entry {
2487 u8 tcam_index; /* Updated TCAM block index */
2489 __le16 entry_index; /* Updated entry index */
2495 /* Input buffer format in case of program ACL entry and response buffer format
2496 * in case of query ACL entry
2498 struct ice_aqc_acl_data {
2499 /* Entry key and entry key invert are 40 bits wide.
2500 * Byte 0..4 : entry key and Byte 5..7 are reserved
2501 * Byte 8..12: entry key invert and Byte 13..15 are reserved
2506 } entry_key, entry_key_invert;
2509 /* Query ACL counter (direct 0x0C27) */
2510 struct ice_aqc_acl_query_counter {
2511 /* Queried counter index */
2512 __le16 counter_index;
2513 /* Queried counter bank */
2520 /* Holds counter value/packet counter value */
2527 /* Add Tx LAN Queues (indirect 0x0C30) */
2528 struct ice_aqc_add_txqs {
2536 /* This is the descriptor of each queue entry for the Add Tx LAN Queues
2537 * command (0x0C30). Only used within struct ice_aqc_add_tx_qgrp.
2539 struct ice_aqc_add_txqs_perq {
2545 struct ice_aqc_txsched_elem info;
2548 /* The format of the command buffer for Add Tx LAN Queues (0x0C30)
2549 * is an array of the following structs. Please note that the length of
2550 * each struct ice_aqc_add_tx_qgrp is variable due
2551 * to the variable number of queues in each group!
2553 struct ice_aqc_add_tx_qgrp {
2557 struct ice_aqc_add_txqs_perq txqs[STRUCT_HACK_VAR_LEN];
2560 /* Disable Tx LAN Queues (indirect 0x0C31) */
2561 struct ice_aqc_dis_txqs {
2563 #define ICE_AQC_Q_DIS_CMD_S 0
2564 #define ICE_AQC_Q_DIS_CMD_M (0x3 << ICE_AQC_Q_DIS_CMD_S)
2565 #define ICE_AQC_Q_DIS_CMD_NO_FUNC_RESET (0 << ICE_AQC_Q_DIS_CMD_S)
2566 #define ICE_AQC_Q_DIS_CMD_VM_RESET BIT(ICE_AQC_Q_DIS_CMD_S)
2567 #define ICE_AQC_Q_DIS_CMD_VF_RESET (2 << ICE_AQC_Q_DIS_CMD_S)
2568 #define ICE_AQC_Q_DIS_CMD_PF_RESET (3 << ICE_AQC_Q_DIS_CMD_S)
2569 #define ICE_AQC_Q_DIS_CMD_SUBSEQ_CALL BIT(2)
2570 #define ICE_AQC_Q_DIS_CMD_FLUSH_PIPE BIT(3)
2572 __le16 vmvf_and_timeout;
2573 #define ICE_AQC_Q_DIS_VMVF_NUM_S 0
2574 #define ICE_AQC_Q_DIS_VMVF_NUM_M (0x3FF << ICE_AQC_Q_DIS_VMVF_NUM_S)
2575 #define ICE_AQC_Q_DIS_TIMEOUT_S 10
2576 #define ICE_AQC_Q_DIS_TIMEOUT_M (0x3F << ICE_AQC_Q_DIS_TIMEOUT_S)
2577 __le32 blocked_cgds;
2582 /* The buffer for Disable Tx LAN Queues (indirect 0x0C31)
2583 * contains the following structures, arrayed one after the
2585 * Note: Since the q_id is 16 bits wide, if the
2586 * number of queues is even, then 2 bytes of alignment MUST be
2587 * added before the start of the next group, to allow correct
2588 * alignment of the parent_teid field.
2591 struct ice_aqc_dis_txq_item {
2595 /* The length of the q_id array varies according to num_qs */
2596 #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S 15
2597 #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_LAN_Q \
2598 (0 << ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S)
2599 #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_RDMA_QSET \
2600 (1 << ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S)
2601 __le16 q_id[STRUCT_HACK_VAR_LEN];
2606 /* Tx LAN Queues Cleanup Event (0x0C31) */
2607 struct ice_aqc_txqs_cleanup {
2613 /* Move / Reconfigure Tx Queues (indirect 0x0C32) */
2614 struct ice_aqc_move_txqs {
2616 #define ICE_AQC_Q_CMD_TYPE_S 0
2617 #define ICE_AQC_Q_CMD_TYPE_M (0x3 << ICE_AQC_Q_CMD_TYPE_S)
2618 #define ICE_AQC_Q_CMD_TYPE_MOVE 1
2619 #define ICE_AQC_Q_CMD_TYPE_TC_CHANGE 2
2620 #define ICE_AQC_Q_CMD_TYPE_MOVE_AND_TC 3
2621 #define ICE_AQC_Q_CMD_SUBSEQ_CALL BIT(2)
2622 #define ICE_AQC_Q_CMD_FLUSH_PIPE BIT(3)
2626 #define ICE_AQC_Q_CMD_TIMEOUT_S 2
2627 #define ICE_AQC_Q_CMD_TIMEOUT_M (0x3F << ICE_AQC_Q_CMD_TIMEOUT_S)
2628 __le32 blocked_cgds;
2633 /* Per-queue data buffer for the Move Tx LAN Queues command/response */
2634 struct ice_aqc_move_txqs_elem {
2641 /* Indirect data buffer for the Move Tx LAN Queues command/response */
2642 struct ice_aqc_move_txqs_data {
2645 struct ice_aqc_move_txqs_elem txqs[STRUCT_HACK_VAR_LEN];
2648 /* Download Package (indirect 0x0C40) */
2649 /* Also used for Update Package (indirect 0x0C42 and 0x0C41) */
2650 struct ice_aqc_download_pkg {
2652 #define ICE_AQC_DOWNLOAD_PKG_LAST_BUF 0x01
2659 struct ice_aqc_download_pkg_resp {
2660 __le32 error_offset;
2666 /* Get Package Info List (indirect 0x0C43) */
2667 struct ice_aqc_get_pkg_info_list {
2674 /* Version format for packages */
2675 struct ice_pkg_ver {
2682 #define ICE_PKG_NAME_SIZE 32
2683 #define ICE_SEG_ID_SIZE 28
2684 #define ICE_SEG_NAME_SIZE 28
2686 struct ice_aqc_get_pkg_info {
2687 struct ice_pkg_ver ver;
2688 char name[ICE_SEG_NAME_SIZE];
2692 u8 is_active_at_boot;
2696 /* Get Package Info List response buffer format (0x0C43) */
2697 struct ice_aqc_get_pkg_info_resp {
2699 struct ice_aqc_get_pkg_info pkg_info[STRUCT_HACK_VAR_LEN];
2702 /* Driver Shared Parameters (direct, 0x0C90) */
2703 struct ice_aqc_driver_shared_params {
2705 #define ICE_AQC_DRIVER_PARAM_OP_MASK BIT(0)
2706 #define ICE_AQC_DRIVER_PARAM_SET 0
2707 #define ICE_AQC_DRIVER_PARAM_GET 1
2709 #define ICE_AQC_DRIVER_PARAM_MAX_IDX 15
2716 /* Lan Queue Overflow Event (direct, 0x1001) */
2717 struct ice_aqc_event_lan_overflow {
2718 __le32 prtdcb_ruptq;
2723 /* Debug Dump Internal Data (indirect 0xFF08) */
2724 struct ice_aqc_debug_dump_internals {
2726 #define ICE_AQC_DBG_DUMP_CLUSTER_ID_SW 0
2727 #define ICE_AQC_DBG_DUMP_CLUSTER_ID_ACL 1
2728 #define ICE_AQC_DBG_DUMP_CLUSTER_ID_TXSCHED 2
2729 #define ICE_AQC_DBG_DUMP_CLUSTER_ID_PROFILES 3
2730 /* EMP_DRAM only dumpable in device debug mode */
2731 #define ICE_AQC_DBG_DUMP_CLUSTER_ID_EMP_DRAM 4
2732 #define ICE_AQC_DBG_DUMP_CLUSTER_ID_LINK 5
2733 /* AUX_REGS only dumpable in device debug mode */
2734 #define ICE_AQC_DBG_DUMP_CLUSTER_ID_AUX_REGS 6
2735 #define ICE_AQC_DBG_DUMP_CLUSTER_ID_DCB 7
2736 #define ICE_AQC_DBG_DUMP_CLUSTER_ID_L2P 8
2738 __le16 table_id; /* Used only for non-memory clusters */
2739 __le32 idx; /* In table entries for tables, in bytes for memory */
2744 /* Set Health Status (direct 0xFF20) */
2745 struct ice_aqc_set_health_status_config {
2747 #define ICE_AQC_HEALTH_STATUS_SET_PF_SPECIFIC_MASK BIT(0)
2748 #define ICE_AQC_HEALTH_STATUS_SET_ALL_PF_MASK BIT(1)
2749 #define ICE_AQC_HEALTH_STATUS_SET_GLOBAL_MASK BIT(2)
2753 #define ICE_AQC_HEALTH_STATUS_ERR_UNKNOWN_MOD_STRICT 0x101
2754 #define ICE_AQC_HEALTH_STATUS_ERR_MOD_TYPE 0x102
2755 #define ICE_AQC_HEALTH_STATUS_ERR_MOD_QUAL 0x103
2756 #define ICE_AQC_HEALTH_STATUS_ERR_MOD_COMM 0x104
2757 #define ICE_AQC_HEALTH_STATUS_ERR_MOD_CONFLICT 0x105
2758 #define ICE_AQC_HEALTH_STATUS_ERR_MOD_NOT_PRESENT 0x106
2759 #define ICE_AQC_HEALTH_STATUS_INFO_MOD_UNDERUTILIZED 0x107
2760 #define ICE_AQC_HEALTH_STATUS_ERR_UNKNOWN_MOD_LENIENT 0x108
2761 #define ICE_AQC_HEALTH_STATUS_ERR_INVALID_LINK_CFG 0x10B
2762 #define ICE_AQC_HEALTH_STATUS_ERR_PORT_ACCESS 0x10C
2763 #define ICE_AQC_HEALTH_STATUS_ERR_PORT_UNREACHABLE 0x10D
2764 #define ICE_AQC_HEALTH_STATUS_INFO_PORT_SPEED_MOD_LIMITED 0x10F
2765 #define ICE_AQC_HEALTH_STATUS_ERR_PARALLEL_FAULT 0x110
2766 #define ICE_AQC_HEALTH_STATUS_INFO_PORT_SPEED_PHY_LIMITED 0x111
2767 #define ICE_AQC_HEALTH_STATUS_ERR_NETLIST_TOPO 0x112
2768 #define ICE_AQC_HEALTH_STATUS_ERR_NETLIST 0x113
2769 #define ICE_AQC_HEALTH_STATUS_ERR_TOPO_CONFLICT 0x114
2770 #define ICE_AQC_HEALTH_STATUS_ERR_LINK_HW_ACCESS 0x115
2771 #define ICE_AQC_HEALTH_STATUS_ERR_LINK_RUNTIME 0x116
2772 #define ICE_AQC_HEALTH_STATUS_ERR_DNL_INIT 0x117
2773 #define ICE_AQC_HEALTH_STATUS_ERR_PHY_NVM_PROG 0x120
2774 #define ICE_AQC_HEALTH_STATUS_ERR_PHY_FW_LOAD 0x121
2775 #define ICE_AQC_HEALTH_STATUS_INFO_RECOVERY 0x500
2776 #define ICE_AQC_HEALTH_STATUS_ERR_FLASH_ACCESS 0x501
2777 #define ICE_AQC_HEALTH_STATUS_ERR_NVM_AUTH 0x502
2778 #define ICE_AQC_HEALTH_STATUS_ERR_OROM_AUTH 0x503
2779 #define ICE_AQC_HEALTH_STATUS_ERR_DDP_AUTH 0x504
2780 #define ICE_AQC_HEALTH_STATUS_ERR_NVM_COMPAT 0x505
2781 #define ICE_AQC_HEALTH_STATUS_ERR_OROM_COMPAT 0x506
2782 #define ICE_AQC_HEALTH_STATUS_ERR_DCB_MIB 0x509
2784 /* Get Health Status codes (indirect 0xFF21) */
2785 struct ice_aqc_get_supported_health_status_codes {
2786 __le16 health_code_count;
2792 /* Get Health Status (indirect 0xFF22) */
2793 struct ice_aqc_get_health_status {
2794 __le16 health_status_count;
2800 /* Get Health Status event buffer entry, (0xFF22)
2801 * repeated per reported health status
2803 struct ice_aqc_health_status_elem {
2804 __le16 health_status_code;
2805 __le16 event_source;
2806 #define ICE_AQC_HEALTH_STATUS_PF (0x1)
2807 #define ICE_AQC_HEALTH_STATUS_PORT (0x2)
2808 #define ICE_AQC_HEALTH_STATUS_GLOBAL (0x3)
2809 __le32 internal_data1;
2810 #define ICE_AQC_HEALTH_STATUS_UNDEFINED_DATA (0xDEADBEEF)
2811 __le32 internal_data2;
2814 /* Clear Health Status (direct 0xFF23) */
2815 struct ice_aqc_clear_health_status {
2820 * struct ice_aq_desc - Admin Queue (AQ) descriptor
2821 * @flags: ICE_AQ_FLAG_* flags
2822 * @opcode: AQ command opcode
2823 * @datalen: length in bytes of indirect/external data buffer
2824 * @retval: return value from firmware
2825 * @cookie_high: opaque data high-half
2826 * @cookie_low: opaque data low-half
2827 * @params: command-specific parameters
2829 * Descriptor format for commands the driver posts on the Admin Transmit Queue
2830 * (ATQ). The firmware writes back onto the command descriptor and returns
2831 * the result of the command. Asynchronous events that are not an immediate
2832 * result of the command are written to the Admin Receive Queue (ARQ) using
2833 * the same descriptor format. Descriptors are in little-endian notation with
2836 struct ice_aq_desc {
2845 struct ice_aqc_generic generic;
2846 struct ice_aqc_get_ver get_ver;
2847 struct ice_aqc_driver_ver driver_ver;
2848 struct ice_aqc_q_shutdown q_shutdown;
2849 struct ice_aqc_req_res res_owner;
2850 struct ice_aqc_manage_mac_read mac_read;
2851 struct ice_aqc_manage_mac_write mac_write;
2852 struct ice_aqc_clear_pxe clear_pxe;
2853 struct ice_aqc_config_no_drop_policy no_drop;
2854 struct ice_aqc_add_update_mir_rule add_update_rule;
2855 struct ice_aqc_delete_mir_rule del_rule;
2856 struct ice_aqc_list_caps get_cap;
2857 struct ice_aqc_get_phy_caps get_phy;
2858 struct ice_aqc_set_phy_cfg set_phy;
2859 struct ice_aqc_restart_an restart_an;
2860 struct ice_aqc_i2c read_write_i2c;
2861 struct ice_aqc_read_i2c_resp read_i2c_resp;
2862 struct ice_aqc_gpio read_write_gpio;
2863 struct ice_aqc_sw_gpio sw_read_write_gpio;
2864 struct ice_aqc_sff_eeprom read_write_sff_param;
2865 struct ice_aqc_set_port_id_led set_port_id_led;
2866 struct ice_aqc_get_sw_cfg get_sw_conf;
2867 struct ice_aqc_set_port_params set_port_params;
2868 struct ice_aqc_sw_rules sw_rules;
2869 struct ice_aqc_storm_cfg storm_conf;
2870 struct ice_aqc_add_get_recipe add_get_recipe;
2871 struct ice_aqc_recipe_to_profile recipe_to_profile;
2872 struct ice_aqc_get_topo get_topo;
2873 struct ice_aqc_sched_elem_cmd sched_elem_cmd;
2874 struct ice_aqc_query_txsched_res query_sched_res;
2875 struct ice_aqc_query_node_to_root query_node_to_root;
2876 struct ice_aqc_cfg_l2_node_cgd cfg_l2_node_cgd;
2877 struct ice_aqc_query_port_ets port_ets;
2878 struct ice_aqc_rl_profile rl_profile;
2879 struct ice_aqc_nvm nvm;
2880 struct ice_aqc_nvm_cfg nvm_cfg;
2881 struct ice_aqc_nvm_checksum nvm_checksum;
2882 struct ice_aqc_pfc_ignore pfc_ignore;
2883 struct ice_aqc_set_query_pfc_mode set_query_pfc_mode;
2884 struct ice_aqc_set_dcb_params set_dcb_params;
2885 struct ice_aqc_lldp_get_mib lldp_get_mib;
2886 struct ice_aqc_lldp_set_mib_change lldp_set_event;
2887 struct ice_aqc_lldp_add_delete_tlv lldp_add_delete_tlv;
2888 struct ice_aqc_lldp_update_tlv lldp_update_tlv;
2889 struct ice_aqc_lldp_stop lldp_stop;
2890 struct ice_aqc_lldp_start lldp_start;
2891 struct ice_aqc_lldp_set_local_mib lldp_set_mib;
2892 struct ice_aqc_lldp_stop_start_specific_agent lldp_agent_ctrl;
2893 struct ice_aqc_lldp_filter_ctrl lldp_filter_ctrl;
2894 struct ice_aqc_get_set_rss_lut get_set_rss_lut;
2895 struct ice_aqc_get_set_rss_key get_set_rss_key;
2896 struct ice_aqc_clear_fd_table clear_fd_table;
2897 struct ice_aqc_acl_alloc_table alloc_table;
2898 struct ice_aqc_acl_tbl_actpair tbl_actpair;
2899 struct ice_aqc_acl_alloc_scen alloc_scen;
2900 struct ice_aqc_acl_dealloc_scen dealloc_scen;
2901 struct ice_aqc_acl_update_query_scen update_query_scen;
2902 struct ice_aqc_acl_alloc_counters alloc_counters;
2903 struct ice_aqc_acl_dealloc_counters dealloc_counters;
2904 struct ice_aqc_acl_dealloc_res dealloc_res;
2905 struct ice_aqc_acl_entry program_query_entry;
2906 struct ice_aqc_acl_actpair program_query_actpair;
2907 struct ice_aqc_acl_profile profile;
2908 struct ice_aqc_acl_query_counter query_counter;
2909 struct ice_aqc_add_txqs add_txqs;
2910 struct ice_aqc_dis_txqs dis_txqs;
2911 struct ice_aqc_move_txqs move_txqs;
2912 struct ice_aqc_txqs_cleanup txqs_cleanup;
2913 struct ice_aqc_add_get_update_free_vsi vsi_cmd;
2914 struct ice_aqc_add_update_free_vsi_resp add_update_free_vsi_res;
2915 struct ice_aqc_get_vsi_resp get_vsi_resp;
2916 struct ice_aqc_download_pkg download_pkg;
2917 struct ice_aqc_get_pkg_info_list get_pkg_info_list;
2918 struct ice_aqc_driver_shared_params drv_shared_params;
2919 struct ice_aqc_debug_dump_internals debug_dump;
2920 struct ice_aqc_set_mac_lb set_mac_lb;
2921 struct ice_aqc_alloc_free_res_cmd sw_res_ctrl;
2922 struct ice_aqc_get_res_alloc get_res;
2923 struct ice_aqc_get_allocd_res_desc get_res_desc;
2924 struct ice_aqc_set_mac_cfg set_mac_cfg;
2925 struct ice_aqc_set_event_mask set_event_mask;
2926 struct ice_aqc_get_link_status get_link_status;
2927 struct ice_aqc_event_lan_overflow lan_overflow;
2928 struct ice_aqc_get_link_topo get_link_topo;
2929 struct ice_aqc_set_health_status_config
2930 set_health_status_config;
2931 struct ice_aqc_get_supported_health_status_codes
2932 get_supported_health_status_codes;
2933 struct ice_aqc_get_health_status get_health_status;
2934 struct ice_aqc_clear_health_status clear_health_status;
2935 struct ice_aqc_prog_topo_dev_nvm prog_topo_dev_nvm;
2936 struct ice_aqc_read_topo_dev_nvm read_topo_dev_nvm;
2940 /* FW defined boundary for a large buffer, 4k >= Large buffer > 512 bytes */
2941 #define ICE_AQ_LG_BUF 512
2943 /* Flags sub-structure
2944 * |0 |1 |2 |3 |4 |5 |6 |7 |8 |9 |10 |11 |12 |13 |14 |15 |
2945 * |DD |CMP|ERR|VFE| * * RESERVED * * |LB |RD |VFC|BUF|SI |EI |FE |
2948 /* command flags and offsets */
2949 #define ICE_AQ_FLAG_DD_S 0
2950 #define ICE_AQ_FLAG_CMP_S 1
2951 #define ICE_AQ_FLAG_ERR_S 2
2952 #define ICE_AQ_FLAG_VFE_S 3
2953 #define ICE_AQ_FLAG_LB_S 9
2954 #define ICE_AQ_FLAG_RD_S 10
2955 #define ICE_AQ_FLAG_VFC_S 11
2956 #define ICE_AQ_FLAG_BUF_S 12
2957 #define ICE_AQ_FLAG_SI_S 13
2958 #define ICE_AQ_FLAG_EI_S 14
2959 #define ICE_AQ_FLAG_FE_S 15
2961 #define ICE_AQ_FLAG_DD BIT(ICE_AQ_FLAG_DD_S) /* 0x1 */
2962 #define ICE_AQ_FLAG_CMP BIT(ICE_AQ_FLAG_CMP_S) /* 0x2 */
2963 #define ICE_AQ_FLAG_ERR BIT(ICE_AQ_FLAG_ERR_S) /* 0x4 */
2964 #define ICE_AQ_FLAG_VFE BIT(ICE_AQ_FLAG_VFE_S) /* 0x8 */
2965 #define ICE_AQ_FLAG_LB BIT(ICE_AQ_FLAG_LB_S) /* 0x200 */
2966 #define ICE_AQ_FLAG_RD BIT(ICE_AQ_FLAG_RD_S) /* 0x400 */
2967 #define ICE_AQ_FLAG_VFC BIT(ICE_AQ_FLAG_VFC_S) /* 0x800 */
2968 #define ICE_AQ_FLAG_BUF BIT(ICE_AQ_FLAG_BUF_S) /* 0x1000 */
2969 #define ICE_AQ_FLAG_SI BIT(ICE_AQ_FLAG_SI_S) /* 0x2000 */
2970 #define ICE_AQ_FLAG_EI BIT(ICE_AQ_FLAG_EI_S) /* 0x4000 */
2971 #define ICE_AQ_FLAG_FE BIT(ICE_AQ_FLAG_FE_S) /* 0x8000 */
2975 ICE_AQ_RC_OK = 0, /* Success */
2976 ICE_AQ_RC_EPERM = 1, /* Operation not permitted */
2977 ICE_AQ_RC_ENOENT = 2, /* No such element */
2978 ICE_AQ_RC_ESRCH = 3, /* Bad opcode */
2979 ICE_AQ_RC_EINTR = 4, /* Operation interrupted */
2980 ICE_AQ_RC_EIO = 5, /* I/O error */
2981 ICE_AQ_RC_ENXIO = 6, /* No such resource */
2982 ICE_AQ_RC_E2BIG = 7, /* Arg too long */
2983 ICE_AQ_RC_EAGAIN = 8, /* Try again */
2984 ICE_AQ_RC_ENOMEM = 9, /* Out of memory */
2985 ICE_AQ_RC_EACCES = 10, /* Permission denied */
2986 ICE_AQ_RC_EFAULT = 11, /* Bad address */
2987 ICE_AQ_RC_EBUSY = 12, /* Device or resource busy */
2988 ICE_AQ_RC_EEXIST = 13, /* Object already exists */
2989 ICE_AQ_RC_EINVAL = 14, /* Invalid argument */
2990 ICE_AQ_RC_ENOTTY = 15, /* Not a typewriter */
2991 ICE_AQ_RC_ENOSPC = 16, /* No space left or allocation failure */
2992 ICE_AQ_RC_ENOSYS = 17, /* Function not implemented */
2993 ICE_AQ_RC_ERANGE = 18, /* Parameter out of range */
2994 ICE_AQ_RC_EFLUSHED = 19, /* Cmd flushed due to prev cmd error */
2995 ICE_AQ_RC_BAD_ADDR = 20, /* Descriptor contains a bad pointer */
2996 ICE_AQ_RC_EMODE = 21, /* Op not allowed in current dev mode */
2997 ICE_AQ_RC_EFBIG = 22, /* File too big */
2998 ICE_AQ_RC_ESBCOMP = 23, /* SB-IOSF completion unsuccessful */
2999 ICE_AQ_RC_ENOSEC = 24, /* Missing security manifest */
3000 ICE_AQ_RC_EBADSIG = 25, /* Bad RSA signature */
3001 ICE_AQ_RC_ESVN = 26, /* SVN number prohibits this package */
3002 ICE_AQ_RC_EBADMAN = 27, /* Manifest hash mismatch */
3003 ICE_AQ_RC_EBADBUF = 28, /* Buffer hash mismatches manifest */
3004 ICE_AQ_RC_EACCES_BMCU = 29, /* BMC Update in progress */
3007 /* Admin Queue command opcodes */
3008 enum ice_adminq_opc {
3010 ice_aqc_opc_get_ver = 0x0001,
3011 ice_aqc_opc_driver_ver = 0x0002,
3012 ice_aqc_opc_q_shutdown = 0x0003,
3013 ice_aqc_opc_get_exp_err = 0x0005,
3015 /* resource ownership */
3016 ice_aqc_opc_req_res = 0x0008,
3017 ice_aqc_opc_release_res = 0x0009,
3019 /* device/function capabilities */
3020 ice_aqc_opc_list_func_caps = 0x000A,
3021 ice_aqc_opc_list_dev_caps = 0x000B,
3023 /* manage MAC address */
3024 ice_aqc_opc_manage_mac_read = 0x0107,
3025 ice_aqc_opc_manage_mac_write = 0x0108,
3028 ice_aqc_opc_clear_pxe_mode = 0x0110,
3030 ice_aqc_opc_config_no_drop_policy = 0x0112,
3032 /* internal switch commands */
3033 ice_aqc_opc_get_sw_cfg = 0x0200,
3034 ice_aqc_opc_set_port_params = 0x0203,
3036 /* Alloc/Free/Get Resources */
3037 ice_aqc_opc_get_res_alloc = 0x0204,
3038 ice_aqc_opc_alloc_res = 0x0208,
3039 ice_aqc_opc_free_res = 0x0209,
3040 ice_aqc_opc_get_allocd_res_desc = 0x020A,
3041 ice_aqc_opc_set_vlan_mode_parameters = 0x020C,
3042 ice_aqc_opc_get_vlan_mode_parameters = 0x020D,
3045 ice_aqc_opc_add_vsi = 0x0210,
3046 ice_aqc_opc_update_vsi = 0x0211,
3047 ice_aqc_opc_get_vsi_params = 0x0212,
3048 ice_aqc_opc_free_vsi = 0x0213,
3050 /* Mirroring rules - add/update, delete */
3051 ice_aqc_opc_add_update_mir_rule = 0x0260,
3052 ice_aqc_opc_del_mir_rule = 0x0261,
3054 /* storm configuration */
3055 ice_aqc_opc_set_storm_cfg = 0x0280,
3056 ice_aqc_opc_get_storm_cfg = 0x0281,
3058 /* recipe commands */
3059 ice_aqc_opc_add_recipe = 0x0290,
3060 ice_aqc_opc_recipe_to_profile = 0x0291,
3061 ice_aqc_opc_get_recipe = 0x0292,
3062 ice_aqc_opc_get_recipe_to_profile = 0x0293,
3064 /* switch rules population commands */
3065 ice_aqc_opc_add_sw_rules = 0x02A0,
3066 ice_aqc_opc_update_sw_rules = 0x02A1,
3067 ice_aqc_opc_remove_sw_rules = 0x02A2,
3068 ice_aqc_opc_get_sw_rules = 0x02A3,
3069 ice_aqc_opc_clear_pf_cfg = 0x02A4,
3072 ice_aqc_opc_pfc_ignore = 0x0301,
3073 ice_aqc_opc_query_pfc_mode = 0x0302,
3074 ice_aqc_opc_set_pfc_mode = 0x0303,
3075 ice_aqc_opc_set_dcb_params = 0x0306,
3077 /* transmit scheduler commands */
3078 ice_aqc_opc_get_dflt_topo = 0x0400,
3079 ice_aqc_opc_add_sched_elems = 0x0401,
3080 ice_aqc_opc_cfg_sched_elems = 0x0403,
3081 ice_aqc_opc_get_sched_elems = 0x0404,
3082 ice_aqc_opc_move_sched_elems = 0x0408,
3083 ice_aqc_opc_suspend_sched_elems = 0x0409,
3084 ice_aqc_opc_resume_sched_elems = 0x040A,
3085 ice_aqc_opc_query_port_ets = 0x040E,
3086 ice_aqc_opc_delete_sched_elems = 0x040F,
3087 ice_aqc_opc_add_rl_profiles = 0x0410,
3088 ice_aqc_opc_query_rl_profiles = 0x0411,
3089 ice_aqc_opc_query_sched_res = 0x0412,
3090 ice_aqc_opc_query_node_to_root = 0x0413,
3091 ice_aqc_opc_cfg_l2_node_cgd = 0x0414,
3092 ice_aqc_opc_remove_rl_profiles = 0x0415,
3095 ice_aqc_opc_get_phy_caps = 0x0600,
3096 ice_aqc_opc_set_phy_cfg = 0x0601,
3097 ice_aqc_opc_set_mac_cfg = 0x0603,
3098 ice_aqc_opc_restart_an = 0x0605,
3099 ice_aqc_opc_get_link_status = 0x0607,
3100 ice_aqc_opc_set_event_mask = 0x0613,
3101 ice_aqc_opc_set_mac_lb = 0x0620,
3102 ice_aqc_opc_get_link_topo = 0x06E0,
3103 ice_aqc_opc_get_link_topo_pin = 0x06E1,
3104 ice_aqc_opc_read_i2c = 0x06E2,
3105 ice_aqc_opc_write_i2c = 0x06E3,
3106 ice_aqc_opc_set_port_id_led = 0x06E9,
3107 ice_aqc_opc_get_port_options = 0x06EA,
3108 ice_aqc_opc_set_port_option = 0x06EB,
3109 ice_aqc_opc_set_gpio = 0x06EC,
3110 ice_aqc_opc_get_gpio = 0x06ED,
3111 ice_aqc_opc_sff_eeprom = 0x06EE,
3112 ice_aqc_opc_sw_set_gpio = 0x06EF,
3113 ice_aqc_opc_sw_get_gpio = 0x06F0,
3114 ice_aqc_opc_prog_topo_dev_nvm = 0x06F2,
3115 ice_aqc_opc_read_topo_dev_nvm = 0x06F3,
3118 ice_aqc_opc_nvm_read = 0x0701,
3119 ice_aqc_opc_nvm_erase = 0x0702,
3120 ice_aqc_opc_nvm_write = 0x0703,
3121 ice_aqc_opc_nvm_cfg_read = 0x0704,
3122 ice_aqc_opc_nvm_cfg_write = 0x0705,
3123 ice_aqc_opc_nvm_checksum = 0x0706,
3124 ice_aqc_opc_nvm_write_activate = 0x0707,
3125 ice_aqc_opc_nvm_sr_dump = 0x0707,
3126 ice_aqc_opc_nvm_save_factory_settings = 0x0708,
3127 ice_aqc_opc_nvm_update_empr = 0x0709,
3130 ice_aqc_opc_lldp_get_mib = 0x0A00,
3131 ice_aqc_opc_lldp_set_mib_change = 0x0A01,
3132 ice_aqc_opc_lldp_add_tlv = 0x0A02,
3133 ice_aqc_opc_lldp_update_tlv = 0x0A03,
3134 ice_aqc_opc_lldp_delete_tlv = 0x0A04,
3135 ice_aqc_opc_lldp_stop = 0x0A05,
3136 ice_aqc_opc_lldp_start = 0x0A06,
3137 ice_aqc_opc_get_cee_dcb_cfg = 0x0A07,
3138 ice_aqc_opc_lldp_set_local_mib = 0x0A08,
3139 ice_aqc_opc_lldp_stop_start_specific_agent = 0x0A09,
3140 ice_aqc_opc_lldp_filter_ctrl = 0x0A0A,
3143 ice_aqc_opc_set_rss_key = 0x0B02,
3144 ice_aqc_opc_set_rss_lut = 0x0B03,
3145 ice_aqc_opc_get_rss_key = 0x0B04,
3146 ice_aqc_opc_get_rss_lut = 0x0B05,
3147 ice_aqc_opc_clear_fd_table = 0x0B06,
3149 ice_aqc_opc_alloc_acl_tbl = 0x0C10,
3150 ice_aqc_opc_dealloc_acl_tbl = 0x0C11,
3151 ice_aqc_opc_alloc_acl_actpair = 0x0C12,
3152 ice_aqc_opc_dealloc_acl_actpair = 0x0C13,
3153 ice_aqc_opc_alloc_acl_scen = 0x0C14,
3154 ice_aqc_opc_dealloc_acl_scen = 0x0C15,
3155 ice_aqc_opc_alloc_acl_counters = 0x0C16,
3156 ice_aqc_opc_dealloc_acl_counters = 0x0C17,
3157 ice_aqc_opc_dealloc_acl_res = 0x0C1A,
3158 ice_aqc_opc_update_acl_scen = 0x0C1B,
3159 ice_aqc_opc_program_acl_actpair = 0x0C1C,
3160 ice_aqc_opc_program_acl_prof_extraction = 0x0C1D,
3161 ice_aqc_opc_program_acl_prof_ranges = 0x0C1E,
3162 ice_aqc_opc_program_acl_entry = 0x0C20,
3163 ice_aqc_opc_query_acl_prof = 0x0C21,
3164 ice_aqc_opc_query_acl_prof_ranges = 0x0C22,
3165 ice_aqc_opc_query_acl_scen = 0x0C23,
3166 ice_aqc_opc_query_acl_entry = 0x0C24,
3167 ice_aqc_opc_query_acl_actpair = 0x0C25,
3168 ice_aqc_opc_query_acl_counter = 0x0C27,
3170 /* Tx queue handling commands/events */
3171 ice_aqc_opc_add_txqs = 0x0C30,
3172 ice_aqc_opc_dis_txqs = 0x0C31,
3173 ice_aqc_opc_txqs_cleanup = 0x0C31,
3174 ice_aqc_opc_move_recfg_txqs = 0x0C32,
3176 /* package commands */
3177 ice_aqc_opc_download_pkg = 0x0C40,
3178 ice_aqc_opc_upload_section = 0x0C41,
3179 ice_aqc_opc_update_pkg = 0x0C42,
3180 ice_aqc_opc_get_pkg_info_list = 0x0C43,
3182 ice_aqc_opc_driver_shared_params = 0x0C90,
3184 /* Standalone Commands/Events */
3185 ice_aqc_opc_event_lan_overflow = 0x1001,
3187 /* debug commands */
3188 ice_aqc_opc_debug_dump_internals = 0xFF08,
3190 /* SystemDiagnostic commands */
3191 ice_aqc_opc_set_health_status_config = 0xFF20,
3192 ice_aqc_opc_get_supported_health_status_codes = 0xFF21,
3193 ice_aqc_opc_get_health_status = 0xFF22,
3194 ice_aqc_opc_clear_health_status = 0xFF23,
3197 #endif /* _ICE_ADMINQ_CMD_H_ */