1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2001-2018
5 #ifndef _ICE_ADMINQ_CMD_H_
6 #define _ICE_ADMINQ_CMD_H_
8 /* This header file defines the Admin Queue commands, error codes and
9 * descriptor format. It is shared between Firmware and Software.
13 #define ICE_MAX_VSI 768
14 #define ICE_AQC_TOPO_MAX_LEVEL_NUM 0x9
15 #define ICE_AQ_SET_MAC_FRAME_SIZE_MAX 9728
18 struct ice_aqc_generic {
26 /* Get version (direct 0x0001) */
27 struct ice_aqc_get_ver {
42 /* Queue Shutdown (direct 0x0003) */
43 struct ice_aqc_q_shutdown {
44 __le32 driver_unloading;
45 #define ICE_AQC_DRIVER_UNLOADING BIT(0)
52 /* Request resource ownership (direct 0x0008)
53 * Release resource ownership (direct 0x0009)
55 struct ice_aqc_req_res {
57 #define ICE_AQC_RES_ID_NVM 1
58 #define ICE_AQC_RES_ID_SDP 2
59 #define ICE_AQC_RES_ID_CHNG_LOCK 3
60 #define ICE_AQC_RES_ID_GLBL_LOCK 4
62 #define ICE_AQC_RES_ACCESS_READ 1
63 #define ICE_AQC_RES_ACCESS_WRITE 2
65 /* Upon successful completion, FW writes this value and driver is
66 * expected to release resource before timeout. This value is provided
70 #define ICE_AQ_RES_NVM_READ_DFLT_TIMEOUT_MS 3000
71 #define ICE_AQ_RES_NVM_WRITE_DFLT_TIMEOUT_MS 180000
72 #define ICE_AQ_RES_CHNG_LOCK_DFLT_TIMEOUT_MS 1000
73 #define ICE_AQ_RES_GLBL_LOCK_DFLT_TIMEOUT_MS 3000
74 /* For SDP: pin ID of the SDP */
76 /* Status is only used for ICE_AQC_RES_ID_GLBL_LOCK */
78 #define ICE_AQ_RES_GLBL_SUCCESS 0
79 #define ICE_AQ_RES_GLBL_IN_PROG 1
80 #define ICE_AQ_RES_GLBL_DONE 2
85 /* Get function capabilities (indirect 0x000A)
86 * Get device capabilities (indirect 0x000B)
88 struct ice_aqc_list_caps {
98 /* Device/Function buffer entry, repeated per reported capability */
99 struct ice_aqc_list_caps_elem {
101 #define ICE_AQC_CAPS_VALID_FUNCTIONS 0x0005
102 #define ICE_AQC_CAPS_VSI 0x0017
103 #define ICE_AQC_CAPS_RSS 0x0040
104 #define ICE_AQC_CAPS_RXQS 0x0041
105 #define ICE_AQC_CAPS_TXQS 0x0042
106 #define ICE_AQC_CAPS_MSIX 0x0043
107 #define ICE_AQC_CAPS_MAX_MTU 0x0047
111 /* Number of resources described by this capability */
113 /* Only meaningful for some types of resources */
115 /* Only meaningful for some types of resources */
122 /* Manage MAC address, read command - indirect (0x0107)
123 * This struct is also used for the response
125 struct ice_aqc_manage_mac_read {
126 __le16 flags; /* Zeroed by device driver */
127 #define ICE_AQC_MAN_MAC_LAN_ADDR_VALID BIT(4)
128 #define ICE_AQC_MAN_MAC_SAN_ADDR_VALID BIT(5)
129 #define ICE_AQC_MAN_MAC_PORT_ADDR_VALID BIT(6)
130 #define ICE_AQC_MAN_MAC_WOL_ADDR_VALID BIT(7)
131 #define ICE_AQC_MAN_MAC_READ_S 4
132 #define ICE_AQC_MAN_MAC_READ_M (0xF << ICE_AQC_MAN_MAC_READ_S)
135 #define ICE_AQC_MAN_MAC_PORT_NUM_IS_VALID BIT(0)
136 u8 num_addr; /* Used in response */
143 /* Response buffer format for manage MAC read command */
144 struct ice_aqc_manage_mac_read_resp {
147 #define ICE_AQC_MAN_MAC_ADDR_TYPE_LAN 0
148 #define ICE_AQC_MAN_MAC_ADDR_TYPE_WOL 1
149 u8 mac_addr[ETH_ALEN];
153 /* Manage MAC address, write command - direct (0x0108) */
154 struct ice_aqc_manage_mac_write {
157 #define ICE_AQC_MAN_MAC_WR_MC_MAG_EN BIT(0)
158 #define ICE_AQC_MAN_MAC_WR_WOL_LAA_PFR_KEEP BIT(1)
159 #define ICE_AQC_MAN_MAC_WR_S 6
160 #define ICE_AQC_MAN_MAC_WR_M (3 << ICE_AQC_MAN_MAC_WR_S)
161 #define ICE_AQC_MAN_MAC_UPDATE_LAA 0
162 #define ICE_AQC_MAN_MAC_UPDATE_LAA_WOL (BIT(0) << ICE_AQC_MAN_MAC_WR_S)
163 /* High 16 bits of MAC address in big endian order */
165 /* Low 32 bits of MAC address in big endian order */
172 /* Clear PXE Command and response (direct 0x0110) */
173 struct ice_aqc_clear_pxe {
175 #define ICE_AQC_CLEAR_PXE_RX_CNT 0x2
180 /* Get switch configuration (0x0200) */
181 struct ice_aqc_get_sw_cfg {
182 /* Reserved for command and copy of request flags for response */
184 /* First desc in case of command and next_elem in case of response
185 * In case of response, if it is not zero, means all the configuration
186 * was not returned and new command shall be sent with this value in
187 * the 'first desc' field
190 /* Reserved for command, only used for response */
198 /* Each entry in the response buffer is of the following type: */
199 struct ice_aqc_get_sw_cfg_resp_elem {
200 /* VSI/Port Number */
202 #define ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_S 0
203 #define ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_M \
204 (0x3FF << ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_S)
205 #define ICE_AQC_GET_SW_CONF_RESP_TYPE_S 14
206 #define ICE_AQC_GET_SW_CONF_RESP_TYPE_M (0x3 << ICE_AQC_GET_SW_CONF_RESP_TYPE_S)
207 #define ICE_AQC_GET_SW_CONF_RESP_PHYS_PORT 0
208 #define ICE_AQC_GET_SW_CONF_RESP_VIRT_PORT 1
209 #define ICE_AQC_GET_SW_CONF_RESP_VSI 2
211 /* SWID VSI/Port belongs to */
214 /* Bit 14..0 : PF/VF number VSI belongs to
215 * Bit 15 : VF indication bit
218 #define ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_S 0
219 #define ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_M \
220 (0x7FFF << ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_S)
221 #define ICE_AQC_GET_SW_CONF_RESP_IS_VF BIT(15)
225 /* The response buffer is as follows. Note that the length of the
226 * elements array varies with the length of the command response.
228 struct ice_aqc_get_sw_cfg_resp {
229 struct ice_aqc_get_sw_cfg_resp_elem elements[1];
234 /* These resource type defines are used for all switch resource
235 * commands where a resource type is required, such as:
236 * Get Resource Allocation command (indirect 0x0204)
237 * Allocate Resources command (indirect 0x0208)
238 * Free Resources command (indirect 0x0209)
239 * Get Allocated Resource Descriptors Command (indirect 0x020A)
241 #define ICE_AQC_RES_TYPE_VEB_COUNTER 0x00
242 #define ICE_AQC_RES_TYPE_VLAN_COUNTER 0x01
243 #define ICE_AQC_RES_TYPE_MIRROR_RULE 0x02
244 #define ICE_AQC_RES_TYPE_VSI_LIST_REP 0x03
245 #define ICE_AQC_RES_TYPE_VSI_LIST_PRUNE 0x04
246 #define ICE_AQC_RES_TYPE_RECIPE 0x05
247 #define ICE_AQC_RES_TYPE_PROFILE 0x06
248 #define ICE_AQC_RES_TYPE_SWID 0x07
249 #define ICE_AQC_RES_TYPE_VSI 0x08
250 #define ICE_AQC_RES_TYPE_FLU 0x09
251 #define ICE_AQC_RES_TYPE_WIDE_TABLE_1 0x0A
252 #define ICE_AQC_RES_TYPE_WIDE_TABLE_2 0x0B
253 #define ICE_AQC_RES_TYPE_WIDE_TABLE_4 0x0C
254 #define ICE_AQC_RES_TYPE_GLOBAL_RSS_HASH 0x20
255 #define ICE_AQC_RES_TYPE_FDIR_COUNTER_BLOCK 0x21
256 #define ICE_AQC_RES_TYPE_FDIR_GUARANTEED_ENTRIES 0x22
257 #define ICE_AQC_RES_TYPE_FDIR_SHARED_ENTRIES 0x23
258 #define ICE_AQC_RES_TYPE_FLEX_DESC_PROG 0x30
259 #define ICE_AQC_RES_TYPE_SWITCH_PROF_BLDR_PROFID 0x48
260 #define ICE_AQC_RES_TYPE_SWITCH_PROF_BLDR_TCAM 0x49
261 #define ICE_AQC_RES_TYPE_ACL_PROF_BLDR_PROFID 0x50
262 #define ICE_AQC_RES_TYPE_ACL_PROF_BLDR_TCAM 0x51
263 #define ICE_AQC_RES_TYPE_FD_PROF_BLDR_PROFID 0x58
264 #define ICE_AQC_RES_TYPE_FD_PROF_BLDR_TCAM 0x59
265 #define ICE_AQC_RES_TYPE_HASH_PROF_BLDR_PROFID 0x60
266 #define ICE_AQC_RES_TYPE_HASH_PROF_BLDR_TCAM 0x61
267 /* Resource types 0x62-67 are reserved for Hash profile builder */
268 #define ICE_AQC_RES_TYPE_QHASH_PROF_BLDR_PROFID 0x68
269 #define ICE_AQC_RES_TYPE_QHASH_PROF_BLDR_TCAM 0x69
271 #define ICE_AQC_RES_TYPE_FLAG_SHARED BIT(7)
272 #define ICE_AQC_RES_TYPE_FLAG_SCAN_BOTTOM BIT(12)
273 #define ICE_AQC_RES_TYPE_FLAG_IGNORE_INDEX BIT(13)
275 #define ICE_AQC_RES_TYPE_FLAG_DEDICATED 0x00
279 /* Allocate Resources command (indirect 0x0208)
280 * Free Resources command (indirect 0x0209)
282 struct ice_aqc_alloc_free_res_cmd {
283 __le16 num_entries; /* Number of Resource entries */
290 /* Resource descriptor */
291 struct ice_aqc_res_elem {
299 /* Buffer for Allocate/Free Resources commands */
300 struct ice_aqc_alloc_free_res_elem {
301 __le16 res_type; /* Types defined above cmd 0x0204 */
302 #define ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_S 8
303 #define ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_M \
304 (0xF << ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_S)
306 struct ice_aqc_res_elem elem[1];
312 /* Add VSI (indirect 0x0210)
313 * Update VSI (indirect 0x0211)
314 * Get VSI (indirect 0x0212)
315 * Free VSI (indirect 0x0213)
317 struct ice_aqc_add_get_update_free_vsi {
319 #define ICE_AQ_VSI_NUM_S 0
320 #define ICE_AQ_VSI_NUM_M (0x03FF << ICE_AQ_VSI_NUM_S)
321 #define ICE_AQ_VSI_IS_VALID BIT(15)
323 #define ICE_AQ_VSI_KEEP_ALLOC 0x1
327 #define ICE_AQ_VSI_TYPE_S 0
328 #define ICE_AQ_VSI_TYPE_M (0x3 << ICE_AQ_VSI_TYPE_S)
329 #define ICE_AQ_VSI_TYPE_VF 0x0
330 #define ICE_AQ_VSI_TYPE_VMDQ2 0x1
331 #define ICE_AQ_VSI_TYPE_PF 0x2
332 #define ICE_AQ_VSI_TYPE_EMP_MNG 0x3
338 /* Response descriptor for:
339 * Add VSI (indirect 0x0210)
340 * Update VSI (indirect 0x0211)
341 * Free VSI (indirect 0x0213)
343 struct ice_aqc_add_update_free_vsi_resp {
354 struct ice_aqc_vsi_props {
355 __le16 valid_sections;
356 #define ICE_AQ_VSI_PROP_SW_VALID BIT(0)
357 #define ICE_AQ_VSI_PROP_SECURITY_VALID BIT(1)
358 #define ICE_AQ_VSI_PROP_VLAN_VALID BIT(2)
359 #define ICE_AQ_VSI_PROP_OUTER_TAG_VALID BIT(3)
360 #define ICE_AQ_VSI_PROP_INGRESS_UP_VALID BIT(4)
361 #define ICE_AQ_VSI_PROP_EGRESS_UP_VALID BIT(5)
362 #define ICE_AQ_VSI_PROP_RXQ_MAP_VALID BIT(6)
363 #define ICE_AQ_VSI_PROP_Q_OPT_VALID BIT(7)
364 #define ICE_AQ_VSI_PROP_OUTER_UP_VALID BIT(8)
365 #define ICE_AQ_VSI_PROP_FLOW_DIR_VALID BIT(11)
366 #define ICE_AQ_VSI_PROP_PASID_VALID BIT(12)
370 #define ICE_AQ_VSI_SW_FLAG_ALLOW_LB BIT(5)
371 #define ICE_AQ_VSI_SW_FLAG_LOCAL_LB BIT(6)
372 #define ICE_AQ_VSI_SW_FLAG_SRC_PRUNE BIT(7)
374 #define ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_S 0
375 #define ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_M \
376 (0xF << ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_S)
377 #define ICE_AQ_VSI_SW_FLAG_RX_VLAN_PRUNE_ENA BIT(0)
378 #define ICE_AQ_VSI_SW_FLAG_LAN_ENA BIT(4)
380 #define ICE_AQ_VSI_SW_VEB_STAT_ID_S 0
381 #define ICE_AQ_VSI_SW_VEB_STAT_ID_M (0x1F << ICE_AQ_VSI_SW_VEB_STAT_ID_S)
382 #define ICE_AQ_VSI_SW_VEB_STAT_ID_VALID BIT(5)
383 /* security section */
385 #define ICE_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD BIT(0)
386 #define ICE_AQ_VSI_SEC_FLAG_ENA_MAC_ANTI_SPOOF BIT(2)
387 #define ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S 4
388 #define ICE_AQ_VSI_SEC_TX_PRUNE_ENA_M (0xF << ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S)
389 #define ICE_AQ_VSI_SEC_TX_VLAN_PRUNE_ENA BIT(0)
392 __le16 pvid; /* VLANS include priority bits */
393 u8 pvlan_reserved[2];
395 #define ICE_AQ_VSI_VLAN_MODE_S 0
396 #define ICE_AQ_VSI_VLAN_MODE_M (0x3 << ICE_AQ_VSI_VLAN_MODE_S)
397 #define ICE_AQ_VSI_VLAN_MODE_UNTAGGED 0x1
398 #define ICE_AQ_VSI_VLAN_MODE_TAGGED 0x2
399 #define ICE_AQ_VSI_VLAN_MODE_ALL 0x3
400 #define ICE_AQ_VSI_PVLAN_INSERT_PVID BIT(2)
401 #define ICE_AQ_VSI_VLAN_EMOD_S 3
402 #define ICE_AQ_VSI_VLAN_EMOD_M (0x3 << ICE_AQ_VSI_VLAN_EMOD_S)
403 #define ICE_AQ_VSI_VLAN_EMOD_STR_BOTH (0x0 << ICE_AQ_VSI_VLAN_EMOD_S)
404 #define ICE_AQ_VSI_VLAN_EMOD_STR_UP (0x1 << ICE_AQ_VSI_VLAN_EMOD_S)
405 #define ICE_AQ_VSI_VLAN_EMOD_STR (0x2 << ICE_AQ_VSI_VLAN_EMOD_S)
406 #define ICE_AQ_VSI_VLAN_EMOD_NOTHING (0x3 << ICE_AQ_VSI_VLAN_EMOD_S)
407 u8 pvlan_reserved2[3];
408 /* ingress egress up sections */
409 __le32 ingress_table; /* bitmap, 3 bits per up */
410 #define ICE_AQ_VSI_UP_TABLE_UP0_S 0
411 #define ICE_AQ_VSI_UP_TABLE_UP0_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP0_S)
412 #define ICE_AQ_VSI_UP_TABLE_UP1_S 3
413 #define ICE_AQ_VSI_UP_TABLE_UP1_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP1_S)
414 #define ICE_AQ_VSI_UP_TABLE_UP2_S 6
415 #define ICE_AQ_VSI_UP_TABLE_UP2_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP2_S)
416 #define ICE_AQ_VSI_UP_TABLE_UP3_S 9
417 #define ICE_AQ_VSI_UP_TABLE_UP3_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP3_S)
418 #define ICE_AQ_VSI_UP_TABLE_UP4_S 12
419 #define ICE_AQ_VSI_UP_TABLE_UP4_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP4_S)
420 #define ICE_AQ_VSI_UP_TABLE_UP5_S 15
421 #define ICE_AQ_VSI_UP_TABLE_UP5_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP5_S)
422 #define ICE_AQ_VSI_UP_TABLE_UP6_S 18
423 #define ICE_AQ_VSI_UP_TABLE_UP6_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP6_S)
424 #define ICE_AQ_VSI_UP_TABLE_UP7_S 21
425 #define ICE_AQ_VSI_UP_TABLE_UP7_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP7_S)
426 __le32 egress_table; /* same defines as for ingress table */
427 /* outer tags section */
430 #define ICE_AQ_VSI_OUTER_TAG_MODE_S 0
431 #define ICE_AQ_VSI_OUTER_TAG_MODE_M (0x3 << ICE_AQ_VSI_OUTER_TAG_MODE_S)
432 #define ICE_AQ_VSI_OUTER_TAG_NOTHING 0x0
433 #define ICE_AQ_VSI_OUTER_TAG_REMOVE 0x1
434 #define ICE_AQ_VSI_OUTER_TAG_COPY 0x2
435 #define ICE_AQ_VSI_OUTER_TAG_TYPE_S 2
436 #define ICE_AQ_VSI_OUTER_TAG_TYPE_M (0x3 << ICE_AQ_VSI_OUTER_TAG_TYPE_S)
437 #define ICE_AQ_VSI_OUTER_TAG_NONE 0x0
438 #define ICE_AQ_VSI_OUTER_TAG_STAG 0x1
439 #define ICE_AQ_VSI_OUTER_TAG_VLAN_8100 0x2
440 #define ICE_AQ_VSI_OUTER_TAG_VLAN_9100 0x3
441 #define ICE_AQ_VSI_OUTER_TAG_INSERT BIT(4)
442 #define ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST BIT(6)
443 u8 outer_tag_reserved;
444 /* queue mapping section */
445 __le16 mapping_flags;
446 #define ICE_AQ_VSI_Q_MAP_CONTIG 0x0
447 #define ICE_AQ_VSI_Q_MAP_NONCONTIG BIT(0)
448 __le16 q_mapping[16];
449 #define ICE_AQ_VSI_Q_S 0
450 #define ICE_AQ_VSI_Q_M (0x7FF << ICE_AQ_VSI_Q_S)
451 __le16 tc_mapping[8];
452 #define ICE_AQ_VSI_TC_Q_OFFSET_S 0
453 #define ICE_AQ_VSI_TC_Q_OFFSET_M (0x7FF << ICE_AQ_VSI_TC_Q_OFFSET_S)
454 #define ICE_AQ_VSI_TC_Q_NUM_S 11
455 #define ICE_AQ_VSI_TC_Q_NUM_M (0xF << ICE_AQ_VSI_TC_Q_NUM_S)
456 /* queueing option section */
458 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_S 0
459 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_M (0x3 << ICE_AQ_VSI_Q_OPT_RSS_LUT_S)
460 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_VSI 0x0
461 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_PF 0x2
462 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_GBL 0x3
463 #define ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_S 2
464 #define ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_M (0xF << ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_S)
465 #define ICE_AQ_VSI_Q_OPT_RSS_HASH_S 6
466 #define ICE_AQ_VSI_Q_OPT_RSS_HASH_M (0x3 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S)
467 #define ICE_AQ_VSI_Q_OPT_RSS_TPLZ (0x0 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S)
468 #define ICE_AQ_VSI_Q_OPT_RSS_SYM_TPLZ (0x1 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S)
469 #define ICE_AQ_VSI_Q_OPT_RSS_XOR (0x2 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S)
470 #define ICE_AQ_VSI_Q_OPT_RSS_JHASH (0x3 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S)
472 #define ICE_AQ_VSI_Q_OPT_TC_OVR_S 0
473 #define ICE_AQ_VSI_Q_OPT_TC_OVR_M (0x1F << ICE_AQ_VSI_Q_OPT_TC_OVR_S)
474 #define ICE_AQ_VSI_Q_OPT_PROF_TC_OVR BIT(7)
476 #define ICE_AQ_VSI_Q_OPT_PE_FLTR_EN BIT(0)
477 u8 q_opt_reserved[3];
478 /* outer up section */
479 __le32 outer_up_table; /* same structure and defines as ingress tbl */
481 __le16 sect_10_reserved;
482 /* flow director section */
484 #define ICE_AQ_VSI_FD_ENABLE BIT(0)
485 #define ICE_AQ_VSI_FD_TX_AUTO_ENABLE BIT(1)
486 #define ICE_AQ_VSI_FD_PROG_ENABLE BIT(3)
487 __le16 max_fd_fltr_dedicated;
488 __le16 max_fd_fltr_shared;
490 #define ICE_AQ_VSI_FD_DEF_Q_S 0
491 #define ICE_AQ_VSI_FD_DEF_Q_M (0x7FF << ICE_AQ_VSI_FD_DEF_Q_S)
492 #define ICE_AQ_VSI_FD_DEF_GRP_S 12
493 #define ICE_AQ_VSI_FD_DEF_GRP_M (0x7 << ICE_AQ_VSI_FD_DEF_GRP_S)
494 __le16 fd_report_opt;
495 #define ICE_AQ_VSI_FD_REPORT_Q_S 0
496 #define ICE_AQ_VSI_FD_REPORT_Q_M (0x7FF << ICE_AQ_VSI_FD_REPORT_Q_S)
497 #define ICE_AQ_VSI_FD_DEF_PRIORITY_S 12
498 #define ICE_AQ_VSI_FD_DEF_PRIORITY_M (0x7 << ICE_AQ_VSI_FD_DEF_PRIORITY_S)
499 #define ICE_AQ_VSI_FD_DEF_DROP BIT(15)
502 #define ICE_AQ_VSI_PASID_ID_S 0
503 #define ICE_AQ_VSI_PASID_ID_M (0xFFFFF << ICE_AQ_VSI_PASID_ID_S)
504 #define ICE_AQ_VSI_PASID_ID_VALID BIT(31)
510 #define ICE_MAX_NUM_RECIPES 64
513 /* Add/Update/Remove/Get switch rules (indirect 0x02A0, 0x02A1, 0x02A2, 0x02A3)
515 struct ice_aqc_sw_rules {
516 /* ops: add switch rules, referring the number of rules.
517 * ops: update switch rules, referring the number of filters
518 * ops: remove switch rules, referring the entry index.
519 * ops: get switch rules, referring to the number of filters.
521 __le16 num_rules_fltr_entry_index;
529 /* Add/Update/Get/Remove lookup Rx/Tx command/response entry
530 * This structures describes the lookup rules and associated actions. "index"
531 * is returned as part of a response to a successful Add command, and can be
532 * used to identify the rule for Update/Get/Remove commands.
534 struct ice_sw_rule_lkup_rx_tx {
536 #define ICE_SW_RECIPE_LOGICAL_PORT_FWD 10
537 /* Source port for LOOKUP_RX and source VSI in case of LOOKUP_TX */
541 /* Bit 0:1 - Action type */
542 #define ICE_SINGLE_ACT_TYPE_S 0x00
543 #define ICE_SINGLE_ACT_TYPE_M (0x3 << ICE_SINGLE_ACT_TYPE_S)
545 /* Bit 2 - Loop back enable
548 #define ICE_SINGLE_ACT_LB_ENABLE BIT(2)
549 #define ICE_SINGLE_ACT_LAN_ENABLE BIT(3)
551 /* Action type = 0 - Forward to VSI or VSI list */
552 #define ICE_SINGLE_ACT_VSI_FORWARDING 0x0
554 #define ICE_SINGLE_ACT_VSI_ID_S 4
555 #define ICE_SINGLE_ACT_VSI_ID_M (0x3FF << ICE_SINGLE_ACT_VSI_ID_S)
556 #define ICE_SINGLE_ACT_VSI_LIST_ID_S 4
557 #define ICE_SINGLE_ACT_VSI_LIST_ID_M (0x3FF << ICE_SINGLE_ACT_VSI_LIST_ID_S)
558 /* This bit needs to be set if action is forward to VSI list */
559 #define ICE_SINGLE_ACT_VSI_LIST BIT(14)
560 #define ICE_SINGLE_ACT_VALID_BIT BIT(17)
561 #define ICE_SINGLE_ACT_DROP BIT(18)
563 /* Action type = 1 - Forward to Queue of Queue group */
564 #define ICE_SINGLE_ACT_TO_Q 0x1
565 #define ICE_SINGLE_ACT_Q_INDEX_S 4
566 #define ICE_SINGLE_ACT_Q_INDEX_M (0x7FF << ICE_SINGLE_ACT_Q_INDEX_S)
567 #define ICE_SINGLE_ACT_Q_REGION_S 15
568 #define ICE_SINGLE_ACT_Q_REGION_M (0x7 << ICE_SINGLE_ACT_Q_REGION_S)
569 #define ICE_SINGLE_ACT_Q_PRIORITY BIT(18)
571 /* Action type = 2 - Prune */
572 #define ICE_SINGLE_ACT_PRUNE 0x2
573 #define ICE_SINGLE_ACT_EGRESS BIT(15)
574 #define ICE_SINGLE_ACT_INGRESS BIT(16)
575 #define ICE_SINGLE_ACT_PRUNET BIT(17)
576 /* Bit 18 should be set to 0 for this action */
578 /* Action type = 2 - Pointer */
579 #define ICE_SINGLE_ACT_PTR 0x2
580 #define ICE_SINGLE_ACT_PTR_VAL_S 4
581 #define ICE_SINGLE_ACT_PTR_VAL_M (0x1FFF << ICE_SINGLE_ACT_PTR_VAL_S)
582 /* Bit 18 should be set to 1 */
583 #define ICE_SINGLE_ACT_PTR_BIT BIT(18)
585 /* Action type = 3 - Other actions. Last two bits
586 * are other action identifier
588 #define ICE_SINGLE_ACT_OTHER_ACTS 0x3
589 #define ICE_SINGLE_OTHER_ACT_IDENTIFIER_S 17
590 #define ICE_SINGLE_OTHER_ACT_IDENTIFIER_M \
591 (0x3 << \ ICE_SINGLE_OTHER_ACT_IDENTIFIER_S)
593 /* Bit 17:18 - Defines other actions */
594 /* Other action = 0 - Mirror VSI */
595 #define ICE_SINGLE_OTHER_ACT_MIRROR 0
596 #define ICE_SINGLE_ACT_MIRROR_VSI_ID_S 4
597 #define ICE_SINGLE_ACT_MIRROR_VSI_ID_M \
598 (0x3FF << ICE_SINGLE_ACT_MIRROR_VSI_ID_S)
600 /* Other action = 3 - Set Stat count */
601 #define ICE_SINGLE_OTHER_ACT_STAT_COUNT 3
602 #define ICE_SINGLE_ACT_STAT_COUNT_INDEX_S 4
603 #define ICE_SINGLE_ACT_STAT_COUNT_INDEX_M \
604 (0x7F << ICE_SINGLE_ACT_STAT_COUNT_INDEX_S)
606 __le16 index; /* The index of the rule in the lookup table */
607 /* Length and values of the header to be matched per recipe or
616 /* Add/Update/Remove large action command/response entry
617 * "index" is returned as part of a response to a successful Add command, and
618 * can be used to identify the action for Update/Get/Remove commands.
620 struct ice_sw_rule_lg_act {
621 __le16 index; /* Index in large action table */
623 __le32 act[1]; /* array of size for actions */
624 /* Max number of large actions */
625 #define ICE_MAX_LG_ACT 4
626 /* Bit 0:1 - Action type */
627 #define ICE_LG_ACT_TYPE_S 0
628 #define ICE_LG_ACT_TYPE_M (0x7 << ICE_LG_ACT_TYPE_S)
630 /* Action type = 0 - Forward to VSI or VSI list */
631 #define ICE_LG_ACT_VSI_FORWARDING 0
632 #define ICE_LG_ACT_VSI_ID_S 3
633 #define ICE_LG_ACT_VSI_ID_M (0x3FF << ICE_LG_ACT_VSI_ID_S)
634 #define ICE_LG_ACT_VSI_LIST_ID_S 3
635 #define ICE_LG_ACT_VSI_LIST_ID_M (0x3FF << ICE_LG_ACT_VSI_LIST_ID_S)
636 /* This bit needs to be set if action is forward to VSI list */
637 #define ICE_LG_ACT_VSI_LIST BIT(13)
639 #define ICE_LG_ACT_VALID_BIT BIT(16)
641 /* Action type = 1 - Forward to Queue of Queue group */
642 #define ICE_LG_ACT_TO_Q 0x1
643 #define ICE_LG_ACT_Q_INDEX_S 3
644 #define ICE_LG_ACT_Q_INDEX_M (0x7FF << ICE_LG_ACT_Q_INDEX_S)
645 #define ICE_LG_ACT_Q_REGION_S 14
646 #define ICE_LG_ACT_Q_REGION_M (0x7 << ICE_LG_ACT_Q_REGION_S)
647 #define ICE_LG_ACT_Q_PRIORITY_SET BIT(17)
649 /* Action type = 2 - Prune */
650 #define ICE_LG_ACT_PRUNE 0x2
651 #define ICE_LG_ACT_EGRESS BIT(14)
652 #define ICE_LG_ACT_INGRESS BIT(15)
653 #define ICE_LG_ACT_PRUNET BIT(16)
655 /* Action type = 3 - Mirror VSI */
656 #define ICE_LG_OTHER_ACT_MIRROR 0x3
657 #define ICE_LG_ACT_MIRROR_VSI_ID_S 3
658 #define ICE_LG_ACT_MIRROR_VSI_ID_M (0x3FF << ICE_LG_ACT_MIRROR_VSI_ID_S)
660 /* Action type = 5 - Generic Value */
661 #define ICE_LG_ACT_GENERIC 0x5
662 #define ICE_LG_ACT_GENERIC_VALUE_S 3
663 #define ICE_LG_ACT_GENERIC_VALUE_M (0xFFFF << ICE_LG_ACT_GENERIC_VALUE_S)
664 #define ICE_LG_ACT_GENERIC_OFFSET_S 19
665 #define ICE_LG_ACT_GENERIC_OFFSET_M (0x7 << ICE_LG_ACT_GENERIC_OFFSET_S)
666 #define ICE_LG_ACT_GENERIC_PRIORITY_S 22
667 #define ICE_LG_ACT_GENERIC_PRIORITY_M (0x7 << ICE_LG_ACT_GENERIC_PRIORITY_S)
668 #define ICE_LG_ACT_GENERIC_OFF_RX_DESC_PROF_IDX 7
670 /* Action = 7 - Set Stat count */
671 #define ICE_LG_ACT_STAT_COUNT 0x7
672 #define ICE_LG_ACT_STAT_COUNT_S 3
673 #define ICE_LG_ACT_STAT_COUNT_M (0x7F << ICE_LG_ACT_STAT_COUNT_S)
677 /* Add/Update/Remove VSI list command/response entry
678 * "index" is returned as part of a response to a successful Add command, and
679 * can be used to identify the VSI list for Update/Get/Remove commands.
681 struct ice_sw_rule_vsi_list {
682 __le16 index; /* Index of VSI/Prune list */
684 __le16 vsi[1]; /* Array of number_vsi VSI numbers */
689 /* Query VSI list command/response entry */
690 struct ice_sw_rule_vsi_list_query {
692 ice_declare_bitmap(vsi_list, ICE_MAX_VSI);
698 /* Add switch rule response:
699 * Content of return buffer is same as the input buffer. The status field and
700 * LUT index are updated as part of the response
702 struct ice_aqc_sw_rules_elem {
703 __le16 type; /* Switch rule type, one of T_... */
704 #define ICE_AQC_SW_RULES_T_LKUP_RX 0x0
705 #define ICE_AQC_SW_RULES_T_LKUP_TX 0x1
706 #define ICE_AQC_SW_RULES_T_LG_ACT 0x2
707 #define ICE_AQC_SW_RULES_T_VSI_LIST_SET 0x3
708 #define ICE_AQC_SW_RULES_T_VSI_LIST_CLEAR 0x4
709 #define ICE_AQC_SW_RULES_T_PRUNE_LIST_SET 0x5
710 #define ICE_AQC_SW_RULES_T_PRUNE_LIST_CLEAR 0x6
713 struct ice_sw_rule_lkup_rx_tx lkup_tx_rx;
714 struct ice_sw_rule_lg_act lg_act;
715 struct ice_sw_rule_vsi_list vsi_list;
716 struct ice_sw_rule_vsi_list_query vsi_list_query;
724 /* Get Default Topology (indirect 0x0400) */
725 struct ice_aqc_get_topo {
735 /* Update TSE (indirect 0x0403)
736 * Get TSE (indirect 0x0404)
737 * Add TSE (indirect 0x0401)
738 * Delete TSE (indirect 0x040F)
739 * Move TSE (indirect 0x0408)
740 * Suspend Nodes (indirect 0x0409)
741 * Resume Nodes (indirect 0x040A)
743 struct ice_aqc_sched_elem_cmd {
744 __le16 num_elem_req; /* Used by commands */
745 __le16 num_elem_resp; /* Used by responses */
752 /* This is the buffer for:
753 * Suspend Nodes (indirect 0x0409)
754 * Resume Nodes (indirect 0x040A)
756 struct ice_aqc_suspend_resume_elem {
761 struct ice_aqc_txsched_move_grp_info_hdr {
762 __le32 src_parent_teid;
763 __le32 dest_parent_teid;
769 struct ice_aqc_move_elem {
770 struct ice_aqc_txsched_move_grp_info_hdr hdr;
775 struct ice_aqc_elem_info_bw {
776 __le16 bw_profile_idx;
781 struct ice_aqc_txsched_elem {
782 u8 elem_type; /* Special field, reserved for some aq calls */
783 #define ICE_AQC_ELEM_TYPE_UNDEFINED 0x0
784 #define ICE_AQC_ELEM_TYPE_ROOT_PORT 0x1
785 #define ICE_AQC_ELEM_TYPE_TC 0x2
786 #define ICE_AQC_ELEM_TYPE_SE_GENERIC 0x3
787 #define ICE_AQC_ELEM_TYPE_ENTRY_POINT 0x4
788 #define ICE_AQC_ELEM_TYPE_LEAF 0x5
789 #define ICE_AQC_ELEM_TYPE_SE_PADDED 0x6
791 #define ICE_AQC_ELEM_VALID_GENERIC BIT(0)
792 #define ICE_AQC_ELEM_VALID_CIR BIT(1)
793 #define ICE_AQC_ELEM_VALID_EIR BIT(2)
794 #define ICE_AQC_ELEM_VALID_SHARED BIT(3)
796 #define ICE_AQC_ELEM_GENERIC_MODE_M 0x1
797 #define ICE_AQC_ELEM_GENERIC_PRIO_S 0x1
798 #define ICE_AQC_ELEM_GENERIC_PRIO_M (0x7 << ICE_AQC_ELEM_GENERIC_PRIO_S)
799 #define ICE_AQC_ELEM_GENERIC_SP_S 0x4
800 #define ICE_AQC_ELEM_GENERIC_SP_M (0x1 << ICE_AQC_ELEM_GENERIC_SP_S)
801 #define ICE_AQC_ELEM_GENERIC_ADJUST_VAL_S 0x5
802 #define ICE_AQC_ELEM_GENERIC_ADJUST_VAL_M \
803 (0x3 << ICE_AQC_ELEM_GENERIC_ADJUST_VAL_S)
804 u8 flags; /* Special field, reserved for some aq calls */
805 #define ICE_AQC_ELEM_FLAG_SUSPEND_M 0x1
806 struct ice_aqc_elem_info_bw cir_bw;
807 struct ice_aqc_elem_info_bw eir_bw;
813 struct ice_aqc_txsched_elem_data {
816 struct ice_aqc_txsched_elem data;
820 struct ice_aqc_txsched_topo_grp_info_hdr {
827 struct ice_aqc_add_elem {
828 struct ice_aqc_txsched_topo_grp_info_hdr hdr;
829 struct ice_aqc_txsched_elem_data generic[1];
833 struct ice_aqc_conf_elem {
834 struct ice_aqc_txsched_elem_data generic[1];
838 struct ice_aqc_get_elem {
839 struct ice_aqc_txsched_elem_data generic[1];
843 struct ice_aqc_get_topo_elem {
844 struct ice_aqc_txsched_topo_grp_info_hdr hdr;
845 struct ice_aqc_txsched_elem_data
846 generic[ICE_AQC_TOPO_MAX_LEVEL_NUM];
850 struct ice_aqc_delete_elem {
851 struct ice_aqc_txsched_topo_grp_info_hdr hdr;
857 /* Rate limiting profile for
858 * Add RL profile (indirect 0x0410)
859 * Query RL profile (indirect 0x0411)
860 * Remove RL profile (indirect 0x0415)
861 * These indirect commands acts on single or multiple
862 * RL profiles with specified data.
864 struct ice_aqc_rl_profile {
866 __le16 num_processed; /* Only for response. Reserved in Command. */
873 struct ice_aqc_rl_profile_elem {
876 #define ICE_AQC_RL_PROFILE_TYPE_S 0x0
877 #define ICE_AQC_RL_PROFILE_TYPE_M (0x3 << ICE_AQC_RL_PROFILE_TYPE_S)
878 #define ICE_AQC_RL_PROFILE_TYPE_CIR 0
879 #define ICE_AQC_RL_PROFILE_TYPE_EIR 1
880 #define ICE_AQC_RL_PROFILE_TYPE_SRL 2
881 /* The following flag is used for Query RL Profile Data */
882 #define ICE_AQC_RL_PROFILE_INVAL_S 0x7
883 #define ICE_AQC_RL_PROFILE_INVAL_M (0x1 << ICE_AQC_RL_PROFILE_INVAL_S)
886 __le16 max_burst_size;
893 struct ice_aqc_rl_profile_generic_elem {
894 struct ice_aqc_rl_profile_elem generic[1];
899 /* Configure L2 Node CGD (indirect 0x0414)
900 * This indirect command allows configuring a congestion domain for given L2
901 * node TEIDs in the scheduler topology.
903 struct ice_aqc_cfg_l2_node_cgd {
911 struct ice_aqc_cfg_l2_node_cgd_elem {
918 struct ice_aqc_cfg_l2_node_cgd_data {
919 struct ice_aqc_cfg_l2_node_cgd_elem elem[1];
923 /* Query Scheduler Resource Allocation (indirect 0x0412)
924 * This indirect command retrieves the scheduler resources allocated by
925 * EMP Firmware to the given PF.
927 struct ice_aqc_query_txsched_res {
934 struct ice_aqc_generic_sched_props {
936 __le16 logical_levels;
937 u8 flattening_bitmap;
946 struct ice_aqc_layer_props {
949 __le16 max_device_nodes;
952 __le16 max_sibl_grp_sz;
953 __le16 max_cir_rl_profiles;
954 __le16 max_eir_rl_profiles;
955 __le16 max_srl_profiles;
960 struct ice_aqc_query_txsched_res_resp {
961 struct ice_aqc_generic_sched_props sched_props;
962 struct ice_aqc_layer_props layer_props[ICE_AQC_TOPO_MAX_LEVEL_NUM];
966 /* Query Node to Root Topology (indirect 0x0413)
967 * This command uses ice_aqc_get_elem as its data buffer.
969 struct ice_aqc_query_node_to_root {
971 __le32 num_nodes; /* Response only */
977 /* Get PHY capabilities (indirect 0x0600) */
978 struct ice_aqc_get_phy_caps {
982 /* 18.0 - Report qualified modules */
983 #define ICE_AQC_GET_PHY_RQM BIT(0)
984 /* 18.1 - 18.2 : Report mode
985 * 00b - Report NVM capabilities
986 * 01b - Report topology capabilities
987 * 10b - Report SW configured
989 #define ICE_AQC_REPORT_MODE_S 1
990 #define ICE_AQC_REPORT_MODE_M (3 << ICE_AQC_REPORT_MODE_S)
991 #define ICE_AQC_REPORT_NVM_CAP 0
992 #define ICE_AQC_REPORT_TOPO_CAP BIT(1)
993 #define ICE_AQC_REPORT_SW_CFG BIT(2)
1000 /* This is #define of PHY type (Extended):
1001 * The first set of defines is for phy_type_low.
1003 #define ICE_PHY_TYPE_LOW_100BASE_TX BIT_ULL(0)
1004 #define ICE_PHY_TYPE_LOW_100M_SGMII BIT_ULL(1)
1005 #define ICE_PHY_TYPE_LOW_1000BASE_T BIT_ULL(2)
1006 #define ICE_PHY_TYPE_LOW_1000BASE_SX BIT_ULL(3)
1007 #define ICE_PHY_TYPE_LOW_1000BASE_LX BIT_ULL(4)
1008 #define ICE_PHY_TYPE_LOW_1000BASE_KX BIT_ULL(5)
1009 #define ICE_PHY_TYPE_LOW_1G_SGMII BIT_ULL(6)
1010 #define ICE_PHY_TYPE_LOW_2500BASE_T BIT_ULL(7)
1011 #define ICE_PHY_TYPE_LOW_2500BASE_X BIT_ULL(8)
1012 #define ICE_PHY_TYPE_LOW_2500BASE_KX BIT_ULL(9)
1013 #define ICE_PHY_TYPE_LOW_5GBASE_T BIT_ULL(10)
1014 #define ICE_PHY_TYPE_LOW_5GBASE_KR BIT_ULL(11)
1015 #define ICE_PHY_TYPE_LOW_10GBASE_T BIT_ULL(12)
1016 #define ICE_PHY_TYPE_LOW_10G_SFI_DA BIT_ULL(13)
1017 #define ICE_PHY_TYPE_LOW_10GBASE_SR BIT_ULL(14)
1018 #define ICE_PHY_TYPE_LOW_10GBASE_LR BIT_ULL(15)
1019 #define ICE_PHY_TYPE_LOW_10GBASE_KR_CR1 BIT_ULL(16)
1020 #define ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC BIT_ULL(17)
1021 #define ICE_PHY_TYPE_LOW_10G_SFI_C2C BIT_ULL(18)
1022 #define ICE_PHY_TYPE_LOW_25GBASE_T BIT_ULL(19)
1023 #define ICE_PHY_TYPE_LOW_25GBASE_CR BIT_ULL(20)
1024 #define ICE_PHY_TYPE_LOW_25GBASE_CR_S BIT_ULL(21)
1025 #define ICE_PHY_TYPE_LOW_25GBASE_CR1 BIT_ULL(22)
1026 #define ICE_PHY_TYPE_LOW_25GBASE_SR BIT_ULL(23)
1027 #define ICE_PHY_TYPE_LOW_25GBASE_LR BIT_ULL(24)
1028 #define ICE_PHY_TYPE_LOW_25GBASE_KR BIT_ULL(25)
1029 #define ICE_PHY_TYPE_LOW_25GBASE_KR_S BIT_ULL(26)
1030 #define ICE_PHY_TYPE_LOW_25GBASE_KR1 BIT_ULL(27)
1031 #define ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC BIT_ULL(28)
1032 #define ICE_PHY_TYPE_LOW_25G_AUI_C2C BIT_ULL(29)
1033 #define ICE_PHY_TYPE_LOW_40GBASE_CR4 BIT_ULL(30)
1034 #define ICE_PHY_TYPE_LOW_40GBASE_SR4 BIT_ULL(31)
1035 #define ICE_PHY_TYPE_LOW_40GBASE_LR4 BIT_ULL(32)
1036 #define ICE_PHY_TYPE_LOW_40GBASE_KR4 BIT_ULL(33)
1037 #define ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC BIT_ULL(34)
1038 #define ICE_PHY_TYPE_LOW_40G_XLAUI BIT_ULL(35)
1039 #define ICE_PHY_TYPE_LOW_50GBASE_CR2 BIT_ULL(36)
1040 #define ICE_PHY_TYPE_LOW_50GBASE_SR2 BIT_ULL(37)
1041 #define ICE_PHY_TYPE_LOW_50GBASE_LR2 BIT_ULL(38)
1042 #define ICE_PHY_TYPE_LOW_50GBASE_KR2 BIT_ULL(39)
1043 #define ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC BIT_ULL(40)
1044 #define ICE_PHY_TYPE_LOW_50G_LAUI2 BIT_ULL(41)
1045 #define ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC BIT_ULL(42)
1046 #define ICE_PHY_TYPE_LOW_50G_AUI2 BIT_ULL(43)
1047 #define ICE_PHY_TYPE_LOW_50GBASE_CP BIT_ULL(44)
1048 #define ICE_PHY_TYPE_LOW_50GBASE_SR BIT_ULL(45)
1049 #define ICE_PHY_TYPE_LOW_50GBASE_FR BIT_ULL(46)
1050 #define ICE_PHY_TYPE_LOW_50GBASE_LR BIT_ULL(47)
1051 #define ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4 BIT_ULL(48)
1052 #define ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC BIT_ULL(49)
1053 #define ICE_PHY_TYPE_LOW_50G_AUI1 BIT_ULL(50)
1054 #define ICE_PHY_TYPE_LOW_100GBASE_CR4 BIT_ULL(51)
1055 #define ICE_PHY_TYPE_LOW_100GBASE_SR4 BIT_ULL(52)
1056 #define ICE_PHY_TYPE_LOW_100GBASE_LR4 BIT_ULL(53)
1057 #define ICE_PHY_TYPE_LOW_100GBASE_KR4 BIT_ULL(54)
1058 #define ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC BIT_ULL(55)
1059 #define ICE_PHY_TYPE_LOW_100G_CAUI4 BIT_ULL(56)
1060 #define ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC BIT_ULL(57)
1061 #define ICE_PHY_TYPE_LOW_100G_AUI4 BIT_ULL(58)
1062 #define ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4 BIT_ULL(59)
1063 #define ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4 BIT_ULL(60)
1064 #define ICE_PHY_TYPE_LOW_100GBASE_CP2 BIT_ULL(61)
1065 #define ICE_PHY_TYPE_LOW_100GBASE_SR2 BIT_ULL(62)
1066 #define ICE_PHY_TYPE_LOW_100GBASE_DR BIT_ULL(63)
1067 #define ICE_PHY_TYPE_LOW_MAX_INDEX 63
1068 /* The second set of defines is for phy_type_high. */
1069 #define ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4 BIT_ULL(0)
1070 #define ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC BIT_ULL(1)
1071 #define ICE_PHY_TYPE_HIGH_100G_CAUI2 BIT_ULL(2)
1072 #define ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC BIT_ULL(3)
1073 #define ICE_PHY_TYPE_HIGH_100G_AUI2 BIT_ULL(4)
1074 #define ICE_PHY_TYPE_HIGH_MAX_INDEX 19
1076 struct ice_aqc_get_phy_caps_data {
1077 __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */
1078 __le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */
1080 #define ICE_AQC_PHY_EN_TX_LINK_PAUSE BIT(0)
1081 #define ICE_AQC_PHY_EN_RX_LINK_PAUSE BIT(1)
1082 #define ICE_AQC_PHY_LOW_POWER_MODE BIT(2)
1083 #define ICE_AQC_PHY_EN_LINK BIT(3)
1084 #define ICE_AQC_PHY_AN_MODE BIT(4)
1085 #define ICE_AQC_PHY_EN_MOD_QUAL BIT(5)
1086 #define ICE_AQC_PHY_EN_LESM BIT(6)
1087 #define ICE_AQC_PHY_EN_AUTO_FEC BIT(7)
1088 #define ICE_AQC_PHY_CAPS_MASK MAKEMASK(0xff, 0)
1090 #define ICE_AQC_PHY_EN_D3COLD_LOW_POWER_AUTONEG BIT(0)
1092 #define ICE_AQC_PHY_EEE_EN_100BASE_TX BIT(0)
1093 #define ICE_AQC_PHY_EEE_EN_1000BASE_T BIT(1)
1094 #define ICE_AQC_PHY_EEE_EN_10GBASE_T BIT(2)
1095 #define ICE_AQC_PHY_EEE_EN_1000BASE_KX BIT(3)
1096 #define ICE_AQC_PHY_EEE_EN_10GBASE_KR BIT(4)
1097 #define ICE_AQC_PHY_EEE_EN_25GBASE_KR BIT(5)
1098 #define ICE_AQC_PHY_EEE_EN_40GBASE_KR4 BIT(6)
1099 #define ICE_AQC_PHY_EEE_EN_50GBASE_KR2 BIT(7)
1100 #define ICE_AQC_PHY_EEE_EN_50GBASE_KR_PAM4 BIT(8)
1101 #define ICE_AQC_PHY_EEE_EN_100GBASE_KR4 BIT(9)
1102 #define ICE_AQC_PHY_EEE_EN_100GBASE_KR2_PAM4 BIT(10)
1104 u8 phy_id_oui[4]; /* PHY/Module ID connected on the port */
1106 u8 link_fec_options;
1107 #define ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN BIT(0)
1108 #define ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ BIT(1)
1109 #define ICE_AQC_PHY_FEC_25G_RS_528_REQ BIT(2)
1110 #define ICE_AQC_PHY_FEC_25G_KR_REQ BIT(3)
1111 #define ICE_AQC_PHY_FEC_25G_RS_544_REQ BIT(4)
1112 #define ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN BIT(6)
1113 #define ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN BIT(7)
1114 #define ICE_AQC_PHY_FEC_MASK MAKEMASK(0xdf, 0)
1115 u8 extended_compliance_code;
1116 #define ICE_MODULE_TYPE_TOTAL_BYTE 3
1117 u8 module_type[ICE_MODULE_TYPE_TOTAL_BYTE];
1118 #define ICE_AQC_MOD_TYPE_BYTE0_SFP_PLUS 0xA0
1119 #define ICE_AQC_MOD_TYPE_BYTE0_QSFP_PLUS 0x80
1120 #define ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_PASSIVE BIT(0)
1121 #define ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_ACTIVE BIT(1)
1122 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_SR BIT(4)
1123 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_LR BIT(5)
1124 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_LRM BIT(6)
1125 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_ER BIT(7)
1126 #define ICE_AQC_MOD_TYPE_BYTE2_SFP_PLUS 0xA0
1127 #define ICE_AQC_MOD_TYPE_BYTE2_QSFP_PLUS 0x86
1128 u8 qualified_module_count;
1129 #define ICE_AQC_QUAL_MOD_COUNT_MAX 16
1136 } qual_modules[ICE_AQC_QUAL_MOD_COUNT_MAX];
1140 /* Set PHY capabilities (direct 0x0601)
1141 * NOTE: This command must be followed by setup link and restart auto-neg
1143 struct ice_aqc_set_phy_cfg {
1151 /* Set PHY config command data structure */
1152 struct ice_aqc_set_phy_cfg_data {
1153 __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */
1154 __le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */
1156 #define ICE_AQ_PHY_ENA_TX_PAUSE_ABILITY BIT(0)
1157 #define ICE_AQ_PHY_ENA_RX_PAUSE_ABILITY BIT(1)
1158 #define ICE_AQ_PHY_ENA_LOW_POWER BIT(2)
1159 #define ICE_AQ_PHY_ENA_LINK BIT(3)
1160 #define ICE_AQ_PHY_ENA_AUTO_LINK_UPDT BIT(5)
1161 #define ICE_AQ_PHY_ENA_LESM BIT(6)
1162 #define ICE_AQ_PHY_ENA_AUTO_FEC BIT(7)
1164 __le16 eee_cap; /* Value from ice_aqc_get_phy_caps */
1166 u8 link_fec_opt; /* Use defines from ice_aqc_get_phy_caps */
1171 /* Set MAC Config command data structure (direct 0x0603) */
1172 struct ice_aqc_set_mac_cfg {
1173 __le16 max_frame_size;
1175 #define ICE_AQ_SET_MAC_PACE_S 3
1176 #define ICE_AQ_SET_MAC_PACE_M (0xF << ICE_AQ_SET_MAC_PACE_S)
1177 #define ICE_AQ_SET_MAC_PACE_TYPE_M BIT(7)
1178 #define ICE_AQ_SET_MAC_PACE_TYPE_RATE 0
1179 #define ICE_AQ_SET_MAC_PACE_TYPE_FIXED ICE_AQ_SET_MAC_PACE_TYPE_M
1181 __le16 tx_tmr_value;
1182 __le16 fc_refresh_threshold;
1184 #define ICE_AQ_SET_MAC_AUTO_DROP_MASK BIT(0)
1185 #define ICE_AQ_SET_MAC_AUTO_DROP_NONE 0
1186 #define ICE_AQ_SET_MAC_AUTO_DROP_BLOCKING_PKTS BIT(0)
1191 /* Restart AN command data structure (direct 0x0605)
1192 * Also used for response, with only the lport_num field present.
1194 struct ice_aqc_restart_an {
1198 #define ICE_AQC_RESTART_AN_LINK_RESTART BIT(1)
1199 #define ICE_AQC_RESTART_AN_LINK_ENABLE BIT(2)
1204 /* Get link status (indirect 0x0607), also used for Link Status Event */
1205 struct ice_aqc_get_link_status {
1209 #define ICE_AQ_LSE_M 0x3
1210 #define ICE_AQ_LSE_NOP 0x0
1211 #define ICE_AQ_LSE_DIS 0x2
1212 #define ICE_AQ_LSE_ENA 0x3
1213 /* only response uses this flag */
1214 #define ICE_AQ_LSE_IS_ENABLED 0x1
1221 /* Get link status response data structure, also used for Link Status Event */
1222 struct ice_aqc_get_link_status_data {
1223 u8 topo_media_conflict;
1224 #define ICE_AQ_LINK_TOPO_CONFLICT BIT(0)
1225 #define ICE_AQ_LINK_MEDIA_CONFLICT BIT(1)
1226 #define ICE_AQ_LINK_TOPO_CORRUPT BIT(2)
1229 #define ICE_AQ_LINK_UP BIT(0) /* Link Status */
1230 #define ICE_AQ_LINK_FAULT BIT(1)
1231 #define ICE_AQ_LINK_FAULT_TX BIT(2)
1232 #define ICE_AQ_LINK_FAULT_RX BIT(3)
1233 #define ICE_AQ_LINK_FAULT_REMOTE BIT(4)
1234 #define ICE_AQ_LINK_UP_PORT BIT(5) /* External Port Link Status */
1235 #define ICE_AQ_MEDIA_AVAILABLE BIT(6)
1236 #define ICE_AQ_SIGNAL_DETECT BIT(7)
1238 #define ICE_AQ_AN_COMPLETED BIT(0)
1239 #define ICE_AQ_LP_AN_ABILITY BIT(1)
1240 #define ICE_AQ_PD_FAULT BIT(2) /* Parallel Detection Fault */
1241 #define ICE_AQ_FEC_EN BIT(3)
1242 #define ICE_AQ_PHY_LOW_POWER BIT(4) /* Low Power State */
1243 #define ICE_AQ_LINK_PAUSE_TX BIT(5)
1244 #define ICE_AQ_LINK_PAUSE_RX BIT(6)
1245 #define ICE_AQ_QUALIFIED_MODULE BIT(7)
1247 #define ICE_AQ_LINK_PHY_TEMP_ALARM BIT(0)
1248 #define ICE_AQ_LINK_EXCESSIVE_ERRORS BIT(1) /* Excessive Link Errors */
1249 /* Port Tx Suspended */
1250 #define ICE_AQ_LINK_TX_S 2
1251 #define ICE_AQ_LINK_TX_M (0x03 << ICE_AQ_LINK_TX_S)
1252 #define ICE_AQ_LINK_TX_ACTIVE 0
1253 #define ICE_AQ_LINK_TX_DRAINED 1
1254 #define ICE_AQ_LINK_TX_FLUSHED 3
1256 __le16 max_frame_size;
1258 #define ICE_AQ_LINK_25G_KR_FEC_EN BIT(0)
1259 #define ICE_AQ_LINK_25G_RS_528_FEC_EN BIT(1)
1260 #define ICE_AQ_LINK_25G_RS_544_FEC_EN BIT(2)
1261 #define ICE_AQ_FEC_MASK MAKEMASK(0x7, 0)
1263 #define ICE_AQ_CFG_PACING_S 3
1264 #define ICE_AQ_CFG_PACING_M (0xF << ICE_AQ_CFG_PACING_S)
1265 #define ICE_AQ_CFG_PACING_TYPE_M BIT(7)
1266 #define ICE_AQ_CFG_PACING_TYPE_AVG 0
1267 #define ICE_AQ_CFG_PACING_TYPE_FIXED ICE_AQ_CFG_PACING_TYPE_M
1268 /* External Device Power Ability */
1270 #define ICE_AQ_PWR_CLASS_M 0x3
1271 #define ICE_AQ_LINK_PWR_BASET_LOW_HIGH 0
1272 #define ICE_AQ_LINK_PWR_BASET_HIGH 1
1273 #define ICE_AQ_LINK_PWR_QSFP_CLASS_1 0
1274 #define ICE_AQ_LINK_PWR_QSFP_CLASS_2 1
1275 #define ICE_AQ_LINK_PWR_QSFP_CLASS_3 2
1276 #define ICE_AQ_LINK_PWR_QSFP_CLASS_4 3
1278 #define ICE_AQ_LINK_SPEED_10MB BIT(0)
1279 #define ICE_AQ_LINK_SPEED_100MB BIT(1)
1280 #define ICE_AQ_LINK_SPEED_1000MB BIT(2)
1281 #define ICE_AQ_LINK_SPEED_2500MB BIT(3)
1282 #define ICE_AQ_LINK_SPEED_5GB BIT(4)
1283 #define ICE_AQ_LINK_SPEED_10GB BIT(5)
1284 #define ICE_AQ_LINK_SPEED_20GB BIT(6)
1285 #define ICE_AQ_LINK_SPEED_25GB BIT(7)
1286 #define ICE_AQ_LINK_SPEED_40GB BIT(8)
1287 #define ICE_AQ_LINK_SPEED_50GB BIT(9)
1288 #define ICE_AQ_LINK_SPEED_100GB BIT(10)
1289 #define ICE_AQ_LINK_SPEED_UNKNOWN BIT(15)
1290 __le32 reserved3; /* Aligns next field to 8-byte boundary */
1291 __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */
1292 __le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */
1296 /* Set event mask command (direct 0x0613) */
1297 struct ice_aqc_set_event_mask {
1301 #define ICE_AQ_LINK_EVENT_UPDOWN BIT(1)
1302 #define ICE_AQ_LINK_EVENT_MEDIA_NA BIT(2)
1303 #define ICE_AQ_LINK_EVENT_LINK_FAULT BIT(3)
1304 #define ICE_AQ_LINK_EVENT_PHY_TEMP_ALARM BIT(4)
1305 #define ICE_AQ_LINK_EVENT_EXCESSIVE_ERRORS BIT(5)
1306 #define ICE_AQ_LINK_EVENT_SIGNAL_DETECT BIT(6)
1307 #define ICE_AQ_LINK_EVENT_AN_COMPLETED BIT(7)
1308 #define ICE_AQ_LINK_EVENT_MODULE_QUAL_FAIL BIT(8)
1309 #define ICE_AQ_LINK_EVENT_PORT_TX_SUSPENDED BIT(9)
1315 /* Set MAC Loopback command (direct 0x0620) */
1316 struct ice_aqc_set_mac_lb {
1318 #define ICE_AQ_MAC_LB_EN BIT(0)
1319 #define ICE_AQ_MAC_LB_OSC_CLK BIT(1)
1327 /* Set Port Identification LED (direct, 0x06E9) */
1328 struct ice_aqc_set_port_id_led {
1331 #define ICE_AQC_PORT_ID_PORT_NUM_VALID BIT(0)
1333 #define ICE_AQC_PORT_IDENT_LED_BLINK BIT(0)
1334 #define ICE_AQC_PORT_IDENT_LED_ORIG 0
1340 /* NVM Read command (indirect 0x0701)
1341 * NVM Erase commands (direct 0x0702)
1342 * NVM Update commands (indirect 0x0703)
1344 struct ice_aqc_nvm {
1348 #define ICE_AQC_NVM_LAST_CMD BIT(0)
1349 #define ICE_AQC_NVM_PCIR_REQ BIT(0) /* Used by NVM Update reply */
1350 #define ICE_AQC_NVM_PRESERVATION_S 1
1351 #define ICE_AQC_NVM_PRESERVATION_M (3 << ICE_AQC_NVM_PRESERVATION_S)
1352 #define ICE_AQC_NVM_NO_PRESERVATION (0 << ICE_AQC_NVM_PRESERVATION_S)
1353 #define ICE_AQC_NVM_PRESERVE_ALL BIT(1)
1354 #define ICE_AQC_NVM_FACTORY_DEFAULT (2 << ICE_AQC_NVM_PRESERVATION_S)
1355 #define ICE_AQC_NVM_PRESERVE_SELECTED (3 << ICE_AQC_NVM_PRESERVATION_S)
1356 #define ICE_AQC_NVM_FLASH_ONLY BIT(7)
1357 __le16 module_typeid;
1359 #define ICE_AQC_NVM_ERASE_LEN 0xFFFF
1365 /* Used for 0x0704 as well as for 0x0705 commands */
1366 struct ice_aqc_nvm_cfg {
1368 #define ICE_AQC_ANVM_MULTIPLE_ELEMS BIT(0)
1369 #define ICE_AQC_ANVM_IMMEDIATE_FIELD BIT(1)
1370 #define ICE_AQC_ANVM_NEW_CFG BIT(2)
1380 struct ice_aqc_nvm_cfg_data {
1382 __le16 field_options;
1387 /* NVM Checksum Command (direct, 0x0706) */
1388 struct ice_aqc_nvm_checksum {
1390 #define ICE_AQC_NVM_CHECKSUM_VERIFY BIT(0)
1391 #define ICE_AQC_NVM_CHECKSUM_RECALC BIT(1)
1393 __le16 checksum; /* Used only by response */
1394 #define ICE_AQC_NVM_CHECKSUM_CORRECT 0xBABA
1402 /* Get/Set RSS key (indirect 0x0B04/0x0B02) */
1403 struct ice_aqc_get_set_rss_key {
1404 #define ICE_AQC_GSET_RSS_KEY_VSI_VALID BIT(15)
1405 #define ICE_AQC_GSET_RSS_KEY_VSI_ID_S 0
1406 #define ICE_AQC_GSET_RSS_KEY_VSI_ID_M (0x3FF << ICE_AQC_GSET_RSS_KEY_VSI_ID_S)
1414 #define ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE 0x28
1415 #define ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE 0xC
1417 struct ice_aqc_get_set_rss_keys {
1418 u8 standard_rss_key[ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE];
1419 u8 extended_hash_key[ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE];
1423 /* Get/Set RSS LUT (indirect 0x0B05/0x0B03) */
1424 struct ice_aqc_get_set_rss_lut {
1425 #define ICE_AQC_GSET_RSS_LUT_VSI_VALID BIT(15)
1426 #define ICE_AQC_GSET_RSS_LUT_VSI_ID_S 0
1427 #define ICE_AQC_GSET_RSS_LUT_VSI_ID_M (0x1FF << ICE_AQC_GSET_RSS_LUT_VSI_ID_S)
1429 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S 0
1430 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_M \
1431 (0x3 << ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S)
1433 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_VSI 0
1434 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF 1
1435 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL 2
1437 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S 2
1438 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M \
1439 (0x3 << ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S)
1441 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128 128
1442 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128_FLAG 0
1443 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512 512
1444 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512_FLAG 1
1445 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K 2048
1446 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K_FLAG 2
1448 #define ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S 4
1449 #define ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_M \
1450 (0xF << ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S)
1462 /* Add Tx LAN Queues (indirect 0x0C30) */
1463 struct ice_aqc_add_txqs {
1472 /* This is the descriptor of each queue entry for the Add Tx LAN Queues
1473 * command (0x0C30). Only used within struct ice_aqc_add_tx_qgrp.
1475 struct ice_aqc_add_txqs_perq {
1481 struct ice_aqc_txsched_elem info;
1485 /* The format of the command buffer for Add Tx LAN Queues (0x0C30)
1486 * is an array of the following structs. Please note that the length of
1487 * each struct ice_aqc_add_tx_qgrp is variable due
1488 * to the variable number of queues in each group!
1490 struct ice_aqc_add_tx_qgrp {
1494 struct ice_aqc_add_txqs_perq txqs[1];
1498 /* Disable Tx LAN Queues (indirect 0x0C31) */
1499 struct ice_aqc_dis_txqs {
1501 #define ICE_AQC_Q_DIS_CMD_S 0
1502 #define ICE_AQC_Q_DIS_CMD_M (0x3 << ICE_AQC_Q_DIS_CMD_S)
1503 #define ICE_AQC_Q_DIS_CMD_NO_FUNC_RESET (0 << ICE_AQC_Q_DIS_CMD_S)
1504 #define ICE_AQC_Q_DIS_CMD_VM_RESET BIT(ICE_AQC_Q_DIS_CMD_S)
1505 #define ICE_AQC_Q_DIS_CMD_VF_RESET (2 << ICE_AQC_Q_DIS_CMD_S)
1506 #define ICE_AQC_Q_DIS_CMD_PF_RESET (3 << ICE_AQC_Q_DIS_CMD_S)
1507 #define ICE_AQC_Q_DIS_CMD_SUBSEQ_CALL BIT(2)
1508 #define ICE_AQC_Q_DIS_CMD_FLUSH_PIPE BIT(3)
1510 __le16 vmvf_and_timeout;
1511 #define ICE_AQC_Q_DIS_VMVF_NUM_S 0
1512 #define ICE_AQC_Q_DIS_VMVF_NUM_M (0x3FF << ICE_AQC_Q_DIS_VMVF_NUM_S)
1513 #define ICE_AQC_Q_DIS_TIMEOUT_S 10
1514 #define ICE_AQC_Q_DIS_TIMEOUT_M (0x3F << ICE_AQC_Q_DIS_TIMEOUT_S)
1515 __le32 blocked_cgds;
1521 /* The buffer for Disable Tx LAN Queues (indirect 0x0C31)
1522 * contains the following structures, arrayed one after the
1524 * Note: Since the q_id is 16 bits wide, if the
1525 * number of queues is even, then 2 bytes of alignment MUST be
1526 * added before the start of the next group, to allow correct
1527 * alignment of the parent_teid field.
1529 struct ice_aqc_dis_txq_item {
1533 /* The length of the q_id array varies according to num_qs */
1535 /* This only applies from F8 onward */
1536 #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S 15
1537 #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_LAN_Q \
1538 (0 << ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S)
1539 #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_RDMA_QSET \
1540 (1 << ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S)
1544 struct ice_aqc_dis_txq {
1545 struct ice_aqc_dis_txq_item qgrps[1];
1549 /* Tx LAN Queues Cleanup Event (0x0C31) */
1550 struct ice_aqc_txqs_cleanup {
1557 /* Move / Reconfigure Tx Queues (indirect 0x0C32) */
1558 struct ice_aqc_move_txqs {
1560 #define ICE_AQC_Q_CMD_TYPE_S 0
1561 #define ICE_AQC_Q_CMD_TYPE_M (0x3 << ICE_AQC_Q_CMD_TYPE_S)
1562 #define ICE_AQC_Q_CMD_TYPE_MOVE 1
1563 #define ICE_AQC_Q_CMD_TYPE_TC_CHANGE 2
1564 #define ICE_AQC_Q_CMD_TYPE_MOVE_AND_TC 3
1565 #define ICE_AQC_Q_CMD_SUBSEQ_CALL BIT(2)
1566 #define ICE_AQC_Q_CMD_FLUSH_PIPE BIT(3)
1570 #define ICE_AQC_Q_CMD_TIMEOUT_S 2
1571 #define ICE_AQC_Q_CMD_TIMEOUT_M (0x3F << ICE_AQC_Q_CMD_TIMEOUT_S)
1572 __le32 blocked_cgds;
1578 /* This is the descriptor of each queue entry for the move Tx LAN Queues
1581 struct ice_aqc_move_txqs_elem {
1589 struct ice_aqc_move_txqs_data {
1592 struct ice_aqc_move_txqs_elem txqs[1];
1597 /* Download Package (indirect 0x0C40) */
1598 /* Also used for Update Package (indirect 0x0C42) */
1599 struct ice_aqc_download_pkg {
1601 #define ICE_AQC_DOWNLOAD_PKG_LAST_BUF 0x01
1608 struct ice_aqc_download_pkg_resp {
1609 __le32 error_offset;
1615 /* Get Package Info List (indirect 0x0C43) */
1616 struct ice_aqc_get_pkg_info_list {
1623 /* Version format for packages */
1624 struct ice_pkg_ver {
1631 #define ICE_PKG_NAME_SIZE 32
1633 struct ice_aqc_get_pkg_info {
1634 struct ice_pkg_ver ver;
1635 char name[ICE_PKG_NAME_SIZE];
1638 u8 is_active_at_boot;
1642 /* Get Package Info List response buffer format (0x0C43) */
1643 struct ice_aqc_get_pkg_info_resp {
1645 struct ice_aqc_get_pkg_info pkg_info[1];
1651 /* Lan Queue Overflow Event (direct, 0x1001) */
1652 struct ice_aqc_event_lan_overflow {
1653 __le32 prtdcb_ruptq;
1660 /* Configure Firmware Logging Command (indirect 0xFF09)
1661 * Logging Information Read Response (indirect 0xFF10)
1662 * Note: The 0xFF10 command has no input parameters.
1664 struct ice_aqc_fw_logging {
1666 #define ICE_AQC_FW_LOG_AQ_EN BIT(0)
1667 #define ICE_AQC_FW_LOG_UART_EN BIT(1)
1669 u8 log_ctrl_valid; /* Not used by 0xFF10 Response */
1670 #define ICE_AQC_FW_LOG_AQ_VALID BIT(0)
1671 #define ICE_AQC_FW_LOG_UART_VALID BIT(1)
1678 enum ice_aqc_fw_logging_mod {
1679 ICE_AQC_FW_LOG_ID_GENERAL = 0,
1680 ICE_AQC_FW_LOG_ID_CTRL,
1681 ICE_AQC_FW_LOG_ID_LINK,
1682 ICE_AQC_FW_LOG_ID_LINK_TOPO,
1683 ICE_AQC_FW_LOG_ID_DNL,
1684 ICE_AQC_FW_LOG_ID_I2C,
1685 ICE_AQC_FW_LOG_ID_SDP,
1686 ICE_AQC_FW_LOG_ID_MDIO,
1687 ICE_AQC_FW_LOG_ID_ADMINQ,
1688 ICE_AQC_FW_LOG_ID_HDMA,
1689 ICE_AQC_FW_LOG_ID_LLDP,
1690 ICE_AQC_FW_LOG_ID_DCBX,
1691 ICE_AQC_FW_LOG_ID_DCB,
1692 ICE_AQC_FW_LOG_ID_NETPROXY,
1693 ICE_AQC_FW_LOG_ID_NVM,
1694 ICE_AQC_FW_LOG_ID_AUTH,
1695 ICE_AQC_FW_LOG_ID_VPD,
1696 ICE_AQC_FW_LOG_ID_IOSF,
1697 ICE_AQC_FW_LOG_ID_PARSER,
1698 ICE_AQC_FW_LOG_ID_SW,
1699 ICE_AQC_FW_LOG_ID_SCHEDULER,
1700 ICE_AQC_FW_LOG_ID_TXQ,
1701 ICE_AQC_FW_LOG_ID_RSVD,
1702 ICE_AQC_FW_LOG_ID_POST,
1703 ICE_AQC_FW_LOG_ID_WATCHDOG,
1704 ICE_AQC_FW_LOG_ID_TASK_DISPATCH,
1705 ICE_AQC_FW_LOG_ID_MNG,
1706 ICE_AQC_FW_LOG_ID_MAX,
1709 /* This is the buffer for both of the logging commands.
1710 * The entry array size depends on the datalen parameter in the descriptor.
1711 * There will be a total of datalen / 2 entries.
1713 struct ice_aqc_fw_logging_data {
1715 #define ICE_AQC_FW_LOG_ID_S 0
1716 #define ICE_AQC_FW_LOG_ID_M (0xFFF << ICE_AQC_FW_LOG_ID_S)
1718 #define ICE_AQC_FW_LOG_CONF_SUCCESS 0 /* Used by response */
1719 #define ICE_AQC_FW_LOG_CONF_BAD_INDX BIT(12) /* Used by response */
1721 #define ICE_AQC_FW_LOG_EN_S 12
1722 #define ICE_AQC_FW_LOG_EN_M (0xF << ICE_AQC_FW_LOG_EN_S)
1723 #define ICE_AQC_FW_LOG_INFO_EN BIT(12) /* Used by command */
1724 #define ICE_AQC_FW_LOG_INIT_EN BIT(13) /* Used by command */
1725 #define ICE_AQC_FW_LOG_FLOW_EN BIT(14) /* Used by command */
1726 #define ICE_AQC_FW_LOG_ERR_EN BIT(15) /* Used by command */
1730 /* Get/Clear FW Log (indirect 0xFF11) */
1731 struct ice_aqc_get_clear_fw_log {
1733 #define ICE_AQC_FW_LOG_CLEAR BIT(0)
1734 #define ICE_AQC_FW_LOG_MORE_DATA_AVAIL BIT(1)
1742 * struct ice_aq_desc - Admin Queue (AQ) descriptor
1743 * @flags: ICE_AQ_FLAG_* flags
1744 * @opcode: AQ command opcode
1745 * @datalen: length in bytes of indirect/external data buffer
1746 * @retval: return value from firmware
1747 * @cookie_h: opaque data high-half
1748 * @cookie_l: opaque data low-half
1749 * @params: command-specific parameters
1751 * Descriptor format for commands the driver posts on the Admin Transmit Queue
1752 * (ATQ). The firmware writes back onto the command descriptor and returns
1753 * the result of the command. Asynchronous events that are not an immediate
1754 * result of the command are written to the Admin Receive Queue (ARQ) using
1755 * the same descriptor format. Descriptors are in little-endian notation with
1758 struct ice_aq_desc {
1767 struct ice_aqc_generic generic;
1768 struct ice_aqc_get_ver get_ver;
1769 struct ice_aqc_q_shutdown q_shutdown;
1770 struct ice_aqc_req_res res_owner;
1771 struct ice_aqc_manage_mac_read mac_read;
1772 struct ice_aqc_manage_mac_write mac_write;
1773 struct ice_aqc_clear_pxe clear_pxe;
1774 struct ice_aqc_list_caps get_cap;
1775 struct ice_aqc_get_phy_caps get_phy;
1776 struct ice_aqc_set_phy_cfg set_phy;
1777 struct ice_aqc_restart_an restart_an;
1778 struct ice_aqc_set_port_id_led set_port_id_led;
1779 struct ice_aqc_get_sw_cfg get_sw_conf;
1780 struct ice_aqc_sw_rules sw_rules;
1781 struct ice_aqc_get_topo get_topo;
1782 struct ice_aqc_sched_elem_cmd sched_elem_cmd;
1783 struct ice_aqc_query_txsched_res query_sched_res;
1784 struct ice_aqc_query_node_to_root query_node_to_root;
1785 struct ice_aqc_cfg_l2_node_cgd cfg_l2_node_cgd;
1786 struct ice_aqc_rl_profile rl_profile;
1788 struct ice_aqc_nvm nvm;
1789 struct ice_aqc_nvm_cfg nvm_cfg;
1790 struct ice_aqc_nvm_checksum nvm_checksum;
1791 struct ice_aqc_get_set_rss_lut get_set_rss_lut;
1792 struct ice_aqc_get_set_rss_key get_set_rss_key;
1793 struct ice_aqc_add_txqs add_txqs;
1794 struct ice_aqc_dis_txqs dis_txqs;
1795 struct ice_aqc_txqs_cleanup txqs_cleanup;
1796 struct ice_aqc_add_get_update_free_vsi vsi_cmd;
1797 struct ice_aqc_add_update_free_vsi_resp add_update_free_vsi_res;
1798 struct ice_aqc_download_pkg download_pkg;
1799 struct ice_aqc_get_pkg_info_list get_pkg_info_list;
1800 struct ice_aqc_fw_logging fw_logging;
1801 struct ice_aqc_get_clear_fw_log get_clear_fw_log;
1802 struct ice_aqc_set_mac_lb set_mac_lb;
1803 struct ice_aqc_alloc_free_res_cmd sw_res_ctrl;
1804 struct ice_aqc_set_mac_cfg set_mac_cfg;
1805 struct ice_aqc_set_event_mask set_event_mask;
1806 struct ice_aqc_get_link_status get_link_status;
1811 /* FW defined boundary for a large buffer, 4k >= Large buffer > 512 bytes */
1812 #define ICE_AQ_LG_BUF 512
1814 /* Flags sub-structure
1815 * |0 |1 |2 |3 |4 |5 |6 |7 |8 |9 |10 |11 |12 |13 |14 |15 |
1816 * |DD |CMP|ERR|VFE| * * RESERVED * * |LB |RD |VFC|BUF|SI |EI |FE |
1819 /* command flags and offsets */
1820 #define ICE_AQ_FLAG_DD_S 0
1821 #define ICE_AQ_FLAG_CMP_S 1
1822 #define ICE_AQ_FLAG_ERR_S 2
1823 #define ICE_AQ_FLAG_VFE_S 3
1824 #define ICE_AQ_FLAG_LB_S 9
1825 #define ICE_AQ_FLAG_RD_S 10
1826 #define ICE_AQ_FLAG_VFC_S 11
1827 #define ICE_AQ_FLAG_BUF_S 12
1828 #define ICE_AQ_FLAG_SI_S 13
1829 #define ICE_AQ_FLAG_EI_S 14
1830 #define ICE_AQ_FLAG_FE_S 15
1832 #define ICE_AQ_FLAG_DD BIT(ICE_AQ_FLAG_DD_S) /* 0x1 */
1833 #define ICE_AQ_FLAG_CMP BIT(ICE_AQ_FLAG_CMP_S) /* 0x2 */
1834 #define ICE_AQ_FLAG_ERR BIT(ICE_AQ_FLAG_ERR_S) /* 0x4 */
1835 #define ICE_AQ_FLAG_VFE BIT(ICE_AQ_FLAG_VFE_S) /* 0x8 */
1836 #define ICE_AQ_FLAG_LB BIT(ICE_AQ_FLAG_LB_S) /* 0x200 */
1837 #define ICE_AQ_FLAG_RD BIT(ICE_AQ_FLAG_RD_S) /* 0x400 */
1838 #define ICE_AQ_FLAG_VFC BIT(ICE_AQ_FLAG_VFC_S) /* 0x800 */
1839 #define ICE_AQ_FLAG_BUF BIT(ICE_AQ_FLAG_BUF_S) /* 0x1000 */
1840 #define ICE_AQ_FLAG_SI BIT(ICE_AQ_FLAG_SI_S) /* 0x2000 */
1841 #define ICE_AQ_FLAG_EI BIT(ICE_AQ_FLAG_EI_S) /* 0x4000 */
1842 #define ICE_AQ_FLAG_FE BIT(ICE_AQ_FLAG_FE_S) /* 0x8000 */
1846 ICE_AQ_RC_OK = 0, /* Success */
1847 ICE_AQ_RC_EPERM = 1, /* Operation not permitted */
1848 ICE_AQ_RC_ENOENT = 2, /* No such element */
1849 ICE_AQ_RC_ESRCH = 3, /* Bad opcode */
1850 ICE_AQ_RC_EINTR = 4, /* Operation interrupted */
1851 ICE_AQ_RC_EIO = 5, /* I/O error */
1852 ICE_AQ_RC_ENXIO = 6, /* No such resource */
1853 ICE_AQ_RC_E2BIG = 7, /* Arg too long */
1854 ICE_AQ_RC_EAGAIN = 8, /* Try again */
1855 ICE_AQ_RC_ENOMEM = 9, /* Out of memory */
1856 ICE_AQ_RC_EACCES = 10, /* Permission denied */
1857 ICE_AQ_RC_EFAULT = 11, /* Bad address */
1858 ICE_AQ_RC_EBUSY = 12, /* Device or resource busy */
1859 ICE_AQ_RC_EEXIST = 13, /* Object already exists */
1860 ICE_AQ_RC_EINVAL = 14, /* Invalid argument */
1861 ICE_AQ_RC_ENOTTY = 15, /* Not a typewriter */
1862 ICE_AQ_RC_ENOSPC = 16, /* No space left or allocation failure */
1863 ICE_AQ_RC_ENOSYS = 17, /* Function not implemented */
1864 ICE_AQ_RC_ERANGE = 18, /* Parameter out of range */
1865 ICE_AQ_RC_EFLUSHED = 19, /* Cmd flushed due to prev cmd error */
1866 ICE_AQ_RC_BAD_ADDR = 20, /* Descriptor contains a bad pointer */
1867 ICE_AQ_RC_EMODE = 21, /* Op not allowed in current dev mode */
1868 ICE_AQ_RC_EFBIG = 22, /* File too big */
1869 ICE_AQ_RC_ESBCOMP = 23, /* SB-IOSF completion unsuccessful */
1870 ICE_AQ_RC_ENOSEC = 24, /* Missing security manifest */
1871 ICE_AQ_RC_EBADSIG = 25, /* Bad RSA signature */
1872 ICE_AQ_RC_ESVN = 26, /* SVN number prohibits this package */
1873 ICE_AQ_RC_EBADMAN = 27, /* Manifest hash mismatch */
1874 ICE_AQ_RC_EBADBUF = 28, /* Buffer hash mismatches manifest */
1877 /* Admin Queue command opcodes */
1878 enum ice_adminq_opc {
1880 ice_aqc_opc_get_ver = 0x0001,
1881 ice_aqc_opc_driver_ver = 0x0002,
1882 ice_aqc_opc_q_shutdown = 0x0003,
1883 ice_aqc_opc_get_exp_err = 0x0005,
1885 /* resource ownership */
1886 ice_aqc_opc_req_res = 0x0008,
1887 ice_aqc_opc_release_res = 0x0009,
1889 /* device/function capabilities */
1890 ice_aqc_opc_list_func_caps = 0x000A,
1891 ice_aqc_opc_list_dev_caps = 0x000B,
1893 /* manage MAC address */
1894 ice_aqc_opc_manage_mac_read = 0x0107,
1895 ice_aqc_opc_manage_mac_write = 0x0108,
1898 ice_aqc_opc_clear_pxe_mode = 0x0110,
1900 /* internal switch commands */
1901 ice_aqc_opc_get_sw_cfg = 0x0200,
1903 /* Alloc/Free/Get Resources */
1904 ice_aqc_opc_get_res_alloc = 0x0204,
1905 ice_aqc_opc_alloc_res = 0x0208,
1906 ice_aqc_opc_free_res = 0x0209,
1907 ice_aqc_opc_get_allocd_res_desc = 0x020A,
1910 ice_aqc_opc_add_vsi = 0x0210,
1911 ice_aqc_opc_update_vsi = 0x0211,
1912 ice_aqc_opc_get_vsi_params = 0x0212,
1913 ice_aqc_opc_free_vsi = 0x0213,
1917 /* switch rules population commands */
1918 ice_aqc_opc_add_sw_rules = 0x02A0,
1919 ice_aqc_opc_update_sw_rules = 0x02A1,
1920 ice_aqc_opc_remove_sw_rules = 0x02A2,
1921 ice_aqc_opc_get_sw_rules = 0x02A3,
1922 ice_aqc_opc_clear_pf_cfg = 0x02A4,
1925 /* transmit scheduler commands */
1926 ice_aqc_opc_get_dflt_topo = 0x0400,
1927 ice_aqc_opc_add_sched_elems = 0x0401,
1928 ice_aqc_opc_cfg_sched_elems = 0x0403,
1929 ice_aqc_opc_get_sched_elems = 0x0404,
1930 ice_aqc_opc_move_sched_elems = 0x0408,
1931 ice_aqc_opc_suspend_sched_elems = 0x0409,
1932 ice_aqc_opc_resume_sched_elems = 0x040A,
1933 ice_aqc_opc_suspend_sched_traffic = 0x040B,
1934 ice_aqc_opc_resume_sched_traffic = 0x040C,
1935 ice_aqc_opc_delete_sched_elems = 0x040F,
1936 ice_aqc_opc_add_rl_profiles = 0x0410,
1937 ice_aqc_opc_query_rl_profiles = 0x0411,
1938 ice_aqc_opc_query_sched_res = 0x0412,
1939 ice_aqc_opc_query_node_to_root = 0x0413,
1940 ice_aqc_opc_cfg_l2_node_cgd = 0x0414,
1941 ice_aqc_opc_remove_rl_profiles = 0x0415,
1944 ice_aqc_opc_get_phy_caps = 0x0600,
1945 ice_aqc_opc_set_phy_cfg = 0x0601,
1946 ice_aqc_opc_set_mac_cfg = 0x0603,
1947 ice_aqc_opc_restart_an = 0x0605,
1948 ice_aqc_opc_get_link_status = 0x0607,
1949 ice_aqc_opc_set_event_mask = 0x0613,
1950 ice_aqc_opc_set_mac_lb = 0x0620,
1951 ice_aqc_opc_set_port_id_led = 0x06E9,
1952 ice_aqc_opc_get_port_options = 0x06EA,
1953 ice_aqc_opc_set_port_option = 0x06EB,
1954 ice_aqc_opc_set_gpio = 0x06EC,
1955 ice_aqc_opc_get_gpio = 0x06ED,
1958 ice_aqc_opc_nvm_read = 0x0701,
1959 ice_aqc_opc_nvm_erase = 0x0702,
1960 ice_aqc_opc_nvm_update = 0x0703,
1961 ice_aqc_opc_nvm_cfg_read = 0x0704,
1962 ice_aqc_opc_nvm_cfg_write = 0x0705,
1963 ice_aqc_opc_nvm_checksum = 0x0706,
1967 ice_aqc_opc_set_rss_key = 0x0B02,
1968 ice_aqc_opc_set_rss_lut = 0x0B03,
1969 ice_aqc_opc_get_rss_key = 0x0B04,
1970 ice_aqc_opc_get_rss_lut = 0x0B05,
1972 /* Tx queue handling commands/events */
1973 ice_aqc_opc_add_txqs = 0x0C30,
1974 ice_aqc_opc_dis_txqs = 0x0C31,
1975 ice_aqc_opc_txqs_cleanup = 0x0C31,
1976 ice_aqc_opc_move_recfg_txqs = 0x0C32,
1978 /* package commands */
1979 ice_aqc_opc_download_pkg = 0x0C40,
1980 ice_aqc_opc_upload_section = 0x0C41,
1981 ice_aqc_opc_update_pkg = 0x0C42,
1982 ice_aqc_opc_get_pkg_info_list = 0x0C43,
1986 /* Standalone Commands/Events */
1987 ice_aqc_opc_event_lan_overflow = 0x1001,
1989 /* debug commands */
1990 ice_aqc_opc_fw_logging = 0xFF09,
1991 ice_aqc_opc_fw_logging_info = 0xFF10,
1992 ice_aqc_opc_get_clear_fw_log = 0xFF11
1995 #endif /* _ICE_ADMINQ_CMD_H_ */