1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2001-2019
5 #include "ice_common.h"
7 #include "ice_adminq_cmd.h"
10 #include "ice_switch.h"
12 #define ICE_PF_RESET_WAIT_COUNT 200
16 * ice_set_mac_type - Sets MAC type
17 * @hw: pointer to the HW structure
19 * This function sets the MAC type of the adapter based on the
20 * vendor ID and device ID stored in the HW structure.
22 static enum ice_status ice_set_mac_type(struct ice_hw *hw)
24 enum ice_status status = ICE_SUCCESS;
26 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
28 if (hw->vendor_id == ICE_INTEL_VENDOR_ID) {
29 switch (hw->device_id) {
31 hw->mac_type = ICE_MAC_GENERIC;
35 status = ICE_ERR_DEVICE_NOT_SUPPORTED;
38 ice_debug(hw, ICE_DBG_INIT, "found mac_type: %d, status: %d\n",
39 hw->mac_type, status);
46 * ice_clear_pf_cfg - Clear PF configuration
47 * @hw: pointer to the hardware structure
49 * Clears any existing PF configuration (VSIs, VSI lists, switch rules, port
50 * configuration, flow director filters, etc.).
52 enum ice_status ice_clear_pf_cfg(struct ice_hw *hw)
54 struct ice_aq_desc desc;
56 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pf_cfg);
58 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
62 * ice_aq_manage_mac_read - manage MAC address read command
63 * @hw: pointer to the HW struct
64 * @buf: a virtual buffer to hold the manage MAC read response
65 * @buf_size: Size of the virtual buffer
66 * @cd: pointer to command details structure or NULL
68 * This function is used to return per PF station MAC address (0x0107).
69 * NOTE: Upon successful completion of this command, MAC address information
70 * is returned in user specified buffer. Please interpret user specified
71 * buffer as "manage_mac_read" response.
72 * Response such as various MAC addresses are stored in HW struct (port.mac)
73 * ice_aq_discover_caps is expected to be called before this function is called.
75 static enum ice_status
76 ice_aq_manage_mac_read(struct ice_hw *hw, void *buf, u16 buf_size,
79 struct ice_aqc_manage_mac_read_resp *resp;
80 struct ice_aqc_manage_mac_read *cmd;
81 struct ice_aq_desc desc;
82 enum ice_status status;
86 cmd = &desc.params.mac_read;
88 if (buf_size < sizeof(*resp))
89 return ICE_ERR_BUF_TOO_SHORT;
91 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_read);
93 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);
97 resp = (struct ice_aqc_manage_mac_read_resp *)buf;
98 flags = LE16_TO_CPU(cmd->flags) & ICE_AQC_MAN_MAC_READ_M;
100 if (!(flags & ICE_AQC_MAN_MAC_LAN_ADDR_VALID)) {
101 ice_debug(hw, ICE_DBG_LAN, "got invalid MAC address\n");
105 /* A single port can report up to two (LAN and WoL) addresses */
106 for (i = 0; i < cmd->num_addr; i++)
107 if (resp[i].addr_type == ICE_AQC_MAN_MAC_ADDR_TYPE_LAN) {
108 ice_memcpy(hw->port_info->mac.lan_addr,
109 resp[i].mac_addr, ETH_ALEN,
111 ice_memcpy(hw->port_info->mac.perm_addr,
113 ETH_ALEN, ICE_DMA_TO_NONDMA);
121 * ice_aq_get_phy_caps - returns PHY capabilities
122 * @pi: port information structure
123 * @qual_mods: report qualified modules
124 * @report_mode: report mode capabilities
125 * @pcaps: structure for PHY capabilities to be filled
126 * @cd: pointer to command details structure or NULL
128 * Returns the various PHY capabilities supported on the Port (0x0600)
131 ice_aq_get_phy_caps(struct ice_port_info *pi, bool qual_mods, u8 report_mode,
132 struct ice_aqc_get_phy_caps_data *pcaps,
133 struct ice_sq_cd *cd)
135 struct ice_aqc_get_phy_caps *cmd;
136 u16 pcaps_size = sizeof(*pcaps);
137 struct ice_aq_desc desc;
138 enum ice_status status;
140 cmd = &desc.params.get_phy;
142 if (!pcaps || (report_mode & ~ICE_AQC_REPORT_MODE_M) || !pi)
143 return ICE_ERR_PARAM;
145 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_phy_caps);
148 cmd->param0 |= CPU_TO_LE16(ICE_AQC_GET_PHY_RQM);
150 cmd->param0 |= CPU_TO_LE16(report_mode);
151 status = ice_aq_send_cmd(pi->hw, &desc, pcaps, pcaps_size, cd);
153 if (status == ICE_SUCCESS && report_mode == ICE_AQC_REPORT_TOPO_CAP) {
154 pi->phy.phy_type_low = LE64_TO_CPU(pcaps->phy_type_low);
155 pi->phy.phy_type_high = LE64_TO_CPU(pcaps->phy_type_high);
162 * ice_aq_get_link_topo_handle - get link topology node return status
163 * @pi: port information structure
164 * @node_type: requested node type
165 * @cd: pointer to command details structure or NULL
167 * Get link topology node return status for specified node type (0x06E0)
169 * Node type cage can be used to determine if cage is present. If AQC
170 * returns error (ENOENT), then no cage present. If no cage present, then
171 * connection type is backplane or BASE-T.
173 static enum ice_status
174 ice_aq_get_link_topo_handle(struct ice_port_info *pi, u8 node_type,
175 struct ice_sq_cd *cd)
177 struct ice_aqc_get_link_topo *cmd;
178 struct ice_aq_desc desc;
180 cmd = &desc.params.get_link_topo;
183 return ICE_ERR_PARAM;
185 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_topo);
187 cmd->addr.node_type_ctx = (ICE_AQC_LINK_TOPO_NODE_CTX_PORT <<
188 ICE_AQC_LINK_TOPO_NODE_CTX_S);
191 cmd->addr.node_type_ctx |= (ICE_AQC_LINK_TOPO_NODE_TYPE_M & node_type);
193 return ice_aq_send_cmd(pi->hw, &desc, NULL, 0, cd);
197 * ice_is_media_cage_present
198 * @pi: port information structure
200 * Returns true if media cage is present, else false. If no cage, then
201 * media type is backplane or BASE-T.
203 static bool ice_is_media_cage_present(struct ice_port_info *pi)
205 /* Node type cage can be used to determine if cage is present. If AQC
206 * returns error (ENOENT), then no cage present. If no cage present then
207 * connection type is backplane or BASE-T.
209 return !ice_aq_get_link_topo_handle(pi,
210 ICE_AQC_LINK_TOPO_NODE_TYPE_CAGE,
215 * ice_get_media_type - Gets media type
216 * @pi: port information structure
218 static enum ice_media_type ice_get_media_type(struct ice_port_info *pi)
220 struct ice_link_status *hw_link_info;
223 return ICE_MEDIA_UNKNOWN;
225 hw_link_info = &pi->phy.link_info;
226 if (hw_link_info->phy_type_low && hw_link_info->phy_type_high)
227 /* If more than one media type is selected, report unknown */
228 return ICE_MEDIA_UNKNOWN;
230 if (hw_link_info->phy_type_low) {
231 switch (hw_link_info->phy_type_low) {
232 case ICE_PHY_TYPE_LOW_1000BASE_SX:
233 case ICE_PHY_TYPE_LOW_1000BASE_LX:
234 case ICE_PHY_TYPE_LOW_10GBASE_SR:
235 case ICE_PHY_TYPE_LOW_10GBASE_LR:
236 case ICE_PHY_TYPE_LOW_10G_SFI_C2C:
237 case ICE_PHY_TYPE_LOW_25GBASE_SR:
238 case ICE_PHY_TYPE_LOW_25GBASE_LR:
239 case ICE_PHY_TYPE_LOW_40GBASE_SR4:
240 case ICE_PHY_TYPE_LOW_40GBASE_LR4:
241 case ICE_PHY_TYPE_LOW_50GBASE_SR2:
242 case ICE_PHY_TYPE_LOW_50GBASE_LR2:
243 case ICE_PHY_TYPE_LOW_50GBASE_SR:
244 case ICE_PHY_TYPE_LOW_50GBASE_FR:
245 case ICE_PHY_TYPE_LOW_50GBASE_LR:
246 case ICE_PHY_TYPE_LOW_100GBASE_SR4:
247 case ICE_PHY_TYPE_LOW_100GBASE_LR4:
248 case ICE_PHY_TYPE_LOW_100GBASE_SR2:
249 case ICE_PHY_TYPE_LOW_100GBASE_DR:
250 return ICE_MEDIA_FIBER;
251 case ICE_PHY_TYPE_LOW_100BASE_TX:
252 case ICE_PHY_TYPE_LOW_1000BASE_T:
253 case ICE_PHY_TYPE_LOW_2500BASE_T:
254 case ICE_PHY_TYPE_LOW_5GBASE_T:
255 case ICE_PHY_TYPE_LOW_10GBASE_T:
256 case ICE_PHY_TYPE_LOW_25GBASE_T:
257 return ICE_MEDIA_BASET;
258 case ICE_PHY_TYPE_LOW_10G_SFI_DA:
259 case ICE_PHY_TYPE_LOW_25GBASE_CR:
260 case ICE_PHY_TYPE_LOW_25GBASE_CR_S:
261 case ICE_PHY_TYPE_LOW_25GBASE_CR1:
262 case ICE_PHY_TYPE_LOW_40GBASE_CR4:
263 case ICE_PHY_TYPE_LOW_50GBASE_CR2:
264 case ICE_PHY_TYPE_LOW_50GBASE_CP:
265 case ICE_PHY_TYPE_LOW_100GBASE_CR4:
266 case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4:
267 case ICE_PHY_TYPE_LOW_100GBASE_CP2:
269 case ICE_PHY_TYPE_LOW_25G_AUI_C2C:
270 case ICE_PHY_TYPE_LOW_40G_XLAUI:
271 case ICE_PHY_TYPE_LOW_50G_LAUI2:
272 case ICE_PHY_TYPE_LOW_50G_AUI2:
273 case ICE_PHY_TYPE_LOW_50G_AUI1:
274 case ICE_PHY_TYPE_LOW_100G_AUI4:
275 case ICE_PHY_TYPE_LOW_100G_CAUI4:
276 if (ice_is_media_cage_present(pi))
279 case ICE_PHY_TYPE_LOW_1000BASE_KX:
280 case ICE_PHY_TYPE_LOW_2500BASE_KX:
281 case ICE_PHY_TYPE_LOW_2500BASE_X:
282 case ICE_PHY_TYPE_LOW_5GBASE_KR:
283 case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1:
284 case ICE_PHY_TYPE_LOW_25GBASE_KR:
285 case ICE_PHY_TYPE_LOW_25GBASE_KR1:
286 case ICE_PHY_TYPE_LOW_25GBASE_KR_S:
287 case ICE_PHY_TYPE_LOW_40GBASE_KR4:
288 case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4:
289 case ICE_PHY_TYPE_LOW_50GBASE_KR2:
290 case ICE_PHY_TYPE_LOW_100GBASE_KR4:
291 case ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4:
292 return ICE_MEDIA_BACKPLANE;
295 switch (hw_link_info->phy_type_high) {
296 case ICE_PHY_TYPE_HIGH_100G_AUI2:
297 if (ice_is_media_cage_present(pi))
300 case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4:
301 return ICE_MEDIA_BACKPLANE;
304 return ICE_MEDIA_UNKNOWN;
308 * ice_aq_get_link_info
309 * @pi: port information structure
310 * @ena_lse: enable/disable LinkStatusEvent reporting
311 * @link: pointer to link status structure - optional
312 * @cd: pointer to command details structure or NULL
314 * Get Link Status (0x607). Returns the link status of the adapter.
317 ice_aq_get_link_info(struct ice_port_info *pi, bool ena_lse,
318 struct ice_link_status *link, struct ice_sq_cd *cd)
320 struct ice_aqc_get_link_status_data link_data = { 0 };
321 struct ice_aqc_get_link_status *resp;
322 struct ice_link_status *li_old, *li;
323 enum ice_media_type *hw_media_type;
324 struct ice_fc_info *hw_fc_info;
325 bool tx_pause, rx_pause;
326 struct ice_aq_desc desc;
327 enum ice_status status;
332 return ICE_ERR_PARAM;
334 li_old = &pi->phy.link_info_old;
335 hw_media_type = &pi->phy.media_type;
336 li = &pi->phy.link_info;
337 hw_fc_info = &pi->fc;
339 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_status);
340 cmd_flags = (ena_lse) ? ICE_AQ_LSE_ENA : ICE_AQ_LSE_DIS;
341 resp = &desc.params.get_link_status;
342 resp->cmd_flags = CPU_TO_LE16(cmd_flags);
343 resp->lport_num = pi->lport;
345 status = ice_aq_send_cmd(hw, &desc, &link_data, sizeof(link_data), cd);
347 if (status != ICE_SUCCESS)
350 /* save off old link status information */
353 /* update current link status information */
354 li->link_speed = LE16_TO_CPU(link_data.link_speed);
355 li->phy_type_low = LE64_TO_CPU(link_data.phy_type_low);
356 li->phy_type_high = LE64_TO_CPU(link_data.phy_type_high);
357 *hw_media_type = ice_get_media_type(pi);
358 li->link_info = link_data.link_info;
359 li->an_info = link_data.an_info;
360 li->ext_info = link_data.ext_info;
361 li->max_frame_size = LE16_TO_CPU(link_data.max_frame_size);
362 li->fec_info = link_data.cfg & ICE_AQ_FEC_MASK;
363 li->topo_media_conflict = link_data.topo_media_conflict;
364 li->pacing = link_data.cfg & (ICE_AQ_CFG_PACING_M |
365 ICE_AQ_CFG_PACING_TYPE_M);
368 tx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_TX);
369 rx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_RX);
370 if (tx_pause && rx_pause)
371 hw_fc_info->current_mode = ICE_FC_FULL;
373 hw_fc_info->current_mode = ICE_FC_TX_PAUSE;
375 hw_fc_info->current_mode = ICE_FC_RX_PAUSE;
377 hw_fc_info->current_mode = ICE_FC_NONE;
379 li->lse_ena = !!(resp->cmd_flags & CPU_TO_LE16(ICE_AQ_LSE_IS_ENABLED));
381 ice_debug(hw, ICE_DBG_LINK, "link_speed = 0x%x\n", li->link_speed);
382 ice_debug(hw, ICE_DBG_LINK, "phy_type_low = 0x%llx\n",
383 (unsigned long long)li->phy_type_low);
384 ice_debug(hw, ICE_DBG_LINK, "phy_type_high = 0x%llx\n",
385 (unsigned long long)li->phy_type_high);
386 ice_debug(hw, ICE_DBG_LINK, "media_type = 0x%x\n", *hw_media_type);
387 ice_debug(hw, ICE_DBG_LINK, "link_info = 0x%x\n", li->link_info);
388 ice_debug(hw, ICE_DBG_LINK, "an_info = 0x%x\n", li->an_info);
389 ice_debug(hw, ICE_DBG_LINK, "ext_info = 0x%x\n", li->ext_info);
390 ice_debug(hw, ICE_DBG_LINK, "lse_ena = 0x%x\n", li->lse_ena);
391 ice_debug(hw, ICE_DBG_LINK, "max_frame = 0x%x\n", li->max_frame_size);
392 ice_debug(hw, ICE_DBG_LINK, "pacing = 0x%x\n", li->pacing);
394 /* save link status information */
398 /* flag cleared so calling functions don't call AQ again */
399 pi->phy.get_link_info = false;
406 * @hw: pointer to the HW struct
407 * @max_frame_size: Maximum Frame Size to be supported
408 * @cd: pointer to command details structure or NULL
410 * Set MAC configuration (0x0603)
413 ice_aq_set_mac_cfg(struct ice_hw *hw, u16 max_frame_size, struct ice_sq_cd *cd)
415 u16 fc_threshold_val, tx_timer_val;
416 struct ice_aqc_set_mac_cfg *cmd;
417 struct ice_aq_desc desc;
420 cmd = &desc.params.set_mac_cfg;
422 if (max_frame_size == 0)
423 return ICE_ERR_PARAM;
425 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_mac_cfg);
427 cmd->max_frame_size = CPU_TO_LE16(max_frame_size);
429 /* We read back the transmit timer and fc threshold value of
430 * LFC. Thus, we will use index =
431 * PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX.
433 * Also, because we are opearating on transmit timer and fc
434 * threshold of LFC, we don't turn on any bit in tx_tmr_priority
436 #define IDX_OF_LFC PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX
438 /* Retrieve the transmit timer */
440 PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(IDX_OF_LFC));
441 tx_timer_val = reg_val &
442 PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_HSEC_CTL_TX_PAUSE_QUANTA_M;
443 cmd->tx_tmr_value = CPU_TO_LE16(tx_timer_val);
445 /* Retrieve the fc threshold */
447 PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(IDX_OF_LFC));
448 fc_threshold_val = reg_val & MAKEMASK(0xFFFF, 0);
449 cmd->fc_refresh_threshold = CPU_TO_LE16(fc_threshold_val);
451 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
455 * ice_init_fltr_mgmt_struct - initializes filter management list and locks
456 * @hw: pointer to the HW struct
458 static enum ice_status ice_init_fltr_mgmt_struct(struct ice_hw *hw)
460 struct ice_switch_info *sw;
462 hw->switch_info = (struct ice_switch_info *)
463 ice_malloc(hw, sizeof(*hw->switch_info));
464 sw = hw->switch_info;
467 return ICE_ERR_NO_MEMORY;
469 INIT_LIST_HEAD(&sw->vsi_list_map_head);
471 return ice_init_def_sw_recp(hw);
475 * ice_cleanup_fltr_mgmt_struct - cleanup filter management list and locks
476 * @hw: pointer to the HW struct
478 static void ice_cleanup_fltr_mgmt_struct(struct ice_hw *hw)
480 struct ice_switch_info *sw = hw->switch_info;
481 struct ice_vsi_list_map_info *v_pos_map;
482 struct ice_vsi_list_map_info *v_tmp_map;
483 struct ice_sw_recipe *recps;
486 LIST_FOR_EACH_ENTRY_SAFE(v_pos_map, v_tmp_map, &sw->vsi_list_map_head,
487 ice_vsi_list_map_info, list_entry) {
488 LIST_DEL(&v_pos_map->list_entry);
489 ice_free(hw, v_pos_map);
491 recps = hw->switch_info->recp_list;
492 for (i = 0; i < ICE_MAX_NUM_RECIPES; i++) {
493 struct ice_recp_grp_entry *rg_entry, *tmprg_entry;
495 recps[i].root_rid = i;
496 LIST_FOR_EACH_ENTRY_SAFE(rg_entry, tmprg_entry,
497 &recps[i].rg_list, ice_recp_grp_entry,
499 LIST_DEL(&rg_entry->l_entry);
500 ice_free(hw, rg_entry);
503 if (recps[i].adv_rule) {
504 struct ice_adv_fltr_mgmt_list_entry *tmp_entry;
505 struct ice_adv_fltr_mgmt_list_entry *lst_itr;
507 ice_destroy_lock(&recps[i].filt_rule_lock);
508 LIST_FOR_EACH_ENTRY_SAFE(lst_itr, tmp_entry,
509 &recps[i].filt_rules,
510 ice_adv_fltr_mgmt_list_entry,
512 LIST_DEL(&lst_itr->list_entry);
513 ice_free(hw, lst_itr->lkups);
514 ice_free(hw, lst_itr);
517 struct ice_fltr_mgmt_list_entry *lst_itr, *tmp_entry;
519 ice_destroy_lock(&recps[i].filt_rule_lock);
520 LIST_FOR_EACH_ENTRY_SAFE(lst_itr, tmp_entry,
521 &recps[i].filt_rules,
522 ice_fltr_mgmt_list_entry,
524 LIST_DEL(&lst_itr->list_entry);
525 ice_free(hw, lst_itr);
528 if (recps[i].root_buf)
529 ice_free(hw, recps[i].root_buf);
531 ice_rm_all_sw_replay_rule_info(hw);
532 ice_free(hw, sw->recp_list);
538 * ice_get_itr_intrl_gran
539 * @hw: pointer to the HW struct
541 * Determines the ITR/INTRL granularities based on the maximum aggregate
542 * bandwidth according to the device's configuration during power-on.
544 static void ice_get_itr_intrl_gran(struct ice_hw *hw)
546 u8 max_agg_bw = (rd32(hw, GL_PWR_MODE_CTL) &
547 GL_PWR_MODE_CTL_CAR_MAX_BW_M) >>
548 GL_PWR_MODE_CTL_CAR_MAX_BW_S;
550 switch (max_agg_bw) {
551 case ICE_MAX_AGG_BW_200G:
552 case ICE_MAX_AGG_BW_100G:
553 case ICE_MAX_AGG_BW_50G:
554 hw->itr_gran = ICE_ITR_GRAN_ABOVE_25;
555 hw->intrl_gran = ICE_INTRL_GRAN_ABOVE_25;
557 case ICE_MAX_AGG_BW_25G:
558 hw->itr_gran = ICE_ITR_GRAN_MAX_25;
559 hw->intrl_gran = ICE_INTRL_GRAN_MAX_25;
565 * ice_get_nvm_version - get cached NVM version data
566 * @hw: pointer to the hardware structure
567 * @oem_ver: 8 bit NVM version
568 * @oem_build: 16 bit NVM build number
569 * @oem_patch: 8 NVM patch number
570 * @ver_hi: high 16 bits of the NVM version
571 * @ver_lo: low 16 bits of the NVM version
574 ice_get_nvm_version(struct ice_hw *hw, u8 *oem_ver, u16 *oem_build,
575 u8 *oem_patch, u8 *ver_hi, u8 *ver_lo)
577 struct ice_nvm_info *nvm = &hw->nvm;
579 *oem_ver = (u8)((nvm->oem_ver & ICE_OEM_VER_MASK) >> ICE_OEM_VER_SHIFT);
580 *oem_patch = (u8)(nvm->oem_ver & ICE_OEM_VER_PATCH_MASK);
581 *oem_build = (u16)((nvm->oem_ver & ICE_OEM_VER_BUILD_MASK) >>
582 ICE_OEM_VER_BUILD_SHIFT);
583 *ver_hi = (nvm->ver & ICE_NVM_VER_HI_MASK) >> ICE_NVM_VER_HI_SHIFT;
584 *ver_lo = (nvm->ver & ICE_NVM_VER_LO_MASK) >> ICE_NVM_VER_LO_SHIFT;
588 * ice_print_rollback_msg - print FW rollback message
589 * @hw: pointer to the hardware structure
591 void ice_print_rollback_msg(struct ice_hw *hw)
593 char nvm_str[ICE_NVM_VER_LEN] = { 0 };
594 u8 oem_ver, oem_patch, ver_hi, ver_lo;
597 ice_get_nvm_version(hw, &oem_ver, &oem_build, &oem_patch, &ver_hi,
599 SNPRINTF(nvm_str, sizeof(nvm_str), "%x.%02x 0x%x %d.%d.%d", ver_hi,
600 ver_lo, hw->nvm.eetrack, oem_ver, oem_build, oem_patch);
603 "Firmware rollback mode detected. Current version is NVM: %s, FW: %d.%d. Device may exhibit limited functionality. Refer to the Intel(R) Ethernet Adapters and Devices User Guide for details on firmware rollback mode",
604 nvm_str, hw->fw_maj_ver, hw->fw_min_ver);
608 * ice_init_hw - main hardware initialization routine
609 * @hw: pointer to the hardware structure
611 enum ice_status ice_init_hw(struct ice_hw *hw)
613 struct ice_aqc_get_phy_caps_data *pcaps;
614 enum ice_status status;
618 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
621 /* Set MAC type based on DeviceID */
622 status = ice_set_mac_type(hw);
626 hw->pf_id = (u8)(rd32(hw, PF_FUNC_RID) &
627 PF_FUNC_RID_FUNCTION_NUMBER_M) >>
628 PF_FUNC_RID_FUNCTION_NUMBER_S;
631 status = ice_reset(hw, ICE_RESET_PFR);
635 ice_get_itr_intrl_gran(hw);
638 status = ice_create_all_ctrlq(hw);
640 goto err_unroll_cqinit;
642 status = ice_init_nvm(hw);
644 goto err_unroll_cqinit;
646 if (ice_get_fw_mode(hw) == ICE_FW_MODE_ROLLBACK)
647 ice_print_rollback_msg(hw);
649 status = ice_clear_pf_cfg(hw);
651 goto err_unroll_cqinit;
653 /* Set bit to enable Flow Director filters */
654 wr32(hw, PFQF_FD_ENA, PFQF_FD_ENA_FD_ENA_M);
655 INIT_LIST_HEAD(&hw->fdir_list_head);
657 ice_clear_pxe_mode(hw);
660 status = ice_get_caps(hw);
662 goto err_unroll_cqinit;
664 hw->port_info = (struct ice_port_info *)
665 ice_malloc(hw, sizeof(*hw->port_info));
666 if (!hw->port_info) {
667 status = ICE_ERR_NO_MEMORY;
668 goto err_unroll_cqinit;
671 /* set the back pointer to HW */
672 hw->port_info->hw = hw;
674 /* Initialize port_info struct with switch configuration data */
675 status = ice_get_initial_sw_cfg(hw);
677 goto err_unroll_alloc;
681 /* Query the allocated resources for Tx scheduler */
682 status = ice_sched_query_res_alloc(hw);
684 ice_debug(hw, ICE_DBG_SCHED,
685 "Failed to get scheduler allocated resources\n");
686 goto err_unroll_alloc;
690 /* Initialize port_info struct with scheduler data */
691 status = ice_sched_init_port(hw->port_info);
693 goto err_unroll_sched;
695 pcaps = (struct ice_aqc_get_phy_caps_data *)
696 ice_malloc(hw, sizeof(*pcaps));
698 status = ICE_ERR_NO_MEMORY;
699 goto err_unroll_sched;
702 /* Initialize port_info struct with PHY capabilities */
703 status = ice_aq_get_phy_caps(hw->port_info, false,
704 ICE_AQC_REPORT_TOPO_CAP, pcaps, NULL);
707 goto err_unroll_sched;
709 /* Initialize port_info struct with link information */
710 status = ice_aq_get_link_info(hw->port_info, false, NULL, NULL);
712 goto err_unroll_sched;
713 /* need a valid SW entry point to build a Tx tree */
714 if (!hw->sw_entry_point_layer) {
715 ice_debug(hw, ICE_DBG_SCHED, "invalid sw entry point\n");
716 status = ICE_ERR_CFG;
717 goto err_unroll_sched;
719 INIT_LIST_HEAD(&hw->agg_list);
720 /* Initialize max burst size */
721 if (!hw->max_burst_size)
722 ice_cfg_rl_burst_size(hw, ICE_SCHED_DFLT_BURST_SIZE);
724 status = ice_init_fltr_mgmt_struct(hw);
726 goto err_unroll_sched;
729 /* Get MAC information */
730 /* A single port can report up to two (LAN and WoL) addresses */
731 mac_buf = ice_calloc(hw, 2,
732 sizeof(struct ice_aqc_manage_mac_read_resp));
733 mac_buf_len = 2 * sizeof(struct ice_aqc_manage_mac_read_resp);
736 status = ICE_ERR_NO_MEMORY;
737 goto err_unroll_fltr_mgmt_struct;
740 status = ice_aq_manage_mac_read(hw, mac_buf, mac_buf_len, NULL);
741 ice_free(hw, mac_buf);
744 goto err_unroll_fltr_mgmt_struct;
745 /* Obtain counter base index which would be used by flow director */
746 status = ice_alloc_fd_res_cntr(hw, &hw->fd_ctr_base);
748 goto err_unroll_fltr_mgmt_struct;
749 status = ice_init_hw_tbls(hw);
751 goto err_unroll_fltr_mgmt_struct;
754 err_unroll_fltr_mgmt_struct:
755 ice_cleanup_fltr_mgmt_struct(hw);
757 ice_sched_cleanup_all(hw);
759 ice_free(hw, hw->port_info);
760 hw->port_info = NULL;
762 ice_destroy_all_ctrlq(hw);
767 * ice_deinit_hw - unroll initialization operations done by ice_init_hw
768 * @hw: pointer to the hardware structure
770 * This should be called only during nominal operation, not as a result of
771 * ice_init_hw() failing since ice_init_hw() will take care of unrolling
772 * applicable initializations if it fails for any reason.
774 void ice_deinit_hw(struct ice_hw *hw)
776 ice_free_fd_res_cntr(hw, hw->fd_ctr_base);
777 ice_cleanup_fltr_mgmt_struct(hw);
779 ice_sched_cleanup_all(hw);
780 ice_sched_clear_agg(hw);
782 ice_free_hw_tbls(hw);
785 ice_free(hw, hw->port_info);
786 hw->port_info = NULL;
789 ice_destroy_all_ctrlq(hw);
791 /* Clear VSI contexts if not already cleared */
792 ice_clear_all_vsi_ctx(hw);
796 * ice_check_reset - Check to see if a global reset is complete
797 * @hw: pointer to the hardware structure
799 enum ice_status ice_check_reset(struct ice_hw *hw)
801 u32 cnt, reg = 0, grst_delay;
803 /* Poll for Device Active state in case a recent CORER, GLOBR,
804 * or EMPR has occurred. The grst delay value is in 100ms units.
805 * Add 1sec for outstanding AQ commands that can take a long time.
807 grst_delay = ((rd32(hw, GLGEN_RSTCTL) & GLGEN_RSTCTL_GRSTDEL_M) >>
808 GLGEN_RSTCTL_GRSTDEL_S) + 10;
810 for (cnt = 0; cnt < grst_delay; cnt++) {
811 ice_msec_delay(100, true);
812 reg = rd32(hw, GLGEN_RSTAT);
813 if (!(reg & GLGEN_RSTAT_DEVSTATE_M))
817 if (cnt == grst_delay) {
818 ice_debug(hw, ICE_DBG_INIT,
819 "Global reset polling failed to complete.\n");
820 return ICE_ERR_RESET_FAILED;
823 #define ICE_RESET_DONE_MASK (GLNVM_ULD_CORER_DONE_M | \
824 GLNVM_ULD_GLOBR_DONE_M)
826 /* Device is Active; check Global Reset processes are done */
827 for (cnt = 0; cnt < ICE_PF_RESET_WAIT_COUNT; cnt++) {
828 reg = rd32(hw, GLNVM_ULD) & ICE_RESET_DONE_MASK;
829 if (reg == ICE_RESET_DONE_MASK) {
830 ice_debug(hw, ICE_DBG_INIT,
831 "Global reset processes done. %d\n", cnt);
834 ice_msec_delay(10, true);
837 if (cnt == ICE_PF_RESET_WAIT_COUNT) {
838 ice_debug(hw, ICE_DBG_INIT,
839 "Wait for Reset Done timed out. GLNVM_ULD = 0x%x\n",
841 return ICE_ERR_RESET_FAILED;
848 * ice_pf_reset - Reset the PF
849 * @hw: pointer to the hardware structure
851 * If a global reset has been triggered, this function checks
852 * for its completion and then issues the PF reset
854 static enum ice_status ice_pf_reset(struct ice_hw *hw)
858 /* If at function entry a global reset was already in progress, i.e.
859 * state is not 'device active' or any of the reset done bits are not
860 * set in GLNVM_ULD, there is no need for a PF Reset; poll until the
861 * global reset is done.
863 if ((rd32(hw, GLGEN_RSTAT) & GLGEN_RSTAT_DEVSTATE_M) ||
864 (rd32(hw, GLNVM_ULD) & ICE_RESET_DONE_MASK) ^ ICE_RESET_DONE_MASK) {
865 /* poll on global reset currently in progress until done */
866 if (ice_check_reset(hw))
867 return ICE_ERR_RESET_FAILED;
873 reg = rd32(hw, PFGEN_CTRL);
875 wr32(hw, PFGEN_CTRL, (reg | PFGEN_CTRL_PFSWR_M));
877 for (cnt = 0; cnt < ICE_PF_RESET_WAIT_COUNT; cnt++) {
878 reg = rd32(hw, PFGEN_CTRL);
879 if (!(reg & PFGEN_CTRL_PFSWR_M))
882 ice_msec_delay(1, true);
885 if (cnt == ICE_PF_RESET_WAIT_COUNT) {
886 ice_debug(hw, ICE_DBG_INIT,
887 "PF reset polling failed to complete.\n");
888 return ICE_ERR_RESET_FAILED;
895 * ice_reset - Perform different types of reset
896 * @hw: pointer to the hardware structure
897 * @req: reset request
899 * This function triggers a reset as specified by the req parameter.
902 * If anything other than a PF reset is triggered, PXE mode is restored.
903 * This has to be cleared using ice_clear_pxe_mode again, once the AQ
904 * interface has been restored in the rebuild flow.
906 enum ice_status ice_reset(struct ice_hw *hw, enum ice_reset_req req)
912 return ice_pf_reset(hw);
913 case ICE_RESET_CORER:
914 ice_debug(hw, ICE_DBG_INIT, "CoreR requested\n");
915 val = GLGEN_RTRIG_CORER_M;
917 case ICE_RESET_GLOBR:
918 ice_debug(hw, ICE_DBG_INIT, "GlobalR requested\n");
919 val = GLGEN_RTRIG_GLOBR_M;
922 return ICE_ERR_PARAM;
925 val |= rd32(hw, GLGEN_RTRIG);
926 wr32(hw, GLGEN_RTRIG, val);
930 /* wait for the FW to be ready */
931 return ice_check_reset(hw);
935 * ice_get_pfa_module_tlv - Reads sub module TLV from NVM PFA
936 * @hw: pointer to hardware structure
937 * @module_tlv: pointer to module TLV to return
938 * @module_tlv_len: pointer to module TLV length to return
939 * @module_type: module type requested
941 * Finds the requested sub module TLV type from the Preserved Field
942 * Area (PFA) and returns the TLV pointer and length. The caller can
943 * use these to read the variable length TLV value.
946 ice_get_pfa_module_tlv(struct ice_hw *hw, u16 *module_tlv, u16 *module_tlv_len,
949 enum ice_status status;
950 u16 pfa_len, pfa_ptr;
953 status = ice_read_sr_word(hw, ICE_SR_PFA_PTR, &pfa_ptr);
954 if (status != ICE_SUCCESS) {
955 ice_debug(hw, ICE_DBG_INIT, "Preserved Field Array pointer.\n");
958 status = ice_read_sr_word(hw, pfa_ptr, &pfa_len);
959 if (status != ICE_SUCCESS) {
960 ice_debug(hw, ICE_DBG_INIT, "Failed to read PFA length.\n");
963 /* Starting with first TLV after PFA length, iterate through the list
964 * of TLVs to find the requested one.
966 next_tlv = pfa_ptr + 1;
967 while (next_tlv < pfa_ptr + pfa_len) {
968 u16 tlv_sub_module_type;
972 status = ice_read_sr_word(hw, next_tlv, &tlv_sub_module_type);
973 if (status != ICE_SUCCESS) {
974 ice_debug(hw, ICE_DBG_INIT, "Failed to read TLV type.\n");
977 /* Read TLV length */
978 status = ice_read_sr_word(hw, next_tlv + 1, &tlv_len);
979 if (status != ICE_SUCCESS) {
980 ice_debug(hw, ICE_DBG_INIT, "Failed to read TLV length.\n");
983 if (tlv_sub_module_type == module_type) {
985 *module_tlv = next_tlv;
986 *module_tlv_len = tlv_len;
989 return ICE_ERR_INVAL_SIZE;
991 /* Check next TLV, i.e. current TLV pointer + length + 2 words
992 * (for current TLV's type and length)
994 next_tlv = next_tlv + tlv_len + 2;
996 /* Module does not exist */
997 return ICE_ERR_DOES_NOT_EXIST;
1003 * ice_copy_rxq_ctx_to_hw
1004 * @hw: pointer to the hardware structure
1005 * @ice_rxq_ctx: pointer to the rxq context
1006 * @rxq_index: the index of the Rx queue
1008 * Copies rxq context from dense structure to HW register space
1010 static enum ice_status
1011 ice_copy_rxq_ctx_to_hw(struct ice_hw *hw, u8 *ice_rxq_ctx, u32 rxq_index)
1016 return ICE_ERR_BAD_PTR;
1018 if (rxq_index > QRX_CTRL_MAX_INDEX)
1019 return ICE_ERR_PARAM;
1021 /* Copy each dword separately to HW */
1022 for (i = 0; i < ICE_RXQ_CTX_SIZE_DWORDS; i++) {
1023 wr32(hw, QRX_CONTEXT(i, rxq_index),
1024 *((u32 *)(ice_rxq_ctx + (i * sizeof(u32)))));
1026 ice_debug(hw, ICE_DBG_QCTX, "qrxdata[%d]: %08X\n", i,
1027 *((u32 *)(ice_rxq_ctx + (i * sizeof(u32)))));
1033 /* LAN Rx Queue Context */
1034 static const struct ice_ctx_ele ice_rlan_ctx_info[] = {
1035 /* Field Width LSB */
1036 ICE_CTX_STORE(ice_rlan_ctx, head, 13, 0),
1037 ICE_CTX_STORE(ice_rlan_ctx, cpuid, 8, 13),
1038 ICE_CTX_STORE(ice_rlan_ctx, base, 57, 32),
1039 ICE_CTX_STORE(ice_rlan_ctx, qlen, 13, 89),
1040 ICE_CTX_STORE(ice_rlan_ctx, dbuf, 7, 102),
1041 ICE_CTX_STORE(ice_rlan_ctx, hbuf, 5, 109),
1042 ICE_CTX_STORE(ice_rlan_ctx, dtype, 2, 114),
1043 ICE_CTX_STORE(ice_rlan_ctx, dsize, 1, 116),
1044 ICE_CTX_STORE(ice_rlan_ctx, crcstrip, 1, 117),
1045 ICE_CTX_STORE(ice_rlan_ctx, l2tsel, 1, 119),
1046 ICE_CTX_STORE(ice_rlan_ctx, hsplit_0, 4, 120),
1047 ICE_CTX_STORE(ice_rlan_ctx, hsplit_1, 2, 124),
1048 ICE_CTX_STORE(ice_rlan_ctx, showiv, 1, 127),
1049 ICE_CTX_STORE(ice_rlan_ctx, rxmax, 14, 174),
1050 ICE_CTX_STORE(ice_rlan_ctx, tphrdesc_ena, 1, 193),
1051 ICE_CTX_STORE(ice_rlan_ctx, tphwdesc_ena, 1, 194),
1052 ICE_CTX_STORE(ice_rlan_ctx, tphdata_ena, 1, 195),
1053 ICE_CTX_STORE(ice_rlan_ctx, tphhead_ena, 1, 196),
1054 ICE_CTX_STORE(ice_rlan_ctx, lrxqthresh, 3, 198),
1055 ICE_CTX_STORE(ice_rlan_ctx, prefena, 1, 201),
1061 * @hw: pointer to the hardware structure
1062 * @rlan_ctx: pointer to the rxq context
1063 * @rxq_index: the index of the Rx queue
1065 * Converts rxq context from sparse to dense structure and then writes
1066 * it to HW register space and enables the hardware to prefetch descriptors
1067 * instead of only fetching them on demand
1070 ice_write_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx,
1073 u8 ctx_buf[ICE_RXQ_CTX_SZ] = { 0 };
1076 return ICE_ERR_BAD_PTR;
1078 rlan_ctx->prefena = 1;
1080 ice_set_ctx((u8 *)rlan_ctx, ctx_buf, ice_rlan_ctx_info);
1081 return ice_copy_rxq_ctx_to_hw(hw, ctx_buf, rxq_index);
1084 #if !defined(NO_UNUSED_CTX_CODE) || defined(AE_DRIVER)
1087 * @hw: pointer to the hardware structure
1088 * @rxq_index: the index of the Rx queue to clear
1090 * Clears rxq context in HW register space
1092 enum ice_status ice_clear_rxq_ctx(struct ice_hw *hw, u32 rxq_index)
1096 if (rxq_index > QRX_CTRL_MAX_INDEX)
1097 return ICE_ERR_PARAM;
1099 /* Clear each dword register separately */
1100 for (i = 0; i < ICE_RXQ_CTX_SIZE_DWORDS; i++)
1101 wr32(hw, QRX_CONTEXT(i, rxq_index), 0);
1105 #endif /* !NO_UNUSED_CTX_CODE || AE_DRIVER */
1107 /* LAN Tx Queue Context */
1108 const struct ice_ctx_ele ice_tlan_ctx_info[] = {
1109 /* Field Width LSB */
1110 ICE_CTX_STORE(ice_tlan_ctx, base, 57, 0),
1111 ICE_CTX_STORE(ice_tlan_ctx, port_num, 3, 57),
1112 ICE_CTX_STORE(ice_tlan_ctx, cgd_num, 5, 60),
1113 ICE_CTX_STORE(ice_tlan_ctx, pf_num, 3, 65),
1114 ICE_CTX_STORE(ice_tlan_ctx, vmvf_num, 10, 68),
1115 ICE_CTX_STORE(ice_tlan_ctx, vmvf_type, 2, 78),
1116 ICE_CTX_STORE(ice_tlan_ctx, src_vsi, 10, 80),
1117 ICE_CTX_STORE(ice_tlan_ctx, tsyn_ena, 1, 90),
1118 ICE_CTX_STORE(ice_tlan_ctx, internal_usage_flag, 1, 91),
1119 ICE_CTX_STORE(ice_tlan_ctx, alt_vlan, 1, 92),
1120 ICE_CTX_STORE(ice_tlan_ctx, cpuid, 8, 93),
1121 ICE_CTX_STORE(ice_tlan_ctx, wb_mode, 1, 101),
1122 ICE_CTX_STORE(ice_tlan_ctx, tphrd_desc, 1, 102),
1123 ICE_CTX_STORE(ice_tlan_ctx, tphrd, 1, 103),
1124 ICE_CTX_STORE(ice_tlan_ctx, tphwr_desc, 1, 104),
1125 ICE_CTX_STORE(ice_tlan_ctx, cmpq_id, 9, 105),
1126 ICE_CTX_STORE(ice_tlan_ctx, qnum_in_func, 14, 114),
1127 ICE_CTX_STORE(ice_tlan_ctx, itr_notification_mode, 1, 128),
1128 ICE_CTX_STORE(ice_tlan_ctx, adjust_prof_id, 6, 129),
1129 ICE_CTX_STORE(ice_tlan_ctx, qlen, 13, 135),
1130 ICE_CTX_STORE(ice_tlan_ctx, quanta_prof_idx, 4, 148),
1131 ICE_CTX_STORE(ice_tlan_ctx, tso_ena, 1, 152),
1132 ICE_CTX_STORE(ice_tlan_ctx, tso_qnum, 11, 153),
1133 ICE_CTX_STORE(ice_tlan_ctx, legacy_int, 1, 164),
1134 ICE_CTX_STORE(ice_tlan_ctx, drop_ena, 1, 165),
1135 ICE_CTX_STORE(ice_tlan_ctx, cache_prof_idx, 2, 166),
1136 ICE_CTX_STORE(ice_tlan_ctx, pkt_shaper_prof_idx, 3, 168),
1137 ICE_CTX_STORE(ice_tlan_ctx, int_q_state, 122, 171),
1141 #if !defined(NO_UNUSED_CTX_CODE) || defined(AE_DRIVER)
1143 * ice_copy_tx_cmpltnq_ctx_to_hw
1144 * @hw: pointer to the hardware structure
1145 * @ice_tx_cmpltnq_ctx: pointer to the Tx completion queue context
1146 * @tx_cmpltnq_index: the index of the completion queue
1148 * Copies Tx completion queue context from dense structure to HW register space
1150 static enum ice_status
1151 ice_copy_tx_cmpltnq_ctx_to_hw(struct ice_hw *hw, u8 *ice_tx_cmpltnq_ctx,
1152 u32 tx_cmpltnq_index)
1156 if (!ice_tx_cmpltnq_ctx)
1157 return ICE_ERR_BAD_PTR;
1159 if (tx_cmpltnq_index > GLTCLAN_CQ_CNTX0_MAX_INDEX)
1160 return ICE_ERR_PARAM;
1162 /* Copy each dword separately to HW */
1163 for (i = 0; i < ICE_TX_CMPLTNQ_CTX_SIZE_DWORDS; i++) {
1164 wr32(hw, GLTCLAN_CQ_CNTX(i, tx_cmpltnq_index),
1165 *((u32 *)(ice_tx_cmpltnq_ctx + (i * sizeof(u32)))));
1167 ice_debug(hw, ICE_DBG_QCTX, "cmpltnqdata[%d]: %08X\n", i,
1168 *((u32 *)(ice_tx_cmpltnq_ctx + (i * sizeof(u32)))));
1174 /* LAN Tx Completion Queue Context */
1175 static const struct ice_ctx_ele ice_tx_cmpltnq_ctx_info[] = {
1176 /* Field Width LSB */
1177 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, base, 57, 0),
1178 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, q_len, 18, 64),
1179 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, generation, 1, 96),
1180 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, wrt_ptr, 22, 97),
1181 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, pf_num, 3, 128),
1182 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, vmvf_num, 10, 131),
1183 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, vmvf_type, 2, 141),
1184 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, tph_desc_wr, 1, 160),
1185 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, cpuid, 8, 161),
1186 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, cmpltn_cache, 512, 192),
1191 * ice_write_tx_cmpltnq_ctx
1192 * @hw: pointer to the hardware structure
1193 * @tx_cmpltnq_ctx: pointer to the completion queue context
1194 * @tx_cmpltnq_index: the index of the completion queue
1196 * Converts completion queue context from sparse to dense structure and then
1197 * writes it to HW register space
1200 ice_write_tx_cmpltnq_ctx(struct ice_hw *hw,
1201 struct ice_tx_cmpltnq_ctx *tx_cmpltnq_ctx,
1202 u32 tx_cmpltnq_index)
1204 u8 ctx_buf[ICE_TX_CMPLTNQ_CTX_SIZE_DWORDS * sizeof(u32)] = { 0 };
1206 ice_set_ctx((u8 *)tx_cmpltnq_ctx, ctx_buf, ice_tx_cmpltnq_ctx_info);
1207 return ice_copy_tx_cmpltnq_ctx_to_hw(hw, ctx_buf, tx_cmpltnq_index);
1211 * ice_clear_tx_cmpltnq_ctx
1212 * @hw: pointer to the hardware structure
1213 * @tx_cmpltnq_index: the index of the completion queue to clear
1215 * Clears Tx completion queue context in HW register space
1218 ice_clear_tx_cmpltnq_ctx(struct ice_hw *hw, u32 tx_cmpltnq_index)
1222 if (tx_cmpltnq_index > GLTCLAN_CQ_CNTX0_MAX_INDEX)
1223 return ICE_ERR_PARAM;
1225 /* Clear each dword register separately */
1226 for (i = 0; i < ICE_TX_CMPLTNQ_CTX_SIZE_DWORDS; i++)
1227 wr32(hw, GLTCLAN_CQ_CNTX(i, tx_cmpltnq_index), 0);
1233 * ice_copy_tx_drbell_q_ctx_to_hw
1234 * @hw: pointer to the hardware structure
1235 * @ice_tx_drbell_q_ctx: pointer to the doorbell queue context
1236 * @tx_drbell_q_index: the index of the doorbell queue
1238 * Copies doorbell queue context from dense structure to HW register space
1240 static enum ice_status
1241 ice_copy_tx_drbell_q_ctx_to_hw(struct ice_hw *hw, u8 *ice_tx_drbell_q_ctx,
1242 u32 tx_drbell_q_index)
1246 if (!ice_tx_drbell_q_ctx)
1247 return ICE_ERR_BAD_PTR;
1249 if (tx_drbell_q_index > QTX_COMM_DBLQ_DBELL_MAX_INDEX)
1250 return ICE_ERR_PARAM;
1252 /* Copy each dword separately to HW */
1253 for (i = 0; i < ICE_TX_DRBELL_Q_CTX_SIZE_DWORDS; i++) {
1254 wr32(hw, QTX_COMM_DBLQ_CNTX(i, tx_drbell_q_index),
1255 *((u32 *)(ice_tx_drbell_q_ctx + (i * sizeof(u32)))));
1257 ice_debug(hw, ICE_DBG_QCTX, "tx_drbell_qdata[%d]: %08X\n", i,
1258 *((u32 *)(ice_tx_drbell_q_ctx + (i * sizeof(u32)))));
1264 /* LAN Tx Doorbell Queue Context info */
1265 static const struct ice_ctx_ele ice_tx_drbell_q_ctx_info[] = {
1266 /* Field Width LSB */
1267 ICE_CTX_STORE(ice_tx_drbell_q_ctx, base, 57, 0),
1268 ICE_CTX_STORE(ice_tx_drbell_q_ctx, ring_len, 13, 64),
1269 ICE_CTX_STORE(ice_tx_drbell_q_ctx, pf_num, 3, 80),
1270 ICE_CTX_STORE(ice_tx_drbell_q_ctx, vf_num, 8, 84),
1271 ICE_CTX_STORE(ice_tx_drbell_q_ctx, vmvf_type, 2, 94),
1272 ICE_CTX_STORE(ice_tx_drbell_q_ctx, cpuid, 8, 96),
1273 ICE_CTX_STORE(ice_tx_drbell_q_ctx, tph_desc_rd, 1, 104),
1274 ICE_CTX_STORE(ice_tx_drbell_q_ctx, tph_desc_wr, 1, 108),
1275 ICE_CTX_STORE(ice_tx_drbell_q_ctx, db_q_en, 1, 112),
1276 ICE_CTX_STORE(ice_tx_drbell_q_ctx, rd_head, 13, 128),
1277 ICE_CTX_STORE(ice_tx_drbell_q_ctx, rd_tail, 13, 144),
1282 * ice_write_tx_drbell_q_ctx
1283 * @hw: pointer to the hardware structure
1284 * @tx_drbell_q_ctx: pointer to the doorbell queue context
1285 * @tx_drbell_q_index: the index of the doorbell queue
1287 * Converts doorbell queue context from sparse to dense structure and then
1288 * writes it to HW register space
1291 ice_write_tx_drbell_q_ctx(struct ice_hw *hw,
1292 struct ice_tx_drbell_q_ctx *tx_drbell_q_ctx,
1293 u32 tx_drbell_q_index)
1295 u8 ctx_buf[ICE_TX_DRBELL_Q_CTX_SIZE_DWORDS * sizeof(u32)] = { 0 };
1297 ice_set_ctx((u8 *)tx_drbell_q_ctx, ctx_buf, ice_tx_drbell_q_ctx_info);
1298 return ice_copy_tx_drbell_q_ctx_to_hw(hw, ctx_buf, tx_drbell_q_index);
1302 * ice_clear_tx_drbell_q_ctx
1303 * @hw: pointer to the hardware structure
1304 * @tx_drbell_q_index: the index of the doorbell queue to clear
1306 * Clears doorbell queue context in HW register space
1309 ice_clear_tx_drbell_q_ctx(struct ice_hw *hw, u32 tx_drbell_q_index)
1313 if (tx_drbell_q_index > QTX_COMM_DBLQ_DBELL_MAX_INDEX)
1314 return ICE_ERR_PARAM;
1316 /* Clear each dword register separately */
1317 for (i = 0; i < ICE_TX_DRBELL_Q_CTX_SIZE_DWORDS; i++)
1318 wr32(hw, QTX_COMM_DBLQ_CNTX(i, tx_drbell_q_index), 0);
1322 #endif /* !NO_UNUSED_CTX_CODE || AE_DRIVER */
1325 /* FW Admin Queue command wrappers */
1328 * ice_aq_send_cmd - send FW Admin Queue command to FW Admin Queue
1329 * @hw: pointer to the HW struct
1330 * @desc: descriptor describing the command
1331 * @buf: buffer to use for indirect commands (NULL for direct commands)
1332 * @buf_size: size of buffer for indirect commands (0 for direct commands)
1333 * @cd: pointer to command details structure
1335 * Helper function to send FW Admin Queue commands to the FW Admin Queue.
1338 ice_aq_send_cmd(struct ice_hw *hw, struct ice_aq_desc *desc, void *buf,
1339 u16 buf_size, struct ice_sq_cd *cd)
1341 return ice_sq_send_cmd(hw, &hw->adminq, desc, buf, buf_size, cd);
1346 * @hw: pointer to the HW struct
1347 * @cd: pointer to command details structure or NULL
1349 * Get the firmware version (0x0001) from the admin queue commands
1351 enum ice_status ice_aq_get_fw_ver(struct ice_hw *hw, struct ice_sq_cd *cd)
1353 struct ice_aqc_get_ver *resp;
1354 struct ice_aq_desc desc;
1355 enum ice_status status;
1357 resp = &desc.params.get_ver;
1359 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_ver);
1361 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
1364 hw->fw_branch = resp->fw_branch;
1365 hw->fw_maj_ver = resp->fw_major;
1366 hw->fw_min_ver = resp->fw_minor;
1367 hw->fw_patch = resp->fw_patch;
1368 hw->fw_build = LE32_TO_CPU(resp->fw_build);
1369 hw->api_branch = resp->api_branch;
1370 hw->api_maj_ver = resp->api_major;
1371 hw->api_min_ver = resp->api_minor;
1372 hw->api_patch = resp->api_patch;
1379 * ice_aq_send_driver_ver
1380 * @hw: pointer to the HW struct
1381 * @dv: driver's major, minor version
1382 * @cd: pointer to command details structure or NULL
1384 * Send the driver version (0x0002) to the firmware
1387 ice_aq_send_driver_ver(struct ice_hw *hw, struct ice_driver_ver *dv,
1388 struct ice_sq_cd *cd)
1390 struct ice_aqc_driver_ver *cmd;
1391 struct ice_aq_desc desc;
1394 cmd = &desc.params.driver_ver;
1397 return ICE_ERR_PARAM;
1399 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_driver_ver);
1401 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
1402 cmd->major_ver = dv->major_ver;
1403 cmd->minor_ver = dv->minor_ver;
1404 cmd->build_ver = dv->build_ver;
1405 cmd->subbuild_ver = dv->subbuild_ver;
1408 while (len < sizeof(dv->driver_string) &&
1409 IS_ASCII(dv->driver_string[len]) && dv->driver_string[len])
1412 return ice_aq_send_cmd(hw, &desc, dv->driver_string, len, cd);
1417 * @hw: pointer to the HW struct
1418 * @unloading: is the driver unloading itself
1420 * Tell the Firmware that we're shutting down the AdminQ and whether
1421 * or not the driver is unloading as well (0x0003).
1423 enum ice_status ice_aq_q_shutdown(struct ice_hw *hw, bool unloading)
1425 struct ice_aqc_q_shutdown *cmd;
1426 struct ice_aq_desc desc;
1428 cmd = &desc.params.q_shutdown;
1430 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_q_shutdown);
1433 cmd->driver_unloading = ICE_AQC_DRIVER_UNLOADING;
1435 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
1440 * @hw: pointer to the HW struct
1442 * @access: access type
1443 * @sdp_number: resource number
1444 * @timeout: the maximum time in ms that the driver may hold the resource
1445 * @cd: pointer to command details structure or NULL
1447 * Requests common resource using the admin queue commands (0x0008).
1448 * When attempting to acquire the Global Config Lock, the driver can
1449 * learn of three states:
1450 * 1) ICE_SUCCESS - acquired lock, and can perform download package
1451 * 2) ICE_ERR_AQ_ERROR - did not get lock, driver should fail to load
1452 * 3) ICE_ERR_AQ_NO_WORK - did not get lock, but another driver has
1453 * successfully downloaded the package; the driver does
1454 * not have to download the package and can continue
1457 * Note that if the caller is in an acquire lock, perform action, release lock
1458 * phase of operation, it is possible that the FW may detect a timeout and issue
1459 * a CORER. In this case, the driver will receive a CORER interrupt and will
1460 * have to determine its cause. The calling thread that is handling this flow
1461 * will likely get an error propagated back to it indicating the Download
1462 * Package, Update Package or the Release Resource AQ commands timed out.
1464 static enum ice_status
1465 ice_aq_req_res(struct ice_hw *hw, enum ice_aq_res_ids res,
1466 enum ice_aq_res_access_type access, u8 sdp_number, u32 *timeout,
1467 struct ice_sq_cd *cd)
1469 struct ice_aqc_req_res *cmd_resp;
1470 struct ice_aq_desc desc;
1471 enum ice_status status;
1473 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
1475 cmd_resp = &desc.params.res_owner;
1477 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_req_res);
1479 cmd_resp->res_id = CPU_TO_LE16(res);
1480 cmd_resp->access_type = CPU_TO_LE16(access);
1481 cmd_resp->res_number = CPU_TO_LE32(sdp_number);
1482 cmd_resp->timeout = CPU_TO_LE32(*timeout);
1485 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
1487 /* The completion specifies the maximum time in ms that the driver
1488 * may hold the resource in the Timeout field.
1491 /* Global config lock response utilizes an additional status field.
1493 * If the Global config lock resource is held by some other driver, the
1494 * command completes with ICE_AQ_RES_GLBL_IN_PROG in the status field
1495 * and the timeout field indicates the maximum time the current owner
1496 * of the resource has to free it.
1498 if (res == ICE_GLOBAL_CFG_LOCK_RES_ID) {
1499 if (LE16_TO_CPU(cmd_resp->status) == ICE_AQ_RES_GLBL_SUCCESS) {
1500 *timeout = LE32_TO_CPU(cmd_resp->timeout);
1502 } else if (LE16_TO_CPU(cmd_resp->status) ==
1503 ICE_AQ_RES_GLBL_IN_PROG) {
1504 *timeout = LE32_TO_CPU(cmd_resp->timeout);
1505 return ICE_ERR_AQ_ERROR;
1506 } else if (LE16_TO_CPU(cmd_resp->status) ==
1507 ICE_AQ_RES_GLBL_DONE) {
1508 return ICE_ERR_AQ_NO_WORK;
1511 /* invalid FW response, force a timeout immediately */
1513 return ICE_ERR_AQ_ERROR;
1516 /* If the resource is held by some other driver, the command completes
1517 * with a busy return value and the timeout field indicates the maximum
1518 * time the current owner of the resource has to free it.
1520 if (!status || hw->adminq.sq_last_status == ICE_AQ_RC_EBUSY)
1521 *timeout = LE32_TO_CPU(cmd_resp->timeout);
1527 * ice_aq_release_res
1528 * @hw: pointer to the HW struct
1530 * @sdp_number: resource number
1531 * @cd: pointer to command details structure or NULL
1533 * release common resource using the admin queue commands (0x0009)
1535 static enum ice_status
1536 ice_aq_release_res(struct ice_hw *hw, enum ice_aq_res_ids res, u8 sdp_number,
1537 struct ice_sq_cd *cd)
1539 struct ice_aqc_req_res *cmd;
1540 struct ice_aq_desc desc;
1542 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
1544 cmd = &desc.params.res_owner;
1546 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_release_res);
1548 cmd->res_id = CPU_TO_LE16(res);
1549 cmd->res_number = CPU_TO_LE32(sdp_number);
1551 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
1556 * @hw: pointer to the HW structure
1558 * @access: access type (read or write)
1559 * @timeout: timeout in milliseconds
1561 * This function will attempt to acquire the ownership of a resource.
1564 ice_acquire_res(struct ice_hw *hw, enum ice_aq_res_ids res,
1565 enum ice_aq_res_access_type access, u32 timeout)
1567 #define ICE_RES_POLLING_DELAY_MS 10
1568 u32 delay = ICE_RES_POLLING_DELAY_MS;
1569 u32 time_left = timeout;
1570 enum ice_status status;
1572 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
1574 status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL);
1576 /* A return code of ICE_ERR_AQ_NO_WORK means that another driver has
1577 * previously acquired the resource and performed any necessary updates;
1578 * in this case the caller does not obtain the resource and has no
1579 * further work to do.
1581 if (status == ICE_ERR_AQ_NO_WORK)
1582 goto ice_acquire_res_exit;
1585 ice_debug(hw, ICE_DBG_RES,
1586 "resource %d acquire type %d failed.\n", res, access);
1588 /* If necessary, poll until the current lock owner timeouts */
1589 timeout = time_left;
1590 while (status && timeout && time_left) {
1591 ice_msec_delay(delay, true);
1592 timeout = (timeout > delay) ? timeout - delay : 0;
1593 status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL);
1595 if (status == ICE_ERR_AQ_NO_WORK)
1596 /* lock free, but no work to do */
1603 if (status && status != ICE_ERR_AQ_NO_WORK)
1604 ice_debug(hw, ICE_DBG_RES, "resource acquire timed out.\n");
1606 ice_acquire_res_exit:
1607 if (status == ICE_ERR_AQ_NO_WORK) {
1608 if (access == ICE_RES_WRITE)
1609 ice_debug(hw, ICE_DBG_RES,
1610 "resource indicates no work to do.\n");
1612 ice_debug(hw, ICE_DBG_RES,
1613 "Warning: ICE_ERR_AQ_NO_WORK not expected\n");
1620 * @hw: pointer to the HW structure
1623 * This function will release a resource using the proper Admin Command.
1625 void ice_release_res(struct ice_hw *hw, enum ice_aq_res_ids res)
1627 enum ice_status status;
1628 u32 total_delay = 0;
1630 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
1632 status = ice_aq_release_res(hw, res, 0, NULL);
1634 /* there are some rare cases when trying to release the resource
1635 * results in an admin queue timeout, so handle them correctly
1637 while ((status == ICE_ERR_AQ_TIMEOUT) &&
1638 (total_delay < hw->adminq.sq_cmd_timeout)) {
1639 ice_msec_delay(1, true);
1640 status = ice_aq_release_res(hw, res, 0, NULL);
1646 * ice_aq_alloc_free_res - command to allocate/free resources
1647 * @hw: pointer to the HW struct
1648 * @num_entries: number of resource entries in buffer
1649 * @buf: Indirect buffer to hold data parameters and response
1650 * @buf_size: size of buffer for indirect commands
1651 * @opc: pass in the command opcode
1652 * @cd: pointer to command details structure or NULL
1654 * Helper function to allocate/free resources using the admin queue commands
1657 ice_aq_alloc_free_res(struct ice_hw *hw, u16 num_entries,
1658 struct ice_aqc_alloc_free_res_elem *buf, u16 buf_size,
1659 enum ice_adminq_opc opc, struct ice_sq_cd *cd)
1661 struct ice_aqc_alloc_free_res_cmd *cmd;
1662 struct ice_aq_desc desc;
1664 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
1666 cmd = &desc.params.sw_res_ctrl;
1669 return ICE_ERR_PARAM;
1671 if (buf_size < (num_entries * sizeof(buf->elem[0])))
1672 return ICE_ERR_PARAM;
1674 ice_fill_dflt_direct_cmd_desc(&desc, opc);
1676 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
1678 cmd->num_entries = CPU_TO_LE16(num_entries);
1680 return ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);
1684 * ice_alloc_hw_res - allocate resource
1685 * @hw: pointer to the HW struct
1686 * @type: type of resource
1687 * @num: number of resources to allocate
1688 * @btm: allocate from bottom
1689 * @res: pointer to array that will receive the resources
1692 ice_alloc_hw_res(struct ice_hw *hw, u16 type, u16 num, bool btm, u16 *res)
1694 struct ice_aqc_alloc_free_res_elem *buf;
1695 enum ice_status status;
1698 buf_len = sizeof(*buf) + sizeof(buf->elem) * (num - 1);
1699 buf = (struct ice_aqc_alloc_free_res_elem *)
1700 ice_malloc(hw, buf_len);
1702 return ICE_ERR_NO_MEMORY;
1704 /* Prepare buffer to allocate resource. */
1705 buf->num_elems = CPU_TO_LE16(num);
1706 buf->res_type = CPU_TO_LE16(type | ICE_AQC_RES_TYPE_FLAG_DEDICATED |
1707 ICE_AQC_RES_TYPE_FLAG_IGNORE_INDEX);
1709 buf->res_type |= CPU_TO_LE16(ICE_AQC_RES_TYPE_FLAG_SCAN_BOTTOM);
1711 status = ice_aq_alloc_free_res(hw, 1, buf, buf_len,
1712 ice_aqc_opc_alloc_res, NULL);
1714 goto ice_alloc_res_exit;
1716 ice_memcpy(res, buf->elem, sizeof(buf->elem) * num,
1717 ICE_NONDMA_TO_NONDMA);
1725 * ice_free_hw_res - free allocated HW resource
1726 * @hw: pointer to the HW struct
1727 * @type: type of resource to free
1728 * @num: number of resources
1729 * @res: pointer to array that contains the resources to free
1732 ice_free_hw_res(struct ice_hw *hw, u16 type, u16 num, u16 *res)
1734 struct ice_aqc_alloc_free_res_elem *buf;
1735 enum ice_status status;
1738 buf_len = sizeof(*buf) + sizeof(buf->elem) * (num - 1);
1739 buf = (struct ice_aqc_alloc_free_res_elem *)ice_malloc(hw, buf_len);
1741 return ICE_ERR_NO_MEMORY;
1743 /* Prepare buffer to free resource. */
1744 buf->num_elems = CPU_TO_LE16(num);
1745 buf->res_type = CPU_TO_LE16(type);
1746 ice_memcpy(buf->elem, res, sizeof(buf->elem) * num,
1747 ICE_NONDMA_TO_NONDMA);
1749 status = ice_aq_alloc_free_res(hw, num, buf, buf_len,
1750 ice_aqc_opc_free_res, NULL);
1752 ice_debug(hw, ICE_DBG_SW, "CQ CMD Buffer:\n");
1759 * ice_get_num_per_func - determine number of resources per PF
1760 * @hw: pointer to the HW structure
1761 * @max: value to be evenly split between each PF
1763 * Determine the number of valid functions by going through the bitmap returned
1764 * from parsing capabilities and use this to calculate the number of resources
1765 * per PF based on the max value passed in.
1767 static u32 ice_get_num_per_func(struct ice_hw *hw, u32 max)
1771 #define ICE_CAPS_VALID_FUNCS_M 0xFF
1772 funcs = ice_hweight8(hw->dev_caps.common_cap.valid_functions &
1773 ICE_CAPS_VALID_FUNCS_M);
1782 * ice_parse_caps - parse function/device capabilities
1783 * @hw: pointer to the HW struct
1784 * @buf: pointer to a buffer containing function/device capability records
1785 * @cap_count: number of capability records in the list
1786 * @opc: type of capabilities list to parse
1788 * Helper function to parse function(0x000a)/device(0x000b) capabilities list.
1791 ice_parse_caps(struct ice_hw *hw, void *buf, u32 cap_count,
1792 enum ice_adminq_opc opc)
1794 struct ice_aqc_list_caps_elem *cap_resp;
1795 struct ice_hw_func_caps *func_p = NULL;
1796 struct ice_hw_dev_caps *dev_p = NULL;
1797 struct ice_hw_common_caps *caps;
1804 cap_resp = (struct ice_aqc_list_caps_elem *)buf;
1806 if (opc == ice_aqc_opc_list_dev_caps) {
1807 dev_p = &hw->dev_caps;
1808 caps = &dev_p->common_cap;
1810 } else if (opc == ice_aqc_opc_list_func_caps) {
1811 func_p = &hw->func_caps;
1812 caps = &func_p->common_cap;
1813 prefix = "func cap";
1815 ice_debug(hw, ICE_DBG_INIT, "wrong opcode\n");
1819 for (i = 0; caps && i < cap_count; i++, cap_resp++) {
1820 u32 logical_id = LE32_TO_CPU(cap_resp->logical_id);
1821 u32 phys_id = LE32_TO_CPU(cap_resp->phys_id);
1822 u32 number = LE32_TO_CPU(cap_resp->number);
1823 u16 cap = LE16_TO_CPU(cap_resp->cap);
1826 case ICE_AQC_CAPS_VALID_FUNCTIONS:
1827 caps->valid_functions = number;
1828 ice_debug(hw, ICE_DBG_INIT,
1829 "%s: valid_functions (bitmap) = %d\n", prefix,
1830 caps->valid_functions);
1832 /* store func count for resource management purposes */
1834 dev_p->num_funcs = ice_hweight32(number);
1836 case ICE_AQC_CAPS_VSI:
1838 dev_p->num_vsi_allocd_to_host = number;
1839 ice_debug(hw, ICE_DBG_INIT,
1840 "%s: num_vsi_allocd_to_host = %d\n",
1842 dev_p->num_vsi_allocd_to_host);
1843 } else if (func_p) {
1844 func_p->guar_num_vsi =
1845 ice_get_num_per_func(hw, ICE_MAX_VSI);
1846 ice_debug(hw, ICE_DBG_INIT,
1847 "%s: guar_num_vsi (fw) = %d\n",
1849 ice_debug(hw, ICE_DBG_INIT,
1850 "%s: guar_num_vsi = %d\n",
1851 prefix, func_p->guar_num_vsi);
1854 case ICE_AQC_CAPS_DCB:
1855 caps->dcb = (number == 1);
1856 caps->active_tc_bitmap = logical_id;
1857 caps->maxtc = phys_id;
1858 ice_debug(hw, ICE_DBG_INIT,
1859 "%s: dcb = %d\n", prefix, caps->dcb);
1860 ice_debug(hw, ICE_DBG_INIT,
1861 "%s: active_tc_bitmap = %d\n", prefix,
1862 caps->active_tc_bitmap);
1863 ice_debug(hw, ICE_DBG_INIT,
1864 "%s: maxtc = %d\n", prefix, caps->maxtc);
1866 case ICE_AQC_CAPS_RSS:
1867 caps->rss_table_size = number;
1868 caps->rss_table_entry_width = logical_id;
1869 ice_debug(hw, ICE_DBG_INIT,
1870 "%s: rss_table_size = %d\n", prefix,
1871 caps->rss_table_size);
1872 ice_debug(hw, ICE_DBG_INIT,
1873 "%s: rss_table_entry_width = %d\n", prefix,
1874 caps->rss_table_entry_width);
1876 case ICE_AQC_CAPS_RXQS:
1877 caps->num_rxq = number;
1878 caps->rxq_first_id = phys_id;
1879 ice_debug(hw, ICE_DBG_INIT,
1880 "%s: num_rxq = %d\n", prefix,
1882 ice_debug(hw, ICE_DBG_INIT,
1883 "%s: rxq_first_id = %d\n", prefix,
1884 caps->rxq_first_id);
1886 case ICE_AQC_CAPS_TXQS:
1887 caps->num_txq = number;
1888 caps->txq_first_id = phys_id;
1889 ice_debug(hw, ICE_DBG_INIT,
1890 "%s: num_txq = %d\n", prefix,
1892 ice_debug(hw, ICE_DBG_INIT,
1893 "%s: txq_first_id = %d\n", prefix,
1894 caps->txq_first_id);
1896 case ICE_AQC_CAPS_MSIX:
1897 caps->num_msix_vectors = number;
1898 caps->msix_vector_first_id = phys_id;
1899 ice_debug(hw, ICE_DBG_INIT,
1900 "%s: num_msix_vectors = %d\n", prefix,
1901 caps->num_msix_vectors);
1902 ice_debug(hw, ICE_DBG_INIT,
1903 "%s: msix_vector_first_id = %d\n", prefix,
1904 caps->msix_vector_first_id);
1906 case ICE_AQC_CAPS_FD:
1911 dev_p->num_flow_director_fltr = number;
1912 ice_debug(hw, ICE_DBG_INIT,
1913 "%s: num_flow_director_fltr = %d\n",
1915 dev_p->num_flow_director_fltr);
1918 reg_val = rd32(hw, GLQF_FD_SIZE);
1919 val = (reg_val & GLQF_FD_SIZE_FD_GSIZE_M) >>
1920 GLQF_FD_SIZE_FD_GSIZE_S;
1921 func_p->fd_fltr_guar =
1922 ice_get_num_per_func(hw, val);
1923 val = (reg_val & GLQF_FD_SIZE_FD_BSIZE_M) >>
1924 GLQF_FD_SIZE_FD_BSIZE_S;
1925 func_p->fd_fltr_best_effort = val;
1926 ice_debug(hw, ICE_DBG_INIT,
1927 "%s: fd_fltr_guar = %d\n",
1928 prefix, func_p->fd_fltr_guar);
1929 ice_debug(hw, ICE_DBG_INIT,
1930 "%s: fd_fltr_best_effort = %d\n",
1931 prefix, func_p->fd_fltr_best_effort);
1935 case ICE_AQC_CAPS_MAX_MTU:
1936 caps->max_mtu = number;
1937 ice_debug(hw, ICE_DBG_INIT, "%s: max_mtu = %d\n",
1938 prefix, caps->max_mtu);
1941 ice_debug(hw, ICE_DBG_INIT,
1942 "%s: unknown capability[%d]: 0x%x\n", prefix,
1948 /* Re-calculate capabilities that are dependent on the number of
1949 * physical ports; i.e. some features are not supported or function
1950 * differently on devices with more than 4 ports.
1952 if (hw->dev_caps.num_funcs > 4) {
1953 /* Max 4 TCs per port */
1955 ice_debug(hw, ICE_DBG_INIT,
1956 "%s: maxtc = %d (based on #ports)\n", prefix,
1962 * ice_aq_discover_caps - query function/device capabilities
1963 * @hw: pointer to the HW struct
1964 * @buf: a virtual buffer to hold the capabilities
1965 * @buf_size: Size of the virtual buffer
1966 * @cap_count: cap count needed if AQ err==ENOMEM
1967 * @opc: capabilities type to discover - pass in the command opcode
1968 * @cd: pointer to command details structure or NULL
1970 * Get the function(0x000a)/device(0x000b) capabilities description from
1973 static enum ice_status
1974 ice_aq_discover_caps(struct ice_hw *hw, void *buf, u16 buf_size, u32 *cap_count,
1975 enum ice_adminq_opc opc, struct ice_sq_cd *cd)
1977 struct ice_aqc_list_caps *cmd;
1978 struct ice_aq_desc desc;
1979 enum ice_status status;
1981 cmd = &desc.params.get_cap;
1983 if (opc != ice_aqc_opc_list_func_caps &&
1984 opc != ice_aqc_opc_list_dev_caps)
1985 return ICE_ERR_PARAM;
1987 ice_fill_dflt_direct_cmd_desc(&desc, opc);
1989 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);
1991 ice_parse_caps(hw, buf, LE32_TO_CPU(cmd->count), opc);
1992 else if (hw->adminq.sq_last_status == ICE_AQ_RC_ENOMEM)
1993 *cap_count = LE32_TO_CPU(cmd->count);
1998 * ice_discover_caps - get info about the HW
1999 * @hw: pointer to the hardware structure
2000 * @opc: capabilities type to discover - pass in the command opcode
2002 static enum ice_status
2003 ice_discover_caps(struct ice_hw *hw, enum ice_adminq_opc opc)
2005 enum ice_status status;
2010 /* The driver doesn't know how many capabilities the device will return
2011 * so the buffer size required isn't known ahead of time. The driver
2012 * starts with cbuf_len and if this turns out to be insufficient, the
2013 * device returns ICE_AQ_RC_ENOMEM and also the cap_count it needs.
2014 * The driver then allocates the buffer based on the count and retries
2015 * the operation. So it follows that the retry count is 2.
2017 #define ICE_GET_CAP_BUF_COUNT 40
2018 #define ICE_GET_CAP_RETRY_COUNT 2
2020 cap_count = ICE_GET_CAP_BUF_COUNT;
2021 retries = ICE_GET_CAP_RETRY_COUNT;
2026 cbuf_len = (u16)(cap_count *
2027 sizeof(struct ice_aqc_list_caps_elem));
2028 cbuf = ice_malloc(hw, cbuf_len);
2030 return ICE_ERR_NO_MEMORY;
2032 status = ice_aq_discover_caps(hw, cbuf, cbuf_len, &cap_count,
2036 if (!status || hw->adminq.sq_last_status != ICE_AQ_RC_ENOMEM)
2039 /* If ENOMEM is returned, try again with bigger buffer */
2040 } while (--retries);
2046 * ice_set_safe_mode_caps - Override dev/func capabilities when in safe mode
2047 * @hw: pointer to the hardware structure
2049 void ice_set_safe_mode_caps(struct ice_hw *hw)
2051 struct ice_hw_func_caps *func_caps = &hw->func_caps;
2052 struct ice_hw_dev_caps *dev_caps = &hw->dev_caps;
2053 u32 valid_func, rxq_first_id, txq_first_id;
2054 u32 msix_vector_first_id, max_mtu;
2057 /* cache some func_caps values that should be restored after memset */
2058 valid_func = func_caps->common_cap.valid_functions;
2059 txq_first_id = func_caps->common_cap.txq_first_id;
2060 rxq_first_id = func_caps->common_cap.rxq_first_id;
2061 msix_vector_first_id = func_caps->common_cap.msix_vector_first_id;
2062 max_mtu = func_caps->common_cap.max_mtu;
2064 /* unset func capabilities */
2065 memset(func_caps, 0, sizeof(*func_caps));
2067 /* restore cached values */
2068 func_caps->common_cap.valid_functions = valid_func;
2069 func_caps->common_cap.txq_first_id = txq_first_id;
2070 func_caps->common_cap.rxq_first_id = rxq_first_id;
2071 func_caps->common_cap.msix_vector_first_id = msix_vector_first_id;
2072 func_caps->common_cap.max_mtu = max_mtu;
2074 /* one Tx and one Rx queue in safe mode */
2075 func_caps->common_cap.num_rxq = 1;
2076 func_caps->common_cap.num_txq = 1;
2078 /* two MSIX vectors, one for traffic and one for misc causes */
2079 func_caps->common_cap.num_msix_vectors = 2;
2080 func_caps->guar_num_vsi = 1;
2082 /* cache some dev_caps values that should be restored after memset */
2083 valid_func = dev_caps->common_cap.valid_functions;
2084 txq_first_id = dev_caps->common_cap.txq_first_id;
2085 rxq_first_id = dev_caps->common_cap.rxq_first_id;
2086 msix_vector_first_id = dev_caps->common_cap.msix_vector_first_id;
2087 max_mtu = dev_caps->common_cap.max_mtu;
2088 num_funcs = dev_caps->num_funcs;
2090 /* unset dev capabilities */
2091 memset(dev_caps, 0, sizeof(*dev_caps));
2093 /* restore cached values */
2094 dev_caps->common_cap.valid_functions = valid_func;
2095 dev_caps->common_cap.txq_first_id = txq_first_id;
2096 dev_caps->common_cap.rxq_first_id = rxq_first_id;
2097 dev_caps->common_cap.msix_vector_first_id = msix_vector_first_id;
2098 dev_caps->common_cap.max_mtu = max_mtu;
2099 dev_caps->num_funcs = num_funcs;
2101 /* one Tx and one Rx queue per function in safe mode */
2102 dev_caps->common_cap.num_rxq = num_funcs;
2103 dev_caps->common_cap.num_txq = num_funcs;
2105 /* two MSIX vectors per function */
2106 dev_caps->common_cap.num_msix_vectors = 2 * num_funcs;
2110 * ice_get_caps - get info about the HW
2111 * @hw: pointer to the hardware structure
2113 enum ice_status ice_get_caps(struct ice_hw *hw)
2115 enum ice_status status;
2117 status = ice_discover_caps(hw, ice_aqc_opc_list_dev_caps);
2119 status = ice_discover_caps(hw, ice_aqc_opc_list_func_caps);
2125 * ice_aq_manage_mac_write - manage MAC address write command
2126 * @hw: pointer to the HW struct
2127 * @mac_addr: MAC address to be written as LAA/LAA+WoL/Port address
2128 * @flags: flags to control write behavior
2129 * @cd: pointer to command details structure or NULL
2131 * This function is used to write MAC address to the NVM (0x0108).
2134 ice_aq_manage_mac_write(struct ice_hw *hw, const u8 *mac_addr, u8 flags,
2135 struct ice_sq_cd *cd)
2137 struct ice_aqc_manage_mac_write *cmd;
2138 struct ice_aq_desc desc;
2140 cmd = &desc.params.mac_write;
2141 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_write);
2146 /* Prep values for flags, sah, sal */
2147 cmd->sah = HTONS(*((const u16 *)mac_addr));
2148 cmd->sal = HTONL(*((const u32 *)(mac_addr + 2)));
2150 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
2154 * ice_aq_clear_pxe_mode
2155 * @hw: pointer to the HW struct
2157 * Tell the firmware that the driver is taking over from PXE (0x0110).
2159 static enum ice_status ice_aq_clear_pxe_mode(struct ice_hw *hw)
2161 struct ice_aq_desc desc;
2163 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pxe_mode);
2164 desc.params.clear_pxe.rx_cnt = ICE_AQC_CLEAR_PXE_RX_CNT;
2166 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
2170 * ice_clear_pxe_mode - clear pxe operations mode
2171 * @hw: pointer to the HW struct
2173 * Make sure all PXE mode settings are cleared, including things
2174 * like descriptor fetch/write-back mode.
2176 void ice_clear_pxe_mode(struct ice_hw *hw)
2178 if (ice_check_sq_alive(hw, &hw->adminq))
2179 ice_aq_clear_pxe_mode(hw);
2184 * ice_get_link_speed_based_on_phy_type - returns link speed
2185 * @phy_type_low: lower part of phy_type
2186 * @phy_type_high: higher part of phy_type
2188 * This helper function will convert an entry in PHY type structure
2189 * [phy_type_low, phy_type_high] to its corresponding link speed.
2190 * Note: In the structure of [phy_type_low, phy_type_high], there should
2191 * be one bit set, as this function will convert one PHY type to its
2193 * If no bit gets set, ICE_LINK_SPEED_UNKNOWN will be returned
2194 * If more than one bit gets set, ICE_LINK_SPEED_UNKNOWN will be returned
2197 ice_get_link_speed_based_on_phy_type(u64 phy_type_low, u64 phy_type_high)
2199 u16 speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN;
2200 u16 speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN;
2202 switch (phy_type_low) {
2203 case ICE_PHY_TYPE_LOW_100BASE_TX:
2204 case ICE_PHY_TYPE_LOW_100M_SGMII:
2205 speed_phy_type_low = ICE_AQ_LINK_SPEED_100MB;
2207 case ICE_PHY_TYPE_LOW_1000BASE_T:
2208 case ICE_PHY_TYPE_LOW_1000BASE_SX:
2209 case ICE_PHY_TYPE_LOW_1000BASE_LX:
2210 case ICE_PHY_TYPE_LOW_1000BASE_KX:
2211 case ICE_PHY_TYPE_LOW_1G_SGMII:
2212 speed_phy_type_low = ICE_AQ_LINK_SPEED_1000MB;
2214 case ICE_PHY_TYPE_LOW_2500BASE_T:
2215 case ICE_PHY_TYPE_LOW_2500BASE_X:
2216 case ICE_PHY_TYPE_LOW_2500BASE_KX:
2217 speed_phy_type_low = ICE_AQ_LINK_SPEED_2500MB;
2219 case ICE_PHY_TYPE_LOW_5GBASE_T:
2220 case ICE_PHY_TYPE_LOW_5GBASE_KR:
2221 speed_phy_type_low = ICE_AQ_LINK_SPEED_5GB;
2223 case ICE_PHY_TYPE_LOW_10GBASE_T:
2224 case ICE_PHY_TYPE_LOW_10G_SFI_DA:
2225 case ICE_PHY_TYPE_LOW_10GBASE_SR:
2226 case ICE_PHY_TYPE_LOW_10GBASE_LR:
2227 case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1:
2228 case ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC:
2229 case ICE_PHY_TYPE_LOW_10G_SFI_C2C:
2230 speed_phy_type_low = ICE_AQ_LINK_SPEED_10GB;
2232 case ICE_PHY_TYPE_LOW_25GBASE_T:
2233 case ICE_PHY_TYPE_LOW_25GBASE_CR:
2234 case ICE_PHY_TYPE_LOW_25GBASE_CR_S:
2235 case ICE_PHY_TYPE_LOW_25GBASE_CR1:
2236 case ICE_PHY_TYPE_LOW_25GBASE_SR:
2237 case ICE_PHY_TYPE_LOW_25GBASE_LR:
2238 case ICE_PHY_TYPE_LOW_25GBASE_KR:
2239 case ICE_PHY_TYPE_LOW_25GBASE_KR_S:
2240 case ICE_PHY_TYPE_LOW_25GBASE_KR1:
2241 case ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC:
2242 case ICE_PHY_TYPE_LOW_25G_AUI_C2C:
2243 speed_phy_type_low = ICE_AQ_LINK_SPEED_25GB;
2245 case ICE_PHY_TYPE_LOW_40GBASE_CR4:
2246 case ICE_PHY_TYPE_LOW_40GBASE_SR4:
2247 case ICE_PHY_TYPE_LOW_40GBASE_LR4:
2248 case ICE_PHY_TYPE_LOW_40GBASE_KR4:
2249 case ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC:
2250 case ICE_PHY_TYPE_LOW_40G_XLAUI:
2251 speed_phy_type_low = ICE_AQ_LINK_SPEED_40GB;
2253 case ICE_PHY_TYPE_LOW_50GBASE_CR2:
2254 case ICE_PHY_TYPE_LOW_50GBASE_SR2:
2255 case ICE_PHY_TYPE_LOW_50GBASE_LR2:
2256 case ICE_PHY_TYPE_LOW_50GBASE_KR2:
2257 case ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC:
2258 case ICE_PHY_TYPE_LOW_50G_LAUI2:
2259 case ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC:
2260 case ICE_PHY_TYPE_LOW_50G_AUI2:
2261 case ICE_PHY_TYPE_LOW_50GBASE_CP:
2262 case ICE_PHY_TYPE_LOW_50GBASE_SR:
2263 case ICE_PHY_TYPE_LOW_50GBASE_FR:
2264 case ICE_PHY_TYPE_LOW_50GBASE_LR:
2265 case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4:
2266 case ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC:
2267 case ICE_PHY_TYPE_LOW_50G_AUI1:
2268 speed_phy_type_low = ICE_AQ_LINK_SPEED_50GB;
2270 case ICE_PHY_TYPE_LOW_100GBASE_CR4:
2271 case ICE_PHY_TYPE_LOW_100GBASE_SR4:
2272 case ICE_PHY_TYPE_LOW_100GBASE_LR4:
2273 case ICE_PHY_TYPE_LOW_100GBASE_KR4:
2274 case ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC:
2275 case ICE_PHY_TYPE_LOW_100G_CAUI4:
2276 case ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC:
2277 case ICE_PHY_TYPE_LOW_100G_AUI4:
2278 case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4:
2279 case ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4:
2280 case ICE_PHY_TYPE_LOW_100GBASE_CP2:
2281 case ICE_PHY_TYPE_LOW_100GBASE_SR2:
2282 case ICE_PHY_TYPE_LOW_100GBASE_DR:
2283 speed_phy_type_low = ICE_AQ_LINK_SPEED_100GB;
2286 speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN;
2290 switch (phy_type_high) {
2291 case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4:
2292 case ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC:
2293 case ICE_PHY_TYPE_HIGH_100G_CAUI2:
2294 case ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC:
2295 case ICE_PHY_TYPE_HIGH_100G_AUI2:
2296 speed_phy_type_high = ICE_AQ_LINK_SPEED_100GB;
2299 speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN;
2303 if (speed_phy_type_low == ICE_AQ_LINK_SPEED_UNKNOWN &&
2304 speed_phy_type_high == ICE_AQ_LINK_SPEED_UNKNOWN)
2305 return ICE_AQ_LINK_SPEED_UNKNOWN;
2306 else if (speed_phy_type_low != ICE_AQ_LINK_SPEED_UNKNOWN &&
2307 speed_phy_type_high != ICE_AQ_LINK_SPEED_UNKNOWN)
2308 return ICE_AQ_LINK_SPEED_UNKNOWN;
2309 else if (speed_phy_type_low != ICE_AQ_LINK_SPEED_UNKNOWN &&
2310 speed_phy_type_high == ICE_AQ_LINK_SPEED_UNKNOWN)
2311 return speed_phy_type_low;
2313 return speed_phy_type_high;
2317 * ice_update_phy_type
2318 * @phy_type_low: pointer to the lower part of phy_type
2319 * @phy_type_high: pointer to the higher part of phy_type
2320 * @link_speeds_bitmap: targeted link speeds bitmap
2322 * Note: For the link_speeds_bitmap structure, you can check it at
2323 * [ice_aqc_get_link_status->link_speed]. Caller can pass in
2324 * link_speeds_bitmap include multiple speeds.
2326 * Each entry in this [phy_type_low, phy_type_high] structure will
2327 * present a certain link speed. This helper function will turn on bits
2328 * in [phy_type_low, phy_type_high] structure based on the value of
2329 * link_speeds_bitmap input parameter.
2332 ice_update_phy_type(u64 *phy_type_low, u64 *phy_type_high,
2333 u16 link_speeds_bitmap)
2340 /* We first check with low part of phy_type */
2341 for (index = 0; index <= ICE_PHY_TYPE_LOW_MAX_INDEX; index++) {
2342 pt_low = BIT_ULL(index);
2343 speed = ice_get_link_speed_based_on_phy_type(pt_low, 0);
2345 if (link_speeds_bitmap & speed)
2346 *phy_type_low |= BIT_ULL(index);
2349 /* We then check with high part of phy_type */
2350 for (index = 0; index <= ICE_PHY_TYPE_HIGH_MAX_INDEX; index++) {
2351 pt_high = BIT_ULL(index);
2352 speed = ice_get_link_speed_based_on_phy_type(0, pt_high);
2354 if (link_speeds_bitmap & speed)
2355 *phy_type_high |= BIT_ULL(index);
2360 * ice_aq_set_phy_cfg
2361 * @hw: pointer to the HW struct
2362 * @pi: port info structure of the interested logical port
2363 * @cfg: structure with PHY configuration data to be set
2364 * @cd: pointer to command details structure or NULL
2366 * Set the various PHY configuration parameters supported on the Port.
2367 * One or more of the Set PHY config parameters may be ignored in an MFP
2368 * mode as the PF may not have the privilege to set some of the PHY Config
2369 * parameters. This status will be indicated by the command response (0x0601).
2372 ice_aq_set_phy_cfg(struct ice_hw *hw, struct ice_port_info *pi,
2373 struct ice_aqc_set_phy_cfg_data *cfg, struct ice_sq_cd *cd)
2375 struct ice_aq_desc desc;
2376 enum ice_status status;
2379 return ICE_ERR_PARAM;
2381 /* Ensure that only valid bits of cfg->caps can be turned on. */
2382 if (cfg->caps & ~ICE_AQ_PHY_ENA_VALID_MASK) {
2383 ice_debug(hw, ICE_DBG_PHY,
2384 "Invalid bit is set in ice_aqc_set_phy_cfg_data->caps : 0x%x\n",
2387 cfg->caps &= ICE_AQ_PHY_ENA_VALID_MASK;
2390 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_phy_cfg);
2391 desc.params.set_phy.lport_num = pi->lport;
2392 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
2394 ice_debug(hw, ICE_DBG_LINK, "phy_type_low = 0x%llx\n",
2395 (unsigned long long)LE64_TO_CPU(cfg->phy_type_low));
2396 ice_debug(hw, ICE_DBG_LINK, "phy_type_high = 0x%llx\n",
2397 (unsigned long long)LE64_TO_CPU(cfg->phy_type_high));
2398 ice_debug(hw, ICE_DBG_LINK, "caps = 0x%x\n", cfg->caps);
2399 ice_debug(hw, ICE_DBG_LINK, "low_power_ctrl = 0x%x\n",
2400 cfg->low_power_ctrl);
2401 ice_debug(hw, ICE_DBG_LINK, "eee_cap = 0x%x\n", cfg->eee_cap);
2402 ice_debug(hw, ICE_DBG_LINK, "eeer_value = 0x%x\n", cfg->eeer_value);
2403 ice_debug(hw, ICE_DBG_LINK, "link_fec_opt = 0x%x\n", cfg->link_fec_opt);
2405 status = ice_aq_send_cmd(hw, &desc, cfg, sizeof(*cfg), cd);
2408 pi->phy.curr_user_phy_cfg = *cfg;
2414 * ice_update_link_info - update status of the HW network link
2415 * @pi: port info structure of the interested logical port
2417 enum ice_status ice_update_link_info(struct ice_port_info *pi)
2419 struct ice_link_status *li;
2420 enum ice_status status;
2423 return ICE_ERR_PARAM;
2425 li = &pi->phy.link_info;
2427 status = ice_aq_get_link_info(pi, true, NULL, NULL);
2431 if (li->link_info & ICE_AQ_MEDIA_AVAILABLE) {
2432 struct ice_aqc_get_phy_caps_data *pcaps;
2436 pcaps = (struct ice_aqc_get_phy_caps_data *)
2437 ice_malloc(hw, sizeof(*pcaps));
2439 return ICE_ERR_NO_MEMORY;
2441 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_TOPO_CAP,
2443 if (status == ICE_SUCCESS)
2444 ice_memcpy(li->module_type, &pcaps->module_type,
2445 sizeof(li->module_type),
2446 ICE_NONDMA_TO_NONDMA);
2448 ice_free(hw, pcaps);
2455 * ice_cache_phy_user_req
2456 * @pi: port information structure
2457 * @cache_data: PHY logging data
2458 * @cache_mode: PHY logging mode
2460 * Log the user request on (FC, FEC, SPEED) for later user.
2463 ice_cache_phy_user_req(struct ice_port_info *pi,
2464 struct ice_phy_cache_mode_data cache_data,
2465 enum ice_phy_cache_mode cache_mode)
2470 switch (cache_mode) {
2472 pi->phy.curr_user_fc_req = cache_data.data.curr_user_fc_req;
2474 case ICE_SPEED_MODE:
2475 pi->phy.curr_user_speed_req =
2476 cache_data.data.curr_user_speed_req;
2479 pi->phy.curr_user_fec_req = cache_data.data.curr_user_fec_req;
2487 * ice_caps_to_fc_mode
2488 * @caps: PHY capabilities
2490 * Convert PHY FC capabilities to ice FC mode
2492 enum ice_fc_mode ice_caps_to_fc_mode(u8 caps)
2494 if (caps & ICE_AQC_PHY_EN_TX_LINK_PAUSE &&
2495 caps & ICE_AQC_PHY_EN_RX_LINK_PAUSE)
2498 if (caps & ICE_AQC_PHY_EN_TX_LINK_PAUSE)
2499 return ICE_FC_TX_PAUSE;
2501 if (caps & ICE_AQC_PHY_EN_RX_LINK_PAUSE)
2502 return ICE_FC_RX_PAUSE;
2508 * ice_caps_to_fec_mode
2509 * @caps: PHY capabilities
2510 * @fec_options: Link FEC options
2512 * Convert PHY FEC capabilities to ice FEC mode
2514 enum ice_fec_mode ice_caps_to_fec_mode(u8 caps, u8 fec_options)
2516 if (caps & ICE_AQC_PHY_EN_AUTO_FEC)
2517 return ICE_FEC_AUTO;
2519 if (fec_options & (ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN |
2520 ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ |
2521 ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN |
2522 ICE_AQC_PHY_FEC_25G_KR_REQ))
2523 return ICE_FEC_BASER;
2525 if (fec_options & (ICE_AQC_PHY_FEC_25G_RS_528_REQ |
2526 ICE_AQC_PHY_FEC_25G_RS_544_REQ |
2527 ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN))
2530 return ICE_FEC_NONE;
2535 * @pi: port information structure
2536 * @aq_failures: pointer to status code, specific to ice_set_fc routine
2537 * @ena_auto_link_update: enable automatic link update
2539 * Set the requested flow control mode.
2542 ice_set_fc(struct ice_port_info *pi, u8 *aq_failures, bool ena_auto_link_update)
2544 struct ice_aqc_set_phy_cfg_data cfg = { 0 };
2545 struct ice_phy_cache_mode_data cache_data;
2546 struct ice_aqc_get_phy_caps_data *pcaps;
2547 enum ice_status status;
2548 u8 pause_mask = 0x0;
2552 return ICE_ERR_PARAM;
2554 *aq_failures = ICE_SET_FC_AQ_FAIL_NONE;
2556 /* Cache user FC request */
2557 cache_data.data.curr_user_fc_req = pi->fc.req_mode;
2558 ice_cache_phy_user_req(pi, cache_data, ICE_FC_MODE);
2560 switch (pi->fc.req_mode) {
2562 pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE;
2563 pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE;
2565 case ICE_FC_RX_PAUSE:
2566 pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE;
2568 case ICE_FC_TX_PAUSE:
2569 pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE;
2575 pcaps = (struct ice_aqc_get_phy_caps_data *)
2576 ice_malloc(hw, sizeof(*pcaps));
2578 return ICE_ERR_NO_MEMORY;
2580 /* Get the current PHY config */
2581 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_SW_CFG, pcaps,
2584 *aq_failures = ICE_SET_FC_AQ_FAIL_GET;
2588 /* clear the old pause settings */
2589 cfg.caps = pcaps->caps & ~(ICE_AQC_PHY_EN_TX_LINK_PAUSE |
2590 ICE_AQC_PHY_EN_RX_LINK_PAUSE);
2592 /* set the new capabilities */
2593 cfg.caps |= pause_mask;
2595 /* If the capabilities have changed, then set the new config */
2596 if (cfg.caps != pcaps->caps) {
2597 int retry_count, retry_max = 10;
2599 /* Auto restart link so settings take effect */
2600 if (ena_auto_link_update)
2601 cfg.caps |= ICE_AQ_PHY_ENA_AUTO_LINK_UPDT;
2602 /* Copy over all the old settings */
2603 cfg.phy_type_high = pcaps->phy_type_high;
2604 cfg.phy_type_low = pcaps->phy_type_low;
2605 cfg.low_power_ctrl = pcaps->low_power_ctrl;
2606 cfg.eee_cap = pcaps->eee_cap;
2607 cfg.eeer_value = pcaps->eeer_value;
2608 cfg.link_fec_opt = pcaps->link_fec_options;
2610 status = ice_aq_set_phy_cfg(hw, pi, &cfg, NULL);
2612 *aq_failures = ICE_SET_FC_AQ_FAIL_SET;
2616 /* Update the link info
2617 * It sometimes takes a really long time for link to
2618 * come back from the atomic reset. Thus, we wait a
2621 for (retry_count = 0; retry_count < retry_max; retry_count++) {
2622 status = ice_update_link_info(pi);
2624 if (status == ICE_SUCCESS)
2627 ice_msec_delay(100, true);
2631 *aq_failures = ICE_SET_FC_AQ_FAIL_UPDATE;
2635 ice_free(hw, pcaps);
2640 * ice_phy_caps_equals_cfg
2641 * @phy_caps: PHY capabilities
2642 * @phy_cfg: PHY configuration
2644 * Helper function to determine if PHY capabilities matches PHY
2648 ice_phy_caps_equals_cfg(struct ice_aqc_get_phy_caps_data *phy_caps,
2649 struct ice_aqc_set_phy_cfg_data *phy_cfg)
2651 u8 caps_mask, cfg_mask;
2653 if (!phy_caps || !phy_cfg)
2656 /* These bits are not common between capabilities and configuration.
2657 * Do not use them to determine equality.
2659 caps_mask = ICE_AQC_PHY_CAPS_MASK & ~(ICE_AQC_PHY_AN_MODE |
2660 ICE_AQC_PHY_EN_MOD_QUAL);
2661 cfg_mask = ICE_AQ_PHY_ENA_VALID_MASK & ~ICE_AQ_PHY_ENA_AUTO_LINK_UPDT;
2663 if (phy_caps->phy_type_low != phy_cfg->phy_type_low ||
2664 phy_caps->phy_type_high != phy_cfg->phy_type_high ||
2665 ((phy_caps->caps & caps_mask) != (phy_cfg->caps & cfg_mask)) ||
2666 phy_caps->low_power_ctrl != phy_cfg->low_power_ctrl ||
2667 phy_caps->eee_cap != phy_cfg->eee_cap ||
2668 phy_caps->eeer_value != phy_cfg->eeer_value ||
2669 phy_caps->link_fec_options != phy_cfg->link_fec_opt)
2676 * ice_copy_phy_caps_to_cfg - Copy PHY ability data to configuration data
2677 * @caps: PHY ability structure to copy date from
2678 * @cfg: PHY configuration structure to copy data to
2680 * Helper function to copy AQC PHY get ability data to PHY set configuration
2684 ice_copy_phy_caps_to_cfg(struct ice_aqc_get_phy_caps_data *caps,
2685 struct ice_aqc_set_phy_cfg_data *cfg)
2690 cfg->phy_type_low = caps->phy_type_low;
2691 cfg->phy_type_high = caps->phy_type_high;
2692 cfg->caps = caps->caps;
2693 cfg->low_power_ctrl = caps->low_power_ctrl;
2694 cfg->eee_cap = caps->eee_cap;
2695 cfg->eeer_value = caps->eeer_value;
2696 cfg->link_fec_opt = caps->link_fec_options;
2700 * ice_cfg_phy_fec - Configure PHY FEC data based on FEC mode
2701 * @cfg: PHY configuration data to set FEC mode
2702 * @fec: FEC mode to configure
2704 * Caller should copy ice_aqc_get_phy_caps_data.caps ICE_AQC_PHY_EN_AUTO_FEC
2705 * (bit 7) and ice_aqc_get_phy_caps_data.link_fec_options to cfg.caps
2706 * ICE_AQ_PHY_ENA_AUTO_FEC (bit 7) and cfg.link_fec_options before calling.
2709 ice_cfg_phy_fec(struct ice_aqc_set_phy_cfg_data *cfg, enum ice_fec_mode fec)
2713 /* Clear RS bits, and AND BASE-R ability
2714 * bits and OR request bits.
2716 cfg->link_fec_opt &= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN |
2717 ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN;
2718 cfg->link_fec_opt |= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ |
2719 ICE_AQC_PHY_FEC_25G_KR_REQ;
2722 /* Clear BASE-R bits, and AND RS ability
2723 * bits and OR request bits.
2725 cfg->link_fec_opt &= ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN;
2726 cfg->link_fec_opt |= ICE_AQC_PHY_FEC_25G_RS_528_REQ |
2727 ICE_AQC_PHY_FEC_25G_RS_544_REQ;
2730 /* Clear all FEC option bits. */
2731 cfg->link_fec_opt &= ~ICE_AQC_PHY_FEC_MASK;
2734 /* AND auto FEC bit, and all caps bits. */
2735 cfg->caps &= ICE_AQC_PHY_CAPS_MASK;
2741 * ice_get_link_status - get status of the HW network link
2742 * @pi: port information structure
2743 * @link_up: pointer to bool (true/false = linkup/linkdown)
2745 * Variable link_up is true if link is up, false if link is down.
2746 * The variable link_up is invalid if status is non zero. As a
2747 * result of this call, link status reporting becomes enabled
2749 enum ice_status ice_get_link_status(struct ice_port_info *pi, bool *link_up)
2751 struct ice_phy_info *phy_info;
2752 enum ice_status status = ICE_SUCCESS;
2754 if (!pi || !link_up)
2755 return ICE_ERR_PARAM;
2757 phy_info = &pi->phy;
2759 if (phy_info->get_link_info) {
2760 status = ice_update_link_info(pi);
2763 ice_debug(pi->hw, ICE_DBG_LINK,
2764 "get link status error, status = %d\n",
2768 *link_up = phy_info->link_info.link_info & ICE_AQ_LINK_UP;
2774 * ice_aq_set_link_restart_an
2775 * @pi: pointer to the port information structure
2776 * @ena_link: if true: enable link, if false: disable link
2777 * @cd: pointer to command details structure or NULL
2779 * Sets up the link and restarts the Auto-Negotiation over the link.
2782 ice_aq_set_link_restart_an(struct ice_port_info *pi, bool ena_link,
2783 struct ice_sq_cd *cd)
2785 struct ice_aqc_restart_an *cmd;
2786 struct ice_aq_desc desc;
2788 cmd = &desc.params.restart_an;
2790 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_restart_an);
2792 cmd->cmd_flags = ICE_AQC_RESTART_AN_LINK_RESTART;
2793 cmd->lport_num = pi->lport;
2795 cmd->cmd_flags |= ICE_AQC_RESTART_AN_LINK_ENABLE;
2797 cmd->cmd_flags &= ~ICE_AQC_RESTART_AN_LINK_ENABLE;
2799 return ice_aq_send_cmd(pi->hw, &desc, NULL, 0, cd);
2803 * ice_aq_set_event_mask
2804 * @hw: pointer to the HW struct
2805 * @port_num: port number of the physical function
2806 * @mask: event mask to be set
2807 * @cd: pointer to command details structure or NULL
2809 * Set event mask (0x0613)
2812 ice_aq_set_event_mask(struct ice_hw *hw, u8 port_num, u16 mask,
2813 struct ice_sq_cd *cd)
2815 struct ice_aqc_set_event_mask *cmd;
2816 struct ice_aq_desc desc;
2818 cmd = &desc.params.set_event_mask;
2820 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_event_mask);
2822 cmd->lport_num = port_num;
2824 cmd->event_mask = CPU_TO_LE16(mask);
2825 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
2829 * ice_aq_set_mac_loopback
2830 * @hw: pointer to the HW struct
2831 * @ena_lpbk: Enable or Disable loopback
2832 * @cd: pointer to command details structure or NULL
2834 * Enable/disable loopback on a given port
2837 ice_aq_set_mac_loopback(struct ice_hw *hw, bool ena_lpbk, struct ice_sq_cd *cd)
2839 struct ice_aqc_set_mac_lb *cmd;
2840 struct ice_aq_desc desc;
2842 cmd = &desc.params.set_mac_lb;
2844 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_mac_lb);
2846 cmd->lb_mode = ICE_AQ_MAC_LB_EN;
2848 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
2853 * ice_aq_set_port_id_led
2854 * @pi: pointer to the port information
2855 * @is_orig_mode: is this LED set to original mode (by the net-list)
2856 * @cd: pointer to command details structure or NULL
2858 * Set LED value for the given port (0x06e9)
2861 ice_aq_set_port_id_led(struct ice_port_info *pi, bool is_orig_mode,
2862 struct ice_sq_cd *cd)
2864 struct ice_aqc_set_port_id_led *cmd;
2865 struct ice_hw *hw = pi->hw;
2866 struct ice_aq_desc desc;
2868 cmd = &desc.params.set_port_id_led;
2870 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_port_id_led);
2874 cmd->ident_mode = ICE_AQC_PORT_IDENT_LED_ORIG;
2876 cmd->ident_mode = ICE_AQC_PORT_IDENT_LED_BLINK;
2878 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
2883 * @hw: pointer to the HW struct
2884 * @lport: bits [7:0] = logical port, bit [8] = logical port valid
2885 * @bus_addr: I2C bus address of the eeprom (typically 0xA0, 0=topo default)
2886 * @mem_addr: I2C offset. lower 8 bits for address, 8 upper bits zero padding.
2888 * @set_page: set or ignore the page
2889 * @data: pointer to data buffer to be read/written to the I2C device.
2890 * @length: 1-16 for read, 1 for write.
2891 * @write: 0 read, 1 for write.
2892 * @cd: pointer to command details structure or NULL
2894 * Read/Write SFF EEPROM (0x06EE)
2897 ice_aq_sff_eeprom(struct ice_hw *hw, u16 lport, u8 bus_addr,
2898 u16 mem_addr, u8 page, u8 set_page, u8 *data, u8 length,
2899 bool write, struct ice_sq_cd *cd)
2901 struct ice_aqc_sff_eeprom *cmd;
2902 struct ice_aq_desc desc;
2903 enum ice_status status;
2905 if (!data || (mem_addr & 0xff00))
2906 return ICE_ERR_PARAM;
2908 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_sff_eeprom);
2909 cmd = &desc.params.read_write_sff_param;
2910 desc.flags = CPU_TO_LE16(ICE_AQ_FLAG_RD | ICE_AQ_FLAG_BUF);
2911 cmd->lport_num = (u8)(lport & 0xff);
2912 cmd->lport_num_valid = (u8)((lport >> 8) & 0x01);
2913 cmd->i2c_bus_addr = CPU_TO_LE16(((bus_addr >> 1) &
2914 ICE_AQC_SFF_I2CBUS_7BIT_M) |
2916 ICE_AQC_SFF_SET_EEPROM_PAGE_S) &
2917 ICE_AQC_SFF_SET_EEPROM_PAGE_M));
2918 cmd->i2c_mem_addr = CPU_TO_LE16(mem_addr & 0xff);
2919 cmd->eeprom_page = CPU_TO_LE16((u16)page << ICE_AQC_SFF_EEPROM_PAGE_S);
2921 cmd->i2c_bus_addr |= CPU_TO_LE16(ICE_AQC_SFF_IS_WRITE);
2923 status = ice_aq_send_cmd(hw, &desc, data, length, cd);
2928 * __ice_aq_get_set_rss_lut
2929 * @hw: pointer to the hardware structure
2930 * @vsi_id: VSI FW index
2931 * @lut_type: LUT table type
2932 * @lut: pointer to the LUT buffer provided by the caller
2933 * @lut_size: size of the LUT buffer
2934 * @glob_lut_idx: global LUT index
2935 * @set: set true to set the table, false to get the table
2937 * Internal function to get (0x0B05) or set (0x0B03) RSS look up table
2939 static enum ice_status
2940 __ice_aq_get_set_rss_lut(struct ice_hw *hw, u16 vsi_id, u8 lut_type, u8 *lut,
2941 u16 lut_size, u8 glob_lut_idx, bool set)
2943 struct ice_aqc_get_set_rss_lut *cmd_resp;
2944 struct ice_aq_desc desc;
2945 enum ice_status status;
2948 cmd_resp = &desc.params.get_set_rss_lut;
2951 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_rss_lut);
2952 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
2954 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_rss_lut);
2957 cmd_resp->vsi_id = CPU_TO_LE16(((vsi_id <<
2958 ICE_AQC_GSET_RSS_LUT_VSI_ID_S) &
2959 ICE_AQC_GSET_RSS_LUT_VSI_ID_M) |
2960 ICE_AQC_GSET_RSS_LUT_VSI_VALID);
2963 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_VSI:
2964 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF:
2965 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL:
2966 flags |= ((lut_type << ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S) &
2967 ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_M);
2970 status = ICE_ERR_PARAM;
2971 goto ice_aq_get_set_rss_lut_exit;
2974 if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL) {
2975 flags |= ((glob_lut_idx << ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S) &
2976 ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_M);
2979 goto ice_aq_get_set_rss_lut_send;
2980 } else if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF) {
2982 goto ice_aq_get_set_rss_lut_send;
2984 goto ice_aq_get_set_rss_lut_send;
2987 /* LUT size is only valid for Global and PF table types */
2989 case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128:
2990 flags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128_FLAG <<
2991 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) &
2992 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M;
2994 case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512:
2995 flags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512_FLAG <<
2996 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) &
2997 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M;
2999 case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K:
3000 if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF) {
3001 flags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K_FLAG <<
3002 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) &
3003 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M;
3008 status = ICE_ERR_PARAM;
3009 goto ice_aq_get_set_rss_lut_exit;
3012 ice_aq_get_set_rss_lut_send:
3013 cmd_resp->flags = CPU_TO_LE16(flags);
3014 status = ice_aq_send_cmd(hw, &desc, lut, lut_size, NULL);
3016 ice_aq_get_set_rss_lut_exit:
3021 * ice_aq_get_rss_lut
3022 * @hw: pointer to the hardware structure
3023 * @vsi_handle: software VSI handle
3024 * @lut_type: LUT table type
3025 * @lut: pointer to the LUT buffer provided by the caller
3026 * @lut_size: size of the LUT buffer
3028 * get the RSS lookup table, PF or VSI type
3031 ice_aq_get_rss_lut(struct ice_hw *hw, u16 vsi_handle, u8 lut_type,
3032 u8 *lut, u16 lut_size)
3034 if (!ice_is_vsi_valid(hw, vsi_handle) || !lut)
3035 return ICE_ERR_PARAM;
3037 return __ice_aq_get_set_rss_lut(hw, ice_get_hw_vsi_num(hw, vsi_handle),
3038 lut_type, lut, lut_size, 0, false);
3042 * ice_aq_set_rss_lut
3043 * @hw: pointer to the hardware structure
3044 * @vsi_handle: software VSI handle
3045 * @lut_type: LUT table type
3046 * @lut: pointer to the LUT buffer provided by the caller
3047 * @lut_size: size of the LUT buffer
3049 * set the RSS lookup table, PF or VSI type
3052 ice_aq_set_rss_lut(struct ice_hw *hw, u16 vsi_handle, u8 lut_type,
3053 u8 *lut, u16 lut_size)
3055 if (!ice_is_vsi_valid(hw, vsi_handle) || !lut)
3056 return ICE_ERR_PARAM;
3058 return __ice_aq_get_set_rss_lut(hw, ice_get_hw_vsi_num(hw, vsi_handle),
3059 lut_type, lut, lut_size, 0, true);
3063 * __ice_aq_get_set_rss_key
3064 * @hw: pointer to the HW struct
3065 * @vsi_id: VSI FW index
3066 * @key: pointer to key info struct
3067 * @set: set true to set the key, false to get the key
3069 * get (0x0B04) or set (0x0B02) the RSS key per VSI
3072 ice_status __ice_aq_get_set_rss_key(struct ice_hw *hw, u16 vsi_id,
3073 struct ice_aqc_get_set_rss_keys *key,
3076 struct ice_aqc_get_set_rss_key *cmd_resp;
3077 u16 key_size = sizeof(*key);
3078 struct ice_aq_desc desc;
3080 cmd_resp = &desc.params.get_set_rss_key;
3083 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_rss_key);
3084 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
3086 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_rss_key);
3089 cmd_resp->vsi_id = CPU_TO_LE16(((vsi_id <<
3090 ICE_AQC_GSET_RSS_KEY_VSI_ID_S) &
3091 ICE_AQC_GSET_RSS_KEY_VSI_ID_M) |
3092 ICE_AQC_GSET_RSS_KEY_VSI_VALID);
3094 return ice_aq_send_cmd(hw, &desc, key, key_size, NULL);
3098 * ice_aq_get_rss_key
3099 * @hw: pointer to the HW struct
3100 * @vsi_handle: software VSI handle
3101 * @key: pointer to key info struct
3103 * get the RSS key per VSI
3106 ice_aq_get_rss_key(struct ice_hw *hw, u16 vsi_handle,
3107 struct ice_aqc_get_set_rss_keys *key)
3109 if (!ice_is_vsi_valid(hw, vsi_handle) || !key)
3110 return ICE_ERR_PARAM;
3112 return __ice_aq_get_set_rss_key(hw, ice_get_hw_vsi_num(hw, vsi_handle),
3117 * ice_aq_set_rss_key
3118 * @hw: pointer to the HW struct
3119 * @vsi_handle: software VSI handle
3120 * @keys: pointer to key info struct
3122 * set the RSS key per VSI
3125 ice_aq_set_rss_key(struct ice_hw *hw, u16 vsi_handle,
3126 struct ice_aqc_get_set_rss_keys *keys)
3128 if (!ice_is_vsi_valid(hw, vsi_handle) || !keys)
3129 return ICE_ERR_PARAM;
3131 return __ice_aq_get_set_rss_key(hw, ice_get_hw_vsi_num(hw, vsi_handle),
3136 * ice_aq_add_lan_txq
3137 * @hw: pointer to the hardware structure
3138 * @num_qgrps: Number of added queue groups
3139 * @qg_list: list of queue groups to be added
3140 * @buf_size: size of buffer for indirect command
3141 * @cd: pointer to command details structure or NULL
3143 * Add Tx LAN queue (0x0C30)
3146 * Prior to calling add Tx LAN queue:
3147 * Initialize the following as part of the Tx queue context:
3148 * Completion queue ID if the queue uses Completion queue, Quanta profile,
3149 * Cache profile and Packet shaper profile.
3151 * After add Tx LAN queue AQ command is completed:
3152 * Interrupts should be associated with specific queues,
3153 * Association of Tx queue to Doorbell queue is not part of Add LAN Tx queue
3157 ice_aq_add_lan_txq(struct ice_hw *hw, u8 num_qgrps,
3158 struct ice_aqc_add_tx_qgrp *qg_list, u16 buf_size,
3159 struct ice_sq_cd *cd)
3161 u16 i, sum_header_size, sum_q_size = 0;
3162 struct ice_aqc_add_tx_qgrp *list;
3163 struct ice_aqc_add_txqs *cmd;
3164 struct ice_aq_desc desc;
3166 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
3168 cmd = &desc.params.add_txqs;
3170 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_add_txqs);
3173 return ICE_ERR_PARAM;
3175 if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS)
3176 return ICE_ERR_PARAM;
3178 sum_header_size = num_qgrps *
3179 (sizeof(*qg_list) - sizeof(*qg_list->txqs));
3182 for (i = 0; i < num_qgrps; i++) {
3183 struct ice_aqc_add_txqs_perq *q = list->txqs;
3185 sum_q_size += list->num_txqs * sizeof(*q);
3186 list = (struct ice_aqc_add_tx_qgrp *)(q + list->num_txqs);
3189 if (buf_size != (sum_header_size + sum_q_size))
3190 return ICE_ERR_PARAM;
3192 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
3194 cmd->num_qgrps = num_qgrps;
3196 return ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd);
3200 * ice_aq_dis_lan_txq
3201 * @hw: pointer to the hardware structure
3202 * @num_qgrps: number of groups in the list
3203 * @qg_list: the list of groups to disable
3204 * @buf_size: the total size of the qg_list buffer in bytes
3205 * @rst_src: if called due to reset, specifies the reset source
3206 * @vmvf_num: the relative VM or VF number that is undergoing the reset
3207 * @cd: pointer to command details structure or NULL
3209 * Disable LAN Tx queue (0x0C31)
3211 static enum ice_status
3212 ice_aq_dis_lan_txq(struct ice_hw *hw, u8 num_qgrps,
3213 struct ice_aqc_dis_txq_item *qg_list, u16 buf_size,
3214 enum ice_disq_rst_src rst_src, u16 vmvf_num,
3215 struct ice_sq_cd *cd)
3217 struct ice_aqc_dis_txqs *cmd;
3218 struct ice_aq_desc desc;
3219 enum ice_status status;
3222 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
3223 cmd = &desc.params.dis_txqs;
3224 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_dis_txqs);
3226 /* qg_list can be NULL only in VM/VF reset flow */
3227 if (!qg_list && !rst_src)
3228 return ICE_ERR_PARAM;
3230 if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS)
3231 return ICE_ERR_PARAM;
3233 cmd->num_entries = num_qgrps;
3235 cmd->vmvf_and_timeout = CPU_TO_LE16((5 << ICE_AQC_Q_DIS_TIMEOUT_S) &
3236 ICE_AQC_Q_DIS_TIMEOUT_M);
3240 cmd->cmd_type = ICE_AQC_Q_DIS_CMD_VM_RESET;
3241 cmd->vmvf_and_timeout |=
3242 CPU_TO_LE16(vmvf_num & ICE_AQC_Q_DIS_VMVF_NUM_M);
3249 /* flush pipe on time out */
3250 cmd->cmd_type |= ICE_AQC_Q_DIS_CMD_FLUSH_PIPE;
3251 /* If no queue group info, we are in a reset flow. Issue the AQ */
3255 /* set RD bit to indicate that command buffer is provided by the driver
3256 * and it needs to be read by the firmware
3258 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
3260 for (i = 0; i < num_qgrps; ++i) {
3261 /* Calculate the size taken up by the queue IDs in this group */
3262 sz += qg_list[i].num_qs * sizeof(qg_list[i].q_id);
3264 /* Add the size of the group header */
3265 sz += sizeof(qg_list[i]) - sizeof(qg_list[i].q_id);
3267 /* If the num of queues is even, add 2 bytes of padding */
3268 if ((qg_list[i].num_qs % 2) == 0)
3273 return ICE_ERR_PARAM;
3276 status = ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd);
3279 ice_debug(hw, ICE_DBG_SCHED, "VM%d disable failed %d\n",
3280 vmvf_num, hw->adminq.sq_last_status);
3282 ice_debug(hw, ICE_DBG_SCHED, "disable queue %d failed %d\n",
3283 LE16_TO_CPU(qg_list[0].q_id[0]),
3284 hw->adminq.sq_last_status);
3290 * ice_aq_move_recfg_lan_txq
3291 * @hw: pointer to the hardware structure
3292 * @num_qs: number of queues to move/reconfigure
3293 * @is_move: true if this operation involves node movement
3294 * @is_tc_change: true if this operation involves a TC change
3295 * @subseq_call: true if this operation is a subsequent call
3296 * @flush_pipe: on timeout, true to flush pipe, false to return EAGAIN
3297 * @timeout: timeout in units of 100 usec (valid values 0-50)
3298 * @blocked_cgds: out param, bitmap of CGDs that timed out if returning EAGAIN
3299 * @buf: struct containing src/dest TEID and per-queue info
3300 * @buf_size: size of buffer for indirect command
3301 * @txqs_moved: out param, number of queues successfully moved
3302 * @cd: pointer to command details structure or NULL
3304 * Move / Reconfigure Tx LAN queues (0x0C32)
3307 ice_aq_move_recfg_lan_txq(struct ice_hw *hw, u8 num_qs, bool is_move,
3308 bool is_tc_change, bool subseq_call, bool flush_pipe,
3309 u8 timeout, u32 *blocked_cgds,
3310 struct ice_aqc_move_txqs_data *buf, u16 buf_size,
3311 u8 *txqs_moved, struct ice_sq_cd *cd)
3313 struct ice_aqc_move_txqs *cmd;
3314 struct ice_aq_desc desc;
3315 enum ice_status status;
3317 cmd = &desc.params.move_txqs;
3318 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_move_recfg_txqs);
3320 #define ICE_LAN_TXQ_MOVE_TIMEOUT_MAX 50
3321 if (timeout > ICE_LAN_TXQ_MOVE_TIMEOUT_MAX)
3322 return ICE_ERR_PARAM;
3324 if (is_tc_change && !flush_pipe && !blocked_cgds)
3325 return ICE_ERR_PARAM;
3327 if (!is_move && !is_tc_change)
3328 return ICE_ERR_PARAM;
3330 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
3333 cmd->cmd_type |= ICE_AQC_Q_CMD_TYPE_MOVE;
3336 cmd->cmd_type |= ICE_AQC_Q_CMD_TYPE_TC_CHANGE;
3339 cmd->cmd_type |= ICE_AQC_Q_CMD_SUBSEQ_CALL;
3342 cmd->cmd_type |= ICE_AQC_Q_CMD_FLUSH_PIPE;
3344 cmd->num_qs = num_qs;
3345 cmd->timeout = ((timeout << ICE_AQC_Q_CMD_TIMEOUT_S) &
3346 ICE_AQC_Q_CMD_TIMEOUT_M);
3348 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);
3350 if (!status && txqs_moved)
3351 *txqs_moved = cmd->num_qs;
3353 if (hw->adminq.sq_last_status == ICE_AQ_RC_EAGAIN &&
3354 is_tc_change && !flush_pipe)
3355 *blocked_cgds = LE32_TO_CPU(cmd->blocked_cgds);
3361 /* End of FW Admin Queue command wrappers */
3364 * ice_write_byte - write a byte to a packed context structure
3365 * @src_ctx: the context structure to read from
3366 * @dest_ctx: the context to be written to
3367 * @ce_info: a description of the struct to be filled
3370 ice_write_byte(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)
3372 u8 src_byte, dest_byte, mask;
3376 /* copy from the next struct field */
3377 from = src_ctx + ce_info->offset;
3379 /* prepare the bits and mask */
3380 shift_width = ce_info->lsb % 8;
3381 mask = (u8)(BIT(ce_info->width) - 1);
3386 /* shift to correct alignment */
3387 mask <<= shift_width;
3388 src_byte <<= shift_width;
3390 /* get the current bits from the target bit string */
3391 dest = dest_ctx + (ce_info->lsb / 8);
3393 ice_memcpy(&dest_byte, dest, sizeof(dest_byte), ICE_DMA_TO_NONDMA);
3395 dest_byte &= ~mask; /* get the bits not changing */
3396 dest_byte |= src_byte; /* add in the new bits */
3398 /* put it all back */
3399 ice_memcpy(dest, &dest_byte, sizeof(dest_byte), ICE_NONDMA_TO_DMA);
3403 * ice_write_word - write a word to a packed context structure
3404 * @src_ctx: the context structure to read from
3405 * @dest_ctx: the context to be written to
3406 * @ce_info: a description of the struct to be filled
3409 ice_write_word(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)
3416 /* copy from the next struct field */
3417 from = src_ctx + ce_info->offset;
3419 /* prepare the bits and mask */
3420 shift_width = ce_info->lsb % 8;
3421 mask = BIT(ce_info->width) - 1;
3423 /* don't swizzle the bits until after the mask because the mask bits
3424 * will be in a different bit position on big endian machines
3426 src_word = *(u16 *)from;
3429 /* shift to correct alignment */
3430 mask <<= shift_width;
3431 src_word <<= shift_width;
3433 /* get the current bits from the target bit string */
3434 dest = dest_ctx + (ce_info->lsb / 8);
3436 ice_memcpy(&dest_word, dest, sizeof(dest_word), ICE_DMA_TO_NONDMA);
3438 dest_word &= ~(CPU_TO_LE16(mask)); /* get the bits not changing */
3439 dest_word |= CPU_TO_LE16(src_word); /* add in the new bits */
3441 /* put it all back */
3442 ice_memcpy(dest, &dest_word, sizeof(dest_word), ICE_NONDMA_TO_DMA);
3446 * ice_write_dword - write a dword to a packed context structure
3447 * @src_ctx: the context structure to read from
3448 * @dest_ctx: the context to be written to
3449 * @ce_info: a description of the struct to be filled
3452 ice_write_dword(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)
3454 u32 src_dword, mask;
3459 /* copy from the next struct field */
3460 from = src_ctx + ce_info->offset;
3462 /* prepare the bits and mask */
3463 shift_width = ce_info->lsb % 8;
3465 /* if the field width is exactly 32 on an x86 machine, then the shift
3466 * operation will not work because the SHL instructions count is masked
3467 * to 5 bits so the shift will do nothing
3469 if (ce_info->width < 32)
3470 mask = BIT(ce_info->width) - 1;
3474 /* don't swizzle the bits until after the mask because the mask bits
3475 * will be in a different bit position on big endian machines
3477 src_dword = *(u32 *)from;
3480 /* shift to correct alignment */
3481 mask <<= shift_width;
3482 src_dword <<= shift_width;
3484 /* get the current bits from the target bit string */
3485 dest = dest_ctx + (ce_info->lsb / 8);
3487 ice_memcpy(&dest_dword, dest, sizeof(dest_dword), ICE_DMA_TO_NONDMA);
3489 dest_dword &= ~(CPU_TO_LE32(mask)); /* get the bits not changing */
3490 dest_dword |= CPU_TO_LE32(src_dword); /* add in the new bits */
3492 /* put it all back */
3493 ice_memcpy(dest, &dest_dword, sizeof(dest_dword), ICE_NONDMA_TO_DMA);
3497 * ice_write_qword - write a qword to a packed context structure
3498 * @src_ctx: the context structure to read from
3499 * @dest_ctx: the context to be written to
3500 * @ce_info: a description of the struct to be filled
3503 ice_write_qword(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)
3505 u64 src_qword, mask;
3510 /* copy from the next struct field */
3511 from = src_ctx + ce_info->offset;
3513 /* prepare the bits and mask */
3514 shift_width = ce_info->lsb % 8;
3516 /* if the field width is exactly 64 on an x86 machine, then the shift
3517 * operation will not work because the SHL instructions count is masked
3518 * to 6 bits so the shift will do nothing
3520 if (ce_info->width < 64)
3521 mask = BIT_ULL(ce_info->width) - 1;
3525 /* don't swizzle the bits until after the mask because the mask bits
3526 * will be in a different bit position on big endian machines
3528 src_qword = *(u64 *)from;
3531 /* shift to correct alignment */
3532 mask <<= shift_width;
3533 src_qword <<= shift_width;
3535 /* get the current bits from the target bit string */
3536 dest = dest_ctx + (ce_info->lsb / 8);
3538 ice_memcpy(&dest_qword, dest, sizeof(dest_qword), ICE_DMA_TO_NONDMA);
3540 dest_qword &= ~(CPU_TO_LE64(mask)); /* get the bits not changing */
3541 dest_qword |= CPU_TO_LE64(src_qword); /* add in the new bits */
3543 /* put it all back */
3544 ice_memcpy(dest, &dest_qword, sizeof(dest_qword), ICE_NONDMA_TO_DMA);
3548 * ice_set_ctx - set context bits in packed structure
3549 * @src_ctx: pointer to a generic non-packed context structure
3550 * @dest_ctx: pointer to memory for the packed structure
3551 * @ce_info: a description of the structure to be transformed
3554 ice_set_ctx(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)
3558 for (f = 0; ce_info[f].width; f++) {
3559 /* We have to deal with each element of the FW response
3560 * using the correct size so that we are correct regardless
3561 * of the endianness of the machine.
3563 switch (ce_info[f].size_of) {
3565 ice_write_byte(src_ctx, dest_ctx, &ce_info[f]);
3568 ice_write_word(src_ctx, dest_ctx, &ce_info[f]);
3571 ice_write_dword(src_ctx, dest_ctx, &ce_info[f]);
3574 ice_write_qword(src_ctx, dest_ctx, &ce_info[f]);
3577 return ICE_ERR_INVAL_SIZE;
3588 * ice_read_byte - read context byte into struct
3589 * @src_ctx: the context structure to read from
3590 * @dest_ctx: the context to be written to
3591 * @ce_info: a description of the struct to be filled
3594 ice_read_byte(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info)
3600 /* prepare the bits and mask */
3601 shift_width = ce_info->lsb % 8;
3602 mask = (u8)(BIT(ce_info->width) - 1);
3604 /* shift to correct alignment */
3605 mask <<= shift_width;
3607 /* get the current bits from the src bit string */
3608 src = src_ctx + (ce_info->lsb / 8);
3610 ice_memcpy(&dest_byte, src, sizeof(dest_byte), ICE_DMA_TO_NONDMA);
3612 dest_byte &= ~(mask);
3614 dest_byte >>= shift_width;
3616 /* get the address from the struct field */
3617 target = dest_ctx + ce_info->offset;
3619 /* put it back in the struct */
3620 ice_memcpy(target, &dest_byte, sizeof(dest_byte), ICE_NONDMA_TO_DMA);
3624 * ice_read_word - read context word into struct
3625 * @src_ctx: the context structure to read from
3626 * @dest_ctx: the context to be written to
3627 * @ce_info: a description of the struct to be filled
3630 ice_read_word(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info)
3632 u16 dest_word, mask;
3637 /* prepare the bits and mask */
3638 shift_width = ce_info->lsb % 8;
3639 mask = BIT(ce_info->width) - 1;
3641 /* shift to correct alignment */
3642 mask <<= shift_width;
3644 /* get the current bits from the src bit string */
3645 src = src_ctx + (ce_info->lsb / 8);
3647 ice_memcpy(&src_word, src, sizeof(src_word), ICE_DMA_TO_NONDMA);
3649 /* the data in the memory is stored as little endian so mask it
3652 src_word &= ~(CPU_TO_LE16(mask));
3654 /* get the data back into host order before shifting */
3655 dest_word = LE16_TO_CPU(src_word);
3657 dest_word >>= shift_width;
3659 /* get the address from the struct field */
3660 target = dest_ctx + ce_info->offset;
3662 /* put it back in the struct */
3663 ice_memcpy(target, &dest_word, sizeof(dest_word), ICE_NONDMA_TO_DMA);
3667 * ice_read_dword - read context dword into struct
3668 * @src_ctx: the context structure to read from
3669 * @dest_ctx: the context to be written to
3670 * @ce_info: a description of the struct to be filled
3673 ice_read_dword(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info)
3675 u32 dest_dword, mask;
3680 /* prepare the bits and mask */
3681 shift_width = ce_info->lsb % 8;
3683 /* if the field width is exactly 32 on an x86 machine, then the shift
3684 * operation will not work because the SHL instructions count is masked
3685 * to 5 bits so the shift will do nothing
3687 if (ce_info->width < 32)
3688 mask = BIT(ce_info->width) - 1;
3692 /* shift to correct alignment */
3693 mask <<= shift_width;
3695 /* get the current bits from the src bit string */
3696 src = src_ctx + (ce_info->lsb / 8);
3698 ice_memcpy(&src_dword, src, sizeof(src_dword), ICE_DMA_TO_NONDMA);
3700 /* the data in the memory is stored as little endian so mask it
3703 src_dword &= ~(CPU_TO_LE32(mask));
3705 /* get the data back into host order before shifting */
3706 dest_dword = LE32_TO_CPU(src_dword);
3708 dest_dword >>= shift_width;
3710 /* get the address from the struct field */
3711 target = dest_ctx + ce_info->offset;
3713 /* put it back in the struct */
3714 ice_memcpy(target, &dest_dword, sizeof(dest_dword), ICE_NONDMA_TO_DMA);
3718 * ice_read_qword - read context qword into struct
3719 * @src_ctx: the context structure to read from
3720 * @dest_ctx: the context to be written to
3721 * @ce_info: a description of the struct to be filled
3724 ice_read_qword(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info)
3726 u64 dest_qword, mask;
3731 /* prepare the bits and mask */
3732 shift_width = ce_info->lsb % 8;
3734 /* if the field width is exactly 64 on an x86 machine, then the shift
3735 * operation will not work because the SHL instructions count is masked
3736 * to 6 bits so the shift will do nothing
3738 if (ce_info->width < 64)
3739 mask = BIT_ULL(ce_info->width) - 1;
3743 /* shift to correct alignment */
3744 mask <<= shift_width;
3746 /* get the current bits from the src bit string */
3747 src = src_ctx + (ce_info->lsb / 8);
3749 ice_memcpy(&src_qword, src, sizeof(src_qword), ICE_DMA_TO_NONDMA);
3751 /* the data in the memory is stored as little endian so mask it
3754 src_qword &= ~(CPU_TO_LE64(mask));
3756 /* get the data back into host order before shifting */
3757 dest_qword = LE64_TO_CPU(src_qword);
3759 dest_qword >>= shift_width;
3761 /* get the address from the struct field */
3762 target = dest_ctx + ce_info->offset;
3764 /* put it back in the struct */
3765 ice_memcpy(target, &dest_qword, sizeof(dest_qword), ICE_NONDMA_TO_DMA);
3769 * ice_get_ctx - extract context bits from a packed structure
3770 * @src_ctx: pointer to a generic packed context structure
3771 * @dest_ctx: pointer to a generic non-packed context structure
3772 * @ce_info: a description of the structure to be read from
3775 ice_get_ctx(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info)
3779 for (f = 0; ce_info[f].width; f++) {
3780 switch (ce_info[f].size_of) {
3782 ice_read_byte(src_ctx, dest_ctx, &ce_info[f]);
3785 ice_read_word(src_ctx, dest_ctx, &ce_info[f]);
3788 ice_read_dword(src_ctx, dest_ctx, &ce_info[f]);
3791 ice_read_qword(src_ctx, dest_ctx, &ce_info[f]);
3794 /* nothing to do, just keep going */
3803 * ice_get_lan_q_ctx - get the LAN queue context for the given VSI and TC
3804 * @hw: pointer to the HW struct
3805 * @vsi_handle: software VSI handle
3807 * @q_handle: software queue handle
3810 ice_get_lan_q_ctx(struct ice_hw *hw, u16 vsi_handle, u8 tc, u16 q_handle)
3812 struct ice_vsi_ctx *vsi;
3813 struct ice_q_ctx *q_ctx;
3815 vsi = ice_get_vsi_ctx(hw, vsi_handle);
3818 if (q_handle >= vsi->num_lan_q_entries[tc])
3820 if (!vsi->lan_q_ctx[tc])
3822 q_ctx = vsi->lan_q_ctx[tc];
3823 return &q_ctx[q_handle];
3828 * @pi: port information structure
3829 * @vsi_handle: software VSI handle
3831 * @q_handle: software queue handle
3832 * @num_qgrps: Number of added queue groups
3833 * @buf: list of queue groups to be added
3834 * @buf_size: size of buffer for indirect command
3835 * @cd: pointer to command details structure or NULL
3837 * This function adds one LAN queue
3840 ice_ena_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u16 q_handle,
3841 u8 num_qgrps, struct ice_aqc_add_tx_qgrp *buf, u16 buf_size,
3842 struct ice_sq_cd *cd)
3844 struct ice_aqc_txsched_elem_data node = { 0 };
3845 struct ice_sched_node *parent;
3846 struct ice_q_ctx *q_ctx;
3847 enum ice_status status;
3850 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY)
3853 if (num_qgrps > 1 || buf->num_txqs > 1)
3854 return ICE_ERR_MAX_LIMIT;
3858 if (!ice_is_vsi_valid(hw, vsi_handle))
3859 return ICE_ERR_PARAM;
3861 ice_acquire_lock(&pi->sched_lock);
3863 q_ctx = ice_get_lan_q_ctx(hw, vsi_handle, tc, q_handle);
3865 ice_debug(hw, ICE_DBG_SCHED, "Enaq: invalid queue handle %d\n",
3867 status = ICE_ERR_PARAM;
3871 /* find a parent node */
3872 parent = ice_sched_get_free_qparent(pi, vsi_handle, tc,
3873 ICE_SCHED_NODE_OWNER_LAN);
3875 status = ICE_ERR_PARAM;
3879 buf->parent_teid = parent->info.node_teid;
3880 node.parent_teid = parent->info.node_teid;
3881 /* Mark that the values in the "generic" section as valid. The default
3882 * value in the "generic" section is zero. This means that :
3883 * - Scheduling mode is Bytes Per Second (BPS), indicated by Bit 0.
3884 * - 0 priority among siblings, indicated by Bit 1-3.
3885 * - WFQ, indicated by Bit 4.
3886 * - 0 Adjustment value is used in PSM credit update flow, indicated by
3888 * - Bit 7 is reserved.
3889 * Without setting the generic section as valid in valid_sections, the
3890 * Admin queue command will fail with error code ICE_AQ_RC_EINVAL.
3892 buf->txqs[0].info.valid_sections = ICE_AQC_ELEM_VALID_GENERIC;
3894 /* add the LAN queue */
3895 status = ice_aq_add_lan_txq(hw, num_qgrps, buf, buf_size, cd);
3896 if (status != ICE_SUCCESS) {
3897 ice_debug(hw, ICE_DBG_SCHED, "enable queue %d failed %d\n",
3898 LE16_TO_CPU(buf->txqs[0].txq_id),
3899 hw->adminq.sq_last_status);
3903 node.node_teid = buf->txqs[0].q_teid;
3904 node.data.elem_type = ICE_AQC_ELEM_TYPE_LEAF;
3905 q_ctx->q_handle = q_handle;
3906 q_ctx->q_teid = LE32_TO_CPU(node.node_teid);
3908 /* add a leaf node into scheduler tree queue layer */
3909 status = ice_sched_add_node(pi, hw->num_tx_sched_layers - 1, &node);
3911 status = ice_sched_replay_q_bw(pi, q_ctx);
3914 ice_release_lock(&pi->sched_lock);
3920 * @pi: port information structure
3921 * @vsi_handle: software VSI handle
3923 * @num_queues: number of queues
3924 * @q_handles: pointer to software queue handle array
3925 * @q_ids: pointer to the q_id array
3926 * @q_teids: pointer to queue node teids
3927 * @rst_src: if called due to reset, specifies the reset source
3928 * @vmvf_num: the relative VM or VF number that is undergoing the reset
3929 * @cd: pointer to command details structure or NULL
3931 * This function removes queues and their corresponding nodes in SW DB
3934 ice_dis_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u8 num_queues,
3935 u16 *q_handles, u16 *q_ids, u32 *q_teids,
3936 enum ice_disq_rst_src rst_src, u16 vmvf_num,
3937 struct ice_sq_cd *cd)
3939 enum ice_status status = ICE_ERR_DOES_NOT_EXIST;
3940 struct ice_aqc_dis_txq_item qg_list;
3941 struct ice_q_ctx *q_ctx;
3944 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY)
3948 /* if queue is disabled already yet the disable queue command
3949 * has to be sent to complete the VF reset, then call
3950 * ice_aq_dis_lan_txq without any queue information
3953 return ice_aq_dis_lan_txq(pi->hw, 0, NULL, 0, rst_src,
3958 ice_acquire_lock(&pi->sched_lock);
3960 for (i = 0; i < num_queues; i++) {
3961 struct ice_sched_node *node;
3963 node = ice_sched_find_node_by_teid(pi->root, q_teids[i]);
3966 q_ctx = ice_get_lan_q_ctx(pi->hw, vsi_handle, tc, q_handles[i]);
3968 ice_debug(pi->hw, ICE_DBG_SCHED, "invalid queue handle%d\n",
3972 if (q_ctx->q_handle != q_handles[i]) {
3973 ice_debug(pi->hw, ICE_DBG_SCHED, "Err:handles %d %d\n",
3974 q_ctx->q_handle, q_handles[i]);
3977 qg_list.parent_teid = node->info.parent_teid;
3979 qg_list.q_id[0] = CPU_TO_LE16(q_ids[i]);
3980 status = ice_aq_dis_lan_txq(pi->hw, 1, &qg_list,
3981 sizeof(qg_list), rst_src, vmvf_num,
3984 if (status != ICE_SUCCESS)
3986 ice_free_sched_node(pi, node);
3987 q_ctx->q_handle = ICE_INVAL_Q_HANDLE;
3989 ice_release_lock(&pi->sched_lock);
3994 * ice_cfg_vsi_qs - configure the new/existing VSI queues
3995 * @pi: port information structure
3996 * @vsi_handle: software VSI handle
3997 * @tc_bitmap: TC bitmap
3998 * @maxqs: max queues array per TC
3999 * @owner: LAN or RDMA
4001 * This function adds/updates the VSI queues per TC.
4003 static enum ice_status
4004 ice_cfg_vsi_qs(struct ice_port_info *pi, u16 vsi_handle, u8 tc_bitmap,
4005 u16 *maxqs, u8 owner)
4007 enum ice_status status = ICE_SUCCESS;
4010 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY)
4013 if (!ice_is_vsi_valid(pi->hw, vsi_handle))
4014 return ICE_ERR_PARAM;
4016 ice_acquire_lock(&pi->sched_lock);
4018 ice_for_each_traffic_class(i) {
4019 /* configuration is possible only if TC node is present */
4020 if (!ice_sched_get_tc_node(pi, i))
4023 status = ice_sched_cfg_vsi(pi, vsi_handle, i, maxqs[i], owner,
4024 ice_is_tc_ena(tc_bitmap, i));
4029 ice_release_lock(&pi->sched_lock);
4034 * ice_cfg_vsi_lan - configure VSI LAN queues
4035 * @pi: port information structure
4036 * @vsi_handle: software VSI handle
4037 * @tc_bitmap: TC bitmap
4038 * @max_lanqs: max LAN queues array per TC
4040 * This function adds/updates the VSI LAN queues per TC.
4043 ice_cfg_vsi_lan(struct ice_port_info *pi, u16 vsi_handle, u8 tc_bitmap,
4046 return ice_cfg_vsi_qs(pi, vsi_handle, tc_bitmap, max_lanqs,
4047 ICE_SCHED_NODE_OWNER_LAN);
4053 * ice_replay_pre_init - replay pre initialization
4054 * @hw: pointer to the HW struct
4056 * Initializes required config data for VSI, FD, ACL, and RSS before replay.
4058 static enum ice_status ice_replay_pre_init(struct ice_hw *hw)
4060 struct ice_switch_info *sw = hw->switch_info;
4063 /* Delete old entries from replay filter list head if there is any */
4064 ice_rm_all_sw_replay_rule_info(hw);
4065 /* In start of replay, move entries into replay_rules list, it
4066 * will allow adding rules entries back to filt_rules list,
4067 * which is operational list.
4069 for (i = 0; i < ICE_MAX_NUM_RECIPES; i++)
4070 LIST_REPLACE_INIT(&sw->recp_list[i].filt_rules,
4071 &sw->recp_list[i].filt_replay_rules);
4072 ice_sched_replay_agg_vsi_preinit(hw);
4074 return ice_sched_replay_tc_node_bw(hw->port_info);
4078 * ice_replay_vsi - replay VSI configuration
4079 * @hw: pointer to the HW struct
4080 * @vsi_handle: driver VSI handle
4082 * Restore all VSI configuration after reset. It is required to call this
4083 * function with main VSI first.
4085 enum ice_status ice_replay_vsi(struct ice_hw *hw, u16 vsi_handle)
4087 enum ice_status status;
4089 if (!ice_is_vsi_valid(hw, vsi_handle))
4090 return ICE_ERR_PARAM;
4092 /* Replay pre-initialization if there is any */
4093 if (vsi_handle == ICE_MAIN_VSI_HANDLE) {
4094 status = ice_replay_pre_init(hw);
4098 /* Replay per VSI all RSS configurations */
4099 status = ice_replay_rss_cfg(hw, vsi_handle);
4102 /* Replay per VSI all filters */
4103 status = ice_replay_vsi_all_fltr(hw, vsi_handle);
4105 status = ice_replay_vsi_agg(hw, vsi_handle);
4110 * ice_replay_post - post replay configuration cleanup
4111 * @hw: pointer to the HW struct
4113 * Post replay cleanup.
4115 void ice_replay_post(struct ice_hw *hw)
4117 /* Delete old entries from replay filter list head */
4118 ice_rm_all_sw_replay_rule_info(hw);
4119 ice_sched_replay_agg(hw);
4123 * ice_stat_update40 - read 40 bit stat from the chip and update stat values
4124 * @hw: ptr to the hardware info
4125 * @reg: offset of 64 bit HW register to read from
4126 * @prev_stat_loaded: bool to specify if previous stats are loaded
4127 * @prev_stat: ptr to previous loaded stat value
4128 * @cur_stat: ptr to current stat value
4131 ice_stat_update40(struct ice_hw *hw, u32 reg, bool prev_stat_loaded,
4132 u64 *prev_stat, u64 *cur_stat)
4134 u64 new_data = rd64(hw, reg) & (BIT_ULL(40) - 1);
4136 /* device stats are not reset at PFR, they likely will not be zeroed
4137 * when the driver starts. Thus, save the value from the first read
4138 * without adding to the statistic value so that we report stats which
4139 * count up from zero.
4141 if (!prev_stat_loaded) {
4142 *prev_stat = new_data;
4146 /* Calculate the difference between the new and old values, and then
4147 * add it to the software stat value.
4149 if (new_data >= *prev_stat)
4150 *cur_stat += new_data - *prev_stat;
4152 /* to manage the potential roll-over */
4153 *cur_stat += (new_data + BIT_ULL(40)) - *prev_stat;
4155 /* Update the previously stored value to prepare for next read */
4156 *prev_stat = new_data;
4160 * ice_stat_update32 - read 32 bit stat from the chip and update stat values
4161 * @hw: ptr to the hardware info
4162 * @reg: offset of HW register to read from
4163 * @prev_stat_loaded: bool to specify if previous stats are loaded
4164 * @prev_stat: ptr to previous loaded stat value
4165 * @cur_stat: ptr to current stat value
4168 ice_stat_update32(struct ice_hw *hw, u32 reg, bool prev_stat_loaded,
4169 u64 *prev_stat, u64 *cur_stat)
4173 new_data = rd32(hw, reg);
4175 /* device stats are not reset at PFR, they likely will not be zeroed
4176 * when the driver starts. Thus, save the value from the first read
4177 * without adding to the statistic value so that we report stats which
4178 * count up from zero.
4180 if (!prev_stat_loaded) {
4181 *prev_stat = new_data;
4185 /* Calculate the difference between the new and old values, and then
4186 * add it to the software stat value.
4188 if (new_data >= *prev_stat)
4189 *cur_stat += new_data - *prev_stat;
4191 /* to manage the potential roll-over */
4192 *cur_stat += (new_data + BIT_ULL(32)) - *prev_stat;
4194 /* Update the previously stored value to prepare for next read */
4195 *prev_stat = new_data;
4199 * ice_stat_update_repc - read GLV_REPC stats from chip and update stat values
4200 * @hw: ptr to the hardware info
4201 * @vsi_handle: VSI handle
4202 * @prev_stat_loaded: bool to specify if the previous stat values are loaded
4203 * @cur_stats: ptr to current stats structure
4205 * The GLV_REPC statistic register actually tracks two 16bit statistics, and
4206 * thus cannot be read using the normal ice_stat_update32 function.
4208 * Read the GLV_REPC register associated with the given VSI, and update the
4209 * rx_no_desc and rx_error values in the ice_eth_stats structure.
4211 * Because the statistics in GLV_REPC stick at 0xFFFF, the register must be
4212 * cleared each time it's read.
4214 * Note that the GLV_RDPC register also counts the causes that would trigger
4215 * GLV_REPC. However, it does not give the finer grained detail about why the
4216 * packets are being dropped. The GLV_REPC values can be used to distinguish
4217 * whether Rx packets are dropped due to errors or due to no available
4221 ice_stat_update_repc(struct ice_hw *hw, u16 vsi_handle, bool prev_stat_loaded,
4222 struct ice_eth_stats *cur_stats)
4224 u16 vsi_num, no_desc, error_cnt;
4227 if (!ice_is_vsi_valid(hw, vsi_handle))
4230 vsi_num = ice_get_hw_vsi_num(hw, vsi_handle);
4232 /* If we haven't loaded stats yet, just clear the current value */
4233 if (!prev_stat_loaded) {
4234 wr32(hw, GLV_REPC(vsi_num), 0);
4238 repc = rd32(hw, GLV_REPC(vsi_num));
4239 no_desc = (repc & GLV_REPC_NO_DESC_CNT_M) >> GLV_REPC_NO_DESC_CNT_S;
4240 error_cnt = (repc & GLV_REPC_ERROR_CNT_M) >> GLV_REPC_ERROR_CNT_S;
4242 /* Clear the count by writing to the stats register */
4243 wr32(hw, GLV_REPC(vsi_num), 0);
4245 cur_stats->rx_no_desc += no_desc;
4246 cur_stats->rx_errors += error_cnt;
4251 * ice_sched_query_elem - query element information from HW
4252 * @hw: pointer to the HW struct
4253 * @node_teid: node TEID to be queried
4254 * @buf: buffer to element information
4256 * This function queries HW element information
4259 ice_sched_query_elem(struct ice_hw *hw, u32 node_teid,
4260 struct ice_aqc_get_elem *buf)
4262 u16 buf_size, num_elem_ret = 0;
4263 enum ice_status status;
4265 buf_size = sizeof(*buf);
4266 ice_memset(buf, 0, buf_size, ICE_NONDMA_MEM);
4267 buf->generic[0].node_teid = CPU_TO_LE32(node_teid);
4268 status = ice_aq_query_sched_elems(hw, 1, buf, buf_size, &num_elem_ret,
4270 if (status != ICE_SUCCESS || num_elem_ret != 1)
4271 ice_debug(hw, ICE_DBG_SCHED, "query element failed\n");
4276 * ice_get_fw_mode - returns FW mode
4277 * @hw: pointer to the HW struct
4279 enum ice_fw_modes ice_get_fw_mode(struct ice_hw *hw)
4281 #define ICE_FW_MODE_DBG_M BIT(0)
4282 #define ICE_FW_MODE_REC_M BIT(1)
4283 #define ICE_FW_MODE_ROLLBACK_M BIT(2)
4286 /* check the current FW mode */
4287 fw_mode = rd32(hw, GL_MNG_FWSM) & GL_MNG_FWSM_FW_MODES_M;
4289 if (fw_mode & ICE_FW_MODE_DBG_M)
4290 return ICE_FW_MODE_DBG;
4291 else if (fw_mode & ICE_FW_MODE_REC_M)
4292 return ICE_FW_MODE_REC;
4293 else if (fw_mode & ICE_FW_MODE_ROLLBACK_M)
4294 return ICE_FW_MODE_ROLLBACK;
4296 return ICE_FW_MODE_NORMAL;