1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2001-2018
5 #include "ice_common.h"
7 #include "ice_adminq_cmd.h"
10 #include "ice_switch.h"
12 #define ICE_PF_RESET_WAIT_COUNT 200
14 #define ICE_PROG_FLEX_ENTRY(hw, rxdid, mdid, idx) \
15 wr32((hw), GLFLXP_RXDID_FLX_WRD_##idx(rxdid), \
16 ((ICE_RX_OPC_MDID << \
17 GLFLXP_RXDID_FLX_WRD_##idx##_RXDID_OPCODE_S) & \
18 GLFLXP_RXDID_FLX_WRD_##idx##_RXDID_OPCODE_M) | \
19 (((mdid) << GLFLXP_RXDID_FLX_WRD_##idx##_PROT_MDID_S) & \
20 GLFLXP_RXDID_FLX_WRD_##idx##_PROT_MDID_M))
22 #define ICE_PROG_FLG_ENTRY(hw, rxdid, flg_0, flg_1, flg_2, flg_3, idx) \
23 wr32((hw), GLFLXP_RXDID_FLAGS(rxdid, idx), \
24 (((flg_0) << GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_S) & \
25 GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_M) | \
26 (((flg_1) << GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_1_S) & \
27 GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_1_M) | \
28 (((flg_2) << GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_2_S) & \
29 GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_2_M) | \
30 (((flg_3) << GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_3_S) & \
31 GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_3_M))
35 * ice_set_mac_type - Sets MAC type
36 * @hw: pointer to the HW structure
38 * This function sets the MAC type of the adapter based on the
39 * vendor ID and device ID stored in the hw structure.
41 static enum ice_status ice_set_mac_type(struct ice_hw *hw)
43 enum ice_status status = ICE_SUCCESS;
45 ice_debug(hw, ICE_DBG_TRACE, "ice_set_mac_type\n");
47 if (hw->vendor_id == ICE_INTEL_VENDOR_ID) {
48 switch (hw->device_id) {
50 hw->mac_type = ICE_MAC_GENERIC;
54 status = ICE_ERR_DEVICE_NOT_SUPPORTED;
57 ice_debug(hw, ICE_DBG_INIT, "found mac_type: %d, status: %d\n",
58 hw->mac_type, status);
65 * ice_clear_pf_cfg - Clear PF configuration
66 * @hw: pointer to the hardware structure
68 * Clears any existing PF configuration (VSIs, VSI lists, switch rules, port
69 * configuration, flow director filters, etc.).
71 enum ice_status ice_clear_pf_cfg(struct ice_hw *hw)
73 struct ice_aq_desc desc;
75 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pf_cfg);
77 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
81 * ice_aq_manage_mac_read - manage MAC address read command
82 * @hw: pointer to the hw struct
83 * @buf: a virtual buffer to hold the manage MAC read response
84 * @buf_size: Size of the virtual buffer
85 * @cd: pointer to command details structure or NULL
87 * This function is used to return per PF station MAC address (0x0107).
88 * NOTE: Upon successful completion of this command, MAC address information
89 * is returned in user specified buffer. Please interpret user specified
90 * buffer as "manage_mac_read" response.
91 * Response such as various MAC addresses are stored in HW struct (port.mac)
92 * ice_aq_discover_caps is expected to be called before this function is called.
94 static enum ice_status
95 ice_aq_manage_mac_read(struct ice_hw *hw, void *buf, u16 buf_size,
98 struct ice_aqc_manage_mac_read_resp *resp;
99 struct ice_aqc_manage_mac_read *cmd;
100 struct ice_aq_desc desc;
101 enum ice_status status;
105 cmd = &desc.params.mac_read;
107 if (buf_size < sizeof(*resp))
108 return ICE_ERR_BUF_TOO_SHORT;
110 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_read);
112 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);
116 resp = (struct ice_aqc_manage_mac_read_resp *)buf;
117 flags = LE16_TO_CPU(cmd->flags) & ICE_AQC_MAN_MAC_READ_M;
119 if (!(flags & ICE_AQC_MAN_MAC_LAN_ADDR_VALID)) {
120 ice_debug(hw, ICE_DBG_LAN, "got invalid MAC address\n");
124 /* A single port can report up to two (LAN and WoL) addresses */
125 for (i = 0; i < cmd->num_addr; i++)
126 if (resp[i].addr_type == ICE_AQC_MAN_MAC_ADDR_TYPE_LAN) {
127 ice_memcpy(hw->port_info->mac.lan_addr,
128 resp[i].mac_addr, ETH_ALEN,
130 ice_memcpy(hw->port_info->mac.perm_addr,
132 ETH_ALEN, ICE_DMA_TO_NONDMA);
140 * ice_aq_get_phy_caps - returns PHY capabilities
141 * @pi: port information structure
142 * @qual_mods: report qualified modules
143 * @report_mode: report mode capabilities
144 * @pcaps: structure for PHY capabilities to be filled
145 * @cd: pointer to command details structure or NULL
147 * Returns the various PHY capabilities supported on the Port (0x0600)
150 ice_aq_get_phy_caps(struct ice_port_info *pi, bool qual_mods, u8 report_mode,
151 struct ice_aqc_get_phy_caps_data *pcaps,
152 struct ice_sq_cd *cd)
154 struct ice_aqc_get_phy_caps *cmd;
155 u16 pcaps_size = sizeof(*pcaps);
156 struct ice_aq_desc desc;
157 enum ice_status status;
159 cmd = &desc.params.get_phy;
161 if (!pcaps || (report_mode & ~ICE_AQC_REPORT_MODE_M) || !pi)
162 return ICE_ERR_PARAM;
164 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_phy_caps);
167 cmd->param0 |= CPU_TO_LE16(ICE_AQC_GET_PHY_RQM);
169 cmd->param0 |= CPU_TO_LE16(report_mode);
170 status = ice_aq_send_cmd(pi->hw, &desc, pcaps, pcaps_size, cd);
172 if (status == ICE_SUCCESS && report_mode == ICE_AQC_REPORT_TOPO_CAP) {
173 pi->phy.phy_type_low = LE64_TO_CPU(pcaps->phy_type_low);
174 pi->phy.phy_type_high = LE64_TO_CPU(pcaps->phy_type_high);
181 * ice_get_media_type - Gets media type
182 * @pi: port information structure
184 static enum ice_media_type ice_get_media_type(struct ice_port_info *pi)
186 struct ice_link_status *hw_link_info;
189 return ICE_MEDIA_UNKNOWN;
191 hw_link_info = &pi->phy.link_info;
192 if (hw_link_info->phy_type_low && hw_link_info->phy_type_high)
193 /* If more than one media type is selected, report unknown */
194 return ICE_MEDIA_UNKNOWN;
196 if (hw_link_info->phy_type_low) {
197 switch (hw_link_info->phy_type_low) {
198 case ICE_PHY_TYPE_LOW_1000BASE_SX:
199 case ICE_PHY_TYPE_LOW_1000BASE_LX:
200 case ICE_PHY_TYPE_LOW_10GBASE_SR:
201 case ICE_PHY_TYPE_LOW_10GBASE_LR:
202 case ICE_PHY_TYPE_LOW_10G_SFI_C2C:
203 case ICE_PHY_TYPE_LOW_25GBASE_SR:
204 case ICE_PHY_TYPE_LOW_25GBASE_LR:
205 case ICE_PHY_TYPE_LOW_25G_AUI_C2C:
206 case ICE_PHY_TYPE_LOW_40GBASE_SR4:
207 case ICE_PHY_TYPE_LOW_40GBASE_LR4:
208 case ICE_PHY_TYPE_LOW_50GBASE_SR2:
209 case ICE_PHY_TYPE_LOW_50GBASE_LR2:
210 case ICE_PHY_TYPE_LOW_50GBASE_SR:
211 case ICE_PHY_TYPE_LOW_50GBASE_FR:
212 case ICE_PHY_TYPE_LOW_50GBASE_LR:
213 case ICE_PHY_TYPE_LOW_100GBASE_SR4:
214 case ICE_PHY_TYPE_LOW_100GBASE_LR4:
215 case ICE_PHY_TYPE_LOW_100GBASE_SR2:
216 case ICE_PHY_TYPE_LOW_100GBASE_DR:
217 return ICE_MEDIA_FIBER;
218 case ICE_PHY_TYPE_LOW_100BASE_TX:
219 case ICE_PHY_TYPE_LOW_1000BASE_T:
220 case ICE_PHY_TYPE_LOW_2500BASE_T:
221 case ICE_PHY_TYPE_LOW_5GBASE_T:
222 case ICE_PHY_TYPE_LOW_10GBASE_T:
223 case ICE_PHY_TYPE_LOW_25GBASE_T:
224 return ICE_MEDIA_BASET;
225 case ICE_PHY_TYPE_LOW_10G_SFI_DA:
226 case ICE_PHY_TYPE_LOW_25GBASE_CR:
227 case ICE_PHY_TYPE_LOW_25GBASE_CR_S:
228 case ICE_PHY_TYPE_LOW_25GBASE_CR1:
229 case ICE_PHY_TYPE_LOW_40GBASE_CR4:
230 case ICE_PHY_TYPE_LOW_50GBASE_CR2:
231 case ICE_PHY_TYPE_LOW_50GBASE_CP:
232 case ICE_PHY_TYPE_LOW_100GBASE_CR4:
233 case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4:
234 case ICE_PHY_TYPE_LOW_100GBASE_CP2:
236 case ICE_PHY_TYPE_LOW_1000BASE_KX:
237 case ICE_PHY_TYPE_LOW_2500BASE_KX:
238 case ICE_PHY_TYPE_LOW_2500BASE_X:
239 case ICE_PHY_TYPE_LOW_5GBASE_KR:
240 case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1:
241 case ICE_PHY_TYPE_LOW_25GBASE_KR:
242 case ICE_PHY_TYPE_LOW_25GBASE_KR1:
243 case ICE_PHY_TYPE_LOW_25GBASE_KR_S:
244 case ICE_PHY_TYPE_LOW_40GBASE_KR4:
245 case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4:
246 case ICE_PHY_TYPE_LOW_50GBASE_KR2:
247 case ICE_PHY_TYPE_LOW_100GBASE_KR4:
248 case ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4:
249 return ICE_MEDIA_BACKPLANE;
252 switch (hw_link_info->phy_type_high) {
253 case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4:
254 return ICE_MEDIA_BACKPLANE;
257 return ICE_MEDIA_UNKNOWN;
261 * ice_aq_get_link_info
262 * @pi: port information structure
263 * @ena_lse: enable/disable LinkStatusEvent reporting
264 * @link: pointer to link status structure - optional
265 * @cd: pointer to command details structure or NULL
267 * Get Link Status (0x607). Returns the link status of the adapter.
270 ice_aq_get_link_info(struct ice_port_info *pi, bool ena_lse,
271 struct ice_link_status *link, struct ice_sq_cd *cd)
273 struct ice_link_status *hw_link_info_old, *hw_link_info;
274 struct ice_aqc_get_link_status_data link_data = { 0 };
275 struct ice_aqc_get_link_status *resp;
276 enum ice_media_type *hw_media_type;
277 struct ice_fc_info *hw_fc_info;
278 bool tx_pause, rx_pause;
279 struct ice_aq_desc desc;
280 enum ice_status status;
284 return ICE_ERR_PARAM;
285 hw_link_info_old = &pi->phy.link_info_old;
286 hw_media_type = &pi->phy.media_type;
287 hw_link_info = &pi->phy.link_info;
288 hw_fc_info = &pi->fc;
290 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_status);
291 cmd_flags = (ena_lse) ? ICE_AQ_LSE_ENA : ICE_AQ_LSE_DIS;
292 resp = &desc.params.get_link_status;
293 resp->cmd_flags = CPU_TO_LE16(cmd_flags);
294 resp->lport_num = pi->lport;
296 status = ice_aq_send_cmd(pi->hw, &desc, &link_data, sizeof(link_data),
299 if (status != ICE_SUCCESS)
302 /* save off old link status information */
303 *hw_link_info_old = *hw_link_info;
305 /* update current link status information */
306 hw_link_info->link_speed = LE16_TO_CPU(link_data.link_speed);
307 hw_link_info->phy_type_low = LE64_TO_CPU(link_data.phy_type_low);
308 hw_link_info->phy_type_high = LE64_TO_CPU(link_data.phy_type_high);
309 *hw_media_type = ice_get_media_type(pi);
310 hw_link_info->link_info = link_data.link_info;
311 hw_link_info->an_info = link_data.an_info;
312 hw_link_info->ext_info = link_data.ext_info;
313 hw_link_info->max_frame_size = LE16_TO_CPU(link_data.max_frame_size);
314 hw_link_info->fec_info = link_data.cfg & ICE_AQ_FEC_MASK;
315 hw_link_info->topo_media_conflict = link_data.topo_media_conflict;
316 hw_link_info->pacing = link_data.cfg & ICE_AQ_CFG_PACING_M;
319 tx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_TX);
320 rx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_RX);
321 if (tx_pause && rx_pause)
322 hw_fc_info->current_mode = ICE_FC_FULL;
324 hw_fc_info->current_mode = ICE_FC_TX_PAUSE;
326 hw_fc_info->current_mode = ICE_FC_RX_PAUSE;
328 hw_fc_info->current_mode = ICE_FC_NONE;
330 hw_link_info->lse_ena =
331 !!(resp->cmd_flags & CPU_TO_LE16(ICE_AQ_LSE_IS_ENABLED));
334 /* save link status information */
336 *link = *hw_link_info;
338 /* flag cleared so calling functions don't call AQ again */
339 pi->phy.get_link_info = false;
345 * ice_init_flex_flags
346 * @hw: pointer to the hardware structure
347 * @prof_id: Rx Descriptor Builder profile ID
349 * Function to initialize Rx flex flags
351 static void ice_init_flex_flags(struct ice_hw *hw, enum ice_rxdid prof_id)
355 /* Flex-flag fields (0-2) are programmed with FLG64 bits with layout:
356 * flexiflags0[5:0] - TCP flags, is_packet_fragmented, is_packet_UDP_GRE
357 * flexiflags1[3:0] - Not used for flag programming
358 * flexiflags2[7:0] - Tunnel and VLAN types
359 * 2 invalid fields in last index
362 /* Rx flex flags are currently programmed for the NIC profiles only.
363 * Different flag bit programming configurations can be added per
366 case ICE_RXDID_FLEX_NIC:
367 case ICE_RXDID_FLEX_NIC_2:
368 ICE_PROG_FLG_ENTRY(hw, prof_id, ICE_RXFLG_PKT_FRG,
369 ICE_RXFLG_UDP_GRE, ICE_RXFLG_PKT_DSI,
370 ICE_RXFLG_FIN, idx++);
371 /* flex flag 1 is not used for flexi-flag programming, skipping
372 * these four FLG64 bits.
374 ICE_PROG_FLG_ENTRY(hw, prof_id, ICE_RXFLG_SYN, ICE_RXFLG_RST,
375 ICE_RXFLG_PKT_DSI, ICE_RXFLG_PKT_DSI, idx++);
376 ICE_PROG_FLG_ENTRY(hw, prof_id, ICE_RXFLG_PKT_DSI,
377 ICE_RXFLG_PKT_DSI, ICE_RXFLG_EVLAN_x8100,
378 ICE_RXFLG_EVLAN_x9100, idx++);
379 ICE_PROG_FLG_ENTRY(hw, prof_id, ICE_RXFLG_VLAN_x8100,
380 ICE_RXFLG_TNL_VLAN, ICE_RXFLG_TNL_MAC,
381 ICE_RXFLG_TNL0, idx++);
382 ICE_PROG_FLG_ENTRY(hw, prof_id, ICE_RXFLG_TNL1, ICE_RXFLG_TNL2,
383 ICE_RXFLG_PKT_DSI, ICE_RXFLG_PKT_DSI, idx);
387 ice_debug(hw, ICE_DBG_INIT,
388 "Flag programming for profile ID %d not supported\n",
395 * @hw: pointer to the hardware structure
396 * @prof_id: Rx Descriptor Builder profile ID
398 * Function to initialize flex descriptors
400 static void ice_init_flex_flds(struct ice_hw *hw, enum ice_rxdid prof_id)
402 enum ice_flex_rx_mdid mdid;
405 case ICE_RXDID_FLEX_NIC:
406 case ICE_RXDID_FLEX_NIC_2:
407 ICE_PROG_FLEX_ENTRY(hw, prof_id, ICE_RX_MDID_HASH_LOW, 0);
408 ICE_PROG_FLEX_ENTRY(hw, prof_id, ICE_RX_MDID_HASH_HIGH, 1);
409 ICE_PROG_FLEX_ENTRY(hw, prof_id, ICE_RX_MDID_FLOW_ID_LOWER, 2);
411 mdid = (prof_id == ICE_RXDID_FLEX_NIC_2) ?
412 ICE_RX_MDID_SRC_VSI : ICE_RX_MDID_FLOW_ID_HIGH;
414 ICE_PROG_FLEX_ENTRY(hw, prof_id, mdid, 3);
416 ice_init_flex_flags(hw, prof_id);
420 ice_debug(hw, ICE_DBG_INIT,
421 "Field init for profile ID %d not supported\n",
428 * ice_init_fltr_mgmt_struct - initializes filter management list and locks
429 * @hw: pointer to the hw struct
431 static enum ice_status ice_init_fltr_mgmt_struct(struct ice_hw *hw)
433 struct ice_switch_info *sw;
435 hw->switch_info = (struct ice_switch_info *)
436 ice_malloc(hw, sizeof(*hw->switch_info));
437 sw = hw->switch_info;
440 return ICE_ERR_NO_MEMORY;
442 INIT_LIST_HEAD(&sw->vsi_list_map_head);
444 return ice_init_def_sw_recp(hw);
448 * ice_cleanup_fltr_mgmt_struct - cleanup filter management list and locks
449 * @hw: pointer to the hw struct
451 static void ice_cleanup_fltr_mgmt_struct(struct ice_hw *hw)
453 struct ice_switch_info *sw = hw->switch_info;
454 struct ice_vsi_list_map_info *v_pos_map;
455 struct ice_vsi_list_map_info *v_tmp_map;
456 struct ice_sw_recipe *recps;
459 LIST_FOR_EACH_ENTRY_SAFE(v_pos_map, v_tmp_map, &sw->vsi_list_map_head,
460 ice_vsi_list_map_info, list_entry) {
461 LIST_DEL(&v_pos_map->list_entry);
462 ice_free(hw, v_pos_map);
464 recps = hw->switch_info->recp_list;
465 for (i = 0; i < ICE_MAX_NUM_RECIPES; i++) {
466 recps[i].root_rid = i;
468 if (recps[i].adv_rule) {
469 struct ice_adv_fltr_mgmt_list_entry *tmp_entry;
470 struct ice_adv_fltr_mgmt_list_entry *lst_itr;
472 ice_destroy_lock(&recps[i].filt_rule_lock);
473 LIST_FOR_EACH_ENTRY_SAFE(lst_itr, tmp_entry,
474 &recps[i].filt_rules,
475 ice_adv_fltr_mgmt_list_entry,
477 LIST_DEL(&lst_itr->list_entry);
478 ice_free(hw, lst_itr->lkups);
479 ice_free(hw, lst_itr);
482 struct ice_fltr_mgmt_list_entry *lst_itr, *tmp_entry;
484 ice_destroy_lock(&recps[i].filt_rule_lock);
485 LIST_FOR_EACH_ENTRY_SAFE(lst_itr, tmp_entry,
486 &recps[i].filt_rules,
487 ice_fltr_mgmt_list_entry,
489 LIST_DEL(&lst_itr->list_entry);
490 ice_free(hw, lst_itr);
494 ice_rm_all_sw_replay_rule_info(hw);
495 ice_free(hw, sw->recp_list);
499 #define ICE_FW_LOG_DESC_SIZE(n) (sizeof(struct ice_aqc_fw_logging_data) + \
500 (((n) - 1) * sizeof(((struct ice_aqc_fw_logging_data *)0)->entry)))
501 #define ICE_FW_LOG_DESC_SIZE_MAX \
502 ICE_FW_LOG_DESC_SIZE(ICE_AQC_FW_LOG_ID_MAX)
505 * ice_cfg_fw_log - configure FW logging
506 * @hw: pointer to the hw struct
507 * @enable: enable certain FW logging events if true, disable all if false
509 * This function enables/disables the FW logging via Rx CQ events and a UART
510 * port based on predetermined configurations. FW logging via the Rx CQ can be
511 * enabled/disabled for individual PF's. However, FW logging via the UART can
512 * only be enabled/disabled for all PFs on the same device.
514 * To enable overall FW logging, the "cq_en" and "uart_en" enable bits in
515 * hw->fw_log need to be set accordingly, e.g. based on user-provided input,
516 * before initializing the device.
518 * When re/configuring FW logging, callers need to update the "cfg" elements of
519 * the hw->fw_log.evnts array with the desired logging event configurations for
520 * modules of interest. When disabling FW logging completely, the callers can
521 * just pass false in the "enable" parameter. On completion, the function will
522 * update the "cur" element of the hw->fw_log.evnts array with the resulting
523 * logging event configurations of the modules that are being re/configured. FW
524 * logging modules that are not part of a reconfiguration operation retain their
527 * Before resetting the device, it is recommended that the driver disables FW
528 * logging before shutting down the control queue. When disabling FW logging
529 * ("enable" = false), the latest configurations of FW logging events stored in
530 * hw->fw_log.evnts[] are not overridden to allow them to be reconfigured after
533 * When enabling FW logging to emit log messages via the Rx CQ during the
534 * device's initialization phase, a mechanism alternative to interrupt handlers
535 * needs to be used to extract FW log messages from the Rx CQ periodically and
536 * to prevent the Rx CQ from being full and stalling other types of control
537 * messages from FW to SW. Interrupts are typically disabled during the device's
538 * initialization phase.
540 static enum ice_status ice_cfg_fw_log(struct ice_hw *hw, bool enable)
542 struct ice_aqc_fw_logging_data *data = NULL;
543 struct ice_aqc_fw_logging *cmd;
544 enum ice_status status = ICE_SUCCESS;
545 u16 i, chgs = 0, len = 0;
546 struct ice_aq_desc desc;
550 if (!hw->fw_log.cq_en && !hw->fw_log.uart_en)
553 /* Disable FW logging only when the control queue is still responsive */
555 (!hw->fw_log.actv_evnts || !ice_check_sq_alive(hw, &hw->adminq)))
558 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_fw_logging);
559 cmd = &desc.params.fw_logging;
561 /* Indicate which controls are valid */
562 if (hw->fw_log.cq_en)
563 cmd->log_ctrl_valid |= ICE_AQC_FW_LOG_AQ_VALID;
565 if (hw->fw_log.uart_en)
566 cmd->log_ctrl_valid |= ICE_AQC_FW_LOG_UART_VALID;
569 /* Fill in an array of entries with FW logging modules and
570 * logging events being reconfigured.
572 for (i = 0; i < ICE_AQC_FW_LOG_ID_MAX; i++) {
575 /* Keep track of enabled event types */
576 actv_evnts |= hw->fw_log.evnts[i].cfg;
578 if (hw->fw_log.evnts[i].cfg == hw->fw_log.evnts[i].cur)
582 data = (struct ice_aqc_fw_logging_data *)
584 ICE_FW_LOG_DESC_SIZE_MAX);
586 return ICE_ERR_NO_MEMORY;
589 val = i << ICE_AQC_FW_LOG_ID_S;
590 val |= hw->fw_log.evnts[i].cfg << ICE_AQC_FW_LOG_EN_S;
591 data->entry[chgs++] = CPU_TO_LE16(val);
594 /* Only enable FW logging if at least one module is specified.
595 * If FW logging is currently enabled but all modules are not
596 * enabled to emit log messages, disable FW logging altogether.
599 /* Leave if there is effectively no change */
603 if (hw->fw_log.cq_en)
604 cmd->log_ctrl |= ICE_AQC_FW_LOG_AQ_EN;
606 if (hw->fw_log.uart_en)
607 cmd->log_ctrl |= ICE_AQC_FW_LOG_UART_EN;
610 len = ICE_FW_LOG_DESC_SIZE(chgs);
611 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
615 status = ice_aq_send_cmd(hw, &desc, buf, len, NULL);
617 /* Update the current configuration to reflect events enabled.
618 * hw->fw_log.cq_en and hw->fw_log.uart_en indicate if the FW
619 * logging mode is enabled for the device. They do not reflect
620 * actual modules being enabled to emit log messages. So, their
621 * values remain unchanged even when all modules are disabled.
623 u16 cnt = enable ? chgs : (u16)ICE_AQC_FW_LOG_ID_MAX;
625 hw->fw_log.actv_evnts = actv_evnts;
626 for (i = 0; i < cnt; i++) {
630 /* When disabling all FW logging events as part
631 * of device's de-initialization, the original
632 * configurations are retained, and can be used
633 * to reconfigure FW logging later if the device
636 hw->fw_log.evnts[i].cur = 0;
640 v = LE16_TO_CPU(data->entry[i]);
641 m = (v & ICE_AQC_FW_LOG_ID_M) >> ICE_AQC_FW_LOG_ID_S;
642 hw->fw_log.evnts[m].cur = hw->fw_log.evnts[m].cfg;
655 * @hw: pointer to the hw struct
656 * @desc: pointer to the AQ message descriptor
657 * @buf: pointer to the buffer accompanying the AQ message
659 * Formats a FW Log message and outputs it via the standard driver logs.
661 void ice_output_fw_log(struct ice_hw *hw, struct ice_aq_desc *desc, void *buf)
663 ice_debug(hw, ICE_DBG_AQ_MSG, "[ FW Log Msg Start ]\n");
664 ice_debug_array(hw, ICE_DBG_AQ_MSG, 16, 1, (u8 *)buf,
665 LE16_TO_CPU(desc->datalen));
666 ice_debug(hw, ICE_DBG_AQ_MSG, "[ FW Log Msg End ]\n");
670 * ice_get_itr_intrl_gran - determine int/intrl granularity
671 * @hw: pointer to the hw struct
673 * Determines the itr/intrl granularities based on the maximum aggregate
674 * bandwidth according to the device's configuration during power-on.
676 static enum ice_status ice_get_itr_intrl_gran(struct ice_hw *hw)
678 u8 max_agg_bw = (rd32(hw, GL_PWR_MODE_CTL) &
679 GL_PWR_MODE_CTL_CAR_MAX_BW_M) >>
680 GL_PWR_MODE_CTL_CAR_MAX_BW_S;
682 switch (max_agg_bw) {
683 case ICE_MAX_AGG_BW_200G:
684 case ICE_MAX_AGG_BW_100G:
685 case ICE_MAX_AGG_BW_50G:
686 hw->itr_gran = ICE_ITR_GRAN_ABOVE_25;
687 hw->intrl_gran = ICE_INTRL_GRAN_ABOVE_25;
689 case ICE_MAX_AGG_BW_25G:
690 hw->itr_gran = ICE_ITR_GRAN_MAX_25;
691 hw->intrl_gran = ICE_INTRL_GRAN_MAX_25;
694 ice_debug(hw, ICE_DBG_INIT,
695 "Failed to determine itr/intrl granularity\n");
703 * ice_init_hw - main hardware initialization routine
704 * @hw: pointer to the hardware structure
706 enum ice_status ice_init_hw(struct ice_hw *hw)
708 struct ice_aqc_get_phy_caps_data *pcaps;
709 enum ice_status status;
713 ice_debug(hw, ICE_DBG_TRACE, "ice_init_hw");
716 /* Set MAC type based on DeviceID */
717 status = ice_set_mac_type(hw);
721 hw->pf_id = (u8)(rd32(hw, PF_FUNC_RID) &
722 PF_FUNC_RID_FUNCTION_NUMBER_M) >>
723 PF_FUNC_RID_FUNCTION_NUMBER_S;
726 status = ice_reset(hw, ICE_RESET_PFR);
730 status = ice_get_itr_intrl_gran(hw);
735 status = ice_init_all_ctrlq(hw);
737 goto err_unroll_cqinit;
739 /* Enable FW logging. Not fatal if this fails. */
740 status = ice_cfg_fw_log(hw, true);
742 ice_debug(hw, ICE_DBG_INIT, "Failed to enable FW logging.\n");
744 status = ice_clear_pf_cfg(hw);
746 goto err_unroll_cqinit;
749 ice_clear_pxe_mode(hw);
751 status = ice_init_nvm(hw);
753 goto err_unroll_cqinit;
755 status = ice_get_caps(hw);
757 goto err_unroll_cqinit;
759 hw->port_info = (struct ice_port_info *)
760 ice_malloc(hw, sizeof(*hw->port_info));
761 if (!hw->port_info) {
762 status = ICE_ERR_NO_MEMORY;
763 goto err_unroll_cqinit;
766 /* set the back pointer to hw */
767 hw->port_info->hw = hw;
769 /* Initialize port_info struct with switch configuration data */
770 status = ice_get_initial_sw_cfg(hw);
772 goto err_unroll_alloc;
776 /* Query the allocated resources for Tx scheduler */
777 status = ice_sched_query_res_alloc(hw);
779 ice_debug(hw, ICE_DBG_SCHED,
780 "Failed to get scheduler allocated resources\n");
781 goto err_unroll_alloc;
785 /* Initialize port_info struct with scheduler data */
786 status = ice_sched_init_port(hw->port_info);
788 goto err_unroll_sched;
790 pcaps = (struct ice_aqc_get_phy_caps_data *)
791 ice_malloc(hw, sizeof(*pcaps));
793 status = ICE_ERR_NO_MEMORY;
794 goto err_unroll_sched;
797 /* Initialize port_info struct with PHY capabilities */
798 status = ice_aq_get_phy_caps(hw->port_info, false,
799 ICE_AQC_REPORT_TOPO_CAP, pcaps, NULL);
802 goto err_unroll_sched;
804 /* Initialize port_info struct with link information */
805 status = ice_aq_get_link_info(hw->port_info, false, NULL, NULL);
807 goto err_unroll_sched;
808 /* need a valid SW entry point to build a Tx tree */
809 if (!hw->sw_entry_point_layer) {
810 ice_debug(hw, ICE_DBG_SCHED, "invalid sw entry point\n");
811 status = ICE_ERR_CFG;
812 goto err_unroll_sched;
814 INIT_LIST_HEAD(&hw->agg_list);
815 /* Initialize max burst size */
816 if (!hw->max_burst_size)
817 ice_cfg_rl_burst_size(hw, ICE_SCHED_DFLT_BURST_SIZE);
819 status = ice_init_fltr_mgmt_struct(hw);
821 goto err_unroll_sched;
824 /* Get MAC information */
825 /* A single port can report up to two (LAN and WoL) addresses */
826 mac_buf = ice_calloc(hw, 2,
827 sizeof(struct ice_aqc_manage_mac_read_resp));
828 mac_buf_len = 2 * sizeof(struct ice_aqc_manage_mac_read_resp);
831 status = ICE_ERR_NO_MEMORY;
832 goto err_unroll_fltr_mgmt_struct;
835 status = ice_aq_manage_mac_read(hw, mac_buf, mac_buf_len, NULL);
836 ice_free(hw, mac_buf);
839 goto err_unroll_fltr_mgmt_struct;
841 ice_init_flex_flds(hw, ICE_RXDID_FLEX_NIC);
842 ice_init_flex_flds(hw, ICE_RXDID_FLEX_NIC_2);
847 err_unroll_fltr_mgmt_struct:
848 ice_cleanup_fltr_mgmt_struct(hw);
850 ice_sched_cleanup_all(hw);
852 ice_free(hw, hw->port_info);
853 hw->port_info = NULL;
855 ice_shutdown_all_ctrlq(hw);
860 * ice_deinit_hw - unroll initialization operations done by ice_init_hw
861 * @hw: pointer to the hardware structure
863 * This should be called only during nominal operation, not as a result of
864 * ice_init_hw() failing since ice_init_hw() will take care of unrolling
865 * applicable initializations if it fails for any reason.
867 void ice_deinit_hw(struct ice_hw *hw)
869 ice_cleanup_fltr_mgmt_struct(hw);
871 ice_sched_cleanup_all(hw);
872 ice_sched_clear_agg(hw);
875 ice_free(hw, hw->port_info);
876 hw->port_info = NULL;
879 /* Attempt to disable FW logging before shutting down control queues */
880 ice_cfg_fw_log(hw, false);
881 ice_shutdown_all_ctrlq(hw);
883 /* Clear VSI contexts if not already cleared */
884 ice_clear_all_vsi_ctx(hw);
888 * ice_check_reset - Check to see if a global reset is complete
889 * @hw: pointer to the hardware structure
891 enum ice_status ice_check_reset(struct ice_hw *hw)
893 u32 cnt, reg = 0, grst_delay;
895 /* Poll for Device Active state in case a recent CORER, GLOBR,
896 * or EMPR has occurred. The grst delay value is in 100ms units.
897 * Add 1sec for outstanding AQ commands that can take a long time.
899 #define GLGEN_RSTCTL 0x000B8180 /* Reset Source: POR */
900 #define GLGEN_RSTCTL_GRSTDEL_S 0
901 #define GLGEN_RSTCTL_GRSTDEL_M MAKEMASK(0x3F, GLGEN_RSTCTL_GRSTDEL_S)
902 grst_delay = ((rd32(hw, GLGEN_RSTCTL) & GLGEN_RSTCTL_GRSTDEL_M) >>
903 GLGEN_RSTCTL_GRSTDEL_S) + 10;
905 for (cnt = 0; cnt < grst_delay; cnt++) {
906 ice_msec_delay(100, true);
907 reg = rd32(hw, GLGEN_RSTAT);
908 if (!(reg & GLGEN_RSTAT_DEVSTATE_M))
912 if (cnt == grst_delay) {
913 ice_debug(hw, ICE_DBG_INIT,
914 "Global reset polling failed to complete.\n");
915 return ICE_ERR_RESET_FAILED;
918 #define ICE_RESET_DONE_MASK (GLNVM_ULD_CORER_DONE_M | \
919 GLNVM_ULD_GLOBR_DONE_M)
921 /* Device is Active; check Global Reset processes are done */
922 for (cnt = 0; cnt < ICE_PF_RESET_WAIT_COUNT; cnt++) {
923 reg = rd32(hw, GLNVM_ULD) & ICE_RESET_DONE_MASK;
924 if (reg == ICE_RESET_DONE_MASK) {
925 ice_debug(hw, ICE_DBG_INIT,
926 "Global reset processes done. %d\n", cnt);
929 ice_msec_delay(10, true);
932 if (cnt == ICE_PF_RESET_WAIT_COUNT) {
933 ice_debug(hw, ICE_DBG_INIT,
934 "Wait for Reset Done timed out. GLNVM_ULD = 0x%x\n",
936 return ICE_ERR_RESET_FAILED;
943 * ice_pf_reset - Reset the PF
944 * @hw: pointer to the hardware structure
946 * If a global reset has been triggered, this function checks
947 * for its completion and then issues the PF reset
949 static enum ice_status ice_pf_reset(struct ice_hw *hw)
953 /* If at function entry a global reset was already in progress, i.e.
954 * state is not 'device active' or any of the reset done bits are not
955 * set in GLNVM_ULD, there is no need for a PF Reset; poll until the
956 * global reset is done.
958 if ((rd32(hw, GLGEN_RSTAT) & GLGEN_RSTAT_DEVSTATE_M) ||
959 (rd32(hw, GLNVM_ULD) & ICE_RESET_DONE_MASK) ^ ICE_RESET_DONE_MASK) {
960 /* poll on global reset currently in progress until done */
961 if (ice_check_reset(hw))
962 return ICE_ERR_RESET_FAILED;
968 reg = rd32(hw, PFGEN_CTRL);
970 wr32(hw, PFGEN_CTRL, (reg | PFGEN_CTRL_PFSWR_M));
972 for (cnt = 0; cnt < ICE_PF_RESET_WAIT_COUNT; cnt++) {
973 reg = rd32(hw, PFGEN_CTRL);
974 if (!(reg & PFGEN_CTRL_PFSWR_M))
977 ice_msec_delay(1, true);
980 if (cnt == ICE_PF_RESET_WAIT_COUNT) {
981 ice_debug(hw, ICE_DBG_INIT,
982 "PF reset polling failed to complete.\n");
983 return ICE_ERR_RESET_FAILED;
990 * ice_reset - Perform different types of reset
991 * @hw: pointer to the hardware structure
992 * @req: reset request
994 * This function triggers a reset as specified by the req parameter.
997 * If anything other than a PF reset is triggered, PXE mode is restored.
998 * This has to be cleared using ice_clear_pxe_mode again, once the AQ
999 * interface has been restored in the rebuild flow.
1001 enum ice_status ice_reset(struct ice_hw *hw, enum ice_reset_req req)
1007 return ice_pf_reset(hw);
1008 case ICE_RESET_CORER:
1009 ice_debug(hw, ICE_DBG_INIT, "CoreR requested\n");
1010 val = GLGEN_RTRIG_CORER_M;
1012 case ICE_RESET_GLOBR:
1013 ice_debug(hw, ICE_DBG_INIT, "GlobalR requested\n");
1014 val = GLGEN_RTRIG_GLOBR_M;
1017 return ICE_ERR_PARAM;
1020 val |= rd32(hw, GLGEN_RTRIG);
1021 wr32(hw, GLGEN_RTRIG, val);
1025 /* wait for the FW to be ready */
1026 return ice_check_reset(hw);
1032 * ice_copy_rxq_ctx_to_hw
1033 * @hw: pointer to the hardware structure
1034 * @ice_rxq_ctx: pointer to the rxq context
1035 * @rxq_index: the index of the Rx queue
1037 * Copies rxq context from dense structure to hw register space
1039 static enum ice_status
1040 ice_copy_rxq_ctx_to_hw(struct ice_hw *hw, u8 *ice_rxq_ctx, u32 rxq_index)
1045 return ICE_ERR_BAD_PTR;
1047 if (rxq_index > QRX_CTRL_MAX_INDEX)
1048 return ICE_ERR_PARAM;
1050 /* Copy each dword separately to hw */
1051 for (i = 0; i < ICE_RXQ_CTX_SIZE_DWORDS; i++) {
1052 wr32(hw, QRX_CONTEXT(i, rxq_index),
1053 *((u32 *)(ice_rxq_ctx + (i * sizeof(u32)))));
1055 ice_debug(hw, ICE_DBG_QCTX, "qrxdata[%d]: %08X\n", i,
1056 *((u32 *)(ice_rxq_ctx + (i * sizeof(u32)))));
1062 /* LAN Rx Queue Context */
1063 static const struct ice_ctx_ele ice_rlan_ctx_info[] = {
1064 /* Field Width LSB */
1065 ICE_CTX_STORE(ice_rlan_ctx, head, 13, 0),
1066 ICE_CTX_STORE(ice_rlan_ctx, cpuid, 8, 13),
1067 ICE_CTX_STORE(ice_rlan_ctx, base, 57, 32),
1068 ICE_CTX_STORE(ice_rlan_ctx, qlen, 13, 89),
1069 ICE_CTX_STORE(ice_rlan_ctx, dbuf, 7, 102),
1070 ICE_CTX_STORE(ice_rlan_ctx, hbuf, 5, 109),
1071 ICE_CTX_STORE(ice_rlan_ctx, dtype, 2, 114),
1072 ICE_CTX_STORE(ice_rlan_ctx, dsize, 1, 116),
1073 ICE_CTX_STORE(ice_rlan_ctx, crcstrip, 1, 117),
1074 ICE_CTX_STORE(ice_rlan_ctx, l2tsel, 1, 119),
1075 ICE_CTX_STORE(ice_rlan_ctx, hsplit_0, 4, 120),
1076 ICE_CTX_STORE(ice_rlan_ctx, hsplit_1, 2, 124),
1077 ICE_CTX_STORE(ice_rlan_ctx, showiv, 1, 127),
1078 ICE_CTX_STORE(ice_rlan_ctx, rxmax, 14, 174),
1079 ICE_CTX_STORE(ice_rlan_ctx, tphrdesc_ena, 1, 193),
1080 ICE_CTX_STORE(ice_rlan_ctx, tphwdesc_ena, 1, 194),
1081 ICE_CTX_STORE(ice_rlan_ctx, tphdata_ena, 1, 195),
1082 ICE_CTX_STORE(ice_rlan_ctx, tphhead_ena, 1, 196),
1083 ICE_CTX_STORE(ice_rlan_ctx, lrxqthresh, 3, 198),
1089 * @hw: pointer to the hardware structure
1090 * @rlan_ctx: pointer to the rxq context
1091 * @rxq_index: the index of the Rx queue
1093 * Converts rxq context from sparse to dense structure and then writes
1094 * it to hw register space
1097 ice_write_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx,
1100 u8 ctx_buf[ICE_RXQ_CTX_SZ] = { 0 };
1102 ice_set_ctx((u8 *)rlan_ctx, ctx_buf, ice_rlan_ctx_info);
1103 return ice_copy_rxq_ctx_to_hw(hw, ctx_buf, rxq_index);
1106 #if !defined(NO_UNUSED_CTX_CODE) || defined(AE_DRIVER)
1109 * @hw: pointer to the hardware structure
1110 * @rxq_index: the index of the Rx queue to clear
1112 * Clears rxq context in hw register space
1114 enum ice_status ice_clear_rxq_ctx(struct ice_hw *hw, u32 rxq_index)
1118 if (rxq_index > QRX_CTRL_MAX_INDEX)
1119 return ICE_ERR_PARAM;
1121 /* Clear each dword register separately */
1122 for (i = 0; i < ICE_RXQ_CTX_SIZE_DWORDS; i++)
1123 wr32(hw, QRX_CONTEXT(i, rxq_index), 0);
1127 #endif /* !NO_UNUSED_CTX_CODE || AE_DRIVER */
1129 /* LAN Tx Queue Context */
1130 const struct ice_ctx_ele ice_tlan_ctx_info[] = {
1131 /* Field Width LSB */
1132 ICE_CTX_STORE(ice_tlan_ctx, base, 57, 0),
1133 ICE_CTX_STORE(ice_tlan_ctx, port_num, 3, 57),
1134 ICE_CTX_STORE(ice_tlan_ctx, cgd_num, 5, 60),
1135 ICE_CTX_STORE(ice_tlan_ctx, pf_num, 3, 65),
1136 ICE_CTX_STORE(ice_tlan_ctx, vmvf_num, 10, 68),
1137 ICE_CTX_STORE(ice_tlan_ctx, vmvf_type, 2, 78),
1138 ICE_CTX_STORE(ice_tlan_ctx, src_vsi, 10, 80),
1139 ICE_CTX_STORE(ice_tlan_ctx, tsyn_ena, 1, 90),
1140 ICE_CTX_STORE(ice_tlan_ctx, alt_vlan, 1, 92),
1141 ICE_CTX_STORE(ice_tlan_ctx, cpuid, 8, 93),
1142 ICE_CTX_STORE(ice_tlan_ctx, wb_mode, 1, 101),
1143 ICE_CTX_STORE(ice_tlan_ctx, tphrd_desc, 1, 102),
1144 ICE_CTX_STORE(ice_tlan_ctx, tphrd, 1, 103),
1145 ICE_CTX_STORE(ice_tlan_ctx, tphwr_desc, 1, 104),
1146 ICE_CTX_STORE(ice_tlan_ctx, cmpq_id, 9, 105),
1147 ICE_CTX_STORE(ice_tlan_ctx, qnum_in_func, 14, 114),
1148 ICE_CTX_STORE(ice_tlan_ctx, itr_notification_mode, 1, 128),
1149 ICE_CTX_STORE(ice_tlan_ctx, adjust_prof_id, 6, 129),
1150 ICE_CTX_STORE(ice_tlan_ctx, qlen, 13, 135),
1151 ICE_CTX_STORE(ice_tlan_ctx, quanta_prof_idx, 4, 148),
1152 ICE_CTX_STORE(ice_tlan_ctx, tso_ena, 1, 152),
1153 ICE_CTX_STORE(ice_tlan_ctx, tso_qnum, 11, 153),
1154 ICE_CTX_STORE(ice_tlan_ctx, legacy_int, 1, 164),
1155 ICE_CTX_STORE(ice_tlan_ctx, drop_ena, 1, 165),
1156 ICE_CTX_STORE(ice_tlan_ctx, cache_prof_idx, 2, 166),
1157 ICE_CTX_STORE(ice_tlan_ctx, pkt_shaper_prof_idx, 3, 168),
1158 ICE_CTX_STORE(ice_tlan_ctx, int_q_state, 110, 171),
1162 #if !defined(NO_UNUSED_CTX_CODE) || defined(AE_DRIVER)
1164 * ice_copy_tx_cmpltnq_ctx_to_hw
1165 * @hw: pointer to the hardware structure
1166 * @ice_tx_cmpltnq_ctx: pointer to the Tx completion queue context
1167 * @tx_cmpltnq_index: the index of the completion queue
1169 * Copies Tx completion q context from dense structure to hw register space
1171 static enum ice_status
1172 ice_copy_tx_cmpltnq_ctx_to_hw(struct ice_hw *hw, u8 *ice_tx_cmpltnq_ctx,
1173 u32 tx_cmpltnq_index)
1177 if (!ice_tx_cmpltnq_ctx)
1178 return ICE_ERR_BAD_PTR;
1180 if (tx_cmpltnq_index > GLTCLAN_CQ_CNTX0_MAX_INDEX)
1181 return ICE_ERR_PARAM;
1183 /* Copy each dword separately to hw */
1184 for (i = 0; i < ICE_TX_CMPLTNQ_CTX_SIZE_DWORDS; i++) {
1185 wr32(hw, GLTCLAN_CQ_CNTX(i, tx_cmpltnq_index),
1186 *((u32 *)(ice_tx_cmpltnq_ctx + (i * sizeof(u32)))));
1188 ice_debug(hw, ICE_DBG_QCTX, "cmpltnqdata[%d]: %08X\n", i,
1189 *((u32 *)(ice_tx_cmpltnq_ctx + (i * sizeof(u32)))));
1195 /* LAN Tx Completion Queue Context */
1196 static const struct ice_ctx_ele ice_tx_cmpltnq_ctx_info[] = {
1197 /* Field Width LSB */
1198 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, base, 57, 0),
1199 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, q_len, 18, 64),
1200 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, generation, 1, 96),
1201 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, wrt_ptr, 22, 97),
1202 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, pf_num, 3, 128),
1203 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, vmvf_num, 10, 131),
1204 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, vmvf_type, 2, 141),
1205 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, tph_desc_wr, 1, 160),
1206 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, cpuid, 8, 161),
1207 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, cmpltn_cache, 512, 192),
1212 * ice_write_tx_cmpltnq_ctx
1213 * @hw: pointer to the hardware structure
1214 * @tx_cmpltnq_ctx: pointer to the completion queue context
1215 * @tx_cmpltnq_index: the index of the completion queue
1217 * Converts completion queue context from sparse to dense structure and then
1218 * writes it to hw register space
1221 ice_write_tx_cmpltnq_ctx(struct ice_hw *hw,
1222 struct ice_tx_cmpltnq_ctx *tx_cmpltnq_ctx,
1223 u32 tx_cmpltnq_index)
1225 u8 ctx_buf[ICE_TX_CMPLTNQ_CTX_SIZE_DWORDS * sizeof(u32)] = { 0 };
1227 ice_set_ctx((u8 *)tx_cmpltnq_ctx, ctx_buf, ice_tx_cmpltnq_ctx_info);
1228 return ice_copy_tx_cmpltnq_ctx_to_hw(hw, ctx_buf, tx_cmpltnq_index);
1232 * ice_clear_tx_cmpltnq_ctx
1233 * @hw: pointer to the hardware structure
1234 * @tx_cmpltnq_index: the index of the completion queue to clear
1236 * Clears Tx completion queue context in hw register space
1239 ice_clear_tx_cmpltnq_ctx(struct ice_hw *hw, u32 tx_cmpltnq_index)
1243 if (tx_cmpltnq_index > GLTCLAN_CQ_CNTX0_MAX_INDEX)
1244 return ICE_ERR_PARAM;
1246 /* Clear each dword register separately */
1247 for (i = 0; i < ICE_TX_CMPLTNQ_CTX_SIZE_DWORDS; i++)
1248 wr32(hw, GLTCLAN_CQ_CNTX(i, tx_cmpltnq_index), 0);
1254 * ice_copy_tx_drbell_q_ctx_to_hw
1255 * @hw: pointer to the hardware structure
1256 * @ice_tx_drbell_q_ctx: pointer to the doorbell queue context
1257 * @tx_drbell_q_index: the index of the doorbell queue
1259 * Copies doorbell q context from dense structure to hw register space
1261 static enum ice_status
1262 ice_copy_tx_drbell_q_ctx_to_hw(struct ice_hw *hw, u8 *ice_tx_drbell_q_ctx,
1263 u32 tx_drbell_q_index)
1267 if (!ice_tx_drbell_q_ctx)
1268 return ICE_ERR_BAD_PTR;
1270 if (tx_drbell_q_index > QTX_COMM_DBLQ_DBELL_MAX_INDEX)
1271 return ICE_ERR_PARAM;
1273 /* Copy each dword separately to hw */
1274 for (i = 0; i < ICE_TX_DRBELL_Q_CTX_SIZE_DWORDS; i++) {
1275 wr32(hw, QTX_COMM_DBLQ_CNTX(i, tx_drbell_q_index),
1276 *((u32 *)(ice_tx_drbell_q_ctx + (i * sizeof(u32)))));
1278 ice_debug(hw, ICE_DBG_QCTX, "tx_drbell_qdata[%d]: %08X\n", i,
1279 *((u32 *)(ice_tx_drbell_q_ctx + (i * sizeof(u32)))));
1285 /* LAN Tx Doorbell Queue Context info */
1286 static const struct ice_ctx_ele ice_tx_drbell_q_ctx_info[] = {
1287 /* Field Width LSB */
1288 ICE_CTX_STORE(ice_tx_drbell_q_ctx, base, 57, 0),
1289 ICE_CTX_STORE(ice_tx_drbell_q_ctx, ring_len, 13, 64),
1290 ICE_CTX_STORE(ice_tx_drbell_q_ctx, pf_num, 3, 80),
1291 ICE_CTX_STORE(ice_tx_drbell_q_ctx, vf_num, 8, 84),
1292 ICE_CTX_STORE(ice_tx_drbell_q_ctx, vmvf_type, 2, 94),
1293 ICE_CTX_STORE(ice_tx_drbell_q_ctx, cpuid, 8, 96),
1294 ICE_CTX_STORE(ice_tx_drbell_q_ctx, tph_desc_rd, 1, 104),
1295 ICE_CTX_STORE(ice_tx_drbell_q_ctx, tph_desc_wr, 1, 108),
1296 ICE_CTX_STORE(ice_tx_drbell_q_ctx, db_q_en, 1, 112),
1297 ICE_CTX_STORE(ice_tx_drbell_q_ctx, rd_head, 13, 128),
1298 ICE_CTX_STORE(ice_tx_drbell_q_ctx, rd_tail, 13, 144),
1303 * ice_write_tx_drbell_q_ctx
1304 * @hw: pointer to the hardware structure
1305 * @tx_drbell_q_ctx: pointer to the doorbell queue context
1306 * @tx_drbell_q_index: the index of the doorbell queue
1308 * Converts doorbell queue context from sparse to dense structure and then
1309 * writes it to hw register space
1312 ice_write_tx_drbell_q_ctx(struct ice_hw *hw,
1313 struct ice_tx_drbell_q_ctx *tx_drbell_q_ctx,
1314 u32 tx_drbell_q_index)
1316 u8 ctx_buf[ICE_TX_DRBELL_Q_CTX_SIZE_DWORDS * sizeof(u32)] = { 0 };
1318 ice_set_ctx((u8 *)tx_drbell_q_ctx, ctx_buf, ice_tx_drbell_q_ctx_info);
1319 return ice_copy_tx_drbell_q_ctx_to_hw(hw, ctx_buf, tx_drbell_q_index);
1323 * ice_clear_tx_drbell_q_ctx
1324 * @hw: pointer to the hardware structure
1325 * @tx_drbell_q_index: the index of the doorbell queue to clear
1327 * Clears doorbell queue context in hw register space
1330 ice_clear_tx_drbell_q_ctx(struct ice_hw *hw, u32 tx_drbell_q_index)
1334 if (tx_drbell_q_index > QTX_COMM_DBLQ_DBELL_MAX_INDEX)
1335 return ICE_ERR_PARAM;
1337 /* Clear each dword register separately */
1338 for (i = 0; i < ICE_TX_DRBELL_Q_CTX_SIZE_DWORDS; i++)
1339 wr32(hw, QTX_COMM_DBLQ_CNTX(i, tx_drbell_q_index), 0);
1343 #endif /* !NO_UNUSED_CTX_CODE || AE_DRIVER */
1347 * @hw: pointer to the hardware structure
1349 * @desc: pointer to control queue descriptor
1350 * @buf: pointer to command buffer
1351 * @buf_len: max length of buf
1353 * Dumps debug log about control command with descriptor contents.
1356 ice_debug_cq(struct ice_hw *hw, u32 mask, void *desc, void *buf, u16 buf_len)
1358 struct ice_aq_desc *cq_desc = (struct ice_aq_desc *)desc;
1361 if (!(mask & hw->debug_mask))
1367 len = LE16_TO_CPU(cq_desc->datalen);
1370 "CQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
1371 LE16_TO_CPU(cq_desc->opcode),
1372 LE16_TO_CPU(cq_desc->flags),
1373 LE16_TO_CPU(cq_desc->datalen), LE16_TO_CPU(cq_desc->retval));
1374 ice_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n",
1375 LE32_TO_CPU(cq_desc->cookie_high),
1376 LE32_TO_CPU(cq_desc->cookie_low));
1377 ice_debug(hw, mask, "\tparam (0,1) 0x%08X 0x%08X\n",
1378 LE32_TO_CPU(cq_desc->params.generic.param0),
1379 LE32_TO_CPU(cq_desc->params.generic.param1));
1380 ice_debug(hw, mask, "\taddr (h,l) 0x%08X 0x%08X\n",
1381 LE32_TO_CPU(cq_desc->params.generic.addr_high),
1382 LE32_TO_CPU(cq_desc->params.generic.addr_low));
1383 if (buf && cq_desc->datalen != 0) {
1384 ice_debug(hw, mask, "Buffer:\n");
1388 ice_debug_array(hw, mask, 16, 1, (u8 *)buf, len);
1393 /* FW Admin Queue command wrappers */
1396 * ice_aq_send_cmd - send FW Admin Queue command to FW Admin Queue
1397 * @hw: pointer to the hw struct
1398 * @desc: descriptor describing the command
1399 * @buf: buffer to use for indirect commands (NULL for direct commands)
1400 * @buf_size: size of buffer for indirect commands (0 for direct commands)
1401 * @cd: pointer to command details structure
1403 * Helper function to send FW Admin Queue commands to the FW Admin Queue.
1406 ice_aq_send_cmd(struct ice_hw *hw, struct ice_aq_desc *desc, void *buf,
1407 u16 buf_size, struct ice_sq_cd *cd)
1409 return ice_sq_send_cmd(hw, &hw->adminq, desc, buf, buf_size, cd);
1414 * @hw: pointer to the hw struct
1415 * @cd: pointer to command details structure or NULL
1417 * Get the firmware version (0x0001) from the admin queue commands
1419 enum ice_status ice_aq_get_fw_ver(struct ice_hw *hw, struct ice_sq_cd *cd)
1421 struct ice_aqc_get_ver *resp;
1422 struct ice_aq_desc desc;
1423 enum ice_status status;
1425 resp = &desc.params.get_ver;
1427 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_ver);
1429 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
1432 hw->fw_branch = resp->fw_branch;
1433 hw->fw_maj_ver = resp->fw_major;
1434 hw->fw_min_ver = resp->fw_minor;
1435 hw->fw_patch = resp->fw_patch;
1436 hw->fw_build = LE32_TO_CPU(resp->fw_build);
1437 hw->api_branch = resp->api_branch;
1438 hw->api_maj_ver = resp->api_major;
1439 hw->api_min_ver = resp->api_minor;
1440 hw->api_patch = resp->api_patch;
1449 * @hw: pointer to the hw struct
1450 * @unloading: is the driver unloading itself
1452 * Tell the Firmware that we're shutting down the AdminQ and whether
1453 * or not the driver is unloading as well (0x0003).
1455 enum ice_status ice_aq_q_shutdown(struct ice_hw *hw, bool unloading)
1457 struct ice_aqc_q_shutdown *cmd;
1458 struct ice_aq_desc desc;
1460 cmd = &desc.params.q_shutdown;
1462 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_q_shutdown);
1465 cmd->driver_unloading = CPU_TO_LE32(ICE_AQC_DRIVER_UNLOADING);
1467 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
1472 * @hw: pointer to the hw struct
1474 * @access: access type
1475 * @sdp_number: resource number
1476 * @timeout: the maximum time in ms that the driver may hold the resource
1477 * @cd: pointer to command details structure or NULL
1479 * Requests common resource using the admin queue commands (0x0008).
1480 * When attempting to acquire the Global Config Lock, the driver can
1481 * learn of three states:
1482 * 1) ICE_SUCCESS - acquired lock, and can perform download package
1483 * 2) ICE_ERR_AQ_ERROR - did not get lock, driver should fail to load
1484 * 3) ICE_ERR_AQ_NO_WORK - did not get lock, but another driver has
1485 * successfully downloaded the package; the driver does
1486 * not have to download the package and can continue
1489 * Note that if the caller is in an acquire lock, perform action, release lock
1490 * phase of operation, it is possible that the FW may detect a timeout and issue
1491 * a CORER. In this case, the driver will receive a CORER interrupt and will
1492 * have to determine its cause. The calling thread that is handling this flow
1493 * will likely get an error propagated back to it indicating the Download
1494 * Package, Update Package or the Release Resource AQ commands timed out.
1496 static enum ice_status
1497 ice_aq_req_res(struct ice_hw *hw, enum ice_aq_res_ids res,
1498 enum ice_aq_res_access_type access, u8 sdp_number, u32 *timeout,
1499 struct ice_sq_cd *cd)
1501 struct ice_aqc_req_res *cmd_resp;
1502 struct ice_aq_desc desc;
1503 enum ice_status status;
1505 ice_debug(hw, ICE_DBG_TRACE, "ice_aq_req_res");
1507 cmd_resp = &desc.params.res_owner;
1509 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_req_res);
1511 cmd_resp->res_id = CPU_TO_LE16(res);
1512 cmd_resp->access_type = CPU_TO_LE16(access);
1513 cmd_resp->res_number = CPU_TO_LE32(sdp_number);
1514 cmd_resp->timeout = CPU_TO_LE32(*timeout);
1517 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
1519 /* The completion specifies the maximum time in ms that the driver
1520 * may hold the resource in the Timeout field.
1523 /* Global config lock response utilizes an additional status field.
1525 * If the Global config lock resource is held by some other driver, the
1526 * command completes with ICE_AQ_RES_GLBL_IN_PROG in the status field
1527 * and the timeout field indicates the maximum time the current owner
1528 * of the resource has to free it.
1530 if (res == ICE_GLOBAL_CFG_LOCK_RES_ID) {
1531 if (LE16_TO_CPU(cmd_resp->status) == ICE_AQ_RES_GLBL_SUCCESS) {
1532 *timeout = LE32_TO_CPU(cmd_resp->timeout);
1534 } else if (LE16_TO_CPU(cmd_resp->status) ==
1535 ICE_AQ_RES_GLBL_IN_PROG) {
1536 *timeout = LE32_TO_CPU(cmd_resp->timeout);
1537 return ICE_ERR_AQ_ERROR;
1538 } else if (LE16_TO_CPU(cmd_resp->status) ==
1539 ICE_AQ_RES_GLBL_DONE) {
1540 return ICE_ERR_AQ_NO_WORK;
1543 /* invalid FW response, force a timeout immediately */
1545 return ICE_ERR_AQ_ERROR;
1548 /* If the resource is held by some other driver, the command completes
1549 * with a busy return value and the timeout field indicates the maximum
1550 * time the current owner of the resource has to free it.
1552 if (!status || hw->adminq.sq_last_status == ICE_AQ_RC_EBUSY)
1553 *timeout = LE32_TO_CPU(cmd_resp->timeout);
1559 * ice_aq_release_res
1560 * @hw: pointer to the hw struct
1562 * @sdp_number: resource number
1563 * @cd: pointer to command details structure or NULL
1565 * release common resource using the admin queue commands (0x0009)
1567 static enum ice_status
1568 ice_aq_release_res(struct ice_hw *hw, enum ice_aq_res_ids res, u8 sdp_number,
1569 struct ice_sq_cd *cd)
1571 struct ice_aqc_req_res *cmd;
1572 struct ice_aq_desc desc;
1574 ice_debug(hw, ICE_DBG_TRACE, "ice_aq_release_res");
1576 cmd = &desc.params.res_owner;
1578 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_release_res);
1580 cmd->res_id = CPU_TO_LE16(res);
1581 cmd->res_number = CPU_TO_LE32(sdp_number);
1583 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
1588 * @hw: pointer to the HW structure
1590 * @access: access type (read or write)
1591 * @timeout: timeout in milliseconds
1593 * This function will attempt to acquire the ownership of a resource.
1596 ice_acquire_res(struct ice_hw *hw, enum ice_aq_res_ids res,
1597 enum ice_aq_res_access_type access, u32 timeout)
1599 #define ICE_RES_POLLING_DELAY_MS 10
1600 u32 delay = ICE_RES_POLLING_DELAY_MS;
1601 u32 time_left = timeout;
1602 enum ice_status status;
1604 ice_debug(hw, ICE_DBG_TRACE, "ice_acquire_res");
1606 status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL);
1608 /* A return code of ICE_ERR_AQ_NO_WORK means that another driver has
1609 * previously acquired the resource and performed any necessary updates;
1610 * in this case the caller does not obtain the resource and has no
1611 * further work to do.
1613 if (status == ICE_ERR_AQ_NO_WORK)
1614 goto ice_acquire_res_exit;
1617 ice_debug(hw, ICE_DBG_RES,
1618 "resource %d acquire type %d failed.\n", res, access);
1620 /* If necessary, poll until the current lock owner timeouts */
1621 timeout = time_left;
1622 while (status && timeout && time_left) {
1623 ice_msec_delay(delay, true);
1624 timeout = (timeout > delay) ? timeout - delay : 0;
1625 status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL);
1627 if (status == ICE_ERR_AQ_NO_WORK)
1628 /* lock free, but no work to do */
1635 if (status && status != ICE_ERR_AQ_NO_WORK)
1636 ice_debug(hw, ICE_DBG_RES, "resource acquire timed out.\n");
1638 ice_acquire_res_exit:
1639 if (status == ICE_ERR_AQ_NO_WORK) {
1640 if (access == ICE_RES_WRITE)
1641 ice_debug(hw, ICE_DBG_RES,
1642 "resource indicates no work to do.\n");
1644 ice_debug(hw, ICE_DBG_RES,
1645 "Warning: ICE_ERR_AQ_NO_WORK not expected\n");
1652 * @hw: pointer to the HW structure
1655 * This function will release a resource using the proper Admin Command.
1657 void ice_release_res(struct ice_hw *hw, enum ice_aq_res_ids res)
1659 enum ice_status status;
1660 u32 total_delay = 0;
1662 ice_debug(hw, ICE_DBG_TRACE, "ice_release_res");
1664 status = ice_aq_release_res(hw, res, 0, NULL);
1666 /* there are some rare cases when trying to release the resource
1667 * results in an admin Q timeout, so handle them correctly
1669 while ((status == ICE_ERR_AQ_TIMEOUT) &&
1670 (total_delay < hw->adminq.sq_cmd_timeout)) {
1671 ice_msec_delay(1, true);
1672 status = ice_aq_release_res(hw, res, 0, NULL);
1678 * ice_aq_alloc_free_res - command to allocate/free resources
1679 * @hw: pointer to the hw struct
1680 * @num_entries: number of resource entries in buffer
1681 * @buf: Indirect buffer to hold data parameters and response
1682 * @buf_size: size of buffer for indirect commands
1683 * @opc: pass in the command opcode
1684 * @cd: pointer to command details structure or NULL
1686 * Helper function to allocate/free resources using the admin queue commands
1689 ice_aq_alloc_free_res(struct ice_hw *hw, u16 num_entries,
1690 struct ice_aqc_alloc_free_res_elem *buf, u16 buf_size,
1691 enum ice_adminq_opc opc, struct ice_sq_cd *cd)
1693 struct ice_aqc_alloc_free_res_cmd *cmd;
1694 struct ice_aq_desc desc;
1696 ice_debug(hw, ICE_DBG_TRACE, "ice_aq_alloc_free_res");
1698 cmd = &desc.params.sw_res_ctrl;
1701 return ICE_ERR_PARAM;
1703 if (buf_size < (num_entries * sizeof(buf->elem[0])))
1704 return ICE_ERR_PARAM;
1706 ice_fill_dflt_direct_cmd_desc(&desc, opc);
1708 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
1710 cmd->num_entries = CPU_TO_LE16(num_entries);
1712 return ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);
1717 * ice_get_num_per_func - determine number of resources per PF
1718 * @hw: pointer to the hw structure
1719 * @max: value to be evenly split between each PF
1721 * Determine the number of valid functions by going through the bitmap returned
1722 * from parsing capabilities and use this to calculate the number of resources
1723 * per PF based on the max value passed in.
1725 static u32 ice_get_num_per_func(struct ice_hw *hw, u32 max)
1729 #define ICE_CAPS_VALID_FUNCS_M 0xFF
1730 funcs = ice_hweight8(hw->dev_caps.common_cap.valid_functions &
1731 ICE_CAPS_VALID_FUNCS_M);
1740 * ice_parse_caps - parse function/device capabilities
1741 * @hw: pointer to the hw struct
1742 * @buf: pointer to a buffer containing function/device capability records
1743 * @cap_count: number of capability records in the list
1744 * @opc: type of capabilities list to parse
1746 * Helper function to parse function(0x000a)/device(0x000b) capabilities list.
1749 ice_parse_caps(struct ice_hw *hw, void *buf, u32 cap_count,
1750 enum ice_adminq_opc opc)
1752 struct ice_aqc_list_caps_elem *cap_resp;
1753 struct ice_hw_func_caps *func_p = NULL;
1754 struct ice_hw_dev_caps *dev_p = NULL;
1755 struct ice_hw_common_caps *caps;
1761 cap_resp = (struct ice_aqc_list_caps_elem *)buf;
1763 if (opc == ice_aqc_opc_list_dev_caps) {
1764 dev_p = &hw->dev_caps;
1765 caps = &dev_p->common_cap;
1766 } else if (opc == ice_aqc_opc_list_func_caps) {
1767 func_p = &hw->func_caps;
1768 caps = &func_p->common_cap;
1770 ice_debug(hw, ICE_DBG_INIT, "wrong opcode\n");
1774 for (i = 0; caps && i < cap_count; i++, cap_resp++) {
1775 u32 logical_id = LE32_TO_CPU(cap_resp->logical_id);
1776 u32 phys_id = LE32_TO_CPU(cap_resp->phys_id);
1777 u32 number = LE32_TO_CPU(cap_resp->number);
1778 u16 cap = LE16_TO_CPU(cap_resp->cap);
1781 case ICE_AQC_CAPS_VALID_FUNCTIONS:
1782 caps->valid_functions = number;
1783 ice_debug(hw, ICE_DBG_INIT,
1784 "HW caps: Valid Functions = %d\n",
1785 caps->valid_functions);
1787 case ICE_AQC_CAPS_VSI:
1789 dev_p->num_vsi_allocd_to_host = number;
1790 ice_debug(hw, ICE_DBG_INIT,
1791 "HW caps: Dev.VSI cnt = %d\n",
1792 dev_p->num_vsi_allocd_to_host);
1793 } else if (func_p) {
1794 func_p->guar_num_vsi =
1795 ice_get_num_per_func(hw, ICE_MAX_VSI);
1796 ice_debug(hw, ICE_DBG_INIT,
1797 "HW caps: Func.VSI cnt = %d\n",
1801 case ICE_AQC_CAPS_RSS:
1802 caps->rss_table_size = number;
1803 caps->rss_table_entry_width = logical_id;
1804 ice_debug(hw, ICE_DBG_INIT,
1805 "HW caps: RSS table size = %d\n",
1806 caps->rss_table_size);
1807 ice_debug(hw, ICE_DBG_INIT,
1808 "HW caps: RSS table width = %d\n",
1809 caps->rss_table_entry_width);
1811 case ICE_AQC_CAPS_RXQS:
1812 caps->num_rxq = number;
1813 caps->rxq_first_id = phys_id;
1814 ice_debug(hw, ICE_DBG_INIT,
1815 "HW caps: Num Rx Qs = %d\n", caps->num_rxq);
1816 ice_debug(hw, ICE_DBG_INIT,
1817 "HW caps: Rx first queue ID = %d\n",
1818 caps->rxq_first_id);
1820 case ICE_AQC_CAPS_TXQS:
1821 caps->num_txq = number;
1822 caps->txq_first_id = phys_id;
1823 ice_debug(hw, ICE_DBG_INIT,
1824 "HW caps: Num Tx Qs = %d\n", caps->num_txq);
1825 ice_debug(hw, ICE_DBG_INIT,
1826 "HW caps: Tx first queue ID = %d\n",
1827 caps->txq_first_id);
1829 case ICE_AQC_CAPS_MSIX:
1830 caps->num_msix_vectors = number;
1831 caps->msix_vector_first_id = phys_id;
1832 ice_debug(hw, ICE_DBG_INIT,
1833 "HW caps: MSIX vector count = %d\n",
1834 caps->num_msix_vectors);
1835 ice_debug(hw, ICE_DBG_INIT,
1836 "HW caps: MSIX first vector index = %d\n",
1837 caps->msix_vector_first_id);
1839 case ICE_AQC_CAPS_MAX_MTU:
1840 caps->max_mtu = number;
1842 ice_debug(hw, ICE_DBG_INIT,
1843 "HW caps: Dev.MaxMTU = %d\n",
1846 ice_debug(hw, ICE_DBG_INIT,
1847 "HW caps: func.MaxMTU = %d\n",
1851 ice_debug(hw, ICE_DBG_INIT,
1852 "HW caps: Unknown capability[%d]: 0x%x\n", i,
1860 * ice_aq_discover_caps - query function/device capabilities
1861 * @hw: pointer to the hw struct
1862 * @buf: a virtual buffer to hold the capabilities
1863 * @buf_size: Size of the virtual buffer
1864 * @cap_count: cap count needed if AQ err==ENOMEM
1865 * @opc: capabilities type to discover - pass in the command opcode
1866 * @cd: pointer to command details structure or NULL
1868 * Get the function(0x000a)/device(0x000b) capabilities description from
1871 static enum ice_status
1872 ice_aq_discover_caps(struct ice_hw *hw, void *buf, u16 buf_size, u32 *cap_count,
1873 enum ice_adminq_opc opc, struct ice_sq_cd *cd)
1875 struct ice_aqc_list_caps *cmd;
1876 struct ice_aq_desc desc;
1877 enum ice_status status;
1879 cmd = &desc.params.get_cap;
1881 if (opc != ice_aqc_opc_list_func_caps &&
1882 opc != ice_aqc_opc_list_dev_caps)
1883 return ICE_ERR_PARAM;
1885 ice_fill_dflt_direct_cmd_desc(&desc, opc);
1887 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);
1889 ice_parse_caps(hw, buf, LE32_TO_CPU(cmd->count), opc);
1890 else if (hw->adminq.sq_last_status == ICE_AQ_RC_ENOMEM)
1891 *cap_count = LE32_TO_CPU(cmd->count);
1896 * ice_discover_caps - get info about the HW
1897 * @hw: pointer to the hardware structure
1898 * @opc: capabilities type to discover - pass in the command opcode
1900 static enum ice_status
1901 ice_discover_caps(struct ice_hw *hw, enum ice_adminq_opc opc)
1903 enum ice_status status;
1908 /* The driver doesn't know how many capabilities the device will return
1909 * so the buffer size required isn't known ahead of time. The driver
1910 * starts with cbuf_len and if this turns out to be insufficient, the
1911 * device returns ICE_AQ_RC_ENOMEM and also the cap_count it needs.
1912 * The driver then allocates the buffer based on the count and retries
1913 * the operation. So it follows that the retry count is 2.
1915 #define ICE_GET_CAP_BUF_COUNT 40
1916 #define ICE_GET_CAP_RETRY_COUNT 2
1918 cap_count = ICE_GET_CAP_BUF_COUNT;
1919 retries = ICE_GET_CAP_RETRY_COUNT;
1924 cbuf_len = (u16)(cap_count *
1925 sizeof(struct ice_aqc_list_caps_elem));
1926 cbuf = ice_malloc(hw, cbuf_len);
1928 return ICE_ERR_NO_MEMORY;
1930 status = ice_aq_discover_caps(hw, cbuf, cbuf_len, &cap_count,
1934 if (!status || hw->adminq.sq_last_status != ICE_AQ_RC_ENOMEM)
1937 /* If ENOMEM is returned, try again with bigger buffer */
1938 } while (--retries);
1944 * ice_get_caps - get info about the HW
1945 * @hw: pointer to the hardware structure
1947 enum ice_status ice_get_caps(struct ice_hw *hw)
1949 enum ice_status status;
1951 status = ice_discover_caps(hw, ice_aqc_opc_list_dev_caps);
1953 status = ice_discover_caps(hw, ice_aqc_opc_list_func_caps);
1959 * ice_aq_manage_mac_write - manage MAC address write command
1960 * @hw: pointer to the hw struct
1961 * @mac_addr: MAC address to be written as LAA/LAA+WoL/Port address
1962 * @flags: flags to control write behavior
1963 * @cd: pointer to command details structure or NULL
1965 * This function is used to write MAC address to the NVM (0x0108).
1968 ice_aq_manage_mac_write(struct ice_hw *hw, const u8 *mac_addr, u8 flags,
1969 struct ice_sq_cd *cd)
1971 struct ice_aqc_manage_mac_write *cmd;
1972 struct ice_aq_desc desc;
1974 cmd = &desc.params.mac_write;
1975 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_write);
1980 /* Prep values for flags, sah, sal */
1981 cmd->sah = HTONS(*((const u16 *)mac_addr));
1982 cmd->sal = HTONL(*((const u32 *)(mac_addr + 2)));
1984 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
1988 * ice_aq_clear_pxe_mode
1989 * @hw: pointer to the hw struct
1991 * Tell the firmware that the driver is taking over from PXE (0x0110).
1993 static enum ice_status ice_aq_clear_pxe_mode(struct ice_hw *hw)
1995 struct ice_aq_desc desc;
1997 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pxe_mode);
1998 desc.params.clear_pxe.rx_cnt = ICE_AQC_CLEAR_PXE_RX_CNT;
2000 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
2004 * ice_clear_pxe_mode - clear pxe operations mode
2005 * @hw: pointer to the hw struct
2007 * Make sure all PXE mode settings are cleared, including things
2008 * like descriptor fetch/write-back mode.
2010 void ice_clear_pxe_mode(struct ice_hw *hw)
2012 if (ice_check_sq_alive(hw, &hw->adminq))
2013 ice_aq_clear_pxe_mode(hw);
2018 * ice_get_link_speed_based_on_phy_type - returns link speed
2019 * @phy_type_low: lower part of phy_type
2020 * @phy_type_high: higher part of phy_type
2022 * This helper function will convert an entry in phy type structure
2023 * [phy_type_low, phy_type_high] to its corresponding link speed.
2024 * Note: In the structure of [phy_type_low, phy_type_high], there should
2025 * be one bit set, as this function will convert one phy type to its
2027 * If no bit gets set, ICE_LINK_SPEED_UNKNOWN will be returned
2028 * If more than one bit gets set, ICE_LINK_SPEED_UNKNOWN will be returned
2031 ice_get_link_speed_based_on_phy_type(u64 phy_type_low, u64 phy_type_high)
2033 u16 speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN;
2034 u16 speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN;
2036 switch (phy_type_low) {
2037 case ICE_PHY_TYPE_LOW_100BASE_TX:
2038 case ICE_PHY_TYPE_LOW_100M_SGMII:
2039 speed_phy_type_low = ICE_AQ_LINK_SPEED_100MB;
2041 case ICE_PHY_TYPE_LOW_1000BASE_T:
2042 case ICE_PHY_TYPE_LOW_1000BASE_SX:
2043 case ICE_PHY_TYPE_LOW_1000BASE_LX:
2044 case ICE_PHY_TYPE_LOW_1000BASE_KX:
2045 case ICE_PHY_TYPE_LOW_1G_SGMII:
2046 speed_phy_type_low = ICE_AQ_LINK_SPEED_1000MB;
2048 case ICE_PHY_TYPE_LOW_2500BASE_T:
2049 case ICE_PHY_TYPE_LOW_2500BASE_X:
2050 case ICE_PHY_TYPE_LOW_2500BASE_KX:
2051 speed_phy_type_low = ICE_AQ_LINK_SPEED_2500MB;
2053 case ICE_PHY_TYPE_LOW_5GBASE_T:
2054 case ICE_PHY_TYPE_LOW_5GBASE_KR:
2055 speed_phy_type_low = ICE_AQ_LINK_SPEED_5GB;
2057 case ICE_PHY_TYPE_LOW_10GBASE_T:
2058 case ICE_PHY_TYPE_LOW_10G_SFI_DA:
2059 case ICE_PHY_TYPE_LOW_10GBASE_SR:
2060 case ICE_PHY_TYPE_LOW_10GBASE_LR:
2061 case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1:
2062 case ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC:
2063 case ICE_PHY_TYPE_LOW_10G_SFI_C2C:
2064 speed_phy_type_low = ICE_AQ_LINK_SPEED_10GB;
2066 case ICE_PHY_TYPE_LOW_25GBASE_T:
2067 case ICE_PHY_TYPE_LOW_25GBASE_CR:
2068 case ICE_PHY_TYPE_LOW_25GBASE_CR_S:
2069 case ICE_PHY_TYPE_LOW_25GBASE_CR1:
2070 case ICE_PHY_TYPE_LOW_25GBASE_SR:
2071 case ICE_PHY_TYPE_LOW_25GBASE_LR:
2072 case ICE_PHY_TYPE_LOW_25GBASE_KR:
2073 case ICE_PHY_TYPE_LOW_25GBASE_KR_S:
2074 case ICE_PHY_TYPE_LOW_25GBASE_KR1:
2075 case ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC:
2076 case ICE_PHY_TYPE_LOW_25G_AUI_C2C:
2077 speed_phy_type_low = ICE_AQ_LINK_SPEED_25GB;
2079 case ICE_PHY_TYPE_LOW_40GBASE_CR4:
2080 case ICE_PHY_TYPE_LOW_40GBASE_SR4:
2081 case ICE_PHY_TYPE_LOW_40GBASE_LR4:
2082 case ICE_PHY_TYPE_LOW_40GBASE_KR4:
2083 case ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC:
2084 case ICE_PHY_TYPE_LOW_40G_XLAUI:
2085 speed_phy_type_low = ICE_AQ_LINK_SPEED_40GB;
2087 case ICE_PHY_TYPE_LOW_50GBASE_CR2:
2088 case ICE_PHY_TYPE_LOW_50GBASE_SR2:
2089 case ICE_PHY_TYPE_LOW_50GBASE_LR2:
2090 case ICE_PHY_TYPE_LOW_50GBASE_KR2:
2091 case ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC:
2092 case ICE_PHY_TYPE_LOW_50G_LAUI2:
2093 case ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC:
2094 case ICE_PHY_TYPE_LOW_50G_AUI2:
2095 case ICE_PHY_TYPE_LOW_50GBASE_CP:
2096 case ICE_PHY_TYPE_LOW_50GBASE_SR:
2097 case ICE_PHY_TYPE_LOW_50GBASE_FR:
2098 case ICE_PHY_TYPE_LOW_50GBASE_LR:
2099 case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4:
2100 case ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC:
2101 case ICE_PHY_TYPE_LOW_50G_AUI1:
2102 speed_phy_type_low = ICE_AQ_LINK_SPEED_50GB;
2104 case ICE_PHY_TYPE_LOW_100GBASE_CR4:
2105 case ICE_PHY_TYPE_LOW_100GBASE_SR4:
2106 case ICE_PHY_TYPE_LOW_100GBASE_LR4:
2107 case ICE_PHY_TYPE_LOW_100GBASE_KR4:
2108 case ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC:
2109 case ICE_PHY_TYPE_LOW_100G_CAUI4:
2110 case ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC:
2111 case ICE_PHY_TYPE_LOW_100G_AUI4:
2112 case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4:
2113 case ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4:
2114 case ICE_PHY_TYPE_LOW_100GBASE_CP2:
2115 case ICE_PHY_TYPE_LOW_100GBASE_SR2:
2116 case ICE_PHY_TYPE_LOW_100GBASE_DR:
2117 speed_phy_type_low = ICE_AQ_LINK_SPEED_100GB;
2120 speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN;
2124 switch (phy_type_high) {
2125 case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4:
2126 case ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC:
2127 case ICE_PHY_TYPE_HIGH_100G_CAUI2:
2128 case ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC:
2129 case ICE_PHY_TYPE_HIGH_100G_AUI2:
2130 speed_phy_type_high = ICE_AQ_LINK_SPEED_100GB;
2133 speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN;
2137 if (speed_phy_type_low == ICE_AQ_LINK_SPEED_UNKNOWN &&
2138 speed_phy_type_high == ICE_AQ_LINK_SPEED_UNKNOWN)
2139 return ICE_AQ_LINK_SPEED_UNKNOWN;
2140 else if (speed_phy_type_low != ICE_AQ_LINK_SPEED_UNKNOWN &&
2141 speed_phy_type_high != ICE_AQ_LINK_SPEED_UNKNOWN)
2142 return ICE_AQ_LINK_SPEED_UNKNOWN;
2143 else if (speed_phy_type_low != ICE_AQ_LINK_SPEED_UNKNOWN &&
2144 speed_phy_type_high == ICE_AQ_LINK_SPEED_UNKNOWN)
2145 return speed_phy_type_low;
2147 return speed_phy_type_high;
2151 * ice_update_phy_type
2152 * @phy_type_low: pointer to the lower part of phy_type
2153 * @phy_type_high: pointer to the higher part of phy_type
2154 * @link_speeds_bitmap: targeted link speeds bitmap
2156 * Note: For the link_speeds_bitmap structure, you can check it at
2157 * [ice_aqc_get_link_status->link_speed]. Caller can pass in
2158 * link_speeds_bitmap include multiple speeds.
2160 * Each entry in this [phy_type_low, phy_type_high] structure will
2161 * present a certain link speed. This helper function will turn on bits
2162 * in [phy_type_low, phy_type_high] structure based on the value of
2163 * link_speeds_bitmap input parameter.
2166 ice_update_phy_type(u64 *phy_type_low, u64 *phy_type_high,
2167 u16 link_speeds_bitmap)
2169 u16 speed = ICE_AQ_LINK_SPEED_UNKNOWN;
2174 /* We first check with low part of phy_type */
2175 for (index = 0; index <= ICE_PHY_TYPE_LOW_MAX_INDEX; index++) {
2176 pt_low = BIT_ULL(index);
2177 speed = ice_get_link_speed_based_on_phy_type(pt_low, 0);
2179 if (link_speeds_bitmap & speed)
2180 *phy_type_low |= BIT_ULL(index);
2183 /* We then check with high part of phy_type */
2184 for (index = 0; index <= ICE_PHY_TYPE_HIGH_MAX_INDEX; index++) {
2185 pt_high = BIT_ULL(index);
2186 speed = ice_get_link_speed_based_on_phy_type(0, pt_high);
2188 if (link_speeds_bitmap & speed)
2189 *phy_type_high |= BIT_ULL(index);
2194 * ice_aq_set_phy_cfg
2195 * @hw: pointer to the hw struct
2196 * @lport: logical port number
2197 * @cfg: structure with PHY configuration data to be set
2198 * @cd: pointer to command details structure or NULL
2200 * Set the various PHY configuration parameters supported on the Port.
2201 * One or more of the Set PHY config parameters may be ignored in an MFP
2202 * mode as the PF may not have the privilege to set some of the PHY Config
2203 * parameters. This status will be indicated by the command response (0x0601).
2206 ice_aq_set_phy_cfg(struct ice_hw *hw, u8 lport,
2207 struct ice_aqc_set_phy_cfg_data *cfg, struct ice_sq_cd *cd)
2209 struct ice_aq_desc desc;
2212 return ICE_ERR_PARAM;
2214 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_phy_cfg);
2215 desc.params.set_phy.lport_num = lport;
2216 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
2218 return ice_aq_send_cmd(hw, &desc, cfg, sizeof(*cfg), cd);
2222 * ice_update_link_info - update status of the HW network link
2223 * @pi: port info structure of the interested logical port
2225 enum ice_status ice_update_link_info(struct ice_port_info *pi)
2227 struct ice_aqc_get_phy_caps_data *pcaps;
2228 struct ice_phy_info *phy_info;
2229 enum ice_status status;
2233 return ICE_ERR_PARAM;
2237 pcaps = (struct ice_aqc_get_phy_caps_data *)
2238 ice_malloc(hw, sizeof(*pcaps));
2240 return ICE_ERR_NO_MEMORY;
2242 phy_info = &pi->phy;
2243 status = ice_aq_get_link_info(pi, true, NULL, NULL);
2247 if (phy_info->link_info.link_info & ICE_AQ_MEDIA_AVAILABLE) {
2248 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_SW_CFG,
2253 ice_memcpy(phy_info->link_info.module_type, &pcaps->module_type,
2254 sizeof(phy_info->link_info.module_type),
2255 ICE_NONDMA_TO_NONDMA);
2258 ice_free(hw, pcaps);
2264 * @pi: port information structure
2265 * @aq_failures: pointer to status code, specific to ice_set_fc routine
2266 * @ena_auto_link_update: enable automatic link update
2268 * Set the requested flow control mode.
2271 ice_set_fc(struct ice_port_info *pi, u8 *aq_failures, bool ena_auto_link_update)
2273 struct ice_aqc_set_phy_cfg_data cfg = { 0 };
2274 struct ice_aqc_get_phy_caps_data *pcaps;
2275 enum ice_status status;
2276 u8 pause_mask = 0x0;
2280 return ICE_ERR_PARAM;
2282 *aq_failures = ICE_SET_FC_AQ_FAIL_NONE;
2284 switch (pi->fc.req_mode) {
2286 pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE;
2287 pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE;
2289 case ICE_FC_RX_PAUSE:
2290 pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE;
2292 case ICE_FC_TX_PAUSE:
2293 pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE;
2299 pcaps = (struct ice_aqc_get_phy_caps_data *)
2300 ice_malloc(hw, sizeof(*pcaps));
2302 return ICE_ERR_NO_MEMORY;
2304 /* Get the current phy config */
2305 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_SW_CFG, pcaps,
2308 *aq_failures = ICE_SET_FC_AQ_FAIL_GET;
2312 /* clear the old pause settings */
2313 cfg.caps = pcaps->caps & ~(ICE_AQC_PHY_EN_TX_LINK_PAUSE |
2314 ICE_AQC_PHY_EN_RX_LINK_PAUSE);
2315 /* set the new capabilities */
2316 cfg.caps |= pause_mask;
2317 /* If the capabilities have changed, then set the new config */
2318 if (cfg.caps != pcaps->caps) {
2319 int retry_count, retry_max = 10;
2321 /* Auto restart link so settings take effect */
2322 if (ena_auto_link_update)
2323 cfg.caps |= ICE_AQ_PHY_ENA_AUTO_LINK_UPDT;
2324 /* Copy over all the old settings */
2325 cfg.phy_type_high = pcaps->phy_type_high;
2326 cfg.phy_type_low = pcaps->phy_type_low;
2327 cfg.low_power_ctrl = pcaps->low_power_ctrl;
2328 cfg.eee_cap = pcaps->eee_cap;
2329 cfg.eeer_value = pcaps->eeer_value;
2330 cfg.link_fec_opt = pcaps->link_fec_options;
2332 status = ice_aq_set_phy_cfg(hw, pi->lport, &cfg, NULL);
2334 *aq_failures = ICE_SET_FC_AQ_FAIL_SET;
2338 /* Update the link info
2339 * It sometimes takes a really long time for link to
2340 * come back from the atomic reset. Thus, we wait a
2343 for (retry_count = 0; retry_count < retry_max; retry_count++) {
2344 status = ice_update_link_info(pi);
2346 if (status == ICE_SUCCESS)
2349 ice_msec_delay(100, true);
2353 *aq_failures = ICE_SET_FC_AQ_FAIL_UPDATE;
2357 ice_free(hw, pcaps);
2362 * ice_copy_phy_caps_to_cfg - Copy PHY ability data to configuration data
2363 * @caps: PHY ability structure to copy date from
2364 * @cfg: PHY configuration structure to copy data to
2366 * Helper function to copy AQC PHY get ability data to PHY set configuration
2370 ice_copy_phy_caps_to_cfg(struct ice_aqc_get_phy_caps_data *caps,
2371 struct ice_aqc_set_phy_cfg_data *cfg)
2376 cfg->phy_type_low = caps->phy_type_low;
2377 cfg->phy_type_high = caps->phy_type_high;
2378 cfg->caps = caps->caps;
2379 cfg->low_power_ctrl = caps->low_power_ctrl;
2380 cfg->eee_cap = caps->eee_cap;
2381 cfg->eeer_value = caps->eeer_value;
2382 cfg->link_fec_opt = caps->link_fec_options;
2386 * ice_cfg_phy_fec - Configure PHY FEC data based on FEC mode
2387 * @cfg: PHY configuration data to set FEC mode
2388 * @fec: FEC mode to configure
2390 * Caller should copy ice_aqc_get_phy_caps_data.caps ICE_AQC_PHY_EN_AUTO_FEC
2391 * (bit 7) and ice_aqc_get_phy_caps_data.link_fec_options to cfg.caps
2392 * ICE_AQ_PHY_ENA_AUTO_FEC (bit 7) and cfg.link_fec_options before calling.
2395 ice_cfg_phy_fec(struct ice_aqc_set_phy_cfg_data *cfg, enum ice_fec_mode fec)
2399 /* Clear auto FEC and RS bits, and AND BASE-R ability
2400 * bits and OR request bits.
2402 cfg->caps &= ~ICE_AQC_PHY_EN_AUTO_FEC;
2403 cfg->link_fec_opt &= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN |
2404 ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN;
2405 cfg->link_fec_opt |= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ |
2406 ICE_AQC_PHY_FEC_25G_KR_REQ;
2409 /* Clear auto FEC and BASE-R bits, and AND RS ability
2410 * bits and OR request bits.
2412 cfg->caps &= ~ICE_AQC_PHY_EN_AUTO_FEC;
2413 cfg->link_fec_opt &= ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN;
2414 cfg->link_fec_opt |= ICE_AQC_PHY_FEC_25G_RS_528_REQ |
2415 ICE_AQC_PHY_FEC_25G_RS_544_REQ;
2418 /* Clear auto FEC and all FEC option bits. */
2419 cfg->caps &= ~ICE_AQC_PHY_EN_AUTO_FEC;
2420 cfg->link_fec_opt &= ~ICE_AQC_PHY_FEC_MASK;
2423 /* AND auto FEC bit, and all caps bits. */
2424 cfg->caps &= ICE_AQC_PHY_CAPS_MASK;
2430 * ice_get_link_status - get status of the HW network link
2431 * @pi: port information structure
2432 * @link_up: pointer to bool (true/false = linkup/linkdown)
2434 * Variable link_up is true if link is up, false if link is down.
2435 * The variable link_up is invalid if status is non zero. As a
2436 * result of this call, link status reporting becomes enabled
2438 enum ice_status ice_get_link_status(struct ice_port_info *pi, bool *link_up)
2440 struct ice_phy_info *phy_info;
2441 enum ice_status status = ICE_SUCCESS;
2443 if (!pi || !link_up)
2444 return ICE_ERR_PARAM;
2446 phy_info = &pi->phy;
2448 if (phy_info->get_link_info) {
2449 status = ice_update_link_info(pi);
2452 ice_debug(pi->hw, ICE_DBG_LINK,
2453 "get link status error, status = %d\n",
2457 *link_up = phy_info->link_info.link_info & ICE_AQ_LINK_UP;
2463 * ice_aq_set_link_restart_an
2464 * @pi: pointer to the port information structure
2465 * @ena_link: if true: enable link, if false: disable link
2466 * @cd: pointer to command details structure or NULL
2468 * Sets up the link and restarts the Auto-Negotiation over the link.
2471 ice_aq_set_link_restart_an(struct ice_port_info *pi, bool ena_link,
2472 struct ice_sq_cd *cd)
2474 struct ice_aqc_restart_an *cmd;
2475 struct ice_aq_desc desc;
2477 cmd = &desc.params.restart_an;
2479 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_restart_an);
2481 cmd->cmd_flags = ICE_AQC_RESTART_AN_LINK_RESTART;
2482 cmd->lport_num = pi->lport;
2484 cmd->cmd_flags |= ICE_AQC_RESTART_AN_LINK_ENABLE;
2486 cmd->cmd_flags &= ~ICE_AQC_RESTART_AN_LINK_ENABLE;
2488 return ice_aq_send_cmd(pi->hw, &desc, NULL, 0, cd);
2492 * ice_aq_set_event_mask
2493 * @hw: pointer to the hw struct
2494 * @port_num: port number of the physical function
2495 * @mask: event mask to be set
2496 * @cd: pointer to command details structure or NULL
2498 * Set event mask (0x0613)
2501 ice_aq_set_event_mask(struct ice_hw *hw, u8 port_num, u16 mask,
2502 struct ice_sq_cd *cd)
2504 struct ice_aqc_set_event_mask *cmd;
2505 struct ice_aq_desc desc;
2507 cmd = &desc.params.set_event_mask;
2509 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_event_mask);
2511 cmd->lport_num = port_num;
2513 cmd->event_mask = CPU_TO_LE16(mask);
2514 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
2518 * ice_aq_set_mac_loopback
2519 * @hw: pointer to the hw struct
2520 * @ena_lpbk: Enable or Disable loopback
2521 * @cd: pointer to command details structure or NULL
2523 * Enable/disable loopback on a given port
2526 ice_aq_set_mac_loopback(struct ice_hw *hw, bool ena_lpbk, struct ice_sq_cd *cd)
2528 struct ice_aqc_set_mac_lb *cmd;
2529 struct ice_aq_desc desc;
2531 cmd = &desc.params.set_mac_lb;
2533 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_mac_lb);
2535 cmd->lb_mode = ICE_AQ_MAC_LB_EN;
2537 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
2542 * ice_aq_set_port_id_led
2543 * @pi: pointer to the port information
2544 * @is_orig_mode: is this LED set to original mode (by the net-list)
2545 * @cd: pointer to command details structure or NULL
2547 * Set LED value for the given port (0x06e9)
2550 ice_aq_set_port_id_led(struct ice_port_info *pi, bool is_orig_mode,
2551 struct ice_sq_cd *cd)
2553 struct ice_aqc_set_port_id_led *cmd;
2554 struct ice_hw *hw = pi->hw;
2555 struct ice_aq_desc desc;
2557 cmd = &desc.params.set_port_id_led;
2559 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_port_id_led);
2563 cmd->ident_mode = ICE_AQC_PORT_IDENT_LED_ORIG;
2565 cmd->ident_mode = ICE_AQC_PORT_IDENT_LED_BLINK;
2567 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
2571 * __ice_aq_get_set_rss_lut
2572 * @hw: pointer to the hardware structure
2573 * @vsi_id: VSI FW index
2574 * @lut_type: LUT table type
2575 * @lut: pointer to the LUT buffer provided by the caller
2576 * @lut_size: size of the LUT buffer
2577 * @glob_lut_idx: global LUT index
2578 * @set: set true to set the table, false to get the table
2580 * Internal function to get (0x0B05) or set (0x0B03) RSS look up table
2582 static enum ice_status
2583 __ice_aq_get_set_rss_lut(struct ice_hw *hw, u16 vsi_id, u8 lut_type, u8 *lut,
2584 u16 lut_size, u8 glob_lut_idx, bool set)
2586 struct ice_aqc_get_set_rss_lut *cmd_resp;
2587 struct ice_aq_desc desc;
2588 enum ice_status status;
2591 cmd_resp = &desc.params.get_set_rss_lut;
2594 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_rss_lut);
2595 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
2597 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_rss_lut);
2600 cmd_resp->vsi_id = CPU_TO_LE16(((vsi_id <<
2601 ICE_AQC_GSET_RSS_LUT_VSI_ID_S) &
2602 ICE_AQC_GSET_RSS_LUT_VSI_ID_M) |
2603 ICE_AQC_GSET_RSS_LUT_VSI_VALID);
2606 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_VSI:
2607 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF:
2608 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL:
2609 flags |= ((lut_type << ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S) &
2610 ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_M);
2613 status = ICE_ERR_PARAM;
2614 goto ice_aq_get_set_rss_lut_exit;
2617 if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL) {
2618 flags |= ((glob_lut_idx << ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S) &
2619 ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_M);
2622 goto ice_aq_get_set_rss_lut_send;
2623 } else if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF) {
2625 goto ice_aq_get_set_rss_lut_send;
2627 goto ice_aq_get_set_rss_lut_send;
2630 /* LUT size is only valid for Global and PF table types */
2632 case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128:
2633 flags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128_FLAG <<
2634 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) &
2635 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M;
2637 case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512:
2638 flags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512_FLAG <<
2639 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) &
2640 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M;
2642 case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K:
2643 if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF) {
2644 flags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K_FLAG <<
2645 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) &
2646 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M;
2651 status = ICE_ERR_PARAM;
2652 goto ice_aq_get_set_rss_lut_exit;
2655 ice_aq_get_set_rss_lut_send:
2656 cmd_resp->flags = CPU_TO_LE16(flags);
2657 status = ice_aq_send_cmd(hw, &desc, lut, lut_size, NULL);
2659 ice_aq_get_set_rss_lut_exit:
2664 * ice_aq_get_rss_lut
2665 * @hw: pointer to the hardware structure
2666 * @vsi_handle: software VSI handle
2667 * @lut_type: LUT table type
2668 * @lut: pointer to the LUT buffer provided by the caller
2669 * @lut_size: size of the LUT buffer
2671 * get the RSS lookup table, PF or VSI type
2674 ice_aq_get_rss_lut(struct ice_hw *hw, u16 vsi_handle, u8 lut_type,
2675 u8 *lut, u16 lut_size)
2677 if (!ice_is_vsi_valid(hw, vsi_handle) || !lut)
2678 return ICE_ERR_PARAM;
2680 return __ice_aq_get_set_rss_lut(hw, ice_get_hw_vsi_num(hw, vsi_handle),
2681 lut_type, lut, lut_size, 0, false);
2685 * ice_aq_set_rss_lut
2686 * @hw: pointer to the hardware structure
2687 * @vsi_handle: software VSI handle
2688 * @lut_type: LUT table type
2689 * @lut: pointer to the LUT buffer provided by the caller
2690 * @lut_size: size of the LUT buffer
2692 * set the RSS lookup table, PF or VSI type
2695 ice_aq_set_rss_lut(struct ice_hw *hw, u16 vsi_handle, u8 lut_type,
2696 u8 *lut, u16 lut_size)
2698 if (!ice_is_vsi_valid(hw, vsi_handle) || !lut)
2699 return ICE_ERR_PARAM;
2701 return __ice_aq_get_set_rss_lut(hw, ice_get_hw_vsi_num(hw, vsi_handle),
2702 lut_type, lut, lut_size, 0, true);
2706 * __ice_aq_get_set_rss_key
2707 * @hw: pointer to the hw struct
2708 * @vsi_id: VSI FW index
2709 * @key: pointer to key info struct
2710 * @set: set true to set the key, false to get the key
2712 * get (0x0B04) or set (0x0B02) the RSS key per VSI
2715 ice_status __ice_aq_get_set_rss_key(struct ice_hw *hw, u16 vsi_id,
2716 struct ice_aqc_get_set_rss_keys *key,
2719 struct ice_aqc_get_set_rss_key *cmd_resp;
2720 u16 key_size = sizeof(*key);
2721 struct ice_aq_desc desc;
2723 cmd_resp = &desc.params.get_set_rss_key;
2726 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_rss_key);
2727 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
2729 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_rss_key);
2732 cmd_resp->vsi_id = CPU_TO_LE16(((vsi_id <<
2733 ICE_AQC_GSET_RSS_KEY_VSI_ID_S) &
2734 ICE_AQC_GSET_RSS_KEY_VSI_ID_M) |
2735 ICE_AQC_GSET_RSS_KEY_VSI_VALID);
2737 return ice_aq_send_cmd(hw, &desc, key, key_size, NULL);
2741 * ice_aq_get_rss_key
2742 * @hw: pointer to the hw struct
2743 * @vsi_handle: software VSI handle
2744 * @key: pointer to key info struct
2746 * get the RSS key per VSI
2749 ice_aq_get_rss_key(struct ice_hw *hw, u16 vsi_handle,
2750 struct ice_aqc_get_set_rss_keys *key)
2752 if (!ice_is_vsi_valid(hw, vsi_handle) || !key)
2753 return ICE_ERR_PARAM;
2755 return __ice_aq_get_set_rss_key(hw, ice_get_hw_vsi_num(hw, vsi_handle),
2760 * ice_aq_set_rss_key
2761 * @hw: pointer to the hw struct
2762 * @vsi_handle: software VSI handle
2763 * @keys: pointer to key info struct
2765 * set the RSS key per VSI
2768 ice_aq_set_rss_key(struct ice_hw *hw, u16 vsi_handle,
2769 struct ice_aqc_get_set_rss_keys *keys)
2771 if (!ice_is_vsi_valid(hw, vsi_handle) || !keys)
2772 return ICE_ERR_PARAM;
2774 return __ice_aq_get_set_rss_key(hw, ice_get_hw_vsi_num(hw, vsi_handle),
2779 * ice_aq_add_lan_txq
2780 * @hw: pointer to the hardware structure
2781 * @num_qgrps: Number of added queue groups
2782 * @qg_list: list of queue groups to be added
2783 * @buf_size: size of buffer for indirect command
2784 * @cd: pointer to command details structure or NULL
2786 * Add Tx LAN queue (0x0C30)
2789 * Prior to calling add Tx LAN queue:
2790 * Initialize the following as part of the Tx queue context:
2791 * Completion queue ID if the queue uses Completion queue, Quanta profile,
2792 * Cache profile and Packet shaper profile.
2794 * After add Tx LAN queue AQ command is completed:
2795 * Interrupts should be associated with specific queues,
2796 * Association of Tx queue to Doorbell queue is not part of Add LAN Tx queue
2799 static enum ice_status
2800 ice_aq_add_lan_txq(struct ice_hw *hw, u8 num_qgrps,
2801 struct ice_aqc_add_tx_qgrp *qg_list, u16 buf_size,
2802 struct ice_sq_cd *cd)
2804 u16 i, sum_header_size, sum_q_size = 0;
2805 struct ice_aqc_add_tx_qgrp *list;
2806 struct ice_aqc_add_txqs *cmd;
2807 struct ice_aq_desc desc;
2809 ice_debug(hw, ICE_DBG_TRACE, "ice_aq_add_lan_txq");
2811 cmd = &desc.params.add_txqs;
2813 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_add_txqs);
2816 return ICE_ERR_PARAM;
2818 if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS)
2819 return ICE_ERR_PARAM;
2821 sum_header_size = num_qgrps *
2822 (sizeof(*qg_list) - sizeof(*qg_list->txqs));
2825 for (i = 0; i < num_qgrps; i++) {
2826 struct ice_aqc_add_txqs_perq *q = list->txqs;
2828 sum_q_size += list->num_txqs * sizeof(*q);
2829 list = (struct ice_aqc_add_tx_qgrp *)(q + list->num_txqs);
2832 if (buf_size != (sum_header_size + sum_q_size))
2833 return ICE_ERR_PARAM;
2835 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
2837 cmd->num_qgrps = num_qgrps;
2839 return ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd);
2843 * ice_aq_dis_lan_txq
2844 * @hw: pointer to the hardware structure
2845 * @num_qgrps: number of groups in the list
2846 * @qg_list: the list of groups to disable
2847 * @buf_size: the total size of the qg_list buffer in bytes
2848 * @rst_src: if called due to reset, specifies the rst source
2849 * @vmvf_num: the relative vm or vf number that is undergoing the reset
2850 * @cd: pointer to command details structure or NULL
2852 * Disable LAN Tx queue (0x0C31)
2854 static enum ice_status
2855 ice_aq_dis_lan_txq(struct ice_hw *hw, u8 num_qgrps,
2856 struct ice_aqc_dis_txq_item *qg_list, u16 buf_size,
2857 enum ice_disq_rst_src rst_src, u16 vmvf_num,
2858 struct ice_sq_cd *cd)
2860 struct ice_aqc_dis_txqs *cmd;
2861 struct ice_aq_desc desc;
2862 enum ice_status status;
2865 ice_debug(hw, ICE_DBG_TRACE, "ice_aq_dis_lan_txq");
2866 cmd = &desc.params.dis_txqs;
2867 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_dis_txqs);
2869 /* qg_list can be NULL only in VM/VF reset flow */
2870 if (!qg_list && !rst_src)
2871 return ICE_ERR_PARAM;
2873 if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS)
2874 return ICE_ERR_PARAM;
2876 cmd->num_entries = num_qgrps;
2878 cmd->vmvf_and_timeout = CPU_TO_LE16((5 << ICE_AQC_Q_DIS_TIMEOUT_S) &
2879 ICE_AQC_Q_DIS_TIMEOUT_M);
2883 cmd->cmd_type = ICE_AQC_Q_DIS_CMD_VM_RESET;
2884 cmd->vmvf_and_timeout |=
2885 CPU_TO_LE16(vmvf_num & ICE_AQC_Q_DIS_VMVF_NUM_M);
2892 /* flush pipe on time out */
2893 cmd->cmd_type |= ICE_AQC_Q_DIS_CMD_FLUSH_PIPE;
2894 /* If no queue group info, we are in a reset flow. Issue the AQ */
2898 /* set RD bit to indicate that command buffer is provided by the driver
2899 * and it needs to be read by the firmware
2901 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
2903 for (i = 0; i < num_qgrps; ++i) {
2904 /* Calculate the size taken up by the queue IDs in this group */
2905 sz += qg_list[i].num_qs * sizeof(qg_list[i].q_id);
2907 /* Add the size of the group header */
2908 sz += sizeof(qg_list[i]) - sizeof(qg_list[i].q_id);
2910 /* If the num of queues is even, add 2 bytes of padding */
2911 if ((qg_list[i].num_qs % 2) == 0)
2916 return ICE_ERR_PARAM;
2919 status = ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd);
2922 ice_debug(hw, ICE_DBG_SCHED, "VM%d disable failed %d\n",
2923 vmvf_num, hw->adminq.sq_last_status);
2925 ice_debug(hw, ICE_DBG_SCHED, "disable Q %d failed %d\n",
2926 LE16_TO_CPU(qg_list[0].q_id[0]),
2927 hw->adminq.sq_last_status);
2933 /* End of FW Admin Queue command wrappers */
2936 * ice_write_byte - write a byte to a packed context structure
2937 * @src_ctx: the context structure to read from
2938 * @dest_ctx: the context to be written to
2939 * @ce_info: a description of the struct to be filled
2942 ice_write_byte(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)
2944 u8 src_byte, dest_byte, mask;
2948 /* copy from the next struct field */
2949 from = src_ctx + ce_info->offset;
2951 /* prepare the bits and mask */
2952 shift_width = ce_info->lsb % 8;
2953 mask = (u8)(BIT(ce_info->width) - 1);
2958 /* shift to correct alignment */
2959 mask <<= shift_width;
2960 src_byte <<= shift_width;
2962 /* get the current bits from the target bit string */
2963 dest = dest_ctx + (ce_info->lsb / 8);
2965 ice_memcpy(&dest_byte, dest, sizeof(dest_byte), ICE_DMA_TO_NONDMA);
2967 dest_byte &= ~mask; /* get the bits not changing */
2968 dest_byte |= src_byte; /* add in the new bits */
2970 /* put it all back */
2971 ice_memcpy(dest, &dest_byte, sizeof(dest_byte), ICE_NONDMA_TO_DMA);
2975 * ice_write_word - write a word to a packed context structure
2976 * @src_ctx: the context structure to read from
2977 * @dest_ctx: the context to be written to
2978 * @ce_info: a description of the struct to be filled
2981 ice_write_word(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)
2988 /* copy from the next struct field */
2989 from = src_ctx + ce_info->offset;
2991 /* prepare the bits and mask */
2992 shift_width = ce_info->lsb % 8;
2993 mask = BIT(ce_info->width) - 1;
2995 /* don't swizzle the bits until after the mask because the mask bits
2996 * will be in a different bit position on big endian machines
2998 src_word = *(u16 *)from;
3001 /* shift to correct alignment */
3002 mask <<= shift_width;
3003 src_word <<= shift_width;
3005 /* get the current bits from the target bit string */
3006 dest = dest_ctx + (ce_info->lsb / 8);
3008 ice_memcpy(&dest_word, dest, sizeof(dest_word), ICE_DMA_TO_NONDMA);
3010 dest_word &= ~(CPU_TO_LE16(mask)); /* get the bits not changing */
3011 dest_word |= CPU_TO_LE16(src_word); /* add in the new bits */
3013 /* put it all back */
3014 ice_memcpy(dest, &dest_word, sizeof(dest_word), ICE_NONDMA_TO_DMA);
3018 * ice_write_dword - write a dword to a packed context structure
3019 * @src_ctx: the context structure to read from
3020 * @dest_ctx: the context to be written to
3021 * @ce_info: a description of the struct to be filled
3024 ice_write_dword(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)
3026 u32 src_dword, mask;
3031 /* copy from the next struct field */
3032 from = src_ctx + ce_info->offset;
3034 /* prepare the bits and mask */
3035 shift_width = ce_info->lsb % 8;
3037 /* if the field width is exactly 32 on an x86 machine, then the shift
3038 * operation will not work because the SHL instructions count is masked
3039 * to 5 bits so the shift will do nothing
3041 if (ce_info->width < 32)
3042 mask = BIT(ce_info->width) - 1;
3046 /* don't swizzle the bits until after the mask because the mask bits
3047 * will be in a different bit position on big endian machines
3049 src_dword = *(u32 *)from;
3052 /* shift to correct alignment */
3053 mask <<= shift_width;
3054 src_dword <<= shift_width;
3056 /* get the current bits from the target bit string */
3057 dest = dest_ctx + (ce_info->lsb / 8);
3059 ice_memcpy(&dest_dword, dest, sizeof(dest_dword), ICE_DMA_TO_NONDMA);
3061 dest_dword &= ~(CPU_TO_LE32(mask)); /* get the bits not changing */
3062 dest_dword |= CPU_TO_LE32(src_dword); /* add in the new bits */
3064 /* put it all back */
3065 ice_memcpy(dest, &dest_dword, sizeof(dest_dword), ICE_NONDMA_TO_DMA);
3069 * ice_write_qword - write a qword to a packed context structure
3070 * @src_ctx: the context structure to read from
3071 * @dest_ctx: the context to be written to
3072 * @ce_info: a description of the struct to be filled
3075 ice_write_qword(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)
3077 u64 src_qword, mask;
3082 /* copy from the next struct field */
3083 from = src_ctx + ce_info->offset;
3085 /* prepare the bits and mask */
3086 shift_width = ce_info->lsb % 8;
3088 /* if the field width is exactly 64 on an x86 machine, then the shift
3089 * operation will not work because the SHL instructions count is masked
3090 * to 6 bits so the shift will do nothing
3092 if (ce_info->width < 64)
3093 mask = BIT_ULL(ce_info->width) - 1;
3097 /* don't swizzle the bits until after the mask because the mask bits
3098 * will be in a different bit position on big endian machines
3100 src_qword = *(u64 *)from;
3103 /* shift to correct alignment */
3104 mask <<= shift_width;
3105 src_qword <<= shift_width;
3107 /* get the current bits from the target bit string */
3108 dest = dest_ctx + (ce_info->lsb / 8);
3110 ice_memcpy(&dest_qword, dest, sizeof(dest_qword), ICE_DMA_TO_NONDMA);
3112 dest_qword &= ~(CPU_TO_LE64(mask)); /* get the bits not changing */
3113 dest_qword |= CPU_TO_LE64(src_qword); /* add in the new bits */
3115 /* put it all back */
3116 ice_memcpy(dest, &dest_qword, sizeof(dest_qword), ICE_NONDMA_TO_DMA);
3120 * ice_set_ctx - set context bits in packed structure
3121 * @src_ctx: pointer to a generic non-packed context structure
3122 * @dest_ctx: pointer to memory for the packed structure
3123 * @ce_info: a description of the structure to be transformed
3126 ice_set_ctx(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)
3130 for (f = 0; ce_info[f].width; f++) {
3131 /* We have to deal with each element of the FW response
3132 * using the correct size so that we are correct regardless
3133 * of the endianness of the machine.
3135 switch (ce_info[f].size_of) {
3137 ice_write_byte(src_ctx, dest_ctx, &ce_info[f]);
3140 ice_write_word(src_ctx, dest_ctx, &ce_info[f]);
3143 ice_write_dword(src_ctx, dest_ctx, &ce_info[f]);
3146 ice_write_qword(src_ctx, dest_ctx, &ce_info[f]);
3149 return ICE_ERR_INVAL_SIZE;
3162 * @pi: port information structure
3163 * @vsi_handle: software VSI handle
3165 * @num_qgrps: Number of added queue groups
3166 * @buf: list of queue groups to be added
3167 * @buf_size: size of buffer for indirect command
3168 * @cd: pointer to command details structure or NULL
3170 * This function adds one lan q
3173 ice_ena_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u8 num_qgrps,
3174 struct ice_aqc_add_tx_qgrp *buf, u16 buf_size,
3175 struct ice_sq_cd *cd)
3177 struct ice_aqc_txsched_elem_data node = { 0 };
3178 struct ice_sched_node *parent;
3179 enum ice_status status;
3182 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY)
3185 if (num_qgrps > 1 || buf->num_txqs > 1)
3186 return ICE_ERR_MAX_LIMIT;
3190 if (!ice_is_vsi_valid(hw, vsi_handle))
3191 return ICE_ERR_PARAM;
3193 ice_acquire_lock(&pi->sched_lock);
3195 /* find a parent node */
3196 parent = ice_sched_get_free_qparent(pi, vsi_handle, tc,
3197 ICE_SCHED_NODE_OWNER_LAN);
3199 status = ICE_ERR_PARAM;
3203 buf->parent_teid = parent->info.node_teid;
3204 node.parent_teid = parent->info.node_teid;
3205 /* Mark that the values in the "generic" section as valid. The default
3206 * value in the "generic" section is zero. This means that :
3207 * - Scheduling mode is Bytes Per Second (BPS), indicated by Bit 0.
3208 * - 0 priority among siblings, indicated by Bit 1-3.
3209 * - WFQ, indicated by Bit 4.
3210 * - 0 Adjustment value is used in PSM credit update flow, indicated by
3212 * - Bit 7 is reserved.
3213 * Without setting the generic section as valid in valid_sections, the
3214 * Admin Q command will fail with error code ICE_AQ_RC_EINVAL.
3216 buf->txqs[0].info.valid_sections = ICE_AQC_ELEM_VALID_GENERIC;
3219 status = ice_aq_add_lan_txq(hw, num_qgrps, buf, buf_size, cd);
3220 if (status != ICE_SUCCESS) {
3221 ice_debug(hw, ICE_DBG_SCHED, "enable Q %d failed %d\n",
3222 LE16_TO_CPU(buf->txqs[0].txq_id),
3223 hw->adminq.sq_last_status);
3227 node.node_teid = buf->txqs[0].q_teid;
3228 node.data.elem_type = ICE_AQC_ELEM_TYPE_LEAF;
3230 /* add a leaf node into schduler tree q layer */
3231 status = ice_sched_add_node(pi, hw->num_tx_sched_layers - 1, &node);
3234 ice_release_lock(&pi->sched_lock);
3240 * @pi: port information structure
3241 * @num_queues: number of queues
3242 * @q_ids: pointer to the q_id array
3243 * @q_teids: pointer to queue node teids
3244 * @rst_src: if called due to reset, specifies the rst source
3245 * @vmvf_num: the relative vm or vf number that is undergoing the reset
3246 * @cd: pointer to command details structure or NULL
3248 * This function removes queues and their corresponding nodes in SW DB
3251 ice_dis_vsi_txq(struct ice_port_info *pi, u8 num_queues, u16 *q_ids,
3252 u32 *q_teids, enum ice_disq_rst_src rst_src, u16 vmvf_num,
3253 struct ice_sq_cd *cd)
3255 enum ice_status status = ICE_ERR_DOES_NOT_EXIST;
3256 struct ice_aqc_dis_txq_item qg_list;
3259 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY)
3262 /* if queue is disabled already yet the disable queue command has to be
3263 * sent to complete the VF reset, then call ice_aq_dis_lan_txq without
3264 * any queue information
3267 if (!num_queues && rst_src)
3268 return ice_aq_dis_lan_txq(pi->hw, 0, NULL, 0, rst_src, vmvf_num,
3271 ice_acquire_lock(&pi->sched_lock);
3273 for (i = 0; i < num_queues; i++) {
3274 struct ice_sched_node *node;
3276 node = ice_sched_find_node_by_teid(pi->root, q_teids[i]);
3279 qg_list.parent_teid = node->info.parent_teid;
3281 qg_list.q_id[0] = CPU_TO_LE16(q_ids[i]);
3282 status = ice_aq_dis_lan_txq(pi->hw, 1, &qg_list,
3283 sizeof(qg_list), rst_src, vmvf_num,
3286 if (status != ICE_SUCCESS)
3288 ice_free_sched_node(pi, node);
3290 ice_release_lock(&pi->sched_lock);
3295 * ice_cfg_vsi_qs - configure the new/exisiting VSI queues
3296 * @pi: port information structure
3297 * @vsi_handle: software VSI handle
3298 * @tc_bitmap: TC bitmap
3299 * @maxqs: max queues array per TC
3300 * @owner: lan or rdma
3302 * This function adds/updates the VSI queues per TC.
3304 static enum ice_status
3305 ice_cfg_vsi_qs(struct ice_port_info *pi, u16 vsi_handle, u8 tc_bitmap,
3306 u16 *maxqs, u8 owner)
3308 enum ice_status status = ICE_SUCCESS;
3311 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY)
3314 if (!ice_is_vsi_valid(pi->hw, vsi_handle))
3315 return ICE_ERR_PARAM;
3317 ice_acquire_lock(&pi->sched_lock);
3319 for (i = 0; i < ICE_MAX_TRAFFIC_CLASS; i++) {
3320 /* configuration is possible only if TC node is present */
3321 if (!ice_sched_get_tc_node(pi, i))
3324 status = ice_sched_cfg_vsi(pi, vsi_handle, i, maxqs[i], owner,
3325 ice_is_tc_ena(tc_bitmap, i));
3330 ice_release_lock(&pi->sched_lock);
3335 * ice_cfg_vsi_lan - configure VSI lan queues
3336 * @pi: port information structure
3337 * @vsi_handle: software VSI handle
3338 * @tc_bitmap: TC bitmap
3339 * @max_lanqs: max lan queues array per TC
3341 * This function adds/updates the VSI lan queues per TC.
3344 ice_cfg_vsi_lan(struct ice_port_info *pi, u16 vsi_handle, u8 tc_bitmap,
3347 return ice_cfg_vsi_qs(pi, vsi_handle, tc_bitmap, max_lanqs,
3348 ICE_SCHED_NODE_OWNER_LAN);
3354 * ice_replay_pre_init - replay pre initialization
3355 * @hw: pointer to the hw struct
3357 * Initializes required config data for VSI, FD, ACL, and RSS before replay.
3359 static enum ice_status ice_replay_pre_init(struct ice_hw *hw)
3361 struct ice_switch_info *sw = hw->switch_info;
3364 /* Delete old entries from replay filter list head if there is any */
3365 ice_rm_all_sw_replay_rule_info(hw);
3366 /* In start of replay, move entries into replay_rules list, it
3367 * will allow adding rules entries back to filt_rules list,
3368 * which is operational list.
3370 for (i = 0; i < ICE_MAX_NUM_RECIPES; i++)
3371 LIST_REPLACE_INIT(&sw->recp_list[i].filt_rules,
3372 &sw->recp_list[i].filt_replay_rules);
3373 ice_sched_replay_agg_vsi_preinit(hw);
3375 return ice_sched_replay_tc_node_bw(hw);
3379 * ice_replay_vsi - replay vsi configuration
3380 * @hw: pointer to the hw struct
3381 * @vsi_handle: driver vsi handle
3383 * Restore all VSI configuration after reset. It is required to call this
3384 * function with main VSI first.
3386 enum ice_status ice_replay_vsi(struct ice_hw *hw, u16 vsi_handle)
3388 enum ice_status status;
3390 if (!ice_is_vsi_valid(hw, vsi_handle))
3391 return ICE_ERR_PARAM;
3393 /* Replay pre-initialization if there is any */
3394 if (vsi_handle == ICE_MAIN_VSI_HANDLE) {
3395 status = ice_replay_pre_init(hw);
3400 /* Replay per VSI all filters */
3401 status = ice_replay_vsi_all_fltr(hw, vsi_handle);
3403 status = ice_replay_vsi_agg(hw, vsi_handle);
3408 * ice_replay_post - post replay configuration cleanup
3409 * @hw: pointer to the hw struct
3411 * Post replay cleanup.
3413 void ice_replay_post(struct ice_hw *hw)
3415 /* Delete old entries from replay filter list head */
3416 ice_rm_all_sw_replay_rule_info(hw);
3417 ice_sched_replay_agg(hw);
3421 * ice_stat_update40 - read 40 bit stat from the chip and update stat values
3422 * @hw: ptr to the hardware info
3423 * @hireg: high 32 bit HW register to read from
3424 * @loreg: low 32 bit HW register to read from
3425 * @prev_stat_loaded: bool to specify if previous stats are loaded
3426 * @prev_stat: ptr to previous loaded stat value
3427 * @cur_stat: ptr to current stat value
3430 ice_stat_update40(struct ice_hw *hw, u32 hireg, u32 loreg,
3431 bool prev_stat_loaded, u64 *prev_stat, u64 *cur_stat)
3435 new_data = rd32(hw, loreg);
3436 new_data |= ((u64)(rd32(hw, hireg) & 0xFFFF)) << 32;
3438 /* device stats are not reset at PFR, they likely will not be zeroed
3439 * when the driver starts. So save the first values read and use them as
3440 * offsets to be subtracted from the raw values in order to report stats
3441 * that count from zero.
3443 if (!prev_stat_loaded)
3444 *prev_stat = new_data;
3445 if (new_data >= *prev_stat)
3446 *cur_stat = new_data - *prev_stat;
3448 /* to manage the potential roll-over */
3449 *cur_stat = (new_data + BIT_ULL(40)) - *prev_stat;
3450 *cur_stat &= 0xFFFFFFFFFFULL;
3454 * ice_stat_update32 - read 32 bit stat from the chip and update stat values
3455 * @hw: ptr to the hardware info
3456 * @reg: HW register to read from
3457 * @prev_stat_loaded: bool to specify if previous stats are loaded
3458 * @prev_stat: ptr to previous loaded stat value
3459 * @cur_stat: ptr to current stat value
3462 ice_stat_update32(struct ice_hw *hw, u32 reg, bool prev_stat_loaded,
3463 u64 *prev_stat, u64 *cur_stat)
3467 new_data = rd32(hw, reg);
3469 /* device stats are not reset at PFR, they likely will not be zeroed
3470 * when the driver starts. So save the first values read and use them as
3471 * offsets to be subtracted from the raw values in order to report stats
3472 * that count from zero.
3474 if (!prev_stat_loaded)
3475 *prev_stat = new_data;
3476 if (new_data >= *prev_stat)
3477 *cur_stat = new_data - *prev_stat;
3479 /* to manage the potential roll-over */
3480 *cur_stat = (new_data + BIT_ULL(32)) - *prev_stat;
3485 * ice_sched_query_elem - query element information from hw
3486 * @hw: pointer to the hw struct
3487 * @node_teid: node teid to be queried
3488 * @buf: buffer to element information
3490 * This function queries HW element information
3493 ice_sched_query_elem(struct ice_hw *hw, u32 node_teid,
3494 struct ice_aqc_get_elem *buf)
3496 u16 buf_size, num_elem_ret = 0;
3497 enum ice_status status;
3499 buf_size = sizeof(*buf);
3500 ice_memset(buf, 0, buf_size, ICE_NONDMA_MEM);
3501 buf->generic[0].node_teid = CPU_TO_LE32(node_teid);
3502 status = ice_aq_query_sched_elems(hw, 1, buf, buf_size, &num_elem_ret,
3504 if (status != ICE_SUCCESS || num_elem_ret != 1)
3505 ice_debug(hw, ICE_DBG_SCHED, "query element failed\n");