1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2001-2019
5 #include "ice_common.h"
7 #include "ice_adminq_cmd.h"
10 #include "ice_switch.h"
12 #define ICE_PF_RESET_WAIT_COUNT 200
14 #define ICE_PROG_FLEX_ENTRY(hw, rxdid, mdid, idx) \
15 wr32((hw), GLFLXP_RXDID_FLX_WRD_##idx(rxdid), \
16 ((ICE_RX_OPC_MDID << \
17 GLFLXP_RXDID_FLX_WRD_##idx##_RXDID_OPCODE_S) & \
18 GLFLXP_RXDID_FLX_WRD_##idx##_RXDID_OPCODE_M) | \
19 (((mdid) << GLFLXP_RXDID_FLX_WRD_##idx##_PROT_MDID_S) & \
20 GLFLXP_RXDID_FLX_WRD_##idx##_PROT_MDID_M))
22 #define ICE_PROG_FLG_ENTRY(hw, rxdid, flg_0, flg_1, flg_2, flg_3, idx) \
23 wr32((hw), GLFLXP_RXDID_FLAGS(rxdid, idx), \
24 (((flg_0) << GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_S) & \
25 GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_M) | \
26 (((flg_1) << GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_1_S) & \
27 GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_1_M) | \
28 (((flg_2) << GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_2_S) & \
29 GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_2_M) | \
30 (((flg_3) << GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_3_S) & \
31 GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_3_M))
35 * ice_set_mac_type - Sets MAC type
36 * @hw: pointer to the HW structure
38 * This function sets the MAC type of the adapter based on the
39 * vendor ID and device ID stored in the HW structure.
41 static enum ice_status ice_set_mac_type(struct ice_hw *hw)
43 enum ice_status status = ICE_SUCCESS;
45 ice_debug(hw, ICE_DBG_TRACE, "ice_set_mac_type\n");
47 if (hw->vendor_id == ICE_INTEL_VENDOR_ID) {
48 switch (hw->device_id) {
50 hw->mac_type = ICE_MAC_GENERIC;
54 status = ICE_ERR_DEVICE_NOT_SUPPORTED;
57 ice_debug(hw, ICE_DBG_INIT, "found mac_type: %d, status: %d\n",
58 hw->mac_type, status);
65 * ice_clear_pf_cfg - Clear PF configuration
66 * @hw: pointer to the hardware structure
68 * Clears any existing PF configuration (VSIs, VSI lists, switch rules, port
69 * configuration, flow director filters, etc.).
71 enum ice_status ice_clear_pf_cfg(struct ice_hw *hw)
73 struct ice_aq_desc desc;
75 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pf_cfg);
77 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
81 * ice_aq_manage_mac_read - manage MAC address read command
82 * @hw: pointer to the HW struct
83 * @buf: a virtual buffer to hold the manage MAC read response
84 * @buf_size: Size of the virtual buffer
85 * @cd: pointer to command details structure or NULL
87 * This function is used to return per PF station MAC address (0x0107).
88 * NOTE: Upon successful completion of this command, MAC address information
89 * is returned in user specified buffer. Please interpret user specified
90 * buffer as "manage_mac_read" response.
91 * Response such as various MAC addresses are stored in HW struct (port.mac)
92 * ice_aq_discover_caps is expected to be called before this function is called.
94 static enum ice_status
95 ice_aq_manage_mac_read(struct ice_hw *hw, void *buf, u16 buf_size,
98 struct ice_aqc_manage_mac_read_resp *resp;
99 struct ice_aqc_manage_mac_read *cmd;
100 struct ice_aq_desc desc;
101 enum ice_status status;
105 cmd = &desc.params.mac_read;
107 if (buf_size < sizeof(*resp))
108 return ICE_ERR_BUF_TOO_SHORT;
110 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_read);
112 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);
116 resp = (struct ice_aqc_manage_mac_read_resp *)buf;
117 flags = LE16_TO_CPU(cmd->flags) & ICE_AQC_MAN_MAC_READ_M;
119 if (!(flags & ICE_AQC_MAN_MAC_LAN_ADDR_VALID)) {
120 ice_debug(hw, ICE_DBG_LAN, "got invalid MAC address\n");
124 /* A single port can report up to two (LAN and WoL) addresses */
125 for (i = 0; i < cmd->num_addr; i++)
126 if (resp[i].addr_type == ICE_AQC_MAN_MAC_ADDR_TYPE_LAN) {
127 ice_memcpy(hw->port_info->mac.lan_addr,
128 resp[i].mac_addr, ETH_ALEN,
130 ice_memcpy(hw->port_info->mac.perm_addr,
132 ETH_ALEN, ICE_DMA_TO_NONDMA);
140 * ice_aq_get_phy_caps - returns PHY capabilities
141 * @pi: port information structure
142 * @qual_mods: report qualified modules
143 * @report_mode: report mode capabilities
144 * @pcaps: structure for PHY capabilities to be filled
145 * @cd: pointer to command details structure or NULL
147 * Returns the various PHY capabilities supported on the Port (0x0600)
150 ice_aq_get_phy_caps(struct ice_port_info *pi, bool qual_mods, u8 report_mode,
151 struct ice_aqc_get_phy_caps_data *pcaps,
152 struct ice_sq_cd *cd)
154 struct ice_aqc_get_phy_caps *cmd;
155 u16 pcaps_size = sizeof(*pcaps);
156 struct ice_aq_desc desc;
157 enum ice_status status;
159 cmd = &desc.params.get_phy;
161 if (!pcaps || (report_mode & ~ICE_AQC_REPORT_MODE_M) || !pi)
162 return ICE_ERR_PARAM;
164 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_phy_caps);
167 cmd->param0 |= CPU_TO_LE16(ICE_AQC_GET_PHY_RQM);
169 cmd->param0 |= CPU_TO_LE16(report_mode);
170 status = ice_aq_send_cmd(pi->hw, &desc, pcaps, pcaps_size, cd);
172 if (status == ICE_SUCCESS && report_mode == ICE_AQC_REPORT_TOPO_CAP) {
173 pi->phy.phy_type_low = LE64_TO_CPU(pcaps->phy_type_low);
174 pi->phy.phy_type_high = LE64_TO_CPU(pcaps->phy_type_high);
181 * ice_get_media_type - Gets media type
182 * @pi: port information structure
184 static enum ice_media_type ice_get_media_type(struct ice_port_info *pi)
186 struct ice_link_status *hw_link_info;
189 return ICE_MEDIA_UNKNOWN;
191 hw_link_info = &pi->phy.link_info;
192 if (hw_link_info->phy_type_low && hw_link_info->phy_type_high)
193 /* If more than one media type is selected, report unknown */
194 return ICE_MEDIA_UNKNOWN;
196 if (hw_link_info->phy_type_low) {
197 switch (hw_link_info->phy_type_low) {
198 case ICE_PHY_TYPE_LOW_1000BASE_SX:
199 case ICE_PHY_TYPE_LOW_1000BASE_LX:
200 case ICE_PHY_TYPE_LOW_10GBASE_SR:
201 case ICE_PHY_TYPE_LOW_10GBASE_LR:
202 case ICE_PHY_TYPE_LOW_10G_SFI_C2C:
203 case ICE_PHY_TYPE_LOW_25GBASE_SR:
204 case ICE_PHY_TYPE_LOW_25GBASE_LR:
205 case ICE_PHY_TYPE_LOW_25G_AUI_C2C:
206 case ICE_PHY_TYPE_LOW_40GBASE_SR4:
207 case ICE_PHY_TYPE_LOW_40GBASE_LR4:
208 case ICE_PHY_TYPE_LOW_50GBASE_SR2:
209 case ICE_PHY_TYPE_LOW_50GBASE_LR2:
210 case ICE_PHY_TYPE_LOW_50GBASE_SR:
211 case ICE_PHY_TYPE_LOW_50GBASE_FR:
212 case ICE_PHY_TYPE_LOW_50GBASE_LR:
213 case ICE_PHY_TYPE_LOW_100GBASE_SR4:
214 case ICE_PHY_TYPE_LOW_100GBASE_LR4:
215 case ICE_PHY_TYPE_LOW_100GBASE_SR2:
216 case ICE_PHY_TYPE_LOW_100GBASE_DR:
217 return ICE_MEDIA_FIBER;
218 case ICE_PHY_TYPE_LOW_100BASE_TX:
219 case ICE_PHY_TYPE_LOW_1000BASE_T:
220 case ICE_PHY_TYPE_LOW_2500BASE_T:
221 case ICE_PHY_TYPE_LOW_5GBASE_T:
222 case ICE_PHY_TYPE_LOW_10GBASE_T:
223 case ICE_PHY_TYPE_LOW_25GBASE_T:
224 return ICE_MEDIA_BASET;
225 case ICE_PHY_TYPE_LOW_10G_SFI_DA:
226 case ICE_PHY_TYPE_LOW_25GBASE_CR:
227 case ICE_PHY_TYPE_LOW_25GBASE_CR_S:
228 case ICE_PHY_TYPE_LOW_25GBASE_CR1:
229 case ICE_PHY_TYPE_LOW_40GBASE_CR4:
230 case ICE_PHY_TYPE_LOW_50GBASE_CR2:
231 case ICE_PHY_TYPE_LOW_50GBASE_CP:
232 case ICE_PHY_TYPE_LOW_100GBASE_CR4:
233 case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4:
234 case ICE_PHY_TYPE_LOW_100GBASE_CP2:
236 case ICE_PHY_TYPE_LOW_1000BASE_KX:
237 case ICE_PHY_TYPE_LOW_2500BASE_KX:
238 case ICE_PHY_TYPE_LOW_2500BASE_X:
239 case ICE_PHY_TYPE_LOW_5GBASE_KR:
240 case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1:
241 case ICE_PHY_TYPE_LOW_25GBASE_KR:
242 case ICE_PHY_TYPE_LOW_25GBASE_KR1:
243 case ICE_PHY_TYPE_LOW_25GBASE_KR_S:
244 case ICE_PHY_TYPE_LOW_40GBASE_KR4:
245 case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4:
246 case ICE_PHY_TYPE_LOW_50GBASE_KR2:
247 case ICE_PHY_TYPE_LOW_100GBASE_KR4:
248 case ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4:
249 return ICE_MEDIA_BACKPLANE;
252 switch (hw_link_info->phy_type_high) {
253 case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4:
254 return ICE_MEDIA_BACKPLANE;
257 return ICE_MEDIA_UNKNOWN;
261 * ice_aq_get_link_info
262 * @pi: port information structure
263 * @ena_lse: enable/disable LinkStatusEvent reporting
264 * @link: pointer to link status structure - optional
265 * @cd: pointer to command details structure or NULL
267 * Get Link Status (0x607). Returns the link status of the adapter.
270 ice_aq_get_link_info(struct ice_port_info *pi, bool ena_lse,
271 struct ice_link_status *link, struct ice_sq_cd *cd)
273 struct ice_aqc_get_link_status_data link_data = { 0 };
274 struct ice_aqc_get_link_status *resp;
275 struct ice_link_status *li_old, *li;
276 enum ice_media_type *hw_media_type;
277 struct ice_fc_info *hw_fc_info;
278 bool tx_pause, rx_pause;
279 struct ice_aq_desc desc;
280 enum ice_status status;
285 return ICE_ERR_PARAM;
287 li_old = &pi->phy.link_info_old;
288 hw_media_type = &pi->phy.media_type;
289 li = &pi->phy.link_info;
290 hw_fc_info = &pi->fc;
292 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_status);
293 cmd_flags = (ena_lse) ? ICE_AQ_LSE_ENA : ICE_AQ_LSE_DIS;
294 resp = &desc.params.get_link_status;
295 resp->cmd_flags = CPU_TO_LE16(cmd_flags);
296 resp->lport_num = pi->lport;
298 status = ice_aq_send_cmd(hw, &desc, &link_data, sizeof(link_data), cd);
300 if (status != ICE_SUCCESS)
303 /* save off old link status information */
306 /* update current link status information */
307 li->link_speed = LE16_TO_CPU(link_data.link_speed);
308 li->phy_type_low = LE64_TO_CPU(link_data.phy_type_low);
309 li->phy_type_high = LE64_TO_CPU(link_data.phy_type_high);
310 *hw_media_type = ice_get_media_type(pi);
311 li->link_info = link_data.link_info;
312 li->an_info = link_data.an_info;
313 li->ext_info = link_data.ext_info;
314 li->max_frame_size = LE16_TO_CPU(link_data.max_frame_size);
315 li->fec_info = link_data.cfg & ICE_AQ_FEC_MASK;
316 li->topo_media_conflict = link_data.topo_media_conflict;
317 li->pacing = link_data.cfg & (ICE_AQ_CFG_PACING_M |
318 ICE_AQ_CFG_PACING_TYPE_M);
321 tx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_TX);
322 rx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_RX);
323 if (tx_pause && rx_pause)
324 hw_fc_info->current_mode = ICE_FC_FULL;
326 hw_fc_info->current_mode = ICE_FC_TX_PAUSE;
328 hw_fc_info->current_mode = ICE_FC_RX_PAUSE;
330 hw_fc_info->current_mode = ICE_FC_NONE;
332 li->lse_ena = !!(resp->cmd_flags & CPU_TO_LE16(ICE_AQ_LSE_IS_ENABLED));
334 ice_debug(hw, ICE_DBG_LINK, "link_speed = 0x%x\n", li->link_speed);
335 ice_debug(hw, ICE_DBG_LINK, "phy_type_low = 0x%llx\n",
336 (unsigned long long)li->phy_type_low);
337 ice_debug(hw, ICE_DBG_LINK, "phy_type_high = 0x%llx\n",
338 (unsigned long long)li->phy_type_high);
339 ice_debug(hw, ICE_DBG_LINK, "media_type = 0x%x\n", *hw_media_type);
340 ice_debug(hw, ICE_DBG_LINK, "link_info = 0x%x\n", li->link_info);
341 ice_debug(hw, ICE_DBG_LINK, "an_info = 0x%x\n", li->an_info);
342 ice_debug(hw, ICE_DBG_LINK, "ext_info = 0x%x\n", li->ext_info);
343 ice_debug(hw, ICE_DBG_LINK, "lse_ena = 0x%x\n", li->lse_ena);
344 ice_debug(hw, ICE_DBG_LINK, "max_frame = 0x%x\n", li->max_frame_size);
345 ice_debug(hw, ICE_DBG_LINK, "pacing = 0x%x\n", li->pacing);
347 /* save link status information */
351 /* flag cleared so calling functions don't call AQ again */
352 pi->phy.get_link_info = false;
358 * ice_init_flex_flags
359 * @hw: pointer to the hardware structure
360 * @prof_id: Rx Descriptor Builder profile ID
362 * Function to initialize Rx flex flags
364 static void ice_init_flex_flags(struct ice_hw *hw, enum ice_rxdid prof_id)
368 /* Flex-flag fields (0-2) are programmed with FLG64 bits with layout:
369 * flexiflags0[5:0] - TCP flags, is_packet_fragmented, is_packet_UDP_GRE
370 * flexiflags1[3:0] - Not used for flag programming
371 * flexiflags2[7:0] - Tunnel and VLAN types
372 * 2 invalid fields in last index
375 /* Rx flex flags are currently programmed for the NIC profiles only.
376 * Different flag bit programming configurations can be added per
379 case ICE_RXDID_FLEX_NIC:
380 case ICE_RXDID_FLEX_NIC_2:
381 ICE_PROG_FLG_ENTRY(hw, prof_id, ICE_FLG_PKT_FRG,
382 ICE_FLG_UDP_GRE, ICE_FLG_PKT_DSI,
384 /* flex flag 1 is not used for flexi-flag programming, skipping
385 * these four FLG64 bits.
387 ICE_PROG_FLG_ENTRY(hw, prof_id, ICE_FLG_SYN, ICE_FLG_RST,
388 ICE_FLG_PKT_DSI, ICE_FLG_PKT_DSI, idx++);
389 ICE_PROG_FLG_ENTRY(hw, prof_id, ICE_FLG_PKT_DSI,
390 ICE_FLG_PKT_DSI, ICE_FLG_EVLAN_x8100,
391 ICE_FLG_EVLAN_x9100, idx++);
392 ICE_PROG_FLG_ENTRY(hw, prof_id, ICE_FLG_VLAN_x8100,
393 ICE_FLG_TNL_VLAN, ICE_FLG_TNL_MAC,
394 ICE_FLG_TNL0, idx++);
395 ICE_PROG_FLG_ENTRY(hw, prof_id, ICE_FLG_TNL1, ICE_FLG_TNL2,
396 ICE_FLG_PKT_DSI, ICE_FLG_PKT_DSI, idx);
400 ice_debug(hw, ICE_DBG_INIT,
401 "Flag programming for profile ID %d not supported\n",
408 * @hw: pointer to the hardware structure
409 * @prof_id: Rx Descriptor Builder profile ID
411 * Function to initialize flex descriptors
413 static void ice_init_flex_flds(struct ice_hw *hw, enum ice_rxdid prof_id)
415 enum ice_flex_mdid mdid;
418 case ICE_RXDID_FLEX_NIC:
419 case ICE_RXDID_FLEX_NIC_2:
420 ICE_PROG_FLEX_ENTRY(hw, prof_id, ICE_MDID_RX_HASH_LOW, 0);
421 ICE_PROG_FLEX_ENTRY(hw, prof_id, ICE_MDID_RX_HASH_HIGH, 1);
422 ICE_PROG_FLEX_ENTRY(hw, prof_id, ICE_MDID_FLOW_ID_LOWER, 2);
424 mdid = (prof_id == ICE_RXDID_FLEX_NIC_2) ?
425 ICE_MDID_SRC_VSI : ICE_MDID_FLOW_ID_HIGH;
427 ICE_PROG_FLEX_ENTRY(hw, prof_id, mdid, 3);
429 ice_init_flex_flags(hw, prof_id);
433 ice_debug(hw, ICE_DBG_INIT,
434 "Field init for profile ID %d not supported\n",
441 * @hw: pointer to the HW struct
442 * @max_frame_size: Maximum Frame Size to be supported
443 * @cd: pointer to command details structure or NULL
445 * Set MAC configuration (0x0603)
448 ice_aq_set_mac_cfg(struct ice_hw *hw, u16 max_frame_size, struct ice_sq_cd *cd)
450 u16 fc_threshold_val, tx_timer_val;
451 struct ice_aqc_set_mac_cfg *cmd;
452 struct ice_aq_desc desc;
455 cmd = &desc.params.set_mac_cfg;
457 if (max_frame_size == 0)
458 return ICE_ERR_PARAM;
460 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_mac_cfg);
462 cmd->max_frame_size = CPU_TO_LE16(max_frame_size);
464 /* We read back the transmit timer and fc threshold value of
465 * LFC. Thus, we will use index =
466 * PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX.
468 * Also, because we are opearating on transmit timer and fc
469 * threshold of LFC, we don't turn on any bit in tx_tmr_priority
471 #define IDX_OF_LFC PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX
473 /* Retrieve the transmit timer */
475 PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(IDX_OF_LFC));
476 tx_timer_val = reg_val &
477 PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_HSEC_CTL_TX_PAUSE_QUANTA_M;
478 cmd->tx_tmr_value = CPU_TO_LE16(tx_timer_val);
480 /* Retrieve the fc threshold */
482 PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(IDX_OF_LFC));
483 fc_threshold_val = reg_val & MAKEMASK(0xFFFF, 0);
484 cmd->fc_refresh_threshold = CPU_TO_LE16(fc_threshold_val);
486 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
490 * ice_init_fltr_mgmt_struct - initializes filter management list and locks
491 * @hw: pointer to the HW struct
493 static enum ice_status ice_init_fltr_mgmt_struct(struct ice_hw *hw)
495 struct ice_switch_info *sw;
497 hw->switch_info = (struct ice_switch_info *)
498 ice_malloc(hw, sizeof(*hw->switch_info));
499 sw = hw->switch_info;
502 return ICE_ERR_NO_MEMORY;
504 INIT_LIST_HEAD(&sw->vsi_list_map_head);
506 return ice_init_def_sw_recp(hw);
510 * ice_cleanup_fltr_mgmt_struct - cleanup filter management list and locks
511 * @hw: pointer to the HW struct
513 static void ice_cleanup_fltr_mgmt_struct(struct ice_hw *hw)
515 struct ice_switch_info *sw = hw->switch_info;
516 struct ice_vsi_list_map_info *v_pos_map;
517 struct ice_vsi_list_map_info *v_tmp_map;
518 struct ice_sw_recipe *recps;
521 LIST_FOR_EACH_ENTRY_SAFE(v_pos_map, v_tmp_map, &sw->vsi_list_map_head,
522 ice_vsi_list_map_info, list_entry) {
523 LIST_DEL(&v_pos_map->list_entry);
524 ice_free(hw, v_pos_map);
526 recps = hw->switch_info->recp_list;
527 for (i = 0; i < ICE_MAX_NUM_RECIPES; i++) {
528 struct ice_recp_grp_entry *rg_entry, *tmprg_entry;
530 recps[i].root_rid = i;
531 LIST_FOR_EACH_ENTRY_SAFE(rg_entry, tmprg_entry,
532 &recps[i].rg_list, ice_recp_grp_entry,
534 LIST_DEL(&rg_entry->l_entry);
535 ice_free(hw, rg_entry);
538 if (recps[i].adv_rule) {
539 struct ice_adv_fltr_mgmt_list_entry *tmp_entry;
540 struct ice_adv_fltr_mgmt_list_entry *lst_itr;
542 ice_destroy_lock(&recps[i].filt_rule_lock);
543 LIST_FOR_EACH_ENTRY_SAFE(lst_itr, tmp_entry,
544 &recps[i].filt_rules,
545 ice_adv_fltr_mgmt_list_entry,
547 LIST_DEL(&lst_itr->list_entry);
548 ice_free(hw, lst_itr->lkups);
549 ice_free(hw, lst_itr);
552 struct ice_fltr_mgmt_list_entry *lst_itr, *tmp_entry;
554 ice_destroy_lock(&recps[i].filt_rule_lock);
555 LIST_FOR_EACH_ENTRY_SAFE(lst_itr, tmp_entry,
556 &recps[i].filt_rules,
557 ice_fltr_mgmt_list_entry,
559 LIST_DEL(&lst_itr->list_entry);
560 ice_free(hw, lst_itr);
563 if (recps[i].root_buf)
564 ice_free(hw, recps[i].root_buf);
566 ice_rm_all_sw_replay_rule_info(hw);
567 ice_free(hw, sw->recp_list);
571 #define ICE_FW_LOG_DESC_SIZE(n) (sizeof(struct ice_aqc_fw_logging_data) + \
572 (((n) - 1) * sizeof(((struct ice_aqc_fw_logging_data *)0)->entry)))
573 #define ICE_FW_LOG_DESC_SIZE_MAX \
574 ICE_FW_LOG_DESC_SIZE(ICE_AQC_FW_LOG_ID_MAX)
577 * ice_get_fw_log_cfg - get FW logging configuration
578 * @hw: pointer to the HW struct
580 static enum ice_status ice_get_fw_log_cfg(struct ice_hw *hw)
582 struct ice_aqc_fw_logging_data *config;
583 struct ice_aq_desc desc;
584 enum ice_status status;
587 size = ICE_FW_LOG_DESC_SIZE_MAX;
588 config = (struct ice_aqc_fw_logging_data *)ice_malloc(hw, size);
590 return ICE_ERR_NO_MEMORY;
592 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_fw_logging_info);
594 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_BUF);
595 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
597 status = ice_aq_send_cmd(hw, &desc, config, size, NULL);
601 /* Save fw logging information into the HW structure */
602 for (i = 0; i < ICE_AQC_FW_LOG_ID_MAX; i++) {
605 v = LE16_TO_CPU(config->entry[i]);
606 m = (v & ICE_AQC_FW_LOG_ID_M) >> ICE_AQC_FW_LOG_ID_S;
607 flgs = (v & ICE_AQC_FW_LOG_EN_M) >> ICE_AQC_FW_LOG_EN_S;
609 if (m < ICE_AQC_FW_LOG_ID_MAX)
610 hw->fw_log.evnts[m].cur = flgs;
614 ice_free(hw, config);
620 * ice_cfg_fw_log - configure FW logging
621 * @hw: pointer to the HW struct
622 * @enable: enable certain FW logging events if true, disable all if false
624 * This function enables/disables the FW logging via Rx CQ events and a UART
625 * port based on predetermined configurations. FW logging via the Rx CQ can be
626 * enabled/disabled for individual PF's. However, FW logging via the UART can
627 * only be enabled/disabled for all PFs on the same device.
629 * To enable overall FW logging, the "cq_en" and "uart_en" enable bits in
630 * hw->fw_log need to be set accordingly, e.g. based on user-provided input,
631 * before initializing the device.
633 * When re/configuring FW logging, callers need to update the "cfg" elements of
634 * the hw->fw_log.evnts array with the desired logging event configurations for
635 * modules of interest. When disabling FW logging completely, the callers can
636 * just pass false in the "enable" parameter. On completion, the function will
637 * update the "cur" element of the hw->fw_log.evnts array with the resulting
638 * logging event configurations of the modules that are being re/configured. FW
639 * logging modules that are not part of a reconfiguration operation retain their
642 * Before resetting the device, it is recommended that the driver disables FW
643 * logging before shutting down the control queue. When disabling FW logging
644 * ("enable" = false), the latest configurations of FW logging events stored in
645 * hw->fw_log.evnts[] are not overridden to allow them to be reconfigured after
648 * When enabling FW logging to emit log messages via the Rx CQ during the
649 * device's initialization phase, a mechanism alternative to interrupt handlers
650 * needs to be used to extract FW log messages from the Rx CQ periodically and
651 * to prevent the Rx CQ from being full and stalling other types of control
652 * messages from FW to SW. Interrupts are typically disabled during the device's
653 * initialization phase.
655 static enum ice_status ice_cfg_fw_log(struct ice_hw *hw, bool enable)
657 struct ice_aqc_fw_logging_data *data = NULL;
658 struct ice_aqc_fw_logging *cmd;
659 enum ice_status status = ICE_SUCCESS;
660 u16 i, chgs = 0, len = 0;
661 struct ice_aq_desc desc;
665 if (!hw->fw_log.cq_en && !hw->fw_log.uart_en)
668 /* Disable FW logging only when the control queue is still responsive */
670 (!hw->fw_log.actv_evnts || !ice_check_sq_alive(hw, &hw->adminq)))
673 /* Get current FW log settings */
674 status = ice_get_fw_log_cfg(hw);
678 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_fw_logging);
679 cmd = &desc.params.fw_logging;
681 /* Indicate which controls are valid */
682 if (hw->fw_log.cq_en)
683 cmd->log_ctrl_valid |= ICE_AQC_FW_LOG_AQ_VALID;
685 if (hw->fw_log.uart_en)
686 cmd->log_ctrl_valid |= ICE_AQC_FW_LOG_UART_VALID;
689 /* Fill in an array of entries with FW logging modules and
690 * logging events being reconfigured.
692 for (i = 0; i < ICE_AQC_FW_LOG_ID_MAX; i++) {
695 /* Keep track of enabled event types */
696 actv_evnts |= hw->fw_log.evnts[i].cfg;
698 if (hw->fw_log.evnts[i].cfg == hw->fw_log.evnts[i].cur)
702 data = (struct ice_aqc_fw_logging_data *)
704 ICE_FW_LOG_DESC_SIZE_MAX);
706 return ICE_ERR_NO_MEMORY;
709 val = i << ICE_AQC_FW_LOG_ID_S;
710 val |= hw->fw_log.evnts[i].cfg << ICE_AQC_FW_LOG_EN_S;
711 data->entry[chgs++] = CPU_TO_LE16(val);
714 /* Only enable FW logging if at least one module is specified.
715 * If FW logging is currently enabled but all modules are not
716 * enabled to emit log messages, disable FW logging altogether.
719 /* Leave if there is effectively no change */
723 if (hw->fw_log.cq_en)
724 cmd->log_ctrl |= ICE_AQC_FW_LOG_AQ_EN;
726 if (hw->fw_log.uart_en)
727 cmd->log_ctrl |= ICE_AQC_FW_LOG_UART_EN;
730 len = ICE_FW_LOG_DESC_SIZE(chgs);
731 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
735 status = ice_aq_send_cmd(hw, &desc, buf, len, NULL);
737 /* Update the current configuration to reflect events enabled.
738 * hw->fw_log.cq_en and hw->fw_log.uart_en indicate if the FW
739 * logging mode is enabled for the device. They do not reflect
740 * actual modules being enabled to emit log messages. So, their
741 * values remain unchanged even when all modules are disabled.
743 u16 cnt = enable ? chgs : (u16)ICE_AQC_FW_LOG_ID_MAX;
745 hw->fw_log.actv_evnts = actv_evnts;
746 for (i = 0; i < cnt; i++) {
750 /* When disabling all FW logging events as part
751 * of device's de-initialization, the original
752 * configurations are retained, and can be used
753 * to reconfigure FW logging later if the device
756 hw->fw_log.evnts[i].cur = 0;
760 v = LE16_TO_CPU(data->entry[i]);
761 m = (v & ICE_AQC_FW_LOG_ID_M) >> ICE_AQC_FW_LOG_ID_S;
762 hw->fw_log.evnts[m].cur = hw->fw_log.evnts[m].cfg;
775 * @hw: pointer to the HW struct
776 * @desc: pointer to the AQ message descriptor
777 * @buf: pointer to the buffer accompanying the AQ message
779 * Formats a FW Log message and outputs it via the standard driver logs.
781 void ice_output_fw_log(struct ice_hw *hw, struct ice_aq_desc *desc, void *buf)
783 ice_debug(hw, ICE_DBG_FW_LOG, "[ FW Log Msg Start ]\n");
784 ice_debug_array(hw, ICE_DBG_FW_LOG, 16, 1, (u8 *)buf,
785 LE16_TO_CPU(desc->datalen));
786 ice_debug(hw, ICE_DBG_FW_LOG, "[ FW Log Msg End ]\n");
790 * ice_get_itr_intrl_gran - determine int/intrl granularity
791 * @hw: pointer to the HW struct
793 * Determines the itr/intrl granularities based on the maximum aggregate
794 * bandwidth according to the device's configuration during power-on.
796 static void ice_get_itr_intrl_gran(struct ice_hw *hw)
798 u8 max_agg_bw = (rd32(hw, GL_PWR_MODE_CTL) &
799 GL_PWR_MODE_CTL_CAR_MAX_BW_M) >>
800 GL_PWR_MODE_CTL_CAR_MAX_BW_S;
802 switch (max_agg_bw) {
803 case ICE_MAX_AGG_BW_200G:
804 case ICE_MAX_AGG_BW_100G:
805 case ICE_MAX_AGG_BW_50G:
806 hw->itr_gran = ICE_ITR_GRAN_ABOVE_25;
807 hw->intrl_gran = ICE_INTRL_GRAN_ABOVE_25;
809 case ICE_MAX_AGG_BW_25G:
810 hw->itr_gran = ICE_ITR_GRAN_MAX_25;
811 hw->intrl_gran = ICE_INTRL_GRAN_MAX_25;
817 * ice_init_hw - main hardware initialization routine
818 * @hw: pointer to the hardware structure
820 enum ice_status ice_init_hw(struct ice_hw *hw)
822 struct ice_aqc_get_phy_caps_data *pcaps;
823 enum ice_status status;
827 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
830 /* Set MAC type based on DeviceID */
831 status = ice_set_mac_type(hw);
835 hw->pf_id = (u8)(rd32(hw, PF_FUNC_RID) &
836 PF_FUNC_RID_FUNCTION_NUMBER_M) >>
837 PF_FUNC_RID_FUNCTION_NUMBER_S;
840 status = ice_reset(hw, ICE_RESET_PFR);
844 ice_get_itr_intrl_gran(hw);
847 status = ice_create_all_ctrlq(hw);
849 goto err_unroll_cqinit;
851 /* Enable FW logging. Not fatal if this fails. */
852 status = ice_cfg_fw_log(hw, true);
854 ice_debug(hw, ICE_DBG_INIT, "Failed to enable FW logging.\n");
856 status = ice_clear_pf_cfg(hw);
858 goto err_unroll_cqinit;
860 /* Set bit to enable Flow Director filters */
861 wr32(hw, PFQF_FD_ENA, PFQF_FD_ENA_FD_ENA_M);
862 INIT_LIST_HEAD(&hw->fdir_list_head);
864 ice_clear_pxe_mode(hw);
866 status = ice_init_nvm(hw);
868 goto err_unroll_cqinit;
870 status = ice_get_caps(hw);
872 goto err_unroll_cqinit;
874 hw->port_info = (struct ice_port_info *)
875 ice_malloc(hw, sizeof(*hw->port_info));
876 if (!hw->port_info) {
877 status = ICE_ERR_NO_MEMORY;
878 goto err_unroll_cqinit;
881 /* set the back pointer to HW */
882 hw->port_info->hw = hw;
884 /* Initialize port_info struct with switch configuration data */
885 status = ice_get_initial_sw_cfg(hw);
887 goto err_unroll_alloc;
891 /* Query the allocated resources for Tx scheduler */
892 status = ice_sched_query_res_alloc(hw);
894 ice_debug(hw, ICE_DBG_SCHED,
895 "Failed to get scheduler allocated resources\n");
896 goto err_unroll_alloc;
900 /* Initialize port_info struct with scheduler data */
901 status = ice_sched_init_port(hw->port_info);
903 goto err_unroll_sched;
905 pcaps = (struct ice_aqc_get_phy_caps_data *)
906 ice_malloc(hw, sizeof(*pcaps));
908 status = ICE_ERR_NO_MEMORY;
909 goto err_unroll_sched;
912 /* Initialize port_info struct with PHY capabilities */
913 status = ice_aq_get_phy_caps(hw->port_info, false,
914 ICE_AQC_REPORT_TOPO_CAP, pcaps, NULL);
917 goto err_unroll_sched;
919 /* Initialize port_info struct with link information */
920 status = ice_aq_get_link_info(hw->port_info, false, NULL, NULL);
922 goto err_unroll_sched;
923 /* need a valid SW entry point to build a Tx tree */
924 if (!hw->sw_entry_point_layer) {
925 ice_debug(hw, ICE_DBG_SCHED, "invalid sw entry point\n");
926 status = ICE_ERR_CFG;
927 goto err_unroll_sched;
929 INIT_LIST_HEAD(&hw->agg_list);
930 /* Initialize max burst size */
931 if (!hw->max_burst_size)
932 ice_cfg_rl_burst_size(hw, ICE_SCHED_DFLT_BURST_SIZE);
934 status = ice_init_fltr_mgmt_struct(hw);
936 goto err_unroll_sched;
939 /* Get MAC information */
940 /* A single port can report up to two (LAN and WoL) addresses */
941 mac_buf = ice_calloc(hw, 2,
942 sizeof(struct ice_aqc_manage_mac_read_resp));
943 mac_buf_len = 2 * sizeof(struct ice_aqc_manage_mac_read_resp);
946 status = ICE_ERR_NO_MEMORY;
947 goto err_unroll_fltr_mgmt_struct;
950 status = ice_aq_manage_mac_read(hw, mac_buf, mac_buf_len, NULL);
951 ice_free(hw, mac_buf);
954 goto err_unroll_fltr_mgmt_struct;
956 ice_init_flex_flds(hw, ICE_RXDID_FLEX_NIC);
957 ice_init_flex_flds(hw, ICE_RXDID_FLEX_NIC_2);
958 /* Obtain counter base index which would be used by flow director */
959 status = ice_alloc_fd_res_cntr(hw, &hw->fd_ctr_base);
961 goto err_unroll_fltr_mgmt_struct;
962 status = ice_init_hw_tbls(hw);
964 goto err_unroll_fltr_mgmt_struct;
967 err_unroll_fltr_mgmt_struct:
968 ice_cleanup_fltr_mgmt_struct(hw);
970 ice_sched_cleanup_all(hw);
972 ice_free(hw, hw->port_info);
973 hw->port_info = NULL;
975 ice_destroy_all_ctrlq(hw);
980 * ice_deinit_hw - unroll initialization operations done by ice_init_hw
981 * @hw: pointer to the hardware structure
983 * This should be called only during nominal operation, not as a result of
984 * ice_init_hw() failing since ice_init_hw() will take care of unrolling
985 * applicable initializations if it fails for any reason.
987 void ice_deinit_hw(struct ice_hw *hw)
989 ice_free_fd_res_cntr(hw, hw->fd_ctr_base);
990 ice_cleanup_fltr_mgmt_struct(hw);
992 ice_sched_cleanup_all(hw);
993 ice_sched_clear_agg(hw);
995 ice_free_hw_tbls(hw);
998 ice_free(hw, hw->port_info);
999 hw->port_info = NULL;
1002 /* Attempt to disable FW logging before shutting down control queues */
1003 ice_cfg_fw_log(hw, false);
1004 ice_destroy_all_ctrlq(hw);
1006 /* Clear VSI contexts if not already cleared */
1007 ice_clear_all_vsi_ctx(hw);
1011 * ice_check_reset - Check to see if a global reset is complete
1012 * @hw: pointer to the hardware structure
1014 enum ice_status ice_check_reset(struct ice_hw *hw)
1016 u32 cnt, reg = 0, grst_delay;
1018 /* Poll for Device Active state in case a recent CORER, GLOBR,
1019 * or EMPR has occurred. The grst delay value is in 100ms units.
1020 * Add 1sec for outstanding AQ commands that can take a long time.
1022 #define GLGEN_RSTCTL 0x000B8180 /* Reset Source: POR */
1023 #define GLGEN_RSTCTL_GRSTDEL_S 0
1024 #define GLGEN_RSTCTL_GRSTDEL_M MAKEMASK(0x3F, GLGEN_RSTCTL_GRSTDEL_S)
1025 grst_delay = ((rd32(hw, GLGEN_RSTCTL) & GLGEN_RSTCTL_GRSTDEL_M) >>
1026 GLGEN_RSTCTL_GRSTDEL_S) + 10;
1028 for (cnt = 0; cnt < grst_delay; cnt++) {
1029 ice_msec_delay(100, true);
1030 reg = rd32(hw, GLGEN_RSTAT);
1031 if (!(reg & GLGEN_RSTAT_DEVSTATE_M))
1035 if (cnt == grst_delay) {
1036 ice_debug(hw, ICE_DBG_INIT,
1037 "Global reset polling failed to complete.\n");
1038 return ICE_ERR_RESET_FAILED;
1041 #define ICE_RESET_DONE_MASK (GLNVM_ULD_CORER_DONE_M | \
1042 GLNVM_ULD_GLOBR_DONE_M)
1044 /* Device is Active; check Global Reset processes are done */
1045 for (cnt = 0; cnt < ICE_PF_RESET_WAIT_COUNT; cnt++) {
1046 reg = rd32(hw, GLNVM_ULD) & ICE_RESET_DONE_MASK;
1047 if (reg == ICE_RESET_DONE_MASK) {
1048 ice_debug(hw, ICE_DBG_INIT,
1049 "Global reset processes done. %d\n", cnt);
1052 ice_msec_delay(10, true);
1055 if (cnt == ICE_PF_RESET_WAIT_COUNT) {
1056 ice_debug(hw, ICE_DBG_INIT,
1057 "Wait for Reset Done timed out. GLNVM_ULD = 0x%x\n",
1059 return ICE_ERR_RESET_FAILED;
1066 * ice_pf_reset - Reset the PF
1067 * @hw: pointer to the hardware structure
1069 * If a global reset has been triggered, this function checks
1070 * for its completion and then issues the PF reset
1072 static enum ice_status ice_pf_reset(struct ice_hw *hw)
1076 /* If at function entry a global reset was already in progress, i.e.
1077 * state is not 'device active' or any of the reset done bits are not
1078 * set in GLNVM_ULD, there is no need for a PF Reset; poll until the
1079 * global reset is done.
1081 if ((rd32(hw, GLGEN_RSTAT) & GLGEN_RSTAT_DEVSTATE_M) ||
1082 (rd32(hw, GLNVM_ULD) & ICE_RESET_DONE_MASK) ^ ICE_RESET_DONE_MASK) {
1083 /* poll on global reset currently in progress until done */
1084 if (ice_check_reset(hw))
1085 return ICE_ERR_RESET_FAILED;
1091 reg = rd32(hw, PFGEN_CTRL);
1093 wr32(hw, PFGEN_CTRL, (reg | PFGEN_CTRL_PFSWR_M));
1095 for (cnt = 0; cnt < ICE_PF_RESET_WAIT_COUNT; cnt++) {
1096 reg = rd32(hw, PFGEN_CTRL);
1097 if (!(reg & PFGEN_CTRL_PFSWR_M))
1100 ice_msec_delay(1, true);
1103 if (cnt == ICE_PF_RESET_WAIT_COUNT) {
1104 ice_debug(hw, ICE_DBG_INIT,
1105 "PF reset polling failed to complete.\n");
1106 return ICE_ERR_RESET_FAILED;
1113 * ice_reset - Perform different types of reset
1114 * @hw: pointer to the hardware structure
1115 * @req: reset request
1117 * This function triggers a reset as specified by the req parameter.
1120 * If anything other than a PF reset is triggered, PXE mode is restored.
1121 * This has to be cleared using ice_clear_pxe_mode again, once the AQ
1122 * interface has been restored in the rebuild flow.
1124 enum ice_status ice_reset(struct ice_hw *hw, enum ice_reset_req req)
1130 return ice_pf_reset(hw);
1131 case ICE_RESET_CORER:
1132 ice_debug(hw, ICE_DBG_INIT, "CoreR requested\n");
1133 val = GLGEN_RTRIG_CORER_M;
1135 case ICE_RESET_GLOBR:
1136 ice_debug(hw, ICE_DBG_INIT, "GlobalR requested\n");
1137 val = GLGEN_RTRIG_GLOBR_M;
1140 return ICE_ERR_PARAM;
1143 val |= rd32(hw, GLGEN_RTRIG);
1144 wr32(hw, GLGEN_RTRIG, val);
1148 /* wait for the FW to be ready */
1149 return ice_check_reset(hw);
1155 * ice_copy_rxq_ctx_to_hw
1156 * @hw: pointer to the hardware structure
1157 * @ice_rxq_ctx: pointer to the rxq context
1158 * @rxq_index: the index of the Rx queue
1160 * Copies rxq context from dense structure to HW register space
1162 static enum ice_status
1163 ice_copy_rxq_ctx_to_hw(struct ice_hw *hw, u8 *ice_rxq_ctx, u32 rxq_index)
1168 return ICE_ERR_BAD_PTR;
1170 if (rxq_index > QRX_CTRL_MAX_INDEX)
1171 return ICE_ERR_PARAM;
1173 /* Copy each dword separately to HW */
1174 for (i = 0; i < ICE_RXQ_CTX_SIZE_DWORDS; i++) {
1175 wr32(hw, QRX_CONTEXT(i, rxq_index),
1176 *((u32 *)(ice_rxq_ctx + (i * sizeof(u32)))));
1178 ice_debug(hw, ICE_DBG_QCTX, "qrxdata[%d]: %08X\n", i,
1179 *((u32 *)(ice_rxq_ctx + (i * sizeof(u32)))));
1185 /* LAN Rx Queue Context */
1186 static const struct ice_ctx_ele ice_rlan_ctx_info[] = {
1187 /* Field Width LSB */
1188 ICE_CTX_STORE(ice_rlan_ctx, head, 13, 0),
1189 ICE_CTX_STORE(ice_rlan_ctx, cpuid, 8, 13),
1190 ICE_CTX_STORE(ice_rlan_ctx, base, 57, 32),
1191 ICE_CTX_STORE(ice_rlan_ctx, qlen, 13, 89),
1192 ICE_CTX_STORE(ice_rlan_ctx, dbuf, 7, 102),
1193 ICE_CTX_STORE(ice_rlan_ctx, hbuf, 5, 109),
1194 ICE_CTX_STORE(ice_rlan_ctx, dtype, 2, 114),
1195 ICE_CTX_STORE(ice_rlan_ctx, dsize, 1, 116),
1196 ICE_CTX_STORE(ice_rlan_ctx, crcstrip, 1, 117),
1197 ICE_CTX_STORE(ice_rlan_ctx, l2tsel, 1, 119),
1198 ICE_CTX_STORE(ice_rlan_ctx, hsplit_0, 4, 120),
1199 ICE_CTX_STORE(ice_rlan_ctx, hsplit_1, 2, 124),
1200 ICE_CTX_STORE(ice_rlan_ctx, showiv, 1, 127),
1201 ICE_CTX_STORE(ice_rlan_ctx, rxmax, 14, 174),
1202 ICE_CTX_STORE(ice_rlan_ctx, tphrdesc_ena, 1, 193),
1203 ICE_CTX_STORE(ice_rlan_ctx, tphwdesc_ena, 1, 194),
1204 ICE_CTX_STORE(ice_rlan_ctx, tphdata_ena, 1, 195),
1205 ICE_CTX_STORE(ice_rlan_ctx, tphhead_ena, 1, 196),
1206 ICE_CTX_STORE(ice_rlan_ctx, lrxqthresh, 3, 198),
1207 ICE_CTX_STORE(ice_rlan_ctx, prefena, 1, 201),
1213 * @hw: pointer to the hardware structure
1214 * @rlan_ctx: pointer to the rxq context
1215 * @rxq_index: the index of the Rx queue
1217 * Converts rxq context from sparse to dense structure and then writes
1218 * it to HW register space and enables the hardware to prefetch descriptors
1219 * instead of only fetching them on demand
1222 ice_write_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx,
1225 u8 ctx_buf[ICE_RXQ_CTX_SZ] = { 0 };
1228 return ICE_ERR_BAD_PTR;
1230 rlan_ctx->prefena = 1;
1232 ice_set_ctx((u8 *)rlan_ctx, ctx_buf, ice_rlan_ctx_info);
1233 return ice_copy_rxq_ctx_to_hw(hw, ctx_buf, rxq_index);
1236 #if !defined(NO_UNUSED_CTX_CODE) || defined(AE_DRIVER)
1239 * @hw: pointer to the hardware structure
1240 * @rxq_index: the index of the Rx queue to clear
1242 * Clears rxq context in HW register space
1244 enum ice_status ice_clear_rxq_ctx(struct ice_hw *hw, u32 rxq_index)
1248 if (rxq_index > QRX_CTRL_MAX_INDEX)
1249 return ICE_ERR_PARAM;
1251 /* Clear each dword register separately */
1252 for (i = 0; i < ICE_RXQ_CTX_SIZE_DWORDS; i++)
1253 wr32(hw, QRX_CONTEXT(i, rxq_index), 0);
1257 #endif /* !NO_UNUSED_CTX_CODE || AE_DRIVER */
1259 /* LAN Tx Queue Context */
1260 const struct ice_ctx_ele ice_tlan_ctx_info[] = {
1261 /* Field Width LSB */
1262 ICE_CTX_STORE(ice_tlan_ctx, base, 57, 0),
1263 ICE_CTX_STORE(ice_tlan_ctx, port_num, 3, 57),
1264 ICE_CTX_STORE(ice_tlan_ctx, cgd_num, 5, 60),
1265 ICE_CTX_STORE(ice_tlan_ctx, pf_num, 3, 65),
1266 ICE_CTX_STORE(ice_tlan_ctx, vmvf_num, 10, 68),
1267 ICE_CTX_STORE(ice_tlan_ctx, vmvf_type, 2, 78),
1268 ICE_CTX_STORE(ice_tlan_ctx, src_vsi, 10, 80),
1269 ICE_CTX_STORE(ice_tlan_ctx, tsyn_ena, 1, 90),
1270 ICE_CTX_STORE(ice_tlan_ctx, internal_usage_flag, 1, 91),
1271 ICE_CTX_STORE(ice_tlan_ctx, alt_vlan, 1, 92),
1272 ICE_CTX_STORE(ice_tlan_ctx, cpuid, 8, 93),
1273 ICE_CTX_STORE(ice_tlan_ctx, wb_mode, 1, 101),
1274 ICE_CTX_STORE(ice_tlan_ctx, tphrd_desc, 1, 102),
1275 ICE_CTX_STORE(ice_tlan_ctx, tphrd, 1, 103),
1276 ICE_CTX_STORE(ice_tlan_ctx, tphwr_desc, 1, 104),
1277 ICE_CTX_STORE(ice_tlan_ctx, cmpq_id, 9, 105),
1278 ICE_CTX_STORE(ice_tlan_ctx, qnum_in_func, 14, 114),
1279 ICE_CTX_STORE(ice_tlan_ctx, itr_notification_mode, 1, 128),
1280 ICE_CTX_STORE(ice_tlan_ctx, adjust_prof_id, 6, 129),
1281 ICE_CTX_STORE(ice_tlan_ctx, qlen, 13, 135),
1282 ICE_CTX_STORE(ice_tlan_ctx, quanta_prof_idx, 4, 148),
1283 ICE_CTX_STORE(ice_tlan_ctx, tso_ena, 1, 152),
1284 ICE_CTX_STORE(ice_tlan_ctx, tso_qnum, 11, 153),
1285 ICE_CTX_STORE(ice_tlan_ctx, legacy_int, 1, 164),
1286 ICE_CTX_STORE(ice_tlan_ctx, drop_ena, 1, 165),
1287 ICE_CTX_STORE(ice_tlan_ctx, cache_prof_idx, 2, 166),
1288 ICE_CTX_STORE(ice_tlan_ctx, pkt_shaper_prof_idx, 3, 168),
1289 ICE_CTX_STORE(ice_tlan_ctx, int_q_state, 122, 171),
1293 #if !defined(NO_UNUSED_CTX_CODE) || defined(AE_DRIVER)
1295 * ice_copy_tx_cmpltnq_ctx_to_hw
1296 * @hw: pointer to the hardware structure
1297 * @ice_tx_cmpltnq_ctx: pointer to the Tx completion queue context
1298 * @tx_cmpltnq_index: the index of the completion queue
1300 * Copies Tx completion queue context from dense structure to HW register space
1302 static enum ice_status
1303 ice_copy_tx_cmpltnq_ctx_to_hw(struct ice_hw *hw, u8 *ice_tx_cmpltnq_ctx,
1304 u32 tx_cmpltnq_index)
1308 if (!ice_tx_cmpltnq_ctx)
1309 return ICE_ERR_BAD_PTR;
1311 if (tx_cmpltnq_index > GLTCLAN_CQ_CNTX0_MAX_INDEX)
1312 return ICE_ERR_PARAM;
1314 /* Copy each dword separately to HW */
1315 for (i = 0; i < ICE_TX_CMPLTNQ_CTX_SIZE_DWORDS; i++) {
1316 wr32(hw, GLTCLAN_CQ_CNTX(i, tx_cmpltnq_index),
1317 *((u32 *)(ice_tx_cmpltnq_ctx + (i * sizeof(u32)))));
1319 ice_debug(hw, ICE_DBG_QCTX, "cmpltnqdata[%d]: %08X\n", i,
1320 *((u32 *)(ice_tx_cmpltnq_ctx + (i * sizeof(u32)))));
1326 /* LAN Tx Completion Queue Context */
1327 static const struct ice_ctx_ele ice_tx_cmpltnq_ctx_info[] = {
1328 /* Field Width LSB */
1329 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, base, 57, 0),
1330 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, q_len, 18, 64),
1331 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, generation, 1, 96),
1332 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, wrt_ptr, 22, 97),
1333 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, pf_num, 3, 128),
1334 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, vmvf_num, 10, 131),
1335 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, vmvf_type, 2, 141),
1336 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, tph_desc_wr, 1, 160),
1337 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, cpuid, 8, 161),
1338 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, cmpltn_cache, 512, 192),
1343 * ice_write_tx_cmpltnq_ctx
1344 * @hw: pointer to the hardware structure
1345 * @tx_cmpltnq_ctx: pointer to the completion queue context
1346 * @tx_cmpltnq_index: the index of the completion queue
1348 * Converts completion queue context from sparse to dense structure and then
1349 * writes it to HW register space
1352 ice_write_tx_cmpltnq_ctx(struct ice_hw *hw,
1353 struct ice_tx_cmpltnq_ctx *tx_cmpltnq_ctx,
1354 u32 tx_cmpltnq_index)
1356 u8 ctx_buf[ICE_TX_CMPLTNQ_CTX_SIZE_DWORDS * sizeof(u32)] = { 0 };
1358 ice_set_ctx((u8 *)tx_cmpltnq_ctx, ctx_buf, ice_tx_cmpltnq_ctx_info);
1359 return ice_copy_tx_cmpltnq_ctx_to_hw(hw, ctx_buf, tx_cmpltnq_index);
1363 * ice_clear_tx_cmpltnq_ctx
1364 * @hw: pointer to the hardware structure
1365 * @tx_cmpltnq_index: the index of the completion queue to clear
1367 * Clears Tx completion queue context in HW register space
1370 ice_clear_tx_cmpltnq_ctx(struct ice_hw *hw, u32 tx_cmpltnq_index)
1374 if (tx_cmpltnq_index > GLTCLAN_CQ_CNTX0_MAX_INDEX)
1375 return ICE_ERR_PARAM;
1377 /* Clear each dword register separately */
1378 for (i = 0; i < ICE_TX_CMPLTNQ_CTX_SIZE_DWORDS; i++)
1379 wr32(hw, GLTCLAN_CQ_CNTX(i, tx_cmpltnq_index), 0);
1385 * ice_copy_tx_drbell_q_ctx_to_hw
1386 * @hw: pointer to the hardware structure
1387 * @ice_tx_drbell_q_ctx: pointer to the doorbell queue context
1388 * @tx_drbell_q_index: the index of the doorbell queue
1390 * Copies doorbell queue context from dense structure to HW register space
1392 static enum ice_status
1393 ice_copy_tx_drbell_q_ctx_to_hw(struct ice_hw *hw, u8 *ice_tx_drbell_q_ctx,
1394 u32 tx_drbell_q_index)
1398 if (!ice_tx_drbell_q_ctx)
1399 return ICE_ERR_BAD_PTR;
1401 if (tx_drbell_q_index > QTX_COMM_DBLQ_DBELL_MAX_INDEX)
1402 return ICE_ERR_PARAM;
1404 /* Copy each dword separately to HW */
1405 for (i = 0; i < ICE_TX_DRBELL_Q_CTX_SIZE_DWORDS; i++) {
1406 wr32(hw, QTX_COMM_DBLQ_CNTX(i, tx_drbell_q_index),
1407 *((u32 *)(ice_tx_drbell_q_ctx + (i * sizeof(u32)))));
1409 ice_debug(hw, ICE_DBG_QCTX, "tx_drbell_qdata[%d]: %08X\n", i,
1410 *((u32 *)(ice_tx_drbell_q_ctx + (i * sizeof(u32)))));
1416 /* LAN Tx Doorbell Queue Context info */
1417 static const struct ice_ctx_ele ice_tx_drbell_q_ctx_info[] = {
1418 /* Field Width LSB */
1419 ICE_CTX_STORE(ice_tx_drbell_q_ctx, base, 57, 0),
1420 ICE_CTX_STORE(ice_tx_drbell_q_ctx, ring_len, 13, 64),
1421 ICE_CTX_STORE(ice_tx_drbell_q_ctx, pf_num, 3, 80),
1422 ICE_CTX_STORE(ice_tx_drbell_q_ctx, vf_num, 8, 84),
1423 ICE_CTX_STORE(ice_tx_drbell_q_ctx, vmvf_type, 2, 94),
1424 ICE_CTX_STORE(ice_tx_drbell_q_ctx, cpuid, 8, 96),
1425 ICE_CTX_STORE(ice_tx_drbell_q_ctx, tph_desc_rd, 1, 104),
1426 ICE_CTX_STORE(ice_tx_drbell_q_ctx, tph_desc_wr, 1, 108),
1427 ICE_CTX_STORE(ice_tx_drbell_q_ctx, db_q_en, 1, 112),
1428 ICE_CTX_STORE(ice_tx_drbell_q_ctx, rd_head, 13, 128),
1429 ICE_CTX_STORE(ice_tx_drbell_q_ctx, rd_tail, 13, 144),
1434 * ice_write_tx_drbell_q_ctx
1435 * @hw: pointer to the hardware structure
1436 * @tx_drbell_q_ctx: pointer to the doorbell queue context
1437 * @tx_drbell_q_index: the index of the doorbell queue
1439 * Converts doorbell queue context from sparse to dense structure and then
1440 * writes it to HW register space
1443 ice_write_tx_drbell_q_ctx(struct ice_hw *hw,
1444 struct ice_tx_drbell_q_ctx *tx_drbell_q_ctx,
1445 u32 tx_drbell_q_index)
1447 u8 ctx_buf[ICE_TX_DRBELL_Q_CTX_SIZE_DWORDS * sizeof(u32)] = { 0 };
1449 ice_set_ctx((u8 *)tx_drbell_q_ctx, ctx_buf, ice_tx_drbell_q_ctx_info);
1450 return ice_copy_tx_drbell_q_ctx_to_hw(hw, ctx_buf, tx_drbell_q_index);
1454 * ice_clear_tx_drbell_q_ctx
1455 * @hw: pointer to the hardware structure
1456 * @tx_drbell_q_index: the index of the doorbell queue to clear
1458 * Clears doorbell queue context in HW register space
1461 ice_clear_tx_drbell_q_ctx(struct ice_hw *hw, u32 tx_drbell_q_index)
1465 if (tx_drbell_q_index > QTX_COMM_DBLQ_DBELL_MAX_INDEX)
1466 return ICE_ERR_PARAM;
1468 /* Clear each dword register separately */
1469 for (i = 0; i < ICE_TX_DRBELL_Q_CTX_SIZE_DWORDS; i++)
1470 wr32(hw, QTX_COMM_DBLQ_CNTX(i, tx_drbell_q_index), 0);
1474 #endif /* !NO_UNUSED_CTX_CODE || AE_DRIVER */
1477 /* FW Admin Queue command wrappers */
1480 * ice_aq_send_cmd - send FW Admin Queue command to FW Admin Queue
1481 * @hw: pointer to the HW struct
1482 * @desc: descriptor describing the command
1483 * @buf: buffer to use for indirect commands (NULL for direct commands)
1484 * @buf_size: size of buffer for indirect commands (0 for direct commands)
1485 * @cd: pointer to command details structure
1487 * Helper function to send FW Admin Queue commands to the FW Admin Queue.
1490 ice_aq_send_cmd(struct ice_hw *hw, struct ice_aq_desc *desc, void *buf,
1491 u16 buf_size, struct ice_sq_cd *cd)
1493 return ice_sq_send_cmd(hw, &hw->adminq, desc, buf, buf_size, cd);
1498 * @hw: pointer to the HW struct
1499 * @cd: pointer to command details structure or NULL
1501 * Get the firmware version (0x0001) from the admin queue commands
1503 enum ice_status ice_aq_get_fw_ver(struct ice_hw *hw, struct ice_sq_cd *cd)
1505 struct ice_aqc_get_ver *resp;
1506 struct ice_aq_desc desc;
1507 enum ice_status status;
1509 resp = &desc.params.get_ver;
1511 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_ver);
1513 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
1516 hw->fw_branch = resp->fw_branch;
1517 hw->fw_maj_ver = resp->fw_major;
1518 hw->fw_min_ver = resp->fw_minor;
1519 hw->fw_patch = resp->fw_patch;
1520 hw->fw_build = LE32_TO_CPU(resp->fw_build);
1521 hw->api_branch = resp->api_branch;
1522 hw->api_maj_ver = resp->api_major;
1523 hw->api_min_ver = resp->api_minor;
1524 hw->api_patch = resp->api_patch;
1531 * ice_aq_send_driver_ver
1532 * @hw: pointer to the HW struct
1533 * @dv: driver's major, minor version
1534 * @cd: pointer to command details structure or NULL
1536 * Send the driver version (0x0002) to the firmware
1539 ice_aq_send_driver_ver(struct ice_hw *hw, struct ice_driver_ver *dv,
1540 struct ice_sq_cd *cd)
1542 struct ice_aqc_driver_ver *cmd;
1543 struct ice_aq_desc desc;
1546 cmd = &desc.params.driver_ver;
1549 return ICE_ERR_PARAM;
1551 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_driver_ver);
1553 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
1554 cmd->major_ver = dv->major_ver;
1555 cmd->minor_ver = dv->minor_ver;
1556 cmd->build_ver = dv->build_ver;
1557 cmd->subbuild_ver = dv->subbuild_ver;
1560 while (len < sizeof(dv->driver_string) &&
1561 IS_ASCII(dv->driver_string[len]) && dv->driver_string[len])
1564 return ice_aq_send_cmd(hw, &desc, dv->driver_string, len, cd);
1569 * @hw: pointer to the HW struct
1570 * @unloading: is the driver unloading itself
1572 * Tell the Firmware that we're shutting down the AdminQ and whether
1573 * or not the driver is unloading as well (0x0003).
1575 enum ice_status ice_aq_q_shutdown(struct ice_hw *hw, bool unloading)
1577 struct ice_aqc_q_shutdown *cmd;
1578 struct ice_aq_desc desc;
1580 cmd = &desc.params.q_shutdown;
1582 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_q_shutdown);
1585 cmd->driver_unloading = ICE_AQC_DRIVER_UNLOADING;
1587 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
1592 * @hw: pointer to the HW struct
1594 * @access: access type
1595 * @sdp_number: resource number
1596 * @timeout: the maximum time in ms that the driver may hold the resource
1597 * @cd: pointer to command details structure or NULL
1599 * Requests common resource using the admin queue commands (0x0008).
1600 * When attempting to acquire the Global Config Lock, the driver can
1601 * learn of three states:
1602 * 1) ICE_SUCCESS - acquired lock, and can perform download package
1603 * 2) ICE_ERR_AQ_ERROR - did not get lock, driver should fail to load
1604 * 3) ICE_ERR_AQ_NO_WORK - did not get lock, but another driver has
1605 * successfully downloaded the package; the driver does
1606 * not have to download the package and can continue
1609 * Note that if the caller is in an acquire lock, perform action, release lock
1610 * phase of operation, it is possible that the FW may detect a timeout and issue
1611 * a CORER. In this case, the driver will receive a CORER interrupt and will
1612 * have to determine its cause. The calling thread that is handling this flow
1613 * will likely get an error propagated back to it indicating the Download
1614 * Package, Update Package or the Release Resource AQ commands timed out.
1616 static enum ice_status
1617 ice_aq_req_res(struct ice_hw *hw, enum ice_aq_res_ids res,
1618 enum ice_aq_res_access_type access, u8 sdp_number, u32 *timeout,
1619 struct ice_sq_cd *cd)
1621 struct ice_aqc_req_res *cmd_resp;
1622 struct ice_aq_desc desc;
1623 enum ice_status status;
1625 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
1627 cmd_resp = &desc.params.res_owner;
1629 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_req_res);
1631 cmd_resp->res_id = CPU_TO_LE16(res);
1632 cmd_resp->access_type = CPU_TO_LE16(access);
1633 cmd_resp->res_number = CPU_TO_LE32(sdp_number);
1634 cmd_resp->timeout = CPU_TO_LE32(*timeout);
1637 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
1639 /* The completion specifies the maximum time in ms that the driver
1640 * may hold the resource in the Timeout field.
1643 /* Global config lock response utilizes an additional status field.
1645 * If the Global config lock resource is held by some other driver, the
1646 * command completes with ICE_AQ_RES_GLBL_IN_PROG in the status field
1647 * and the timeout field indicates the maximum time the current owner
1648 * of the resource has to free it.
1650 if (res == ICE_GLOBAL_CFG_LOCK_RES_ID) {
1651 if (LE16_TO_CPU(cmd_resp->status) == ICE_AQ_RES_GLBL_SUCCESS) {
1652 *timeout = LE32_TO_CPU(cmd_resp->timeout);
1654 } else if (LE16_TO_CPU(cmd_resp->status) ==
1655 ICE_AQ_RES_GLBL_IN_PROG) {
1656 *timeout = LE32_TO_CPU(cmd_resp->timeout);
1657 return ICE_ERR_AQ_ERROR;
1658 } else if (LE16_TO_CPU(cmd_resp->status) ==
1659 ICE_AQ_RES_GLBL_DONE) {
1660 return ICE_ERR_AQ_NO_WORK;
1663 /* invalid FW response, force a timeout immediately */
1665 return ICE_ERR_AQ_ERROR;
1668 /* If the resource is held by some other driver, the command completes
1669 * with a busy return value and the timeout field indicates the maximum
1670 * time the current owner of the resource has to free it.
1672 if (!status || hw->adminq.sq_last_status == ICE_AQ_RC_EBUSY)
1673 *timeout = LE32_TO_CPU(cmd_resp->timeout);
1679 * ice_aq_release_res
1680 * @hw: pointer to the HW struct
1682 * @sdp_number: resource number
1683 * @cd: pointer to command details structure or NULL
1685 * release common resource using the admin queue commands (0x0009)
1687 static enum ice_status
1688 ice_aq_release_res(struct ice_hw *hw, enum ice_aq_res_ids res, u8 sdp_number,
1689 struct ice_sq_cd *cd)
1691 struct ice_aqc_req_res *cmd;
1692 struct ice_aq_desc desc;
1694 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
1696 cmd = &desc.params.res_owner;
1698 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_release_res);
1700 cmd->res_id = CPU_TO_LE16(res);
1701 cmd->res_number = CPU_TO_LE32(sdp_number);
1703 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
1708 * @hw: pointer to the HW structure
1710 * @access: access type (read or write)
1711 * @timeout: timeout in milliseconds
1713 * This function will attempt to acquire the ownership of a resource.
1716 ice_acquire_res(struct ice_hw *hw, enum ice_aq_res_ids res,
1717 enum ice_aq_res_access_type access, u32 timeout)
1719 #define ICE_RES_POLLING_DELAY_MS 10
1720 u32 delay = ICE_RES_POLLING_DELAY_MS;
1721 u32 time_left = timeout;
1722 enum ice_status status;
1724 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
1726 status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL);
1728 /* A return code of ICE_ERR_AQ_NO_WORK means that another driver has
1729 * previously acquired the resource and performed any necessary updates;
1730 * in this case the caller does not obtain the resource and has no
1731 * further work to do.
1733 if (status == ICE_ERR_AQ_NO_WORK)
1734 goto ice_acquire_res_exit;
1737 ice_debug(hw, ICE_DBG_RES,
1738 "resource %d acquire type %d failed.\n", res, access);
1740 /* If necessary, poll until the current lock owner timeouts */
1741 timeout = time_left;
1742 while (status && timeout && time_left) {
1743 ice_msec_delay(delay, true);
1744 timeout = (timeout > delay) ? timeout - delay : 0;
1745 status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL);
1747 if (status == ICE_ERR_AQ_NO_WORK)
1748 /* lock free, but no work to do */
1755 if (status && status != ICE_ERR_AQ_NO_WORK)
1756 ice_debug(hw, ICE_DBG_RES, "resource acquire timed out.\n");
1758 ice_acquire_res_exit:
1759 if (status == ICE_ERR_AQ_NO_WORK) {
1760 if (access == ICE_RES_WRITE)
1761 ice_debug(hw, ICE_DBG_RES,
1762 "resource indicates no work to do.\n");
1764 ice_debug(hw, ICE_DBG_RES,
1765 "Warning: ICE_ERR_AQ_NO_WORK not expected\n");
1772 * @hw: pointer to the HW structure
1775 * This function will release a resource using the proper Admin Command.
1777 void ice_release_res(struct ice_hw *hw, enum ice_aq_res_ids res)
1779 enum ice_status status;
1780 u32 total_delay = 0;
1782 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
1784 status = ice_aq_release_res(hw, res, 0, NULL);
1786 /* there are some rare cases when trying to release the resource
1787 * results in an admin queue timeout, so handle them correctly
1789 while ((status == ICE_ERR_AQ_TIMEOUT) &&
1790 (total_delay < hw->adminq.sq_cmd_timeout)) {
1791 ice_msec_delay(1, true);
1792 status = ice_aq_release_res(hw, res, 0, NULL);
1798 * ice_aq_alloc_free_res - command to allocate/free resources
1799 * @hw: pointer to the HW struct
1800 * @num_entries: number of resource entries in buffer
1801 * @buf: Indirect buffer to hold data parameters and response
1802 * @buf_size: size of buffer for indirect commands
1803 * @opc: pass in the command opcode
1804 * @cd: pointer to command details structure or NULL
1806 * Helper function to allocate/free resources using the admin queue commands
1809 ice_aq_alloc_free_res(struct ice_hw *hw, u16 num_entries,
1810 struct ice_aqc_alloc_free_res_elem *buf, u16 buf_size,
1811 enum ice_adminq_opc opc, struct ice_sq_cd *cd)
1813 struct ice_aqc_alloc_free_res_cmd *cmd;
1814 struct ice_aq_desc desc;
1816 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
1818 cmd = &desc.params.sw_res_ctrl;
1821 return ICE_ERR_PARAM;
1823 if (buf_size < (num_entries * sizeof(buf->elem[0])))
1824 return ICE_ERR_PARAM;
1826 ice_fill_dflt_direct_cmd_desc(&desc, opc);
1828 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
1830 cmd->num_entries = CPU_TO_LE16(num_entries);
1832 return ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);
1836 * ice_alloc_hw_res - allocate resource
1837 * @hw: pointer to the HW struct
1838 * @type: type of resource
1839 * @num: number of resources to allocate
1840 * @btm: allocate from bottom
1841 * @res: pointer to array that will receive the resources
1844 ice_alloc_hw_res(struct ice_hw *hw, u16 type, u16 num, bool btm, u16 *res)
1846 struct ice_aqc_alloc_free_res_elem *buf;
1847 enum ice_status status;
1850 buf_len = sizeof(*buf) + sizeof(buf->elem) * (num - 1);
1851 buf = (struct ice_aqc_alloc_free_res_elem *)
1852 ice_malloc(hw, buf_len);
1854 return ICE_ERR_NO_MEMORY;
1856 /* Prepare buffer to allocate resource. */
1857 buf->num_elems = CPU_TO_LE16(num);
1858 buf->res_type = CPU_TO_LE16(type | ICE_AQC_RES_TYPE_FLAG_DEDICATED |
1859 ICE_AQC_RES_TYPE_FLAG_IGNORE_INDEX);
1861 buf->res_type |= CPU_TO_LE16(ICE_AQC_RES_TYPE_FLAG_SCAN_BOTTOM);
1863 status = ice_aq_alloc_free_res(hw, 1, buf, buf_len,
1864 ice_aqc_opc_alloc_res, NULL);
1866 goto ice_alloc_res_exit;
1868 ice_memcpy(res, buf->elem, sizeof(buf->elem) * num,
1869 ICE_NONDMA_TO_NONDMA);
1877 * ice_free_hw_res - free allocated HW resource
1878 * @hw: pointer to the HW struct
1879 * @type: type of resource to free
1880 * @num: number of resources
1881 * @res: pointer to array that contains the resources to free
1884 ice_free_hw_res(struct ice_hw *hw, u16 type, u16 num, u16 *res)
1886 struct ice_aqc_alloc_free_res_elem *buf;
1887 enum ice_status status;
1890 buf_len = sizeof(*buf) + sizeof(buf->elem) * (num - 1);
1891 buf = (struct ice_aqc_alloc_free_res_elem *)ice_malloc(hw, buf_len);
1893 return ICE_ERR_NO_MEMORY;
1895 /* Prepare buffer to free resource. */
1896 buf->num_elems = CPU_TO_LE16(num);
1897 buf->res_type = CPU_TO_LE16(type);
1898 ice_memcpy(buf->elem, res, sizeof(buf->elem) * num,
1899 ICE_NONDMA_TO_NONDMA);
1901 status = ice_aq_alloc_free_res(hw, num, buf, buf_len,
1902 ice_aqc_opc_free_res, NULL);
1904 ice_debug(hw, ICE_DBG_SW, "CQ CMD Buffer:\n");
1911 * ice_get_num_per_func - determine number of resources per PF
1912 * @hw: pointer to the HW structure
1913 * @max: value to be evenly split between each PF
1915 * Determine the number of valid functions by going through the bitmap returned
1916 * from parsing capabilities and use this to calculate the number of resources
1917 * per PF based on the max value passed in.
1919 static u32 ice_get_num_per_func(struct ice_hw *hw, u32 max)
1923 #define ICE_CAPS_VALID_FUNCS_M 0xFF
1924 funcs = ice_hweight8(hw->dev_caps.common_cap.valid_functions &
1925 ICE_CAPS_VALID_FUNCS_M);
1934 * ice_parse_caps - parse function/device capabilities
1935 * @hw: pointer to the HW struct
1936 * @buf: pointer to a buffer containing function/device capability records
1937 * @cap_count: number of capability records in the list
1938 * @opc: type of capabilities list to parse
1940 * Helper function to parse function(0x000a)/device(0x000b) capabilities list.
1943 ice_parse_caps(struct ice_hw *hw, void *buf, u32 cap_count,
1944 enum ice_adminq_opc opc)
1946 struct ice_aqc_list_caps_elem *cap_resp;
1947 struct ice_hw_func_caps *func_p = NULL;
1948 struct ice_hw_dev_caps *dev_p = NULL;
1949 struct ice_hw_common_caps *caps;
1956 cap_resp = (struct ice_aqc_list_caps_elem *)buf;
1958 if (opc == ice_aqc_opc_list_dev_caps) {
1959 dev_p = &hw->dev_caps;
1960 caps = &dev_p->common_cap;
1962 } else if (opc == ice_aqc_opc_list_func_caps) {
1963 func_p = &hw->func_caps;
1964 caps = &func_p->common_cap;
1965 prefix = "func cap";
1967 ice_debug(hw, ICE_DBG_INIT, "wrong opcode\n");
1971 for (i = 0; caps && i < cap_count; i++, cap_resp++) {
1972 u32 logical_id = LE32_TO_CPU(cap_resp->logical_id);
1973 u32 phys_id = LE32_TO_CPU(cap_resp->phys_id);
1974 u32 number = LE32_TO_CPU(cap_resp->number);
1975 u16 cap = LE16_TO_CPU(cap_resp->cap);
1978 case ICE_AQC_CAPS_VALID_FUNCTIONS:
1979 caps->valid_functions = number;
1980 ice_debug(hw, ICE_DBG_INIT,
1981 "%s: valid functions = %d\n", prefix,
1982 caps->valid_functions);
1984 case ICE_AQC_CAPS_VSI:
1986 dev_p->num_vsi_allocd_to_host = number;
1987 ice_debug(hw, ICE_DBG_INIT,
1988 "%s: num VSI alloc to host = %d\n",
1990 dev_p->num_vsi_allocd_to_host);
1991 } else if (func_p) {
1992 func_p->guar_num_vsi =
1993 ice_get_num_per_func(hw, ICE_MAX_VSI);
1994 ice_debug(hw, ICE_DBG_INIT,
1995 "%s: num guaranteed VSI (fw) = %d\n",
1997 ice_debug(hw, ICE_DBG_INIT,
1998 "%s: num guaranteed VSI = %d\n",
1999 prefix, func_p->guar_num_vsi);
2002 case ICE_AQC_CAPS_DCB:
2003 caps->dcb = (number == 1);
2004 caps->active_tc_bitmap = logical_id;
2005 caps->maxtc = phys_id;
2006 ice_debug(hw, ICE_DBG_INIT,
2007 "%s: DCB = %d\n", prefix, caps->dcb);
2008 ice_debug(hw, ICE_DBG_INIT,
2009 "%s: active TC bitmap = %d\n", prefix,
2010 caps->active_tc_bitmap);
2011 ice_debug(hw, ICE_DBG_INIT,
2012 "%s: TC max = %d\n", prefix, caps->maxtc);
2014 case ICE_AQC_CAPS_RSS:
2015 caps->rss_table_size = number;
2016 caps->rss_table_entry_width = logical_id;
2017 ice_debug(hw, ICE_DBG_INIT,
2018 "%s: RSS table size = %d\n", prefix,
2019 caps->rss_table_size);
2020 ice_debug(hw, ICE_DBG_INIT,
2021 "%s: RSS table width = %d\n", prefix,
2022 caps->rss_table_entry_width);
2024 case ICE_AQC_CAPS_RXQS:
2025 caps->num_rxq = number;
2026 caps->rxq_first_id = phys_id;
2027 ice_debug(hw, ICE_DBG_INIT,
2028 "%s: num Rx queues = %d\n", prefix,
2030 ice_debug(hw, ICE_DBG_INIT,
2031 "%s: Rx first queue ID = %d\n", prefix,
2032 caps->rxq_first_id);
2034 case ICE_AQC_CAPS_TXQS:
2035 caps->num_txq = number;
2036 caps->txq_first_id = phys_id;
2037 ice_debug(hw, ICE_DBG_INIT,
2038 "%s: num Tx queues = %d\n", prefix,
2040 ice_debug(hw, ICE_DBG_INIT,
2041 "%s: Tx first queue ID = %d\n", prefix,
2042 caps->txq_first_id);
2044 case ICE_AQC_CAPS_MSIX:
2045 caps->num_msix_vectors = number;
2046 caps->msix_vector_first_id = phys_id;
2047 ice_debug(hw, ICE_DBG_INIT,
2048 "%s: MSIX vector count = %d\n", prefix,
2049 caps->num_msix_vectors);
2050 ice_debug(hw, ICE_DBG_INIT,
2051 "%s: MSIX first vector index = %d\n", prefix,
2052 caps->msix_vector_first_id);
2054 case ICE_AQC_CAPS_FD:
2059 dev_p->num_flow_director_fltr = number;
2060 ice_debug(hw, ICE_DBG_INIT,
2061 "%s: num FD filters = %d\n", prefix,
2062 dev_p->num_flow_director_fltr);
2065 reg_val = rd32(hw, GLQF_FD_SIZE);
2066 val = (reg_val & GLQF_FD_SIZE_FD_GSIZE_M) >>
2067 GLQF_FD_SIZE_FD_GSIZE_S;
2068 func_p->fd_fltr_guar =
2069 ice_get_num_per_func(hw, val);
2070 val = (reg_val & GLQF_FD_SIZE_FD_BSIZE_M) >>
2071 GLQF_FD_SIZE_FD_BSIZE_S;
2072 func_p->fd_fltr_best_effort = val;
2073 ice_debug(hw, ICE_DBG_INIT,
2074 "%s: num guaranteed FD filters = %d\n",
2075 prefix, func_p->fd_fltr_guar);
2076 ice_debug(hw, ICE_DBG_INIT,
2077 "%s: num best effort FD filters = %d\n",
2078 prefix, func_p->fd_fltr_best_effort);
2082 case ICE_AQC_CAPS_MAX_MTU:
2083 caps->max_mtu = number;
2084 ice_debug(hw, ICE_DBG_INIT, "%s: max MTU = %d\n",
2085 prefix, caps->max_mtu);
2088 ice_debug(hw, ICE_DBG_INIT,
2089 "%s: unknown capability[%d]: 0x%x\n", prefix,
2095 /* Re-calculate capabilities that are dependent on the number of
2096 * physical ports; i.e. some features are not supported or function
2097 * differently on devices with more than 4 ports.
2099 if (caps && (ice_hweight32(caps->valid_functions) > 4)) {
2100 /* Max 4 TCs per port */
2102 ice_debug(hw, ICE_DBG_INIT,
2103 "%s: TC max = %d (based on #ports)\n", prefix,
2109 * ice_aq_discover_caps - query function/device capabilities
2110 * @hw: pointer to the HW struct
2111 * @buf: a virtual buffer to hold the capabilities
2112 * @buf_size: Size of the virtual buffer
2113 * @cap_count: cap count needed if AQ err==ENOMEM
2114 * @opc: capabilities type to discover - pass in the command opcode
2115 * @cd: pointer to command details structure or NULL
2117 * Get the function(0x000a)/device(0x000b) capabilities description from
2120 static enum ice_status
2121 ice_aq_discover_caps(struct ice_hw *hw, void *buf, u16 buf_size, u32 *cap_count,
2122 enum ice_adminq_opc opc, struct ice_sq_cd *cd)
2124 struct ice_aqc_list_caps *cmd;
2125 struct ice_aq_desc desc;
2126 enum ice_status status;
2128 cmd = &desc.params.get_cap;
2130 if (opc != ice_aqc_opc_list_func_caps &&
2131 opc != ice_aqc_opc_list_dev_caps)
2132 return ICE_ERR_PARAM;
2134 ice_fill_dflt_direct_cmd_desc(&desc, opc);
2136 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);
2138 ice_parse_caps(hw, buf, LE32_TO_CPU(cmd->count), opc);
2139 else if (hw->adminq.sq_last_status == ICE_AQ_RC_ENOMEM)
2140 *cap_count = LE32_TO_CPU(cmd->count);
2145 * ice_discover_caps - get info about the HW
2146 * @hw: pointer to the hardware structure
2147 * @opc: capabilities type to discover - pass in the command opcode
2149 static enum ice_status
2150 ice_discover_caps(struct ice_hw *hw, enum ice_adminq_opc opc)
2152 enum ice_status status;
2157 /* The driver doesn't know how many capabilities the device will return
2158 * so the buffer size required isn't known ahead of time. The driver
2159 * starts with cbuf_len and if this turns out to be insufficient, the
2160 * device returns ICE_AQ_RC_ENOMEM and also the cap_count it needs.
2161 * The driver then allocates the buffer based on the count and retries
2162 * the operation. So it follows that the retry count is 2.
2164 #define ICE_GET_CAP_BUF_COUNT 40
2165 #define ICE_GET_CAP_RETRY_COUNT 2
2167 cap_count = ICE_GET_CAP_BUF_COUNT;
2168 retries = ICE_GET_CAP_RETRY_COUNT;
2173 cbuf_len = (u16)(cap_count *
2174 sizeof(struct ice_aqc_list_caps_elem));
2175 cbuf = ice_malloc(hw, cbuf_len);
2177 return ICE_ERR_NO_MEMORY;
2179 status = ice_aq_discover_caps(hw, cbuf, cbuf_len, &cap_count,
2183 if (!status || hw->adminq.sq_last_status != ICE_AQ_RC_ENOMEM)
2186 /* If ENOMEM is returned, try again with bigger buffer */
2187 } while (--retries);
2193 * ice_get_caps - get info about the HW
2194 * @hw: pointer to the hardware structure
2196 enum ice_status ice_get_caps(struct ice_hw *hw)
2198 enum ice_status status;
2200 status = ice_discover_caps(hw, ice_aqc_opc_list_dev_caps);
2202 status = ice_discover_caps(hw, ice_aqc_opc_list_func_caps);
2208 * ice_aq_manage_mac_write - manage MAC address write command
2209 * @hw: pointer to the HW struct
2210 * @mac_addr: MAC address to be written as LAA/LAA+WoL/Port address
2211 * @flags: flags to control write behavior
2212 * @cd: pointer to command details structure or NULL
2214 * This function is used to write MAC address to the NVM (0x0108).
2217 ice_aq_manage_mac_write(struct ice_hw *hw, const u8 *mac_addr, u8 flags,
2218 struct ice_sq_cd *cd)
2220 struct ice_aqc_manage_mac_write *cmd;
2221 struct ice_aq_desc desc;
2223 cmd = &desc.params.mac_write;
2224 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_write);
2229 /* Prep values for flags, sah, sal */
2230 cmd->sah = HTONS(*((const u16 *)mac_addr));
2231 cmd->sal = HTONL(*((const u32 *)(mac_addr + 2)));
2233 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
2237 * ice_aq_clear_pxe_mode
2238 * @hw: pointer to the HW struct
2240 * Tell the firmware that the driver is taking over from PXE (0x0110).
2242 static enum ice_status ice_aq_clear_pxe_mode(struct ice_hw *hw)
2244 struct ice_aq_desc desc;
2246 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pxe_mode);
2247 desc.params.clear_pxe.rx_cnt = ICE_AQC_CLEAR_PXE_RX_CNT;
2249 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
2253 * ice_clear_pxe_mode - clear pxe operations mode
2254 * @hw: pointer to the HW struct
2256 * Make sure all PXE mode settings are cleared, including things
2257 * like descriptor fetch/write-back mode.
2259 void ice_clear_pxe_mode(struct ice_hw *hw)
2261 if (ice_check_sq_alive(hw, &hw->adminq))
2262 ice_aq_clear_pxe_mode(hw);
2267 * ice_get_link_speed_based_on_phy_type - returns link speed
2268 * @phy_type_low: lower part of phy_type
2269 * @phy_type_high: higher part of phy_type
2271 * This helper function will convert an entry in PHY type structure
2272 * [phy_type_low, phy_type_high] to its corresponding link speed.
2273 * Note: In the structure of [phy_type_low, phy_type_high], there should
2274 * be one bit set, as this function will convert one PHY type to its
2276 * If no bit gets set, ICE_LINK_SPEED_UNKNOWN will be returned
2277 * If more than one bit gets set, ICE_LINK_SPEED_UNKNOWN will be returned
2280 ice_get_link_speed_based_on_phy_type(u64 phy_type_low, u64 phy_type_high)
2282 u16 speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN;
2283 u16 speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN;
2285 switch (phy_type_low) {
2286 case ICE_PHY_TYPE_LOW_100BASE_TX:
2287 case ICE_PHY_TYPE_LOW_100M_SGMII:
2288 speed_phy_type_low = ICE_AQ_LINK_SPEED_100MB;
2290 case ICE_PHY_TYPE_LOW_1000BASE_T:
2291 case ICE_PHY_TYPE_LOW_1000BASE_SX:
2292 case ICE_PHY_TYPE_LOW_1000BASE_LX:
2293 case ICE_PHY_TYPE_LOW_1000BASE_KX:
2294 case ICE_PHY_TYPE_LOW_1G_SGMII:
2295 speed_phy_type_low = ICE_AQ_LINK_SPEED_1000MB;
2297 case ICE_PHY_TYPE_LOW_2500BASE_T:
2298 case ICE_PHY_TYPE_LOW_2500BASE_X:
2299 case ICE_PHY_TYPE_LOW_2500BASE_KX:
2300 speed_phy_type_low = ICE_AQ_LINK_SPEED_2500MB;
2302 case ICE_PHY_TYPE_LOW_5GBASE_T:
2303 case ICE_PHY_TYPE_LOW_5GBASE_KR:
2304 speed_phy_type_low = ICE_AQ_LINK_SPEED_5GB;
2306 case ICE_PHY_TYPE_LOW_10GBASE_T:
2307 case ICE_PHY_TYPE_LOW_10G_SFI_DA:
2308 case ICE_PHY_TYPE_LOW_10GBASE_SR:
2309 case ICE_PHY_TYPE_LOW_10GBASE_LR:
2310 case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1:
2311 case ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC:
2312 case ICE_PHY_TYPE_LOW_10G_SFI_C2C:
2313 speed_phy_type_low = ICE_AQ_LINK_SPEED_10GB;
2315 case ICE_PHY_TYPE_LOW_25GBASE_T:
2316 case ICE_PHY_TYPE_LOW_25GBASE_CR:
2317 case ICE_PHY_TYPE_LOW_25GBASE_CR_S:
2318 case ICE_PHY_TYPE_LOW_25GBASE_CR1:
2319 case ICE_PHY_TYPE_LOW_25GBASE_SR:
2320 case ICE_PHY_TYPE_LOW_25GBASE_LR:
2321 case ICE_PHY_TYPE_LOW_25GBASE_KR:
2322 case ICE_PHY_TYPE_LOW_25GBASE_KR_S:
2323 case ICE_PHY_TYPE_LOW_25GBASE_KR1:
2324 case ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC:
2325 case ICE_PHY_TYPE_LOW_25G_AUI_C2C:
2326 speed_phy_type_low = ICE_AQ_LINK_SPEED_25GB;
2328 case ICE_PHY_TYPE_LOW_40GBASE_CR4:
2329 case ICE_PHY_TYPE_LOW_40GBASE_SR4:
2330 case ICE_PHY_TYPE_LOW_40GBASE_LR4:
2331 case ICE_PHY_TYPE_LOW_40GBASE_KR4:
2332 case ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC:
2333 case ICE_PHY_TYPE_LOW_40G_XLAUI:
2334 speed_phy_type_low = ICE_AQ_LINK_SPEED_40GB;
2336 case ICE_PHY_TYPE_LOW_50GBASE_CR2:
2337 case ICE_PHY_TYPE_LOW_50GBASE_SR2:
2338 case ICE_PHY_TYPE_LOW_50GBASE_LR2:
2339 case ICE_PHY_TYPE_LOW_50GBASE_KR2:
2340 case ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC:
2341 case ICE_PHY_TYPE_LOW_50G_LAUI2:
2342 case ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC:
2343 case ICE_PHY_TYPE_LOW_50G_AUI2:
2344 case ICE_PHY_TYPE_LOW_50GBASE_CP:
2345 case ICE_PHY_TYPE_LOW_50GBASE_SR:
2346 case ICE_PHY_TYPE_LOW_50GBASE_FR:
2347 case ICE_PHY_TYPE_LOW_50GBASE_LR:
2348 case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4:
2349 case ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC:
2350 case ICE_PHY_TYPE_LOW_50G_AUI1:
2351 speed_phy_type_low = ICE_AQ_LINK_SPEED_50GB;
2353 case ICE_PHY_TYPE_LOW_100GBASE_CR4:
2354 case ICE_PHY_TYPE_LOW_100GBASE_SR4:
2355 case ICE_PHY_TYPE_LOW_100GBASE_LR4:
2356 case ICE_PHY_TYPE_LOW_100GBASE_KR4:
2357 case ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC:
2358 case ICE_PHY_TYPE_LOW_100G_CAUI4:
2359 case ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC:
2360 case ICE_PHY_TYPE_LOW_100G_AUI4:
2361 case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4:
2362 case ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4:
2363 case ICE_PHY_TYPE_LOW_100GBASE_CP2:
2364 case ICE_PHY_TYPE_LOW_100GBASE_SR2:
2365 case ICE_PHY_TYPE_LOW_100GBASE_DR:
2366 speed_phy_type_low = ICE_AQ_LINK_SPEED_100GB;
2369 speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN;
2373 switch (phy_type_high) {
2374 case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4:
2375 case ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC:
2376 case ICE_PHY_TYPE_HIGH_100G_CAUI2:
2377 case ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC:
2378 case ICE_PHY_TYPE_HIGH_100G_AUI2:
2379 speed_phy_type_high = ICE_AQ_LINK_SPEED_100GB;
2382 speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN;
2386 if (speed_phy_type_low == ICE_AQ_LINK_SPEED_UNKNOWN &&
2387 speed_phy_type_high == ICE_AQ_LINK_SPEED_UNKNOWN)
2388 return ICE_AQ_LINK_SPEED_UNKNOWN;
2389 else if (speed_phy_type_low != ICE_AQ_LINK_SPEED_UNKNOWN &&
2390 speed_phy_type_high != ICE_AQ_LINK_SPEED_UNKNOWN)
2391 return ICE_AQ_LINK_SPEED_UNKNOWN;
2392 else if (speed_phy_type_low != ICE_AQ_LINK_SPEED_UNKNOWN &&
2393 speed_phy_type_high == ICE_AQ_LINK_SPEED_UNKNOWN)
2394 return speed_phy_type_low;
2396 return speed_phy_type_high;
2400 * ice_update_phy_type
2401 * @phy_type_low: pointer to the lower part of phy_type
2402 * @phy_type_high: pointer to the higher part of phy_type
2403 * @link_speeds_bitmap: targeted link speeds bitmap
2405 * Note: For the link_speeds_bitmap structure, you can check it at
2406 * [ice_aqc_get_link_status->link_speed]. Caller can pass in
2407 * link_speeds_bitmap include multiple speeds.
2409 * Each entry in this [phy_type_low, phy_type_high] structure will
2410 * present a certain link speed. This helper function will turn on bits
2411 * in [phy_type_low, phy_type_high] structure based on the value of
2412 * link_speeds_bitmap input parameter.
2415 ice_update_phy_type(u64 *phy_type_low, u64 *phy_type_high,
2416 u16 link_speeds_bitmap)
2423 /* We first check with low part of phy_type */
2424 for (index = 0; index <= ICE_PHY_TYPE_LOW_MAX_INDEX; index++) {
2425 pt_low = BIT_ULL(index);
2426 speed = ice_get_link_speed_based_on_phy_type(pt_low, 0);
2428 if (link_speeds_bitmap & speed)
2429 *phy_type_low |= BIT_ULL(index);
2432 /* We then check with high part of phy_type */
2433 for (index = 0; index <= ICE_PHY_TYPE_HIGH_MAX_INDEX; index++) {
2434 pt_high = BIT_ULL(index);
2435 speed = ice_get_link_speed_based_on_phy_type(0, pt_high);
2437 if (link_speeds_bitmap & speed)
2438 *phy_type_high |= BIT_ULL(index);
2443 * ice_aq_set_phy_cfg
2444 * @hw: pointer to the HW struct
2445 * @pi: port info structure of the interested logical port
2446 * @cfg: structure with PHY configuration data to be set
2447 * @cd: pointer to command details structure or NULL
2449 * Set the various PHY configuration parameters supported on the Port.
2450 * One or more of the Set PHY config parameters may be ignored in an MFP
2451 * mode as the PF may not have the privilege to set some of the PHY Config
2452 * parameters. This status will be indicated by the command response (0x0601).
2455 ice_aq_set_phy_cfg(struct ice_hw *hw, struct ice_port_info *pi,
2456 struct ice_aqc_set_phy_cfg_data *cfg, struct ice_sq_cd *cd)
2458 struct ice_aq_desc desc;
2459 enum ice_status status;
2462 return ICE_ERR_PARAM;
2464 /* Ensure that only valid bits of cfg->caps can be turned on. */
2465 if (cfg->caps & ~ICE_AQ_PHY_ENA_VALID_MASK) {
2466 ice_debug(hw, ICE_DBG_PHY,
2467 "Invalid bit is set in ice_aqc_set_phy_cfg_data->caps : 0x%x\n",
2470 cfg->caps &= ICE_AQ_PHY_ENA_VALID_MASK;
2473 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_phy_cfg);
2474 desc.params.set_phy.lport_num = pi->lport;
2475 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
2477 ice_debug(hw, ICE_DBG_LINK, "phy_type_low = 0x%llx\n",
2478 (unsigned long long)LE64_TO_CPU(cfg->phy_type_low));
2479 ice_debug(hw, ICE_DBG_LINK, "phy_type_high = 0x%llx\n",
2480 (unsigned long long)LE64_TO_CPU(cfg->phy_type_high));
2481 ice_debug(hw, ICE_DBG_LINK, "caps = 0x%x\n", cfg->caps);
2482 ice_debug(hw, ICE_DBG_LINK, "low_power_ctrl = 0x%x\n",
2483 cfg->low_power_ctrl);
2484 ice_debug(hw, ICE_DBG_LINK, "eee_cap = 0x%x\n", cfg->eee_cap);
2485 ice_debug(hw, ICE_DBG_LINK, "eeer_value = 0x%x\n", cfg->eeer_value);
2486 ice_debug(hw, ICE_DBG_LINK, "link_fec_opt = 0x%x\n", cfg->link_fec_opt);
2488 status = ice_aq_send_cmd(hw, &desc, cfg, sizeof(*cfg), cd);
2491 pi->phy.curr_user_phy_cfg = *cfg;
2497 * ice_update_link_info - update status of the HW network link
2498 * @pi: port info structure of the interested logical port
2500 enum ice_status ice_update_link_info(struct ice_port_info *pi)
2502 struct ice_link_status *li;
2503 enum ice_status status;
2506 return ICE_ERR_PARAM;
2508 li = &pi->phy.link_info;
2510 status = ice_aq_get_link_info(pi, true, NULL, NULL);
2514 if (li->link_info & ICE_AQ_MEDIA_AVAILABLE) {
2515 struct ice_aqc_get_phy_caps_data *pcaps;
2519 pcaps = (struct ice_aqc_get_phy_caps_data *)
2520 ice_malloc(hw, sizeof(*pcaps));
2522 return ICE_ERR_NO_MEMORY;
2524 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_TOPO_CAP,
2526 if (status == ICE_SUCCESS)
2527 ice_memcpy(li->module_type, &pcaps->module_type,
2528 sizeof(li->module_type),
2529 ICE_NONDMA_TO_NONDMA);
2531 ice_free(hw, pcaps);
2538 * ice_cache_phy_user_req
2539 * @pi: port information structure
2540 * @cache_data: PHY logging data
2541 * @cache_mode: PHY logging mode
2543 * Log the user request on (FC, FEC, SPEED) for later user.
2546 ice_cache_phy_user_req(struct ice_port_info *pi,
2547 struct ice_phy_cache_mode_data cache_data,
2548 enum ice_phy_cache_mode cache_mode)
2553 switch (cache_mode) {
2555 pi->phy.curr_user_fc_req = cache_data.data.curr_user_fc_req;
2557 case ICE_SPEED_MODE:
2558 pi->phy.curr_user_speed_req =
2559 cache_data.data.curr_user_speed_req;
2562 pi->phy.curr_user_fec_req = cache_data.data.curr_user_fec_req;
2571 * @pi: port information structure
2572 * @aq_failures: pointer to status code, specific to ice_set_fc routine
2573 * @ena_auto_link_update: enable automatic link update
2575 * Set the requested flow control mode.
2578 ice_set_fc(struct ice_port_info *pi, u8 *aq_failures, bool ena_auto_link_update)
2580 struct ice_aqc_set_phy_cfg_data cfg = { 0 };
2581 struct ice_phy_cache_mode_data cache_data;
2582 struct ice_aqc_get_phy_caps_data *pcaps;
2583 enum ice_status status;
2584 u8 pause_mask = 0x0;
2588 return ICE_ERR_PARAM;
2590 *aq_failures = ICE_SET_FC_AQ_FAIL_NONE;
2592 /* Cache user FC request */
2593 cache_data.data.curr_user_fc_req = pi->fc.req_mode;
2594 ice_cache_phy_user_req(pi, cache_data, ICE_FC_MODE);
2596 switch (pi->fc.req_mode) {
2598 pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE;
2599 pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE;
2601 case ICE_FC_RX_PAUSE:
2602 pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE;
2604 case ICE_FC_TX_PAUSE:
2605 pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE;
2611 pcaps = (struct ice_aqc_get_phy_caps_data *)
2612 ice_malloc(hw, sizeof(*pcaps));
2614 return ICE_ERR_NO_MEMORY;
2616 /* Get the current PHY config */
2617 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_SW_CFG, pcaps,
2620 *aq_failures = ICE_SET_FC_AQ_FAIL_GET;
2624 /* clear the old pause settings */
2625 cfg.caps = pcaps->caps & ~(ICE_AQC_PHY_EN_TX_LINK_PAUSE |
2626 ICE_AQC_PHY_EN_RX_LINK_PAUSE);
2628 /* set the new capabilities */
2629 cfg.caps |= pause_mask;
2631 /* If the capabilities have changed, then set the new config */
2632 if (cfg.caps != pcaps->caps) {
2633 int retry_count, retry_max = 10;
2635 /* Auto restart link so settings take effect */
2636 if (ena_auto_link_update)
2637 cfg.caps |= ICE_AQ_PHY_ENA_AUTO_LINK_UPDT;
2638 /* Copy over all the old settings */
2639 cfg.phy_type_high = pcaps->phy_type_high;
2640 cfg.phy_type_low = pcaps->phy_type_low;
2641 cfg.low_power_ctrl = pcaps->low_power_ctrl;
2642 cfg.eee_cap = pcaps->eee_cap;
2643 cfg.eeer_value = pcaps->eeer_value;
2644 cfg.link_fec_opt = pcaps->link_fec_options;
2646 status = ice_aq_set_phy_cfg(hw, pi, &cfg, NULL);
2648 *aq_failures = ICE_SET_FC_AQ_FAIL_SET;
2652 /* Update the link info
2653 * It sometimes takes a really long time for link to
2654 * come back from the atomic reset. Thus, we wait a
2657 for (retry_count = 0; retry_count < retry_max; retry_count++) {
2658 status = ice_update_link_info(pi);
2660 if (status == ICE_SUCCESS)
2663 ice_msec_delay(100, true);
2667 *aq_failures = ICE_SET_FC_AQ_FAIL_UPDATE;
2671 ice_free(hw, pcaps);
2676 * ice_copy_phy_caps_to_cfg - Copy PHY ability data to configuration data
2677 * @caps: PHY ability structure to copy date from
2678 * @cfg: PHY configuration structure to copy data to
2680 * Helper function to copy AQC PHY get ability data to PHY set configuration
2684 ice_copy_phy_caps_to_cfg(struct ice_aqc_get_phy_caps_data *caps,
2685 struct ice_aqc_set_phy_cfg_data *cfg)
2690 cfg->phy_type_low = caps->phy_type_low;
2691 cfg->phy_type_high = caps->phy_type_high;
2692 cfg->caps = caps->caps;
2693 cfg->low_power_ctrl = caps->low_power_ctrl;
2694 cfg->eee_cap = caps->eee_cap;
2695 cfg->eeer_value = caps->eeer_value;
2696 cfg->link_fec_opt = caps->link_fec_options;
2700 * ice_cfg_phy_fec - Configure PHY FEC data based on FEC mode
2701 * @cfg: PHY configuration data to set FEC mode
2702 * @fec: FEC mode to configure
2704 * Caller should copy ice_aqc_get_phy_caps_data.caps ICE_AQC_PHY_EN_AUTO_FEC
2705 * (bit 7) and ice_aqc_get_phy_caps_data.link_fec_options to cfg.caps
2706 * ICE_AQ_PHY_ENA_AUTO_FEC (bit 7) and cfg.link_fec_options before calling.
2709 ice_cfg_phy_fec(struct ice_aqc_set_phy_cfg_data *cfg, enum ice_fec_mode fec)
2713 /* Clear RS bits, and AND BASE-R ability
2714 * bits and OR request bits.
2716 cfg->link_fec_opt &= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN |
2717 ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN;
2718 cfg->link_fec_opt |= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ |
2719 ICE_AQC_PHY_FEC_25G_KR_REQ;
2722 /* Clear BASE-R bits, and AND RS ability
2723 * bits and OR request bits.
2725 cfg->link_fec_opt &= ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN;
2726 cfg->link_fec_opt |= ICE_AQC_PHY_FEC_25G_RS_528_REQ |
2727 ICE_AQC_PHY_FEC_25G_RS_544_REQ;
2730 /* Clear all FEC option bits. */
2731 cfg->link_fec_opt &= ~ICE_AQC_PHY_FEC_MASK;
2734 /* AND auto FEC bit, and all caps bits. */
2735 cfg->caps &= ICE_AQC_PHY_CAPS_MASK;
2741 * ice_get_link_status - get status of the HW network link
2742 * @pi: port information structure
2743 * @link_up: pointer to bool (true/false = linkup/linkdown)
2745 * Variable link_up is true if link is up, false if link is down.
2746 * The variable link_up is invalid if status is non zero. As a
2747 * result of this call, link status reporting becomes enabled
2749 enum ice_status ice_get_link_status(struct ice_port_info *pi, bool *link_up)
2751 struct ice_phy_info *phy_info;
2752 enum ice_status status = ICE_SUCCESS;
2754 if (!pi || !link_up)
2755 return ICE_ERR_PARAM;
2757 phy_info = &pi->phy;
2759 if (phy_info->get_link_info) {
2760 status = ice_update_link_info(pi);
2763 ice_debug(pi->hw, ICE_DBG_LINK,
2764 "get link status error, status = %d\n",
2768 *link_up = phy_info->link_info.link_info & ICE_AQ_LINK_UP;
2774 * ice_aq_set_link_restart_an
2775 * @pi: pointer to the port information structure
2776 * @ena_link: if true: enable link, if false: disable link
2777 * @cd: pointer to command details structure or NULL
2779 * Sets up the link and restarts the Auto-Negotiation over the link.
2782 ice_aq_set_link_restart_an(struct ice_port_info *pi, bool ena_link,
2783 struct ice_sq_cd *cd)
2785 struct ice_aqc_restart_an *cmd;
2786 struct ice_aq_desc desc;
2788 cmd = &desc.params.restart_an;
2790 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_restart_an);
2792 cmd->cmd_flags = ICE_AQC_RESTART_AN_LINK_RESTART;
2793 cmd->lport_num = pi->lport;
2795 cmd->cmd_flags |= ICE_AQC_RESTART_AN_LINK_ENABLE;
2797 cmd->cmd_flags &= ~ICE_AQC_RESTART_AN_LINK_ENABLE;
2799 return ice_aq_send_cmd(pi->hw, &desc, NULL, 0, cd);
2803 * ice_aq_set_event_mask
2804 * @hw: pointer to the HW struct
2805 * @port_num: port number of the physical function
2806 * @mask: event mask to be set
2807 * @cd: pointer to command details structure or NULL
2809 * Set event mask (0x0613)
2812 ice_aq_set_event_mask(struct ice_hw *hw, u8 port_num, u16 mask,
2813 struct ice_sq_cd *cd)
2815 struct ice_aqc_set_event_mask *cmd;
2816 struct ice_aq_desc desc;
2818 cmd = &desc.params.set_event_mask;
2820 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_event_mask);
2822 cmd->lport_num = port_num;
2824 cmd->event_mask = CPU_TO_LE16(mask);
2825 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
2829 * ice_aq_set_mac_loopback
2830 * @hw: pointer to the HW struct
2831 * @ena_lpbk: Enable or Disable loopback
2832 * @cd: pointer to command details structure or NULL
2834 * Enable/disable loopback on a given port
2837 ice_aq_set_mac_loopback(struct ice_hw *hw, bool ena_lpbk, struct ice_sq_cd *cd)
2839 struct ice_aqc_set_mac_lb *cmd;
2840 struct ice_aq_desc desc;
2842 cmd = &desc.params.set_mac_lb;
2844 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_mac_lb);
2846 cmd->lb_mode = ICE_AQ_MAC_LB_EN;
2848 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
2853 * ice_aq_set_port_id_led
2854 * @pi: pointer to the port information
2855 * @is_orig_mode: is this LED set to original mode (by the net-list)
2856 * @cd: pointer to command details structure or NULL
2858 * Set LED value for the given port (0x06e9)
2861 ice_aq_set_port_id_led(struct ice_port_info *pi, bool is_orig_mode,
2862 struct ice_sq_cd *cd)
2864 struct ice_aqc_set_port_id_led *cmd;
2865 struct ice_hw *hw = pi->hw;
2866 struct ice_aq_desc desc;
2868 cmd = &desc.params.set_port_id_led;
2870 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_port_id_led);
2874 cmd->ident_mode = ICE_AQC_PORT_IDENT_LED_ORIG;
2876 cmd->ident_mode = ICE_AQC_PORT_IDENT_LED_BLINK;
2878 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
2882 * __ice_aq_get_set_rss_lut
2883 * @hw: pointer to the hardware structure
2884 * @vsi_id: VSI FW index
2885 * @lut_type: LUT table type
2886 * @lut: pointer to the LUT buffer provided by the caller
2887 * @lut_size: size of the LUT buffer
2888 * @glob_lut_idx: global LUT index
2889 * @set: set true to set the table, false to get the table
2891 * Internal function to get (0x0B05) or set (0x0B03) RSS look up table
2893 static enum ice_status
2894 __ice_aq_get_set_rss_lut(struct ice_hw *hw, u16 vsi_id, u8 lut_type, u8 *lut,
2895 u16 lut_size, u8 glob_lut_idx, bool set)
2897 struct ice_aqc_get_set_rss_lut *cmd_resp;
2898 struct ice_aq_desc desc;
2899 enum ice_status status;
2902 cmd_resp = &desc.params.get_set_rss_lut;
2905 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_rss_lut);
2906 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
2908 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_rss_lut);
2911 cmd_resp->vsi_id = CPU_TO_LE16(((vsi_id <<
2912 ICE_AQC_GSET_RSS_LUT_VSI_ID_S) &
2913 ICE_AQC_GSET_RSS_LUT_VSI_ID_M) |
2914 ICE_AQC_GSET_RSS_LUT_VSI_VALID);
2917 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_VSI:
2918 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF:
2919 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL:
2920 flags |= ((lut_type << ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S) &
2921 ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_M);
2924 status = ICE_ERR_PARAM;
2925 goto ice_aq_get_set_rss_lut_exit;
2928 if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL) {
2929 flags |= ((glob_lut_idx << ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S) &
2930 ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_M);
2933 goto ice_aq_get_set_rss_lut_send;
2934 } else if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF) {
2936 goto ice_aq_get_set_rss_lut_send;
2938 goto ice_aq_get_set_rss_lut_send;
2941 /* LUT size is only valid for Global and PF table types */
2943 case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128:
2944 flags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128_FLAG <<
2945 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) &
2946 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M;
2948 case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512:
2949 flags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512_FLAG <<
2950 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) &
2951 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M;
2953 case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K:
2954 if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF) {
2955 flags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K_FLAG <<
2956 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) &
2957 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M;
2962 status = ICE_ERR_PARAM;
2963 goto ice_aq_get_set_rss_lut_exit;
2966 ice_aq_get_set_rss_lut_send:
2967 cmd_resp->flags = CPU_TO_LE16(flags);
2968 status = ice_aq_send_cmd(hw, &desc, lut, lut_size, NULL);
2970 ice_aq_get_set_rss_lut_exit:
2975 * ice_aq_get_rss_lut
2976 * @hw: pointer to the hardware structure
2977 * @vsi_handle: software VSI handle
2978 * @lut_type: LUT table type
2979 * @lut: pointer to the LUT buffer provided by the caller
2980 * @lut_size: size of the LUT buffer
2982 * get the RSS lookup table, PF or VSI type
2985 ice_aq_get_rss_lut(struct ice_hw *hw, u16 vsi_handle, u8 lut_type,
2986 u8 *lut, u16 lut_size)
2988 if (!ice_is_vsi_valid(hw, vsi_handle) || !lut)
2989 return ICE_ERR_PARAM;
2991 return __ice_aq_get_set_rss_lut(hw, ice_get_hw_vsi_num(hw, vsi_handle),
2992 lut_type, lut, lut_size, 0, false);
2996 * ice_aq_set_rss_lut
2997 * @hw: pointer to the hardware structure
2998 * @vsi_handle: software VSI handle
2999 * @lut_type: LUT table type
3000 * @lut: pointer to the LUT buffer provided by the caller
3001 * @lut_size: size of the LUT buffer
3003 * set the RSS lookup table, PF or VSI type
3006 ice_aq_set_rss_lut(struct ice_hw *hw, u16 vsi_handle, u8 lut_type,
3007 u8 *lut, u16 lut_size)
3009 if (!ice_is_vsi_valid(hw, vsi_handle) || !lut)
3010 return ICE_ERR_PARAM;
3012 return __ice_aq_get_set_rss_lut(hw, ice_get_hw_vsi_num(hw, vsi_handle),
3013 lut_type, lut, lut_size, 0, true);
3017 * __ice_aq_get_set_rss_key
3018 * @hw: pointer to the HW struct
3019 * @vsi_id: VSI FW index
3020 * @key: pointer to key info struct
3021 * @set: set true to set the key, false to get the key
3023 * get (0x0B04) or set (0x0B02) the RSS key per VSI
3026 ice_status __ice_aq_get_set_rss_key(struct ice_hw *hw, u16 vsi_id,
3027 struct ice_aqc_get_set_rss_keys *key,
3030 struct ice_aqc_get_set_rss_key *cmd_resp;
3031 u16 key_size = sizeof(*key);
3032 struct ice_aq_desc desc;
3034 cmd_resp = &desc.params.get_set_rss_key;
3037 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_rss_key);
3038 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
3040 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_rss_key);
3043 cmd_resp->vsi_id = CPU_TO_LE16(((vsi_id <<
3044 ICE_AQC_GSET_RSS_KEY_VSI_ID_S) &
3045 ICE_AQC_GSET_RSS_KEY_VSI_ID_M) |
3046 ICE_AQC_GSET_RSS_KEY_VSI_VALID);
3048 return ice_aq_send_cmd(hw, &desc, key, key_size, NULL);
3052 * ice_aq_get_rss_key
3053 * @hw: pointer to the HW struct
3054 * @vsi_handle: software VSI handle
3055 * @key: pointer to key info struct
3057 * get the RSS key per VSI
3060 ice_aq_get_rss_key(struct ice_hw *hw, u16 vsi_handle,
3061 struct ice_aqc_get_set_rss_keys *key)
3063 if (!ice_is_vsi_valid(hw, vsi_handle) || !key)
3064 return ICE_ERR_PARAM;
3066 return __ice_aq_get_set_rss_key(hw, ice_get_hw_vsi_num(hw, vsi_handle),
3071 * ice_aq_set_rss_key
3072 * @hw: pointer to the HW struct
3073 * @vsi_handle: software VSI handle
3074 * @keys: pointer to key info struct
3076 * set the RSS key per VSI
3079 ice_aq_set_rss_key(struct ice_hw *hw, u16 vsi_handle,
3080 struct ice_aqc_get_set_rss_keys *keys)
3082 if (!ice_is_vsi_valid(hw, vsi_handle) || !keys)
3083 return ICE_ERR_PARAM;
3085 return __ice_aq_get_set_rss_key(hw, ice_get_hw_vsi_num(hw, vsi_handle),
3090 * ice_aq_add_lan_txq
3091 * @hw: pointer to the hardware structure
3092 * @num_qgrps: Number of added queue groups
3093 * @qg_list: list of queue groups to be added
3094 * @buf_size: size of buffer for indirect command
3095 * @cd: pointer to command details structure or NULL
3097 * Add Tx LAN queue (0x0C30)
3100 * Prior to calling add Tx LAN queue:
3101 * Initialize the following as part of the Tx queue context:
3102 * Completion queue ID if the queue uses Completion queue, Quanta profile,
3103 * Cache profile and Packet shaper profile.
3105 * After add Tx LAN queue AQ command is completed:
3106 * Interrupts should be associated with specific queues,
3107 * Association of Tx queue to Doorbell queue is not part of Add LAN Tx queue
3111 ice_aq_add_lan_txq(struct ice_hw *hw, u8 num_qgrps,
3112 struct ice_aqc_add_tx_qgrp *qg_list, u16 buf_size,
3113 struct ice_sq_cd *cd)
3115 u16 i, sum_header_size, sum_q_size = 0;
3116 struct ice_aqc_add_tx_qgrp *list;
3117 struct ice_aqc_add_txqs *cmd;
3118 struct ice_aq_desc desc;
3120 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
3122 cmd = &desc.params.add_txqs;
3124 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_add_txqs);
3127 return ICE_ERR_PARAM;
3129 if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS)
3130 return ICE_ERR_PARAM;
3132 sum_header_size = num_qgrps *
3133 (sizeof(*qg_list) - sizeof(*qg_list->txqs));
3136 for (i = 0; i < num_qgrps; i++) {
3137 struct ice_aqc_add_txqs_perq *q = list->txqs;
3139 sum_q_size += list->num_txqs * sizeof(*q);
3140 list = (struct ice_aqc_add_tx_qgrp *)(q + list->num_txqs);
3143 if (buf_size != (sum_header_size + sum_q_size))
3144 return ICE_ERR_PARAM;
3146 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
3148 cmd->num_qgrps = num_qgrps;
3150 return ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd);
3154 * ice_aq_dis_lan_txq
3155 * @hw: pointer to the hardware structure
3156 * @num_qgrps: number of groups in the list
3157 * @qg_list: the list of groups to disable
3158 * @buf_size: the total size of the qg_list buffer in bytes
3159 * @rst_src: if called due to reset, specifies the reset source
3160 * @vmvf_num: the relative VM or VF number that is undergoing the reset
3161 * @cd: pointer to command details structure or NULL
3163 * Disable LAN Tx queue (0x0C31)
3165 static enum ice_status
3166 ice_aq_dis_lan_txq(struct ice_hw *hw, u8 num_qgrps,
3167 struct ice_aqc_dis_txq_item *qg_list, u16 buf_size,
3168 enum ice_disq_rst_src rst_src, u16 vmvf_num,
3169 struct ice_sq_cd *cd)
3171 struct ice_aqc_dis_txqs *cmd;
3172 struct ice_aq_desc desc;
3173 enum ice_status status;
3176 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
3177 cmd = &desc.params.dis_txqs;
3178 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_dis_txqs);
3180 /* qg_list can be NULL only in VM/VF reset flow */
3181 if (!qg_list && !rst_src)
3182 return ICE_ERR_PARAM;
3184 if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS)
3185 return ICE_ERR_PARAM;
3187 cmd->num_entries = num_qgrps;
3189 cmd->vmvf_and_timeout = CPU_TO_LE16((5 << ICE_AQC_Q_DIS_TIMEOUT_S) &
3190 ICE_AQC_Q_DIS_TIMEOUT_M);
3194 cmd->cmd_type = ICE_AQC_Q_DIS_CMD_VM_RESET;
3195 cmd->vmvf_and_timeout |=
3196 CPU_TO_LE16(vmvf_num & ICE_AQC_Q_DIS_VMVF_NUM_M);
3203 /* flush pipe on time out */
3204 cmd->cmd_type |= ICE_AQC_Q_DIS_CMD_FLUSH_PIPE;
3205 /* If no queue group info, we are in a reset flow. Issue the AQ */
3209 /* set RD bit to indicate that command buffer is provided by the driver
3210 * and it needs to be read by the firmware
3212 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
3214 for (i = 0; i < num_qgrps; ++i) {
3215 /* Calculate the size taken up by the queue IDs in this group */
3216 sz += qg_list[i].num_qs * sizeof(qg_list[i].q_id);
3218 /* Add the size of the group header */
3219 sz += sizeof(qg_list[i]) - sizeof(qg_list[i].q_id);
3221 /* If the num of queues is even, add 2 bytes of padding */
3222 if ((qg_list[i].num_qs % 2) == 0)
3227 return ICE_ERR_PARAM;
3230 status = ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd);
3233 ice_debug(hw, ICE_DBG_SCHED, "VM%d disable failed %d\n",
3234 vmvf_num, hw->adminq.sq_last_status);
3236 ice_debug(hw, ICE_DBG_SCHED, "disable queue %d failed %d\n",
3237 LE16_TO_CPU(qg_list[0].q_id[0]),
3238 hw->adminq.sq_last_status);
3244 /* End of FW Admin Queue command wrappers */
3247 * ice_write_byte - write a byte to a packed context structure
3248 * @src_ctx: the context structure to read from
3249 * @dest_ctx: the context to be written to
3250 * @ce_info: a description of the struct to be filled
3253 ice_write_byte(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)
3255 u8 src_byte, dest_byte, mask;
3259 /* copy from the next struct field */
3260 from = src_ctx + ce_info->offset;
3262 /* prepare the bits and mask */
3263 shift_width = ce_info->lsb % 8;
3264 mask = (u8)(BIT(ce_info->width) - 1);
3269 /* shift to correct alignment */
3270 mask <<= shift_width;
3271 src_byte <<= shift_width;
3273 /* get the current bits from the target bit string */
3274 dest = dest_ctx + (ce_info->lsb / 8);
3276 ice_memcpy(&dest_byte, dest, sizeof(dest_byte), ICE_DMA_TO_NONDMA);
3278 dest_byte &= ~mask; /* get the bits not changing */
3279 dest_byte |= src_byte; /* add in the new bits */
3281 /* put it all back */
3282 ice_memcpy(dest, &dest_byte, sizeof(dest_byte), ICE_NONDMA_TO_DMA);
3286 * ice_write_word - write a word to a packed context structure
3287 * @src_ctx: the context structure to read from
3288 * @dest_ctx: the context to be written to
3289 * @ce_info: a description of the struct to be filled
3292 ice_write_word(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)
3299 /* copy from the next struct field */
3300 from = src_ctx + ce_info->offset;
3302 /* prepare the bits and mask */
3303 shift_width = ce_info->lsb % 8;
3304 mask = BIT(ce_info->width) - 1;
3306 /* don't swizzle the bits until after the mask because the mask bits
3307 * will be in a different bit position on big endian machines
3309 src_word = *(u16 *)from;
3312 /* shift to correct alignment */
3313 mask <<= shift_width;
3314 src_word <<= shift_width;
3316 /* get the current bits from the target bit string */
3317 dest = dest_ctx + (ce_info->lsb / 8);
3319 ice_memcpy(&dest_word, dest, sizeof(dest_word), ICE_DMA_TO_NONDMA);
3321 dest_word &= ~(CPU_TO_LE16(mask)); /* get the bits not changing */
3322 dest_word |= CPU_TO_LE16(src_word); /* add in the new bits */
3324 /* put it all back */
3325 ice_memcpy(dest, &dest_word, sizeof(dest_word), ICE_NONDMA_TO_DMA);
3329 * ice_write_dword - write a dword to a packed context structure
3330 * @src_ctx: the context structure to read from
3331 * @dest_ctx: the context to be written to
3332 * @ce_info: a description of the struct to be filled
3335 ice_write_dword(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)
3337 u32 src_dword, mask;
3342 /* copy from the next struct field */
3343 from = src_ctx + ce_info->offset;
3345 /* prepare the bits and mask */
3346 shift_width = ce_info->lsb % 8;
3348 /* if the field width is exactly 32 on an x86 machine, then the shift
3349 * operation will not work because the SHL instructions count is masked
3350 * to 5 bits so the shift will do nothing
3352 if (ce_info->width < 32)
3353 mask = BIT(ce_info->width) - 1;
3357 /* don't swizzle the bits until after the mask because the mask bits
3358 * will be in a different bit position on big endian machines
3360 src_dword = *(u32 *)from;
3363 /* shift to correct alignment */
3364 mask <<= shift_width;
3365 src_dword <<= shift_width;
3367 /* get the current bits from the target bit string */
3368 dest = dest_ctx + (ce_info->lsb / 8);
3370 ice_memcpy(&dest_dword, dest, sizeof(dest_dword), ICE_DMA_TO_NONDMA);
3372 dest_dword &= ~(CPU_TO_LE32(mask)); /* get the bits not changing */
3373 dest_dword |= CPU_TO_LE32(src_dword); /* add in the new bits */
3375 /* put it all back */
3376 ice_memcpy(dest, &dest_dword, sizeof(dest_dword), ICE_NONDMA_TO_DMA);
3380 * ice_write_qword - write a qword to a packed context structure
3381 * @src_ctx: the context structure to read from
3382 * @dest_ctx: the context to be written to
3383 * @ce_info: a description of the struct to be filled
3386 ice_write_qword(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)
3388 u64 src_qword, mask;
3393 /* copy from the next struct field */
3394 from = src_ctx + ce_info->offset;
3396 /* prepare the bits and mask */
3397 shift_width = ce_info->lsb % 8;
3399 /* if the field width is exactly 64 on an x86 machine, then the shift
3400 * operation will not work because the SHL instructions count is masked
3401 * to 6 bits so the shift will do nothing
3403 if (ce_info->width < 64)
3404 mask = BIT_ULL(ce_info->width) - 1;
3408 /* don't swizzle the bits until after the mask because the mask bits
3409 * will be in a different bit position on big endian machines
3411 src_qword = *(u64 *)from;
3414 /* shift to correct alignment */
3415 mask <<= shift_width;
3416 src_qword <<= shift_width;
3418 /* get the current bits from the target bit string */
3419 dest = dest_ctx + (ce_info->lsb / 8);
3421 ice_memcpy(&dest_qword, dest, sizeof(dest_qword), ICE_DMA_TO_NONDMA);
3423 dest_qword &= ~(CPU_TO_LE64(mask)); /* get the bits not changing */
3424 dest_qword |= CPU_TO_LE64(src_qword); /* add in the new bits */
3426 /* put it all back */
3427 ice_memcpy(dest, &dest_qword, sizeof(dest_qword), ICE_NONDMA_TO_DMA);
3431 * ice_set_ctx - set context bits in packed structure
3432 * @src_ctx: pointer to a generic non-packed context structure
3433 * @dest_ctx: pointer to memory for the packed structure
3434 * @ce_info: a description of the structure to be transformed
3437 ice_set_ctx(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)
3441 for (f = 0; ce_info[f].width; f++) {
3442 /* We have to deal with each element of the FW response
3443 * using the correct size so that we are correct regardless
3444 * of the endianness of the machine.
3446 switch (ce_info[f].size_of) {
3448 ice_write_byte(src_ctx, dest_ctx, &ce_info[f]);
3451 ice_write_word(src_ctx, dest_ctx, &ce_info[f]);
3454 ice_write_dword(src_ctx, dest_ctx, &ce_info[f]);
3457 ice_write_qword(src_ctx, dest_ctx, &ce_info[f]);
3460 return ICE_ERR_INVAL_SIZE;
3471 * ice_read_byte - read context byte into struct
3472 * @src_ctx: the context structure to read from
3473 * @dest_ctx: the context to be written to
3474 * @ce_info: a description of the struct to be filled
3477 ice_read_byte(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info)
3483 /* prepare the bits and mask */
3484 shift_width = ce_info->lsb % 8;
3485 mask = (u8)(BIT(ce_info->width) - 1);
3487 /* shift to correct alignment */
3488 mask <<= shift_width;
3490 /* get the current bits from the src bit string */
3491 src = src_ctx + (ce_info->lsb / 8);
3493 ice_memcpy(&dest_byte, src, sizeof(dest_byte), ICE_DMA_TO_NONDMA);
3495 dest_byte &= ~(mask);
3497 dest_byte >>= shift_width;
3499 /* get the address from the struct field */
3500 target = dest_ctx + ce_info->offset;
3502 /* put it back in the struct */
3503 ice_memcpy(target, &dest_byte, sizeof(dest_byte), ICE_NONDMA_TO_DMA);
3507 * ice_read_word - read context word into struct
3508 * @src_ctx: the context structure to read from
3509 * @dest_ctx: the context to be written to
3510 * @ce_info: a description of the struct to be filled
3513 ice_read_word(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info)
3515 u16 dest_word, mask;
3520 /* prepare the bits and mask */
3521 shift_width = ce_info->lsb % 8;
3522 mask = BIT(ce_info->width) - 1;
3524 /* shift to correct alignment */
3525 mask <<= shift_width;
3527 /* get the current bits from the src bit string */
3528 src = src_ctx + (ce_info->lsb / 8);
3530 ice_memcpy(&src_word, src, sizeof(src_word), ICE_DMA_TO_NONDMA);
3532 /* the data in the memory is stored as little endian so mask it
3535 src_word &= ~(CPU_TO_LE16(mask));
3537 /* get the data back into host order before shifting */
3538 dest_word = LE16_TO_CPU(src_word);
3540 dest_word >>= shift_width;
3542 /* get the address from the struct field */
3543 target = dest_ctx + ce_info->offset;
3545 /* put it back in the struct */
3546 ice_memcpy(target, &dest_word, sizeof(dest_word), ICE_NONDMA_TO_DMA);
3550 * ice_read_dword - read context dword into struct
3551 * @src_ctx: the context structure to read from
3552 * @dest_ctx: the context to be written to
3553 * @ce_info: a description of the struct to be filled
3556 ice_read_dword(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info)
3558 u32 dest_dword, mask;
3563 /* prepare the bits and mask */
3564 shift_width = ce_info->lsb % 8;
3566 /* if the field width is exactly 32 on an x86 machine, then the shift
3567 * operation will not work because the SHL instructions count is masked
3568 * to 5 bits so the shift will do nothing
3570 if (ce_info->width < 32)
3571 mask = BIT(ce_info->width) - 1;
3575 /* shift to correct alignment */
3576 mask <<= shift_width;
3578 /* get the current bits from the src bit string */
3579 src = src_ctx + (ce_info->lsb / 8);
3581 ice_memcpy(&src_dword, src, sizeof(src_dword), ICE_DMA_TO_NONDMA);
3583 /* the data in the memory is stored as little endian so mask it
3586 src_dword &= ~(CPU_TO_LE32(mask));
3588 /* get the data back into host order before shifting */
3589 dest_dword = LE32_TO_CPU(src_dword);
3591 dest_dword >>= shift_width;
3593 /* get the address from the struct field */
3594 target = dest_ctx + ce_info->offset;
3596 /* put it back in the struct */
3597 ice_memcpy(target, &dest_dword, sizeof(dest_dword), ICE_NONDMA_TO_DMA);
3601 * ice_read_qword - read context qword into struct
3602 * @src_ctx: the context structure to read from
3603 * @dest_ctx: the context to be written to
3604 * @ce_info: a description of the struct to be filled
3607 ice_read_qword(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info)
3609 u64 dest_qword, mask;
3614 /* prepare the bits and mask */
3615 shift_width = ce_info->lsb % 8;
3617 /* if the field width is exactly 64 on an x86 machine, then the shift
3618 * operation will not work because the SHL instructions count is masked
3619 * to 6 bits so the shift will do nothing
3621 if (ce_info->width < 64)
3622 mask = BIT_ULL(ce_info->width) - 1;
3626 /* shift to correct alignment */
3627 mask <<= shift_width;
3629 /* get the current bits from the src bit string */
3630 src = src_ctx + (ce_info->lsb / 8);
3632 ice_memcpy(&src_qword, src, sizeof(src_qword), ICE_DMA_TO_NONDMA);
3634 /* the data in the memory is stored as little endian so mask it
3637 src_qword &= ~(CPU_TO_LE64(mask));
3639 /* get the data back into host order before shifting */
3640 dest_qword = LE64_TO_CPU(src_qword);
3642 dest_qword >>= shift_width;
3644 /* get the address from the struct field */
3645 target = dest_ctx + ce_info->offset;
3647 /* put it back in the struct */
3648 ice_memcpy(target, &dest_qword, sizeof(dest_qword), ICE_NONDMA_TO_DMA);
3652 * ice_get_ctx - extract context bits from a packed structure
3653 * @src_ctx: pointer to a generic packed context structure
3654 * @dest_ctx: pointer to a generic non-packed context structure
3655 * @ce_info: a description of the structure to be read from
3658 ice_get_ctx(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info)
3662 for (f = 0; ce_info[f].width; f++) {
3663 switch (ce_info[f].size_of) {
3665 ice_read_byte(src_ctx, dest_ctx, &ce_info[f]);
3668 ice_read_word(src_ctx, dest_ctx, &ce_info[f]);
3671 ice_read_dword(src_ctx, dest_ctx, &ce_info[f]);
3674 ice_read_qword(src_ctx, dest_ctx, &ce_info[f]);
3677 /* nothing to do, just keep going */
3686 * ice_get_lan_q_ctx - get the LAN queue context for the given VSI and TC
3687 * @hw: pointer to the HW struct
3688 * @vsi_handle: software VSI handle
3690 * @q_handle: software queue handle
3693 ice_get_lan_q_ctx(struct ice_hw *hw, u16 vsi_handle, u8 tc, u16 q_handle)
3695 struct ice_vsi_ctx *vsi;
3696 struct ice_q_ctx *q_ctx;
3698 vsi = ice_get_vsi_ctx(hw, vsi_handle);
3701 if (q_handle >= vsi->num_lan_q_entries[tc])
3703 if (!vsi->lan_q_ctx[tc])
3705 q_ctx = vsi->lan_q_ctx[tc];
3706 return &q_ctx[q_handle];
3711 * @pi: port information structure
3712 * @vsi_handle: software VSI handle
3714 * @q_handle: software queue handle
3715 * @num_qgrps: Number of added queue groups
3716 * @buf: list of queue groups to be added
3717 * @buf_size: size of buffer for indirect command
3718 * @cd: pointer to command details structure or NULL
3720 * This function adds one LAN queue
3723 ice_ena_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u16 q_handle,
3724 u8 num_qgrps, struct ice_aqc_add_tx_qgrp *buf, u16 buf_size,
3725 struct ice_sq_cd *cd)
3727 struct ice_aqc_txsched_elem_data node = { 0 };
3728 struct ice_sched_node *parent;
3729 struct ice_q_ctx *q_ctx;
3730 enum ice_status status;
3733 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY)
3736 if (num_qgrps > 1 || buf->num_txqs > 1)
3737 return ICE_ERR_MAX_LIMIT;
3741 if (!ice_is_vsi_valid(hw, vsi_handle))
3742 return ICE_ERR_PARAM;
3744 ice_acquire_lock(&pi->sched_lock);
3746 q_ctx = ice_get_lan_q_ctx(hw, vsi_handle, tc, q_handle);
3748 ice_debug(hw, ICE_DBG_SCHED, "Enaq: invalid queue handle %d\n",
3750 status = ICE_ERR_PARAM;
3754 /* find a parent node */
3755 parent = ice_sched_get_free_qparent(pi, vsi_handle, tc,
3756 ICE_SCHED_NODE_OWNER_LAN);
3758 status = ICE_ERR_PARAM;
3762 buf->parent_teid = parent->info.node_teid;
3763 node.parent_teid = parent->info.node_teid;
3764 /* Mark that the values in the "generic" section as valid. The default
3765 * value in the "generic" section is zero. This means that :
3766 * - Scheduling mode is Bytes Per Second (BPS), indicated by Bit 0.
3767 * - 0 priority among siblings, indicated by Bit 1-3.
3768 * - WFQ, indicated by Bit 4.
3769 * - 0 Adjustment value is used in PSM credit update flow, indicated by
3771 * - Bit 7 is reserved.
3772 * Without setting the generic section as valid in valid_sections, the
3773 * Admin queue command will fail with error code ICE_AQ_RC_EINVAL.
3775 buf->txqs[0].info.valid_sections = ICE_AQC_ELEM_VALID_GENERIC;
3777 /* add the LAN queue */
3778 status = ice_aq_add_lan_txq(hw, num_qgrps, buf, buf_size, cd);
3779 if (status != ICE_SUCCESS) {
3780 ice_debug(hw, ICE_DBG_SCHED, "enable queue %d failed %d\n",
3781 LE16_TO_CPU(buf->txqs[0].txq_id),
3782 hw->adminq.sq_last_status);
3786 node.node_teid = buf->txqs[0].q_teid;
3787 node.data.elem_type = ICE_AQC_ELEM_TYPE_LEAF;
3788 q_ctx->q_handle = q_handle;
3789 q_ctx->q_teid = LE32_TO_CPU(node.node_teid);
3791 /* add a leaf node into scheduler tree queue layer */
3792 status = ice_sched_add_node(pi, hw->num_tx_sched_layers - 1, &node);
3794 status = ice_sched_replay_q_bw(pi, q_ctx);
3797 ice_release_lock(&pi->sched_lock);
3803 * @pi: port information structure
3804 * @vsi_handle: software VSI handle
3806 * @num_queues: number of queues
3807 * @q_handles: pointer to software queue handle array
3808 * @q_ids: pointer to the q_id array
3809 * @q_teids: pointer to queue node teids
3810 * @rst_src: if called due to reset, specifies the reset source
3811 * @vmvf_num: the relative VM or VF number that is undergoing the reset
3812 * @cd: pointer to command details structure or NULL
3814 * This function removes queues and their corresponding nodes in SW DB
3817 ice_dis_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u8 num_queues,
3818 u16 *q_handles, u16 *q_ids, u32 *q_teids,
3819 enum ice_disq_rst_src rst_src, u16 vmvf_num,
3820 struct ice_sq_cd *cd)
3822 enum ice_status status = ICE_ERR_DOES_NOT_EXIST;
3823 struct ice_aqc_dis_txq_item qg_list;
3824 struct ice_q_ctx *q_ctx;
3827 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY)
3831 /* if queue is disabled already yet the disable queue command
3832 * has to be sent to complete the VF reset, then call
3833 * ice_aq_dis_lan_txq without any queue information
3836 return ice_aq_dis_lan_txq(pi->hw, 0, NULL, 0, rst_src,
3841 ice_acquire_lock(&pi->sched_lock);
3843 for (i = 0; i < num_queues; i++) {
3844 struct ice_sched_node *node;
3846 node = ice_sched_find_node_by_teid(pi->root, q_teids[i]);
3849 q_ctx = ice_get_lan_q_ctx(pi->hw, vsi_handle, tc, q_handles[i]);
3851 ice_debug(pi->hw, ICE_DBG_SCHED, "invalid queue handle%d\n",
3855 if (q_ctx->q_handle != q_handles[i]) {
3856 ice_debug(pi->hw, ICE_DBG_SCHED, "Err:handles %d %d\n",
3857 q_ctx->q_handle, q_handles[i]);
3860 qg_list.parent_teid = node->info.parent_teid;
3862 qg_list.q_id[0] = CPU_TO_LE16(q_ids[i]);
3863 status = ice_aq_dis_lan_txq(pi->hw, 1, &qg_list,
3864 sizeof(qg_list), rst_src, vmvf_num,
3867 if (status != ICE_SUCCESS)
3869 ice_free_sched_node(pi, node);
3870 q_ctx->q_handle = ICE_INVAL_Q_HANDLE;
3872 ice_release_lock(&pi->sched_lock);
3877 * ice_cfg_vsi_qs - configure the new/existing VSI queues
3878 * @pi: port information structure
3879 * @vsi_handle: software VSI handle
3880 * @tc_bitmap: TC bitmap
3881 * @maxqs: max queues array per TC
3882 * @owner: LAN or RDMA
3884 * This function adds/updates the VSI queues per TC.
3886 static enum ice_status
3887 ice_cfg_vsi_qs(struct ice_port_info *pi, u16 vsi_handle, u8 tc_bitmap,
3888 u16 *maxqs, u8 owner)
3890 enum ice_status status = ICE_SUCCESS;
3893 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY)
3896 if (!ice_is_vsi_valid(pi->hw, vsi_handle))
3897 return ICE_ERR_PARAM;
3899 ice_acquire_lock(&pi->sched_lock);
3901 ice_for_each_traffic_class(i) {
3902 /* configuration is possible only if TC node is present */
3903 if (!ice_sched_get_tc_node(pi, i))
3906 status = ice_sched_cfg_vsi(pi, vsi_handle, i, maxqs[i], owner,
3907 ice_is_tc_ena(tc_bitmap, i));
3912 ice_release_lock(&pi->sched_lock);
3917 * ice_cfg_vsi_lan - configure VSI LAN queues
3918 * @pi: port information structure
3919 * @vsi_handle: software VSI handle
3920 * @tc_bitmap: TC bitmap
3921 * @max_lanqs: max LAN queues array per TC
3923 * This function adds/updates the VSI LAN queues per TC.
3926 ice_cfg_vsi_lan(struct ice_port_info *pi, u16 vsi_handle, u8 tc_bitmap,
3929 return ice_cfg_vsi_qs(pi, vsi_handle, tc_bitmap, max_lanqs,
3930 ICE_SCHED_NODE_OWNER_LAN);
3936 * ice_replay_pre_init - replay pre initialization
3937 * @hw: pointer to the HW struct
3939 * Initializes required config data for VSI, FD, ACL, and RSS before replay.
3941 static enum ice_status ice_replay_pre_init(struct ice_hw *hw)
3943 struct ice_switch_info *sw = hw->switch_info;
3946 /* Delete old entries from replay filter list head if there is any */
3947 ice_rm_all_sw_replay_rule_info(hw);
3948 /* In start of replay, move entries into replay_rules list, it
3949 * will allow adding rules entries back to filt_rules list,
3950 * which is operational list.
3952 for (i = 0; i < ICE_MAX_NUM_RECIPES; i++)
3953 LIST_REPLACE_INIT(&sw->recp_list[i].filt_rules,
3954 &sw->recp_list[i].filt_replay_rules);
3955 ice_sched_replay_agg_vsi_preinit(hw);
3957 return ice_sched_replay_tc_node_bw(hw);
3961 * ice_replay_vsi - replay VSI configuration
3962 * @hw: pointer to the HW struct
3963 * @vsi_handle: driver VSI handle
3965 * Restore all VSI configuration after reset. It is required to call this
3966 * function with main VSI first.
3968 enum ice_status ice_replay_vsi(struct ice_hw *hw, u16 vsi_handle)
3970 enum ice_status status;
3972 if (!ice_is_vsi_valid(hw, vsi_handle))
3973 return ICE_ERR_PARAM;
3975 /* Replay pre-initialization if there is any */
3976 if (vsi_handle == ICE_MAIN_VSI_HANDLE) {
3977 status = ice_replay_pre_init(hw);
3981 /* Replay per VSI all RSS configurations */
3982 status = ice_replay_rss_cfg(hw, vsi_handle);
3985 /* Replay per VSI all filters */
3986 status = ice_replay_vsi_all_fltr(hw, vsi_handle);
3988 status = ice_replay_vsi_agg(hw, vsi_handle);
3993 * ice_replay_post - post replay configuration cleanup
3994 * @hw: pointer to the HW struct
3996 * Post replay cleanup.
3998 void ice_replay_post(struct ice_hw *hw)
4000 /* Delete old entries from replay filter list head */
4001 ice_rm_all_sw_replay_rule_info(hw);
4002 ice_sched_replay_agg(hw);
4006 * ice_stat_update40 - read 40 bit stat from the chip and update stat values
4007 * @hw: ptr to the hardware info
4008 * @reg: offset of 64 bit HW register to read from
4009 * @prev_stat_loaded: bool to specify if previous stats are loaded
4010 * @prev_stat: ptr to previous loaded stat value
4011 * @cur_stat: ptr to current stat value
4014 ice_stat_update40(struct ice_hw *hw, u32 reg, bool prev_stat_loaded,
4015 u64 *prev_stat, u64 *cur_stat)
4017 u64 new_data = rd64(hw, reg) & (BIT_ULL(40) - 1);
4019 /* device stats are not reset at PFR, they likely will not be zeroed
4020 * when the driver starts. Thus, save the value from the first read
4021 * without adding to the statistic value so that we report stats which
4022 * count up from zero.
4024 if (!prev_stat_loaded) {
4025 *prev_stat = new_data;
4029 /* Calculate the difference between the new and old values, and then
4030 * add it to the software stat value.
4032 if (new_data >= *prev_stat)
4033 *cur_stat += new_data - *prev_stat;
4035 /* to manage the potential roll-over */
4036 *cur_stat += (new_data + BIT_ULL(40)) - *prev_stat;
4038 /* Update the previously stored value to prepare for next read */
4039 *prev_stat = new_data;
4043 * ice_stat_update32 - read 32 bit stat from the chip and update stat values
4044 * @hw: ptr to the hardware info
4045 * @reg: offset of HW register to read from
4046 * @prev_stat_loaded: bool to specify if previous stats are loaded
4047 * @prev_stat: ptr to previous loaded stat value
4048 * @cur_stat: ptr to current stat value
4051 ice_stat_update32(struct ice_hw *hw, u32 reg, bool prev_stat_loaded,
4052 u64 *prev_stat, u64 *cur_stat)
4056 new_data = rd32(hw, reg);
4058 /* device stats are not reset at PFR, they likely will not be zeroed
4059 * when the driver starts. Thus, save the value from the first read
4060 * without adding to the statistic value so that we report stats which
4061 * count up from zero.
4063 if (!prev_stat_loaded) {
4064 *prev_stat = new_data;
4068 /* Calculate the difference between the new and old values, and then
4069 * add it to the software stat value.
4071 if (new_data >= *prev_stat)
4072 *cur_stat += new_data - *prev_stat;
4074 /* to manage the potential roll-over */
4075 *cur_stat += (new_data + BIT_ULL(32)) - *prev_stat;
4077 /* Update the previously stored value to prepare for next read */
4078 *prev_stat = new_data;
4083 * ice_sched_query_elem - query element information from HW
4084 * @hw: pointer to the HW struct
4085 * @node_teid: node TEID to be queried
4086 * @buf: buffer to element information
4088 * This function queries HW element information
4091 ice_sched_query_elem(struct ice_hw *hw, u32 node_teid,
4092 struct ice_aqc_get_elem *buf)
4094 u16 buf_size, num_elem_ret = 0;
4095 enum ice_status status;
4097 buf_size = sizeof(*buf);
4098 ice_memset(buf, 0, buf_size, ICE_NONDMA_MEM);
4099 buf->generic[0].node_teid = CPU_TO_LE32(node_teid);
4100 status = ice_aq_query_sched_elems(hw, 1, buf, buf_size, &num_elem_ret,
4102 if (status != ICE_SUCCESS || num_elem_ret != 1)
4103 ice_debug(hw, ICE_DBG_SCHED, "query element failed\n");
4108 * ice_is_fw_in_rec_mode
4109 * @hw: pointer to the HW struct
4111 * This function returns true if fw is in recovery mode
4113 bool ice_is_fw_in_rec_mode(struct ice_hw *hw)
4117 /* check the current FW mode */
4118 reg = rd32(hw, GL_MNG_FWSM);
4119 return (reg & GL_MNG_FWSM_FW_MODES_M) > ICE_FW_MODE_DBG;