1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2001-2019
5 #include "ice_common.h"
7 #include "ice_adminq_cmd.h"
10 #include "ice_switch.h"
12 #define ICE_PF_RESET_WAIT_COUNT 200
14 #define ICE_PROG_FLEX_ENTRY(hw, rxdid, mdid, idx) \
15 wr32((hw), GLFLXP_RXDID_FLX_WRD_##idx(rxdid), \
16 ((ICE_RX_OPC_MDID << \
17 GLFLXP_RXDID_FLX_WRD_##idx##_RXDID_OPCODE_S) & \
18 GLFLXP_RXDID_FLX_WRD_##idx##_RXDID_OPCODE_M) | \
19 (((mdid) << GLFLXP_RXDID_FLX_WRD_##idx##_PROT_MDID_S) & \
20 GLFLXP_RXDID_FLX_WRD_##idx##_PROT_MDID_M))
22 #define ICE_PROG_FLEX_ENTRY_EXTRACT(hw, rxdid, protid, off, idx) \
23 wr32((hw), GLFLXP_RXDID_FLX_WRD_##idx(rxdid), \
24 ((ICE_RX_OPC_EXTRACT << \
25 GLFLXP_RXDID_FLX_WRD_##idx##_RXDID_OPCODE_S) & \
26 GLFLXP_RXDID_FLX_WRD_##idx##_RXDID_OPCODE_M) | \
27 (((protid) << GLFLXP_RXDID_FLX_WRD_##idx##_PROT_MDID_S) & \
28 GLFLXP_RXDID_FLX_WRD_##idx##_PROT_MDID_M) | \
29 (((off) << GLFLXP_RXDID_FLX_WRD_##idx##_EXTRACTION_OFFSET_S) & \
30 GLFLXP_RXDID_FLX_WRD_##idx##_EXTRACTION_OFFSET_M))
32 #define ICE_PROG_FLG_ENTRY(hw, rxdid, flg_0, flg_1, flg_2, flg_3, idx) \
33 wr32((hw), GLFLXP_RXDID_FLAGS(rxdid, idx), \
34 (((flg_0) << GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_S) & \
35 GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_M) | \
36 (((flg_1) << GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_1_S) & \
37 GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_1_M) | \
38 (((flg_2) << GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_2_S) & \
39 GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_2_M) | \
40 (((flg_3) << GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_3_S) & \
41 GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_3_M))
45 * ice_set_mac_type - Sets MAC type
46 * @hw: pointer to the HW structure
48 * This function sets the MAC type of the adapter based on the
49 * vendor ID and device ID stored in the HW structure.
51 static enum ice_status ice_set_mac_type(struct ice_hw *hw)
53 enum ice_status status = ICE_SUCCESS;
55 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
57 if (hw->vendor_id == ICE_INTEL_VENDOR_ID) {
58 switch (hw->device_id) {
60 hw->mac_type = ICE_MAC_GENERIC;
64 status = ICE_ERR_DEVICE_NOT_SUPPORTED;
67 ice_debug(hw, ICE_DBG_INIT, "found mac_type: %d, status: %d\n",
68 hw->mac_type, status);
75 * ice_clear_pf_cfg - Clear PF configuration
76 * @hw: pointer to the hardware structure
78 * Clears any existing PF configuration (VSIs, VSI lists, switch rules, port
79 * configuration, flow director filters, etc.).
81 enum ice_status ice_clear_pf_cfg(struct ice_hw *hw)
83 struct ice_aq_desc desc;
85 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pf_cfg);
87 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
91 * ice_aq_manage_mac_read - manage MAC address read command
92 * @hw: pointer to the HW struct
93 * @buf: a virtual buffer to hold the manage MAC read response
94 * @buf_size: Size of the virtual buffer
95 * @cd: pointer to command details structure or NULL
97 * This function is used to return per PF station MAC address (0x0107).
98 * NOTE: Upon successful completion of this command, MAC address information
99 * is returned in user specified buffer. Please interpret user specified
100 * buffer as "manage_mac_read" response.
101 * Response such as various MAC addresses are stored in HW struct (port.mac)
102 * ice_aq_discover_caps is expected to be called before this function is called.
104 static enum ice_status
105 ice_aq_manage_mac_read(struct ice_hw *hw, void *buf, u16 buf_size,
106 struct ice_sq_cd *cd)
108 struct ice_aqc_manage_mac_read_resp *resp;
109 struct ice_aqc_manage_mac_read *cmd;
110 struct ice_aq_desc desc;
111 enum ice_status status;
115 cmd = &desc.params.mac_read;
117 if (buf_size < sizeof(*resp))
118 return ICE_ERR_BUF_TOO_SHORT;
120 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_read);
122 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);
126 resp = (struct ice_aqc_manage_mac_read_resp *)buf;
127 flags = LE16_TO_CPU(cmd->flags) & ICE_AQC_MAN_MAC_READ_M;
129 if (!(flags & ICE_AQC_MAN_MAC_LAN_ADDR_VALID)) {
130 ice_debug(hw, ICE_DBG_LAN, "got invalid MAC address\n");
134 /* A single port can report up to two (LAN and WoL) addresses */
135 for (i = 0; i < cmd->num_addr; i++)
136 if (resp[i].addr_type == ICE_AQC_MAN_MAC_ADDR_TYPE_LAN) {
137 ice_memcpy(hw->port_info->mac.lan_addr,
138 resp[i].mac_addr, ETH_ALEN,
140 ice_memcpy(hw->port_info->mac.perm_addr,
142 ETH_ALEN, ICE_DMA_TO_NONDMA);
150 * ice_aq_get_phy_caps - returns PHY capabilities
151 * @pi: port information structure
152 * @qual_mods: report qualified modules
153 * @report_mode: report mode capabilities
154 * @pcaps: structure for PHY capabilities to be filled
155 * @cd: pointer to command details structure or NULL
157 * Returns the various PHY capabilities supported on the Port (0x0600)
160 ice_aq_get_phy_caps(struct ice_port_info *pi, bool qual_mods, u8 report_mode,
161 struct ice_aqc_get_phy_caps_data *pcaps,
162 struct ice_sq_cd *cd)
164 struct ice_aqc_get_phy_caps *cmd;
165 u16 pcaps_size = sizeof(*pcaps);
166 struct ice_aq_desc desc;
167 enum ice_status status;
169 cmd = &desc.params.get_phy;
171 if (!pcaps || (report_mode & ~ICE_AQC_REPORT_MODE_M) || !pi)
172 return ICE_ERR_PARAM;
174 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_phy_caps);
177 cmd->param0 |= CPU_TO_LE16(ICE_AQC_GET_PHY_RQM);
179 cmd->param0 |= CPU_TO_LE16(report_mode);
180 status = ice_aq_send_cmd(pi->hw, &desc, pcaps, pcaps_size, cd);
182 if (status == ICE_SUCCESS && report_mode == ICE_AQC_REPORT_TOPO_CAP) {
183 pi->phy.phy_type_low = LE64_TO_CPU(pcaps->phy_type_low);
184 pi->phy.phy_type_high = LE64_TO_CPU(pcaps->phy_type_high);
191 * ice_get_media_type - Gets media type
192 * @pi: port information structure
194 static enum ice_media_type ice_get_media_type(struct ice_port_info *pi)
196 struct ice_link_status *hw_link_info;
199 return ICE_MEDIA_UNKNOWN;
201 hw_link_info = &pi->phy.link_info;
202 if (hw_link_info->phy_type_low && hw_link_info->phy_type_high)
203 /* If more than one media type is selected, report unknown */
204 return ICE_MEDIA_UNKNOWN;
206 if (hw_link_info->phy_type_low) {
207 switch (hw_link_info->phy_type_low) {
208 case ICE_PHY_TYPE_LOW_1000BASE_SX:
209 case ICE_PHY_TYPE_LOW_1000BASE_LX:
210 case ICE_PHY_TYPE_LOW_10GBASE_SR:
211 case ICE_PHY_TYPE_LOW_10GBASE_LR:
212 case ICE_PHY_TYPE_LOW_10G_SFI_C2C:
213 case ICE_PHY_TYPE_LOW_25GBASE_SR:
214 case ICE_PHY_TYPE_LOW_25GBASE_LR:
215 case ICE_PHY_TYPE_LOW_25G_AUI_C2C:
216 case ICE_PHY_TYPE_LOW_40GBASE_SR4:
217 case ICE_PHY_TYPE_LOW_40GBASE_LR4:
218 case ICE_PHY_TYPE_LOW_50GBASE_SR2:
219 case ICE_PHY_TYPE_LOW_50GBASE_LR2:
220 case ICE_PHY_TYPE_LOW_50GBASE_SR:
221 case ICE_PHY_TYPE_LOW_50GBASE_FR:
222 case ICE_PHY_TYPE_LOW_50GBASE_LR:
223 case ICE_PHY_TYPE_LOW_100GBASE_SR4:
224 case ICE_PHY_TYPE_LOW_100GBASE_LR4:
225 case ICE_PHY_TYPE_LOW_100GBASE_SR2:
226 case ICE_PHY_TYPE_LOW_100GBASE_DR:
227 return ICE_MEDIA_FIBER;
228 case ICE_PHY_TYPE_LOW_100BASE_TX:
229 case ICE_PHY_TYPE_LOW_1000BASE_T:
230 case ICE_PHY_TYPE_LOW_2500BASE_T:
231 case ICE_PHY_TYPE_LOW_5GBASE_T:
232 case ICE_PHY_TYPE_LOW_10GBASE_T:
233 case ICE_PHY_TYPE_LOW_25GBASE_T:
234 return ICE_MEDIA_BASET;
235 case ICE_PHY_TYPE_LOW_10G_SFI_DA:
236 case ICE_PHY_TYPE_LOW_25GBASE_CR:
237 case ICE_PHY_TYPE_LOW_25GBASE_CR_S:
238 case ICE_PHY_TYPE_LOW_25GBASE_CR1:
239 case ICE_PHY_TYPE_LOW_40GBASE_CR4:
240 case ICE_PHY_TYPE_LOW_50GBASE_CR2:
241 case ICE_PHY_TYPE_LOW_50GBASE_CP:
242 case ICE_PHY_TYPE_LOW_100GBASE_CR4:
243 case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4:
244 case ICE_PHY_TYPE_LOW_100GBASE_CP2:
246 case ICE_PHY_TYPE_LOW_1000BASE_KX:
247 case ICE_PHY_TYPE_LOW_2500BASE_KX:
248 case ICE_PHY_TYPE_LOW_2500BASE_X:
249 case ICE_PHY_TYPE_LOW_5GBASE_KR:
250 case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1:
251 case ICE_PHY_TYPE_LOW_25GBASE_KR:
252 case ICE_PHY_TYPE_LOW_25GBASE_KR1:
253 case ICE_PHY_TYPE_LOW_25GBASE_KR_S:
254 case ICE_PHY_TYPE_LOW_40GBASE_KR4:
255 case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4:
256 case ICE_PHY_TYPE_LOW_50GBASE_KR2:
257 case ICE_PHY_TYPE_LOW_100GBASE_KR4:
258 case ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4:
259 return ICE_MEDIA_BACKPLANE;
262 switch (hw_link_info->phy_type_high) {
263 case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4:
264 return ICE_MEDIA_BACKPLANE;
267 return ICE_MEDIA_UNKNOWN;
271 * ice_aq_get_link_info
272 * @pi: port information structure
273 * @ena_lse: enable/disable LinkStatusEvent reporting
274 * @link: pointer to link status structure - optional
275 * @cd: pointer to command details structure or NULL
277 * Get Link Status (0x607). Returns the link status of the adapter.
280 ice_aq_get_link_info(struct ice_port_info *pi, bool ena_lse,
281 struct ice_link_status *link, struct ice_sq_cd *cd)
283 struct ice_aqc_get_link_status_data link_data = { 0 };
284 struct ice_aqc_get_link_status *resp;
285 struct ice_link_status *li_old, *li;
286 enum ice_media_type *hw_media_type;
287 struct ice_fc_info *hw_fc_info;
288 bool tx_pause, rx_pause;
289 struct ice_aq_desc desc;
290 enum ice_status status;
295 return ICE_ERR_PARAM;
297 li_old = &pi->phy.link_info_old;
298 hw_media_type = &pi->phy.media_type;
299 li = &pi->phy.link_info;
300 hw_fc_info = &pi->fc;
302 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_status);
303 cmd_flags = (ena_lse) ? ICE_AQ_LSE_ENA : ICE_AQ_LSE_DIS;
304 resp = &desc.params.get_link_status;
305 resp->cmd_flags = CPU_TO_LE16(cmd_flags);
306 resp->lport_num = pi->lport;
308 status = ice_aq_send_cmd(hw, &desc, &link_data, sizeof(link_data), cd);
310 if (status != ICE_SUCCESS)
313 /* save off old link status information */
316 /* update current link status information */
317 li->link_speed = LE16_TO_CPU(link_data.link_speed);
318 li->phy_type_low = LE64_TO_CPU(link_data.phy_type_low);
319 li->phy_type_high = LE64_TO_CPU(link_data.phy_type_high);
320 *hw_media_type = ice_get_media_type(pi);
321 li->link_info = link_data.link_info;
322 li->an_info = link_data.an_info;
323 li->ext_info = link_data.ext_info;
324 li->max_frame_size = LE16_TO_CPU(link_data.max_frame_size);
325 li->fec_info = link_data.cfg & ICE_AQ_FEC_MASK;
326 li->topo_media_conflict = link_data.topo_media_conflict;
327 li->pacing = link_data.cfg & (ICE_AQ_CFG_PACING_M |
328 ICE_AQ_CFG_PACING_TYPE_M);
331 tx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_TX);
332 rx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_RX);
333 if (tx_pause && rx_pause)
334 hw_fc_info->current_mode = ICE_FC_FULL;
336 hw_fc_info->current_mode = ICE_FC_TX_PAUSE;
338 hw_fc_info->current_mode = ICE_FC_RX_PAUSE;
340 hw_fc_info->current_mode = ICE_FC_NONE;
342 li->lse_ena = !!(resp->cmd_flags & CPU_TO_LE16(ICE_AQ_LSE_IS_ENABLED));
344 ice_debug(hw, ICE_DBG_LINK, "link_speed = 0x%x\n", li->link_speed);
345 ice_debug(hw, ICE_DBG_LINK, "phy_type_low = 0x%llx\n",
346 (unsigned long long)li->phy_type_low);
347 ice_debug(hw, ICE_DBG_LINK, "phy_type_high = 0x%llx\n",
348 (unsigned long long)li->phy_type_high);
349 ice_debug(hw, ICE_DBG_LINK, "media_type = 0x%x\n", *hw_media_type);
350 ice_debug(hw, ICE_DBG_LINK, "link_info = 0x%x\n", li->link_info);
351 ice_debug(hw, ICE_DBG_LINK, "an_info = 0x%x\n", li->an_info);
352 ice_debug(hw, ICE_DBG_LINK, "ext_info = 0x%x\n", li->ext_info);
353 ice_debug(hw, ICE_DBG_LINK, "lse_ena = 0x%x\n", li->lse_ena);
354 ice_debug(hw, ICE_DBG_LINK, "max_frame = 0x%x\n", li->max_frame_size);
355 ice_debug(hw, ICE_DBG_LINK, "pacing = 0x%x\n", li->pacing);
357 /* save link status information */
361 /* flag cleared so calling functions don't call AQ again */
362 pi->phy.get_link_info = false;
368 * ice_init_flex_flags
369 * @hw: pointer to the hardware structure
370 * @prof_id: Rx Descriptor Builder profile ID
372 * Function to initialize Rx flex flags
374 static void ice_init_flex_flags(struct ice_hw *hw, enum ice_rxdid prof_id)
378 /* Flex-flag fields (0-2) are programmed with FLG64 bits with layout:
379 * flexiflags0[5:0] - TCP flags, is_packet_fragmented, is_packet_UDP_GRE
380 * flexiflags1[3:0] - Not used for flag programming
381 * flexiflags2[7:0] - Tunnel and VLAN types
382 * 2 invalid fields in last index
385 /* Rx flex flags are currently programmed for the NIC profiles only.
386 * Different flag bit programming configurations can be added per
389 case ICE_RXDID_FLEX_NIC:
390 case ICE_RXDID_FLEX_NIC_2:
391 ICE_PROG_FLG_ENTRY(hw, prof_id, ICE_FLG_PKT_FRG,
392 ICE_FLG_UDP_GRE, ICE_FLG_PKT_DSI,
394 /* flex flag 1 is not used for flexi-flag programming, skipping
395 * these four FLG64 bits.
397 ICE_PROG_FLG_ENTRY(hw, prof_id, ICE_FLG_SYN, ICE_FLG_RST,
398 ICE_FLG_PKT_DSI, ICE_FLG_PKT_DSI, idx++);
399 ICE_PROG_FLG_ENTRY(hw, prof_id, ICE_FLG_PKT_DSI,
400 ICE_FLG_PKT_DSI, ICE_FLG_EVLAN_x8100,
401 ICE_FLG_EVLAN_x9100, idx++);
402 ICE_PROG_FLG_ENTRY(hw, prof_id, ICE_FLG_VLAN_x8100,
403 ICE_FLG_TNL_VLAN, ICE_FLG_TNL_MAC,
404 ICE_FLG_TNL0, idx++);
405 ICE_PROG_FLG_ENTRY(hw, prof_id, ICE_FLG_TNL1, ICE_FLG_TNL2,
406 ICE_FLG_PKT_DSI, ICE_FLG_PKT_DSI, idx);
410 ice_debug(hw, ICE_DBG_INIT,
411 "Flag programming for profile ID %d not supported\n",
418 * @hw: pointer to the hardware structure
419 * @prof_id: Rx Descriptor Builder profile ID
421 * Function to initialize flex descriptors
423 static void ice_init_flex_flds(struct ice_hw *hw, enum ice_rxdid prof_id)
425 enum ice_prot_id protid_0, protid_1;
426 u16 offset_0, offset_1;
427 enum ice_flex_mdid mdid;
430 case ICE_RXDID_FLEX_NIC:
431 case ICE_RXDID_FLEX_NIC_2:
432 ICE_PROG_FLEX_ENTRY(hw, prof_id, ICE_MDID_RX_HASH_LOW, 0);
433 ICE_PROG_FLEX_ENTRY(hw, prof_id, ICE_MDID_RX_HASH_HIGH, 1);
434 ICE_PROG_FLEX_ENTRY(hw, prof_id, ICE_MDID_FLOW_ID_LOWER, 2);
436 mdid = (prof_id == ICE_RXDID_FLEX_NIC_2) ?
437 ICE_MDID_SRC_VSI : ICE_MDID_FLOW_ID_HIGH;
439 ICE_PROG_FLEX_ENTRY(hw, prof_id, mdid, 3);
441 ice_init_flex_flags(hw, prof_id);
443 case ICE_RXDID_COMMS_GENERIC:
444 case ICE_RXDID_COMMS_AUX_VLAN:
445 case ICE_RXDID_COMMS_AUX_IPV4:
446 case ICE_RXDID_COMMS_AUX_IPV6:
447 case ICE_RXDID_COMMS_AUX_IPV6_FLOW:
448 case ICE_RXDID_COMMS_AUX_TCP:
449 ICE_PROG_FLEX_ENTRY(hw, prof_id, ICE_MDID_RX_HASH_LOW, 0);
450 ICE_PROG_FLEX_ENTRY(hw, prof_id, ICE_MDID_RX_HASH_HIGH, 1);
451 ICE_PROG_FLEX_ENTRY(hw, prof_id, ICE_MDID_FLOW_ID_LOWER, 2);
452 ICE_PROG_FLEX_ENTRY(hw, prof_id, ICE_MDID_FLOW_ID_HIGH, 3);
454 if (prof_id == ICE_RXDID_COMMS_AUX_VLAN) {
455 /* FlexiMD.4: VLAN1 - single or EVLAN (first for QinQ).
456 * FlexiMD.5: VLAN2 - C-VLAN (second for QinQ).
458 protid_0 = ICE_PROT_EVLAN_O;
460 protid_1 = ICE_PROT_VLAN_O;
462 } else if (prof_id == ICE_RXDID_COMMS_AUX_IPV4) {
463 /* FlexiMD.4: IPHDR1 - IPv4 header word 4, "TTL" and
465 * FlexiMD.5: IPHDR0 - IPv4 header word 0, "Ver",
466 * "Hdr Len" and "Type of Service" fields.
468 protid_0 = ICE_PROT_IPV4_OF_OR_S;
470 protid_1 = ICE_PROT_IPV4_OF_OR_S;
472 } else if (prof_id == ICE_RXDID_COMMS_AUX_IPV6) {
473 /* FlexiMD.4: IPHDR1 - IPv6 header word 3,
474 * "Next Header" and "Hop Limit" fields.
475 * FlexiMD.5: IPHDR0 - IPv6 header word 0,
476 * "Ver", "Traffic class" and high 4 bits of
477 * "Flow Label" fields.
479 protid_0 = ICE_PROT_IPV6_OF_OR_S;
481 protid_1 = ICE_PROT_IPV6_OF_OR_S;
483 } else if (prof_id == ICE_RXDID_COMMS_AUX_IPV6_FLOW) {
484 /* FlexiMD.4: IPHDR1 - IPv6 header word 1,
485 * 16 low bits of the "Flow Label" field.
486 * FlexiMD.5: IPHDR0 - IPv6 header word 0,
487 * "Ver", "Traffic class" and high 4 bits
488 * of "Flow Label" fields.
490 protid_0 = ICE_PROT_IPV6_OF_OR_S;
492 protid_1 = ICE_PROT_IPV6_OF_OR_S;
494 } else if (prof_id == ICE_RXDID_COMMS_AUX_TCP) {
495 /* FlexiMD.4: TCPHDR - TCP header word 6,
496 * "Data Offset" and "Flags" fields.
497 * FlexiMD.5: Reserved
499 protid_0 = ICE_PROT_TCP_IL;
501 protid_1 = ICE_PROT_ID_INVAL;
504 protid_0 = ICE_PROT_ID_INVAL;
506 protid_1 = ICE_PROT_ID_INVAL;
510 ICE_PROG_FLEX_ENTRY_EXTRACT(hw, prof_id,
511 protid_0, offset_0, 4);
512 ICE_PROG_FLEX_ENTRY_EXTRACT(hw, prof_id,
513 protid_1, offset_1, 5);
515 ice_init_flex_flags(hw, prof_id);
518 ice_debug(hw, ICE_DBG_INIT,
519 "Field init for profile ID %d not supported\n",
526 * @hw: pointer to the HW struct
527 * @max_frame_size: Maximum Frame Size to be supported
528 * @cd: pointer to command details structure or NULL
530 * Set MAC configuration (0x0603)
533 ice_aq_set_mac_cfg(struct ice_hw *hw, u16 max_frame_size, struct ice_sq_cd *cd)
535 u16 fc_threshold_val, tx_timer_val;
536 struct ice_aqc_set_mac_cfg *cmd;
537 struct ice_aq_desc desc;
540 cmd = &desc.params.set_mac_cfg;
542 if (max_frame_size == 0)
543 return ICE_ERR_PARAM;
545 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_mac_cfg);
547 cmd->max_frame_size = CPU_TO_LE16(max_frame_size);
549 /* We read back the transmit timer and fc threshold value of
550 * LFC. Thus, we will use index =
551 * PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX.
553 * Also, because we are opearating on transmit timer and fc
554 * threshold of LFC, we don't turn on any bit in tx_tmr_priority
556 #define IDX_OF_LFC PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX
558 /* Retrieve the transmit timer */
560 PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(IDX_OF_LFC));
561 tx_timer_val = reg_val &
562 PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_HSEC_CTL_TX_PAUSE_QUANTA_M;
563 cmd->tx_tmr_value = CPU_TO_LE16(tx_timer_val);
565 /* Retrieve the fc threshold */
567 PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(IDX_OF_LFC));
568 fc_threshold_val = reg_val & MAKEMASK(0xFFFF, 0);
569 cmd->fc_refresh_threshold = CPU_TO_LE16(fc_threshold_val);
571 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
575 * ice_init_fltr_mgmt_struct - initializes filter management list and locks
576 * @hw: pointer to the HW struct
578 static enum ice_status ice_init_fltr_mgmt_struct(struct ice_hw *hw)
580 struct ice_switch_info *sw;
582 hw->switch_info = (struct ice_switch_info *)
583 ice_malloc(hw, sizeof(*hw->switch_info));
584 sw = hw->switch_info;
587 return ICE_ERR_NO_MEMORY;
589 INIT_LIST_HEAD(&sw->vsi_list_map_head);
591 return ice_init_def_sw_recp(hw);
595 * ice_cleanup_fltr_mgmt_struct - cleanup filter management list and locks
596 * @hw: pointer to the HW struct
598 static void ice_cleanup_fltr_mgmt_struct(struct ice_hw *hw)
600 struct ice_switch_info *sw = hw->switch_info;
601 struct ice_vsi_list_map_info *v_pos_map;
602 struct ice_vsi_list_map_info *v_tmp_map;
603 struct ice_sw_recipe *recps;
606 LIST_FOR_EACH_ENTRY_SAFE(v_pos_map, v_tmp_map, &sw->vsi_list_map_head,
607 ice_vsi_list_map_info, list_entry) {
608 LIST_DEL(&v_pos_map->list_entry);
609 ice_free(hw, v_pos_map);
611 recps = hw->switch_info->recp_list;
612 for (i = 0; i < ICE_MAX_NUM_RECIPES; i++) {
613 struct ice_recp_grp_entry *rg_entry, *tmprg_entry;
615 recps[i].root_rid = i;
616 LIST_FOR_EACH_ENTRY_SAFE(rg_entry, tmprg_entry,
617 &recps[i].rg_list, ice_recp_grp_entry,
619 LIST_DEL(&rg_entry->l_entry);
620 ice_free(hw, rg_entry);
623 if (recps[i].adv_rule) {
624 struct ice_adv_fltr_mgmt_list_entry *tmp_entry;
625 struct ice_adv_fltr_mgmt_list_entry *lst_itr;
627 ice_destroy_lock(&recps[i].filt_rule_lock);
628 LIST_FOR_EACH_ENTRY_SAFE(lst_itr, tmp_entry,
629 &recps[i].filt_rules,
630 ice_adv_fltr_mgmt_list_entry,
632 LIST_DEL(&lst_itr->list_entry);
633 ice_free(hw, lst_itr->lkups);
634 ice_free(hw, lst_itr);
637 struct ice_fltr_mgmt_list_entry *lst_itr, *tmp_entry;
639 ice_destroy_lock(&recps[i].filt_rule_lock);
640 LIST_FOR_EACH_ENTRY_SAFE(lst_itr, tmp_entry,
641 &recps[i].filt_rules,
642 ice_fltr_mgmt_list_entry,
644 LIST_DEL(&lst_itr->list_entry);
645 ice_free(hw, lst_itr);
648 if (recps[i].root_buf)
649 ice_free(hw, recps[i].root_buf);
651 ice_rm_all_sw_replay_rule_info(hw);
652 ice_free(hw, sw->recp_list);
656 #define ICE_FW_LOG_DESC_SIZE(n) (sizeof(struct ice_aqc_fw_logging_data) + \
657 (((n) - 1) * sizeof(((struct ice_aqc_fw_logging_data *)0)->entry)))
658 #define ICE_FW_LOG_DESC_SIZE_MAX \
659 ICE_FW_LOG_DESC_SIZE(ICE_AQC_FW_LOG_ID_MAX)
662 * ice_get_fw_log_cfg - get FW logging configuration
663 * @hw: pointer to the HW struct
665 static enum ice_status ice_get_fw_log_cfg(struct ice_hw *hw)
667 struct ice_aqc_fw_logging_data *config;
668 struct ice_aq_desc desc;
669 enum ice_status status;
672 size = ICE_FW_LOG_DESC_SIZE_MAX;
673 config = (struct ice_aqc_fw_logging_data *)ice_malloc(hw, size);
675 return ICE_ERR_NO_MEMORY;
677 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_fw_logging_info);
679 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_BUF);
680 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
682 status = ice_aq_send_cmd(hw, &desc, config, size, NULL);
686 /* Save fw logging information into the HW structure */
687 for (i = 0; i < ICE_AQC_FW_LOG_ID_MAX; i++) {
690 v = LE16_TO_CPU(config->entry[i]);
691 m = (v & ICE_AQC_FW_LOG_ID_M) >> ICE_AQC_FW_LOG_ID_S;
692 flgs = (v & ICE_AQC_FW_LOG_EN_M) >> ICE_AQC_FW_LOG_EN_S;
694 if (m < ICE_AQC_FW_LOG_ID_MAX)
695 hw->fw_log.evnts[m].cur = flgs;
699 ice_free(hw, config);
705 * ice_cfg_fw_log - configure FW logging
706 * @hw: pointer to the HW struct
707 * @enable: enable certain FW logging events if true, disable all if false
709 * This function enables/disables the FW logging via Rx CQ events and a UART
710 * port based on predetermined configurations. FW logging via the Rx CQ can be
711 * enabled/disabled for individual PF's. However, FW logging via the UART can
712 * only be enabled/disabled for all PFs on the same device.
714 * To enable overall FW logging, the "cq_en" and "uart_en" enable bits in
715 * hw->fw_log need to be set accordingly, e.g. based on user-provided input,
716 * before initializing the device.
718 * When re/configuring FW logging, callers need to update the "cfg" elements of
719 * the hw->fw_log.evnts array with the desired logging event configurations for
720 * modules of interest. When disabling FW logging completely, the callers can
721 * just pass false in the "enable" parameter. On completion, the function will
722 * update the "cur" element of the hw->fw_log.evnts array with the resulting
723 * logging event configurations of the modules that are being re/configured. FW
724 * logging modules that are not part of a reconfiguration operation retain their
727 * Before resetting the device, it is recommended that the driver disables FW
728 * logging before shutting down the control queue. When disabling FW logging
729 * ("enable" = false), the latest configurations of FW logging events stored in
730 * hw->fw_log.evnts[] are not overridden to allow them to be reconfigured after
733 * When enabling FW logging to emit log messages via the Rx CQ during the
734 * device's initialization phase, a mechanism alternative to interrupt handlers
735 * needs to be used to extract FW log messages from the Rx CQ periodically and
736 * to prevent the Rx CQ from being full and stalling other types of control
737 * messages from FW to SW. Interrupts are typically disabled during the device's
738 * initialization phase.
740 static enum ice_status ice_cfg_fw_log(struct ice_hw *hw, bool enable)
742 struct ice_aqc_fw_logging_data *data = NULL;
743 struct ice_aqc_fw_logging *cmd;
744 enum ice_status status = ICE_SUCCESS;
745 u16 i, chgs = 0, len = 0;
746 struct ice_aq_desc desc;
750 if (!hw->fw_log.cq_en && !hw->fw_log.uart_en)
753 /* Disable FW logging only when the control queue is still responsive */
755 (!hw->fw_log.actv_evnts || !ice_check_sq_alive(hw, &hw->adminq)))
758 /* Get current FW log settings */
759 status = ice_get_fw_log_cfg(hw);
763 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_fw_logging);
764 cmd = &desc.params.fw_logging;
766 /* Indicate which controls are valid */
767 if (hw->fw_log.cq_en)
768 cmd->log_ctrl_valid |= ICE_AQC_FW_LOG_AQ_VALID;
770 if (hw->fw_log.uart_en)
771 cmd->log_ctrl_valid |= ICE_AQC_FW_LOG_UART_VALID;
774 /* Fill in an array of entries with FW logging modules and
775 * logging events being reconfigured.
777 for (i = 0; i < ICE_AQC_FW_LOG_ID_MAX; i++) {
780 /* Keep track of enabled event types */
781 actv_evnts |= hw->fw_log.evnts[i].cfg;
783 if (hw->fw_log.evnts[i].cfg == hw->fw_log.evnts[i].cur)
787 data = (struct ice_aqc_fw_logging_data *)
789 ICE_FW_LOG_DESC_SIZE_MAX);
791 return ICE_ERR_NO_MEMORY;
794 val = i << ICE_AQC_FW_LOG_ID_S;
795 val |= hw->fw_log.evnts[i].cfg << ICE_AQC_FW_LOG_EN_S;
796 data->entry[chgs++] = CPU_TO_LE16(val);
799 /* Only enable FW logging if at least one module is specified.
800 * If FW logging is currently enabled but all modules are not
801 * enabled to emit log messages, disable FW logging altogether.
804 /* Leave if there is effectively no change */
808 if (hw->fw_log.cq_en)
809 cmd->log_ctrl |= ICE_AQC_FW_LOG_AQ_EN;
811 if (hw->fw_log.uart_en)
812 cmd->log_ctrl |= ICE_AQC_FW_LOG_UART_EN;
815 len = ICE_FW_LOG_DESC_SIZE(chgs);
816 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
820 status = ice_aq_send_cmd(hw, &desc, buf, len, NULL);
822 /* Update the current configuration to reflect events enabled.
823 * hw->fw_log.cq_en and hw->fw_log.uart_en indicate if the FW
824 * logging mode is enabled for the device. They do not reflect
825 * actual modules being enabled to emit log messages. So, their
826 * values remain unchanged even when all modules are disabled.
828 u16 cnt = enable ? chgs : (u16)ICE_AQC_FW_LOG_ID_MAX;
830 hw->fw_log.actv_evnts = actv_evnts;
831 for (i = 0; i < cnt; i++) {
835 /* When disabling all FW logging events as part
836 * of device's de-initialization, the original
837 * configurations are retained, and can be used
838 * to reconfigure FW logging later if the device
841 hw->fw_log.evnts[i].cur = 0;
845 v = LE16_TO_CPU(data->entry[i]);
846 m = (v & ICE_AQC_FW_LOG_ID_M) >> ICE_AQC_FW_LOG_ID_S;
847 hw->fw_log.evnts[m].cur = hw->fw_log.evnts[m].cfg;
860 * @hw: pointer to the HW struct
861 * @desc: pointer to the AQ message descriptor
862 * @buf: pointer to the buffer accompanying the AQ message
864 * Formats a FW Log message and outputs it via the standard driver logs.
866 void ice_output_fw_log(struct ice_hw *hw, struct ice_aq_desc *desc, void *buf)
868 ice_debug(hw, ICE_DBG_FW_LOG, "[ FW Log Msg Start ]\n");
869 ice_debug_array(hw, ICE_DBG_FW_LOG, 16, 1, (u8 *)buf,
870 LE16_TO_CPU(desc->datalen));
871 ice_debug(hw, ICE_DBG_FW_LOG, "[ FW Log Msg End ]\n");
875 * ice_get_itr_intrl_gran - determine int/intrl granularity
876 * @hw: pointer to the HW struct
878 * Determines the itr/intrl granularities based on the maximum aggregate
879 * bandwidth according to the device's configuration during power-on.
881 static void ice_get_itr_intrl_gran(struct ice_hw *hw)
883 u8 max_agg_bw = (rd32(hw, GL_PWR_MODE_CTL) &
884 GL_PWR_MODE_CTL_CAR_MAX_BW_M) >>
885 GL_PWR_MODE_CTL_CAR_MAX_BW_S;
887 switch (max_agg_bw) {
888 case ICE_MAX_AGG_BW_200G:
889 case ICE_MAX_AGG_BW_100G:
890 case ICE_MAX_AGG_BW_50G:
891 hw->itr_gran = ICE_ITR_GRAN_ABOVE_25;
892 hw->intrl_gran = ICE_INTRL_GRAN_ABOVE_25;
894 case ICE_MAX_AGG_BW_25G:
895 hw->itr_gran = ICE_ITR_GRAN_MAX_25;
896 hw->intrl_gran = ICE_INTRL_GRAN_MAX_25;
902 * ice_get_nvm_version - get cached NVM version data
903 * @hw: pointer to the hardware structure
904 * @oem_ver: 8 bit NVM version
905 * @oem_build: 16 bit NVM build number
906 * @oem_patch: 8 NVM patch number
907 * @ver_hi: high 16 bits of the NVM version
908 * @ver_lo: low 16 bits of the NVM version
911 ice_get_nvm_version(struct ice_hw *hw, u8 *oem_ver, u16 *oem_build,
912 u8 *oem_patch, u8 *ver_hi, u8 *ver_lo)
914 struct ice_nvm_info *nvm = &hw->nvm;
916 *oem_ver = (u8)((nvm->oem_ver & ICE_OEM_VER_MASK) >> ICE_OEM_VER_SHIFT);
917 *oem_patch = (u8)(nvm->oem_ver & ICE_OEM_VER_PATCH_MASK);
918 *oem_build = (u16)((nvm->oem_ver & ICE_OEM_VER_BUILD_MASK) >>
919 ICE_OEM_VER_BUILD_SHIFT);
920 *ver_hi = (nvm->ver & ICE_NVM_VER_HI_MASK) >> ICE_NVM_VER_HI_SHIFT;
921 *ver_lo = (nvm->ver & ICE_NVM_VER_LO_MASK) >> ICE_NVM_VER_LO_SHIFT;
925 * ice_print_rollback_msg - print FW rollback message
926 * @hw: pointer to the hardware structure
928 void ice_print_rollback_msg(struct ice_hw *hw)
930 char nvm_str[ICE_NVM_VER_LEN] = { 0 };
931 u8 oem_ver, oem_patch, ver_hi, ver_lo;
934 ice_get_nvm_version(hw, &oem_ver, &oem_build, &oem_patch, &ver_hi,
936 SNPRINTF(nvm_str, sizeof(nvm_str), "%x.%02x 0x%x %d.%d.%d", ver_hi,
937 ver_lo, hw->nvm.eetrack, oem_ver, oem_build, oem_patch);
940 "Firmware rollback mode detected. Current version is NVM: %s, FW: %d.%d. Device may exhibit limited functionality. Refer to the Intel(R) Ethernet Adapters and Devices User Guide for details on firmware rollback mode",
941 nvm_str, hw->fw_maj_ver, hw->fw_min_ver);
945 * ice_init_hw - main hardware initialization routine
946 * @hw: pointer to the hardware structure
948 enum ice_status ice_init_hw(struct ice_hw *hw)
950 struct ice_aqc_get_phy_caps_data *pcaps;
951 enum ice_status status;
955 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
958 /* Set MAC type based on DeviceID */
959 status = ice_set_mac_type(hw);
963 hw->pf_id = (u8)(rd32(hw, PF_FUNC_RID) &
964 PF_FUNC_RID_FUNCTION_NUMBER_M) >>
965 PF_FUNC_RID_FUNCTION_NUMBER_S;
968 status = ice_reset(hw, ICE_RESET_PFR);
972 ice_get_itr_intrl_gran(hw);
975 status = ice_create_all_ctrlq(hw);
977 goto err_unroll_cqinit;
979 if (ice_get_fw_mode(hw) == ICE_FW_MODE_ROLLBACK)
980 ice_print_rollback_msg(hw);
982 /* Enable FW logging. Not fatal if this fails. */
983 status = ice_cfg_fw_log(hw, true);
985 ice_debug(hw, ICE_DBG_INIT, "Failed to enable FW logging.\n");
987 status = ice_clear_pf_cfg(hw);
989 goto err_unroll_cqinit;
991 /* Set bit to enable Flow Director filters */
992 wr32(hw, PFQF_FD_ENA, PFQF_FD_ENA_FD_ENA_M);
993 INIT_LIST_HEAD(&hw->fdir_list_head);
995 ice_clear_pxe_mode(hw);
997 status = ice_init_nvm(hw);
999 goto err_unroll_cqinit;
1001 status = ice_get_caps(hw);
1003 goto err_unroll_cqinit;
1005 hw->port_info = (struct ice_port_info *)
1006 ice_malloc(hw, sizeof(*hw->port_info));
1007 if (!hw->port_info) {
1008 status = ICE_ERR_NO_MEMORY;
1009 goto err_unroll_cqinit;
1012 /* set the back pointer to HW */
1013 hw->port_info->hw = hw;
1015 /* Initialize port_info struct with switch configuration data */
1016 status = ice_get_initial_sw_cfg(hw);
1018 goto err_unroll_alloc;
1022 /* Query the allocated resources for Tx scheduler */
1023 status = ice_sched_query_res_alloc(hw);
1025 ice_debug(hw, ICE_DBG_SCHED,
1026 "Failed to get scheduler allocated resources\n");
1027 goto err_unroll_alloc;
1031 /* Initialize port_info struct with scheduler data */
1032 status = ice_sched_init_port(hw->port_info);
1034 goto err_unroll_sched;
1036 pcaps = (struct ice_aqc_get_phy_caps_data *)
1037 ice_malloc(hw, sizeof(*pcaps));
1039 status = ICE_ERR_NO_MEMORY;
1040 goto err_unroll_sched;
1043 /* Initialize port_info struct with PHY capabilities */
1044 status = ice_aq_get_phy_caps(hw->port_info, false,
1045 ICE_AQC_REPORT_TOPO_CAP, pcaps, NULL);
1046 ice_free(hw, pcaps);
1048 goto err_unroll_sched;
1050 /* Initialize port_info struct with link information */
1051 status = ice_aq_get_link_info(hw->port_info, false, NULL, NULL);
1053 goto err_unroll_sched;
1054 /* need a valid SW entry point to build a Tx tree */
1055 if (!hw->sw_entry_point_layer) {
1056 ice_debug(hw, ICE_DBG_SCHED, "invalid sw entry point\n");
1057 status = ICE_ERR_CFG;
1058 goto err_unroll_sched;
1060 INIT_LIST_HEAD(&hw->agg_list);
1061 /* Initialize max burst size */
1062 if (!hw->max_burst_size)
1063 ice_cfg_rl_burst_size(hw, ICE_SCHED_DFLT_BURST_SIZE);
1065 status = ice_init_fltr_mgmt_struct(hw);
1067 goto err_unroll_sched;
1070 /* Get MAC information */
1071 /* A single port can report up to two (LAN and WoL) addresses */
1072 mac_buf = ice_calloc(hw, 2,
1073 sizeof(struct ice_aqc_manage_mac_read_resp));
1074 mac_buf_len = 2 * sizeof(struct ice_aqc_manage_mac_read_resp);
1077 status = ICE_ERR_NO_MEMORY;
1078 goto err_unroll_fltr_mgmt_struct;
1081 status = ice_aq_manage_mac_read(hw, mac_buf, mac_buf_len, NULL);
1082 ice_free(hw, mac_buf);
1085 goto err_unroll_fltr_mgmt_struct;
1087 ice_init_flex_flds(hw, ICE_RXDID_FLEX_NIC);
1088 ice_init_flex_flds(hw, ICE_RXDID_FLEX_NIC_2);
1089 ice_init_flex_flds(hw, ICE_RXDID_COMMS_GENERIC);
1090 ice_init_flex_flds(hw, ICE_RXDID_COMMS_AUX_VLAN);
1091 ice_init_flex_flds(hw, ICE_RXDID_COMMS_AUX_IPV4);
1092 ice_init_flex_flds(hw, ICE_RXDID_COMMS_AUX_IPV6);
1093 ice_init_flex_flds(hw, ICE_RXDID_COMMS_AUX_IPV6_FLOW);
1094 ice_init_flex_flds(hw, ICE_RXDID_COMMS_AUX_TCP);
1095 /* Obtain counter base index which would be used by flow director */
1096 status = ice_alloc_fd_res_cntr(hw, &hw->fd_ctr_base);
1098 goto err_unroll_fltr_mgmt_struct;
1099 status = ice_init_hw_tbls(hw);
1101 goto err_unroll_fltr_mgmt_struct;
1104 err_unroll_fltr_mgmt_struct:
1105 ice_cleanup_fltr_mgmt_struct(hw);
1107 ice_sched_cleanup_all(hw);
1109 ice_free(hw, hw->port_info);
1110 hw->port_info = NULL;
1112 ice_destroy_all_ctrlq(hw);
1117 * ice_deinit_hw - unroll initialization operations done by ice_init_hw
1118 * @hw: pointer to the hardware structure
1120 * This should be called only during nominal operation, not as a result of
1121 * ice_init_hw() failing since ice_init_hw() will take care of unrolling
1122 * applicable initializations if it fails for any reason.
1124 void ice_deinit_hw(struct ice_hw *hw)
1126 ice_free_fd_res_cntr(hw, hw->fd_ctr_base);
1127 ice_cleanup_fltr_mgmt_struct(hw);
1129 ice_sched_cleanup_all(hw);
1130 ice_sched_clear_agg(hw);
1132 ice_free_hw_tbls(hw);
1134 if (hw->port_info) {
1135 ice_free(hw, hw->port_info);
1136 hw->port_info = NULL;
1139 /* Attempt to disable FW logging before shutting down control queues */
1140 ice_cfg_fw_log(hw, false);
1141 ice_destroy_all_ctrlq(hw);
1143 /* Clear VSI contexts if not already cleared */
1144 ice_clear_all_vsi_ctx(hw);
1148 * ice_check_reset - Check to see if a global reset is complete
1149 * @hw: pointer to the hardware structure
1151 enum ice_status ice_check_reset(struct ice_hw *hw)
1153 u32 cnt, reg = 0, grst_delay;
1155 /* Poll for Device Active state in case a recent CORER, GLOBR,
1156 * or EMPR has occurred. The grst delay value is in 100ms units.
1157 * Add 1sec for outstanding AQ commands that can take a long time.
1159 grst_delay = ((rd32(hw, GLGEN_RSTCTL) & GLGEN_RSTCTL_GRSTDEL_M) >>
1160 GLGEN_RSTCTL_GRSTDEL_S) + 10;
1162 for (cnt = 0; cnt < grst_delay; cnt++) {
1163 ice_msec_delay(100, true);
1164 reg = rd32(hw, GLGEN_RSTAT);
1165 if (!(reg & GLGEN_RSTAT_DEVSTATE_M))
1169 if (cnt == grst_delay) {
1170 ice_debug(hw, ICE_DBG_INIT,
1171 "Global reset polling failed to complete.\n");
1172 return ICE_ERR_RESET_FAILED;
1175 #define ICE_RESET_DONE_MASK (GLNVM_ULD_CORER_DONE_M | \
1176 GLNVM_ULD_GLOBR_DONE_M)
1178 /* Device is Active; check Global Reset processes are done */
1179 for (cnt = 0; cnt < ICE_PF_RESET_WAIT_COUNT; cnt++) {
1180 reg = rd32(hw, GLNVM_ULD) & ICE_RESET_DONE_MASK;
1181 if (reg == ICE_RESET_DONE_MASK) {
1182 ice_debug(hw, ICE_DBG_INIT,
1183 "Global reset processes done. %d\n", cnt);
1186 ice_msec_delay(10, true);
1189 if (cnt == ICE_PF_RESET_WAIT_COUNT) {
1190 ice_debug(hw, ICE_DBG_INIT,
1191 "Wait for Reset Done timed out. GLNVM_ULD = 0x%x\n",
1193 return ICE_ERR_RESET_FAILED;
1200 * ice_pf_reset - Reset the PF
1201 * @hw: pointer to the hardware structure
1203 * If a global reset has been triggered, this function checks
1204 * for its completion and then issues the PF reset
1206 static enum ice_status ice_pf_reset(struct ice_hw *hw)
1210 /* If at function entry a global reset was already in progress, i.e.
1211 * state is not 'device active' or any of the reset done bits are not
1212 * set in GLNVM_ULD, there is no need for a PF Reset; poll until the
1213 * global reset is done.
1215 if ((rd32(hw, GLGEN_RSTAT) & GLGEN_RSTAT_DEVSTATE_M) ||
1216 (rd32(hw, GLNVM_ULD) & ICE_RESET_DONE_MASK) ^ ICE_RESET_DONE_MASK) {
1217 /* poll on global reset currently in progress until done */
1218 if (ice_check_reset(hw))
1219 return ICE_ERR_RESET_FAILED;
1225 reg = rd32(hw, PFGEN_CTRL);
1227 wr32(hw, PFGEN_CTRL, (reg | PFGEN_CTRL_PFSWR_M));
1229 for (cnt = 0; cnt < ICE_PF_RESET_WAIT_COUNT; cnt++) {
1230 reg = rd32(hw, PFGEN_CTRL);
1231 if (!(reg & PFGEN_CTRL_PFSWR_M))
1234 ice_msec_delay(1, true);
1237 if (cnt == ICE_PF_RESET_WAIT_COUNT) {
1238 ice_debug(hw, ICE_DBG_INIT,
1239 "PF reset polling failed to complete.\n");
1240 return ICE_ERR_RESET_FAILED;
1247 * ice_reset - Perform different types of reset
1248 * @hw: pointer to the hardware structure
1249 * @req: reset request
1251 * This function triggers a reset as specified by the req parameter.
1254 * If anything other than a PF reset is triggered, PXE mode is restored.
1255 * This has to be cleared using ice_clear_pxe_mode again, once the AQ
1256 * interface has been restored in the rebuild flow.
1258 enum ice_status ice_reset(struct ice_hw *hw, enum ice_reset_req req)
1264 return ice_pf_reset(hw);
1265 case ICE_RESET_CORER:
1266 ice_debug(hw, ICE_DBG_INIT, "CoreR requested\n");
1267 val = GLGEN_RTRIG_CORER_M;
1269 case ICE_RESET_GLOBR:
1270 ice_debug(hw, ICE_DBG_INIT, "GlobalR requested\n");
1271 val = GLGEN_RTRIG_GLOBR_M;
1274 return ICE_ERR_PARAM;
1277 val |= rd32(hw, GLGEN_RTRIG);
1278 wr32(hw, GLGEN_RTRIG, val);
1282 /* wait for the FW to be ready */
1283 return ice_check_reset(hw);
1289 * ice_copy_rxq_ctx_to_hw
1290 * @hw: pointer to the hardware structure
1291 * @ice_rxq_ctx: pointer to the rxq context
1292 * @rxq_index: the index of the Rx queue
1294 * Copies rxq context from dense structure to HW register space
1296 static enum ice_status
1297 ice_copy_rxq_ctx_to_hw(struct ice_hw *hw, u8 *ice_rxq_ctx, u32 rxq_index)
1302 return ICE_ERR_BAD_PTR;
1304 if (rxq_index > QRX_CTRL_MAX_INDEX)
1305 return ICE_ERR_PARAM;
1307 /* Copy each dword separately to HW */
1308 for (i = 0; i < ICE_RXQ_CTX_SIZE_DWORDS; i++) {
1309 wr32(hw, QRX_CONTEXT(i, rxq_index),
1310 *((u32 *)(ice_rxq_ctx + (i * sizeof(u32)))));
1312 ice_debug(hw, ICE_DBG_QCTX, "qrxdata[%d]: %08X\n", i,
1313 *((u32 *)(ice_rxq_ctx + (i * sizeof(u32)))));
1319 /* LAN Rx Queue Context */
1320 static const struct ice_ctx_ele ice_rlan_ctx_info[] = {
1321 /* Field Width LSB */
1322 ICE_CTX_STORE(ice_rlan_ctx, head, 13, 0),
1323 ICE_CTX_STORE(ice_rlan_ctx, cpuid, 8, 13),
1324 ICE_CTX_STORE(ice_rlan_ctx, base, 57, 32),
1325 ICE_CTX_STORE(ice_rlan_ctx, qlen, 13, 89),
1326 ICE_CTX_STORE(ice_rlan_ctx, dbuf, 7, 102),
1327 ICE_CTX_STORE(ice_rlan_ctx, hbuf, 5, 109),
1328 ICE_CTX_STORE(ice_rlan_ctx, dtype, 2, 114),
1329 ICE_CTX_STORE(ice_rlan_ctx, dsize, 1, 116),
1330 ICE_CTX_STORE(ice_rlan_ctx, crcstrip, 1, 117),
1331 ICE_CTX_STORE(ice_rlan_ctx, l2tsel, 1, 119),
1332 ICE_CTX_STORE(ice_rlan_ctx, hsplit_0, 4, 120),
1333 ICE_CTX_STORE(ice_rlan_ctx, hsplit_1, 2, 124),
1334 ICE_CTX_STORE(ice_rlan_ctx, showiv, 1, 127),
1335 ICE_CTX_STORE(ice_rlan_ctx, rxmax, 14, 174),
1336 ICE_CTX_STORE(ice_rlan_ctx, tphrdesc_ena, 1, 193),
1337 ICE_CTX_STORE(ice_rlan_ctx, tphwdesc_ena, 1, 194),
1338 ICE_CTX_STORE(ice_rlan_ctx, tphdata_ena, 1, 195),
1339 ICE_CTX_STORE(ice_rlan_ctx, tphhead_ena, 1, 196),
1340 ICE_CTX_STORE(ice_rlan_ctx, lrxqthresh, 3, 198),
1341 ICE_CTX_STORE(ice_rlan_ctx, prefena, 1, 201),
1347 * @hw: pointer to the hardware structure
1348 * @rlan_ctx: pointer to the rxq context
1349 * @rxq_index: the index of the Rx queue
1351 * Converts rxq context from sparse to dense structure and then writes
1352 * it to HW register space and enables the hardware to prefetch descriptors
1353 * instead of only fetching them on demand
1356 ice_write_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx,
1359 u8 ctx_buf[ICE_RXQ_CTX_SZ] = { 0 };
1362 return ICE_ERR_BAD_PTR;
1364 rlan_ctx->prefena = 1;
1366 ice_set_ctx((u8 *)rlan_ctx, ctx_buf, ice_rlan_ctx_info);
1367 return ice_copy_rxq_ctx_to_hw(hw, ctx_buf, rxq_index);
1370 #if !defined(NO_UNUSED_CTX_CODE) || defined(AE_DRIVER)
1373 * @hw: pointer to the hardware structure
1374 * @rxq_index: the index of the Rx queue to clear
1376 * Clears rxq context in HW register space
1378 enum ice_status ice_clear_rxq_ctx(struct ice_hw *hw, u32 rxq_index)
1382 if (rxq_index > QRX_CTRL_MAX_INDEX)
1383 return ICE_ERR_PARAM;
1385 /* Clear each dword register separately */
1386 for (i = 0; i < ICE_RXQ_CTX_SIZE_DWORDS; i++)
1387 wr32(hw, QRX_CONTEXT(i, rxq_index), 0);
1391 #endif /* !NO_UNUSED_CTX_CODE || AE_DRIVER */
1393 /* LAN Tx Queue Context */
1394 const struct ice_ctx_ele ice_tlan_ctx_info[] = {
1395 /* Field Width LSB */
1396 ICE_CTX_STORE(ice_tlan_ctx, base, 57, 0),
1397 ICE_CTX_STORE(ice_tlan_ctx, port_num, 3, 57),
1398 ICE_CTX_STORE(ice_tlan_ctx, cgd_num, 5, 60),
1399 ICE_CTX_STORE(ice_tlan_ctx, pf_num, 3, 65),
1400 ICE_CTX_STORE(ice_tlan_ctx, vmvf_num, 10, 68),
1401 ICE_CTX_STORE(ice_tlan_ctx, vmvf_type, 2, 78),
1402 ICE_CTX_STORE(ice_tlan_ctx, src_vsi, 10, 80),
1403 ICE_CTX_STORE(ice_tlan_ctx, tsyn_ena, 1, 90),
1404 ICE_CTX_STORE(ice_tlan_ctx, internal_usage_flag, 1, 91),
1405 ICE_CTX_STORE(ice_tlan_ctx, alt_vlan, 1, 92),
1406 ICE_CTX_STORE(ice_tlan_ctx, cpuid, 8, 93),
1407 ICE_CTX_STORE(ice_tlan_ctx, wb_mode, 1, 101),
1408 ICE_CTX_STORE(ice_tlan_ctx, tphrd_desc, 1, 102),
1409 ICE_CTX_STORE(ice_tlan_ctx, tphrd, 1, 103),
1410 ICE_CTX_STORE(ice_tlan_ctx, tphwr_desc, 1, 104),
1411 ICE_CTX_STORE(ice_tlan_ctx, cmpq_id, 9, 105),
1412 ICE_CTX_STORE(ice_tlan_ctx, qnum_in_func, 14, 114),
1413 ICE_CTX_STORE(ice_tlan_ctx, itr_notification_mode, 1, 128),
1414 ICE_CTX_STORE(ice_tlan_ctx, adjust_prof_id, 6, 129),
1415 ICE_CTX_STORE(ice_tlan_ctx, qlen, 13, 135),
1416 ICE_CTX_STORE(ice_tlan_ctx, quanta_prof_idx, 4, 148),
1417 ICE_CTX_STORE(ice_tlan_ctx, tso_ena, 1, 152),
1418 ICE_CTX_STORE(ice_tlan_ctx, tso_qnum, 11, 153),
1419 ICE_CTX_STORE(ice_tlan_ctx, legacy_int, 1, 164),
1420 ICE_CTX_STORE(ice_tlan_ctx, drop_ena, 1, 165),
1421 ICE_CTX_STORE(ice_tlan_ctx, cache_prof_idx, 2, 166),
1422 ICE_CTX_STORE(ice_tlan_ctx, pkt_shaper_prof_idx, 3, 168),
1423 ICE_CTX_STORE(ice_tlan_ctx, int_q_state, 122, 171),
1427 #if !defined(NO_UNUSED_CTX_CODE) || defined(AE_DRIVER)
1429 * ice_copy_tx_cmpltnq_ctx_to_hw
1430 * @hw: pointer to the hardware structure
1431 * @ice_tx_cmpltnq_ctx: pointer to the Tx completion queue context
1432 * @tx_cmpltnq_index: the index of the completion queue
1434 * Copies Tx completion queue context from dense structure to HW register space
1436 static enum ice_status
1437 ice_copy_tx_cmpltnq_ctx_to_hw(struct ice_hw *hw, u8 *ice_tx_cmpltnq_ctx,
1438 u32 tx_cmpltnq_index)
1442 if (!ice_tx_cmpltnq_ctx)
1443 return ICE_ERR_BAD_PTR;
1445 if (tx_cmpltnq_index > GLTCLAN_CQ_CNTX0_MAX_INDEX)
1446 return ICE_ERR_PARAM;
1448 /* Copy each dword separately to HW */
1449 for (i = 0; i < ICE_TX_CMPLTNQ_CTX_SIZE_DWORDS; i++) {
1450 wr32(hw, GLTCLAN_CQ_CNTX(i, tx_cmpltnq_index),
1451 *((u32 *)(ice_tx_cmpltnq_ctx + (i * sizeof(u32)))));
1453 ice_debug(hw, ICE_DBG_QCTX, "cmpltnqdata[%d]: %08X\n", i,
1454 *((u32 *)(ice_tx_cmpltnq_ctx + (i * sizeof(u32)))));
1460 /* LAN Tx Completion Queue Context */
1461 static const struct ice_ctx_ele ice_tx_cmpltnq_ctx_info[] = {
1462 /* Field Width LSB */
1463 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, base, 57, 0),
1464 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, q_len, 18, 64),
1465 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, generation, 1, 96),
1466 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, wrt_ptr, 22, 97),
1467 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, pf_num, 3, 128),
1468 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, vmvf_num, 10, 131),
1469 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, vmvf_type, 2, 141),
1470 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, tph_desc_wr, 1, 160),
1471 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, cpuid, 8, 161),
1472 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, cmpltn_cache, 512, 192),
1477 * ice_write_tx_cmpltnq_ctx
1478 * @hw: pointer to the hardware structure
1479 * @tx_cmpltnq_ctx: pointer to the completion queue context
1480 * @tx_cmpltnq_index: the index of the completion queue
1482 * Converts completion queue context from sparse to dense structure and then
1483 * writes it to HW register space
1486 ice_write_tx_cmpltnq_ctx(struct ice_hw *hw,
1487 struct ice_tx_cmpltnq_ctx *tx_cmpltnq_ctx,
1488 u32 tx_cmpltnq_index)
1490 u8 ctx_buf[ICE_TX_CMPLTNQ_CTX_SIZE_DWORDS * sizeof(u32)] = { 0 };
1492 ice_set_ctx((u8 *)tx_cmpltnq_ctx, ctx_buf, ice_tx_cmpltnq_ctx_info);
1493 return ice_copy_tx_cmpltnq_ctx_to_hw(hw, ctx_buf, tx_cmpltnq_index);
1497 * ice_clear_tx_cmpltnq_ctx
1498 * @hw: pointer to the hardware structure
1499 * @tx_cmpltnq_index: the index of the completion queue to clear
1501 * Clears Tx completion queue context in HW register space
1504 ice_clear_tx_cmpltnq_ctx(struct ice_hw *hw, u32 tx_cmpltnq_index)
1508 if (tx_cmpltnq_index > GLTCLAN_CQ_CNTX0_MAX_INDEX)
1509 return ICE_ERR_PARAM;
1511 /* Clear each dword register separately */
1512 for (i = 0; i < ICE_TX_CMPLTNQ_CTX_SIZE_DWORDS; i++)
1513 wr32(hw, GLTCLAN_CQ_CNTX(i, tx_cmpltnq_index), 0);
1519 * ice_copy_tx_drbell_q_ctx_to_hw
1520 * @hw: pointer to the hardware structure
1521 * @ice_tx_drbell_q_ctx: pointer to the doorbell queue context
1522 * @tx_drbell_q_index: the index of the doorbell queue
1524 * Copies doorbell queue context from dense structure to HW register space
1526 static enum ice_status
1527 ice_copy_tx_drbell_q_ctx_to_hw(struct ice_hw *hw, u8 *ice_tx_drbell_q_ctx,
1528 u32 tx_drbell_q_index)
1532 if (!ice_tx_drbell_q_ctx)
1533 return ICE_ERR_BAD_PTR;
1535 if (tx_drbell_q_index > QTX_COMM_DBLQ_DBELL_MAX_INDEX)
1536 return ICE_ERR_PARAM;
1538 /* Copy each dword separately to HW */
1539 for (i = 0; i < ICE_TX_DRBELL_Q_CTX_SIZE_DWORDS; i++) {
1540 wr32(hw, QTX_COMM_DBLQ_CNTX(i, tx_drbell_q_index),
1541 *((u32 *)(ice_tx_drbell_q_ctx + (i * sizeof(u32)))));
1543 ice_debug(hw, ICE_DBG_QCTX, "tx_drbell_qdata[%d]: %08X\n", i,
1544 *((u32 *)(ice_tx_drbell_q_ctx + (i * sizeof(u32)))));
1550 /* LAN Tx Doorbell Queue Context info */
1551 static const struct ice_ctx_ele ice_tx_drbell_q_ctx_info[] = {
1552 /* Field Width LSB */
1553 ICE_CTX_STORE(ice_tx_drbell_q_ctx, base, 57, 0),
1554 ICE_CTX_STORE(ice_tx_drbell_q_ctx, ring_len, 13, 64),
1555 ICE_CTX_STORE(ice_tx_drbell_q_ctx, pf_num, 3, 80),
1556 ICE_CTX_STORE(ice_tx_drbell_q_ctx, vf_num, 8, 84),
1557 ICE_CTX_STORE(ice_tx_drbell_q_ctx, vmvf_type, 2, 94),
1558 ICE_CTX_STORE(ice_tx_drbell_q_ctx, cpuid, 8, 96),
1559 ICE_CTX_STORE(ice_tx_drbell_q_ctx, tph_desc_rd, 1, 104),
1560 ICE_CTX_STORE(ice_tx_drbell_q_ctx, tph_desc_wr, 1, 108),
1561 ICE_CTX_STORE(ice_tx_drbell_q_ctx, db_q_en, 1, 112),
1562 ICE_CTX_STORE(ice_tx_drbell_q_ctx, rd_head, 13, 128),
1563 ICE_CTX_STORE(ice_tx_drbell_q_ctx, rd_tail, 13, 144),
1568 * ice_write_tx_drbell_q_ctx
1569 * @hw: pointer to the hardware structure
1570 * @tx_drbell_q_ctx: pointer to the doorbell queue context
1571 * @tx_drbell_q_index: the index of the doorbell queue
1573 * Converts doorbell queue context from sparse to dense structure and then
1574 * writes it to HW register space
1577 ice_write_tx_drbell_q_ctx(struct ice_hw *hw,
1578 struct ice_tx_drbell_q_ctx *tx_drbell_q_ctx,
1579 u32 tx_drbell_q_index)
1581 u8 ctx_buf[ICE_TX_DRBELL_Q_CTX_SIZE_DWORDS * sizeof(u32)] = { 0 };
1583 ice_set_ctx((u8 *)tx_drbell_q_ctx, ctx_buf, ice_tx_drbell_q_ctx_info);
1584 return ice_copy_tx_drbell_q_ctx_to_hw(hw, ctx_buf, tx_drbell_q_index);
1588 * ice_clear_tx_drbell_q_ctx
1589 * @hw: pointer to the hardware structure
1590 * @tx_drbell_q_index: the index of the doorbell queue to clear
1592 * Clears doorbell queue context in HW register space
1595 ice_clear_tx_drbell_q_ctx(struct ice_hw *hw, u32 tx_drbell_q_index)
1599 if (tx_drbell_q_index > QTX_COMM_DBLQ_DBELL_MAX_INDEX)
1600 return ICE_ERR_PARAM;
1602 /* Clear each dword register separately */
1603 for (i = 0; i < ICE_TX_DRBELL_Q_CTX_SIZE_DWORDS; i++)
1604 wr32(hw, QTX_COMM_DBLQ_CNTX(i, tx_drbell_q_index), 0);
1608 #endif /* !NO_UNUSED_CTX_CODE || AE_DRIVER */
1611 /* FW Admin Queue command wrappers */
1614 * ice_aq_send_cmd - send FW Admin Queue command to FW Admin Queue
1615 * @hw: pointer to the HW struct
1616 * @desc: descriptor describing the command
1617 * @buf: buffer to use for indirect commands (NULL for direct commands)
1618 * @buf_size: size of buffer for indirect commands (0 for direct commands)
1619 * @cd: pointer to command details structure
1621 * Helper function to send FW Admin Queue commands to the FW Admin Queue.
1624 ice_aq_send_cmd(struct ice_hw *hw, struct ice_aq_desc *desc, void *buf,
1625 u16 buf_size, struct ice_sq_cd *cd)
1627 return ice_sq_send_cmd(hw, &hw->adminq, desc, buf, buf_size, cd);
1632 * @hw: pointer to the HW struct
1633 * @cd: pointer to command details structure or NULL
1635 * Get the firmware version (0x0001) from the admin queue commands
1637 enum ice_status ice_aq_get_fw_ver(struct ice_hw *hw, struct ice_sq_cd *cd)
1639 struct ice_aqc_get_ver *resp;
1640 struct ice_aq_desc desc;
1641 enum ice_status status;
1643 resp = &desc.params.get_ver;
1645 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_ver);
1647 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
1650 hw->fw_branch = resp->fw_branch;
1651 hw->fw_maj_ver = resp->fw_major;
1652 hw->fw_min_ver = resp->fw_minor;
1653 hw->fw_patch = resp->fw_patch;
1654 hw->fw_build = LE32_TO_CPU(resp->fw_build);
1655 hw->api_branch = resp->api_branch;
1656 hw->api_maj_ver = resp->api_major;
1657 hw->api_min_ver = resp->api_minor;
1658 hw->api_patch = resp->api_patch;
1665 * ice_aq_send_driver_ver
1666 * @hw: pointer to the HW struct
1667 * @dv: driver's major, minor version
1668 * @cd: pointer to command details structure or NULL
1670 * Send the driver version (0x0002) to the firmware
1673 ice_aq_send_driver_ver(struct ice_hw *hw, struct ice_driver_ver *dv,
1674 struct ice_sq_cd *cd)
1676 struct ice_aqc_driver_ver *cmd;
1677 struct ice_aq_desc desc;
1680 cmd = &desc.params.driver_ver;
1683 return ICE_ERR_PARAM;
1685 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_driver_ver);
1687 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
1688 cmd->major_ver = dv->major_ver;
1689 cmd->minor_ver = dv->minor_ver;
1690 cmd->build_ver = dv->build_ver;
1691 cmd->subbuild_ver = dv->subbuild_ver;
1694 while (len < sizeof(dv->driver_string) &&
1695 IS_ASCII(dv->driver_string[len]) && dv->driver_string[len])
1698 return ice_aq_send_cmd(hw, &desc, dv->driver_string, len, cd);
1703 * @hw: pointer to the HW struct
1704 * @unloading: is the driver unloading itself
1706 * Tell the Firmware that we're shutting down the AdminQ and whether
1707 * or not the driver is unloading as well (0x0003).
1709 enum ice_status ice_aq_q_shutdown(struct ice_hw *hw, bool unloading)
1711 struct ice_aqc_q_shutdown *cmd;
1712 struct ice_aq_desc desc;
1714 cmd = &desc.params.q_shutdown;
1716 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_q_shutdown);
1719 cmd->driver_unloading = ICE_AQC_DRIVER_UNLOADING;
1721 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
1726 * @hw: pointer to the HW struct
1728 * @access: access type
1729 * @sdp_number: resource number
1730 * @timeout: the maximum time in ms that the driver may hold the resource
1731 * @cd: pointer to command details structure or NULL
1733 * Requests common resource using the admin queue commands (0x0008).
1734 * When attempting to acquire the Global Config Lock, the driver can
1735 * learn of three states:
1736 * 1) ICE_SUCCESS - acquired lock, and can perform download package
1737 * 2) ICE_ERR_AQ_ERROR - did not get lock, driver should fail to load
1738 * 3) ICE_ERR_AQ_NO_WORK - did not get lock, but another driver has
1739 * successfully downloaded the package; the driver does
1740 * not have to download the package and can continue
1743 * Note that if the caller is in an acquire lock, perform action, release lock
1744 * phase of operation, it is possible that the FW may detect a timeout and issue
1745 * a CORER. In this case, the driver will receive a CORER interrupt and will
1746 * have to determine its cause. The calling thread that is handling this flow
1747 * will likely get an error propagated back to it indicating the Download
1748 * Package, Update Package or the Release Resource AQ commands timed out.
1750 static enum ice_status
1751 ice_aq_req_res(struct ice_hw *hw, enum ice_aq_res_ids res,
1752 enum ice_aq_res_access_type access, u8 sdp_number, u32 *timeout,
1753 struct ice_sq_cd *cd)
1755 struct ice_aqc_req_res *cmd_resp;
1756 struct ice_aq_desc desc;
1757 enum ice_status status;
1759 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
1761 cmd_resp = &desc.params.res_owner;
1763 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_req_res);
1765 cmd_resp->res_id = CPU_TO_LE16(res);
1766 cmd_resp->access_type = CPU_TO_LE16(access);
1767 cmd_resp->res_number = CPU_TO_LE32(sdp_number);
1768 cmd_resp->timeout = CPU_TO_LE32(*timeout);
1771 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
1773 /* The completion specifies the maximum time in ms that the driver
1774 * may hold the resource in the Timeout field.
1777 /* Global config lock response utilizes an additional status field.
1779 * If the Global config lock resource is held by some other driver, the
1780 * command completes with ICE_AQ_RES_GLBL_IN_PROG in the status field
1781 * and the timeout field indicates the maximum time the current owner
1782 * of the resource has to free it.
1784 if (res == ICE_GLOBAL_CFG_LOCK_RES_ID) {
1785 if (LE16_TO_CPU(cmd_resp->status) == ICE_AQ_RES_GLBL_SUCCESS) {
1786 *timeout = LE32_TO_CPU(cmd_resp->timeout);
1788 } else if (LE16_TO_CPU(cmd_resp->status) ==
1789 ICE_AQ_RES_GLBL_IN_PROG) {
1790 *timeout = LE32_TO_CPU(cmd_resp->timeout);
1791 return ICE_ERR_AQ_ERROR;
1792 } else if (LE16_TO_CPU(cmd_resp->status) ==
1793 ICE_AQ_RES_GLBL_DONE) {
1794 return ICE_ERR_AQ_NO_WORK;
1797 /* invalid FW response, force a timeout immediately */
1799 return ICE_ERR_AQ_ERROR;
1802 /* If the resource is held by some other driver, the command completes
1803 * with a busy return value and the timeout field indicates the maximum
1804 * time the current owner of the resource has to free it.
1806 if (!status || hw->adminq.sq_last_status == ICE_AQ_RC_EBUSY)
1807 *timeout = LE32_TO_CPU(cmd_resp->timeout);
1813 * ice_aq_release_res
1814 * @hw: pointer to the HW struct
1816 * @sdp_number: resource number
1817 * @cd: pointer to command details structure or NULL
1819 * release common resource using the admin queue commands (0x0009)
1821 static enum ice_status
1822 ice_aq_release_res(struct ice_hw *hw, enum ice_aq_res_ids res, u8 sdp_number,
1823 struct ice_sq_cd *cd)
1825 struct ice_aqc_req_res *cmd;
1826 struct ice_aq_desc desc;
1828 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
1830 cmd = &desc.params.res_owner;
1832 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_release_res);
1834 cmd->res_id = CPU_TO_LE16(res);
1835 cmd->res_number = CPU_TO_LE32(sdp_number);
1837 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
1842 * @hw: pointer to the HW structure
1844 * @access: access type (read or write)
1845 * @timeout: timeout in milliseconds
1847 * This function will attempt to acquire the ownership of a resource.
1850 ice_acquire_res(struct ice_hw *hw, enum ice_aq_res_ids res,
1851 enum ice_aq_res_access_type access, u32 timeout)
1853 #define ICE_RES_POLLING_DELAY_MS 10
1854 u32 delay = ICE_RES_POLLING_DELAY_MS;
1855 u32 time_left = timeout;
1856 enum ice_status status;
1858 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
1860 status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL);
1862 /* A return code of ICE_ERR_AQ_NO_WORK means that another driver has
1863 * previously acquired the resource and performed any necessary updates;
1864 * in this case the caller does not obtain the resource and has no
1865 * further work to do.
1867 if (status == ICE_ERR_AQ_NO_WORK)
1868 goto ice_acquire_res_exit;
1871 ice_debug(hw, ICE_DBG_RES,
1872 "resource %d acquire type %d failed.\n", res, access);
1874 /* If necessary, poll until the current lock owner timeouts */
1875 timeout = time_left;
1876 while (status && timeout && time_left) {
1877 ice_msec_delay(delay, true);
1878 timeout = (timeout > delay) ? timeout - delay : 0;
1879 status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL);
1881 if (status == ICE_ERR_AQ_NO_WORK)
1882 /* lock free, but no work to do */
1889 if (status && status != ICE_ERR_AQ_NO_WORK)
1890 ice_debug(hw, ICE_DBG_RES, "resource acquire timed out.\n");
1892 ice_acquire_res_exit:
1893 if (status == ICE_ERR_AQ_NO_WORK) {
1894 if (access == ICE_RES_WRITE)
1895 ice_debug(hw, ICE_DBG_RES,
1896 "resource indicates no work to do.\n");
1898 ice_debug(hw, ICE_DBG_RES,
1899 "Warning: ICE_ERR_AQ_NO_WORK not expected\n");
1906 * @hw: pointer to the HW structure
1909 * This function will release a resource using the proper Admin Command.
1911 void ice_release_res(struct ice_hw *hw, enum ice_aq_res_ids res)
1913 enum ice_status status;
1914 u32 total_delay = 0;
1916 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
1918 status = ice_aq_release_res(hw, res, 0, NULL);
1920 /* there are some rare cases when trying to release the resource
1921 * results in an admin queue timeout, so handle them correctly
1923 while ((status == ICE_ERR_AQ_TIMEOUT) &&
1924 (total_delay < hw->adminq.sq_cmd_timeout)) {
1925 ice_msec_delay(1, true);
1926 status = ice_aq_release_res(hw, res, 0, NULL);
1932 * ice_aq_alloc_free_res - command to allocate/free resources
1933 * @hw: pointer to the HW struct
1934 * @num_entries: number of resource entries in buffer
1935 * @buf: Indirect buffer to hold data parameters and response
1936 * @buf_size: size of buffer for indirect commands
1937 * @opc: pass in the command opcode
1938 * @cd: pointer to command details structure or NULL
1940 * Helper function to allocate/free resources using the admin queue commands
1943 ice_aq_alloc_free_res(struct ice_hw *hw, u16 num_entries,
1944 struct ice_aqc_alloc_free_res_elem *buf, u16 buf_size,
1945 enum ice_adminq_opc opc, struct ice_sq_cd *cd)
1947 struct ice_aqc_alloc_free_res_cmd *cmd;
1948 struct ice_aq_desc desc;
1950 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
1952 cmd = &desc.params.sw_res_ctrl;
1955 return ICE_ERR_PARAM;
1957 if (buf_size < (num_entries * sizeof(buf->elem[0])))
1958 return ICE_ERR_PARAM;
1960 ice_fill_dflt_direct_cmd_desc(&desc, opc);
1962 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
1964 cmd->num_entries = CPU_TO_LE16(num_entries);
1966 return ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);
1970 * ice_alloc_hw_res - allocate resource
1971 * @hw: pointer to the HW struct
1972 * @type: type of resource
1973 * @num: number of resources to allocate
1974 * @btm: allocate from bottom
1975 * @res: pointer to array that will receive the resources
1978 ice_alloc_hw_res(struct ice_hw *hw, u16 type, u16 num, bool btm, u16 *res)
1980 struct ice_aqc_alloc_free_res_elem *buf;
1981 enum ice_status status;
1984 buf_len = sizeof(*buf) + sizeof(buf->elem) * (num - 1);
1985 buf = (struct ice_aqc_alloc_free_res_elem *)
1986 ice_malloc(hw, buf_len);
1988 return ICE_ERR_NO_MEMORY;
1990 /* Prepare buffer to allocate resource. */
1991 buf->num_elems = CPU_TO_LE16(num);
1992 buf->res_type = CPU_TO_LE16(type | ICE_AQC_RES_TYPE_FLAG_DEDICATED |
1993 ICE_AQC_RES_TYPE_FLAG_IGNORE_INDEX);
1995 buf->res_type |= CPU_TO_LE16(ICE_AQC_RES_TYPE_FLAG_SCAN_BOTTOM);
1997 status = ice_aq_alloc_free_res(hw, 1, buf, buf_len,
1998 ice_aqc_opc_alloc_res, NULL);
2000 goto ice_alloc_res_exit;
2002 ice_memcpy(res, buf->elem, sizeof(buf->elem) * num,
2003 ICE_NONDMA_TO_NONDMA);
2011 * ice_free_hw_res - free allocated HW resource
2012 * @hw: pointer to the HW struct
2013 * @type: type of resource to free
2014 * @num: number of resources
2015 * @res: pointer to array that contains the resources to free
2018 ice_free_hw_res(struct ice_hw *hw, u16 type, u16 num, u16 *res)
2020 struct ice_aqc_alloc_free_res_elem *buf;
2021 enum ice_status status;
2024 buf_len = sizeof(*buf) + sizeof(buf->elem) * (num - 1);
2025 buf = (struct ice_aqc_alloc_free_res_elem *)ice_malloc(hw, buf_len);
2027 return ICE_ERR_NO_MEMORY;
2029 /* Prepare buffer to free resource. */
2030 buf->num_elems = CPU_TO_LE16(num);
2031 buf->res_type = CPU_TO_LE16(type);
2032 ice_memcpy(buf->elem, res, sizeof(buf->elem) * num,
2033 ICE_NONDMA_TO_NONDMA);
2035 status = ice_aq_alloc_free_res(hw, num, buf, buf_len,
2036 ice_aqc_opc_free_res, NULL);
2038 ice_debug(hw, ICE_DBG_SW, "CQ CMD Buffer:\n");
2045 * ice_get_num_per_func - determine number of resources per PF
2046 * @hw: pointer to the HW structure
2047 * @max: value to be evenly split between each PF
2049 * Determine the number of valid functions by going through the bitmap returned
2050 * from parsing capabilities and use this to calculate the number of resources
2051 * per PF based on the max value passed in.
2053 static u32 ice_get_num_per_func(struct ice_hw *hw, u32 max)
2057 #define ICE_CAPS_VALID_FUNCS_M 0xFF
2058 funcs = ice_hweight8(hw->dev_caps.common_cap.valid_functions &
2059 ICE_CAPS_VALID_FUNCS_M);
2068 * ice_parse_caps - parse function/device capabilities
2069 * @hw: pointer to the HW struct
2070 * @buf: pointer to a buffer containing function/device capability records
2071 * @cap_count: number of capability records in the list
2072 * @opc: type of capabilities list to parse
2074 * Helper function to parse function(0x000a)/device(0x000b) capabilities list.
2077 ice_parse_caps(struct ice_hw *hw, void *buf, u32 cap_count,
2078 enum ice_adminq_opc opc)
2080 struct ice_aqc_list_caps_elem *cap_resp;
2081 struct ice_hw_func_caps *func_p = NULL;
2082 struct ice_hw_dev_caps *dev_p = NULL;
2083 struct ice_hw_common_caps *caps;
2090 cap_resp = (struct ice_aqc_list_caps_elem *)buf;
2092 if (opc == ice_aqc_opc_list_dev_caps) {
2093 dev_p = &hw->dev_caps;
2094 caps = &dev_p->common_cap;
2096 } else if (opc == ice_aqc_opc_list_func_caps) {
2097 func_p = &hw->func_caps;
2098 caps = &func_p->common_cap;
2099 prefix = "func cap";
2101 ice_debug(hw, ICE_DBG_INIT, "wrong opcode\n");
2105 for (i = 0; caps && i < cap_count; i++, cap_resp++) {
2106 u32 logical_id = LE32_TO_CPU(cap_resp->logical_id);
2107 u32 phys_id = LE32_TO_CPU(cap_resp->phys_id);
2108 u32 number = LE32_TO_CPU(cap_resp->number);
2109 u16 cap = LE16_TO_CPU(cap_resp->cap);
2112 case ICE_AQC_CAPS_VALID_FUNCTIONS:
2113 caps->valid_functions = number;
2114 ice_debug(hw, ICE_DBG_INIT,
2115 "%s: valid functions = %d\n", prefix,
2116 caps->valid_functions);
2118 case ICE_AQC_CAPS_VSI:
2120 dev_p->num_vsi_allocd_to_host = number;
2121 ice_debug(hw, ICE_DBG_INIT,
2122 "%s: num VSI alloc to host = %d\n",
2124 dev_p->num_vsi_allocd_to_host);
2125 } else if (func_p) {
2126 func_p->guar_num_vsi =
2127 ice_get_num_per_func(hw, ICE_MAX_VSI);
2128 ice_debug(hw, ICE_DBG_INIT,
2129 "%s: num guaranteed VSI (fw) = %d\n",
2131 ice_debug(hw, ICE_DBG_INIT,
2132 "%s: num guaranteed VSI = %d\n",
2133 prefix, func_p->guar_num_vsi);
2136 case ICE_AQC_CAPS_DCB:
2137 caps->dcb = (number == 1);
2138 caps->active_tc_bitmap = logical_id;
2139 caps->maxtc = phys_id;
2140 ice_debug(hw, ICE_DBG_INIT,
2141 "%s: DCB = %d\n", prefix, caps->dcb);
2142 ice_debug(hw, ICE_DBG_INIT,
2143 "%s: active TC bitmap = %d\n", prefix,
2144 caps->active_tc_bitmap);
2145 ice_debug(hw, ICE_DBG_INIT,
2146 "%s: TC max = %d\n", prefix, caps->maxtc);
2148 case ICE_AQC_CAPS_RSS:
2149 caps->rss_table_size = number;
2150 caps->rss_table_entry_width = logical_id;
2151 ice_debug(hw, ICE_DBG_INIT,
2152 "%s: RSS table size = %d\n", prefix,
2153 caps->rss_table_size);
2154 ice_debug(hw, ICE_DBG_INIT,
2155 "%s: RSS table width = %d\n", prefix,
2156 caps->rss_table_entry_width);
2158 case ICE_AQC_CAPS_RXQS:
2159 caps->num_rxq = number;
2160 caps->rxq_first_id = phys_id;
2161 ice_debug(hw, ICE_DBG_INIT,
2162 "%s: num Rx queues = %d\n", prefix,
2164 ice_debug(hw, ICE_DBG_INIT,
2165 "%s: Rx first queue ID = %d\n", prefix,
2166 caps->rxq_first_id);
2168 case ICE_AQC_CAPS_TXQS:
2169 caps->num_txq = number;
2170 caps->txq_first_id = phys_id;
2171 ice_debug(hw, ICE_DBG_INIT,
2172 "%s: num Tx queues = %d\n", prefix,
2174 ice_debug(hw, ICE_DBG_INIT,
2175 "%s: Tx first queue ID = %d\n", prefix,
2176 caps->txq_first_id);
2178 case ICE_AQC_CAPS_MSIX:
2179 caps->num_msix_vectors = number;
2180 caps->msix_vector_first_id = phys_id;
2181 ice_debug(hw, ICE_DBG_INIT,
2182 "%s: MSIX vector count = %d\n", prefix,
2183 caps->num_msix_vectors);
2184 ice_debug(hw, ICE_DBG_INIT,
2185 "%s: MSIX first vector index = %d\n", prefix,
2186 caps->msix_vector_first_id);
2188 case ICE_AQC_CAPS_FD:
2193 dev_p->num_flow_director_fltr = number;
2194 ice_debug(hw, ICE_DBG_INIT,
2195 "%s: num FD filters = %d\n", prefix,
2196 dev_p->num_flow_director_fltr);
2199 reg_val = rd32(hw, GLQF_FD_SIZE);
2200 val = (reg_val & GLQF_FD_SIZE_FD_GSIZE_M) >>
2201 GLQF_FD_SIZE_FD_GSIZE_S;
2202 func_p->fd_fltr_guar =
2203 ice_get_num_per_func(hw, val);
2204 val = (reg_val & GLQF_FD_SIZE_FD_BSIZE_M) >>
2205 GLQF_FD_SIZE_FD_BSIZE_S;
2206 func_p->fd_fltr_best_effort = val;
2207 ice_debug(hw, ICE_DBG_INIT,
2208 "%s: num guaranteed FD filters = %d\n",
2209 prefix, func_p->fd_fltr_guar);
2210 ice_debug(hw, ICE_DBG_INIT,
2211 "%s: num best effort FD filters = %d\n",
2212 prefix, func_p->fd_fltr_best_effort);
2216 case ICE_AQC_CAPS_MAX_MTU:
2217 caps->max_mtu = number;
2218 ice_debug(hw, ICE_DBG_INIT, "%s: max MTU = %d\n",
2219 prefix, caps->max_mtu);
2222 ice_debug(hw, ICE_DBG_INIT,
2223 "%s: unknown capability[%d]: 0x%x\n", prefix,
2229 /* Re-calculate capabilities that are dependent on the number of
2230 * physical ports; i.e. some features are not supported or function
2231 * differently on devices with more than 4 ports.
2233 if (caps && (ice_hweight32(caps->valid_functions) > 4)) {
2234 /* Max 4 TCs per port */
2236 ice_debug(hw, ICE_DBG_INIT,
2237 "%s: TC max = %d (based on #ports)\n", prefix,
2243 * ice_aq_discover_caps - query function/device capabilities
2244 * @hw: pointer to the HW struct
2245 * @buf: a virtual buffer to hold the capabilities
2246 * @buf_size: Size of the virtual buffer
2247 * @cap_count: cap count needed if AQ err==ENOMEM
2248 * @opc: capabilities type to discover - pass in the command opcode
2249 * @cd: pointer to command details structure or NULL
2251 * Get the function(0x000a)/device(0x000b) capabilities description from
2254 static enum ice_status
2255 ice_aq_discover_caps(struct ice_hw *hw, void *buf, u16 buf_size, u32 *cap_count,
2256 enum ice_adminq_opc opc, struct ice_sq_cd *cd)
2258 struct ice_aqc_list_caps *cmd;
2259 struct ice_aq_desc desc;
2260 enum ice_status status;
2262 cmd = &desc.params.get_cap;
2264 if (opc != ice_aqc_opc_list_func_caps &&
2265 opc != ice_aqc_opc_list_dev_caps)
2266 return ICE_ERR_PARAM;
2268 ice_fill_dflt_direct_cmd_desc(&desc, opc);
2270 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);
2272 ice_parse_caps(hw, buf, LE32_TO_CPU(cmd->count), opc);
2273 else if (hw->adminq.sq_last_status == ICE_AQ_RC_ENOMEM)
2274 *cap_count = LE32_TO_CPU(cmd->count);
2279 * ice_discover_caps - get info about the HW
2280 * @hw: pointer to the hardware structure
2281 * @opc: capabilities type to discover - pass in the command opcode
2283 static enum ice_status
2284 ice_discover_caps(struct ice_hw *hw, enum ice_adminq_opc opc)
2286 enum ice_status status;
2291 /* The driver doesn't know how many capabilities the device will return
2292 * so the buffer size required isn't known ahead of time. The driver
2293 * starts with cbuf_len and if this turns out to be insufficient, the
2294 * device returns ICE_AQ_RC_ENOMEM and also the cap_count it needs.
2295 * The driver then allocates the buffer based on the count and retries
2296 * the operation. So it follows that the retry count is 2.
2298 #define ICE_GET_CAP_BUF_COUNT 40
2299 #define ICE_GET_CAP_RETRY_COUNT 2
2301 cap_count = ICE_GET_CAP_BUF_COUNT;
2302 retries = ICE_GET_CAP_RETRY_COUNT;
2307 cbuf_len = (u16)(cap_count *
2308 sizeof(struct ice_aqc_list_caps_elem));
2309 cbuf = ice_malloc(hw, cbuf_len);
2311 return ICE_ERR_NO_MEMORY;
2313 status = ice_aq_discover_caps(hw, cbuf, cbuf_len, &cap_count,
2317 if (!status || hw->adminq.sq_last_status != ICE_AQ_RC_ENOMEM)
2320 /* If ENOMEM is returned, try again with bigger buffer */
2321 } while (--retries);
2327 * ice_get_caps - get info about the HW
2328 * @hw: pointer to the hardware structure
2330 enum ice_status ice_get_caps(struct ice_hw *hw)
2332 enum ice_status status;
2334 status = ice_discover_caps(hw, ice_aqc_opc_list_dev_caps);
2336 status = ice_discover_caps(hw, ice_aqc_opc_list_func_caps);
2342 * ice_aq_manage_mac_write - manage MAC address write command
2343 * @hw: pointer to the HW struct
2344 * @mac_addr: MAC address to be written as LAA/LAA+WoL/Port address
2345 * @flags: flags to control write behavior
2346 * @cd: pointer to command details structure or NULL
2348 * This function is used to write MAC address to the NVM (0x0108).
2351 ice_aq_manage_mac_write(struct ice_hw *hw, const u8 *mac_addr, u8 flags,
2352 struct ice_sq_cd *cd)
2354 struct ice_aqc_manage_mac_write *cmd;
2355 struct ice_aq_desc desc;
2357 cmd = &desc.params.mac_write;
2358 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_write);
2363 /* Prep values for flags, sah, sal */
2364 cmd->sah = HTONS(*((const u16 *)mac_addr));
2365 cmd->sal = HTONL(*((const u32 *)(mac_addr + 2)));
2367 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
2371 * ice_aq_clear_pxe_mode
2372 * @hw: pointer to the HW struct
2374 * Tell the firmware that the driver is taking over from PXE (0x0110).
2376 static enum ice_status ice_aq_clear_pxe_mode(struct ice_hw *hw)
2378 struct ice_aq_desc desc;
2380 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pxe_mode);
2381 desc.params.clear_pxe.rx_cnt = ICE_AQC_CLEAR_PXE_RX_CNT;
2383 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
2387 * ice_clear_pxe_mode - clear pxe operations mode
2388 * @hw: pointer to the HW struct
2390 * Make sure all PXE mode settings are cleared, including things
2391 * like descriptor fetch/write-back mode.
2393 void ice_clear_pxe_mode(struct ice_hw *hw)
2395 if (ice_check_sq_alive(hw, &hw->adminq))
2396 ice_aq_clear_pxe_mode(hw);
2401 * ice_get_link_speed_based_on_phy_type - returns link speed
2402 * @phy_type_low: lower part of phy_type
2403 * @phy_type_high: higher part of phy_type
2405 * This helper function will convert an entry in PHY type structure
2406 * [phy_type_low, phy_type_high] to its corresponding link speed.
2407 * Note: In the structure of [phy_type_low, phy_type_high], there should
2408 * be one bit set, as this function will convert one PHY type to its
2410 * If no bit gets set, ICE_LINK_SPEED_UNKNOWN will be returned
2411 * If more than one bit gets set, ICE_LINK_SPEED_UNKNOWN will be returned
2414 ice_get_link_speed_based_on_phy_type(u64 phy_type_low, u64 phy_type_high)
2416 u16 speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN;
2417 u16 speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN;
2419 switch (phy_type_low) {
2420 case ICE_PHY_TYPE_LOW_100BASE_TX:
2421 case ICE_PHY_TYPE_LOW_100M_SGMII:
2422 speed_phy_type_low = ICE_AQ_LINK_SPEED_100MB;
2424 case ICE_PHY_TYPE_LOW_1000BASE_T:
2425 case ICE_PHY_TYPE_LOW_1000BASE_SX:
2426 case ICE_PHY_TYPE_LOW_1000BASE_LX:
2427 case ICE_PHY_TYPE_LOW_1000BASE_KX:
2428 case ICE_PHY_TYPE_LOW_1G_SGMII:
2429 speed_phy_type_low = ICE_AQ_LINK_SPEED_1000MB;
2431 case ICE_PHY_TYPE_LOW_2500BASE_T:
2432 case ICE_PHY_TYPE_LOW_2500BASE_X:
2433 case ICE_PHY_TYPE_LOW_2500BASE_KX:
2434 speed_phy_type_low = ICE_AQ_LINK_SPEED_2500MB;
2436 case ICE_PHY_TYPE_LOW_5GBASE_T:
2437 case ICE_PHY_TYPE_LOW_5GBASE_KR:
2438 speed_phy_type_low = ICE_AQ_LINK_SPEED_5GB;
2440 case ICE_PHY_TYPE_LOW_10GBASE_T:
2441 case ICE_PHY_TYPE_LOW_10G_SFI_DA:
2442 case ICE_PHY_TYPE_LOW_10GBASE_SR:
2443 case ICE_PHY_TYPE_LOW_10GBASE_LR:
2444 case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1:
2445 case ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC:
2446 case ICE_PHY_TYPE_LOW_10G_SFI_C2C:
2447 speed_phy_type_low = ICE_AQ_LINK_SPEED_10GB;
2449 case ICE_PHY_TYPE_LOW_25GBASE_T:
2450 case ICE_PHY_TYPE_LOW_25GBASE_CR:
2451 case ICE_PHY_TYPE_LOW_25GBASE_CR_S:
2452 case ICE_PHY_TYPE_LOW_25GBASE_CR1:
2453 case ICE_PHY_TYPE_LOW_25GBASE_SR:
2454 case ICE_PHY_TYPE_LOW_25GBASE_LR:
2455 case ICE_PHY_TYPE_LOW_25GBASE_KR:
2456 case ICE_PHY_TYPE_LOW_25GBASE_KR_S:
2457 case ICE_PHY_TYPE_LOW_25GBASE_KR1:
2458 case ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC:
2459 case ICE_PHY_TYPE_LOW_25G_AUI_C2C:
2460 speed_phy_type_low = ICE_AQ_LINK_SPEED_25GB;
2462 case ICE_PHY_TYPE_LOW_40GBASE_CR4:
2463 case ICE_PHY_TYPE_LOW_40GBASE_SR4:
2464 case ICE_PHY_TYPE_LOW_40GBASE_LR4:
2465 case ICE_PHY_TYPE_LOW_40GBASE_KR4:
2466 case ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC:
2467 case ICE_PHY_TYPE_LOW_40G_XLAUI:
2468 speed_phy_type_low = ICE_AQ_LINK_SPEED_40GB;
2470 case ICE_PHY_TYPE_LOW_50GBASE_CR2:
2471 case ICE_PHY_TYPE_LOW_50GBASE_SR2:
2472 case ICE_PHY_TYPE_LOW_50GBASE_LR2:
2473 case ICE_PHY_TYPE_LOW_50GBASE_KR2:
2474 case ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC:
2475 case ICE_PHY_TYPE_LOW_50G_LAUI2:
2476 case ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC:
2477 case ICE_PHY_TYPE_LOW_50G_AUI2:
2478 case ICE_PHY_TYPE_LOW_50GBASE_CP:
2479 case ICE_PHY_TYPE_LOW_50GBASE_SR:
2480 case ICE_PHY_TYPE_LOW_50GBASE_FR:
2481 case ICE_PHY_TYPE_LOW_50GBASE_LR:
2482 case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4:
2483 case ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC:
2484 case ICE_PHY_TYPE_LOW_50G_AUI1:
2485 speed_phy_type_low = ICE_AQ_LINK_SPEED_50GB;
2487 case ICE_PHY_TYPE_LOW_100GBASE_CR4:
2488 case ICE_PHY_TYPE_LOW_100GBASE_SR4:
2489 case ICE_PHY_TYPE_LOW_100GBASE_LR4:
2490 case ICE_PHY_TYPE_LOW_100GBASE_KR4:
2491 case ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC:
2492 case ICE_PHY_TYPE_LOW_100G_CAUI4:
2493 case ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC:
2494 case ICE_PHY_TYPE_LOW_100G_AUI4:
2495 case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4:
2496 case ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4:
2497 case ICE_PHY_TYPE_LOW_100GBASE_CP2:
2498 case ICE_PHY_TYPE_LOW_100GBASE_SR2:
2499 case ICE_PHY_TYPE_LOW_100GBASE_DR:
2500 speed_phy_type_low = ICE_AQ_LINK_SPEED_100GB;
2503 speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN;
2507 switch (phy_type_high) {
2508 case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4:
2509 case ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC:
2510 case ICE_PHY_TYPE_HIGH_100G_CAUI2:
2511 case ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC:
2512 case ICE_PHY_TYPE_HIGH_100G_AUI2:
2513 speed_phy_type_high = ICE_AQ_LINK_SPEED_100GB;
2516 speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN;
2520 if (speed_phy_type_low == ICE_AQ_LINK_SPEED_UNKNOWN &&
2521 speed_phy_type_high == ICE_AQ_LINK_SPEED_UNKNOWN)
2522 return ICE_AQ_LINK_SPEED_UNKNOWN;
2523 else if (speed_phy_type_low != ICE_AQ_LINK_SPEED_UNKNOWN &&
2524 speed_phy_type_high != ICE_AQ_LINK_SPEED_UNKNOWN)
2525 return ICE_AQ_LINK_SPEED_UNKNOWN;
2526 else if (speed_phy_type_low != ICE_AQ_LINK_SPEED_UNKNOWN &&
2527 speed_phy_type_high == ICE_AQ_LINK_SPEED_UNKNOWN)
2528 return speed_phy_type_low;
2530 return speed_phy_type_high;
2534 * ice_update_phy_type
2535 * @phy_type_low: pointer to the lower part of phy_type
2536 * @phy_type_high: pointer to the higher part of phy_type
2537 * @link_speeds_bitmap: targeted link speeds bitmap
2539 * Note: For the link_speeds_bitmap structure, you can check it at
2540 * [ice_aqc_get_link_status->link_speed]. Caller can pass in
2541 * link_speeds_bitmap include multiple speeds.
2543 * Each entry in this [phy_type_low, phy_type_high] structure will
2544 * present a certain link speed. This helper function will turn on bits
2545 * in [phy_type_low, phy_type_high] structure based on the value of
2546 * link_speeds_bitmap input parameter.
2549 ice_update_phy_type(u64 *phy_type_low, u64 *phy_type_high,
2550 u16 link_speeds_bitmap)
2557 /* We first check with low part of phy_type */
2558 for (index = 0; index <= ICE_PHY_TYPE_LOW_MAX_INDEX; index++) {
2559 pt_low = BIT_ULL(index);
2560 speed = ice_get_link_speed_based_on_phy_type(pt_low, 0);
2562 if (link_speeds_bitmap & speed)
2563 *phy_type_low |= BIT_ULL(index);
2566 /* We then check with high part of phy_type */
2567 for (index = 0; index <= ICE_PHY_TYPE_HIGH_MAX_INDEX; index++) {
2568 pt_high = BIT_ULL(index);
2569 speed = ice_get_link_speed_based_on_phy_type(0, pt_high);
2571 if (link_speeds_bitmap & speed)
2572 *phy_type_high |= BIT_ULL(index);
2577 * ice_aq_set_phy_cfg
2578 * @hw: pointer to the HW struct
2579 * @pi: port info structure of the interested logical port
2580 * @cfg: structure with PHY configuration data to be set
2581 * @cd: pointer to command details structure or NULL
2583 * Set the various PHY configuration parameters supported on the Port.
2584 * One or more of the Set PHY config parameters may be ignored in an MFP
2585 * mode as the PF may not have the privilege to set some of the PHY Config
2586 * parameters. This status will be indicated by the command response (0x0601).
2589 ice_aq_set_phy_cfg(struct ice_hw *hw, struct ice_port_info *pi,
2590 struct ice_aqc_set_phy_cfg_data *cfg, struct ice_sq_cd *cd)
2592 struct ice_aq_desc desc;
2593 enum ice_status status;
2596 return ICE_ERR_PARAM;
2598 /* Ensure that only valid bits of cfg->caps can be turned on. */
2599 if (cfg->caps & ~ICE_AQ_PHY_ENA_VALID_MASK) {
2600 ice_debug(hw, ICE_DBG_PHY,
2601 "Invalid bit is set in ice_aqc_set_phy_cfg_data->caps : 0x%x\n",
2604 cfg->caps &= ICE_AQ_PHY_ENA_VALID_MASK;
2607 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_phy_cfg);
2608 desc.params.set_phy.lport_num = pi->lport;
2609 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
2611 ice_debug(hw, ICE_DBG_LINK, "phy_type_low = 0x%llx\n",
2612 (unsigned long long)LE64_TO_CPU(cfg->phy_type_low));
2613 ice_debug(hw, ICE_DBG_LINK, "phy_type_high = 0x%llx\n",
2614 (unsigned long long)LE64_TO_CPU(cfg->phy_type_high));
2615 ice_debug(hw, ICE_DBG_LINK, "caps = 0x%x\n", cfg->caps);
2616 ice_debug(hw, ICE_DBG_LINK, "low_power_ctrl = 0x%x\n",
2617 cfg->low_power_ctrl);
2618 ice_debug(hw, ICE_DBG_LINK, "eee_cap = 0x%x\n", cfg->eee_cap);
2619 ice_debug(hw, ICE_DBG_LINK, "eeer_value = 0x%x\n", cfg->eeer_value);
2620 ice_debug(hw, ICE_DBG_LINK, "link_fec_opt = 0x%x\n", cfg->link_fec_opt);
2622 status = ice_aq_send_cmd(hw, &desc, cfg, sizeof(*cfg), cd);
2625 pi->phy.curr_user_phy_cfg = *cfg;
2631 * ice_update_link_info - update status of the HW network link
2632 * @pi: port info structure of the interested logical port
2634 enum ice_status ice_update_link_info(struct ice_port_info *pi)
2636 struct ice_link_status *li;
2637 enum ice_status status;
2640 return ICE_ERR_PARAM;
2642 li = &pi->phy.link_info;
2644 status = ice_aq_get_link_info(pi, true, NULL, NULL);
2648 if (li->link_info & ICE_AQ_MEDIA_AVAILABLE) {
2649 struct ice_aqc_get_phy_caps_data *pcaps;
2653 pcaps = (struct ice_aqc_get_phy_caps_data *)
2654 ice_malloc(hw, sizeof(*pcaps));
2656 return ICE_ERR_NO_MEMORY;
2658 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_TOPO_CAP,
2660 if (status == ICE_SUCCESS)
2661 ice_memcpy(li->module_type, &pcaps->module_type,
2662 sizeof(li->module_type),
2663 ICE_NONDMA_TO_NONDMA);
2665 ice_free(hw, pcaps);
2672 * ice_cache_phy_user_req
2673 * @pi: port information structure
2674 * @cache_data: PHY logging data
2675 * @cache_mode: PHY logging mode
2677 * Log the user request on (FC, FEC, SPEED) for later user.
2680 ice_cache_phy_user_req(struct ice_port_info *pi,
2681 struct ice_phy_cache_mode_data cache_data,
2682 enum ice_phy_cache_mode cache_mode)
2687 switch (cache_mode) {
2689 pi->phy.curr_user_fc_req = cache_data.data.curr_user_fc_req;
2691 case ICE_SPEED_MODE:
2692 pi->phy.curr_user_speed_req =
2693 cache_data.data.curr_user_speed_req;
2696 pi->phy.curr_user_fec_req = cache_data.data.curr_user_fec_req;
2705 * @pi: port information structure
2706 * @aq_failures: pointer to status code, specific to ice_set_fc routine
2707 * @ena_auto_link_update: enable automatic link update
2709 * Set the requested flow control mode.
2712 ice_set_fc(struct ice_port_info *pi, u8 *aq_failures, bool ena_auto_link_update)
2714 struct ice_aqc_set_phy_cfg_data cfg = { 0 };
2715 struct ice_phy_cache_mode_data cache_data;
2716 struct ice_aqc_get_phy_caps_data *pcaps;
2717 enum ice_status status;
2718 u8 pause_mask = 0x0;
2722 return ICE_ERR_PARAM;
2724 *aq_failures = ICE_SET_FC_AQ_FAIL_NONE;
2726 /* Cache user FC request */
2727 cache_data.data.curr_user_fc_req = pi->fc.req_mode;
2728 ice_cache_phy_user_req(pi, cache_data, ICE_FC_MODE);
2730 switch (pi->fc.req_mode) {
2732 pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE;
2733 pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE;
2735 case ICE_FC_RX_PAUSE:
2736 pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE;
2738 case ICE_FC_TX_PAUSE:
2739 pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE;
2745 pcaps = (struct ice_aqc_get_phy_caps_data *)
2746 ice_malloc(hw, sizeof(*pcaps));
2748 return ICE_ERR_NO_MEMORY;
2750 /* Get the current PHY config */
2751 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_SW_CFG, pcaps,
2754 *aq_failures = ICE_SET_FC_AQ_FAIL_GET;
2758 /* clear the old pause settings */
2759 cfg.caps = pcaps->caps & ~(ICE_AQC_PHY_EN_TX_LINK_PAUSE |
2760 ICE_AQC_PHY_EN_RX_LINK_PAUSE);
2762 /* set the new capabilities */
2763 cfg.caps |= pause_mask;
2765 /* If the capabilities have changed, then set the new config */
2766 if (cfg.caps != pcaps->caps) {
2767 int retry_count, retry_max = 10;
2769 /* Auto restart link so settings take effect */
2770 if (ena_auto_link_update)
2771 cfg.caps |= ICE_AQ_PHY_ENA_AUTO_LINK_UPDT;
2772 /* Copy over all the old settings */
2773 cfg.phy_type_high = pcaps->phy_type_high;
2774 cfg.phy_type_low = pcaps->phy_type_low;
2775 cfg.low_power_ctrl = pcaps->low_power_ctrl;
2776 cfg.eee_cap = pcaps->eee_cap;
2777 cfg.eeer_value = pcaps->eeer_value;
2778 cfg.link_fec_opt = pcaps->link_fec_options;
2780 status = ice_aq_set_phy_cfg(hw, pi, &cfg, NULL);
2782 *aq_failures = ICE_SET_FC_AQ_FAIL_SET;
2786 /* Update the link info
2787 * It sometimes takes a really long time for link to
2788 * come back from the atomic reset. Thus, we wait a
2791 for (retry_count = 0; retry_count < retry_max; retry_count++) {
2792 status = ice_update_link_info(pi);
2794 if (status == ICE_SUCCESS)
2797 ice_msec_delay(100, true);
2801 *aq_failures = ICE_SET_FC_AQ_FAIL_UPDATE;
2805 ice_free(hw, pcaps);
2810 * ice_copy_phy_caps_to_cfg - Copy PHY ability data to configuration data
2811 * @caps: PHY ability structure to copy date from
2812 * @cfg: PHY configuration structure to copy data to
2814 * Helper function to copy AQC PHY get ability data to PHY set configuration
2818 ice_copy_phy_caps_to_cfg(struct ice_aqc_get_phy_caps_data *caps,
2819 struct ice_aqc_set_phy_cfg_data *cfg)
2824 cfg->phy_type_low = caps->phy_type_low;
2825 cfg->phy_type_high = caps->phy_type_high;
2826 cfg->caps = caps->caps;
2827 cfg->low_power_ctrl = caps->low_power_ctrl;
2828 cfg->eee_cap = caps->eee_cap;
2829 cfg->eeer_value = caps->eeer_value;
2830 cfg->link_fec_opt = caps->link_fec_options;
2834 * ice_cfg_phy_fec - Configure PHY FEC data based on FEC mode
2835 * @cfg: PHY configuration data to set FEC mode
2836 * @fec: FEC mode to configure
2838 * Caller should copy ice_aqc_get_phy_caps_data.caps ICE_AQC_PHY_EN_AUTO_FEC
2839 * (bit 7) and ice_aqc_get_phy_caps_data.link_fec_options to cfg.caps
2840 * ICE_AQ_PHY_ENA_AUTO_FEC (bit 7) and cfg.link_fec_options before calling.
2843 ice_cfg_phy_fec(struct ice_aqc_set_phy_cfg_data *cfg, enum ice_fec_mode fec)
2847 /* Clear RS bits, and AND BASE-R ability
2848 * bits and OR request bits.
2850 cfg->link_fec_opt &= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN |
2851 ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN;
2852 cfg->link_fec_opt |= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ |
2853 ICE_AQC_PHY_FEC_25G_KR_REQ;
2856 /* Clear BASE-R bits, and AND RS ability
2857 * bits and OR request bits.
2859 cfg->link_fec_opt &= ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN;
2860 cfg->link_fec_opt |= ICE_AQC_PHY_FEC_25G_RS_528_REQ |
2861 ICE_AQC_PHY_FEC_25G_RS_544_REQ;
2864 /* Clear all FEC option bits. */
2865 cfg->link_fec_opt &= ~ICE_AQC_PHY_FEC_MASK;
2868 /* AND auto FEC bit, and all caps bits. */
2869 cfg->caps &= ICE_AQC_PHY_CAPS_MASK;
2875 * ice_get_link_status - get status of the HW network link
2876 * @pi: port information structure
2877 * @link_up: pointer to bool (true/false = linkup/linkdown)
2879 * Variable link_up is true if link is up, false if link is down.
2880 * The variable link_up is invalid if status is non zero. As a
2881 * result of this call, link status reporting becomes enabled
2883 enum ice_status ice_get_link_status(struct ice_port_info *pi, bool *link_up)
2885 struct ice_phy_info *phy_info;
2886 enum ice_status status = ICE_SUCCESS;
2888 if (!pi || !link_up)
2889 return ICE_ERR_PARAM;
2891 phy_info = &pi->phy;
2893 if (phy_info->get_link_info) {
2894 status = ice_update_link_info(pi);
2897 ice_debug(pi->hw, ICE_DBG_LINK,
2898 "get link status error, status = %d\n",
2902 *link_up = phy_info->link_info.link_info & ICE_AQ_LINK_UP;
2908 * ice_aq_set_link_restart_an
2909 * @pi: pointer to the port information structure
2910 * @ena_link: if true: enable link, if false: disable link
2911 * @cd: pointer to command details structure or NULL
2913 * Sets up the link and restarts the Auto-Negotiation over the link.
2916 ice_aq_set_link_restart_an(struct ice_port_info *pi, bool ena_link,
2917 struct ice_sq_cd *cd)
2919 struct ice_aqc_restart_an *cmd;
2920 struct ice_aq_desc desc;
2922 cmd = &desc.params.restart_an;
2924 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_restart_an);
2926 cmd->cmd_flags = ICE_AQC_RESTART_AN_LINK_RESTART;
2927 cmd->lport_num = pi->lport;
2929 cmd->cmd_flags |= ICE_AQC_RESTART_AN_LINK_ENABLE;
2931 cmd->cmd_flags &= ~ICE_AQC_RESTART_AN_LINK_ENABLE;
2933 return ice_aq_send_cmd(pi->hw, &desc, NULL, 0, cd);
2937 * ice_aq_set_event_mask
2938 * @hw: pointer to the HW struct
2939 * @port_num: port number of the physical function
2940 * @mask: event mask to be set
2941 * @cd: pointer to command details structure or NULL
2943 * Set event mask (0x0613)
2946 ice_aq_set_event_mask(struct ice_hw *hw, u8 port_num, u16 mask,
2947 struct ice_sq_cd *cd)
2949 struct ice_aqc_set_event_mask *cmd;
2950 struct ice_aq_desc desc;
2952 cmd = &desc.params.set_event_mask;
2954 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_event_mask);
2956 cmd->lport_num = port_num;
2958 cmd->event_mask = CPU_TO_LE16(mask);
2959 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
2963 * ice_aq_set_mac_loopback
2964 * @hw: pointer to the HW struct
2965 * @ena_lpbk: Enable or Disable loopback
2966 * @cd: pointer to command details structure or NULL
2968 * Enable/disable loopback on a given port
2971 ice_aq_set_mac_loopback(struct ice_hw *hw, bool ena_lpbk, struct ice_sq_cd *cd)
2973 struct ice_aqc_set_mac_lb *cmd;
2974 struct ice_aq_desc desc;
2976 cmd = &desc.params.set_mac_lb;
2978 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_mac_lb);
2980 cmd->lb_mode = ICE_AQ_MAC_LB_EN;
2982 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
2987 * ice_aq_set_port_id_led
2988 * @pi: pointer to the port information
2989 * @is_orig_mode: is this LED set to original mode (by the net-list)
2990 * @cd: pointer to command details structure or NULL
2992 * Set LED value for the given port (0x06e9)
2995 ice_aq_set_port_id_led(struct ice_port_info *pi, bool is_orig_mode,
2996 struct ice_sq_cd *cd)
2998 struct ice_aqc_set_port_id_led *cmd;
2999 struct ice_hw *hw = pi->hw;
3000 struct ice_aq_desc desc;
3002 cmd = &desc.params.set_port_id_led;
3004 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_port_id_led);
3008 cmd->ident_mode = ICE_AQC_PORT_IDENT_LED_ORIG;
3010 cmd->ident_mode = ICE_AQC_PORT_IDENT_LED_BLINK;
3012 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
3016 * __ice_aq_get_set_rss_lut
3017 * @hw: pointer to the hardware structure
3018 * @vsi_id: VSI FW index
3019 * @lut_type: LUT table type
3020 * @lut: pointer to the LUT buffer provided by the caller
3021 * @lut_size: size of the LUT buffer
3022 * @glob_lut_idx: global LUT index
3023 * @set: set true to set the table, false to get the table
3025 * Internal function to get (0x0B05) or set (0x0B03) RSS look up table
3027 static enum ice_status
3028 __ice_aq_get_set_rss_lut(struct ice_hw *hw, u16 vsi_id, u8 lut_type, u8 *lut,
3029 u16 lut_size, u8 glob_lut_idx, bool set)
3031 struct ice_aqc_get_set_rss_lut *cmd_resp;
3032 struct ice_aq_desc desc;
3033 enum ice_status status;
3036 cmd_resp = &desc.params.get_set_rss_lut;
3039 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_rss_lut);
3040 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
3042 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_rss_lut);
3045 cmd_resp->vsi_id = CPU_TO_LE16(((vsi_id <<
3046 ICE_AQC_GSET_RSS_LUT_VSI_ID_S) &
3047 ICE_AQC_GSET_RSS_LUT_VSI_ID_M) |
3048 ICE_AQC_GSET_RSS_LUT_VSI_VALID);
3051 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_VSI:
3052 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF:
3053 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL:
3054 flags |= ((lut_type << ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S) &
3055 ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_M);
3058 status = ICE_ERR_PARAM;
3059 goto ice_aq_get_set_rss_lut_exit;
3062 if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL) {
3063 flags |= ((glob_lut_idx << ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S) &
3064 ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_M);
3067 goto ice_aq_get_set_rss_lut_send;
3068 } else if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF) {
3070 goto ice_aq_get_set_rss_lut_send;
3072 goto ice_aq_get_set_rss_lut_send;
3075 /* LUT size is only valid for Global and PF table types */
3077 case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128:
3078 flags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128_FLAG <<
3079 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) &
3080 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M;
3082 case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512:
3083 flags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512_FLAG <<
3084 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) &
3085 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M;
3087 case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K:
3088 if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF) {
3089 flags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K_FLAG <<
3090 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) &
3091 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M;
3096 status = ICE_ERR_PARAM;
3097 goto ice_aq_get_set_rss_lut_exit;
3100 ice_aq_get_set_rss_lut_send:
3101 cmd_resp->flags = CPU_TO_LE16(flags);
3102 status = ice_aq_send_cmd(hw, &desc, lut, lut_size, NULL);
3104 ice_aq_get_set_rss_lut_exit:
3109 * ice_aq_get_rss_lut
3110 * @hw: pointer to the hardware structure
3111 * @vsi_handle: software VSI handle
3112 * @lut_type: LUT table type
3113 * @lut: pointer to the LUT buffer provided by the caller
3114 * @lut_size: size of the LUT buffer
3116 * get the RSS lookup table, PF or VSI type
3119 ice_aq_get_rss_lut(struct ice_hw *hw, u16 vsi_handle, u8 lut_type,
3120 u8 *lut, u16 lut_size)
3122 if (!ice_is_vsi_valid(hw, vsi_handle) || !lut)
3123 return ICE_ERR_PARAM;
3125 return __ice_aq_get_set_rss_lut(hw, ice_get_hw_vsi_num(hw, vsi_handle),
3126 lut_type, lut, lut_size, 0, false);
3130 * ice_aq_set_rss_lut
3131 * @hw: pointer to the hardware structure
3132 * @vsi_handle: software VSI handle
3133 * @lut_type: LUT table type
3134 * @lut: pointer to the LUT buffer provided by the caller
3135 * @lut_size: size of the LUT buffer
3137 * set the RSS lookup table, PF or VSI type
3140 ice_aq_set_rss_lut(struct ice_hw *hw, u16 vsi_handle, u8 lut_type,
3141 u8 *lut, u16 lut_size)
3143 if (!ice_is_vsi_valid(hw, vsi_handle) || !lut)
3144 return ICE_ERR_PARAM;
3146 return __ice_aq_get_set_rss_lut(hw, ice_get_hw_vsi_num(hw, vsi_handle),
3147 lut_type, lut, lut_size, 0, true);
3151 * __ice_aq_get_set_rss_key
3152 * @hw: pointer to the HW struct
3153 * @vsi_id: VSI FW index
3154 * @key: pointer to key info struct
3155 * @set: set true to set the key, false to get the key
3157 * get (0x0B04) or set (0x0B02) the RSS key per VSI
3160 ice_status __ice_aq_get_set_rss_key(struct ice_hw *hw, u16 vsi_id,
3161 struct ice_aqc_get_set_rss_keys *key,
3164 struct ice_aqc_get_set_rss_key *cmd_resp;
3165 u16 key_size = sizeof(*key);
3166 struct ice_aq_desc desc;
3168 cmd_resp = &desc.params.get_set_rss_key;
3171 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_rss_key);
3172 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
3174 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_rss_key);
3177 cmd_resp->vsi_id = CPU_TO_LE16(((vsi_id <<
3178 ICE_AQC_GSET_RSS_KEY_VSI_ID_S) &
3179 ICE_AQC_GSET_RSS_KEY_VSI_ID_M) |
3180 ICE_AQC_GSET_RSS_KEY_VSI_VALID);
3182 return ice_aq_send_cmd(hw, &desc, key, key_size, NULL);
3186 * ice_aq_get_rss_key
3187 * @hw: pointer to the HW struct
3188 * @vsi_handle: software VSI handle
3189 * @key: pointer to key info struct
3191 * get the RSS key per VSI
3194 ice_aq_get_rss_key(struct ice_hw *hw, u16 vsi_handle,
3195 struct ice_aqc_get_set_rss_keys *key)
3197 if (!ice_is_vsi_valid(hw, vsi_handle) || !key)
3198 return ICE_ERR_PARAM;
3200 return __ice_aq_get_set_rss_key(hw, ice_get_hw_vsi_num(hw, vsi_handle),
3205 * ice_aq_set_rss_key
3206 * @hw: pointer to the HW struct
3207 * @vsi_handle: software VSI handle
3208 * @keys: pointer to key info struct
3210 * set the RSS key per VSI
3213 ice_aq_set_rss_key(struct ice_hw *hw, u16 vsi_handle,
3214 struct ice_aqc_get_set_rss_keys *keys)
3216 if (!ice_is_vsi_valid(hw, vsi_handle) || !keys)
3217 return ICE_ERR_PARAM;
3219 return __ice_aq_get_set_rss_key(hw, ice_get_hw_vsi_num(hw, vsi_handle),
3224 * ice_aq_add_lan_txq
3225 * @hw: pointer to the hardware structure
3226 * @num_qgrps: Number of added queue groups
3227 * @qg_list: list of queue groups to be added
3228 * @buf_size: size of buffer for indirect command
3229 * @cd: pointer to command details structure or NULL
3231 * Add Tx LAN queue (0x0C30)
3234 * Prior to calling add Tx LAN queue:
3235 * Initialize the following as part of the Tx queue context:
3236 * Completion queue ID if the queue uses Completion queue, Quanta profile,
3237 * Cache profile and Packet shaper profile.
3239 * After add Tx LAN queue AQ command is completed:
3240 * Interrupts should be associated with specific queues,
3241 * Association of Tx queue to Doorbell queue is not part of Add LAN Tx queue
3245 ice_aq_add_lan_txq(struct ice_hw *hw, u8 num_qgrps,
3246 struct ice_aqc_add_tx_qgrp *qg_list, u16 buf_size,
3247 struct ice_sq_cd *cd)
3249 u16 i, sum_header_size, sum_q_size = 0;
3250 struct ice_aqc_add_tx_qgrp *list;
3251 struct ice_aqc_add_txqs *cmd;
3252 struct ice_aq_desc desc;
3254 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
3256 cmd = &desc.params.add_txqs;
3258 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_add_txqs);
3261 return ICE_ERR_PARAM;
3263 if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS)
3264 return ICE_ERR_PARAM;
3266 sum_header_size = num_qgrps *
3267 (sizeof(*qg_list) - sizeof(*qg_list->txqs));
3270 for (i = 0; i < num_qgrps; i++) {
3271 struct ice_aqc_add_txqs_perq *q = list->txqs;
3273 sum_q_size += list->num_txqs * sizeof(*q);
3274 list = (struct ice_aqc_add_tx_qgrp *)(q + list->num_txqs);
3277 if (buf_size != (sum_header_size + sum_q_size))
3278 return ICE_ERR_PARAM;
3280 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
3282 cmd->num_qgrps = num_qgrps;
3284 return ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd);
3288 * ice_aq_dis_lan_txq
3289 * @hw: pointer to the hardware structure
3290 * @num_qgrps: number of groups in the list
3291 * @qg_list: the list of groups to disable
3292 * @buf_size: the total size of the qg_list buffer in bytes
3293 * @rst_src: if called due to reset, specifies the reset source
3294 * @vmvf_num: the relative VM or VF number that is undergoing the reset
3295 * @cd: pointer to command details structure or NULL
3297 * Disable LAN Tx queue (0x0C31)
3299 static enum ice_status
3300 ice_aq_dis_lan_txq(struct ice_hw *hw, u8 num_qgrps,
3301 struct ice_aqc_dis_txq_item *qg_list, u16 buf_size,
3302 enum ice_disq_rst_src rst_src, u16 vmvf_num,
3303 struct ice_sq_cd *cd)
3305 struct ice_aqc_dis_txqs *cmd;
3306 struct ice_aq_desc desc;
3307 enum ice_status status;
3310 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
3311 cmd = &desc.params.dis_txqs;
3312 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_dis_txqs);
3314 /* qg_list can be NULL only in VM/VF reset flow */
3315 if (!qg_list && !rst_src)
3316 return ICE_ERR_PARAM;
3318 if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS)
3319 return ICE_ERR_PARAM;
3321 cmd->num_entries = num_qgrps;
3323 cmd->vmvf_and_timeout = CPU_TO_LE16((5 << ICE_AQC_Q_DIS_TIMEOUT_S) &
3324 ICE_AQC_Q_DIS_TIMEOUT_M);
3328 cmd->cmd_type = ICE_AQC_Q_DIS_CMD_VM_RESET;
3329 cmd->vmvf_and_timeout |=
3330 CPU_TO_LE16(vmvf_num & ICE_AQC_Q_DIS_VMVF_NUM_M);
3337 /* flush pipe on time out */
3338 cmd->cmd_type |= ICE_AQC_Q_DIS_CMD_FLUSH_PIPE;
3339 /* If no queue group info, we are in a reset flow. Issue the AQ */
3343 /* set RD bit to indicate that command buffer is provided by the driver
3344 * and it needs to be read by the firmware
3346 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
3348 for (i = 0; i < num_qgrps; ++i) {
3349 /* Calculate the size taken up by the queue IDs in this group */
3350 sz += qg_list[i].num_qs * sizeof(qg_list[i].q_id);
3352 /* Add the size of the group header */
3353 sz += sizeof(qg_list[i]) - sizeof(qg_list[i].q_id);
3355 /* If the num of queues is even, add 2 bytes of padding */
3356 if ((qg_list[i].num_qs % 2) == 0)
3361 return ICE_ERR_PARAM;
3364 status = ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd);
3367 ice_debug(hw, ICE_DBG_SCHED, "VM%d disable failed %d\n",
3368 vmvf_num, hw->adminq.sq_last_status);
3370 ice_debug(hw, ICE_DBG_SCHED, "disable queue %d failed %d\n",
3371 LE16_TO_CPU(qg_list[0].q_id[0]),
3372 hw->adminq.sq_last_status);
3378 /* End of FW Admin Queue command wrappers */
3381 * ice_write_byte - write a byte to a packed context structure
3382 * @src_ctx: the context structure to read from
3383 * @dest_ctx: the context to be written to
3384 * @ce_info: a description of the struct to be filled
3387 ice_write_byte(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)
3389 u8 src_byte, dest_byte, mask;
3393 /* copy from the next struct field */
3394 from = src_ctx + ce_info->offset;
3396 /* prepare the bits and mask */
3397 shift_width = ce_info->lsb % 8;
3398 mask = (u8)(BIT(ce_info->width) - 1);
3403 /* shift to correct alignment */
3404 mask <<= shift_width;
3405 src_byte <<= shift_width;
3407 /* get the current bits from the target bit string */
3408 dest = dest_ctx + (ce_info->lsb / 8);
3410 ice_memcpy(&dest_byte, dest, sizeof(dest_byte), ICE_DMA_TO_NONDMA);
3412 dest_byte &= ~mask; /* get the bits not changing */
3413 dest_byte |= src_byte; /* add in the new bits */
3415 /* put it all back */
3416 ice_memcpy(dest, &dest_byte, sizeof(dest_byte), ICE_NONDMA_TO_DMA);
3420 * ice_write_word - write a word to a packed context structure
3421 * @src_ctx: the context structure to read from
3422 * @dest_ctx: the context to be written to
3423 * @ce_info: a description of the struct to be filled
3426 ice_write_word(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)
3433 /* copy from the next struct field */
3434 from = src_ctx + ce_info->offset;
3436 /* prepare the bits and mask */
3437 shift_width = ce_info->lsb % 8;
3438 mask = BIT(ce_info->width) - 1;
3440 /* don't swizzle the bits until after the mask because the mask bits
3441 * will be in a different bit position on big endian machines
3443 src_word = *(u16 *)from;
3446 /* shift to correct alignment */
3447 mask <<= shift_width;
3448 src_word <<= shift_width;
3450 /* get the current bits from the target bit string */
3451 dest = dest_ctx + (ce_info->lsb / 8);
3453 ice_memcpy(&dest_word, dest, sizeof(dest_word), ICE_DMA_TO_NONDMA);
3455 dest_word &= ~(CPU_TO_LE16(mask)); /* get the bits not changing */
3456 dest_word |= CPU_TO_LE16(src_word); /* add in the new bits */
3458 /* put it all back */
3459 ice_memcpy(dest, &dest_word, sizeof(dest_word), ICE_NONDMA_TO_DMA);
3463 * ice_write_dword - write a dword to a packed context structure
3464 * @src_ctx: the context structure to read from
3465 * @dest_ctx: the context to be written to
3466 * @ce_info: a description of the struct to be filled
3469 ice_write_dword(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)
3471 u32 src_dword, mask;
3476 /* copy from the next struct field */
3477 from = src_ctx + ce_info->offset;
3479 /* prepare the bits and mask */
3480 shift_width = ce_info->lsb % 8;
3482 /* if the field width is exactly 32 on an x86 machine, then the shift
3483 * operation will not work because the SHL instructions count is masked
3484 * to 5 bits so the shift will do nothing
3486 if (ce_info->width < 32)
3487 mask = BIT(ce_info->width) - 1;
3491 /* don't swizzle the bits until after the mask because the mask bits
3492 * will be in a different bit position on big endian machines
3494 src_dword = *(u32 *)from;
3497 /* shift to correct alignment */
3498 mask <<= shift_width;
3499 src_dword <<= shift_width;
3501 /* get the current bits from the target bit string */
3502 dest = dest_ctx + (ce_info->lsb / 8);
3504 ice_memcpy(&dest_dword, dest, sizeof(dest_dword), ICE_DMA_TO_NONDMA);
3506 dest_dword &= ~(CPU_TO_LE32(mask)); /* get the bits not changing */
3507 dest_dword |= CPU_TO_LE32(src_dword); /* add in the new bits */
3509 /* put it all back */
3510 ice_memcpy(dest, &dest_dword, sizeof(dest_dword), ICE_NONDMA_TO_DMA);
3514 * ice_write_qword - write a qword to a packed context structure
3515 * @src_ctx: the context structure to read from
3516 * @dest_ctx: the context to be written to
3517 * @ce_info: a description of the struct to be filled
3520 ice_write_qword(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)
3522 u64 src_qword, mask;
3527 /* copy from the next struct field */
3528 from = src_ctx + ce_info->offset;
3530 /* prepare the bits and mask */
3531 shift_width = ce_info->lsb % 8;
3533 /* if the field width is exactly 64 on an x86 machine, then the shift
3534 * operation will not work because the SHL instructions count is masked
3535 * to 6 bits so the shift will do nothing
3537 if (ce_info->width < 64)
3538 mask = BIT_ULL(ce_info->width) - 1;
3542 /* don't swizzle the bits until after the mask because the mask bits
3543 * will be in a different bit position on big endian machines
3545 src_qword = *(u64 *)from;
3548 /* shift to correct alignment */
3549 mask <<= shift_width;
3550 src_qword <<= shift_width;
3552 /* get the current bits from the target bit string */
3553 dest = dest_ctx + (ce_info->lsb / 8);
3555 ice_memcpy(&dest_qword, dest, sizeof(dest_qword), ICE_DMA_TO_NONDMA);
3557 dest_qword &= ~(CPU_TO_LE64(mask)); /* get the bits not changing */
3558 dest_qword |= CPU_TO_LE64(src_qword); /* add in the new bits */
3560 /* put it all back */
3561 ice_memcpy(dest, &dest_qword, sizeof(dest_qword), ICE_NONDMA_TO_DMA);
3565 * ice_set_ctx - set context bits in packed structure
3566 * @src_ctx: pointer to a generic non-packed context structure
3567 * @dest_ctx: pointer to memory for the packed structure
3568 * @ce_info: a description of the structure to be transformed
3571 ice_set_ctx(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)
3575 for (f = 0; ce_info[f].width; f++) {
3576 /* We have to deal with each element of the FW response
3577 * using the correct size so that we are correct regardless
3578 * of the endianness of the machine.
3580 switch (ce_info[f].size_of) {
3582 ice_write_byte(src_ctx, dest_ctx, &ce_info[f]);
3585 ice_write_word(src_ctx, dest_ctx, &ce_info[f]);
3588 ice_write_dword(src_ctx, dest_ctx, &ce_info[f]);
3591 ice_write_qword(src_ctx, dest_ctx, &ce_info[f]);
3594 return ICE_ERR_INVAL_SIZE;
3605 * ice_read_byte - read context byte into struct
3606 * @src_ctx: the context structure to read from
3607 * @dest_ctx: the context to be written to
3608 * @ce_info: a description of the struct to be filled
3611 ice_read_byte(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info)
3617 /* prepare the bits and mask */
3618 shift_width = ce_info->lsb % 8;
3619 mask = (u8)(BIT(ce_info->width) - 1);
3621 /* shift to correct alignment */
3622 mask <<= shift_width;
3624 /* get the current bits from the src bit string */
3625 src = src_ctx + (ce_info->lsb / 8);
3627 ice_memcpy(&dest_byte, src, sizeof(dest_byte), ICE_DMA_TO_NONDMA);
3629 dest_byte &= ~(mask);
3631 dest_byte >>= shift_width;
3633 /* get the address from the struct field */
3634 target = dest_ctx + ce_info->offset;
3636 /* put it back in the struct */
3637 ice_memcpy(target, &dest_byte, sizeof(dest_byte), ICE_NONDMA_TO_DMA);
3641 * ice_read_word - read context word into struct
3642 * @src_ctx: the context structure to read from
3643 * @dest_ctx: the context to be written to
3644 * @ce_info: a description of the struct to be filled
3647 ice_read_word(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info)
3649 u16 dest_word, mask;
3654 /* prepare the bits and mask */
3655 shift_width = ce_info->lsb % 8;
3656 mask = BIT(ce_info->width) - 1;
3658 /* shift to correct alignment */
3659 mask <<= shift_width;
3661 /* get the current bits from the src bit string */
3662 src = src_ctx + (ce_info->lsb / 8);
3664 ice_memcpy(&src_word, src, sizeof(src_word), ICE_DMA_TO_NONDMA);
3666 /* the data in the memory is stored as little endian so mask it
3669 src_word &= ~(CPU_TO_LE16(mask));
3671 /* get the data back into host order before shifting */
3672 dest_word = LE16_TO_CPU(src_word);
3674 dest_word >>= shift_width;
3676 /* get the address from the struct field */
3677 target = dest_ctx + ce_info->offset;
3679 /* put it back in the struct */
3680 ice_memcpy(target, &dest_word, sizeof(dest_word), ICE_NONDMA_TO_DMA);
3684 * ice_read_dword - read context dword into struct
3685 * @src_ctx: the context structure to read from
3686 * @dest_ctx: the context to be written to
3687 * @ce_info: a description of the struct to be filled
3690 ice_read_dword(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info)
3692 u32 dest_dword, mask;
3697 /* prepare the bits and mask */
3698 shift_width = ce_info->lsb % 8;
3700 /* if the field width is exactly 32 on an x86 machine, then the shift
3701 * operation will not work because the SHL instructions count is masked
3702 * to 5 bits so the shift will do nothing
3704 if (ce_info->width < 32)
3705 mask = BIT(ce_info->width) - 1;
3709 /* shift to correct alignment */
3710 mask <<= shift_width;
3712 /* get the current bits from the src bit string */
3713 src = src_ctx + (ce_info->lsb / 8);
3715 ice_memcpy(&src_dword, src, sizeof(src_dword), ICE_DMA_TO_NONDMA);
3717 /* the data in the memory is stored as little endian so mask it
3720 src_dword &= ~(CPU_TO_LE32(mask));
3722 /* get the data back into host order before shifting */
3723 dest_dword = LE32_TO_CPU(src_dword);
3725 dest_dword >>= shift_width;
3727 /* get the address from the struct field */
3728 target = dest_ctx + ce_info->offset;
3730 /* put it back in the struct */
3731 ice_memcpy(target, &dest_dword, sizeof(dest_dword), ICE_NONDMA_TO_DMA);
3735 * ice_read_qword - read context qword into struct
3736 * @src_ctx: the context structure to read from
3737 * @dest_ctx: the context to be written to
3738 * @ce_info: a description of the struct to be filled
3741 ice_read_qword(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info)
3743 u64 dest_qword, mask;
3748 /* prepare the bits and mask */
3749 shift_width = ce_info->lsb % 8;
3751 /* if the field width is exactly 64 on an x86 machine, then the shift
3752 * operation will not work because the SHL instructions count is masked
3753 * to 6 bits so the shift will do nothing
3755 if (ce_info->width < 64)
3756 mask = BIT_ULL(ce_info->width) - 1;
3760 /* shift to correct alignment */
3761 mask <<= shift_width;
3763 /* get the current bits from the src bit string */
3764 src = src_ctx + (ce_info->lsb / 8);
3766 ice_memcpy(&src_qword, src, sizeof(src_qword), ICE_DMA_TO_NONDMA);
3768 /* the data in the memory is stored as little endian so mask it
3771 src_qword &= ~(CPU_TO_LE64(mask));
3773 /* get the data back into host order before shifting */
3774 dest_qword = LE64_TO_CPU(src_qword);
3776 dest_qword >>= shift_width;
3778 /* get the address from the struct field */
3779 target = dest_ctx + ce_info->offset;
3781 /* put it back in the struct */
3782 ice_memcpy(target, &dest_qword, sizeof(dest_qword), ICE_NONDMA_TO_DMA);
3786 * ice_get_ctx - extract context bits from a packed structure
3787 * @src_ctx: pointer to a generic packed context structure
3788 * @dest_ctx: pointer to a generic non-packed context structure
3789 * @ce_info: a description of the structure to be read from
3792 ice_get_ctx(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info)
3796 for (f = 0; ce_info[f].width; f++) {
3797 switch (ce_info[f].size_of) {
3799 ice_read_byte(src_ctx, dest_ctx, &ce_info[f]);
3802 ice_read_word(src_ctx, dest_ctx, &ce_info[f]);
3805 ice_read_dword(src_ctx, dest_ctx, &ce_info[f]);
3808 ice_read_qword(src_ctx, dest_ctx, &ce_info[f]);
3811 /* nothing to do, just keep going */
3820 * ice_get_lan_q_ctx - get the LAN queue context for the given VSI and TC
3821 * @hw: pointer to the HW struct
3822 * @vsi_handle: software VSI handle
3824 * @q_handle: software queue handle
3827 ice_get_lan_q_ctx(struct ice_hw *hw, u16 vsi_handle, u8 tc, u16 q_handle)
3829 struct ice_vsi_ctx *vsi;
3830 struct ice_q_ctx *q_ctx;
3832 vsi = ice_get_vsi_ctx(hw, vsi_handle);
3835 if (q_handle >= vsi->num_lan_q_entries[tc])
3837 if (!vsi->lan_q_ctx[tc])
3839 q_ctx = vsi->lan_q_ctx[tc];
3840 return &q_ctx[q_handle];
3845 * @pi: port information structure
3846 * @vsi_handle: software VSI handle
3848 * @q_handle: software queue handle
3849 * @num_qgrps: Number of added queue groups
3850 * @buf: list of queue groups to be added
3851 * @buf_size: size of buffer for indirect command
3852 * @cd: pointer to command details structure or NULL
3854 * This function adds one LAN queue
3857 ice_ena_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u16 q_handle,
3858 u8 num_qgrps, struct ice_aqc_add_tx_qgrp *buf, u16 buf_size,
3859 struct ice_sq_cd *cd)
3861 struct ice_aqc_txsched_elem_data node = { 0 };
3862 struct ice_sched_node *parent;
3863 struct ice_q_ctx *q_ctx;
3864 enum ice_status status;
3867 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY)
3870 if (num_qgrps > 1 || buf->num_txqs > 1)
3871 return ICE_ERR_MAX_LIMIT;
3875 if (!ice_is_vsi_valid(hw, vsi_handle))
3876 return ICE_ERR_PARAM;
3878 ice_acquire_lock(&pi->sched_lock);
3880 q_ctx = ice_get_lan_q_ctx(hw, vsi_handle, tc, q_handle);
3882 ice_debug(hw, ICE_DBG_SCHED, "Enaq: invalid queue handle %d\n",
3884 status = ICE_ERR_PARAM;
3888 /* find a parent node */
3889 parent = ice_sched_get_free_qparent(pi, vsi_handle, tc,
3890 ICE_SCHED_NODE_OWNER_LAN);
3892 status = ICE_ERR_PARAM;
3896 buf->parent_teid = parent->info.node_teid;
3897 node.parent_teid = parent->info.node_teid;
3898 /* Mark that the values in the "generic" section as valid. The default
3899 * value in the "generic" section is zero. This means that :
3900 * - Scheduling mode is Bytes Per Second (BPS), indicated by Bit 0.
3901 * - 0 priority among siblings, indicated by Bit 1-3.
3902 * - WFQ, indicated by Bit 4.
3903 * - 0 Adjustment value is used in PSM credit update flow, indicated by
3905 * - Bit 7 is reserved.
3906 * Without setting the generic section as valid in valid_sections, the
3907 * Admin queue command will fail with error code ICE_AQ_RC_EINVAL.
3909 buf->txqs[0].info.valid_sections = ICE_AQC_ELEM_VALID_GENERIC;
3911 /* add the LAN queue */
3912 status = ice_aq_add_lan_txq(hw, num_qgrps, buf, buf_size, cd);
3913 if (status != ICE_SUCCESS) {
3914 ice_debug(hw, ICE_DBG_SCHED, "enable queue %d failed %d\n",
3915 LE16_TO_CPU(buf->txqs[0].txq_id),
3916 hw->adminq.sq_last_status);
3920 node.node_teid = buf->txqs[0].q_teid;
3921 node.data.elem_type = ICE_AQC_ELEM_TYPE_LEAF;
3922 q_ctx->q_handle = q_handle;
3923 q_ctx->q_teid = LE32_TO_CPU(node.node_teid);
3925 /* add a leaf node into scheduler tree queue layer */
3926 status = ice_sched_add_node(pi, hw->num_tx_sched_layers - 1, &node);
3928 status = ice_sched_replay_q_bw(pi, q_ctx);
3931 ice_release_lock(&pi->sched_lock);
3937 * @pi: port information structure
3938 * @vsi_handle: software VSI handle
3940 * @num_queues: number of queues
3941 * @q_handles: pointer to software queue handle array
3942 * @q_ids: pointer to the q_id array
3943 * @q_teids: pointer to queue node teids
3944 * @rst_src: if called due to reset, specifies the reset source
3945 * @vmvf_num: the relative VM or VF number that is undergoing the reset
3946 * @cd: pointer to command details structure or NULL
3948 * This function removes queues and their corresponding nodes in SW DB
3951 ice_dis_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u8 num_queues,
3952 u16 *q_handles, u16 *q_ids, u32 *q_teids,
3953 enum ice_disq_rst_src rst_src, u16 vmvf_num,
3954 struct ice_sq_cd *cd)
3956 enum ice_status status = ICE_ERR_DOES_NOT_EXIST;
3957 struct ice_aqc_dis_txq_item qg_list;
3958 struct ice_q_ctx *q_ctx;
3961 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY)
3965 /* if queue is disabled already yet the disable queue command
3966 * has to be sent to complete the VF reset, then call
3967 * ice_aq_dis_lan_txq without any queue information
3970 return ice_aq_dis_lan_txq(pi->hw, 0, NULL, 0, rst_src,
3975 ice_acquire_lock(&pi->sched_lock);
3977 for (i = 0; i < num_queues; i++) {
3978 struct ice_sched_node *node;
3980 node = ice_sched_find_node_by_teid(pi->root, q_teids[i]);
3983 q_ctx = ice_get_lan_q_ctx(pi->hw, vsi_handle, tc, q_handles[i]);
3985 ice_debug(pi->hw, ICE_DBG_SCHED, "invalid queue handle%d\n",
3989 if (q_ctx->q_handle != q_handles[i]) {
3990 ice_debug(pi->hw, ICE_DBG_SCHED, "Err:handles %d %d\n",
3991 q_ctx->q_handle, q_handles[i]);
3994 qg_list.parent_teid = node->info.parent_teid;
3996 qg_list.q_id[0] = CPU_TO_LE16(q_ids[i]);
3997 status = ice_aq_dis_lan_txq(pi->hw, 1, &qg_list,
3998 sizeof(qg_list), rst_src, vmvf_num,
4001 if (status != ICE_SUCCESS)
4003 ice_free_sched_node(pi, node);
4004 q_ctx->q_handle = ICE_INVAL_Q_HANDLE;
4006 ice_release_lock(&pi->sched_lock);
4011 * ice_cfg_vsi_qs - configure the new/existing VSI queues
4012 * @pi: port information structure
4013 * @vsi_handle: software VSI handle
4014 * @tc_bitmap: TC bitmap
4015 * @maxqs: max queues array per TC
4016 * @owner: LAN or RDMA
4018 * This function adds/updates the VSI queues per TC.
4020 static enum ice_status
4021 ice_cfg_vsi_qs(struct ice_port_info *pi, u16 vsi_handle, u8 tc_bitmap,
4022 u16 *maxqs, u8 owner)
4024 enum ice_status status = ICE_SUCCESS;
4027 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY)
4030 if (!ice_is_vsi_valid(pi->hw, vsi_handle))
4031 return ICE_ERR_PARAM;
4033 ice_acquire_lock(&pi->sched_lock);
4035 ice_for_each_traffic_class(i) {
4036 /* configuration is possible only if TC node is present */
4037 if (!ice_sched_get_tc_node(pi, i))
4040 status = ice_sched_cfg_vsi(pi, vsi_handle, i, maxqs[i], owner,
4041 ice_is_tc_ena(tc_bitmap, i));
4046 ice_release_lock(&pi->sched_lock);
4051 * ice_cfg_vsi_lan - configure VSI LAN queues
4052 * @pi: port information structure
4053 * @vsi_handle: software VSI handle
4054 * @tc_bitmap: TC bitmap
4055 * @max_lanqs: max LAN queues array per TC
4057 * This function adds/updates the VSI LAN queues per TC.
4060 ice_cfg_vsi_lan(struct ice_port_info *pi, u16 vsi_handle, u8 tc_bitmap,
4063 return ice_cfg_vsi_qs(pi, vsi_handle, tc_bitmap, max_lanqs,
4064 ICE_SCHED_NODE_OWNER_LAN);
4070 * ice_replay_pre_init - replay pre initialization
4071 * @hw: pointer to the HW struct
4073 * Initializes required config data for VSI, FD, ACL, and RSS before replay.
4075 static enum ice_status ice_replay_pre_init(struct ice_hw *hw)
4077 struct ice_switch_info *sw = hw->switch_info;
4080 /* Delete old entries from replay filter list head if there is any */
4081 ice_rm_all_sw_replay_rule_info(hw);
4082 /* In start of replay, move entries into replay_rules list, it
4083 * will allow adding rules entries back to filt_rules list,
4084 * which is operational list.
4086 for (i = 0; i < ICE_MAX_NUM_RECIPES; i++)
4087 LIST_REPLACE_INIT(&sw->recp_list[i].filt_rules,
4088 &sw->recp_list[i].filt_replay_rules);
4089 ice_sched_replay_agg_vsi_preinit(hw);
4091 return ice_sched_replay_tc_node_bw(hw);
4095 * ice_replay_vsi - replay VSI configuration
4096 * @hw: pointer to the HW struct
4097 * @vsi_handle: driver VSI handle
4099 * Restore all VSI configuration after reset. It is required to call this
4100 * function with main VSI first.
4102 enum ice_status ice_replay_vsi(struct ice_hw *hw, u16 vsi_handle)
4104 enum ice_status status;
4106 if (!ice_is_vsi_valid(hw, vsi_handle))
4107 return ICE_ERR_PARAM;
4109 /* Replay pre-initialization if there is any */
4110 if (vsi_handle == ICE_MAIN_VSI_HANDLE) {
4111 status = ice_replay_pre_init(hw);
4115 /* Replay per VSI all RSS configurations */
4116 status = ice_replay_rss_cfg(hw, vsi_handle);
4119 /* Replay per VSI all filters */
4120 status = ice_replay_vsi_all_fltr(hw, vsi_handle);
4122 status = ice_replay_vsi_agg(hw, vsi_handle);
4127 * ice_replay_post - post replay configuration cleanup
4128 * @hw: pointer to the HW struct
4130 * Post replay cleanup.
4132 void ice_replay_post(struct ice_hw *hw)
4134 /* Delete old entries from replay filter list head */
4135 ice_rm_all_sw_replay_rule_info(hw);
4136 ice_sched_replay_agg(hw);
4140 * ice_stat_update40 - read 40 bit stat from the chip and update stat values
4141 * @hw: ptr to the hardware info
4142 * @reg: offset of 64 bit HW register to read from
4143 * @prev_stat_loaded: bool to specify if previous stats are loaded
4144 * @prev_stat: ptr to previous loaded stat value
4145 * @cur_stat: ptr to current stat value
4148 ice_stat_update40(struct ice_hw *hw, u32 reg, bool prev_stat_loaded,
4149 u64 *prev_stat, u64 *cur_stat)
4151 u64 new_data = rd64(hw, reg) & (BIT_ULL(40) - 1);
4153 /* device stats are not reset at PFR, they likely will not be zeroed
4154 * when the driver starts. Thus, save the value from the first read
4155 * without adding to the statistic value so that we report stats which
4156 * count up from zero.
4158 if (!prev_stat_loaded) {
4159 *prev_stat = new_data;
4163 /* Calculate the difference between the new and old values, and then
4164 * add it to the software stat value.
4166 if (new_data >= *prev_stat)
4167 *cur_stat += new_data - *prev_stat;
4169 /* to manage the potential roll-over */
4170 *cur_stat += (new_data + BIT_ULL(40)) - *prev_stat;
4172 /* Update the previously stored value to prepare for next read */
4173 *prev_stat = new_data;
4177 * ice_stat_update32 - read 32 bit stat from the chip and update stat values
4178 * @hw: ptr to the hardware info
4179 * @reg: offset of HW register to read from
4180 * @prev_stat_loaded: bool to specify if previous stats are loaded
4181 * @prev_stat: ptr to previous loaded stat value
4182 * @cur_stat: ptr to current stat value
4185 ice_stat_update32(struct ice_hw *hw, u32 reg, bool prev_stat_loaded,
4186 u64 *prev_stat, u64 *cur_stat)
4190 new_data = rd32(hw, reg);
4192 /* device stats are not reset at PFR, they likely will not be zeroed
4193 * when the driver starts. Thus, save the value from the first read
4194 * without adding to the statistic value so that we report stats which
4195 * count up from zero.
4197 if (!prev_stat_loaded) {
4198 *prev_stat = new_data;
4202 /* Calculate the difference between the new and old values, and then
4203 * add it to the software stat value.
4205 if (new_data >= *prev_stat)
4206 *cur_stat += new_data - *prev_stat;
4208 /* to manage the potential roll-over */
4209 *cur_stat += (new_data + BIT_ULL(32)) - *prev_stat;
4211 /* Update the previously stored value to prepare for next read */
4212 *prev_stat = new_data;
4217 * ice_sched_query_elem - query element information from HW
4218 * @hw: pointer to the HW struct
4219 * @node_teid: node TEID to be queried
4220 * @buf: buffer to element information
4222 * This function queries HW element information
4225 ice_sched_query_elem(struct ice_hw *hw, u32 node_teid,
4226 struct ice_aqc_get_elem *buf)
4228 u16 buf_size, num_elem_ret = 0;
4229 enum ice_status status;
4231 buf_size = sizeof(*buf);
4232 ice_memset(buf, 0, buf_size, ICE_NONDMA_MEM);
4233 buf->generic[0].node_teid = CPU_TO_LE32(node_teid);
4234 status = ice_aq_query_sched_elems(hw, 1, buf, buf_size, &num_elem_ret,
4236 if (status != ICE_SUCCESS || num_elem_ret != 1)
4237 ice_debug(hw, ICE_DBG_SCHED, "query element failed\n");
4242 * ice_get_fw_mode - returns FW mode
4243 * @hw: pointer to the HW struct
4245 enum ice_fw_modes ice_get_fw_mode(struct ice_hw *hw)
4247 #define ICE_FW_MODE_DBG_M BIT(0)
4248 #define ICE_FW_MODE_REC_M BIT(1)
4249 #define ICE_FW_MODE_ROLLBACK_M BIT(2)
4252 /* check the current FW mode */
4253 fw_mode = rd32(hw, GL_MNG_FWSM) & GL_MNG_FWSM_FW_MODES_M;
4255 if (fw_mode & ICE_FW_MODE_DBG_M)
4256 return ICE_FW_MODE_DBG;
4257 else if (fw_mode & ICE_FW_MODE_REC_M)
4258 return ICE_FW_MODE_REC;
4259 else if (fw_mode & ICE_FW_MODE_ROLLBACK_M)
4260 return ICE_FW_MODE_ROLLBACK;
4262 return ICE_FW_MODE_NORMAL;