1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2001-2020 Intel Corporation
5 #include "ice_common.h"
7 #include "ice_adminq_cmd.h"
10 #include "ice_switch.h"
12 #define ICE_PF_RESET_WAIT_COUNT 300
15 * ice_set_mac_type - Sets MAC type
16 * @hw: pointer to the HW structure
18 * This function sets the MAC type of the adapter based on the
19 * vendor ID and device ID stored in the HW structure.
21 static enum ice_status ice_set_mac_type(struct ice_hw *hw)
23 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
25 if (hw->vendor_id != ICE_INTEL_VENDOR_ID)
26 return ICE_ERR_DEVICE_NOT_SUPPORTED;
28 switch (hw->device_id) {
29 case ICE_DEV_ID_E810C_BACKPLANE:
30 case ICE_DEV_ID_E810C_QSFP:
31 case ICE_DEV_ID_E810C_SFP:
32 case ICE_DEV_ID_E810_XXV_BACKPLANE:
33 case ICE_DEV_ID_E810_XXV_QSFP:
34 case ICE_DEV_ID_E810_XXV_SFP:
35 hw->mac_type = ICE_MAC_E810;
37 case ICE_DEV_ID_E822C_10G_BASE_T:
38 case ICE_DEV_ID_E822C_BACKPLANE:
39 case ICE_DEV_ID_E822C_QSFP:
40 case ICE_DEV_ID_E822C_SFP:
41 case ICE_DEV_ID_E822C_SGMII:
42 case ICE_DEV_ID_E822L_10G_BASE_T:
43 case ICE_DEV_ID_E822L_BACKPLANE:
44 case ICE_DEV_ID_E822L_SFP:
45 case ICE_DEV_ID_E822L_SGMII:
46 case ICE_DEV_ID_E823L_10G_BASE_T:
47 case ICE_DEV_ID_E823L_1GBE:
48 case ICE_DEV_ID_E823L_BACKPLANE:
49 case ICE_DEV_ID_E823L_QSFP:
50 case ICE_DEV_ID_E823L_SFP:
51 hw->mac_type = ICE_MAC_GENERIC;
54 hw->mac_type = ICE_MAC_UNKNOWN;
58 ice_debug(hw, ICE_DBG_INIT, "mac_type: %d\n", hw->mac_type);
63 * ice_clear_pf_cfg - Clear PF configuration
64 * @hw: pointer to the hardware structure
66 * Clears any existing PF configuration (VSIs, VSI lists, switch rules, port
67 * configuration, flow director filters, etc.).
69 enum ice_status ice_clear_pf_cfg(struct ice_hw *hw)
71 struct ice_aq_desc desc;
73 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pf_cfg);
75 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
79 * ice_aq_manage_mac_read - manage MAC address read command
80 * @hw: pointer to the HW struct
81 * @buf: a virtual buffer to hold the manage MAC read response
82 * @buf_size: Size of the virtual buffer
83 * @cd: pointer to command details structure or NULL
85 * This function is used to return per PF station MAC address (0x0107).
86 * NOTE: Upon successful completion of this command, MAC address information
87 * is returned in user specified buffer. Please interpret user specified
88 * buffer as "manage_mac_read" response.
89 * Response such as various MAC addresses are stored in HW struct (port.mac)
90 * ice_discover_dev_caps is expected to be called before this function is
93 static enum ice_status
94 ice_aq_manage_mac_read(struct ice_hw *hw, void *buf, u16 buf_size,
97 struct ice_aqc_manage_mac_read_resp *resp;
98 struct ice_aqc_manage_mac_read *cmd;
99 struct ice_aq_desc desc;
100 enum ice_status status;
104 cmd = &desc.params.mac_read;
106 if (buf_size < sizeof(*resp))
107 return ICE_ERR_BUF_TOO_SHORT;
109 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_read);
111 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);
115 resp = (struct ice_aqc_manage_mac_read_resp *)buf;
116 flags = LE16_TO_CPU(cmd->flags) & ICE_AQC_MAN_MAC_READ_M;
118 if (!(flags & ICE_AQC_MAN_MAC_LAN_ADDR_VALID)) {
119 ice_debug(hw, ICE_DBG_LAN, "got invalid MAC address\n");
123 /* A single port can report up to two (LAN and WoL) addresses */
124 for (i = 0; i < cmd->num_addr; i++)
125 if (resp[i].addr_type == ICE_AQC_MAN_MAC_ADDR_TYPE_LAN) {
126 ice_memcpy(hw->port_info->mac.lan_addr,
127 resp[i].mac_addr, ETH_ALEN,
129 ice_memcpy(hw->port_info->mac.perm_addr,
131 ETH_ALEN, ICE_DMA_TO_NONDMA);
138 * ice_aq_get_phy_caps - returns PHY capabilities
139 * @pi: port information structure
140 * @qual_mods: report qualified modules
141 * @report_mode: report mode capabilities
142 * @pcaps: structure for PHY capabilities to be filled
143 * @cd: pointer to command details structure or NULL
145 * Returns the various PHY capabilities supported on the Port (0x0600)
148 ice_aq_get_phy_caps(struct ice_port_info *pi, bool qual_mods, u8 report_mode,
149 struct ice_aqc_get_phy_caps_data *pcaps,
150 struct ice_sq_cd *cd)
152 struct ice_aqc_get_phy_caps *cmd;
153 u16 pcaps_size = sizeof(*pcaps);
154 struct ice_aq_desc desc;
155 enum ice_status status;
158 cmd = &desc.params.get_phy;
160 if (!pcaps || (report_mode & ~ICE_AQC_REPORT_MODE_M) || !pi)
161 return ICE_ERR_PARAM;
164 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_phy_caps);
167 cmd->param0 |= CPU_TO_LE16(ICE_AQC_GET_PHY_RQM);
169 cmd->param0 |= CPU_TO_LE16(report_mode);
170 status = ice_aq_send_cmd(hw, &desc, pcaps, pcaps_size, cd);
172 ice_debug(hw, ICE_DBG_LINK, "get phy caps - report_mode = 0x%x\n",
174 ice_debug(hw, ICE_DBG_LINK, " phy_type_low = 0x%llx\n",
175 (unsigned long long)LE64_TO_CPU(pcaps->phy_type_low));
176 ice_debug(hw, ICE_DBG_LINK, " phy_type_high = 0x%llx\n",
177 (unsigned long long)LE64_TO_CPU(pcaps->phy_type_high));
178 ice_debug(hw, ICE_DBG_LINK, " caps = 0x%x\n", pcaps->caps);
179 ice_debug(hw, ICE_DBG_LINK, " low_power_ctrl_an = 0x%x\n",
180 pcaps->low_power_ctrl_an);
181 ice_debug(hw, ICE_DBG_LINK, " eee_cap = 0x%x\n", pcaps->eee_cap);
182 ice_debug(hw, ICE_DBG_LINK, " eeer_value = 0x%x\n",
184 ice_debug(hw, ICE_DBG_LINK, " link_fec_options = 0x%x\n",
185 pcaps->link_fec_options);
186 ice_debug(hw, ICE_DBG_LINK, " module_compliance_enforcement = 0x%x\n",
187 pcaps->module_compliance_enforcement);
188 ice_debug(hw, ICE_DBG_LINK, " extended_compliance_code = 0x%x\n",
189 pcaps->extended_compliance_code);
190 ice_debug(hw, ICE_DBG_LINK, " module_type[0] = 0x%x\n",
191 pcaps->module_type[0]);
192 ice_debug(hw, ICE_DBG_LINK, " module_type[1] = 0x%x\n",
193 pcaps->module_type[1]);
194 ice_debug(hw, ICE_DBG_LINK, " module_type[2] = 0x%x\n",
195 pcaps->module_type[2]);
197 if (status == ICE_SUCCESS && report_mode == ICE_AQC_REPORT_TOPO_CAP) {
198 pi->phy.phy_type_low = LE64_TO_CPU(pcaps->phy_type_low);
199 pi->phy.phy_type_high = LE64_TO_CPU(pcaps->phy_type_high);
200 ice_memcpy(pi->phy.link_info.module_type, &pcaps->module_type,
201 sizeof(pi->phy.link_info.module_type),
202 ICE_NONDMA_TO_NONDMA);
209 * ice_aq_get_link_topo_handle - get link topology node return status
210 * @pi: port information structure
211 * @node_type: requested node type
212 * @cd: pointer to command details structure or NULL
214 * Get link topology node return status for specified node type (0x06E0)
216 * Node type cage can be used to determine if cage is present. If AQC
217 * returns error (ENOENT), then no cage present. If no cage present, then
218 * connection type is backplane or BASE-T.
220 static enum ice_status
221 ice_aq_get_link_topo_handle(struct ice_port_info *pi, u8 node_type,
222 struct ice_sq_cd *cd)
224 struct ice_aqc_get_link_topo *cmd;
225 struct ice_aq_desc desc;
227 cmd = &desc.params.get_link_topo;
229 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_topo);
231 cmd->addr.node_type_ctx = (ICE_AQC_LINK_TOPO_NODE_CTX_PORT <<
232 ICE_AQC_LINK_TOPO_NODE_CTX_S);
235 cmd->addr.node_type_ctx |= (ICE_AQC_LINK_TOPO_NODE_TYPE_M & node_type);
237 return ice_aq_send_cmd(pi->hw, &desc, NULL, 0, cd);
241 * ice_is_media_cage_present
242 * @pi: port information structure
244 * Returns true if media cage is present, else false. If no cage, then
245 * media type is backplane or BASE-T.
247 static bool ice_is_media_cage_present(struct ice_port_info *pi)
249 /* Node type cage can be used to determine if cage is present. If AQC
250 * returns error (ENOENT), then no cage present. If no cage present then
251 * connection type is backplane or BASE-T.
253 return !ice_aq_get_link_topo_handle(pi,
254 ICE_AQC_LINK_TOPO_NODE_TYPE_CAGE,
259 * ice_get_media_type - Gets media type
260 * @pi: port information structure
262 static enum ice_media_type ice_get_media_type(struct ice_port_info *pi)
264 struct ice_link_status *hw_link_info;
267 return ICE_MEDIA_UNKNOWN;
269 hw_link_info = &pi->phy.link_info;
270 if (hw_link_info->phy_type_low && hw_link_info->phy_type_high)
271 /* If more than one media type is selected, report unknown */
272 return ICE_MEDIA_UNKNOWN;
274 if (hw_link_info->phy_type_low) {
275 /* 1G SGMII is a special case where some DA cable PHYs
276 * may show this as an option when it really shouldn't
277 * be since SGMII is meant to be between a MAC and a PHY
278 * in a backplane. Try to detect this case and handle it
280 if (hw_link_info->phy_type_low == ICE_PHY_TYPE_LOW_1G_SGMII &&
281 (hw_link_info->module_type[ICE_AQC_MOD_TYPE_IDENT] ==
282 ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_ACTIVE ||
283 hw_link_info->module_type[ICE_AQC_MOD_TYPE_IDENT] ==
284 ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_PASSIVE))
287 switch (hw_link_info->phy_type_low) {
288 case ICE_PHY_TYPE_LOW_1000BASE_SX:
289 case ICE_PHY_TYPE_LOW_1000BASE_LX:
290 case ICE_PHY_TYPE_LOW_10GBASE_SR:
291 case ICE_PHY_TYPE_LOW_10GBASE_LR:
292 case ICE_PHY_TYPE_LOW_10G_SFI_C2C:
293 case ICE_PHY_TYPE_LOW_25GBASE_SR:
294 case ICE_PHY_TYPE_LOW_25GBASE_LR:
295 case ICE_PHY_TYPE_LOW_40GBASE_SR4:
296 case ICE_PHY_TYPE_LOW_40GBASE_LR4:
297 case ICE_PHY_TYPE_LOW_50GBASE_SR2:
298 case ICE_PHY_TYPE_LOW_50GBASE_LR2:
299 case ICE_PHY_TYPE_LOW_50GBASE_SR:
300 case ICE_PHY_TYPE_LOW_50GBASE_FR:
301 case ICE_PHY_TYPE_LOW_50GBASE_LR:
302 case ICE_PHY_TYPE_LOW_100GBASE_SR4:
303 case ICE_PHY_TYPE_LOW_100GBASE_LR4:
304 case ICE_PHY_TYPE_LOW_100GBASE_SR2:
305 case ICE_PHY_TYPE_LOW_100GBASE_DR:
306 return ICE_MEDIA_FIBER;
307 case ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC:
308 case ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC:
309 case ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC:
310 case ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC:
311 case ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC:
312 case ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC:
313 case ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC:
314 case ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC:
315 return ICE_MEDIA_FIBER;
316 case ICE_PHY_TYPE_LOW_100BASE_TX:
317 case ICE_PHY_TYPE_LOW_1000BASE_T:
318 case ICE_PHY_TYPE_LOW_2500BASE_T:
319 case ICE_PHY_TYPE_LOW_5GBASE_T:
320 case ICE_PHY_TYPE_LOW_10GBASE_T:
321 case ICE_PHY_TYPE_LOW_25GBASE_T:
322 return ICE_MEDIA_BASET;
323 case ICE_PHY_TYPE_LOW_10G_SFI_DA:
324 case ICE_PHY_TYPE_LOW_25GBASE_CR:
325 case ICE_PHY_TYPE_LOW_25GBASE_CR_S:
326 case ICE_PHY_TYPE_LOW_25GBASE_CR1:
327 case ICE_PHY_TYPE_LOW_40GBASE_CR4:
328 case ICE_PHY_TYPE_LOW_50GBASE_CR2:
329 case ICE_PHY_TYPE_LOW_50GBASE_CP:
330 case ICE_PHY_TYPE_LOW_100GBASE_CR4:
331 case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4:
332 case ICE_PHY_TYPE_LOW_100GBASE_CP2:
334 case ICE_PHY_TYPE_LOW_25G_AUI_C2C:
335 case ICE_PHY_TYPE_LOW_40G_XLAUI:
336 case ICE_PHY_TYPE_LOW_50G_LAUI2:
337 case ICE_PHY_TYPE_LOW_50G_AUI2:
338 case ICE_PHY_TYPE_LOW_50G_AUI1:
339 case ICE_PHY_TYPE_LOW_100G_AUI4:
340 case ICE_PHY_TYPE_LOW_100G_CAUI4:
341 if (ice_is_media_cage_present(pi))
342 return ICE_MEDIA_AUI;
344 case ICE_PHY_TYPE_LOW_1000BASE_KX:
345 case ICE_PHY_TYPE_LOW_2500BASE_KX:
346 case ICE_PHY_TYPE_LOW_2500BASE_X:
347 case ICE_PHY_TYPE_LOW_5GBASE_KR:
348 case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1:
349 case ICE_PHY_TYPE_LOW_25GBASE_KR:
350 case ICE_PHY_TYPE_LOW_25GBASE_KR1:
351 case ICE_PHY_TYPE_LOW_25GBASE_KR_S:
352 case ICE_PHY_TYPE_LOW_40GBASE_KR4:
353 case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4:
354 case ICE_PHY_TYPE_LOW_50GBASE_KR2:
355 case ICE_PHY_TYPE_LOW_100GBASE_KR4:
356 case ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4:
357 return ICE_MEDIA_BACKPLANE;
360 switch (hw_link_info->phy_type_high) {
361 case ICE_PHY_TYPE_HIGH_100G_AUI2:
362 case ICE_PHY_TYPE_HIGH_100G_CAUI2:
363 if (ice_is_media_cage_present(pi))
364 return ICE_MEDIA_AUI;
366 case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4:
367 return ICE_MEDIA_BACKPLANE;
368 case ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC:
369 case ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC:
370 return ICE_MEDIA_FIBER;
373 return ICE_MEDIA_UNKNOWN;
377 * ice_aq_get_link_info
378 * @pi: port information structure
379 * @ena_lse: enable/disable LinkStatusEvent reporting
380 * @link: pointer to link status structure - optional
381 * @cd: pointer to command details structure or NULL
383 * Get Link Status (0x607). Returns the link status of the adapter.
386 ice_aq_get_link_info(struct ice_port_info *pi, bool ena_lse,
387 struct ice_link_status *link, struct ice_sq_cd *cd)
389 struct ice_aqc_get_link_status_data link_data = { 0 };
390 struct ice_aqc_get_link_status *resp;
391 struct ice_link_status *li_old, *li;
392 enum ice_media_type *hw_media_type;
393 struct ice_fc_info *hw_fc_info;
394 bool tx_pause, rx_pause;
395 struct ice_aq_desc desc;
396 enum ice_status status;
401 return ICE_ERR_PARAM;
403 li_old = &pi->phy.link_info_old;
404 hw_media_type = &pi->phy.media_type;
405 li = &pi->phy.link_info;
406 hw_fc_info = &pi->fc;
408 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_status);
409 cmd_flags = (ena_lse) ? ICE_AQ_LSE_ENA : ICE_AQ_LSE_DIS;
410 resp = &desc.params.get_link_status;
411 resp->cmd_flags = CPU_TO_LE16(cmd_flags);
412 resp->lport_num = pi->lport;
414 status = ice_aq_send_cmd(hw, &desc, &link_data, sizeof(link_data), cd);
416 if (status != ICE_SUCCESS)
419 /* save off old link status information */
422 /* update current link status information */
423 li->link_speed = LE16_TO_CPU(link_data.link_speed);
424 li->phy_type_low = LE64_TO_CPU(link_data.phy_type_low);
425 li->phy_type_high = LE64_TO_CPU(link_data.phy_type_high);
426 *hw_media_type = ice_get_media_type(pi);
427 li->link_info = link_data.link_info;
428 li->an_info = link_data.an_info;
429 li->ext_info = link_data.ext_info;
430 li->max_frame_size = LE16_TO_CPU(link_data.max_frame_size);
431 li->fec_info = link_data.cfg & ICE_AQ_FEC_MASK;
432 li->topo_media_conflict = link_data.topo_media_conflict;
433 li->pacing = link_data.cfg & (ICE_AQ_CFG_PACING_M |
434 ICE_AQ_CFG_PACING_TYPE_M);
437 tx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_TX);
438 rx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_RX);
439 if (tx_pause && rx_pause)
440 hw_fc_info->current_mode = ICE_FC_FULL;
442 hw_fc_info->current_mode = ICE_FC_TX_PAUSE;
444 hw_fc_info->current_mode = ICE_FC_RX_PAUSE;
446 hw_fc_info->current_mode = ICE_FC_NONE;
448 li->lse_ena = !!(resp->cmd_flags & CPU_TO_LE16(ICE_AQ_LSE_IS_ENABLED));
450 ice_debug(hw, ICE_DBG_LINK, "get link info\n");
451 ice_debug(hw, ICE_DBG_LINK, " link_speed = 0x%x\n", li->link_speed);
452 ice_debug(hw, ICE_DBG_LINK, " phy_type_low = 0x%llx\n",
453 (unsigned long long)li->phy_type_low);
454 ice_debug(hw, ICE_DBG_LINK, " phy_type_high = 0x%llx\n",
455 (unsigned long long)li->phy_type_high);
456 ice_debug(hw, ICE_DBG_LINK, " media_type = 0x%x\n", *hw_media_type);
457 ice_debug(hw, ICE_DBG_LINK, " link_info = 0x%x\n", li->link_info);
458 ice_debug(hw, ICE_DBG_LINK, " an_info = 0x%x\n", li->an_info);
459 ice_debug(hw, ICE_DBG_LINK, " ext_info = 0x%x\n", li->ext_info);
460 ice_debug(hw, ICE_DBG_LINK, " fec_info = 0x%x\n", li->fec_info);
461 ice_debug(hw, ICE_DBG_LINK, " lse_ena = 0x%x\n", li->lse_ena);
462 ice_debug(hw, ICE_DBG_LINK, " max_frame = 0x%x\n",
464 ice_debug(hw, ICE_DBG_LINK, " pacing = 0x%x\n", li->pacing);
466 /* save link status information */
470 /* flag cleared so calling functions don't call AQ again */
471 pi->phy.get_link_info = false;
477 * ice_fill_tx_timer_and_fc_thresh
478 * @hw: pointer to the HW struct
479 * @cmd: pointer to MAC cfg structure
481 * Add Tx timer and FC refresh threshold info to Set MAC Config AQ command
485 ice_fill_tx_timer_and_fc_thresh(struct ice_hw *hw,
486 struct ice_aqc_set_mac_cfg *cmd)
488 u16 fc_thres_val, tx_timer_val;
491 /* We read back the transmit timer and fc threshold value of
492 * LFC. Thus, we will use index =
493 * PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX.
495 * Also, because we are opearating on transmit timer and fc
496 * threshold of LFC, we don't turn on any bit in tx_tmr_priority
498 #define IDX_OF_LFC PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX
500 /* Retrieve the transmit timer */
501 val = rd32(hw, PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(IDX_OF_LFC));
503 PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_HSEC_CTL_TX_PAUSE_QUANTA_M;
504 cmd->tx_tmr_value = CPU_TO_LE16(tx_timer_val);
506 /* Retrieve the fc threshold */
507 val = rd32(hw, PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(IDX_OF_LFC));
508 fc_thres_val = val & PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_M;
510 cmd->fc_refresh_threshold = CPU_TO_LE16(fc_thres_val);
515 * @hw: pointer to the HW struct
516 * @max_frame_size: Maximum Frame Size to be supported
517 * @cd: pointer to command details structure or NULL
519 * Set MAC configuration (0x0603)
522 ice_aq_set_mac_cfg(struct ice_hw *hw, u16 max_frame_size, struct ice_sq_cd *cd)
524 struct ice_aqc_set_mac_cfg *cmd;
525 struct ice_aq_desc desc;
527 cmd = &desc.params.set_mac_cfg;
529 if (max_frame_size == 0)
530 return ICE_ERR_PARAM;
532 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_mac_cfg);
534 cmd->max_frame_size = CPU_TO_LE16(max_frame_size);
536 ice_fill_tx_timer_and_fc_thresh(hw, cmd);
538 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
542 * ice_init_fltr_mgmt_struct - initializes filter management list and locks
543 * @hw: pointer to the HW struct
545 enum ice_status ice_init_fltr_mgmt_struct(struct ice_hw *hw)
547 struct ice_switch_info *sw;
548 enum ice_status status;
550 hw->switch_info = (struct ice_switch_info *)
551 ice_malloc(hw, sizeof(*hw->switch_info));
553 sw = hw->switch_info;
556 return ICE_ERR_NO_MEMORY;
558 INIT_LIST_HEAD(&sw->vsi_list_map_head);
559 sw->prof_res_bm_init = 0;
561 status = ice_init_def_sw_recp(hw, &hw->switch_info->recp_list);
563 ice_free(hw, hw->switch_info);
570 * ice_cleanup_fltr_mgmt_single - clears single filter mngt struct
571 * @hw: pointer to the HW struct
572 * @sw: pointer to switch info struct for which function clears filters
575 ice_cleanup_fltr_mgmt_single(struct ice_hw *hw, struct ice_switch_info *sw)
577 struct ice_vsi_list_map_info *v_pos_map;
578 struct ice_vsi_list_map_info *v_tmp_map;
579 struct ice_sw_recipe *recps;
585 LIST_FOR_EACH_ENTRY_SAFE(v_pos_map, v_tmp_map, &sw->vsi_list_map_head,
586 ice_vsi_list_map_info, list_entry) {
587 LIST_DEL(&v_pos_map->list_entry);
588 ice_free(hw, v_pos_map);
590 recps = sw->recp_list;
591 for (i = 0; i < ICE_MAX_NUM_RECIPES; i++) {
592 struct ice_recp_grp_entry *rg_entry, *tmprg_entry;
594 recps[i].root_rid = i;
595 LIST_FOR_EACH_ENTRY_SAFE(rg_entry, tmprg_entry,
596 &recps[i].rg_list, ice_recp_grp_entry,
598 LIST_DEL(&rg_entry->l_entry);
599 ice_free(hw, rg_entry);
602 if (recps[i].adv_rule) {
603 struct ice_adv_fltr_mgmt_list_entry *tmp_entry;
604 struct ice_adv_fltr_mgmt_list_entry *lst_itr;
606 ice_destroy_lock(&recps[i].filt_rule_lock);
607 LIST_FOR_EACH_ENTRY_SAFE(lst_itr, tmp_entry,
608 &recps[i].filt_rules,
609 ice_adv_fltr_mgmt_list_entry,
611 LIST_DEL(&lst_itr->list_entry);
612 ice_free(hw, lst_itr->lkups);
613 ice_free(hw, lst_itr);
616 struct ice_fltr_mgmt_list_entry *lst_itr, *tmp_entry;
618 ice_destroy_lock(&recps[i].filt_rule_lock);
619 LIST_FOR_EACH_ENTRY_SAFE(lst_itr, tmp_entry,
620 &recps[i].filt_rules,
621 ice_fltr_mgmt_list_entry,
623 LIST_DEL(&lst_itr->list_entry);
624 ice_free(hw, lst_itr);
627 if (recps[i].root_buf)
628 ice_free(hw, recps[i].root_buf);
630 ice_rm_sw_replay_rule_info(hw, sw);
631 ice_free(hw, sw->recp_list);
636 * ice_cleanup_all_fltr_mgmt - cleanup filter management list and locks
637 * @hw: pointer to the HW struct
639 void ice_cleanup_fltr_mgmt_struct(struct ice_hw *hw)
641 ice_cleanup_fltr_mgmt_single(hw, hw->switch_info);
645 * ice_get_itr_intrl_gran
646 * @hw: pointer to the HW struct
648 * Determines the ITR/INTRL granularities based on the maximum aggregate
649 * bandwidth according to the device's configuration during power-on.
651 static void ice_get_itr_intrl_gran(struct ice_hw *hw)
653 u8 max_agg_bw = (rd32(hw, GL_PWR_MODE_CTL) &
654 GL_PWR_MODE_CTL_CAR_MAX_BW_M) >>
655 GL_PWR_MODE_CTL_CAR_MAX_BW_S;
657 switch (max_agg_bw) {
658 case ICE_MAX_AGG_BW_200G:
659 case ICE_MAX_AGG_BW_100G:
660 case ICE_MAX_AGG_BW_50G:
661 hw->itr_gran = ICE_ITR_GRAN_ABOVE_25;
662 hw->intrl_gran = ICE_INTRL_GRAN_ABOVE_25;
664 case ICE_MAX_AGG_BW_25G:
665 hw->itr_gran = ICE_ITR_GRAN_MAX_25;
666 hw->intrl_gran = ICE_INTRL_GRAN_MAX_25;
672 * ice_print_rollback_msg - print FW rollback message
673 * @hw: pointer to the hardware structure
675 void ice_print_rollback_msg(struct ice_hw *hw)
677 char nvm_str[ICE_NVM_VER_LEN] = { 0 };
678 struct ice_orom_info *orom;
679 struct ice_nvm_info *nvm;
681 orom = &hw->flash.orom;
682 nvm = &hw->flash.nvm;
684 SNPRINTF(nvm_str, sizeof(nvm_str), "%x.%02x 0x%x %d.%d.%d",
685 nvm->major, nvm->minor, nvm->eetrack, orom->major,
686 orom->build, orom->patch);
688 "Firmware rollback mode detected. Current version is NVM: %s, FW: %d.%d. Device may exhibit limited functionality. Refer to the Intel(R) Ethernet Adapters and Devices User Guide for details on firmware rollback mode\n",
689 nvm_str, hw->fw_maj_ver, hw->fw_min_ver);
693 * ice_init_hw - main hardware initialization routine
694 * @hw: pointer to the hardware structure
696 enum ice_status ice_init_hw(struct ice_hw *hw)
698 struct ice_aqc_get_phy_caps_data *pcaps;
699 enum ice_status status;
703 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
705 /* Set MAC type based on DeviceID */
706 status = ice_set_mac_type(hw);
710 hw->pf_id = (u8)(rd32(hw, PF_FUNC_RID) &
711 PF_FUNC_RID_FUNCTION_NUMBER_M) >>
712 PF_FUNC_RID_FUNCTION_NUMBER_S;
714 status = ice_reset(hw, ICE_RESET_PFR);
718 ice_get_itr_intrl_gran(hw);
720 status = ice_create_all_ctrlq(hw);
722 goto err_unroll_cqinit;
724 status = ice_init_nvm(hw);
726 goto err_unroll_cqinit;
728 if (ice_get_fw_mode(hw) == ICE_FW_MODE_ROLLBACK)
729 ice_print_rollback_msg(hw);
731 status = ice_clear_pf_cfg(hw);
733 goto err_unroll_cqinit;
735 /* Set bit to enable Flow Director filters */
736 wr32(hw, PFQF_FD_ENA, PFQF_FD_ENA_FD_ENA_M);
737 INIT_LIST_HEAD(&hw->fdir_list_head);
739 ice_clear_pxe_mode(hw);
741 status = ice_get_caps(hw);
743 goto err_unroll_cqinit;
745 hw->port_info = (struct ice_port_info *)
746 ice_malloc(hw, sizeof(*hw->port_info));
747 if (!hw->port_info) {
748 status = ICE_ERR_NO_MEMORY;
749 goto err_unroll_cqinit;
752 /* set the back pointer to HW */
753 hw->port_info->hw = hw;
755 /* Initialize port_info struct with switch configuration data */
756 status = ice_get_initial_sw_cfg(hw);
758 goto err_unroll_alloc;
761 /* Query the allocated resources for Tx scheduler */
762 status = ice_sched_query_res_alloc(hw);
764 ice_debug(hw, ICE_DBG_SCHED, "Failed to get scheduler allocated resources\n");
765 goto err_unroll_alloc;
767 ice_sched_get_psm_clk_freq(hw);
769 /* Initialize port_info struct with scheduler data */
770 status = ice_sched_init_port(hw->port_info);
772 goto err_unroll_sched;
773 pcaps = (struct ice_aqc_get_phy_caps_data *)
774 ice_malloc(hw, sizeof(*pcaps));
776 status = ICE_ERR_NO_MEMORY;
777 goto err_unroll_sched;
780 /* Initialize port_info struct with PHY capabilities */
781 status = ice_aq_get_phy_caps(hw->port_info, false,
782 ICE_AQC_REPORT_TOPO_CAP, pcaps, NULL);
785 ice_warn(hw, "Get PHY capabilities failed status = %d, continuing anyway\n",
788 /* Initialize port_info struct with link information */
789 status = ice_aq_get_link_info(hw->port_info, false, NULL, NULL);
791 goto err_unroll_sched;
792 /* need a valid SW entry point to build a Tx tree */
793 if (!hw->sw_entry_point_layer) {
794 ice_debug(hw, ICE_DBG_SCHED, "invalid sw entry point\n");
795 status = ICE_ERR_CFG;
796 goto err_unroll_sched;
798 INIT_LIST_HEAD(&hw->agg_list);
799 /* Initialize max burst size */
800 if (!hw->max_burst_size)
801 ice_cfg_rl_burst_size(hw, ICE_SCHED_DFLT_BURST_SIZE);
802 status = ice_init_fltr_mgmt_struct(hw);
804 goto err_unroll_sched;
806 /* Get MAC information */
807 /* A single port can report up to two (LAN and WoL) addresses */
808 mac_buf = ice_calloc(hw, 2,
809 sizeof(struct ice_aqc_manage_mac_read_resp));
810 mac_buf_len = 2 * sizeof(struct ice_aqc_manage_mac_read_resp);
813 status = ICE_ERR_NO_MEMORY;
814 goto err_unroll_fltr_mgmt_struct;
817 status = ice_aq_manage_mac_read(hw, mac_buf, mac_buf_len, NULL);
818 ice_free(hw, mac_buf);
821 goto err_unroll_fltr_mgmt_struct;
822 /* enable jumbo frame support at MAC level */
823 status = ice_aq_set_mac_cfg(hw, ICE_AQ_SET_MAC_FRAME_SIZE_MAX, NULL);
825 goto err_unroll_fltr_mgmt_struct;
826 /* Obtain counter base index which would be used by flow director */
827 status = ice_alloc_fd_res_cntr(hw, &hw->fd_ctr_base);
829 goto err_unroll_fltr_mgmt_struct;
830 status = ice_init_hw_tbls(hw);
832 goto err_unroll_fltr_mgmt_struct;
833 ice_init_lock(&hw->tnl_lock);
835 ice_init_vlan_mode_ops(hw);
839 err_unroll_fltr_mgmt_struct:
840 ice_cleanup_fltr_mgmt_struct(hw);
842 ice_sched_cleanup_all(hw);
844 ice_free(hw, hw->port_info);
845 hw->port_info = NULL;
847 ice_destroy_all_ctrlq(hw);
852 * ice_deinit_hw - unroll initialization operations done by ice_init_hw
853 * @hw: pointer to the hardware structure
855 * This should be called only during nominal operation, not as a result of
856 * ice_init_hw() failing since ice_init_hw() will take care of unrolling
857 * applicable initializations if it fails for any reason.
859 void ice_deinit_hw(struct ice_hw *hw)
861 ice_free_fd_res_cntr(hw, hw->fd_ctr_base);
862 ice_cleanup_fltr_mgmt_struct(hw);
864 ice_sched_cleanup_all(hw);
865 ice_sched_clear_agg(hw);
867 ice_free_hw_tbls(hw);
868 ice_destroy_lock(&hw->tnl_lock);
871 ice_free(hw, hw->port_info);
872 hw->port_info = NULL;
875 ice_destroy_all_ctrlq(hw);
877 /* Clear VSI contexts if not already cleared */
878 ice_clear_all_vsi_ctx(hw);
882 * ice_check_reset - Check to see if a global reset is complete
883 * @hw: pointer to the hardware structure
885 enum ice_status ice_check_reset(struct ice_hw *hw)
887 u32 cnt, reg = 0, grst_timeout, uld_mask;
889 /* Poll for Device Active state in case a recent CORER, GLOBR,
890 * or EMPR has occurred. The grst delay value is in 100ms units.
891 * Add 1sec for outstanding AQ commands that can take a long time.
893 grst_timeout = ((rd32(hw, GLGEN_RSTCTL) & GLGEN_RSTCTL_GRSTDEL_M) >>
894 GLGEN_RSTCTL_GRSTDEL_S) + 10;
896 for (cnt = 0; cnt < grst_timeout; cnt++) {
897 ice_msec_delay(100, true);
898 reg = rd32(hw, GLGEN_RSTAT);
899 if (!(reg & GLGEN_RSTAT_DEVSTATE_M))
903 if (cnt == grst_timeout) {
904 ice_debug(hw, ICE_DBG_INIT, "Global reset polling failed to complete.\n");
905 return ICE_ERR_RESET_FAILED;
908 #define ICE_RESET_DONE_MASK (GLNVM_ULD_PCIER_DONE_M |\
909 GLNVM_ULD_PCIER_DONE_1_M |\
910 GLNVM_ULD_CORER_DONE_M |\
911 GLNVM_ULD_GLOBR_DONE_M |\
912 GLNVM_ULD_POR_DONE_M |\
913 GLNVM_ULD_POR_DONE_1_M |\
914 GLNVM_ULD_PCIER_DONE_2_M)
916 uld_mask = ICE_RESET_DONE_MASK;
918 /* Device is Active; check Global Reset processes are done */
919 for (cnt = 0; cnt < ICE_PF_RESET_WAIT_COUNT; cnt++) {
920 reg = rd32(hw, GLNVM_ULD) & uld_mask;
921 if (reg == uld_mask) {
922 ice_debug(hw, ICE_DBG_INIT, "Global reset processes done. %d\n", cnt);
925 ice_msec_delay(10, true);
928 if (cnt == ICE_PF_RESET_WAIT_COUNT) {
929 ice_debug(hw, ICE_DBG_INIT, "Wait for Reset Done timed out. GLNVM_ULD = 0x%x\n",
931 return ICE_ERR_RESET_FAILED;
938 * ice_pf_reset - Reset the PF
939 * @hw: pointer to the hardware structure
941 * If a global reset has been triggered, this function checks
942 * for its completion and then issues the PF reset
944 static enum ice_status ice_pf_reset(struct ice_hw *hw)
948 /* If at function entry a global reset was already in progress, i.e.
949 * state is not 'device active' or any of the reset done bits are not
950 * set in GLNVM_ULD, there is no need for a PF Reset; poll until the
951 * global reset is done.
953 if ((rd32(hw, GLGEN_RSTAT) & GLGEN_RSTAT_DEVSTATE_M) ||
954 (rd32(hw, GLNVM_ULD) & ICE_RESET_DONE_MASK) ^ ICE_RESET_DONE_MASK) {
955 /* poll on global reset currently in progress until done */
956 if (ice_check_reset(hw))
957 return ICE_ERR_RESET_FAILED;
963 reg = rd32(hw, PFGEN_CTRL);
965 wr32(hw, PFGEN_CTRL, (reg | PFGEN_CTRL_PFSWR_M));
967 /* Wait for the PFR to complete. The wait time is the global config lock
968 * timeout plus the PFR timeout which will account for a possible reset
969 * that is occurring during a download package operation.
971 for (cnt = 0; cnt < ICE_GLOBAL_CFG_LOCK_TIMEOUT +
972 ICE_PF_RESET_WAIT_COUNT; cnt++) {
973 reg = rd32(hw, PFGEN_CTRL);
974 if (!(reg & PFGEN_CTRL_PFSWR_M))
977 ice_msec_delay(1, true);
980 if (cnt == ICE_PF_RESET_WAIT_COUNT) {
981 ice_debug(hw, ICE_DBG_INIT, "PF reset polling failed to complete.\n");
982 return ICE_ERR_RESET_FAILED;
989 * ice_reset - Perform different types of reset
990 * @hw: pointer to the hardware structure
991 * @req: reset request
993 * This function triggers a reset as specified by the req parameter.
996 * If anything other than a PF reset is triggered, PXE mode is restored.
997 * This has to be cleared using ice_clear_pxe_mode again, once the AQ
998 * interface has been restored in the rebuild flow.
1000 enum ice_status ice_reset(struct ice_hw *hw, enum ice_reset_req req)
1006 return ice_pf_reset(hw);
1007 case ICE_RESET_CORER:
1008 ice_debug(hw, ICE_DBG_INIT, "CoreR requested\n");
1009 val = GLGEN_RTRIG_CORER_M;
1011 case ICE_RESET_GLOBR:
1012 ice_debug(hw, ICE_DBG_INIT, "GlobalR requested\n");
1013 val = GLGEN_RTRIG_GLOBR_M;
1016 return ICE_ERR_PARAM;
1019 val |= rd32(hw, GLGEN_RTRIG);
1020 wr32(hw, GLGEN_RTRIG, val);
1023 /* wait for the FW to be ready */
1024 return ice_check_reset(hw);
1028 * ice_copy_rxq_ctx_to_hw
1029 * @hw: pointer to the hardware structure
1030 * @ice_rxq_ctx: pointer to the rxq context
1031 * @rxq_index: the index of the Rx queue
1033 * Copies rxq context from dense structure to HW register space
1035 static enum ice_status
1036 ice_copy_rxq_ctx_to_hw(struct ice_hw *hw, u8 *ice_rxq_ctx, u32 rxq_index)
1041 return ICE_ERR_BAD_PTR;
1043 if (rxq_index > QRX_CTRL_MAX_INDEX)
1044 return ICE_ERR_PARAM;
1046 /* Copy each dword separately to HW */
1047 for (i = 0; i < ICE_RXQ_CTX_SIZE_DWORDS; i++) {
1048 wr32(hw, QRX_CONTEXT(i, rxq_index),
1049 *((u32 *)(ice_rxq_ctx + (i * sizeof(u32)))));
1051 ice_debug(hw, ICE_DBG_QCTX, "qrxdata[%d]: %08X\n", i,
1052 *((u32 *)(ice_rxq_ctx + (i * sizeof(u32)))));
1058 /* LAN Rx Queue Context */
1059 static const struct ice_ctx_ele ice_rlan_ctx_info[] = {
1060 /* Field Width LSB */
1061 ICE_CTX_STORE(ice_rlan_ctx, head, 13, 0),
1062 ICE_CTX_STORE(ice_rlan_ctx, cpuid, 8, 13),
1063 ICE_CTX_STORE(ice_rlan_ctx, base, 57, 32),
1064 ICE_CTX_STORE(ice_rlan_ctx, qlen, 13, 89),
1065 ICE_CTX_STORE(ice_rlan_ctx, dbuf, 7, 102),
1066 ICE_CTX_STORE(ice_rlan_ctx, hbuf, 5, 109),
1067 ICE_CTX_STORE(ice_rlan_ctx, dtype, 2, 114),
1068 ICE_CTX_STORE(ice_rlan_ctx, dsize, 1, 116),
1069 ICE_CTX_STORE(ice_rlan_ctx, crcstrip, 1, 117),
1070 ICE_CTX_STORE(ice_rlan_ctx, l2tsel, 1, 119),
1071 ICE_CTX_STORE(ice_rlan_ctx, hsplit_0, 4, 120),
1072 ICE_CTX_STORE(ice_rlan_ctx, hsplit_1, 2, 124),
1073 ICE_CTX_STORE(ice_rlan_ctx, showiv, 1, 127),
1074 ICE_CTX_STORE(ice_rlan_ctx, rxmax, 14, 174),
1075 ICE_CTX_STORE(ice_rlan_ctx, tphrdesc_ena, 1, 193),
1076 ICE_CTX_STORE(ice_rlan_ctx, tphwdesc_ena, 1, 194),
1077 ICE_CTX_STORE(ice_rlan_ctx, tphdata_ena, 1, 195),
1078 ICE_CTX_STORE(ice_rlan_ctx, tphhead_ena, 1, 196),
1079 ICE_CTX_STORE(ice_rlan_ctx, lrxqthresh, 3, 198),
1080 ICE_CTX_STORE(ice_rlan_ctx, prefena, 1, 201),
1086 * @hw: pointer to the hardware structure
1087 * @rlan_ctx: pointer to the rxq context
1088 * @rxq_index: the index of the Rx queue
1090 * Converts rxq context from sparse to dense structure and then writes
1091 * it to HW register space and enables the hardware to prefetch descriptors
1092 * instead of only fetching them on demand
1095 ice_write_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx,
1098 u8 ctx_buf[ICE_RXQ_CTX_SZ] = { 0 };
1101 return ICE_ERR_BAD_PTR;
1103 rlan_ctx->prefena = 1;
1105 ice_set_ctx(hw, (u8 *)rlan_ctx, ctx_buf, ice_rlan_ctx_info);
1106 return ice_copy_rxq_ctx_to_hw(hw, ctx_buf, rxq_index);
1111 * @hw: pointer to the hardware structure
1112 * @rxq_index: the index of the Rx queue to clear
1114 * Clears rxq context in HW register space
1116 enum ice_status ice_clear_rxq_ctx(struct ice_hw *hw, u32 rxq_index)
1120 if (rxq_index > QRX_CTRL_MAX_INDEX)
1121 return ICE_ERR_PARAM;
1123 /* Clear each dword register separately */
1124 for (i = 0; i < ICE_RXQ_CTX_SIZE_DWORDS; i++)
1125 wr32(hw, QRX_CONTEXT(i, rxq_index), 0);
1130 /* LAN Tx Queue Context */
1131 const struct ice_ctx_ele ice_tlan_ctx_info[] = {
1132 /* Field Width LSB */
1133 ICE_CTX_STORE(ice_tlan_ctx, base, 57, 0),
1134 ICE_CTX_STORE(ice_tlan_ctx, port_num, 3, 57),
1135 ICE_CTX_STORE(ice_tlan_ctx, cgd_num, 5, 60),
1136 ICE_CTX_STORE(ice_tlan_ctx, pf_num, 3, 65),
1137 ICE_CTX_STORE(ice_tlan_ctx, vmvf_num, 10, 68),
1138 ICE_CTX_STORE(ice_tlan_ctx, vmvf_type, 2, 78),
1139 ICE_CTX_STORE(ice_tlan_ctx, src_vsi, 10, 80),
1140 ICE_CTX_STORE(ice_tlan_ctx, tsyn_ena, 1, 90),
1141 ICE_CTX_STORE(ice_tlan_ctx, internal_usage_flag, 1, 91),
1142 ICE_CTX_STORE(ice_tlan_ctx, alt_vlan, 1, 92),
1143 ICE_CTX_STORE(ice_tlan_ctx, cpuid, 8, 93),
1144 ICE_CTX_STORE(ice_tlan_ctx, wb_mode, 1, 101),
1145 ICE_CTX_STORE(ice_tlan_ctx, tphrd_desc, 1, 102),
1146 ICE_CTX_STORE(ice_tlan_ctx, tphrd, 1, 103),
1147 ICE_CTX_STORE(ice_tlan_ctx, tphwr_desc, 1, 104),
1148 ICE_CTX_STORE(ice_tlan_ctx, cmpq_id, 9, 105),
1149 ICE_CTX_STORE(ice_tlan_ctx, qnum_in_func, 14, 114),
1150 ICE_CTX_STORE(ice_tlan_ctx, itr_notification_mode, 1, 128),
1151 ICE_CTX_STORE(ice_tlan_ctx, adjust_prof_id, 6, 129),
1152 ICE_CTX_STORE(ice_tlan_ctx, qlen, 13, 135),
1153 ICE_CTX_STORE(ice_tlan_ctx, quanta_prof_idx, 4, 148),
1154 ICE_CTX_STORE(ice_tlan_ctx, tso_ena, 1, 152),
1155 ICE_CTX_STORE(ice_tlan_ctx, tso_qnum, 11, 153),
1156 ICE_CTX_STORE(ice_tlan_ctx, legacy_int, 1, 164),
1157 ICE_CTX_STORE(ice_tlan_ctx, drop_ena, 1, 165),
1158 ICE_CTX_STORE(ice_tlan_ctx, cache_prof_idx, 2, 166),
1159 ICE_CTX_STORE(ice_tlan_ctx, pkt_shaper_prof_idx, 3, 168),
1160 ICE_CTX_STORE(ice_tlan_ctx, int_q_state, 122, 171),
1165 * ice_copy_tx_cmpltnq_ctx_to_hw
1166 * @hw: pointer to the hardware structure
1167 * @ice_tx_cmpltnq_ctx: pointer to the Tx completion queue context
1168 * @tx_cmpltnq_index: the index of the completion queue
1170 * Copies Tx completion queue context from dense structure to HW register space
1172 static enum ice_status
1173 ice_copy_tx_cmpltnq_ctx_to_hw(struct ice_hw *hw, u8 *ice_tx_cmpltnq_ctx,
1174 u32 tx_cmpltnq_index)
1178 if (!ice_tx_cmpltnq_ctx)
1179 return ICE_ERR_BAD_PTR;
1181 if (tx_cmpltnq_index > GLTCLAN_CQ_CNTX0_MAX_INDEX)
1182 return ICE_ERR_PARAM;
1184 /* Copy each dword separately to HW */
1185 for (i = 0; i < ICE_TX_CMPLTNQ_CTX_SIZE_DWORDS; i++) {
1186 wr32(hw, GLTCLAN_CQ_CNTX(i, tx_cmpltnq_index),
1187 *((u32 *)(ice_tx_cmpltnq_ctx + (i * sizeof(u32)))));
1189 ice_debug(hw, ICE_DBG_QCTX, "cmpltnqdata[%d]: %08X\n", i,
1190 *((u32 *)(ice_tx_cmpltnq_ctx + (i * sizeof(u32)))));
1196 /* LAN Tx Completion Queue Context */
1197 static const struct ice_ctx_ele ice_tx_cmpltnq_ctx_info[] = {
1198 /* Field Width LSB */
1199 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, base, 57, 0),
1200 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, q_len, 18, 64),
1201 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, generation, 1, 96),
1202 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, wrt_ptr, 22, 97),
1203 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, pf_num, 3, 128),
1204 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, vmvf_num, 10, 131),
1205 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, vmvf_type, 2, 141),
1206 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, tph_desc_wr, 1, 160),
1207 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, cpuid, 8, 161),
1208 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, cmpltn_cache, 512, 192),
1213 * ice_write_tx_cmpltnq_ctx
1214 * @hw: pointer to the hardware structure
1215 * @tx_cmpltnq_ctx: pointer to the completion queue context
1216 * @tx_cmpltnq_index: the index of the completion queue
1218 * Converts completion queue context from sparse to dense structure and then
1219 * writes it to HW register space
1222 ice_write_tx_cmpltnq_ctx(struct ice_hw *hw,
1223 struct ice_tx_cmpltnq_ctx *tx_cmpltnq_ctx,
1224 u32 tx_cmpltnq_index)
1226 u8 ctx_buf[ICE_TX_CMPLTNQ_CTX_SIZE_DWORDS * sizeof(u32)] = { 0 };
1228 ice_set_ctx(hw, (u8 *)tx_cmpltnq_ctx, ctx_buf, ice_tx_cmpltnq_ctx_info);
1229 return ice_copy_tx_cmpltnq_ctx_to_hw(hw, ctx_buf, tx_cmpltnq_index);
1233 * ice_clear_tx_cmpltnq_ctx
1234 * @hw: pointer to the hardware structure
1235 * @tx_cmpltnq_index: the index of the completion queue to clear
1237 * Clears Tx completion queue context in HW register space
1240 ice_clear_tx_cmpltnq_ctx(struct ice_hw *hw, u32 tx_cmpltnq_index)
1244 if (tx_cmpltnq_index > GLTCLAN_CQ_CNTX0_MAX_INDEX)
1245 return ICE_ERR_PARAM;
1247 /* Clear each dword register separately */
1248 for (i = 0; i < ICE_TX_CMPLTNQ_CTX_SIZE_DWORDS; i++)
1249 wr32(hw, GLTCLAN_CQ_CNTX(i, tx_cmpltnq_index), 0);
1255 * ice_copy_tx_drbell_q_ctx_to_hw
1256 * @hw: pointer to the hardware structure
1257 * @ice_tx_drbell_q_ctx: pointer to the doorbell queue context
1258 * @tx_drbell_q_index: the index of the doorbell queue
1260 * Copies doorbell queue context from dense structure to HW register space
1262 static enum ice_status
1263 ice_copy_tx_drbell_q_ctx_to_hw(struct ice_hw *hw, u8 *ice_tx_drbell_q_ctx,
1264 u32 tx_drbell_q_index)
1268 if (!ice_tx_drbell_q_ctx)
1269 return ICE_ERR_BAD_PTR;
1271 if (tx_drbell_q_index > QTX_COMM_DBLQ_DBELL_MAX_INDEX)
1272 return ICE_ERR_PARAM;
1274 /* Copy each dword separately to HW */
1275 for (i = 0; i < ICE_TX_DRBELL_Q_CTX_SIZE_DWORDS; i++) {
1276 wr32(hw, QTX_COMM_DBLQ_CNTX(i, tx_drbell_q_index),
1277 *((u32 *)(ice_tx_drbell_q_ctx + (i * sizeof(u32)))));
1279 ice_debug(hw, ICE_DBG_QCTX, "tx_drbell_qdata[%d]: %08X\n", i,
1280 *((u32 *)(ice_tx_drbell_q_ctx + (i * sizeof(u32)))));
1286 /* LAN Tx Doorbell Queue Context info */
1287 static const struct ice_ctx_ele ice_tx_drbell_q_ctx_info[] = {
1288 /* Field Width LSB */
1289 ICE_CTX_STORE(ice_tx_drbell_q_ctx, base, 57, 0),
1290 ICE_CTX_STORE(ice_tx_drbell_q_ctx, ring_len, 13, 64),
1291 ICE_CTX_STORE(ice_tx_drbell_q_ctx, pf_num, 3, 80),
1292 ICE_CTX_STORE(ice_tx_drbell_q_ctx, vf_num, 8, 84),
1293 ICE_CTX_STORE(ice_tx_drbell_q_ctx, vmvf_type, 2, 94),
1294 ICE_CTX_STORE(ice_tx_drbell_q_ctx, cpuid, 8, 96),
1295 ICE_CTX_STORE(ice_tx_drbell_q_ctx, tph_desc_rd, 1, 104),
1296 ICE_CTX_STORE(ice_tx_drbell_q_ctx, tph_desc_wr, 1, 108),
1297 ICE_CTX_STORE(ice_tx_drbell_q_ctx, db_q_en, 1, 112),
1298 ICE_CTX_STORE(ice_tx_drbell_q_ctx, rd_head, 13, 128),
1299 ICE_CTX_STORE(ice_tx_drbell_q_ctx, rd_tail, 13, 144),
1304 * ice_write_tx_drbell_q_ctx
1305 * @hw: pointer to the hardware structure
1306 * @tx_drbell_q_ctx: pointer to the doorbell queue context
1307 * @tx_drbell_q_index: the index of the doorbell queue
1309 * Converts doorbell queue context from sparse to dense structure and then
1310 * writes it to HW register space
1313 ice_write_tx_drbell_q_ctx(struct ice_hw *hw,
1314 struct ice_tx_drbell_q_ctx *tx_drbell_q_ctx,
1315 u32 tx_drbell_q_index)
1317 u8 ctx_buf[ICE_TX_DRBELL_Q_CTX_SIZE_DWORDS * sizeof(u32)] = { 0 };
1319 ice_set_ctx(hw, (u8 *)tx_drbell_q_ctx, ctx_buf,
1320 ice_tx_drbell_q_ctx_info);
1321 return ice_copy_tx_drbell_q_ctx_to_hw(hw, ctx_buf, tx_drbell_q_index);
1325 * ice_clear_tx_drbell_q_ctx
1326 * @hw: pointer to the hardware structure
1327 * @tx_drbell_q_index: the index of the doorbell queue to clear
1329 * Clears doorbell queue context in HW register space
1332 ice_clear_tx_drbell_q_ctx(struct ice_hw *hw, u32 tx_drbell_q_index)
1336 if (tx_drbell_q_index > QTX_COMM_DBLQ_DBELL_MAX_INDEX)
1337 return ICE_ERR_PARAM;
1339 /* Clear each dword register separately */
1340 for (i = 0; i < ICE_TX_DRBELL_Q_CTX_SIZE_DWORDS; i++)
1341 wr32(hw, QTX_COMM_DBLQ_CNTX(i, tx_drbell_q_index), 0);
1346 /* FW Admin Queue command wrappers */
1349 * ice_should_retry_sq_send_cmd
1350 * @opcode: AQ opcode
1352 * Decide if we should retry the send command routine for the ATQ, depending
1355 static bool ice_should_retry_sq_send_cmd(u16 opcode)
1358 case ice_aqc_opc_get_link_topo:
1359 case ice_aqc_opc_lldp_stop:
1360 case ice_aqc_opc_lldp_start:
1361 case ice_aqc_opc_lldp_filter_ctrl:
1369 * ice_sq_send_cmd_retry - send command to Control Queue (ATQ)
1370 * @hw: pointer to the HW struct
1371 * @cq: pointer to the specific Control queue
1372 * @desc: prefilled descriptor describing the command
1373 * @buf: buffer to use for indirect commands (or NULL for direct commands)
1374 * @buf_size: size of buffer for indirect commands (or 0 for direct commands)
1375 * @cd: pointer to command details structure
1377 * Retry sending the FW Admin Queue command, multiple times, to the FW Admin
1378 * Queue if the EBUSY AQ error is returned.
1380 static enum ice_status
1381 ice_sq_send_cmd_retry(struct ice_hw *hw, struct ice_ctl_q_info *cq,
1382 struct ice_aq_desc *desc, void *buf, u16 buf_size,
1383 struct ice_sq_cd *cd)
1385 struct ice_aq_desc desc_cpy;
1386 enum ice_status status;
1387 bool is_cmd_for_retry;
1392 opcode = LE16_TO_CPU(desc->opcode);
1393 is_cmd_for_retry = ice_should_retry_sq_send_cmd(opcode);
1394 ice_memset(&desc_cpy, 0, sizeof(desc_cpy), ICE_NONDMA_MEM);
1396 if (is_cmd_for_retry) {
1398 buf_cpy = (u8 *)ice_malloc(hw, buf_size);
1400 return ICE_ERR_NO_MEMORY;
1403 ice_memcpy(&desc_cpy, desc, sizeof(desc_cpy),
1404 ICE_NONDMA_TO_NONDMA);
1408 status = ice_sq_send_cmd(hw, cq, desc, buf, buf_size, cd);
1410 if (!is_cmd_for_retry || status == ICE_SUCCESS ||
1411 hw->adminq.sq_last_status != ICE_AQ_RC_EBUSY)
1415 ice_memcpy(buf, buf_cpy, buf_size,
1416 ICE_NONDMA_TO_NONDMA);
1418 ice_memcpy(desc, &desc_cpy, sizeof(desc_cpy),
1419 ICE_NONDMA_TO_NONDMA);
1421 ice_msec_delay(ICE_SQ_SEND_DELAY_TIME_MS, false);
1423 } while (++idx < ICE_SQ_SEND_MAX_EXECUTE);
1426 ice_free(hw, buf_cpy);
1432 * ice_aq_send_cmd - send FW Admin Queue command to FW Admin Queue
1433 * @hw: pointer to the HW struct
1434 * @desc: descriptor describing the command
1435 * @buf: buffer to use for indirect commands (NULL for direct commands)
1436 * @buf_size: size of buffer for indirect commands (0 for direct commands)
1437 * @cd: pointer to command details structure
1439 * Helper function to send FW Admin Queue commands to the FW Admin Queue.
1442 ice_aq_send_cmd(struct ice_hw *hw, struct ice_aq_desc *desc, void *buf,
1443 u16 buf_size, struct ice_sq_cd *cd)
1445 if (hw->aq_send_cmd_fn) {
1446 enum ice_status status = ICE_ERR_NOT_READY;
1447 u16 retval = ICE_AQ_RC_OK;
1449 ice_acquire_lock(&hw->adminq.sq_lock);
1450 if (!hw->aq_send_cmd_fn(hw->aq_send_cmd_param, desc,
1452 retval = LE16_TO_CPU(desc->retval);
1453 /* strip off FW internal code */
1456 if (retval == ICE_AQ_RC_OK)
1457 status = ICE_SUCCESS;
1459 status = ICE_ERR_AQ_ERROR;
1462 hw->adminq.sq_last_status = (enum ice_aq_err)retval;
1463 ice_release_lock(&hw->adminq.sq_lock);
1467 return ice_sq_send_cmd_retry(hw, &hw->adminq, desc, buf, buf_size, cd);
1472 * @hw: pointer to the HW struct
1473 * @cd: pointer to command details structure or NULL
1475 * Get the firmware version (0x0001) from the admin queue commands
1477 enum ice_status ice_aq_get_fw_ver(struct ice_hw *hw, struct ice_sq_cd *cd)
1479 struct ice_aqc_get_ver *resp;
1480 struct ice_aq_desc desc;
1481 enum ice_status status;
1483 resp = &desc.params.get_ver;
1485 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_ver);
1487 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
1490 hw->fw_branch = resp->fw_branch;
1491 hw->fw_maj_ver = resp->fw_major;
1492 hw->fw_min_ver = resp->fw_minor;
1493 hw->fw_patch = resp->fw_patch;
1494 hw->fw_build = LE32_TO_CPU(resp->fw_build);
1495 hw->api_branch = resp->api_branch;
1496 hw->api_maj_ver = resp->api_major;
1497 hw->api_min_ver = resp->api_minor;
1498 hw->api_patch = resp->api_patch;
1505 * ice_aq_send_driver_ver
1506 * @hw: pointer to the HW struct
1507 * @dv: driver's major, minor version
1508 * @cd: pointer to command details structure or NULL
1510 * Send the driver version (0x0002) to the firmware
1513 ice_aq_send_driver_ver(struct ice_hw *hw, struct ice_driver_ver *dv,
1514 struct ice_sq_cd *cd)
1516 struct ice_aqc_driver_ver *cmd;
1517 struct ice_aq_desc desc;
1520 cmd = &desc.params.driver_ver;
1523 return ICE_ERR_PARAM;
1525 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_driver_ver);
1527 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
1528 cmd->major_ver = dv->major_ver;
1529 cmd->minor_ver = dv->minor_ver;
1530 cmd->build_ver = dv->build_ver;
1531 cmd->subbuild_ver = dv->subbuild_ver;
1534 while (len < sizeof(dv->driver_string) &&
1535 IS_ASCII(dv->driver_string[len]) && dv->driver_string[len])
1538 return ice_aq_send_cmd(hw, &desc, dv->driver_string, len, cd);
1543 * @hw: pointer to the HW struct
1544 * @unloading: is the driver unloading itself
1546 * Tell the Firmware that we're shutting down the AdminQ and whether
1547 * or not the driver is unloading as well (0x0003).
1549 enum ice_status ice_aq_q_shutdown(struct ice_hw *hw, bool unloading)
1551 struct ice_aqc_q_shutdown *cmd;
1552 struct ice_aq_desc desc;
1554 cmd = &desc.params.q_shutdown;
1556 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_q_shutdown);
1559 cmd->driver_unloading = ICE_AQC_DRIVER_UNLOADING;
1561 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
1566 * @hw: pointer to the HW struct
1568 * @access: access type
1569 * @sdp_number: resource number
1570 * @timeout: the maximum time in ms that the driver may hold the resource
1571 * @cd: pointer to command details structure or NULL
1573 * Requests common resource using the admin queue commands (0x0008).
1574 * When attempting to acquire the Global Config Lock, the driver can
1575 * learn of three states:
1576 * 1) ICE_SUCCESS - acquired lock, and can perform download package
1577 * 2) ICE_ERR_AQ_ERROR - did not get lock, driver should fail to load
1578 * 3) ICE_ERR_AQ_NO_WORK - did not get lock, but another driver has
1579 * successfully downloaded the package; the driver does
1580 * not have to download the package and can continue
1583 * Note that if the caller is in an acquire lock, perform action, release lock
1584 * phase of operation, it is possible that the FW may detect a timeout and issue
1585 * a CORER. In this case, the driver will receive a CORER interrupt and will
1586 * have to determine its cause. The calling thread that is handling this flow
1587 * will likely get an error propagated back to it indicating the Download
1588 * Package, Update Package or the Release Resource AQ commands timed out.
1590 static enum ice_status
1591 ice_aq_req_res(struct ice_hw *hw, enum ice_aq_res_ids res,
1592 enum ice_aq_res_access_type access, u8 sdp_number, u32 *timeout,
1593 struct ice_sq_cd *cd)
1595 struct ice_aqc_req_res *cmd_resp;
1596 struct ice_aq_desc desc;
1597 enum ice_status status;
1599 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
1601 cmd_resp = &desc.params.res_owner;
1603 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_req_res);
1605 cmd_resp->res_id = CPU_TO_LE16(res);
1606 cmd_resp->access_type = CPU_TO_LE16(access);
1607 cmd_resp->res_number = CPU_TO_LE32(sdp_number);
1608 cmd_resp->timeout = CPU_TO_LE32(*timeout);
1611 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
1613 /* The completion specifies the maximum time in ms that the driver
1614 * may hold the resource in the Timeout field.
1617 /* Global config lock response utilizes an additional status field.
1619 * If the Global config lock resource is held by some other driver, the
1620 * command completes with ICE_AQ_RES_GLBL_IN_PROG in the status field
1621 * and the timeout field indicates the maximum time the current owner
1622 * of the resource has to free it.
1624 if (res == ICE_GLOBAL_CFG_LOCK_RES_ID) {
1625 if (LE16_TO_CPU(cmd_resp->status) == ICE_AQ_RES_GLBL_SUCCESS) {
1626 *timeout = LE32_TO_CPU(cmd_resp->timeout);
1628 } else if (LE16_TO_CPU(cmd_resp->status) ==
1629 ICE_AQ_RES_GLBL_IN_PROG) {
1630 *timeout = LE32_TO_CPU(cmd_resp->timeout);
1631 return ICE_ERR_AQ_ERROR;
1632 } else if (LE16_TO_CPU(cmd_resp->status) ==
1633 ICE_AQ_RES_GLBL_DONE) {
1634 return ICE_ERR_AQ_NO_WORK;
1637 /* invalid FW response, force a timeout immediately */
1639 return ICE_ERR_AQ_ERROR;
1642 /* If the resource is held by some other driver, the command completes
1643 * with a busy return value and the timeout field indicates the maximum
1644 * time the current owner of the resource has to free it.
1646 if (!status || hw->adminq.sq_last_status == ICE_AQ_RC_EBUSY)
1647 *timeout = LE32_TO_CPU(cmd_resp->timeout);
1653 * ice_aq_release_res
1654 * @hw: pointer to the HW struct
1656 * @sdp_number: resource number
1657 * @cd: pointer to command details structure or NULL
1659 * release common resource using the admin queue commands (0x0009)
1661 static enum ice_status
1662 ice_aq_release_res(struct ice_hw *hw, enum ice_aq_res_ids res, u8 sdp_number,
1663 struct ice_sq_cd *cd)
1665 struct ice_aqc_req_res *cmd;
1666 struct ice_aq_desc desc;
1668 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
1670 cmd = &desc.params.res_owner;
1672 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_release_res);
1674 cmd->res_id = CPU_TO_LE16(res);
1675 cmd->res_number = CPU_TO_LE32(sdp_number);
1677 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
1682 * @hw: pointer to the HW structure
1684 * @access: access type (read or write)
1685 * @timeout: timeout in milliseconds
1687 * This function will attempt to acquire the ownership of a resource.
1690 ice_acquire_res(struct ice_hw *hw, enum ice_aq_res_ids res,
1691 enum ice_aq_res_access_type access, u32 timeout)
1693 #define ICE_RES_POLLING_DELAY_MS 10
1694 u32 delay = ICE_RES_POLLING_DELAY_MS;
1695 u32 time_left = timeout;
1696 enum ice_status status;
1698 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
1700 status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL);
1702 /* A return code of ICE_ERR_AQ_NO_WORK means that another driver has
1703 * previously acquired the resource and performed any necessary updates;
1704 * in this case the caller does not obtain the resource and has no
1705 * further work to do.
1707 if (status == ICE_ERR_AQ_NO_WORK)
1708 goto ice_acquire_res_exit;
1711 ice_debug(hw, ICE_DBG_RES, "resource %d acquire type %d failed.\n", res, access);
1713 /* If necessary, poll until the current lock owner timeouts */
1714 timeout = time_left;
1715 while (status && timeout && time_left) {
1716 ice_msec_delay(delay, true);
1717 timeout = (timeout > delay) ? timeout - delay : 0;
1718 status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL);
1720 if (status == ICE_ERR_AQ_NO_WORK)
1721 /* lock free, but no work to do */
1728 if (status && status != ICE_ERR_AQ_NO_WORK)
1729 ice_debug(hw, ICE_DBG_RES, "resource acquire timed out.\n");
1731 ice_acquire_res_exit:
1732 if (status == ICE_ERR_AQ_NO_WORK) {
1733 if (access == ICE_RES_WRITE)
1734 ice_debug(hw, ICE_DBG_RES, "resource indicates no work to do.\n");
1736 ice_debug(hw, ICE_DBG_RES, "Warning: ICE_ERR_AQ_NO_WORK not expected\n");
1743 * @hw: pointer to the HW structure
1746 * This function will release a resource using the proper Admin Command.
1748 void ice_release_res(struct ice_hw *hw, enum ice_aq_res_ids res)
1750 enum ice_status status;
1751 u32 total_delay = 0;
1753 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
1755 status = ice_aq_release_res(hw, res, 0, NULL);
1757 /* there are some rare cases when trying to release the resource
1758 * results in an admin queue timeout, so handle them correctly
1760 while ((status == ICE_ERR_AQ_TIMEOUT) &&
1761 (total_delay < hw->adminq.sq_cmd_timeout)) {
1762 ice_msec_delay(1, true);
1763 status = ice_aq_release_res(hw, res, 0, NULL);
1769 * ice_aq_alloc_free_res - command to allocate/free resources
1770 * @hw: pointer to the HW struct
1771 * @num_entries: number of resource entries in buffer
1772 * @buf: Indirect buffer to hold data parameters and response
1773 * @buf_size: size of buffer for indirect commands
1774 * @opc: pass in the command opcode
1775 * @cd: pointer to command details structure or NULL
1777 * Helper function to allocate/free resources using the admin queue commands
1780 ice_aq_alloc_free_res(struct ice_hw *hw, u16 num_entries,
1781 struct ice_aqc_alloc_free_res_elem *buf, u16 buf_size,
1782 enum ice_adminq_opc opc, struct ice_sq_cd *cd)
1784 struct ice_aqc_alloc_free_res_cmd *cmd;
1785 struct ice_aq_desc desc;
1787 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
1789 cmd = &desc.params.sw_res_ctrl;
1792 return ICE_ERR_PARAM;
1794 if (buf_size < FLEX_ARRAY_SIZE(buf, elem, num_entries))
1795 return ICE_ERR_PARAM;
1797 ice_fill_dflt_direct_cmd_desc(&desc, opc);
1799 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
1801 cmd->num_entries = CPU_TO_LE16(num_entries);
1803 return ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);
1807 * ice_alloc_hw_res - allocate resource
1808 * @hw: pointer to the HW struct
1809 * @type: type of resource
1810 * @num: number of resources to allocate
1811 * @btm: allocate from bottom
1812 * @res: pointer to array that will receive the resources
1815 ice_alloc_hw_res(struct ice_hw *hw, u16 type, u16 num, bool btm, u16 *res)
1817 struct ice_aqc_alloc_free_res_elem *buf;
1818 enum ice_status status;
1821 buf_len = ice_struct_size(buf, elem, num);
1822 buf = (struct ice_aqc_alloc_free_res_elem *)ice_malloc(hw, buf_len);
1824 return ICE_ERR_NO_MEMORY;
1826 /* Prepare buffer to allocate resource. */
1827 buf->num_elems = CPU_TO_LE16(num);
1828 buf->res_type = CPU_TO_LE16(type | ICE_AQC_RES_TYPE_FLAG_DEDICATED |
1829 ICE_AQC_RES_TYPE_FLAG_IGNORE_INDEX);
1831 buf->res_type |= CPU_TO_LE16(ICE_AQC_RES_TYPE_FLAG_SCAN_BOTTOM);
1833 status = ice_aq_alloc_free_res(hw, 1, buf, buf_len,
1834 ice_aqc_opc_alloc_res, NULL);
1836 goto ice_alloc_res_exit;
1838 ice_memcpy(res, buf->elem, sizeof(*buf->elem) * num,
1839 ICE_NONDMA_TO_NONDMA);
1847 * ice_free_hw_res - free allocated HW resource
1848 * @hw: pointer to the HW struct
1849 * @type: type of resource to free
1850 * @num: number of resources
1851 * @res: pointer to array that contains the resources to free
1853 enum ice_status ice_free_hw_res(struct ice_hw *hw, u16 type, u16 num, u16 *res)
1855 struct ice_aqc_alloc_free_res_elem *buf;
1856 enum ice_status status;
1859 buf_len = ice_struct_size(buf, elem, num);
1860 buf = (struct ice_aqc_alloc_free_res_elem *)ice_malloc(hw, buf_len);
1862 return ICE_ERR_NO_MEMORY;
1864 /* Prepare buffer to free resource. */
1865 buf->num_elems = CPU_TO_LE16(num);
1866 buf->res_type = CPU_TO_LE16(type);
1867 ice_memcpy(buf->elem, res, sizeof(*buf->elem) * num,
1868 ICE_NONDMA_TO_NONDMA);
1870 status = ice_aq_alloc_free_res(hw, num, buf, buf_len,
1871 ice_aqc_opc_free_res, NULL);
1873 ice_debug(hw, ICE_DBG_SW, "CQ CMD Buffer:\n");
1880 * ice_get_num_per_func - determine number of resources per PF
1881 * @hw: pointer to the HW structure
1882 * @max: value to be evenly split between each PF
1884 * Determine the number of valid functions by going through the bitmap returned
1885 * from parsing capabilities and use this to calculate the number of resources
1886 * per PF based on the max value passed in.
1888 static u32 ice_get_num_per_func(struct ice_hw *hw, u32 max)
1892 #define ICE_CAPS_VALID_FUNCS_M 0xFF
1893 funcs = ice_hweight8(hw->dev_caps.common_cap.valid_functions &
1894 ICE_CAPS_VALID_FUNCS_M);
1903 * ice_parse_common_caps - parse common device/function capabilities
1904 * @hw: pointer to the HW struct
1905 * @caps: pointer to common capabilities structure
1906 * @elem: the capability element to parse
1907 * @prefix: message prefix for tracing capabilities
1909 * Given a capability element, extract relevant details into the common
1910 * capability structure.
1912 * Returns: true if the capability matches one of the common capability ids,
1916 ice_parse_common_caps(struct ice_hw *hw, struct ice_hw_common_caps *caps,
1917 struct ice_aqc_list_caps_elem *elem, const char *prefix)
1919 u32 logical_id = LE32_TO_CPU(elem->logical_id);
1920 u32 phys_id = LE32_TO_CPU(elem->phys_id);
1921 u32 number = LE32_TO_CPU(elem->number);
1922 u16 cap = LE16_TO_CPU(elem->cap);
1926 case ICE_AQC_CAPS_VALID_FUNCTIONS:
1927 caps->valid_functions = number;
1928 ice_debug(hw, ICE_DBG_INIT, "%s: valid_functions (bitmap) = %d\n", prefix,
1929 caps->valid_functions);
1931 case ICE_AQC_CAPS_DCB:
1932 caps->dcb = (number == 1);
1933 caps->active_tc_bitmap = logical_id;
1934 caps->maxtc = phys_id;
1935 ice_debug(hw, ICE_DBG_INIT, "%s: dcb = %d\n", prefix, caps->dcb);
1936 ice_debug(hw, ICE_DBG_INIT, "%s: active_tc_bitmap = %d\n", prefix,
1937 caps->active_tc_bitmap);
1938 ice_debug(hw, ICE_DBG_INIT, "%s: maxtc = %d\n", prefix, caps->maxtc);
1940 case ICE_AQC_CAPS_RSS:
1941 caps->rss_table_size = number;
1942 caps->rss_table_entry_width = logical_id;
1943 ice_debug(hw, ICE_DBG_INIT, "%s: rss_table_size = %d\n", prefix,
1944 caps->rss_table_size);
1945 ice_debug(hw, ICE_DBG_INIT, "%s: rss_table_entry_width = %d\n", prefix,
1946 caps->rss_table_entry_width);
1948 case ICE_AQC_CAPS_RXQS:
1949 caps->num_rxq = number;
1950 caps->rxq_first_id = phys_id;
1951 ice_debug(hw, ICE_DBG_INIT, "%s: num_rxq = %d\n", prefix,
1953 ice_debug(hw, ICE_DBG_INIT, "%s: rxq_first_id = %d\n", prefix,
1954 caps->rxq_first_id);
1956 case ICE_AQC_CAPS_TXQS:
1957 caps->num_txq = number;
1958 caps->txq_first_id = phys_id;
1959 ice_debug(hw, ICE_DBG_INIT, "%s: num_txq = %d\n", prefix,
1961 ice_debug(hw, ICE_DBG_INIT, "%s: txq_first_id = %d\n", prefix,
1962 caps->txq_first_id);
1964 case ICE_AQC_CAPS_MSIX:
1965 caps->num_msix_vectors = number;
1966 caps->msix_vector_first_id = phys_id;
1967 ice_debug(hw, ICE_DBG_INIT, "%s: num_msix_vectors = %d\n", prefix,
1968 caps->num_msix_vectors);
1969 ice_debug(hw, ICE_DBG_INIT, "%s: msix_vector_first_id = %d\n", prefix,
1970 caps->msix_vector_first_id);
1972 case ICE_AQC_CAPS_NVM_MGMT:
1973 caps->sec_rev_disabled =
1974 (number & ICE_NVM_MGMT_SEC_REV_DISABLED) ?
1976 ice_debug(hw, ICE_DBG_INIT, "%s: sec_rev_disabled = %d\n", prefix,
1977 caps->sec_rev_disabled);
1978 caps->update_disabled =
1979 (number & ICE_NVM_MGMT_UPDATE_DISABLED) ?
1981 ice_debug(hw, ICE_DBG_INIT, "%s: update_disabled = %d\n", prefix,
1982 caps->update_disabled);
1983 caps->nvm_unified_update =
1984 (number & ICE_NVM_MGMT_UNIFIED_UPD_SUPPORT) ?
1986 ice_debug(hw, ICE_DBG_INIT, "%s: nvm_unified_update = %d\n", prefix,
1987 caps->nvm_unified_update);
1989 case ICE_AQC_CAPS_MAX_MTU:
1990 caps->max_mtu = number;
1991 ice_debug(hw, ICE_DBG_INIT, "%s: max_mtu = %d\n",
1992 prefix, caps->max_mtu);
1995 /* Not one of the recognized common capabilities */
2003 * ice_recalc_port_limited_caps - Recalculate port limited capabilities
2004 * @hw: pointer to the HW structure
2005 * @caps: pointer to capabilities structure to fix
2007 * Re-calculate the capabilities that are dependent on the number of physical
2008 * ports; i.e. some features are not supported or function differently on
2009 * devices with more than 4 ports.
2012 ice_recalc_port_limited_caps(struct ice_hw *hw, struct ice_hw_common_caps *caps)
2014 /* This assumes device capabilities are always scanned before function
2015 * capabilities during the initialization flow.
2017 if (hw->dev_caps.num_funcs > 4) {
2018 /* Max 4 TCs per port */
2020 ice_debug(hw, ICE_DBG_INIT, "reducing maxtc to %d (based on #ports)\n",
2026 * ice_parse_vsi_func_caps - Parse ICE_AQC_CAPS_VSI function caps
2027 * @hw: pointer to the HW struct
2028 * @func_p: pointer to function capabilities structure
2029 * @cap: pointer to the capability element to parse
2031 * Extract function capabilities for ICE_AQC_CAPS_VSI.
2034 ice_parse_vsi_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p,
2035 struct ice_aqc_list_caps_elem *cap)
2037 func_p->guar_num_vsi = ice_get_num_per_func(hw, ICE_MAX_VSI);
2038 ice_debug(hw, ICE_DBG_INIT, "func caps: guar_num_vsi (fw) = %d\n",
2039 LE32_TO_CPU(cap->number));
2040 ice_debug(hw, ICE_DBG_INIT, "func caps: guar_num_vsi = %d\n",
2041 func_p->guar_num_vsi);
2045 * ice_parse_fdir_func_caps - Parse ICE_AQC_CAPS_FD function caps
2046 * @hw: pointer to the HW struct
2047 * @func_p: pointer to function capabilities structure
2049 * Extract function capabilities for ICE_AQC_CAPS_FD.
2052 ice_parse_fdir_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p)
2056 if (hw->dcf_enabled)
2058 reg_val = rd32(hw, GLQF_FD_SIZE);
2059 val = (reg_val & GLQF_FD_SIZE_FD_GSIZE_M) >>
2060 GLQF_FD_SIZE_FD_GSIZE_S;
2061 func_p->fd_fltr_guar =
2062 ice_get_num_per_func(hw, val);
2063 val = (reg_val & GLQF_FD_SIZE_FD_BSIZE_M) >>
2064 GLQF_FD_SIZE_FD_BSIZE_S;
2065 func_p->fd_fltr_best_effort = val;
2067 ice_debug(hw, ICE_DBG_INIT, "func caps: fd_fltr_guar = %d\n",
2068 func_p->fd_fltr_guar);
2069 ice_debug(hw, ICE_DBG_INIT, "func caps: fd_fltr_best_effort = %d\n",
2070 func_p->fd_fltr_best_effort);
2074 * ice_parse_func_caps - Parse function capabilities
2075 * @hw: pointer to the HW struct
2076 * @func_p: pointer to function capabilities structure
2077 * @buf: buffer containing the function capability records
2078 * @cap_count: the number of capabilities
2080 * Helper function to parse function (0x000A) capabilities list. For
2081 * capabilities shared between device and function, this relies on
2082 * ice_parse_common_caps.
2084 * Loop through the list of provided capabilities and extract the relevant
2085 * data into the function capabilities structured.
2088 ice_parse_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p,
2089 void *buf, u32 cap_count)
2091 struct ice_aqc_list_caps_elem *cap_resp;
2094 cap_resp = (struct ice_aqc_list_caps_elem *)buf;
2096 ice_memset(func_p, 0, sizeof(*func_p), ICE_NONDMA_MEM);
2098 for (i = 0; i < cap_count; i++) {
2099 u16 cap = LE16_TO_CPU(cap_resp[i].cap);
2102 found = ice_parse_common_caps(hw, &func_p->common_cap,
2103 &cap_resp[i], "func caps");
2106 case ICE_AQC_CAPS_VSI:
2107 ice_parse_vsi_func_caps(hw, func_p, &cap_resp[i]);
2109 case ICE_AQC_CAPS_FD:
2110 ice_parse_fdir_func_caps(hw, func_p);
2113 /* Don't list common capabilities as unknown */
2115 ice_debug(hw, ICE_DBG_INIT, "func caps: unknown capability[%d]: 0x%x\n",
2121 ice_recalc_port_limited_caps(hw, &func_p->common_cap);
2125 * ice_parse_valid_functions_cap - Parse ICE_AQC_CAPS_VALID_FUNCTIONS caps
2126 * @hw: pointer to the HW struct
2127 * @dev_p: pointer to device capabilities structure
2128 * @cap: capability element to parse
2130 * Parse ICE_AQC_CAPS_VALID_FUNCTIONS for device capabilities.
2133 ice_parse_valid_functions_cap(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p,
2134 struct ice_aqc_list_caps_elem *cap)
2136 u32 number = LE32_TO_CPU(cap->number);
2138 dev_p->num_funcs = ice_hweight32(number);
2139 ice_debug(hw, ICE_DBG_INIT, "dev caps: num_funcs = %d\n",
2144 * ice_parse_vsi_dev_caps - Parse ICE_AQC_CAPS_VSI device caps
2145 * @hw: pointer to the HW struct
2146 * @dev_p: pointer to device capabilities structure
2147 * @cap: capability element to parse
2149 * Parse ICE_AQC_CAPS_VSI for device capabilities.
2152 ice_parse_vsi_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p,
2153 struct ice_aqc_list_caps_elem *cap)
2155 u32 number = LE32_TO_CPU(cap->number);
2157 dev_p->num_vsi_allocd_to_host = number;
2158 ice_debug(hw, ICE_DBG_INIT, "dev caps: num_vsi_allocd_to_host = %d\n",
2159 dev_p->num_vsi_allocd_to_host);
2163 * ice_parse_fdir_dev_caps - Parse ICE_AQC_CAPS_FD device caps
2164 * @hw: pointer to the HW struct
2165 * @dev_p: pointer to device capabilities structure
2166 * @cap: capability element to parse
2168 * Parse ICE_AQC_CAPS_FD for device capabilities.
2171 ice_parse_fdir_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p,
2172 struct ice_aqc_list_caps_elem *cap)
2174 u32 number = LE32_TO_CPU(cap->number);
2176 dev_p->num_flow_director_fltr = number;
2177 ice_debug(hw, ICE_DBG_INIT, "dev caps: num_flow_director_fltr = %d\n",
2178 dev_p->num_flow_director_fltr);
2182 * ice_parse_dev_caps - Parse device capabilities
2183 * @hw: pointer to the HW struct
2184 * @dev_p: pointer to device capabilities structure
2185 * @buf: buffer containing the device capability records
2186 * @cap_count: the number of capabilities
2188 * Helper device to parse device (0x000B) capabilities list. For
2189 * capabilities shared between device and function, this relies on
2190 * ice_parse_common_caps.
2192 * Loop through the list of provided capabilities and extract the relevant
2193 * data into the device capabilities structured.
2196 ice_parse_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p,
2197 void *buf, u32 cap_count)
2199 struct ice_aqc_list_caps_elem *cap_resp;
2202 cap_resp = (struct ice_aqc_list_caps_elem *)buf;
2204 ice_memset(dev_p, 0, sizeof(*dev_p), ICE_NONDMA_MEM);
2206 for (i = 0; i < cap_count; i++) {
2207 u16 cap = LE16_TO_CPU(cap_resp[i].cap);
2210 found = ice_parse_common_caps(hw, &dev_p->common_cap,
2211 &cap_resp[i], "dev caps");
2214 case ICE_AQC_CAPS_VALID_FUNCTIONS:
2215 ice_parse_valid_functions_cap(hw, dev_p, &cap_resp[i]);
2217 case ICE_AQC_CAPS_VSI:
2218 ice_parse_vsi_dev_caps(hw, dev_p, &cap_resp[i]);
2220 case ICE_AQC_CAPS_FD:
2221 ice_parse_fdir_dev_caps(hw, dev_p, &cap_resp[i]);
2224 /* Don't list common capabilities as unknown */
2226 ice_debug(hw, ICE_DBG_INIT, "dev caps: unknown capability[%d]: 0x%x\n",
2232 ice_recalc_port_limited_caps(hw, &dev_p->common_cap);
2236 * ice_aq_list_caps - query function/device capabilities
2237 * @hw: pointer to the HW struct
2238 * @buf: a buffer to hold the capabilities
2239 * @buf_size: size of the buffer
2240 * @cap_count: if not NULL, set to the number of capabilities reported
2241 * @opc: capabilities type to discover, device or function
2242 * @cd: pointer to command details structure or NULL
2244 * Get the function (0x000A) or device (0x000B) capabilities description from
2245 * firmware and store it in the buffer.
2247 * If the cap_count pointer is not NULL, then it is set to the number of
2248 * capabilities firmware will report. Note that if the buffer size is too
2249 * small, it is possible the command will return ICE_AQ_ERR_ENOMEM. The
2250 * cap_count will still be updated in this case. It is recommended that the
2251 * buffer size be set to ICE_AQ_MAX_BUF_LEN (the largest possible buffer that
2252 * firmware could return) to avoid this.
2254 static enum ice_status
2255 ice_aq_list_caps(struct ice_hw *hw, void *buf, u16 buf_size, u32 *cap_count,
2256 enum ice_adminq_opc opc, struct ice_sq_cd *cd)
2258 struct ice_aqc_list_caps *cmd;
2259 struct ice_aq_desc desc;
2260 enum ice_status status;
2262 cmd = &desc.params.get_cap;
2264 if (opc != ice_aqc_opc_list_func_caps &&
2265 opc != ice_aqc_opc_list_dev_caps)
2266 return ICE_ERR_PARAM;
2268 ice_fill_dflt_direct_cmd_desc(&desc, opc);
2269 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);
2272 *cap_count = LE32_TO_CPU(cmd->count);
2278 * ice_discover_dev_caps - Read and extract device capabilities
2279 * @hw: pointer to the hardware structure
2280 * @dev_caps: pointer to device capabilities structure
2282 * Read the device capabilities and extract them into the dev_caps structure
2285 static enum ice_status
2286 ice_discover_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_caps)
2288 enum ice_status status;
2292 cbuf = ice_malloc(hw, ICE_AQ_MAX_BUF_LEN);
2294 return ICE_ERR_NO_MEMORY;
2296 /* Although the driver doesn't know the number of capabilities the
2297 * device will return, we can simply send a 4KB buffer, the maximum
2298 * possible size that firmware can return.
2300 cap_count = ICE_AQ_MAX_BUF_LEN / sizeof(struct ice_aqc_list_caps_elem);
2302 status = ice_aq_list_caps(hw, cbuf, ICE_AQ_MAX_BUF_LEN, &cap_count,
2303 ice_aqc_opc_list_dev_caps, NULL);
2305 ice_parse_dev_caps(hw, dev_caps, cbuf, cap_count);
2312 * ice_discover_func_caps - Read and extract function capabilities
2313 * @hw: pointer to the hardware structure
2314 * @func_caps: pointer to function capabilities structure
2316 * Read the function capabilities and extract them into the func_caps structure
2319 static enum ice_status
2320 ice_discover_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_caps)
2322 enum ice_status status;
2326 cbuf = ice_malloc(hw, ICE_AQ_MAX_BUF_LEN);
2328 return ICE_ERR_NO_MEMORY;
2330 /* Although the driver doesn't know the number of capabilities the
2331 * device will return, we can simply send a 4KB buffer, the maximum
2332 * possible size that firmware can return.
2334 cap_count = ICE_AQ_MAX_BUF_LEN / sizeof(struct ice_aqc_list_caps_elem);
2336 status = ice_aq_list_caps(hw, cbuf, ICE_AQ_MAX_BUF_LEN, &cap_count,
2337 ice_aqc_opc_list_func_caps, NULL);
2339 ice_parse_func_caps(hw, func_caps, cbuf, cap_count);
2346 * ice_set_safe_mode_caps - Override dev/func capabilities when in safe mode
2347 * @hw: pointer to the hardware structure
2349 void ice_set_safe_mode_caps(struct ice_hw *hw)
2351 struct ice_hw_func_caps *func_caps = &hw->func_caps;
2352 struct ice_hw_dev_caps *dev_caps = &hw->dev_caps;
2353 struct ice_hw_common_caps cached_caps;
2356 /* cache some func_caps values that should be restored after memset */
2357 cached_caps = func_caps->common_cap;
2359 /* unset func capabilities */
2360 memset(func_caps, 0, sizeof(*func_caps));
2362 #define ICE_RESTORE_FUNC_CAP(name) \
2363 func_caps->common_cap.name = cached_caps.name
2365 /* restore cached values */
2366 ICE_RESTORE_FUNC_CAP(valid_functions);
2367 ICE_RESTORE_FUNC_CAP(txq_first_id);
2368 ICE_RESTORE_FUNC_CAP(rxq_first_id);
2369 ICE_RESTORE_FUNC_CAP(msix_vector_first_id);
2370 ICE_RESTORE_FUNC_CAP(max_mtu);
2371 ICE_RESTORE_FUNC_CAP(nvm_unified_update);
2373 /* one Tx and one Rx queue in safe mode */
2374 func_caps->common_cap.num_rxq = 1;
2375 func_caps->common_cap.num_txq = 1;
2377 /* two MSIX vectors, one for traffic and one for misc causes */
2378 func_caps->common_cap.num_msix_vectors = 2;
2379 func_caps->guar_num_vsi = 1;
2381 /* cache some dev_caps values that should be restored after memset */
2382 cached_caps = dev_caps->common_cap;
2383 num_funcs = dev_caps->num_funcs;
2385 /* unset dev capabilities */
2386 memset(dev_caps, 0, sizeof(*dev_caps));
2388 #define ICE_RESTORE_DEV_CAP(name) \
2389 dev_caps->common_cap.name = cached_caps.name
2391 /* restore cached values */
2392 ICE_RESTORE_DEV_CAP(valid_functions);
2393 ICE_RESTORE_DEV_CAP(txq_first_id);
2394 ICE_RESTORE_DEV_CAP(rxq_first_id);
2395 ICE_RESTORE_DEV_CAP(msix_vector_first_id);
2396 ICE_RESTORE_DEV_CAP(max_mtu);
2397 ICE_RESTORE_DEV_CAP(nvm_unified_update);
2398 dev_caps->num_funcs = num_funcs;
2400 /* one Tx and one Rx queue per function in safe mode */
2401 dev_caps->common_cap.num_rxq = num_funcs;
2402 dev_caps->common_cap.num_txq = num_funcs;
2404 /* two MSIX vectors per function */
2405 dev_caps->common_cap.num_msix_vectors = 2 * num_funcs;
2409 * ice_get_caps - get info about the HW
2410 * @hw: pointer to the hardware structure
2412 enum ice_status ice_get_caps(struct ice_hw *hw)
2414 enum ice_status status;
2416 status = ice_discover_dev_caps(hw, &hw->dev_caps);
2420 return ice_discover_func_caps(hw, &hw->func_caps);
2424 * ice_aq_manage_mac_write - manage MAC address write command
2425 * @hw: pointer to the HW struct
2426 * @mac_addr: MAC address to be written as LAA/LAA+WoL/Port address
2427 * @flags: flags to control write behavior
2428 * @cd: pointer to command details structure or NULL
2430 * This function is used to write MAC address to the NVM (0x0108).
2433 ice_aq_manage_mac_write(struct ice_hw *hw, const u8 *mac_addr, u8 flags,
2434 struct ice_sq_cd *cd)
2436 struct ice_aqc_manage_mac_write *cmd;
2437 struct ice_aq_desc desc;
2439 cmd = &desc.params.mac_write;
2440 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_write);
2443 ice_memcpy(cmd->mac_addr, mac_addr, ETH_ALEN, ICE_NONDMA_TO_NONDMA);
2445 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
2449 * ice_aq_clear_pxe_mode
2450 * @hw: pointer to the HW struct
2452 * Tell the firmware that the driver is taking over from PXE (0x0110).
2454 static enum ice_status ice_aq_clear_pxe_mode(struct ice_hw *hw)
2456 struct ice_aq_desc desc;
2458 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pxe_mode);
2459 desc.params.clear_pxe.rx_cnt = ICE_AQC_CLEAR_PXE_RX_CNT;
2461 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
2465 * ice_clear_pxe_mode - clear pxe operations mode
2466 * @hw: pointer to the HW struct
2468 * Make sure all PXE mode settings are cleared, including things
2469 * like descriptor fetch/write-back mode.
2471 void ice_clear_pxe_mode(struct ice_hw *hw)
2473 if (ice_check_sq_alive(hw, &hw->adminq))
2474 ice_aq_clear_pxe_mode(hw);
2478 * ice_aq_set_port_params - set physical port parameters.
2479 * @pi: pointer to the port info struct
2480 * @bad_frame_vsi: defines the VSI to which bad frames are forwarded
2481 * @save_bad_pac: if set packets with errors are forwarded to the bad frames VSI
2482 * @pad_short_pac: if set transmit packets smaller than 60 bytes are padded
2483 * @double_vlan: if set double VLAN is enabled
2484 * @cd: pointer to command details structure or NULL
2486 * Set Physical port parameters (0x0203)
2489 ice_aq_set_port_params(struct ice_port_info *pi, u16 bad_frame_vsi,
2490 bool save_bad_pac, bool pad_short_pac, bool double_vlan,
2491 struct ice_sq_cd *cd)
2494 struct ice_aqc_set_port_params *cmd;
2495 struct ice_hw *hw = pi->hw;
2496 struct ice_aq_desc desc;
2499 cmd = &desc.params.set_port_params;
2501 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_port_params);
2502 cmd->bad_frame_vsi = CPU_TO_LE16(bad_frame_vsi);
2504 cmd_flags |= ICE_AQC_SET_P_PARAMS_SAVE_BAD_PACKETS;
2506 cmd_flags |= ICE_AQC_SET_P_PARAMS_PAD_SHORT_PACKETS;
2508 cmd_flags |= ICE_AQC_SET_P_PARAMS_DOUBLE_VLAN_ENA;
2509 cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
2511 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
2515 * ice_get_link_speed_based_on_phy_type - returns link speed
2516 * @phy_type_low: lower part of phy_type
2517 * @phy_type_high: higher part of phy_type
2519 * This helper function will convert an entry in PHY type structure
2520 * [phy_type_low, phy_type_high] to its corresponding link speed.
2521 * Note: In the structure of [phy_type_low, phy_type_high], there should
2522 * be one bit set, as this function will convert one PHY type to its
2524 * If no bit gets set, ICE_LINK_SPEED_UNKNOWN will be returned
2525 * If more than one bit gets set, ICE_LINK_SPEED_UNKNOWN will be returned
2528 ice_get_link_speed_based_on_phy_type(u64 phy_type_low, u64 phy_type_high)
2530 u16 speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN;
2531 u16 speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN;
2533 switch (phy_type_low) {
2534 case ICE_PHY_TYPE_LOW_100BASE_TX:
2535 case ICE_PHY_TYPE_LOW_100M_SGMII:
2536 speed_phy_type_low = ICE_AQ_LINK_SPEED_100MB;
2538 case ICE_PHY_TYPE_LOW_1000BASE_T:
2539 case ICE_PHY_TYPE_LOW_1000BASE_SX:
2540 case ICE_PHY_TYPE_LOW_1000BASE_LX:
2541 case ICE_PHY_TYPE_LOW_1000BASE_KX:
2542 case ICE_PHY_TYPE_LOW_1G_SGMII:
2543 speed_phy_type_low = ICE_AQ_LINK_SPEED_1000MB;
2545 case ICE_PHY_TYPE_LOW_2500BASE_T:
2546 case ICE_PHY_TYPE_LOW_2500BASE_X:
2547 case ICE_PHY_TYPE_LOW_2500BASE_KX:
2548 speed_phy_type_low = ICE_AQ_LINK_SPEED_2500MB;
2550 case ICE_PHY_TYPE_LOW_5GBASE_T:
2551 case ICE_PHY_TYPE_LOW_5GBASE_KR:
2552 speed_phy_type_low = ICE_AQ_LINK_SPEED_5GB;
2554 case ICE_PHY_TYPE_LOW_10GBASE_T:
2555 case ICE_PHY_TYPE_LOW_10G_SFI_DA:
2556 case ICE_PHY_TYPE_LOW_10GBASE_SR:
2557 case ICE_PHY_TYPE_LOW_10GBASE_LR:
2558 case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1:
2559 case ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC:
2560 case ICE_PHY_TYPE_LOW_10G_SFI_C2C:
2561 speed_phy_type_low = ICE_AQ_LINK_SPEED_10GB;
2563 case ICE_PHY_TYPE_LOW_25GBASE_T:
2564 case ICE_PHY_TYPE_LOW_25GBASE_CR:
2565 case ICE_PHY_TYPE_LOW_25GBASE_CR_S:
2566 case ICE_PHY_TYPE_LOW_25GBASE_CR1:
2567 case ICE_PHY_TYPE_LOW_25GBASE_SR:
2568 case ICE_PHY_TYPE_LOW_25GBASE_LR:
2569 case ICE_PHY_TYPE_LOW_25GBASE_KR:
2570 case ICE_PHY_TYPE_LOW_25GBASE_KR_S:
2571 case ICE_PHY_TYPE_LOW_25GBASE_KR1:
2572 case ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC:
2573 case ICE_PHY_TYPE_LOW_25G_AUI_C2C:
2574 speed_phy_type_low = ICE_AQ_LINK_SPEED_25GB;
2576 case ICE_PHY_TYPE_LOW_40GBASE_CR4:
2577 case ICE_PHY_TYPE_LOW_40GBASE_SR4:
2578 case ICE_PHY_TYPE_LOW_40GBASE_LR4:
2579 case ICE_PHY_TYPE_LOW_40GBASE_KR4:
2580 case ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC:
2581 case ICE_PHY_TYPE_LOW_40G_XLAUI:
2582 speed_phy_type_low = ICE_AQ_LINK_SPEED_40GB;
2584 case ICE_PHY_TYPE_LOW_50GBASE_CR2:
2585 case ICE_PHY_TYPE_LOW_50GBASE_SR2:
2586 case ICE_PHY_TYPE_LOW_50GBASE_LR2:
2587 case ICE_PHY_TYPE_LOW_50GBASE_KR2:
2588 case ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC:
2589 case ICE_PHY_TYPE_LOW_50G_LAUI2:
2590 case ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC:
2591 case ICE_PHY_TYPE_LOW_50G_AUI2:
2592 case ICE_PHY_TYPE_LOW_50GBASE_CP:
2593 case ICE_PHY_TYPE_LOW_50GBASE_SR:
2594 case ICE_PHY_TYPE_LOW_50GBASE_FR:
2595 case ICE_PHY_TYPE_LOW_50GBASE_LR:
2596 case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4:
2597 case ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC:
2598 case ICE_PHY_TYPE_LOW_50G_AUI1:
2599 speed_phy_type_low = ICE_AQ_LINK_SPEED_50GB;
2601 case ICE_PHY_TYPE_LOW_100GBASE_CR4:
2602 case ICE_PHY_TYPE_LOW_100GBASE_SR4:
2603 case ICE_PHY_TYPE_LOW_100GBASE_LR4:
2604 case ICE_PHY_TYPE_LOW_100GBASE_KR4:
2605 case ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC:
2606 case ICE_PHY_TYPE_LOW_100G_CAUI4:
2607 case ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC:
2608 case ICE_PHY_TYPE_LOW_100G_AUI4:
2609 case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4:
2610 case ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4:
2611 case ICE_PHY_TYPE_LOW_100GBASE_CP2:
2612 case ICE_PHY_TYPE_LOW_100GBASE_SR2:
2613 case ICE_PHY_TYPE_LOW_100GBASE_DR:
2614 speed_phy_type_low = ICE_AQ_LINK_SPEED_100GB;
2617 speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN;
2621 switch (phy_type_high) {
2622 case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4:
2623 case ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC:
2624 case ICE_PHY_TYPE_HIGH_100G_CAUI2:
2625 case ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC:
2626 case ICE_PHY_TYPE_HIGH_100G_AUI2:
2627 speed_phy_type_high = ICE_AQ_LINK_SPEED_100GB;
2630 speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN;
2634 if (speed_phy_type_low == ICE_AQ_LINK_SPEED_UNKNOWN &&
2635 speed_phy_type_high == ICE_AQ_LINK_SPEED_UNKNOWN)
2636 return ICE_AQ_LINK_SPEED_UNKNOWN;
2637 else if (speed_phy_type_low != ICE_AQ_LINK_SPEED_UNKNOWN &&
2638 speed_phy_type_high != ICE_AQ_LINK_SPEED_UNKNOWN)
2639 return ICE_AQ_LINK_SPEED_UNKNOWN;
2640 else if (speed_phy_type_low != ICE_AQ_LINK_SPEED_UNKNOWN &&
2641 speed_phy_type_high == ICE_AQ_LINK_SPEED_UNKNOWN)
2642 return speed_phy_type_low;
2644 return speed_phy_type_high;
2648 * ice_update_phy_type
2649 * @phy_type_low: pointer to the lower part of phy_type
2650 * @phy_type_high: pointer to the higher part of phy_type
2651 * @link_speeds_bitmap: targeted link speeds bitmap
2653 * Note: For the link_speeds_bitmap structure, you can check it at
2654 * [ice_aqc_get_link_status->link_speed]. Caller can pass in
2655 * link_speeds_bitmap include multiple speeds.
2657 * Each entry in this [phy_type_low, phy_type_high] structure will
2658 * present a certain link speed. This helper function will turn on bits
2659 * in [phy_type_low, phy_type_high] structure based on the value of
2660 * link_speeds_bitmap input parameter.
2663 ice_update_phy_type(u64 *phy_type_low, u64 *phy_type_high,
2664 u16 link_speeds_bitmap)
2671 /* We first check with low part of phy_type */
2672 for (index = 0; index <= ICE_PHY_TYPE_LOW_MAX_INDEX; index++) {
2673 pt_low = BIT_ULL(index);
2674 speed = ice_get_link_speed_based_on_phy_type(pt_low, 0);
2676 if (link_speeds_bitmap & speed)
2677 *phy_type_low |= BIT_ULL(index);
2680 /* We then check with high part of phy_type */
2681 for (index = 0; index <= ICE_PHY_TYPE_HIGH_MAX_INDEX; index++) {
2682 pt_high = BIT_ULL(index);
2683 speed = ice_get_link_speed_based_on_phy_type(0, pt_high);
2685 if (link_speeds_bitmap & speed)
2686 *phy_type_high |= BIT_ULL(index);
2691 * ice_aq_set_phy_cfg
2692 * @hw: pointer to the HW struct
2693 * @pi: port info structure of the interested logical port
2694 * @cfg: structure with PHY configuration data to be set
2695 * @cd: pointer to command details structure or NULL
2697 * Set the various PHY configuration parameters supported on the Port.
2698 * One or more of the Set PHY config parameters may be ignored in an MFP
2699 * mode as the PF may not have the privilege to set some of the PHY Config
2700 * parameters. This status will be indicated by the command response (0x0601).
2703 ice_aq_set_phy_cfg(struct ice_hw *hw, struct ice_port_info *pi,
2704 struct ice_aqc_set_phy_cfg_data *cfg, struct ice_sq_cd *cd)
2706 struct ice_aq_desc desc;
2707 enum ice_status status;
2710 return ICE_ERR_PARAM;
2712 /* Ensure that only valid bits of cfg->caps can be turned on. */
2713 if (cfg->caps & ~ICE_AQ_PHY_ENA_VALID_MASK) {
2714 ice_debug(hw, ICE_DBG_PHY, "Invalid bit is set in ice_aqc_set_phy_cfg_data->caps : 0x%x\n",
2717 cfg->caps &= ICE_AQ_PHY_ENA_VALID_MASK;
2720 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_phy_cfg);
2721 desc.params.set_phy.lport_num = pi->lport;
2722 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
2724 ice_debug(hw, ICE_DBG_LINK, "set phy cfg\n");
2725 ice_debug(hw, ICE_DBG_LINK, " phy_type_low = 0x%llx\n",
2726 (unsigned long long)LE64_TO_CPU(cfg->phy_type_low));
2727 ice_debug(hw, ICE_DBG_LINK, " phy_type_high = 0x%llx\n",
2728 (unsigned long long)LE64_TO_CPU(cfg->phy_type_high));
2729 ice_debug(hw, ICE_DBG_LINK, " caps = 0x%x\n", cfg->caps);
2730 ice_debug(hw, ICE_DBG_LINK, " low_power_ctrl_an = 0x%x\n",
2731 cfg->low_power_ctrl_an);
2732 ice_debug(hw, ICE_DBG_LINK, " eee_cap = 0x%x\n", cfg->eee_cap);
2733 ice_debug(hw, ICE_DBG_LINK, " eeer_value = 0x%x\n", cfg->eeer_value);
2734 ice_debug(hw, ICE_DBG_LINK, " link_fec_opt = 0x%x\n",
2737 status = ice_aq_send_cmd(hw, &desc, cfg, sizeof(*cfg), cd);
2739 if (hw->adminq.sq_last_status == ICE_AQ_RC_EMODE)
2740 status = ICE_SUCCESS;
2743 pi->phy.curr_user_phy_cfg = *cfg;
2749 * ice_update_link_info - update status of the HW network link
2750 * @pi: port info structure of the interested logical port
2752 enum ice_status ice_update_link_info(struct ice_port_info *pi)
2754 struct ice_link_status *li;
2755 enum ice_status status;
2758 return ICE_ERR_PARAM;
2760 li = &pi->phy.link_info;
2762 status = ice_aq_get_link_info(pi, true, NULL, NULL);
2766 if (li->link_info & ICE_AQ_MEDIA_AVAILABLE) {
2767 struct ice_aqc_get_phy_caps_data *pcaps;
2771 pcaps = (struct ice_aqc_get_phy_caps_data *)
2772 ice_malloc(hw, sizeof(*pcaps));
2774 return ICE_ERR_NO_MEMORY;
2776 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_TOPO_CAP,
2779 if (status == ICE_SUCCESS)
2780 ice_memcpy(li->module_type, &pcaps->module_type,
2781 sizeof(li->module_type),
2782 ICE_NONDMA_TO_NONDMA);
2784 ice_free(hw, pcaps);
2791 * ice_cache_phy_user_req
2792 * @pi: port information structure
2793 * @cache_data: PHY logging data
2794 * @cache_mode: PHY logging mode
2796 * Log the user request on (FC, FEC, SPEED) for later user.
2799 ice_cache_phy_user_req(struct ice_port_info *pi,
2800 struct ice_phy_cache_mode_data cache_data,
2801 enum ice_phy_cache_mode cache_mode)
2806 switch (cache_mode) {
2808 pi->phy.curr_user_fc_req = cache_data.data.curr_user_fc_req;
2810 case ICE_SPEED_MODE:
2811 pi->phy.curr_user_speed_req =
2812 cache_data.data.curr_user_speed_req;
2815 pi->phy.curr_user_fec_req = cache_data.data.curr_user_fec_req;
2823 * ice_caps_to_fc_mode
2824 * @caps: PHY capabilities
2826 * Convert PHY FC capabilities to ice FC mode
2828 enum ice_fc_mode ice_caps_to_fc_mode(u8 caps)
2830 if (caps & ICE_AQC_PHY_EN_TX_LINK_PAUSE &&
2831 caps & ICE_AQC_PHY_EN_RX_LINK_PAUSE)
2834 if (caps & ICE_AQC_PHY_EN_TX_LINK_PAUSE)
2835 return ICE_FC_TX_PAUSE;
2837 if (caps & ICE_AQC_PHY_EN_RX_LINK_PAUSE)
2838 return ICE_FC_RX_PAUSE;
2844 * ice_caps_to_fec_mode
2845 * @caps: PHY capabilities
2846 * @fec_options: Link FEC options
2848 * Convert PHY FEC capabilities to ice FEC mode
2850 enum ice_fec_mode ice_caps_to_fec_mode(u8 caps, u8 fec_options)
2852 if (caps & ICE_AQC_PHY_EN_AUTO_FEC)
2853 return ICE_FEC_AUTO;
2855 if (fec_options & (ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN |
2856 ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ |
2857 ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN |
2858 ICE_AQC_PHY_FEC_25G_KR_REQ))
2859 return ICE_FEC_BASER;
2861 if (fec_options & (ICE_AQC_PHY_FEC_25G_RS_528_REQ |
2862 ICE_AQC_PHY_FEC_25G_RS_544_REQ |
2863 ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN))
2866 return ICE_FEC_NONE;
2870 * ice_cfg_phy_fc - Configure PHY FC data based on FC mode
2871 * @pi: port information structure
2872 * @cfg: PHY configuration data to set FC mode
2873 * @req_mode: FC mode to configure
2875 static enum ice_status
2876 ice_cfg_phy_fc(struct ice_port_info *pi, struct ice_aqc_set_phy_cfg_data *cfg,
2877 enum ice_fc_mode req_mode)
2879 struct ice_phy_cache_mode_data cache_data;
2880 u8 pause_mask = 0x0;
2883 return ICE_ERR_BAD_PTR;
2888 struct ice_aqc_get_phy_caps_data *pcaps;
2889 enum ice_status status;
2891 pcaps = (struct ice_aqc_get_phy_caps_data *)
2892 ice_malloc(pi->hw, sizeof(*pcaps));
2894 return ICE_ERR_NO_MEMORY;
2896 /* Query the value of FC that both the NIC and attached media
2899 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_TOPO_CAP,
2902 ice_free(pi->hw, pcaps);
2906 pause_mask |= pcaps->caps & ICE_AQC_PHY_EN_TX_LINK_PAUSE;
2907 pause_mask |= pcaps->caps & ICE_AQC_PHY_EN_RX_LINK_PAUSE;
2909 ice_free(pi->hw, pcaps);
2913 pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE;
2914 pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE;
2916 case ICE_FC_RX_PAUSE:
2917 pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE;
2919 case ICE_FC_TX_PAUSE:
2920 pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE;
2926 /* clear the old pause settings */
2927 cfg->caps &= ~(ICE_AQC_PHY_EN_TX_LINK_PAUSE |
2928 ICE_AQC_PHY_EN_RX_LINK_PAUSE);
2930 /* set the new capabilities */
2931 cfg->caps |= pause_mask;
2933 /* Cache user FC request */
2934 cache_data.data.curr_user_fc_req = req_mode;
2935 ice_cache_phy_user_req(pi, cache_data, ICE_FC_MODE);
2942 * @pi: port information structure
2943 * @aq_failures: pointer to status code, specific to ice_set_fc routine
2944 * @ena_auto_link_update: enable automatic link update
2946 * Set the requested flow control mode.
2949 ice_set_fc(struct ice_port_info *pi, u8 *aq_failures, bool ena_auto_link_update)
2951 struct ice_aqc_set_phy_cfg_data cfg = { 0 };
2952 struct ice_aqc_get_phy_caps_data *pcaps;
2953 enum ice_status status;
2956 if (!pi || !aq_failures)
2957 return ICE_ERR_BAD_PTR;
2962 pcaps = (struct ice_aqc_get_phy_caps_data *)
2963 ice_malloc(hw, sizeof(*pcaps));
2965 return ICE_ERR_NO_MEMORY;
2967 /* Get the current PHY config */
2968 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_SW_CFG, pcaps,
2971 *aq_failures = ICE_SET_FC_AQ_FAIL_GET;
2975 ice_copy_phy_caps_to_cfg(pi, pcaps, &cfg);
2977 /* Configure the set PHY data */
2978 status = ice_cfg_phy_fc(pi, &cfg, pi->fc.req_mode);
2980 if (status != ICE_ERR_BAD_PTR)
2981 *aq_failures = ICE_SET_FC_AQ_FAIL_GET;
2986 /* If the capabilities have changed, then set the new config */
2987 if (cfg.caps != pcaps->caps) {
2988 int retry_count, retry_max = 10;
2990 /* Auto restart link so settings take effect */
2991 if (ena_auto_link_update)
2992 cfg.caps |= ICE_AQ_PHY_ENA_AUTO_LINK_UPDT;
2994 status = ice_aq_set_phy_cfg(hw, pi, &cfg, NULL);
2996 *aq_failures = ICE_SET_FC_AQ_FAIL_SET;
3000 /* Update the link info
3001 * It sometimes takes a really long time for link to
3002 * come back from the atomic reset. Thus, we wait a
3005 for (retry_count = 0; retry_count < retry_max; retry_count++) {
3006 status = ice_update_link_info(pi);
3008 if (status == ICE_SUCCESS)
3011 ice_msec_delay(100, true);
3015 *aq_failures = ICE_SET_FC_AQ_FAIL_UPDATE;
3019 ice_free(hw, pcaps);
3024 * ice_phy_caps_equals_cfg
3025 * @phy_caps: PHY capabilities
3026 * @phy_cfg: PHY configuration
3028 * Helper function to determine if PHY capabilities matches PHY
3032 ice_phy_caps_equals_cfg(struct ice_aqc_get_phy_caps_data *phy_caps,
3033 struct ice_aqc_set_phy_cfg_data *phy_cfg)
3035 u8 caps_mask, cfg_mask;
3037 if (!phy_caps || !phy_cfg)
3040 /* These bits are not common between capabilities and configuration.
3041 * Do not use them to determine equality.
3043 caps_mask = ICE_AQC_PHY_CAPS_MASK & ~(ICE_AQC_PHY_AN_MODE |
3044 ICE_AQC_PHY_EN_MOD_QUAL);
3045 cfg_mask = ICE_AQ_PHY_ENA_VALID_MASK & ~ICE_AQ_PHY_ENA_AUTO_LINK_UPDT;
3047 if (phy_caps->phy_type_low != phy_cfg->phy_type_low ||
3048 phy_caps->phy_type_high != phy_cfg->phy_type_high ||
3049 ((phy_caps->caps & caps_mask) != (phy_cfg->caps & cfg_mask)) ||
3050 phy_caps->low_power_ctrl_an != phy_cfg->low_power_ctrl_an ||
3051 phy_caps->eee_cap != phy_cfg->eee_cap ||
3052 phy_caps->eeer_value != phy_cfg->eeer_value ||
3053 phy_caps->link_fec_options != phy_cfg->link_fec_opt)
3060 * ice_copy_phy_caps_to_cfg - Copy PHY ability data to configuration data
3061 * @pi: port information structure
3062 * @caps: PHY ability structure to copy date from
3063 * @cfg: PHY configuration structure to copy data to
3065 * Helper function to copy AQC PHY get ability data to PHY set configuration
3069 ice_copy_phy_caps_to_cfg(struct ice_port_info *pi,
3070 struct ice_aqc_get_phy_caps_data *caps,
3071 struct ice_aqc_set_phy_cfg_data *cfg)
3073 if (!pi || !caps || !cfg)
3076 ice_memset(cfg, 0, sizeof(*cfg), ICE_NONDMA_MEM);
3077 cfg->phy_type_low = caps->phy_type_low;
3078 cfg->phy_type_high = caps->phy_type_high;
3079 cfg->caps = caps->caps;
3080 cfg->low_power_ctrl_an = caps->low_power_ctrl_an;
3081 cfg->eee_cap = caps->eee_cap;
3082 cfg->eeer_value = caps->eeer_value;
3083 cfg->link_fec_opt = caps->link_fec_options;
3084 cfg->module_compliance_enforcement =
3085 caps->module_compliance_enforcement;
3087 if (ice_fw_supports_link_override(pi->hw)) {
3088 struct ice_link_default_override_tlv tlv;
3090 if (ice_get_link_default_override(&tlv, pi))
3093 if (tlv.options & ICE_LINK_OVERRIDE_STRICT_MODE)
3094 cfg->module_compliance_enforcement |=
3095 ICE_LINK_OVERRIDE_STRICT_MODE;
3100 * ice_cfg_phy_fec - Configure PHY FEC data based on FEC mode
3101 * @pi: port information structure
3102 * @cfg: PHY configuration data to set FEC mode
3103 * @fec: FEC mode to configure
3106 ice_cfg_phy_fec(struct ice_port_info *pi, struct ice_aqc_set_phy_cfg_data *cfg,
3107 enum ice_fec_mode fec)
3109 struct ice_aqc_get_phy_caps_data *pcaps;
3110 enum ice_status status = ICE_SUCCESS;
3114 return ICE_ERR_BAD_PTR;
3118 pcaps = (struct ice_aqc_get_phy_caps_data *)
3119 ice_malloc(hw, sizeof(*pcaps));
3121 return ICE_ERR_NO_MEMORY;
3123 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_TOPO_CAP, pcaps,
3128 cfg->caps |= (pcaps->caps & ICE_AQC_PHY_EN_AUTO_FEC);
3129 cfg->link_fec_opt = pcaps->link_fec_options;
3133 /* Clear RS bits, and AND BASE-R ability
3134 * bits and OR request bits.
3136 cfg->link_fec_opt &= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN |
3137 ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN;
3138 cfg->link_fec_opt |= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ |
3139 ICE_AQC_PHY_FEC_25G_KR_REQ;
3142 /* Clear BASE-R bits, and AND RS ability
3143 * bits and OR request bits.
3145 cfg->link_fec_opt &= ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN;
3146 cfg->link_fec_opt |= ICE_AQC_PHY_FEC_25G_RS_528_REQ |
3147 ICE_AQC_PHY_FEC_25G_RS_544_REQ;
3150 /* Clear all FEC option bits. */
3151 cfg->link_fec_opt &= ~ICE_AQC_PHY_FEC_MASK;
3154 /* AND auto FEC bit, and all caps bits. */
3155 cfg->caps &= ICE_AQC_PHY_CAPS_MASK;
3156 cfg->link_fec_opt |= pcaps->link_fec_options;
3159 status = ICE_ERR_PARAM;
3163 if (fec == ICE_FEC_AUTO && ice_fw_supports_link_override(pi->hw)) {
3164 struct ice_link_default_override_tlv tlv;
3166 if (ice_get_link_default_override(&tlv, pi))
3169 if (!(tlv.options & ICE_LINK_OVERRIDE_STRICT_MODE) &&
3170 (tlv.options & ICE_LINK_OVERRIDE_EN))
3171 cfg->link_fec_opt = tlv.fec_options;
3175 ice_free(hw, pcaps);
3181 * ice_get_link_status - get status of the HW network link
3182 * @pi: port information structure
3183 * @link_up: pointer to bool (true/false = linkup/linkdown)
3185 * Variable link_up is true if link is up, false if link is down.
3186 * The variable link_up is invalid if status is non zero. As a
3187 * result of this call, link status reporting becomes enabled
3189 enum ice_status ice_get_link_status(struct ice_port_info *pi, bool *link_up)
3191 struct ice_phy_info *phy_info;
3192 enum ice_status status = ICE_SUCCESS;
3194 if (!pi || !link_up)
3195 return ICE_ERR_PARAM;
3197 phy_info = &pi->phy;
3199 if (phy_info->get_link_info) {
3200 status = ice_update_link_info(pi);
3203 ice_debug(pi->hw, ICE_DBG_LINK, "get link status error, status = %d\n",
3207 *link_up = phy_info->link_info.link_info & ICE_AQ_LINK_UP;
3213 * ice_aq_set_link_restart_an
3214 * @pi: pointer to the port information structure
3215 * @ena_link: if true: enable link, if false: disable link
3216 * @cd: pointer to command details structure or NULL
3218 * Sets up the link and restarts the Auto-Negotiation over the link.
3221 ice_aq_set_link_restart_an(struct ice_port_info *pi, bool ena_link,
3222 struct ice_sq_cd *cd)
3224 struct ice_aqc_restart_an *cmd;
3225 struct ice_aq_desc desc;
3227 cmd = &desc.params.restart_an;
3229 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_restart_an);
3231 cmd->cmd_flags = ICE_AQC_RESTART_AN_LINK_RESTART;
3232 cmd->lport_num = pi->lport;
3234 cmd->cmd_flags |= ICE_AQC_RESTART_AN_LINK_ENABLE;
3236 cmd->cmd_flags &= ~ICE_AQC_RESTART_AN_LINK_ENABLE;
3238 return ice_aq_send_cmd(pi->hw, &desc, NULL, 0, cd);
3242 * ice_aq_set_event_mask
3243 * @hw: pointer to the HW struct
3244 * @port_num: port number of the physical function
3245 * @mask: event mask to be set
3246 * @cd: pointer to command details structure or NULL
3248 * Set event mask (0x0613)
3251 ice_aq_set_event_mask(struct ice_hw *hw, u8 port_num, u16 mask,
3252 struct ice_sq_cd *cd)
3254 struct ice_aqc_set_event_mask *cmd;
3255 struct ice_aq_desc desc;
3257 cmd = &desc.params.set_event_mask;
3259 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_event_mask);
3261 cmd->lport_num = port_num;
3263 cmd->event_mask = CPU_TO_LE16(mask);
3264 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
3268 * ice_aq_set_mac_loopback
3269 * @hw: pointer to the HW struct
3270 * @ena_lpbk: Enable or Disable loopback
3271 * @cd: pointer to command details structure or NULL
3273 * Enable/disable loopback on a given port
3276 ice_aq_set_mac_loopback(struct ice_hw *hw, bool ena_lpbk, struct ice_sq_cd *cd)
3278 struct ice_aqc_set_mac_lb *cmd;
3279 struct ice_aq_desc desc;
3281 cmd = &desc.params.set_mac_lb;
3283 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_mac_lb);
3285 cmd->lb_mode = ICE_AQ_MAC_LB_EN;
3287 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
3291 * ice_aq_set_port_id_led
3292 * @pi: pointer to the port information
3293 * @is_orig_mode: is this LED set to original mode (by the net-list)
3294 * @cd: pointer to command details structure or NULL
3296 * Set LED value for the given port (0x06e9)
3299 ice_aq_set_port_id_led(struct ice_port_info *pi, bool is_orig_mode,
3300 struct ice_sq_cd *cd)
3302 struct ice_aqc_set_port_id_led *cmd;
3303 struct ice_hw *hw = pi->hw;
3304 struct ice_aq_desc desc;
3306 cmd = &desc.params.set_port_id_led;
3308 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_port_id_led);
3311 cmd->ident_mode = ICE_AQC_PORT_IDENT_LED_ORIG;
3313 cmd->ident_mode = ICE_AQC_PORT_IDENT_LED_BLINK;
3315 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
3320 * @hw: pointer to the HW struct
3321 * @lport: bits [7:0] = logical port, bit [8] = logical port valid
3322 * @bus_addr: I2C bus address of the eeprom (typically 0xA0, 0=topo default)
3323 * @mem_addr: I2C offset. lower 8 bits for address, 8 upper bits zero padding.
3325 * @set_page: set or ignore the page
3326 * @data: pointer to data buffer to be read/written to the I2C device.
3327 * @length: 1-16 for read, 1 for write.
3328 * @write: 0 read, 1 for write.
3329 * @cd: pointer to command details structure or NULL
3331 * Read/Write SFF EEPROM (0x06EE)
3334 ice_aq_sff_eeprom(struct ice_hw *hw, u16 lport, u8 bus_addr,
3335 u16 mem_addr, u8 page, u8 set_page, u8 *data, u8 length,
3336 bool write, struct ice_sq_cd *cd)
3338 struct ice_aqc_sff_eeprom *cmd;
3339 struct ice_aq_desc desc;
3340 enum ice_status status;
3342 if (!data || (mem_addr & 0xff00))
3343 return ICE_ERR_PARAM;
3345 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_sff_eeprom);
3346 cmd = &desc.params.read_write_sff_param;
3347 desc.flags = CPU_TO_LE16(ICE_AQ_FLAG_RD);
3348 cmd->lport_num = (u8)(lport & 0xff);
3349 cmd->lport_num_valid = (u8)((lport >> 8) & 0x01);
3350 cmd->i2c_bus_addr = CPU_TO_LE16(((bus_addr >> 1) &
3351 ICE_AQC_SFF_I2CBUS_7BIT_M) |
3353 ICE_AQC_SFF_SET_EEPROM_PAGE_S) &
3354 ICE_AQC_SFF_SET_EEPROM_PAGE_M));
3355 cmd->i2c_mem_addr = CPU_TO_LE16(mem_addr & 0xff);
3356 cmd->eeprom_page = CPU_TO_LE16((u16)page << ICE_AQC_SFF_EEPROM_PAGE_S);
3358 cmd->i2c_bus_addr |= CPU_TO_LE16(ICE_AQC_SFF_IS_WRITE);
3360 status = ice_aq_send_cmd(hw, &desc, data, length, cd);
3365 * __ice_aq_get_set_rss_lut
3366 * @hw: pointer to the hardware structure
3367 * @params: RSS LUT parameters
3368 * @set: set true to set the table, false to get the table
3370 * Internal function to get (0x0B05) or set (0x0B03) RSS look up table
3372 static enum ice_status
3373 __ice_aq_get_set_rss_lut(struct ice_hw *hw, struct ice_aq_get_set_rss_lut_params *params, bool set)
3375 u16 flags = 0, vsi_id, lut_type, lut_size, glob_lut_idx, vsi_handle;
3376 struct ice_aqc_get_set_rss_lut *cmd_resp;
3377 struct ice_aq_desc desc;
3378 enum ice_status status;
3382 return ICE_ERR_PARAM;
3384 vsi_handle = params->vsi_handle;
3387 if (!ice_is_vsi_valid(hw, vsi_handle) || !lut)
3388 return ICE_ERR_PARAM;
3390 lut_size = params->lut_size;
3391 lut_type = params->lut_type;
3392 glob_lut_idx = params->global_lut_id;
3393 vsi_id = ice_get_hw_vsi_num(hw, vsi_handle);
3395 cmd_resp = &desc.params.get_set_rss_lut;
3398 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_rss_lut);
3399 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
3401 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_rss_lut);
3404 cmd_resp->vsi_id = CPU_TO_LE16(((vsi_id <<
3405 ICE_AQC_GSET_RSS_LUT_VSI_ID_S) &
3406 ICE_AQC_GSET_RSS_LUT_VSI_ID_M) |
3407 ICE_AQC_GSET_RSS_LUT_VSI_VALID);
3410 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_VSI:
3411 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF:
3412 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL:
3413 flags |= ((lut_type << ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S) &
3414 ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_M);
3417 status = ICE_ERR_PARAM;
3418 goto ice_aq_get_set_rss_lut_exit;
3421 if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL) {
3422 flags |= ((glob_lut_idx << ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S) &
3423 ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_M);
3426 goto ice_aq_get_set_rss_lut_send;
3427 } else if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF) {
3429 goto ice_aq_get_set_rss_lut_send;
3431 goto ice_aq_get_set_rss_lut_send;
3434 /* LUT size is only valid for Global and PF table types */
3436 case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128:
3437 flags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128_FLAG <<
3438 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) &
3439 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M;
3441 case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512:
3442 flags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512_FLAG <<
3443 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) &
3444 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M;
3446 case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K:
3447 if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF) {
3448 flags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K_FLAG <<
3449 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) &
3450 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M;
3455 status = ICE_ERR_PARAM;
3456 goto ice_aq_get_set_rss_lut_exit;
3459 ice_aq_get_set_rss_lut_send:
3460 cmd_resp->flags = CPU_TO_LE16(flags);
3461 status = ice_aq_send_cmd(hw, &desc, lut, lut_size, NULL);
3463 ice_aq_get_set_rss_lut_exit:
3468 * ice_aq_get_rss_lut
3469 * @hw: pointer to the hardware structure
3470 * @get_params: RSS LUT parameters used to specify which RSS LUT to get
3472 * get the RSS lookup table, PF or VSI type
3475 ice_aq_get_rss_lut(struct ice_hw *hw, struct ice_aq_get_set_rss_lut_params *get_params)
3477 return __ice_aq_get_set_rss_lut(hw, get_params, false);
3481 * ice_aq_set_rss_lut
3482 * @hw: pointer to the hardware structure
3483 * @set_params: RSS LUT parameters used to specify how to set the RSS LUT
3485 * set the RSS lookup table, PF or VSI type
3488 ice_aq_set_rss_lut(struct ice_hw *hw, struct ice_aq_get_set_rss_lut_params *set_params)
3490 return __ice_aq_get_set_rss_lut(hw, set_params, true);
3494 * __ice_aq_get_set_rss_key
3495 * @hw: pointer to the HW struct
3496 * @vsi_id: VSI FW index
3497 * @key: pointer to key info struct
3498 * @set: set true to set the key, false to get the key
3500 * get (0x0B04) or set (0x0B02) the RSS key per VSI
3503 ice_status __ice_aq_get_set_rss_key(struct ice_hw *hw, u16 vsi_id,
3504 struct ice_aqc_get_set_rss_keys *key,
3507 struct ice_aqc_get_set_rss_key *cmd_resp;
3508 u16 key_size = sizeof(*key);
3509 struct ice_aq_desc desc;
3511 cmd_resp = &desc.params.get_set_rss_key;
3514 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_rss_key);
3515 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
3517 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_rss_key);
3520 cmd_resp->vsi_id = CPU_TO_LE16(((vsi_id <<
3521 ICE_AQC_GSET_RSS_KEY_VSI_ID_S) &
3522 ICE_AQC_GSET_RSS_KEY_VSI_ID_M) |
3523 ICE_AQC_GSET_RSS_KEY_VSI_VALID);
3525 return ice_aq_send_cmd(hw, &desc, key, key_size, NULL);
3529 * ice_aq_get_rss_key
3530 * @hw: pointer to the HW struct
3531 * @vsi_handle: software VSI handle
3532 * @key: pointer to key info struct
3534 * get the RSS key per VSI
3537 ice_aq_get_rss_key(struct ice_hw *hw, u16 vsi_handle,
3538 struct ice_aqc_get_set_rss_keys *key)
3540 if (!ice_is_vsi_valid(hw, vsi_handle) || !key)
3541 return ICE_ERR_PARAM;
3543 return __ice_aq_get_set_rss_key(hw, ice_get_hw_vsi_num(hw, vsi_handle),
3548 * ice_aq_set_rss_key
3549 * @hw: pointer to the HW struct
3550 * @vsi_handle: software VSI handle
3551 * @keys: pointer to key info struct
3553 * set the RSS key per VSI
3556 ice_aq_set_rss_key(struct ice_hw *hw, u16 vsi_handle,
3557 struct ice_aqc_get_set_rss_keys *keys)
3559 if (!ice_is_vsi_valid(hw, vsi_handle) || !keys)
3560 return ICE_ERR_PARAM;
3562 return __ice_aq_get_set_rss_key(hw, ice_get_hw_vsi_num(hw, vsi_handle),
3567 * ice_aq_add_lan_txq
3568 * @hw: pointer to the hardware structure
3569 * @num_qgrps: Number of added queue groups
3570 * @qg_list: list of queue groups to be added
3571 * @buf_size: size of buffer for indirect command
3572 * @cd: pointer to command details structure or NULL
3574 * Add Tx LAN queue (0x0C30)
3577 * Prior to calling add Tx LAN queue:
3578 * Initialize the following as part of the Tx queue context:
3579 * Completion queue ID if the queue uses Completion queue, Quanta profile,
3580 * Cache profile and Packet shaper profile.
3582 * After add Tx LAN queue AQ command is completed:
3583 * Interrupts should be associated with specific queues,
3584 * Association of Tx queue to Doorbell queue is not part of Add LAN Tx queue
3588 ice_aq_add_lan_txq(struct ice_hw *hw, u8 num_qgrps,
3589 struct ice_aqc_add_tx_qgrp *qg_list, u16 buf_size,
3590 struct ice_sq_cd *cd)
3592 struct ice_aqc_add_tx_qgrp *list;
3593 struct ice_aqc_add_txqs *cmd;
3594 struct ice_aq_desc desc;
3595 u16 i, sum_size = 0;
3597 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
3599 cmd = &desc.params.add_txqs;
3601 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_add_txqs);
3604 return ICE_ERR_PARAM;
3606 if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS)
3607 return ICE_ERR_PARAM;
3609 for (i = 0, list = qg_list; i < num_qgrps; i++) {
3610 sum_size += ice_struct_size(list, txqs, list->num_txqs);
3611 list = (struct ice_aqc_add_tx_qgrp *)(list->txqs +
3615 if (buf_size != sum_size)
3616 return ICE_ERR_PARAM;
3618 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
3620 cmd->num_qgrps = num_qgrps;
3622 return ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd);
3626 * ice_aq_dis_lan_txq
3627 * @hw: pointer to the hardware structure
3628 * @num_qgrps: number of groups in the list
3629 * @qg_list: the list of groups to disable
3630 * @buf_size: the total size of the qg_list buffer in bytes
3631 * @rst_src: if called due to reset, specifies the reset source
3632 * @vmvf_num: the relative VM or VF number that is undergoing the reset
3633 * @cd: pointer to command details structure or NULL
3635 * Disable LAN Tx queue (0x0C31)
3637 static enum ice_status
3638 ice_aq_dis_lan_txq(struct ice_hw *hw, u8 num_qgrps,
3639 struct ice_aqc_dis_txq_item *qg_list, u16 buf_size,
3640 enum ice_disq_rst_src rst_src, u16 vmvf_num,
3641 struct ice_sq_cd *cd)
3643 struct ice_aqc_dis_txq_item *item;
3644 struct ice_aqc_dis_txqs *cmd;
3645 struct ice_aq_desc desc;
3646 enum ice_status status;
3649 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
3650 cmd = &desc.params.dis_txqs;
3651 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_dis_txqs);
3653 /* qg_list can be NULL only in VM/VF reset flow */
3654 if (!qg_list && !rst_src)
3655 return ICE_ERR_PARAM;
3657 if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS)
3658 return ICE_ERR_PARAM;
3660 cmd->num_entries = num_qgrps;
3662 cmd->vmvf_and_timeout = CPU_TO_LE16((5 << ICE_AQC_Q_DIS_TIMEOUT_S) &
3663 ICE_AQC_Q_DIS_TIMEOUT_M);
3667 cmd->cmd_type = ICE_AQC_Q_DIS_CMD_VM_RESET;
3668 cmd->vmvf_and_timeout |=
3669 CPU_TO_LE16(vmvf_num & ICE_AQC_Q_DIS_VMVF_NUM_M);
3676 /* flush pipe on time out */
3677 cmd->cmd_type |= ICE_AQC_Q_DIS_CMD_FLUSH_PIPE;
3678 /* If no queue group info, we are in a reset flow. Issue the AQ */
3682 /* set RD bit to indicate that command buffer is provided by the driver
3683 * and it needs to be read by the firmware
3685 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
3687 for (i = 0, item = qg_list; i < num_qgrps; i++) {
3688 u16 item_size = ice_struct_size(item, q_id, item->num_qs);
3690 /* If the num of queues is even, add 2 bytes of padding */
3691 if ((item->num_qs % 2) == 0)
3696 item = (struct ice_aqc_dis_txq_item *)((u8 *)item + item_size);
3700 return ICE_ERR_PARAM;
3703 status = ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd);
3706 ice_debug(hw, ICE_DBG_SCHED, "VM%d disable failed %d\n",
3707 vmvf_num, hw->adminq.sq_last_status);
3709 ice_debug(hw, ICE_DBG_SCHED, "disable queue %d failed %d\n",
3710 LE16_TO_CPU(qg_list[0].q_id[0]),
3711 hw->adminq.sq_last_status);
3717 * ice_aq_move_recfg_lan_txq
3718 * @hw: pointer to the hardware structure
3719 * @num_qs: number of queues to move/reconfigure
3720 * @is_move: true if this operation involves node movement
3721 * @is_tc_change: true if this operation involves a TC change
3722 * @subseq_call: true if this operation is a subsequent call
3723 * @flush_pipe: on timeout, true to flush pipe, false to return EAGAIN
3724 * @timeout: timeout in units of 100 usec (valid values 0-50)
3725 * @blocked_cgds: out param, bitmap of CGDs that timed out if returning EAGAIN
3726 * @buf: struct containing src/dest TEID and per-queue info
3727 * @buf_size: size of buffer for indirect command
3728 * @txqs_moved: out param, number of queues successfully moved
3729 * @cd: pointer to command details structure or NULL
3731 * Move / Reconfigure Tx LAN queues (0x0C32)
3734 ice_aq_move_recfg_lan_txq(struct ice_hw *hw, u8 num_qs, bool is_move,
3735 bool is_tc_change, bool subseq_call, bool flush_pipe,
3736 u8 timeout, u32 *blocked_cgds,
3737 struct ice_aqc_move_txqs_data *buf, u16 buf_size,
3738 u8 *txqs_moved, struct ice_sq_cd *cd)
3740 struct ice_aqc_move_txqs *cmd;
3741 struct ice_aq_desc desc;
3742 enum ice_status status;
3744 cmd = &desc.params.move_txqs;
3745 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_move_recfg_txqs);
3747 #define ICE_LAN_TXQ_MOVE_TIMEOUT_MAX 50
3748 if (timeout > ICE_LAN_TXQ_MOVE_TIMEOUT_MAX)
3749 return ICE_ERR_PARAM;
3751 if (is_tc_change && !flush_pipe && !blocked_cgds)
3752 return ICE_ERR_PARAM;
3754 if (!is_move && !is_tc_change)
3755 return ICE_ERR_PARAM;
3757 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
3760 cmd->cmd_type |= ICE_AQC_Q_CMD_TYPE_MOVE;
3763 cmd->cmd_type |= ICE_AQC_Q_CMD_TYPE_TC_CHANGE;
3766 cmd->cmd_type |= ICE_AQC_Q_CMD_SUBSEQ_CALL;
3769 cmd->cmd_type |= ICE_AQC_Q_CMD_FLUSH_PIPE;
3771 cmd->num_qs = num_qs;
3772 cmd->timeout = ((timeout << ICE_AQC_Q_CMD_TIMEOUT_S) &
3773 ICE_AQC_Q_CMD_TIMEOUT_M);
3775 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);
3777 if (!status && txqs_moved)
3778 *txqs_moved = cmd->num_qs;
3780 if (hw->adminq.sq_last_status == ICE_AQ_RC_EAGAIN &&
3781 is_tc_change && !flush_pipe)
3782 *blocked_cgds = LE32_TO_CPU(cmd->blocked_cgds);
3787 /* End of FW Admin Queue command wrappers */
3790 * ice_write_byte - write a byte to a packed context structure
3791 * @src_ctx: the context structure to read from
3792 * @dest_ctx: the context to be written to
3793 * @ce_info: a description of the struct to be filled
3796 ice_write_byte(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)
3798 u8 src_byte, dest_byte, mask;
3802 /* copy from the next struct field */
3803 from = src_ctx + ce_info->offset;
3805 /* prepare the bits and mask */
3806 shift_width = ce_info->lsb % 8;
3807 mask = (u8)(BIT(ce_info->width) - 1);
3812 /* shift to correct alignment */
3813 mask <<= shift_width;
3814 src_byte <<= shift_width;
3816 /* get the current bits from the target bit string */
3817 dest = dest_ctx + (ce_info->lsb / 8);
3819 ice_memcpy(&dest_byte, dest, sizeof(dest_byte), ICE_DMA_TO_NONDMA);
3821 dest_byte &= ~mask; /* get the bits not changing */
3822 dest_byte |= src_byte; /* add in the new bits */
3824 /* put it all back */
3825 ice_memcpy(dest, &dest_byte, sizeof(dest_byte), ICE_NONDMA_TO_DMA);
3829 * ice_write_word - write a word to a packed context structure
3830 * @src_ctx: the context structure to read from
3831 * @dest_ctx: the context to be written to
3832 * @ce_info: a description of the struct to be filled
3835 ice_write_word(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)
3842 /* copy from the next struct field */
3843 from = src_ctx + ce_info->offset;
3845 /* prepare the bits and mask */
3846 shift_width = ce_info->lsb % 8;
3847 mask = BIT(ce_info->width) - 1;
3849 /* don't swizzle the bits until after the mask because the mask bits
3850 * will be in a different bit position on big endian machines
3852 src_word = *(u16 *)from;
3855 /* shift to correct alignment */
3856 mask <<= shift_width;
3857 src_word <<= shift_width;
3859 /* get the current bits from the target bit string */
3860 dest = dest_ctx + (ce_info->lsb / 8);
3862 ice_memcpy(&dest_word, dest, sizeof(dest_word), ICE_DMA_TO_NONDMA);
3864 dest_word &= ~(CPU_TO_LE16(mask)); /* get the bits not changing */
3865 dest_word |= CPU_TO_LE16(src_word); /* add in the new bits */
3867 /* put it all back */
3868 ice_memcpy(dest, &dest_word, sizeof(dest_word), ICE_NONDMA_TO_DMA);
3872 * ice_write_dword - write a dword to a packed context structure
3873 * @src_ctx: the context structure to read from
3874 * @dest_ctx: the context to be written to
3875 * @ce_info: a description of the struct to be filled
3878 ice_write_dword(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)
3880 u32 src_dword, mask;
3885 /* copy from the next struct field */
3886 from = src_ctx + ce_info->offset;
3888 /* prepare the bits and mask */
3889 shift_width = ce_info->lsb % 8;
3891 /* if the field width is exactly 32 on an x86 machine, then the shift
3892 * operation will not work because the SHL instructions count is masked
3893 * to 5 bits so the shift will do nothing
3895 if (ce_info->width < 32)
3896 mask = BIT(ce_info->width) - 1;
3900 /* don't swizzle the bits until after the mask because the mask bits
3901 * will be in a different bit position on big endian machines
3903 src_dword = *(u32 *)from;
3906 /* shift to correct alignment */
3907 mask <<= shift_width;
3908 src_dword <<= shift_width;
3910 /* get the current bits from the target bit string */
3911 dest = dest_ctx + (ce_info->lsb / 8);
3913 ice_memcpy(&dest_dword, dest, sizeof(dest_dword), ICE_DMA_TO_NONDMA);
3915 dest_dword &= ~(CPU_TO_LE32(mask)); /* get the bits not changing */
3916 dest_dword |= CPU_TO_LE32(src_dword); /* add in the new bits */
3918 /* put it all back */
3919 ice_memcpy(dest, &dest_dword, sizeof(dest_dword), ICE_NONDMA_TO_DMA);
3923 * ice_write_qword - write a qword to a packed context structure
3924 * @src_ctx: the context structure to read from
3925 * @dest_ctx: the context to be written to
3926 * @ce_info: a description of the struct to be filled
3929 ice_write_qword(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)
3931 u64 src_qword, mask;
3936 /* copy from the next struct field */
3937 from = src_ctx + ce_info->offset;
3939 /* prepare the bits and mask */
3940 shift_width = ce_info->lsb % 8;
3942 /* if the field width is exactly 64 on an x86 machine, then the shift
3943 * operation will not work because the SHL instructions count is masked
3944 * to 6 bits so the shift will do nothing
3946 if (ce_info->width < 64)
3947 mask = BIT_ULL(ce_info->width) - 1;
3951 /* don't swizzle the bits until after the mask because the mask bits
3952 * will be in a different bit position on big endian machines
3954 src_qword = *(u64 *)from;
3957 /* shift to correct alignment */
3958 mask <<= shift_width;
3959 src_qword <<= shift_width;
3961 /* get the current bits from the target bit string */
3962 dest = dest_ctx + (ce_info->lsb / 8);
3964 ice_memcpy(&dest_qword, dest, sizeof(dest_qword), ICE_DMA_TO_NONDMA);
3966 dest_qword &= ~(CPU_TO_LE64(mask)); /* get the bits not changing */
3967 dest_qword |= CPU_TO_LE64(src_qword); /* add in the new bits */
3969 /* put it all back */
3970 ice_memcpy(dest, &dest_qword, sizeof(dest_qword), ICE_NONDMA_TO_DMA);
3974 * ice_set_ctx - set context bits in packed structure
3975 * @hw: pointer to the hardware structure
3976 * @src_ctx: pointer to a generic non-packed context structure
3977 * @dest_ctx: pointer to memory for the packed structure
3978 * @ce_info: a description of the structure to be transformed
3981 ice_set_ctx(struct ice_hw *hw, u8 *src_ctx, u8 *dest_ctx,
3982 const struct ice_ctx_ele *ce_info)
3986 for (f = 0; ce_info[f].width; f++) {
3987 /* We have to deal with each element of the FW response
3988 * using the correct size so that we are correct regardless
3989 * of the endianness of the machine.
3991 if (ce_info[f].width > (ce_info[f].size_of * BITS_PER_BYTE)) {
3992 ice_debug(hw, ICE_DBG_QCTX, "Field %d width of %d bits larger than size of %d byte(s) ... skipping write\n",
3993 f, ce_info[f].width, ce_info[f].size_of);
3996 switch (ce_info[f].size_of) {
3998 ice_write_byte(src_ctx, dest_ctx, &ce_info[f]);
4001 ice_write_word(src_ctx, dest_ctx, &ce_info[f]);
4004 ice_write_dword(src_ctx, dest_ctx, &ce_info[f]);
4007 ice_write_qword(src_ctx, dest_ctx, &ce_info[f]);
4010 return ICE_ERR_INVAL_SIZE;
4018 * ice_read_byte - read context byte into struct
4019 * @src_ctx: the context structure to read from
4020 * @dest_ctx: the context to be written to
4021 * @ce_info: a description of the struct to be filled
4024 ice_read_byte(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info)
4030 /* prepare the bits and mask */
4031 shift_width = ce_info->lsb % 8;
4032 mask = (u8)(BIT(ce_info->width) - 1);
4034 /* shift to correct alignment */
4035 mask <<= shift_width;
4037 /* get the current bits from the src bit string */
4038 src = src_ctx + (ce_info->lsb / 8);
4040 ice_memcpy(&dest_byte, src, sizeof(dest_byte), ICE_DMA_TO_NONDMA);
4042 dest_byte &= ~(mask);
4044 dest_byte >>= shift_width;
4046 /* get the address from the struct field */
4047 target = dest_ctx + ce_info->offset;
4049 /* put it back in the struct */
4050 ice_memcpy(target, &dest_byte, sizeof(dest_byte), ICE_NONDMA_TO_DMA);
4054 * ice_read_word - read context word into struct
4055 * @src_ctx: the context structure to read from
4056 * @dest_ctx: the context to be written to
4057 * @ce_info: a description of the struct to be filled
4060 ice_read_word(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info)
4062 u16 dest_word, mask;
4067 /* prepare the bits and mask */
4068 shift_width = ce_info->lsb % 8;
4069 mask = BIT(ce_info->width) - 1;
4071 /* shift to correct alignment */
4072 mask <<= shift_width;
4074 /* get the current bits from the src bit string */
4075 src = src_ctx + (ce_info->lsb / 8);
4077 ice_memcpy(&src_word, src, sizeof(src_word), ICE_DMA_TO_NONDMA);
4079 /* the data in the memory is stored as little endian so mask it
4082 src_word &= ~(CPU_TO_LE16(mask));
4084 /* get the data back into host order before shifting */
4085 dest_word = LE16_TO_CPU(src_word);
4087 dest_word >>= shift_width;
4089 /* get the address from the struct field */
4090 target = dest_ctx + ce_info->offset;
4092 /* put it back in the struct */
4093 ice_memcpy(target, &dest_word, sizeof(dest_word), ICE_NONDMA_TO_DMA);
4097 * ice_read_dword - read context dword into struct
4098 * @src_ctx: the context structure to read from
4099 * @dest_ctx: the context to be written to
4100 * @ce_info: a description of the struct to be filled
4103 ice_read_dword(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info)
4105 u32 dest_dword, mask;
4110 /* prepare the bits and mask */
4111 shift_width = ce_info->lsb % 8;
4113 /* if the field width is exactly 32 on an x86 machine, then the shift
4114 * operation will not work because the SHL instructions count is masked
4115 * to 5 bits so the shift will do nothing
4117 if (ce_info->width < 32)
4118 mask = BIT(ce_info->width) - 1;
4122 /* shift to correct alignment */
4123 mask <<= shift_width;
4125 /* get the current bits from the src bit string */
4126 src = src_ctx + (ce_info->lsb / 8);
4128 ice_memcpy(&src_dword, src, sizeof(src_dword), ICE_DMA_TO_NONDMA);
4130 /* the data in the memory is stored as little endian so mask it
4133 src_dword &= ~(CPU_TO_LE32(mask));
4135 /* get the data back into host order before shifting */
4136 dest_dword = LE32_TO_CPU(src_dword);
4138 dest_dword >>= shift_width;
4140 /* get the address from the struct field */
4141 target = dest_ctx + ce_info->offset;
4143 /* put it back in the struct */
4144 ice_memcpy(target, &dest_dword, sizeof(dest_dword), ICE_NONDMA_TO_DMA);
4148 * ice_read_qword - read context qword into struct
4149 * @src_ctx: the context structure to read from
4150 * @dest_ctx: the context to be written to
4151 * @ce_info: a description of the struct to be filled
4154 ice_read_qword(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info)
4156 u64 dest_qword, mask;
4161 /* prepare the bits and mask */
4162 shift_width = ce_info->lsb % 8;
4164 /* if the field width is exactly 64 on an x86 machine, then the shift
4165 * operation will not work because the SHL instructions count is masked
4166 * to 6 bits so the shift will do nothing
4168 if (ce_info->width < 64)
4169 mask = BIT_ULL(ce_info->width) - 1;
4173 /* shift to correct alignment */
4174 mask <<= shift_width;
4176 /* get the current bits from the src bit string */
4177 src = src_ctx + (ce_info->lsb / 8);
4179 ice_memcpy(&src_qword, src, sizeof(src_qword), ICE_DMA_TO_NONDMA);
4181 /* the data in the memory is stored as little endian so mask it
4184 src_qword &= ~(CPU_TO_LE64(mask));
4186 /* get the data back into host order before shifting */
4187 dest_qword = LE64_TO_CPU(src_qword);
4189 dest_qword >>= shift_width;
4191 /* get the address from the struct field */
4192 target = dest_ctx + ce_info->offset;
4194 /* put it back in the struct */
4195 ice_memcpy(target, &dest_qword, sizeof(dest_qword), ICE_NONDMA_TO_DMA);
4199 * ice_get_ctx - extract context bits from a packed structure
4200 * @src_ctx: pointer to a generic packed context structure
4201 * @dest_ctx: pointer to a generic non-packed context structure
4202 * @ce_info: a description of the structure to be read from
4205 ice_get_ctx(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info)
4209 for (f = 0; ce_info[f].width; f++) {
4210 switch (ce_info[f].size_of) {
4212 ice_read_byte(src_ctx, dest_ctx, &ce_info[f]);
4215 ice_read_word(src_ctx, dest_ctx, &ce_info[f]);
4218 ice_read_dword(src_ctx, dest_ctx, &ce_info[f]);
4221 ice_read_qword(src_ctx, dest_ctx, &ce_info[f]);
4224 /* nothing to do, just keep going */
4233 * ice_get_lan_q_ctx - get the LAN queue context for the given VSI and TC
4234 * @hw: pointer to the HW struct
4235 * @vsi_handle: software VSI handle
4237 * @q_handle: software queue handle
4240 ice_get_lan_q_ctx(struct ice_hw *hw, u16 vsi_handle, u8 tc, u16 q_handle)
4242 struct ice_vsi_ctx *vsi;
4243 struct ice_q_ctx *q_ctx;
4245 vsi = ice_get_vsi_ctx(hw, vsi_handle);
4248 if (q_handle >= vsi->num_lan_q_entries[tc])
4250 if (!vsi->lan_q_ctx[tc])
4252 q_ctx = vsi->lan_q_ctx[tc];
4253 return &q_ctx[q_handle];
4258 * @pi: port information structure
4259 * @vsi_handle: software VSI handle
4261 * @q_handle: software queue handle
4262 * @num_qgrps: Number of added queue groups
4263 * @buf: list of queue groups to be added
4264 * @buf_size: size of buffer for indirect command
4265 * @cd: pointer to command details structure or NULL
4267 * This function adds one LAN queue
4270 ice_ena_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u16 q_handle,
4271 u8 num_qgrps, struct ice_aqc_add_tx_qgrp *buf, u16 buf_size,
4272 struct ice_sq_cd *cd)
4274 struct ice_aqc_txsched_elem_data node = { 0 };
4275 struct ice_sched_node *parent;
4276 struct ice_q_ctx *q_ctx;
4277 enum ice_status status;
4280 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY)
4283 if (num_qgrps > 1 || buf->num_txqs > 1)
4284 return ICE_ERR_MAX_LIMIT;
4288 if (!ice_is_vsi_valid(hw, vsi_handle))
4289 return ICE_ERR_PARAM;
4291 ice_acquire_lock(&pi->sched_lock);
4293 q_ctx = ice_get_lan_q_ctx(hw, vsi_handle, tc, q_handle);
4295 ice_debug(hw, ICE_DBG_SCHED, "Enaq: invalid queue handle %d\n",
4297 status = ICE_ERR_PARAM;
4301 /* find a parent node */
4302 parent = ice_sched_get_free_qparent(pi, vsi_handle, tc,
4303 ICE_SCHED_NODE_OWNER_LAN);
4305 status = ICE_ERR_PARAM;
4309 buf->parent_teid = parent->info.node_teid;
4310 node.parent_teid = parent->info.node_teid;
4311 /* Mark that the values in the "generic" section as valid. The default
4312 * value in the "generic" section is zero. This means that :
4313 * - Scheduling mode is Bytes Per Second (BPS), indicated by Bit 0.
4314 * - 0 priority among siblings, indicated by Bit 1-3.
4315 * - WFQ, indicated by Bit 4.
4316 * - 0 Adjustment value is used in PSM credit update flow, indicated by
4318 * - Bit 7 is reserved.
4319 * Without setting the generic section as valid in valid_sections, the
4320 * Admin queue command will fail with error code ICE_AQ_RC_EINVAL.
4322 buf->txqs[0].info.valid_sections =
4323 ICE_AQC_ELEM_VALID_GENERIC | ICE_AQC_ELEM_VALID_CIR |
4324 ICE_AQC_ELEM_VALID_EIR;
4325 buf->txqs[0].info.generic = 0;
4326 buf->txqs[0].info.cir_bw.bw_profile_idx =
4327 CPU_TO_LE16(ICE_SCHED_DFLT_RL_PROF_ID);
4328 buf->txqs[0].info.cir_bw.bw_alloc =
4329 CPU_TO_LE16(ICE_SCHED_DFLT_BW_WT);
4330 buf->txqs[0].info.eir_bw.bw_profile_idx =
4331 CPU_TO_LE16(ICE_SCHED_DFLT_RL_PROF_ID);
4332 buf->txqs[0].info.eir_bw.bw_alloc =
4333 CPU_TO_LE16(ICE_SCHED_DFLT_BW_WT);
4335 /* add the LAN queue */
4336 status = ice_aq_add_lan_txq(hw, num_qgrps, buf, buf_size, cd);
4337 if (status != ICE_SUCCESS) {
4338 ice_debug(hw, ICE_DBG_SCHED, "enable queue %d failed %d\n",
4339 LE16_TO_CPU(buf->txqs[0].txq_id),
4340 hw->adminq.sq_last_status);
4344 node.node_teid = buf->txqs[0].q_teid;
4345 node.data.elem_type = ICE_AQC_ELEM_TYPE_LEAF;
4346 q_ctx->q_handle = q_handle;
4347 q_ctx->q_teid = LE32_TO_CPU(node.node_teid);
4349 /* add a leaf node into scheduler tree queue layer */
4350 status = ice_sched_add_node(pi, hw->num_tx_sched_layers - 1, &node);
4352 status = ice_sched_replay_q_bw(pi, q_ctx);
4355 ice_release_lock(&pi->sched_lock);
4361 * @pi: port information structure
4362 * @vsi_handle: software VSI handle
4364 * @num_queues: number of queues
4365 * @q_handles: pointer to software queue handle array
4366 * @q_ids: pointer to the q_id array
4367 * @q_teids: pointer to queue node teids
4368 * @rst_src: if called due to reset, specifies the reset source
4369 * @vmvf_num: the relative VM or VF number that is undergoing the reset
4370 * @cd: pointer to command details structure or NULL
4372 * This function removes queues and their corresponding nodes in SW DB
4375 ice_dis_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u8 num_queues,
4376 u16 *q_handles, u16 *q_ids, u32 *q_teids,
4377 enum ice_disq_rst_src rst_src, u16 vmvf_num,
4378 struct ice_sq_cd *cd)
4380 enum ice_status status = ICE_ERR_DOES_NOT_EXIST;
4381 struct ice_aqc_dis_txq_item *qg_list;
4382 struct ice_q_ctx *q_ctx;
4386 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY)
4392 /* if queue is disabled already yet the disable queue command
4393 * has to be sent to complete the VF reset, then call
4394 * ice_aq_dis_lan_txq without any queue information
4397 return ice_aq_dis_lan_txq(hw, 0, NULL, 0, rst_src,
4402 buf_size = ice_struct_size(qg_list, q_id, 1);
4403 qg_list = (struct ice_aqc_dis_txq_item *)ice_malloc(hw, buf_size);
4405 return ICE_ERR_NO_MEMORY;
4407 ice_acquire_lock(&pi->sched_lock);
4409 for (i = 0; i < num_queues; i++) {
4410 struct ice_sched_node *node;
4412 node = ice_sched_find_node_by_teid(pi->root, q_teids[i]);
4415 q_ctx = ice_get_lan_q_ctx(hw, vsi_handle, tc, q_handles[i]);
4417 ice_debug(hw, ICE_DBG_SCHED, "invalid queue handle%d\n",
4421 if (q_ctx->q_handle != q_handles[i]) {
4422 ice_debug(hw, ICE_DBG_SCHED, "Err:handles %d %d\n",
4423 q_ctx->q_handle, q_handles[i]);
4426 qg_list->parent_teid = node->info.parent_teid;
4427 qg_list->num_qs = 1;
4428 qg_list->q_id[0] = CPU_TO_LE16(q_ids[i]);
4429 status = ice_aq_dis_lan_txq(hw, 1, qg_list, buf_size, rst_src,
4432 if (status != ICE_SUCCESS)
4434 ice_free_sched_node(pi, node);
4435 q_ctx->q_handle = ICE_INVAL_Q_HANDLE;
4437 ice_release_lock(&pi->sched_lock);
4438 ice_free(hw, qg_list);
4443 * ice_cfg_vsi_qs - configure the new/existing VSI queues
4444 * @pi: port information structure
4445 * @vsi_handle: software VSI handle
4446 * @tc_bitmap: TC bitmap
4447 * @maxqs: max queues array per TC
4448 * @owner: LAN or RDMA
4450 * This function adds/updates the VSI queues per TC.
4452 static enum ice_status
4453 ice_cfg_vsi_qs(struct ice_port_info *pi, u16 vsi_handle, u16 tc_bitmap,
4454 u16 *maxqs, u8 owner)
4456 enum ice_status status = ICE_SUCCESS;
4459 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY)
4462 if (!ice_is_vsi_valid(pi->hw, vsi_handle))
4463 return ICE_ERR_PARAM;
4465 ice_acquire_lock(&pi->sched_lock);
4467 ice_for_each_traffic_class(i) {
4468 /* configuration is possible only if TC node is present */
4469 if (!ice_sched_get_tc_node(pi, i))
4472 status = ice_sched_cfg_vsi(pi, vsi_handle, i, maxqs[i], owner,
4473 ice_is_tc_ena(tc_bitmap, i));
4478 ice_release_lock(&pi->sched_lock);
4483 * ice_cfg_vsi_lan - configure VSI LAN queues
4484 * @pi: port information structure
4485 * @vsi_handle: software VSI handle
4486 * @tc_bitmap: TC bitmap
4487 * @max_lanqs: max LAN queues array per TC
4489 * This function adds/updates the VSI LAN queues per TC.
4492 ice_cfg_vsi_lan(struct ice_port_info *pi, u16 vsi_handle, u16 tc_bitmap,
4495 return ice_cfg_vsi_qs(pi, vsi_handle, tc_bitmap, max_lanqs,
4496 ICE_SCHED_NODE_OWNER_LAN);
4500 * ice_is_main_vsi - checks whether the VSI is main VSI
4501 * @hw: pointer to the HW struct
4502 * @vsi_handle: VSI handle
4504 * Checks whether the VSI is the main VSI (the first PF VSI created on
4507 static bool ice_is_main_vsi(struct ice_hw *hw, u16 vsi_handle)
4509 return vsi_handle == ICE_MAIN_VSI_HANDLE && hw->vsi_ctx[vsi_handle];
4513 * ice_replay_pre_init - replay pre initialization
4514 * @hw: pointer to the HW struct
4515 * @sw: pointer to switch info struct for which function initializes filters
4517 * Initializes required config data for VSI, FD, ACL, and RSS before replay.
4519 static enum ice_status
4520 ice_replay_pre_init(struct ice_hw *hw, struct ice_switch_info *sw)
4522 enum ice_status status;
4525 /* Delete old entries from replay filter list head if there is any */
4526 ice_rm_sw_replay_rule_info(hw, sw);
4527 /* In start of replay, move entries into replay_rules list, it
4528 * will allow adding rules entries back to filt_rules list,
4529 * which is operational list.
4531 for (i = 0; i < ICE_MAX_NUM_RECIPES; i++)
4532 LIST_REPLACE_INIT(&sw->recp_list[i].filt_rules,
4533 &sw->recp_list[i].filt_replay_rules);
4534 ice_sched_replay_agg_vsi_preinit(hw);
4536 status = ice_sched_replay_root_node_bw(hw->port_info);
4540 return ice_sched_replay_tc_node_bw(hw->port_info);
4544 * ice_replay_vsi - replay VSI configuration
4545 * @hw: pointer to the HW struct
4546 * @vsi_handle: driver VSI handle
4548 * Restore all VSI configuration after reset. It is required to call this
4549 * function with main VSI first.
4551 enum ice_status ice_replay_vsi(struct ice_hw *hw, u16 vsi_handle)
4553 struct ice_switch_info *sw = hw->switch_info;
4554 struct ice_port_info *pi = hw->port_info;
4555 enum ice_status status;
4557 if (!ice_is_vsi_valid(hw, vsi_handle))
4558 return ICE_ERR_PARAM;
4560 /* Replay pre-initialization if there is any */
4561 if (ice_is_main_vsi(hw, vsi_handle)) {
4562 status = ice_replay_pre_init(hw, sw);
4566 /* Replay per VSI all RSS configurations */
4567 status = ice_replay_rss_cfg(hw, vsi_handle);
4570 /* Replay per VSI all filters */
4571 status = ice_replay_vsi_all_fltr(hw, pi, vsi_handle);
4573 status = ice_replay_vsi_agg(hw, vsi_handle);
4578 * ice_replay_post - post replay configuration cleanup
4579 * @hw: pointer to the HW struct
4581 * Post replay cleanup.
4583 void ice_replay_post(struct ice_hw *hw)
4585 /* Delete old entries from replay filter list head */
4586 ice_rm_all_sw_replay_rule_info(hw);
4587 ice_sched_replay_agg(hw);
4591 * ice_stat_update40 - read 40 bit stat from the chip and update stat values
4592 * @hw: ptr to the hardware info
4593 * @reg: offset of 64 bit HW register to read from
4594 * @prev_stat_loaded: bool to specify if previous stats are loaded
4595 * @prev_stat: ptr to previous loaded stat value
4596 * @cur_stat: ptr to current stat value
4599 ice_stat_update40(struct ice_hw *hw, u32 reg, bool prev_stat_loaded,
4600 u64 *prev_stat, u64 *cur_stat)
4602 u64 new_data = rd64(hw, reg) & (BIT_ULL(40) - 1);
4604 /* device stats are not reset at PFR, they likely will not be zeroed
4605 * when the driver starts. Thus, save the value from the first read
4606 * without adding to the statistic value so that we report stats which
4607 * count up from zero.
4609 if (!prev_stat_loaded) {
4610 *prev_stat = new_data;
4614 /* Calculate the difference between the new and old values, and then
4615 * add it to the software stat value.
4617 if (new_data >= *prev_stat)
4618 *cur_stat += new_data - *prev_stat;
4620 /* to manage the potential roll-over */
4621 *cur_stat += (new_data + BIT_ULL(40)) - *prev_stat;
4623 /* Update the previously stored value to prepare for next read */
4624 *prev_stat = new_data;
4628 * ice_stat_update32 - read 32 bit stat from the chip and update stat values
4629 * @hw: ptr to the hardware info
4630 * @reg: offset of HW register to read from
4631 * @prev_stat_loaded: bool to specify if previous stats are loaded
4632 * @prev_stat: ptr to previous loaded stat value
4633 * @cur_stat: ptr to current stat value
4636 ice_stat_update32(struct ice_hw *hw, u32 reg, bool prev_stat_loaded,
4637 u64 *prev_stat, u64 *cur_stat)
4641 new_data = rd32(hw, reg);
4643 /* device stats are not reset at PFR, they likely will not be zeroed
4644 * when the driver starts. Thus, save the value from the first read
4645 * without adding to the statistic value so that we report stats which
4646 * count up from zero.
4648 if (!prev_stat_loaded) {
4649 *prev_stat = new_data;
4653 /* Calculate the difference between the new and old values, and then
4654 * add it to the software stat value.
4656 if (new_data >= *prev_stat)
4657 *cur_stat += new_data - *prev_stat;
4659 /* to manage the potential roll-over */
4660 *cur_stat += (new_data + BIT_ULL(32)) - *prev_stat;
4662 /* Update the previously stored value to prepare for next read */
4663 *prev_stat = new_data;
4667 * ice_stat_update_repc - read GLV_REPC stats from chip and update stat values
4668 * @hw: ptr to the hardware info
4669 * @vsi_handle: VSI handle
4670 * @prev_stat_loaded: bool to specify if the previous stat values are loaded
4671 * @cur_stats: ptr to current stats structure
4673 * The GLV_REPC statistic register actually tracks two 16bit statistics, and
4674 * thus cannot be read using the normal ice_stat_update32 function.
4676 * Read the GLV_REPC register associated with the given VSI, and update the
4677 * rx_no_desc and rx_error values in the ice_eth_stats structure.
4679 * Because the statistics in GLV_REPC stick at 0xFFFF, the register must be
4680 * cleared each time it's read.
4682 * Note that the GLV_RDPC register also counts the causes that would trigger
4683 * GLV_REPC. However, it does not give the finer grained detail about why the
4684 * packets are being dropped. The GLV_REPC values can be used to distinguish
4685 * whether Rx packets are dropped due to errors or due to no available
4689 ice_stat_update_repc(struct ice_hw *hw, u16 vsi_handle, bool prev_stat_loaded,
4690 struct ice_eth_stats *cur_stats)
4692 u16 vsi_num, no_desc, error_cnt;
4695 if (!ice_is_vsi_valid(hw, vsi_handle))
4698 vsi_num = ice_get_hw_vsi_num(hw, vsi_handle);
4700 /* If we haven't loaded stats yet, just clear the current value */
4701 if (!prev_stat_loaded) {
4702 wr32(hw, GLV_REPC(vsi_num), 0);
4706 repc = rd32(hw, GLV_REPC(vsi_num));
4707 no_desc = (repc & GLV_REPC_NO_DESC_CNT_M) >> GLV_REPC_NO_DESC_CNT_S;
4708 error_cnt = (repc & GLV_REPC_ERROR_CNT_M) >> GLV_REPC_ERROR_CNT_S;
4710 /* Clear the count by writing to the stats register */
4711 wr32(hw, GLV_REPC(vsi_num), 0);
4713 cur_stats->rx_no_desc += no_desc;
4714 cur_stats->rx_errors += error_cnt;
4718 * ice_sched_query_elem - query element information from HW
4719 * @hw: pointer to the HW struct
4720 * @node_teid: node TEID to be queried
4721 * @buf: buffer to element information
4723 * This function queries HW element information
4726 ice_sched_query_elem(struct ice_hw *hw, u32 node_teid,
4727 struct ice_aqc_txsched_elem_data *buf)
4729 u16 buf_size, num_elem_ret = 0;
4730 enum ice_status status;
4732 buf_size = sizeof(*buf);
4733 ice_memset(buf, 0, buf_size, ICE_NONDMA_MEM);
4734 buf->node_teid = CPU_TO_LE32(node_teid);
4735 status = ice_aq_query_sched_elems(hw, 1, buf, buf_size, &num_elem_ret,
4737 if (status != ICE_SUCCESS || num_elem_ret != 1)
4738 ice_debug(hw, ICE_DBG_SCHED, "query element failed\n");
4743 * ice_get_fw_mode - returns FW mode
4744 * @hw: pointer to the HW struct
4746 enum ice_fw_modes ice_get_fw_mode(struct ice_hw *hw)
4748 #define ICE_FW_MODE_DBG_M BIT(0)
4749 #define ICE_FW_MODE_REC_M BIT(1)
4750 #define ICE_FW_MODE_ROLLBACK_M BIT(2)
4753 /* check the current FW mode */
4754 fw_mode = rd32(hw, GL_MNG_FWSM) & GL_MNG_FWSM_FW_MODES_M;
4756 if (fw_mode & ICE_FW_MODE_DBG_M)
4757 return ICE_FW_MODE_DBG;
4758 else if (fw_mode & ICE_FW_MODE_REC_M)
4759 return ICE_FW_MODE_REC;
4760 else if (fw_mode & ICE_FW_MODE_ROLLBACK_M)
4761 return ICE_FW_MODE_ROLLBACK;
4763 return ICE_FW_MODE_NORMAL;
4767 * ice_fw_supports_link_override
4768 * @hw: pointer to the hardware structure
4770 * Checks if the firmware supports link override
4772 bool ice_fw_supports_link_override(struct ice_hw *hw)
4774 if (hw->api_maj_ver == ICE_FW_API_LINK_OVERRIDE_MAJ) {
4775 if (hw->api_min_ver > ICE_FW_API_LINK_OVERRIDE_MIN)
4777 if (hw->api_min_ver == ICE_FW_API_LINK_OVERRIDE_MIN &&
4778 hw->api_patch >= ICE_FW_API_LINK_OVERRIDE_PATCH)
4780 } else if (hw->api_maj_ver > ICE_FW_API_LINK_OVERRIDE_MAJ) {
4788 * ice_get_link_default_override
4789 * @ldo: pointer to the link default override struct
4790 * @pi: pointer to the port info struct
4792 * Gets the link default override for a port
4795 ice_get_link_default_override(struct ice_link_default_override_tlv *ldo,
4796 struct ice_port_info *pi)
4798 u16 i, tlv, tlv_len, tlv_start, buf, offset;
4799 struct ice_hw *hw = pi->hw;
4800 enum ice_status status;
4802 status = ice_get_pfa_module_tlv(hw, &tlv, &tlv_len,
4803 ICE_SR_LINK_DEFAULT_OVERRIDE_PTR);
4805 ice_debug(hw, ICE_DBG_INIT, "Failed to read link override TLV.\n");
4809 /* Each port has its own config; calculate for our port */
4810 tlv_start = tlv + pi->lport * ICE_SR_PFA_LINK_OVERRIDE_WORDS +
4811 ICE_SR_PFA_LINK_OVERRIDE_OFFSET;
4813 /* link options first */
4814 status = ice_read_sr_word(hw, tlv_start, &buf);
4816 ice_debug(hw, ICE_DBG_INIT, "Failed to read override link options.\n");
4819 ldo->options = buf & ICE_LINK_OVERRIDE_OPT_M;
4820 ldo->phy_config = (buf & ICE_LINK_OVERRIDE_PHY_CFG_M) >>
4821 ICE_LINK_OVERRIDE_PHY_CFG_S;
4823 /* link PHY config */
4824 offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_FEC_OFFSET;
4825 status = ice_read_sr_word(hw, offset, &buf);
4827 ice_debug(hw, ICE_DBG_INIT, "Failed to read override phy config.\n");
4830 ldo->fec_options = buf & ICE_LINK_OVERRIDE_FEC_OPT_M;
4833 offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_PHY_OFFSET;
4834 for (i = 0; i < ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS; i++) {
4835 status = ice_read_sr_word(hw, (offset + i), &buf);
4837 ice_debug(hw, ICE_DBG_INIT, "Failed to read override link options.\n");
4840 /* shift 16 bits at a time to fill 64 bits */
4841 ldo->phy_type_low |= ((u64)buf << (i * 16));
4844 /* PHY types high */
4845 offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_PHY_OFFSET +
4846 ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS;
4847 for (i = 0; i < ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS; i++) {
4848 status = ice_read_sr_word(hw, (offset + i), &buf);
4850 ice_debug(hw, ICE_DBG_INIT, "Failed to read override link options.\n");
4853 /* shift 16 bits at a time to fill 64 bits */
4854 ldo->phy_type_high |= ((u64)buf << (i * 16));
4861 * ice_is_phy_caps_an_enabled - check if PHY capabilities autoneg is enabled
4862 * @caps: get PHY capability data
4864 bool ice_is_phy_caps_an_enabled(struct ice_aqc_get_phy_caps_data *caps)
4866 if (caps->caps & ICE_AQC_PHY_AN_MODE ||
4867 caps->low_power_ctrl_an & (ICE_AQC_PHY_AN_EN_CLAUSE28 |
4868 ICE_AQC_PHY_AN_EN_CLAUSE73 |
4869 ICE_AQC_PHY_AN_EN_CLAUSE37))
4876 * ice_aq_set_lldp_mib - Set the LLDP MIB
4877 * @hw: pointer to the HW struct
4878 * @mib_type: Local, Remote or both Local and Remote MIBs
4879 * @buf: pointer to the caller-supplied buffer to store the MIB block
4880 * @buf_size: size of the buffer (in bytes)
4881 * @cd: pointer to command details structure or NULL
4883 * Set the LLDP MIB. (0x0A08)
4886 ice_aq_set_lldp_mib(struct ice_hw *hw, u8 mib_type, void *buf, u16 buf_size,
4887 struct ice_sq_cd *cd)
4889 struct ice_aqc_lldp_set_local_mib *cmd;
4890 struct ice_aq_desc desc;
4892 cmd = &desc.params.lldp_set_mib;
4894 if (buf_size == 0 || !buf)
4895 return ICE_ERR_PARAM;
4897 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_lldp_set_local_mib);
4899 desc.flags |= CPU_TO_LE16((u16)ICE_AQ_FLAG_RD);
4900 desc.datalen = CPU_TO_LE16(buf_size);
4902 cmd->type = mib_type;
4903 cmd->length = CPU_TO_LE16(buf_size);
4905 return ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);
4909 * ice_fw_supports_lldp_fltr - check NVM version supports lldp_fltr_ctrl
4910 * @hw: pointer to HW struct
4912 bool ice_fw_supports_lldp_fltr_ctrl(struct ice_hw *hw)
4914 if (hw->mac_type != ICE_MAC_E810)
4917 if (hw->api_maj_ver == ICE_FW_API_LLDP_FLTR_MAJ) {
4918 if (hw->api_min_ver > ICE_FW_API_LLDP_FLTR_MIN)
4920 if (hw->api_min_ver == ICE_FW_API_LLDP_FLTR_MIN &&
4921 hw->api_patch >= ICE_FW_API_LLDP_FLTR_PATCH)
4923 } else if (hw->api_maj_ver > ICE_FW_API_LLDP_FLTR_MAJ) {
4930 * ice_lldp_fltr_add_remove - add or remove a LLDP Rx switch filter
4931 * @hw: pointer to HW struct
4932 * @vsi_num: absolute HW index for VSI
4933 * @add: boolean for if adding or removing a filter
4936 ice_lldp_fltr_add_remove(struct ice_hw *hw, u16 vsi_num, bool add)
4938 struct ice_aqc_lldp_filter_ctrl *cmd;
4939 struct ice_aq_desc desc;
4941 cmd = &desc.params.lldp_filter_ctrl;
4943 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_lldp_filter_ctrl);
4946 cmd->cmd_flags = ICE_AQC_LLDP_FILTER_ACTION_ADD;
4948 cmd->cmd_flags = ICE_AQC_LLDP_FILTER_ACTION_DELETE;
4950 cmd->vsi_num = CPU_TO_LE16(vsi_num);
4952 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);