1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2001-2019
5 #include "ice_common.h"
7 #include "ice_adminq_cmd.h"
10 #include "ice_switch.h"
12 #define ICE_PF_RESET_WAIT_COUNT 200
14 #define ICE_PROG_FLEX_ENTRY(hw, rxdid, mdid, idx) \
15 wr32((hw), GLFLXP_RXDID_FLX_WRD_##idx(rxdid), \
16 ((ICE_RX_OPC_MDID << \
17 GLFLXP_RXDID_FLX_WRD_##idx##_RXDID_OPCODE_S) & \
18 GLFLXP_RXDID_FLX_WRD_##idx##_RXDID_OPCODE_M) | \
19 (((mdid) << GLFLXP_RXDID_FLX_WRD_##idx##_PROT_MDID_S) & \
20 GLFLXP_RXDID_FLX_WRD_##idx##_PROT_MDID_M))
22 #define ICE_PROG_FLG_ENTRY(hw, rxdid, flg_0, flg_1, flg_2, flg_3, idx) \
23 wr32((hw), GLFLXP_RXDID_FLAGS(rxdid, idx), \
24 (((flg_0) << GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_S) & \
25 GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_M) | \
26 (((flg_1) << GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_1_S) & \
27 GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_1_M) | \
28 (((flg_2) << GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_2_S) & \
29 GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_2_M) | \
30 (((flg_3) << GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_3_S) & \
31 GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_3_M))
35 * ice_set_mac_type - Sets MAC type
36 * @hw: pointer to the HW structure
38 * This function sets the MAC type of the adapter based on the
39 * vendor ID and device ID stored in the HW structure.
41 static enum ice_status ice_set_mac_type(struct ice_hw *hw)
43 enum ice_status status = ICE_SUCCESS;
45 ice_debug(hw, ICE_DBG_TRACE, "ice_set_mac_type\n");
47 if (hw->vendor_id == ICE_INTEL_VENDOR_ID) {
48 switch (hw->device_id) {
50 hw->mac_type = ICE_MAC_GENERIC;
54 status = ICE_ERR_DEVICE_NOT_SUPPORTED;
57 ice_debug(hw, ICE_DBG_INIT, "found mac_type: %d, status: %d\n",
58 hw->mac_type, status);
65 * ice_clear_pf_cfg - Clear PF configuration
66 * @hw: pointer to the hardware structure
68 * Clears any existing PF configuration (VSIs, VSI lists, switch rules, port
69 * configuration, flow director filters, etc.).
71 enum ice_status ice_clear_pf_cfg(struct ice_hw *hw)
73 struct ice_aq_desc desc;
75 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pf_cfg);
77 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
81 * ice_aq_manage_mac_read - manage MAC address read command
82 * @hw: pointer to the HW struct
83 * @buf: a virtual buffer to hold the manage MAC read response
84 * @buf_size: Size of the virtual buffer
85 * @cd: pointer to command details structure or NULL
87 * This function is used to return per PF station MAC address (0x0107).
88 * NOTE: Upon successful completion of this command, MAC address information
89 * is returned in user specified buffer. Please interpret user specified
90 * buffer as "manage_mac_read" response.
91 * Response such as various MAC addresses are stored in HW struct (port.mac)
92 * ice_aq_discover_caps is expected to be called before this function is called.
94 static enum ice_status
95 ice_aq_manage_mac_read(struct ice_hw *hw, void *buf, u16 buf_size,
98 struct ice_aqc_manage_mac_read_resp *resp;
99 struct ice_aqc_manage_mac_read *cmd;
100 struct ice_aq_desc desc;
101 enum ice_status status;
105 cmd = &desc.params.mac_read;
107 if (buf_size < sizeof(*resp))
108 return ICE_ERR_BUF_TOO_SHORT;
110 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_read);
112 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);
116 resp = (struct ice_aqc_manage_mac_read_resp *)buf;
117 flags = LE16_TO_CPU(cmd->flags) & ICE_AQC_MAN_MAC_READ_M;
119 if (!(flags & ICE_AQC_MAN_MAC_LAN_ADDR_VALID)) {
120 ice_debug(hw, ICE_DBG_LAN, "got invalid MAC address\n");
124 /* A single port can report up to two (LAN and WoL) addresses */
125 for (i = 0; i < cmd->num_addr; i++)
126 if (resp[i].addr_type == ICE_AQC_MAN_MAC_ADDR_TYPE_LAN) {
127 ice_memcpy(hw->port_info->mac.lan_addr,
128 resp[i].mac_addr, ETH_ALEN,
130 ice_memcpy(hw->port_info->mac.perm_addr,
132 ETH_ALEN, ICE_DMA_TO_NONDMA);
140 * ice_aq_get_phy_caps - returns PHY capabilities
141 * @pi: port information structure
142 * @qual_mods: report qualified modules
143 * @report_mode: report mode capabilities
144 * @pcaps: structure for PHY capabilities to be filled
145 * @cd: pointer to command details structure or NULL
147 * Returns the various PHY capabilities supported on the Port (0x0600)
150 ice_aq_get_phy_caps(struct ice_port_info *pi, bool qual_mods, u8 report_mode,
151 struct ice_aqc_get_phy_caps_data *pcaps,
152 struct ice_sq_cd *cd)
154 struct ice_aqc_get_phy_caps *cmd;
155 u16 pcaps_size = sizeof(*pcaps);
156 struct ice_aq_desc desc;
157 enum ice_status status;
159 cmd = &desc.params.get_phy;
161 if (!pcaps || (report_mode & ~ICE_AQC_REPORT_MODE_M) || !pi)
162 return ICE_ERR_PARAM;
164 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_phy_caps);
167 cmd->param0 |= CPU_TO_LE16(ICE_AQC_GET_PHY_RQM);
169 cmd->param0 |= CPU_TO_LE16(report_mode);
170 status = ice_aq_send_cmd(pi->hw, &desc, pcaps, pcaps_size, cd);
172 if (status == ICE_SUCCESS && report_mode == ICE_AQC_REPORT_TOPO_CAP) {
173 pi->phy.phy_type_low = LE64_TO_CPU(pcaps->phy_type_low);
174 pi->phy.phy_type_high = LE64_TO_CPU(pcaps->phy_type_high);
181 * ice_get_media_type - Gets media type
182 * @pi: port information structure
184 static enum ice_media_type ice_get_media_type(struct ice_port_info *pi)
186 struct ice_link_status *hw_link_info;
189 return ICE_MEDIA_UNKNOWN;
191 hw_link_info = &pi->phy.link_info;
192 if (hw_link_info->phy_type_low && hw_link_info->phy_type_high)
193 /* If more than one media type is selected, report unknown */
194 return ICE_MEDIA_UNKNOWN;
196 if (hw_link_info->phy_type_low) {
197 switch (hw_link_info->phy_type_low) {
198 case ICE_PHY_TYPE_LOW_1000BASE_SX:
199 case ICE_PHY_TYPE_LOW_1000BASE_LX:
200 case ICE_PHY_TYPE_LOW_10GBASE_SR:
201 case ICE_PHY_TYPE_LOW_10GBASE_LR:
202 case ICE_PHY_TYPE_LOW_10G_SFI_C2C:
203 case ICE_PHY_TYPE_LOW_25GBASE_SR:
204 case ICE_PHY_TYPE_LOW_25GBASE_LR:
205 case ICE_PHY_TYPE_LOW_25G_AUI_C2C:
206 case ICE_PHY_TYPE_LOW_40GBASE_SR4:
207 case ICE_PHY_TYPE_LOW_40GBASE_LR4:
208 case ICE_PHY_TYPE_LOW_50GBASE_SR2:
209 case ICE_PHY_TYPE_LOW_50GBASE_LR2:
210 case ICE_PHY_TYPE_LOW_50GBASE_SR:
211 case ICE_PHY_TYPE_LOW_50GBASE_FR:
212 case ICE_PHY_TYPE_LOW_50GBASE_LR:
213 case ICE_PHY_TYPE_LOW_100GBASE_SR4:
214 case ICE_PHY_TYPE_LOW_100GBASE_LR4:
215 case ICE_PHY_TYPE_LOW_100GBASE_SR2:
216 case ICE_PHY_TYPE_LOW_100GBASE_DR:
217 return ICE_MEDIA_FIBER;
218 case ICE_PHY_TYPE_LOW_100BASE_TX:
219 case ICE_PHY_TYPE_LOW_1000BASE_T:
220 case ICE_PHY_TYPE_LOW_2500BASE_T:
221 case ICE_PHY_TYPE_LOW_5GBASE_T:
222 case ICE_PHY_TYPE_LOW_10GBASE_T:
223 case ICE_PHY_TYPE_LOW_25GBASE_T:
224 return ICE_MEDIA_BASET;
225 case ICE_PHY_TYPE_LOW_10G_SFI_DA:
226 case ICE_PHY_TYPE_LOW_25GBASE_CR:
227 case ICE_PHY_TYPE_LOW_25GBASE_CR_S:
228 case ICE_PHY_TYPE_LOW_25GBASE_CR1:
229 case ICE_PHY_TYPE_LOW_40GBASE_CR4:
230 case ICE_PHY_TYPE_LOW_50GBASE_CR2:
231 case ICE_PHY_TYPE_LOW_50GBASE_CP:
232 case ICE_PHY_TYPE_LOW_100GBASE_CR4:
233 case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4:
234 case ICE_PHY_TYPE_LOW_100GBASE_CP2:
236 case ICE_PHY_TYPE_LOW_1000BASE_KX:
237 case ICE_PHY_TYPE_LOW_2500BASE_KX:
238 case ICE_PHY_TYPE_LOW_2500BASE_X:
239 case ICE_PHY_TYPE_LOW_5GBASE_KR:
240 case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1:
241 case ICE_PHY_TYPE_LOW_25GBASE_KR:
242 case ICE_PHY_TYPE_LOW_25GBASE_KR1:
243 case ICE_PHY_TYPE_LOW_25GBASE_KR_S:
244 case ICE_PHY_TYPE_LOW_40GBASE_KR4:
245 case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4:
246 case ICE_PHY_TYPE_LOW_50GBASE_KR2:
247 case ICE_PHY_TYPE_LOW_100GBASE_KR4:
248 case ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4:
249 return ICE_MEDIA_BACKPLANE;
252 switch (hw_link_info->phy_type_high) {
253 case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4:
254 return ICE_MEDIA_BACKPLANE;
257 return ICE_MEDIA_UNKNOWN;
261 * ice_aq_get_link_info
262 * @pi: port information structure
263 * @ena_lse: enable/disable LinkStatusEvent reporting
264 * @link: pointer to link status structure - optional
265 * @cd: pointer to command details structure or NULL
267 * Get Link Status (0x607). Returns the link status of the adapter.
270 ice_aq_get_link_info(struct ice_port_info *pi, bool ena_lse,
271 struct ice_link_status *link, struct ice_sq_cd *cd)
273 struct ice_aqc_get_link_status_data link_data = { 0 };
274 struct ice_aqc_get_link_status *resp;
275 struct ice_link_status *li_old, *li;
276 enum ice_media_type *hw_media_type;
277 struct ice_fc_info *hw_fc_info;
278 bool tx_pause, rx_pause;
279 struct ice_aq_desc desc;
280 enum ice_status status;
285 return ICE_ERR_PARAM;
287 li_old = &pi->phy.link_info_old;
288 hw_media_type = &pi->phy.media_type;
289 li = &pi->phy.link_info;
290 hw_fc_info = &pi->fc;
292 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_status);
293 cmd_flags = (ena_lse) ? ICE_AQ_LSE_ENA : ICE_AQ_LSE_DIS;
294 resp = &desc.params.get_link_status;
295 resp->cmd_flags = CPU_TO_LE16(cmd_flags);
296 resp->lport_num = pi->lport;
298 status = ice_aq_send_cmd(hw, &desc, &link_data, sizeof(link_data), cd);
300 if (status != ICE_SUCCESS)
303 /* save off old link status information */
306 /* update current link status information */
307 li->link_speed = LE16_TO_CPU(link_data.link_speed);
308 li->phy_type_low = LE64_TO_CPU(link_data.phy_type_low);
309 li->phy_type_high = LE64_TO_CPU(link_data.phy_type_high);
310 *hw_media_type = ice_get_media_type(pi);
311 li->link_info = link_data.link_info;
312 li->an_info = link_data.an_info;
313 li->ext_info = link_data.ext_info;
314 li->max_frame_size = LE16_TO_CPU(link_data.max_frame_size);
315 li->fec_info = link_data.cfg & ICE_AQ_FEC_MASK;
316 li->topo_media_conflict = link_data.topo_media_conflict;
317 li->pacing = link_data.cfg & (ICE_AQ_CFG_PACING_M |
318 ICE_AQ_CFG_PACING_TYPE_M);
321 tx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_TX);
322 rx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_RX);
323 if (tx_pause && rx_pause)
324 hw_fc_info->current_mode = ICE_FC_FULL;
326 hw_fc_info->current_mode = ICE_FC_TX_PAUSE;
328 hw_fc_info->current_mode = ICE_FC_RX_PAUSE;
330 hw_fc_info->current_mode = ICE_FC_NONE;
332 li->lse_ena = !!(resp->cmd_flags & CPU_TO_LE16(ICE_AQ_LSE_IS_ENABLED));
334 ice_debug(hw, ICE_DBG_LINK, "link_speed = 0x%x\n", li->link_speed);
335 ice_debug(hw, ICE_DBG_LINK, "phy_type_low = 0x%llx\n",
336 (unsigned long long)li->phy_type_low);
337 ice_debug(hw, ICE_DBG_LINK, "phy_type_high = 0x%llx\n",
338 (unsigned long long)li->phy_type_high);
339 ice_debug(hw, ICE_DBG_LINK, "media_type = 0x%x\n", *hw_media_type);
340 ice_debug(hw, ICE_DBG_LINK, "link_info = 0x%x\n", li->link_info);
341 ice_debug(hw, ICE_DBG_LINK, "an_info = 0x%x\n", li->an_info);
342 ice_debug(hw, ICE_DBG_LINK, "ext_info = 0x%x\n", li->ext_info);
343 ice_debug(hw, ICE_DBG_LINK, "lse_ena = 0x%x\n", li->lse_ena);
344 ice_debug(hw, ICE_DBG_LINK, "max_frame = 0x%x\n", li->max_frame_size);
345 ice_debug(hw, ICE_DBG_LINK, "pacing = 0x%x\n", li->pacing);
347 /* save link status information */
351 /* flag cleared so calling functions don't call AQ again */
352 pi->phy.get_link_info = false;
358 * ice_init_flex_flags
359 * @hw: pointer to the hardware structure
360 * @prof_id: Rx Descriptor Builder profile ID
362 * Function to initialize Rx flex flags
364 static void ice_init_flex_flags(struct ice_hw *hw, enum ice_rxdid prof_id)
368 /* Flex-flag fields (0-2) are programmed with FLG64 bits with layout:
369 * flexiflags0[5:0] - TCP flags, is_packet_fragmented, is_packet_UDP_GRE
370 * flexiflags1[3:0] - Not used for flag programming
371 * flexiflags2[7:0] - Tunnel and VLAN types
372 * 2 invalid fields in last index
375 /* Rx flex flags are currently programmed for the NIC profiles only.
376 * Different flag bit programming configurations can be added per
379 case ICE_RXDID_FLEX_NIC:
380 case ICE_RXDID_FLEX_NIC_2:
381 ICE_PROG_FLG_ENTRY(hw, prof_id, ICE_FLG_PKT_FRG,
382 ICE_FLG_UDP_GRE, ICE_FLG_PKT_DSI,
384 /* flex flag 1 is not used for flexi-flag programming, skipping
385 * these four FLG64 bits.
387 ICE_PROG_FLG_ENTRY(hw, prof_id, ICE_FLG_SYN, ICE_FLG_RST,
388 ICE_FLG_PKT_DSI, ICE_FLG_PKT_DSI, idx++);
389 ICE_PROG_FLG_ENTRY(hw, prof_id, ICE_FLG_PKT_DSI,
390 ICE_FLG_PKT_DSI, ICE_FLG_EVLAN_x8100,
391 ICE_FLG_EVLAN_x9100, idx++);
392 ICE_PROG_FLG_ENTRY(hw, prof_id, ICE_FLG_VLAN_x8100,
393 ICE_FLG_TNL_VLAN, ICE_FLG_TNL_MAC,
394 ICE_FLG_TNL0, idx++);
395 ICE_PROG_FLG_ENTRY(hw, prof_id, ICE_FLG_TNL1, ICE_FLG_TNL2,
396 ICE_FLG_PKT_DSI, ICE_FLG_PKT_DSI, idx);
400 ice_debug(hw, ICE_DBG_INIT,
401 "Flag programming for profile ID %d not supported\n",
408 * @hw: pointer to the hardware structure
409 * @prof_id: Rx Descriptor Builder profile ID
411 * Function to initialize flex descriptors
413 static void ice_init_flex_flds(struct ice_hw *hw, enum ice_rxdid prof_id)
415 enum ice_flex_mdid mdid;
418 case ICE_RXDID_FLEX_NIC:
419 case ICE_RXDID_FLEX_NIC_2:
420 ICE_PROG_FLEX_ENTRY(hw, prof_id, ICE_MDID_RX_HASH_LOW, 0);
421 ICE_PROG_FLEX_ENTRY(hw, prof_id, ICE_MDID_RX_HASH_HIGH, 1);
422 ICE_PROG_FLEX_ENTRY(hw, prof_id, ICE_MDID_FLOW_ID_LOWER, 2);
424 mdid = (prof_id == ICE_RXDID_FLEX_NIC_2) ?
425 ICE_MDID_SRC_VSI : ICE_MDID_FLOW_ID_HIGH;
427 ICE_PROG_FLEX_ENTRY(hw, prof_id, mdid, 3);
429 ice_init_flex_flags(hw, prof_id);
433 ice_debug(hw, ICE_DBG_INIT,
434 "Field init for profile ID %d not supported\n",
441 * @hw: pointer to the HW struct
442 * @max_frame_size: Maximum Frame Size to be supported
443 * @cd: pointer to command details structure or NULL
445 * Set MAC configuration (0x0603)
448 ice_aq_set_mac_cfg(struct ice_hw *hw, u16 max_frame_size, struct ice_sq_cd *cd)
450 u16 fc_threshold_val, tx_timer_val;
451 struct ice_aqc_set_mac_cfg *cmd;
452 struct ice_port_info *pi;
453 struct ice_aq_desc desc;
454 enum ice_status status;
459 cmd = &desc.params.set_mac_cfg;
461 if (max_frame_size == 0)
462 return ICE_ERR_PARAM;
464 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_mac_cfg);
466 cmd->max_frame_size = CPU_TO_LE16(max_frame_size);
468 /* Retrieve the current data_pacing value in FW*/
469 pi = &hw->port_info[port_num];
471 /* We turn on the get_link_info so that ice_update_link_info(...)
474 pi->phy.get_link_info = 1;
476 status = ice_get_link_status(pi, &link_up);
481 cmd->params = pi->phy.link_info.pacing;
483 /* We read back the transmit timer and fc threshold value of
484 * LFC. Thus, we will use index =
485 * PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX.
487 * Also, because we are opearating on transmit timer and fc
488 * threshold of LFC, we don't turn on any bit in tx_tmr_priority
490 #define IDX_OF_LFC PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX
492 /* Retrieve the transmit timer */
494 PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(IDX_OF_LFC));
495 tx_timer_val = reg_val &
496 PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_HSEC_CTL_TX_PAUSE_QUANTA_M;
497 cmd->tx_tmr_value = CPU_TO_LE16(tx_timer_val);
499 /* Retrieve the fc threshold */
501 PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(IDX_OF_LFC));
502 fc_threshold_val = reg_val & MAKEMASK(0xFFFF, 0);
503 cmd->fc_refresh_threshold = CPU_TO_LE16(fc_threshold_val);
505 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
509 * ice_init_fltr_mgmt_struct - initializes filter management list and locks
510 * @hw: pointer to the HW struct
512 static enum ice_status ice_init_fltr_mgmt_struct(struct ice_hw *hw)
514 struct ice_switch_info *sw;
516 hw->switch_info = (struct ice_switch_info *)
517 ice_malloc(hw, sizeof(*hw->switch_info));
518 sw = hw->switch_info;
521 return ICE_ERR_NO_MEMORY;
523 INIT_LIST_HEAD(&sw->vsi_list_map_head);
525 return ice_init_def_sw_recp(hw);
529 * ice_cleanup_fltr_mgmt_struct - cleanup filter management list and locks
530 * @hw: pointer to the HW struct
532 static void ice_cleanup_fltr_mgmt_struct(struct ice_hw *hw)
534 struct ice_switch_info *sw = hw->switch_info;
535 struct ice_vsi_list_map_info *v_pos_map;
536 struct ice_vsi_list_map_info *v_tmp_map;
537 struct ice_sw_recipe *recps;
540 LIST_FOR_EACH_ENTRY_SAFE(v_pos_map, v_tmp_map, &sw->vsi_list_map_head,
541 ice_vsi_list_map_info, list_entry) {
542 LIST_DEL(&v_pos_map->list_entry);
543 ice_free(hw, v_pos_map);
545 recps = hw->switch_info->recp_list;
546 for (i = 0; i < ICE_MAX_NUM_RECIPES; i++) {
547 recps[i].root_rid = i;
549 if (recps[i].adv_rule) {
550 struct ice_adv_fltr_mgmt_list_entry *tmp_entry;
551 struct ice_adv_fltr_mgmt_list_entry *lst_itr;
553 ice_destroy_lock(&recps[i].filt_rule_lock);
554 LIST_FOR_EACH_ENTRY_SAFE(lst_itr, tmp_entry,
555 &recps[i].filt_rules,
556 ice_adv_fltr_mgmt_list_entry,
558 LIST_DEL(&lst_itr->list_entry);
559 ice_free(hw, lst_itr->lkups);
560 ice_free(hw, lst_itr);
563 struct ice_fltr_mgmt_list_entry *lst_itr, *tmp_entry;
565 ice_destroy_lock(&recps[i].filt_rule_lock);
566 LIST_FOR_EACH_ENTRY_SAFE(lst_itr, tmp_entry,
567 &recps[i].filt_rules,
568 ice_fltr_mgmt_list_entry,
570 LIST_DEL(&lst_itr->list_entry);
571 ice_free(hw, lst_itr);
575 ice_rm_all_sw_replay_rule_info(hw);
576 ice_free(hw, sw->recp_list);
580 #define ICE_FW_LOG_DESC_SIZE(n) (sizeof(struct ice_aqc_fw_logging_data) + \
581 (((n) - 1) * sizeof(((struct ice_aqc_fw_logging_data *)0)->entry)))
582 #define ICE_FW_LOG_DESC_SIZE_MAX \
583 ICE_FW_LOG_DESC_SIZE(ICE_AQC_FW_LOG_ID_MAX)
586 * ice_get_fw_log_cfg - get FW logging configuration
587 * @hw: pointer to the HW struct
589 static enum ice_status ice_get_fw_log_cfg(struct ice_hw *hw)
591 struct ice_aqc_fw_logging_data *config;
592 struct ice_aq_desc desc;
593 enum ice_status status;
596 size = ICE_FW_LOG_DESC_SIZE_MAX;
597 config = (struct ice_aqc_fw_logging_data *)ice_malloc(hw, size);
599 return ICE_ERR_NO_MEMORY;
601 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_fw_logging_info);
603 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_BUF);
604 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
606 status = ice_aq_send_cmd(hw, &desc, config, size, NULL);
610 /* Save fw logging information into the HW structure */
611 for (i = 0; i < ICE_AQC_FW_LOG_ID_MAX; i++) {
614 v = LE16_TO_CPU(config->entry[i]);
615 m = (v & ICE_AQC_FW_LOG_ID_M) >> ICE_AQC_FW_LOG_ID_S;
616 flgs = (v & ICE_AQC_FW_LOG_EN_M) >> ICE_AQC_FW_LOG_EN_S;
618 if (m < ICE_AQC_FW_LOG_ID_MAX)
619 hw->fw_log.evnts[m].cur = flgs;
623 ice_free(hw, config);
629 * ice_cfg_fw_log - configure FW logging
630 * @hw: pointer to the HW struct
631 * @enable: enable certain FW logging events if true, disable all if false
633 * This function enables/disables the FW logging via Rx CQ events and a UART
634 * port based on predetermined configurations. FW logging via the Rx CQ can be
635 * enabled/disabled for individual PF's. However, FW logging via the UART can
636 * only be enabled/disabled for all PFs on the same device.
638 * To enable overall FW logging, the "cq_en" and "uart_en" enable bits in
639 * hw->fw_log need to be set accordingly, e.g. based on user-provided input,
640 * before initializing the device.
642 * When re/configuring FW logging, callers need to update the "cfg" elements of
643 * the hw->fw_log.evnts array with the desired logging event configurations for
644 * modules of interest. When disabling FW logging completely, the callers can
645 * just pass false in the "enable" parameter. On completion, the function will
646 * update the "cur" element of the hw->fw_log.evnts array with the resulting
647 * logging event configurations of the modules that are being re/configured. FW
648 * logging modules that are not part of a reconfiguration operation retain their
651 * Before resetting the device, it is recommended that the driver disables FW
652 * logging before shutting down the control queue. When disabling FW logging
653 * ("enable" = false), the latest configurations of FW logging events stored in
654 * hw->fw_log.evnts[] are not overridden to allow them to be reconfigured after
657 * When enabling FW logging to emit log messages via the Rx CQ during the
658 * device's initialization phase, a mechanism alternative to interrupt handlers
659 * needs to be used to extract FW log messages from the Rx CQ periodically and
660 * to prevent the Rx CQ from being full and stalling other types of control
661 * messages from FW to SW. Interrupts are typically disabled during the device's
662 * initialization phase.
664 static enum ice_status ice_cfg_fw_log(struct ice_hw *hw, bool enable)
666 struct ice_aqc_fw_logging_data *data = NULL;
667 struct ice_aqc_fw_logging *cmd;
668 enum ice_status status = ICE_SUCCESS;
669 u16 i, chgs = 0, len = 0;
670 struct ice_aq_desc desc;
674 if (!hw->fw_log.cq_en && !hw->fw_log.uart_en)
677 /* Disable FW logging only when the control queue is still responsive */
679 (!hw->fw_log.actv_evnts || !ice_check_sq_alive(hw, &hw->adminq)))
682 /* Get current FW log settings */
683 status = ice_get_fw_log_cfg(hw);
687 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_fw_logging);
688 cmd = &desc.params.fw_logging;
690 /* Indicate which controls are valid */
691 if (hw->fw_log.cq_en)
692 cmd->log_ctrl_valid |= ICE_AQC_FW_LOG_AQ_VALID;
694 if (hw->fw_log.uart_en)
695 cmd->log_ctrl_valid |= ICE_AQC_FW_LOG_UART_VALID;
698 /* Fill in an array of entries with FW logging modules and
699 * logging events being reconfigured.
701 for (i = 0; i < ICE_AQC_FW_LOG_ID_MAX; i++) {
704 /* Keep track of enabled event types */
705 actv_evnts |= hw->fw_log.evnts[i].cfg;
707 if (hw->fw_log.evnts[i].cfg == hw->fw_log.evnts[i].cur)
711 data = (struct ice_aqc_fw_logging_data *)
713 ICE_FW_LOG_DESC_SIZE_MAX);
715 return ICE_ERR_NO_MEMORY;
718 val = i << ICE_AQC_FW_LOG_ID_S;
719 val |= hw->fw_log.evnts[i].cfg << ICE_AQC_FW_LOG_EN_S;
720 data->entry[chgs++] = CPU_TO_LE16(val);
723 /* Only enable FW logging if at least one module is specified.
724 * If FW logging is currently enabled but all modules are not
725 * enabled to emit log messages, disable FW logging altogether.
728 /* Leave if there is effectively no change */
732 if (hw->fw_log.cq_en)
733 cmd->log_ctrl |= ICE_AQC_FW_LOG_AQ_EN;
735 if (hw->fw_log.uart_en)
736 cmd->log_ctrl |= ICE_AQC_FW_LOG_UART_EN;
739 len = ICE_FW_LOG_DESC_SIZE(chgs);
740 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
744 status = ice_aq_send_cmd(hw, &desc, buf, len, NULL);
746 /* Update the current configuration to reflect events enabled.
747 * hw->fw_log.cq_en and hw->fw_log.uart_en indicate if the FW
748 * logging mode is enabled for the device. They do not reflect
749 * actual modules being enabled to emit log messages. So, their
750 * values remain unchanged even when all modules are disabled.
752 u16 cnt = enable ? chgs : (u16)ICE_AQC_FW_LOG_ID_MAX;
754 hw->fw_log.actv_evnts = actv_evnts;
755 for (i = 0; i < cnt; i++) {
759 /* When disabling all FW logging events as part
760 * of device's de-initialization, the original
761 * configurations are retained, and can be used
762 * to reconfigure FW logging later if the device
765 hw->fw_log.evnts[i].cur = 0;
769 v = LE16_TO_CPU(data->entry[i]);
770 m = (v & ICE_AQC_FW_LOG_ID_M) >> ICE_AQC_FW_LOG_ID_S;
771 hw->fw_log.evnts[m].cur = hw->fw_log.evnts[m].cfg;
784 * @hw: pointer to the HW struct
785 * @desc: pointer to the AQ message descriptor
786 * @buf: pointer to the buffer accompanying the AQ message
788 * Formats a FW Log message and outputs it via the standard driver logs.
790 void ice_output_fw_log(struct ice_hw *hw, struct ice_aq_desc *desc, void *buf)
792 ice_debug(hw, ICE_DBG_AQ_MSG, "[ FW Log Msg Start ]\n");
793 ice_debug_array(hw, ICE_DBG_AQ_MSG, 16, 1, (u8 *)buf,
794 LE16_TO_CPU(desc->datalen));
795 ice_debug(hw, ICE_DBG_AQ_MSG, "[ FW Log Msg End ]\n");
799 * ice_get_itr_intrl_gran - determine int/intrl granularity
800 * @hw: pointer to the HW struct
802 * Determines the itr/intrl granularities based on the maximum aggregate
803 * bandwidth according to the device's configuration during power-on.
805 static void ice_get_itr_intrl_gran(struct ice_hw *hw)
807 u8 max_agg_bw = (rd32(hw, GL_PWR_MODE_CTL) &
808 GL_PWR_MODE_CTL_CAR_MAX_BW_M) >>
809 GL_PWR_MODE_CTL_CAR_MAX_BW_S;
811 switch (max_agg_bw) {
812 case ICE_MAX_AGG_BW_200G:
813 case ICE_MAX_AGG_BW_100G:
814 case ICE_MAX_AGG_BW_50G:
815 hw->itr_gran = ICE_ITR_GRAN_ABOVE_25;
816 hw->intrl_gran = ICE_INTRL_GRAN_ABOVE_25;
818 case ICE_MAX_AGG_BW_25G:
819 hw->itr_gran = ICE_ITR_GRAN_MAX_25;
820 hw->intrl_gran = ICE_INTRL_GRAN_MAX_25;
826 * ice_init_hw - main hardware initialization routine
827 * @hw: pointer to the hardware structure
829 enum ice_status ice_init_hw(struct ice_hw *hw)
831 struct ice_aqc_get_phy_caps_data *pcaps;
832 enum ice_status status;
836 ice_debug(hw, ICE_DBG_TRACE, "ice_init_hw");
839 /* Set MAC type based on DeviceID */
840 status = ice_set_mac_type(hw);
844 hw->pf_id = (u8)(rd32(hw, PF_FUNC_RID) &
845 PF_FUNC_RID_FUNCTION_NUMBER_M) >>
846 PF_FUNC_RID_FUNCTION_NUMBER_S;
849 status = ice_reset(hw, ICE_RESET_PFR);
853 ice_get_itr_intrl_gran(hw);
856 status = ice_init_all_ctrlq(hw);
858 goto err_unroll_cqinit;
860 /* Enable FW logging. Not fatal if this fails. */
861 status = ice_cfg_fw_log(hw, true);
863 ice_debug(hw, ICE_DBG_INIT, "Failed to enable FW logging.\n");
865 status = ice_clear_pf_cfg(hw);
867 goto err_unroll_cqinit;
869 /* Set bit to enable Flow Director filters */
870 wr32(hw, PFQF_FD_ENA, PFQF_FD_ENA_FD_ENA_M);
871 INIT_LIST_HEAD(&hw->fdir_list_head);
873 ice_clear_pxe_mode(hw);
875 status = ice_init_nvm(hw);
877 goto err_unroll_cqinit;
879 status = ice_get_caps(hw);
881 goto err_unroll_cqinit;
883 hw->port_info = (struct ice_port_info *)
884 ice_malloc(hw, sizeof(*hw->port_info));
885 if (!hw->port_info) {
886 status = ICE_ERR_NO_MEMORY;
887 goto err_unroll_cqinit;
890 /* set the back pointer to HW */
891 hw->port_info->hw = hw;
893 /* Initialize port_info struct with switch configuration data */
894 status = ice_get_initial_sw_cfg(hw);
896 goto err_unroll_alloc;
900 /* Query the allocated resources for Tx scheduler */
901 status = ice_sched_query_res_alloc(hw);
903 ice_debug(hw, ICE_DBG_SCHED,
904 "Failed to get scheduler allocated resources\n");
905 goto err_unroll_alloc;
909 /* Initialize port_info struct with scheduler data */
910 status = ice_sched_init_port(hw->port_info);
912 goto err_unroll_sched;
914 pcaps = (struct ice_aqc_get_phy_caps_data *)
915 ice_malloc(hw, sizeof(*pcaps));
917 status = ICE_ERR_NO_MEMORY;
918 goto err_unroll_sched;
921 /* Initialize port_info struct with PHY capabilities */
922 status = ice_aq_get_phy_caps(hw->port_info, false,
923 ICE_AQC_REPORT_TOPO_CAP, pcaps, NULL);
926 goto err_unroll_sched;
928 /* Initialize port_info struct with link information */
929 status = ice_aq_get_link_info(hw->port_info, false, NULL, NULL);
931 goto err_unroll_sched;
932 /* need a valid SW entry point to build a Tx tree */
933 if (!hw->sw_entry_point_layer) {
934 ice_debug(hw, ICE_DBG_SCHED, "invalid sw entry point\n");
935 status = ICE_ERR_CFG;
936 goto err_unroll_sched;
938 INIT_LIST_HEAD(&hw->agg_list);
939 /* Initialize max burst size */
940 if (!hw->max_burst_size)
941 ice_cfg_rl_burst_size(hw, ICE_SCHED_DFLT_BURST_SIZE);
943 status = ice_init_fltr_mgmt_struct(hw);
945 goto err_unroll_sched;
948 /* Get MAC information */
949 /* A single port can report up to two (LAN and WoL) addresses */
950 mac_buf = ice_calloc(hw, 2,
951 sizeof(struct ice_aqc_manage_mac_read_resp));
952 mac_buf_len = 2 * sizeof(struct ice_aqc_manage_mac_read_resp);
955 status = ICE_ERR_NO_MEMORY;
956 goto err_unroll_fltr_mgmt_struct;
959 status = ice_aq_manage_mac_read(hw, mac_buf, mac_buf_len, NULL);
960 ice_free(hw, mac_buf);
963 goto err_unroll_fltr_mgmt_struct;
965 ice_init_flex_flds(hw, ICE_RXDID_FLEX_NIC);
966 ice_init_flex_flds(hw, ICE_RXDID_FLEX_NIC_2);
967 /* Obtain counter base index which would be used by flow director */
968 status = ice_alloc_fd_res_cntr(hw, &hw->fd_ctr_base);
970 goto err_unroll_fltr_mgmt_struct;
971 status = ice_init_hw_tbls(hw);
973 goto err_unroll_fltr_mgmt_struct;
976 err_unroll_fltr_mgmt_struct:
977 ice_cleanup_fltr_mgmt_struct(hw);
979 ice_sched_cleanup_all(hw);
981 ice_free(hw, hw->port_info);
982 hw->port_info = NULL;
984 ice_shutdown_all_ctrlq(hw);
989 * ice_deinit_hw - unroll initialization operations done by ice_init_hw
990 * @hw: pointer to the hardware structure
992 * This should be called only during nominal operation, not as a result of
993 * ice_init_hw() failing since ice_init_hw() will take care of unrolling
994 * applicable initializations if it fails for any reason.
996 void ice_deinit_hw(struct ice_hw *hw)
998 ice_free_fd_res_cntr(hw, hw->fd_ctr_base);
999 ice_cleanup_fltr_mgmt_struct(hw);
1001 ice_sched_cleanup_all(hw);
1002 ice_sched_clear_agg(hw);
1004 ice_free_hw_tbls(hw);
1006 if (hw->port_info) {
1007 ice_free(hw, hw->port_info);
1008 hw->port_info = NULL;
1011 /* Attempt to disable FW logging before shutting down control queues */
1012 ice_cfg_fw_log(hw, false);
1013 ice_shutdown_all_ctrlq(hw);
1015 /* Clear VSI contexts if not already cleared */
1016 ice_clear_all_vsi_ctx(hw);
1020 * ice_check_reset - Check to see if a global reset is complete
1021 * @hw: pointer to the hardware structure
1023 enum ice_status ice_check_reset(struct ice_hw *hw)
1025 u32 cnt, reg = 0, grst_delay;
1027 /* Poll for Device Active state in case a recent CORER, GLOBR,
1028 * or EMPR has occurred. The grst delay value is in 100ms units.
1029 * Add 1sec for outstanding AQ commands that can take a long time.
1031 #define GLGEN_RSTCTL 0x000B8180 /* Reset Source: POR */
1032 #define GLGEN_RSTCTL_GRSTDEL_S 0
1033 #define GLGEN_RSTCTL_GRSTDEL_M MAKEMASK(0x3F, GLGEN_RSTCTL_GRSTDEL_S)
1034 grst_delay = ((rd32(hw, GLGEN_RSTCTL) & GLGEN_RSTCTL_GRSTDEL_M) >>
1035 GLGEN_RSTCTL_GRSTDEL_S) + 10;
1037 for (cnt = 0; cnt < grst_delay; cnt++) {
1038 ice_msec_delay(100, true);
1039 reg = rd32(hw, GLGEN_RSTAT);
1040 if (!(reg & GLGEN_RSTAT_DEVSTATE_M))
1044 if (cnt == grst_delay) {
1045 ice_debug(hw, ICE_DBG_INIT,
1046 "Global reset polling failed to complete.\n");
1047 return ICE_ERR_RESET_FAILED;
1050 #define ICE_RESET_DONE_MASK (GLNVM_ULD_CORER_DONE_M | \
1051 GLNVM_ULD_GLOBR_DONE_M)
1053 /* Device is Active; check Global Reset processes are done */
1054 for (cnt = 0; cnt < ICE_PF_RESET_WAIT_COUNT; cnt++) {
1055 reg = rd32(hw, GLNVM_ULD) & ICE_RESET_DONE_MASK;
1056 if (reg == ICE_RESET_DONE_MASK) {
1057 ice_debug(hw, ICE_DBG_INIT,
1058 "Global reset processes done. %d\n", cnt);
1061 ice_msec_delay(10, true);
1064 if (cnt == ICE_PF_RESET_WAIT_COUNT) {
1065 ice_debug(hw, ICE_DBG_INIT,
1066 "Wait for Reset Done timed out. GLNVM_ULD = 0x%x\n",
1068 return ICE_ERR_RESET_FAILED;
1075 * ice_pf_reset - Reset the PF
1076 * @hw: pointer to the hardware structure
1078 * If a global reset has been triggered, this function checks
1079 * for its completion and then issues the PF reset
1081 static enum ice_status ice_pf_reset(struct ice_hw *hw)
1085 /* If at function entry a global reset was already in progress, i.e.
1086 * state is not 'device active' or any of the reset done bits are not
1087 * set in GLNVM_ULD, there is no need for a PF Reset; poll until the
1088 * global reset is done.
1090 if ((rd32(hw, GLGEN_RSTAT) & GLGEN_RSTAT_DEVSTATE_M) ||
1091 (rd32(hw, GLNVM_ULD) & ICE_RESET_DONE_MASK) ^ ICE_RESET_DONE_MASK) {
1092 /* poll on global reset currently in progress until done */
1093 if (ice_check_reset(hw))
1094 return ICE_ERR_RESET_FAILED;
1100 reg = rd32(hw, PFGEN_CTRL);
1102 wr32(hw, PFGEN_CTRL, (reg | PFGEN_CTRL_PFSWR_M));
1104 for (cnt = 0; cnt < ICE_PF_RESET_WAIT_COUNT; cnt++) {
1105 reg = rd32(hw, PFGEN_CTRL);
1106 if (!(reg & PFGEN_CTRL_PFSWR_M))
1109 ice_msec_delay(1, true);
1112 if (cnt == ICE_PF_RESET_WAIT_COUNT) {
1113 ice_debug(hw, ICE_DBG_INIT,
1114 "PF reset polling failed to complete.\n");
1115 return ICE_ERR_RESET_FAILED;
1122 * ice_reset - Perform different types of reset
1123 * @hw: pointer to the hardware structure
1124 * @req: reset request
1126 * This function triggers a reset as specified by the req parameter.
1129 * If anything other than a PF reset is triggered, PXE mode is restored.
1130 * This has to be cleared using ice_clear_pxe_mode again, once the AQ
1131 * interface has been restored in the rebuild flow.
1133 enum ice_status ice_reset(struct ice_hw *hw, enum ice_reset_req req)
1139 return ice_pf_reset(hw);
1140 case ICE_RESET_CORER:
1141 ice_debug(hw, ICE_DBG_INIT, "CoreR requested\n");
1142 val = GLGEN_RTRIG_CORER_M;
1144 case ICE_RESET_GLOBR:
1145 ice_debug(hw, ICE_DBG_INIT, "GlobalR requested\n");
1146 val = GLGEN_RTRIG_GLOBR_M;
1149 return ICE_ERR_PARAM;
1152 val |= rd32(hw, GLGEN_RTRIG);
1153 wr32(hw, GLGEN_RTRIG, val);
1157 /* wait for the FW to be ready */
1158 return ice_check_reset(hw);
1164 * ice_copy_rxq_ctx_to_hw
1165 * @hw: pointer to the hardware structure
1166 * @ice_rxq_ctx: pointer to the rxq context
1167 * @rxq_index: the index of the Rx queue
1169 * Copies rxq context from dense structure to HW register space
1171 static enum ice_status
1172 ice_copy_rxq_ctx_to_hw(struct ice_hw *hw, u8 *ice_rxq_ctx, u32 rxq_index)
1177 return ICE_ERR_BAD_PTR;
1179 if (rxq_index > QRX_CTRL_MAX_INDEX)
1180 return ICE_ERR_PARAM;
1182 /* Copy each dword separately to HW */
1183 for (i = 0; i < ICE_RXQ_CTX_SIZE_DWORDS; i++) {
1184 wr32(hw, QRX_CONTEXT(i, rxq_index),
1185 *((u32 *)(ice_rxq_ctx + (i * sizeof(u32)))));
1187 ice_debug(hw, ICE_DBG_QCTX, "qrxdata[%d]: %08X\n", i,
1188 *((u32 *)(ice_rxq_ctx + (i * sizeof(u32)))));
1194 /* LAN Rx Queue Context */
1195 static const struct ice_ctx_ele ice_rlan_ctx_info[] = {
1196 /* Field Width LSB */
1197 ICE_CTX_STORE(ice_rlan_ctx, head, 13, 0),
1198 ICE_CTX_STORE(ice_rlan_ctx, cpuid, 8, 13),
1199 ICE_CTX_STORE(ice_rlan_ctx, base, 57, 32),
1200 ICE_CTX_STORE(ice_rlan_ctx, qlen, 13, 89),
1201 ICE_CTX_STORE(ice_rlan_ctx, dbuf, 7, 102),
1202 ICE_CTX_STORE(ice_rlan_ctx, hbuf, 5, 109),
1203 ICE_CTX_STORE(ice_rlan_ctx, dtype, 2, 114),
1204 ICE_CTX_STORE(ice_rlan_ctx, dsize, 1, 116),
1205 ICE_CTX_STORE(ice_rlan_ctx, crcstrip, 1, 117),
1206 ICE_CTX_STORE(ice_rlan_ctx, l2tsel, 1, 119),
1207 ICE_CTX_STORE(ice_rlan_ctx, hsplit_0, 4, 120),
1208 ICE_CTX_STORE(ice_rlan_ctx, hsplit_1, 2, 124),
1209 ICE_CTX_STORE(ice_rlan_ctx, showiv, 1, 127),
1210 ICE_CTX_STORE(ice_rlan_ctx, rxmax, 14, 174),
1211 ICE_CTX_STORE(ice_rlan_ctx, tphrdesc_ena, 1, 193),
1212 ICE_CTX_STORE(ice_rlan_ctx, tphwdesc_ena, 1, 194),
1213 ICE_CTX_STORE(ice_rlan_ctx, tphdata_ena, 1, 195),
1214 ICE_CTX_STORE(ice_rlan_ctx, tphhead_ena, 1, 196),
1215 ICE_CTX_STORE(ice_rlan_ctx, lrxqthresh, 3, 198),
1221 * @hw: pointer to the hardware structure
1222 * @rlan_ctx: pointer to the rxq context
1223 * @rxq_index: the index of the Rx queue
1225 * Converts rxq context from sparse to dense structure and then writes
1226 * it to HW register space
1229 ice_write_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx,
1232 u8 ctx_buf[ICE_RXQ_CTX_SZ] = { 0 };
1234 ice_set_ctx((u8 *)rlan_ctx, ctx_buf, ice_rlan_ctx_info);
1235 return ice_copy_rxq_ctx_to_hw(hw, ctx_buf, rxq_index);
1238 #if !defined(NO_UNUSED_CTX_CODE) || defined(AE_DRIVER)
1241 * @hw: pointer to the hardware structure
1242 * @rxq_index: the index of the Rx queue to clear
1244 * Clears rxq context in HW register space
1246 enum ice_status ice_clear_rxq_ctx(struct ice_hw *hw, u32 rxq_index)
1250 if (rxq_index > QRX_CTRL_MAX_INDEX)
1251 return ICE_ERR_PARAM;
1253 /* Clear each dword register separately */
1254 for (i = 0; i < ICE_RXQ_CTX_SIZE_DWORDS; i++)
1255 wr32(hw, QRX_CONTEXT(i, rxq_index), 0);
1259 #endif /* !NO_UNUSED_CTX_CODE || AE_DRIVER */
1261 /* LAN Tx Queue Context */
1262 const struct ice_ctx_ele ice_tlan_ctx_info[] = {
1263 /* Field Width LSB */
1264 ICE_CTX_STORE(ice_tlan_ctx, base, 57, 0),
1265 ICE_CTX_STORE(ice_tlan_ctx, port_num, 3, 57),
1266 ICE_CTX_STORE(ice_tlan_ctx, cgd_num, 5, 60),
1267 ICE_CTX_STORE(ice_tlan_ctx, pf_num, 3, 65),
1268 ICE_CTX_STORE(ice_tlan_ctx, vmvf_num, 10, 68),
1269 ICE_CTX_STORE(ice_tlan_ctx, vmvf_type, 2, 78),
1270 ICE_CTX_STORE(ice_tlan_ctx, src_vsi, 10, 80),
1271 ICE_CTX_STORE(ice_tlan_ctx, tsyn_ena, 1, 90),
1272 ICE_CTX_STORE(ice_tlan_ctx, alt_vlan, 1, 92),
1273 ICE_CTX_STORE(ice_tlan_ctx, cpuid, 8, 93),
1274 ICE_CTX_STORE(ice_tlan_ctx, wb_mode, 1, 101),
1275 ICE_CTX_STORE(ice_tlan_ctx, tphrd_desc, 1, 102),
1276 ICE_CTX_STORE(ice_tlan_ctx, tphrd, 1, 103),
1277 ICE_CTX_STORE(ice_tlan_ctx, tphwr_desc, 1, 104),
1278 ICE_CTX_STORE(ice_tlan_ctx, cmpq_id, 9, 105),
1279 ICE_CTX_STORE(ice_tlan_ctx, qnum_in_func, 14, 114),
1280 ICE_CTX_STORE(ice_tlan_ctx, itr_notification_mode, 1, 128),
1281 ICE_CTX_STORE(ice_tlan_ctx, adjust_prof_id, 6, 129),
1282 ICE_CTX_STORE(ice_tlan_ctx, qlen, 13, 135),
1283 ICE_CTX_STORE(ice_tlan_ctx, quanta_prof_idx, 4, 148),
1284 ICE_CTX_STORE(ice_tlan_ctx, tso_ena, 1, 152),
1285 ICE_CTX_STORE(ice_tlan_ctx, tso_qnum, 11, 153),
1286 ICE_CTX_STORE(ice_tlan_ctx, legacy_int, 1, 164),
1287 ICE_CTX_STORE(ice_tlan_ctx, drop_ena, 1, 165),
1288 ICE_CTX_STORE(ice_tlan_ctx, cache_prof_idx, 2, 166),
1289 ICE_CTX_STORE(ice_tlan_ctx, pkt_shaper_prof_idx, 3, 168),
1290 ICE_CTX_STORE(ice_tlan_ctx, int_q_state, 110, 171),
1294 #if !defined(NO_UNUSED_CTX_CODE) || defined(AE_DRIVER)
1296 * ice_copy_tx_cmpltnq_ctx_to_hw
1297 * @hw: pointer to the hardware structure
1298 * @ice_tx_cmpltnq_ctx: pointer to the Tx completion queue context
1299 * @tx_cmpltnq_index: the index of the completion queue
1301 * Copies Tx completion queue context from dense structure to HW register space
1303 static enum ice_status
1304 ice_copy_tx_cmpltnq_ctx_to_hw(struct ice_hw *hw, u8 *ice_tx_cmpltnq_ctx,
1305 u32 tx_cmpltnq_index)
1309 if (!ice_tx_cmpltnq_ctx)
1310 return ICE_ERR_BAD_PTR;
1312 if (tx_cmpltnq_index > GLTCLAN_CQ_CNTX0_MAX_INDEX)
1313 return ICE_ERR_PARAM;
1315 /* Copy each dword separately to HW */
1316 for (i = 0; i < ICE_TX_CMPLTNQ_CTX_SIZE_DWORDS; i++) {
1317 wr32(hw, GLTCLAN_CQ_CNTX(i, tx_cmpltnq_index),
1318 *((u32 *)(ice_tx_cmpltnq_ctx + (i * sizeof(u32)))));
1320 ice_debug(hw, ICE_DBG_QCTX, "cmpltnqdata[%d]: %08X\n", i,
1321 *((u32 *)(ice_tx_cmpltnq_ctx + (i * sizeof(u32)))));
1327 /* LAN Tx Completion Queue Context */
1328 static const struct ice_ctx_ele ice_tx_cmpltnq_ctx_info[] = {
1329 /* Field Width LSB */
1330 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, base, 57, 0),
1331 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, q_len, 18, 64),
1332 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, generation, 1, 96),
1333 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, wrt_ptr, 22, 97),
1334 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, pf_num, 3, 128),
1335 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, vmvf_num, 10, 131),
1336 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, vmvf_type, 2, 141),
1337 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, tph_desc_wr, 1, 160),
1338 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, cpuid, 8, 161),
1339 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, cmpltn_cache, 512, 192),
1344 * ice_write_tx_cmpltnq_ctx
1345 * @hw: pointer to the hardware structure
1346 * @tx_cmpltnq_ctx: pointer to the completion queue context
1347 * @tx_cmpltnq_index: the index of the completion queue
1349 * Converts completion queue context from sparse to dense structure and then
1350 * writes it to HW register space
1353 ice_write_tx_cmpltnq_ctx(struct ice_hw *hw,
1354 struct ice_tx_cmpltnq_ctx *tx_cmpltnq_ctx,
1355 u32 tx_cmpltnq_index)
1357 u8 ctx_buf[ICE_TX_CMPLTNQ_CTX_SIZE_DWORDS * sizeof(u32)] = { 0 };
1359 ice_set_ctx((u8 *)tx_cmpltnq_ctx, ctx_buf, ice_tx_cmpltnq_ctx_info);
1360 return ice_copy_tx_cmpltnq_ctx_to_hw(hw, ctx_buf, tx_cmpltnq_index);
1364 * ice_clear_tx_cmpltnq_ctx
1365 * @hw: pointer to the hardware structure
1366 * @tx_cmpltnq_index: the index of the completion queue to clear
1368 * Clears Tx completion queue context in HW register space
1371 ice_clear_tx_cmpltnq_ctx(struct ice_hw *hw, u32 tx_cmpltnq_index)
1375 if (tx_cmpltnq_index > GLTCLAN_CQ_CNTX0_MAX_INDEX)
1376 return ICE_ERR_PARAM;
1378 /* Clear each dword register separately */
1379 for (i = 0; i < ICE_TX_CMPLTNQ_CTX_SIZE_DWORDS; i++)
1380 wr32(hw, GLTCLAN_CQ_CNTX(i, tx_cmpltnq_index), 0);
1386 * ice_copy_tx_drbell_q_ctx_to_hw
1387 * @hw: pointer to the hardware structure
1388 * @ice_tx_drbell_q_ctx: pointer to the doorbell queue context
1389 * @tx_drbell_q_index: the index of the doorbell queue
1391 * Copies doorbell queue context from dense structure to HW register space
1393 static enum ice_status
1394 ice_copy_tx_drbell_q_ctx_to_hw(struct ice_hw *hw, u8 *ice_tx_drbell_q_ctx,
1395 u32 tx_drbell_q_index)
1399 if (!ice_tx_drbell_q_ctx)
1400 return ICE_ERR_BAD_PTR;
1402 if (tx_drbell_q_index > QTX_COMM_DBLQ_DBELL_MAX_INDEX)
1403 return ICE_ERR_PARAM;
1405 /* Copy each dword separately to HW */
1406 for (i = 0; i < ICE_TX_DRBELL_Q_CTX_SIZE_DWORDS; i++) {
1407 wr32(hw, QTX_COMM_DBLQ_CNTX(i, tx_drbell_q_index),
1408 *((u32 *)(ice_tx_drbell_q_ctx + (i * sizeof(u32)))));
1410 ice_debug(hw, ICE_DBG_QCTX, "tx_drbell_qdata[%d]: %08X\n", i,
1411 *((u32 *)(ice_tx_drbell_q_ctx + (i * sizeof(u32)))));
1417 /* LAN Tx Doorbell Queue Context info */
1418 static const struct ice_ctx_ele ice_tx_drbell_q_ctx_info[] = {
1419 /* Field Width LSB */
1420 ICE_CTX_STORE(ice_tx_drbell_q_ctx, base, 57, 0),
1421 ICE_CTX_STORE(ice_tx_drbell_q_ctx, ring_len, 13, 64),
1422 ICE_CTX_STORE(ice_tx_drbell_q_ctx, pf_num, 3, 80),
1423 ICE_CTX_STORE(ice_tx_drbell_q_ctx, vf_num, 8, 84),
1424 ICE_CTX_STORE(ice_tx_drbell_q_ctx, vmvf_type, 2, 94),
1425 ICE_CTX_STORE(ice_tx_drbell_q_ctx, cpuid, 8, 96),
1426 ICE_CTX_STORE(ice_tx_drbell_q_ctx, tph_desc_rd, 1, 104),
1427 ICE_CTX_STORE(ice_tx_drbell_q_ctx, tph_desc_wr, 1, 108),
1428 ICE_CTX_STORE(ice_tx_drbell_q_ctx, db_q_en, 1, 112),
1429 ICE_CTX_STORE(ice_tx_drbell_q_ctx, rd_head, 13, 128),
1430 ICE_CTX_STORE(ice_tx_drbell_q_ctx, rd_tail, 13, 144),
1435 * ice_write_tx_drbell_q_ctx
1436 * @hw: pointer to the hardware structure
1437 * @tx_drbell_q_ctx: pointer to the doorbell queue context
1438 * @tx_drbell_q_index: the index of the doorbell queue
1440 * Converts doorbell queue context from sparse to dense structure and then
1441 * writes it to HW register space
1444 ice_write_tx_drbell_q_ctx(struct ice_hw *hw,
1445 struct ice_tx_drbell_q_ctx *tx_drbell_q_ctx,
1446 u32 tx_drbell_q_index)
1448 u8 ctx_buf[ICE_TX_DRBELL_Q_CTX_SIZE_DWORDS * sizeof(u32)] = { 0 };
1450 ice_set_ctx((u8 *)tx_drbell_q_ctx, ctx_buf, ice_tx_drbell_q_ctx_info);
1451 return ice_copy_tx_drbell_q_ctx_to_hw(hw, ctx_buf, tx_drbell_q_index);
1455 * ice_clear_tx_drbell_q_ctx
1456 * @hw: pointer to the hardware structure
1457 * @tx_drbell_q_index: the index of the doorbell queue to clear
1459 * Clears doorbell queue context in HW register space
1462 ice_clear_tx_drbell_q_ctx(struct ice_hw *hw, u32 tx_drbell_q_index)
1466 if (tx_drbell_q_index > QTX_COMM_DBLQ_DBELL_MAX_INDEX)
1467 return ICE_ERR_PARAM;
1469 /* Clear each dword register separately */
1470 for (i = 0; i < ICE_TX_DRBELL_Q_CTX_SIZE_DWORDS; i++)
1471 wr32(hw, QTX_COMM_DBLQ_CNTX(i, tx_drbell_q_index), 0);
1475 #endif /* !NO_UNUSED_CTX_CODE || AE_DRIVER */
1479 * @hw: pointer to the hardware structure
1481 * @desc: pointer to control queue descriptor
1482 * @buf: pointer to command buffer
1483 * @buf_len: max length of buf
1485 * Dumps debug log about control command with descriptor contents.
1488 ice_debug_cq(struct ice_hw *hw, u32 mask, void *desc, void *buf, u16 buf_len)
1490 struct ice_aq_desc *cq_desc = (struct ice_aq_desc *)desc;
1493 if (!(mask & hw->debug_mask))
1499 len = LE16_TO_CPU(cq_desc->datalen);
1502 "CQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
1503 LE16_TO_CPU(cq_desc->opcode),
1504 LE16_TO_CPU(cq_desc->flags),
1505 LE16_TO_CPU(cq_desc->datalen), LE16_TO_CPU(cq_desc->retval));
1506 ice_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n",
1507 LE32_TO_CPU(cq_desc->cookie_high),
1508 LE32_TO_CPU(cq_desc->cookie_low));
1509 ice_debug(hw, mask, "\tparam (0,1) 0x%08X 0x%08X\n",
1510 LE32_TO_CPU(cq_desc->params.generic.param0),
1511 LE32_TO_CPU(cq_desc->params.generic.param1));
1512 ice_debug(hw, mask, "\taddr (h,l) 0x%08X 0x%08X\n",
1513 LE32_TO_CPU(cq_desc->params.generic.addr_high),
1514 LE32_TO_CPU(cq_desc->params.generic.addr_low));
1515 if (buf && cq_desc->datalen != 0) {
1516 ice_debug(hw, mask, "Buffer:\n");
1520 ice_debug_array(hw, mask, 16, 1, (u8 *)buf, len);
1525 /* FW Admin Queue command wrappers */
1528 * ice_aq_send_cmd - send FW Admin Queue command to FW Admin Queue
1529 * @hw: pointer to the HW struct
1530 * @desc: descriptor describing the command
1531 * @buf: buffer to use for indirect commands (NULL for direct commands)
1532 * @buf_size: size of buffer for indirect commands (0 for direct commands)
1533 * @cd: pointer to command details structure
1535 * Helper function to send FW Admin Queue commands to the FW Admin Queue.
1538 ice_aq_send_cmd(struct ice_hw *hw, struct ice_aq_desc *desc, void *buf,
1539 u16 buf_size, struct ice_sq_cd *cd)
1541 return ice_sq_send_cmd(hw, &hw->adminq, desc, buf, buf_size, cd);
1546 * @hw: pointer to the HW struct
1547 * @cd: pointer to command details structure or NULL
1549 * Get the firmware version (0x0001) from the admin queue commands
1551 enum ice_status ice_aq_get_fw_ver(struct ice_hw *hw, struct ice_sq_cd *cd)
1553 struct ice_aqc_get_ver *resp;
1554 struct ice_aq_desc desc;
1555 enum ice_status status;
1557 resp = &desc.params.get_ver;
1559 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_ver);
1561 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
1564 hw->fw_branch = resp->fw_branch;
1565 hw->fw_maj_ver = resp->fw_major;
1566 hw->fw_min_ver = resp->fw_minor;
1567 hw->fw_patch = resp->fw_patch;
1568 hw->fw_build = LE32_TO_CPU(resp->fw_build);
1569 hw->api_branch = resp->api_branch;
1570 hw->api_maj_ver = resp->api_major;
1571 hw->api_min_ver = resp->api_minor;
1572 hw->api_patch = resp->api_patch;
1579 * ice_aq_send_driver_ver
1580 * @hw: pointer to the HW struct
1581 * @dv: driver's major, minor version
1582 * @cd: pointer to command details structure or NULL
1584 * Send the driver version (0x0002) to the firmware
1587 ice_aq_send_driver_ver(struct ice_hw *hw, struct ice_driver_ver *dv,
1588 struct ice_sq_cd *cd)
1590 struct ice_aqc_driver_ver *cmd;
1591 struct ice_aq_desc desc;
1594 cmd = &desc.params.driver_ver;
1597 return ICE_ERR_PARAM;
1599 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_driver_ver);
1601 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
1602 cmd->major_ver = dv->major_ver;
1603 cmd->minor_ver = dv->minor_ver;
1604 cmd->build_ver = dv->build_ver;
1605 cmd->subbuild_ver = dv->subbuild_ver;
1608 while (len < sizeof(dv->driver_string) &&
1609 IS_ASCII(dv->driver_string[len]) && dv->driver_string[len])
1612 return ice_aq_send_cmd(hw, &desc, dv->driver_string, len, cd);
1617 * @hw: pointer to the HW struct
1618 * @unloading: is the driver unloading itself
1620 * Tell the Firmware that we're shutting down the AdminQ and whether
1621 * or not the driver is unloading as well (0x0003).
1623 enum ice_status ice_aq_q_shutdown(struct ice_hw *hw, bool unloading)
1625 struct ice_aqc_q_shutdown *cmd;
1626 struct ice_aq_desc desc;
1628 cmd = &desc.params.q_shutdown;
1630 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_q_shutdown);
1633 cmd->driver_unloading = CPU_TO_LE32(ICE_AQC_DRIVER_UNLOADING);
1635 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
1640 * @hw: pointer to the HW struct
1642 * @access: access type
1643 * @sdp_number: resource number
1644 * @timeout: the maximum time in ms that the driver may hold the resource
1645 * @cd: pointer to command details structure or NULL
1647 * Requests common resource using the admin queue commands (0x0008).
1648 * When attempting to acquire the Global Config Lock, the driver can
1649 * learn of three states:
1650 * 1) ICE_SUCCESS - acquired lock, and can perform download package
1651 * 2) ICE_ERR_AQ_ERROR - did not get lock, driver should fail to load
1652 * 3) ICE_ERR_AQ_NO_WORK - did not get lock, but another driver has
1653 * successfully downloaded the package; the driver does
1654 * not have to download the package and can continue
1657 * Note that if the caller is in an acquire lock, perform action, release lock
1658 * phase of operation, it is possible that the FW may detect a timeout and issue
1659 * a CORER. In this case, the driver will receive a CORER interrupt and will
1660 * have to determine its cause. The calling thread that is handling this flow
1661 * will likely get an error propagated back to it indicating the Download
1662 * Package, Update Package or the Release Resource AQ commands timed out.
1664 static enum ice_status
1665 ice_aq_req_res(struct ice_hw *hw, enum ice_aq_res_ids res,
1666 enum ice_aq_res_access_type access, u8 sdp_number, u32 *timeout,
1667 struct ice_sq_cd *cd)
1669 struct ice_aqc_req_res *cmd_resp;
1670 struct ice_aq_desc desc;
1671 enum ice_status status;
1673 ice_debug(hw, ICE_DBG_TRACE, "ice_aq_req_res");
1675 cmd_resp = &desc.params.res_owner;
1677 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_req_res);
1679 cmd_resp->res_id = CPU_TO_LE16(res);
1680 cmd_resp->access_type = CPU_TO_LE16(access);
1681 cmd_resp->res_number = CPU_TO_LE32(sdp_number);
1682 cmd_resp->timeout = CPU_TO_LE32(*timeout);
1685 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
1687 /* The completion specifies the maximum time in ms that the driver
1688 * may hold the resource in the Timeout field.
1691 /* Global config lock response utilizes an additional status field.
1693 * If the Global config lock resource is held by some other driver, the
1694 * command completes with ICE_AQ_RES_GLBL_IN_PROG in the status field
1695 * and the timeout field indicates the maximum time the current owner
1696 * of the resource has to free it.
1698 if (res == ICE_GLOBAL_CFG_LOCK_RES_ID) {
1699 if (LE16_TO_CPU(cmd_resp->status) == ICE_AQ_RES_GLBL_SUCCESS) {
1700 *timeout = LE32_TO_CPU(cmd_resp->timeout);
1702 } else if (LE16_TO_CPU(cmd_resp->status) ==
1703 ICE_AQ_RES_GLBL_IN_PROG) {
1704 *timeout = LE32_TO_CPU(cmd_resp->timeout);
1705 return ICE_ERR_AQ_ERROR;
1706 } else if (LE16_TO_CPU(cmd_resp->status) ==
1707 ICE_AQ_RES_GLBL_DONE) {
1708 return ICE_ERR_AQ_NO_WORK;
1711 /* invalid FW response, force a timeout immediately */
1713 return ICE_ERR_AQ_ERROR;
1716 /* If the resource is held by some other driver, the command completes
1717 * with a busy return value and the timeout field indicates the maximum
1718 * time the current owner of the resource has to free it.
1720 if (!status || hw->adminq.sq_last_status == ICE_AQ_RC_EBUSY)
1721 *timeout = LE32_TO_CPU(cmd_resp->timeout);
1727 * ice_aq_release_res
1728 * @hw: pointer to the HW struct
1730 * @sdp_number: resource number
1731 * @cd: pointer to command details structure or NULL
1733 * release common resource using the admin queue commands (0x0009)
1735 static enum ice_status
1736 ice_aq_release_res(struct ice_hw *hw, enum ice_aq_res_ids res, u8 sdp_number,
1737 struct ice_sq_cd *cd)
1739 struct ice_aqc_req_res *cmd;
1740 struct ice_aq_desc desc;
1742 ice_debug(hw, ICE_DBG_TRACE, "ice_aq_release_res");
1744 cmd = &desc.params.res_owner;
1746 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_release_res);
1748 cmd->res_id = CPU_TO_LE16(res);
1749 cmd->res_number = CPU_TO_LE32(sdp_number);
1751 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
1756 * @hw: pointer to the HW structure
1758 * @access: access type (read or write)
1759 * @timeout: timeout in milliseconds
1761 * This function will attempt to acquire the ownership of a resource.
1764 ice_acquire_res(struct ice_hw *hw, enum ice_aq_res_ids res,
1765 enum ice_aq_res_access_type access, u32 timeout)
1767 #define ICE_RES_POLLING_DELAY_MS 10
1768 u32 delay = ICE_RES_POLLING_DELAY_MS;
1769 u32 time_left = timeout;
1770 enum ice_status status;
1772 ice_debug(hw, ICE_DBG_TRACE, "ice_acquire_res");
1774 status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL);
1776 /* A return code of ICE_ERR_AQ_NO_WORK means that another driver has
1777 * previously acquired the resource and performed any necessary updates;
1778 * in this case the caller does not obtain the resource and has no
1779 * further work to do.
1781 if (status == ICE_ERR_AQ_NO_WORK)
1782 goto ice_acquire_res_exit;
1785 ice_debug(hw, ICE_DBG_RES,
1786 "resource %d acquire type %d failed.\n", res, access);
1788 /* If necessary, poll until the current lock owner timeouts */
1789 timeout = time_left;
1790 while (status && timeout && time_left) {
1791 ice_msec_delay(delay, true);
1792 timeout = (timeout > delay) ? timeout - delay : 0;
1793 status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL);
1795 if (status == ICE_ERR_AQ_NO_WORK)
1796 /* lock free, but no work to do */
1803 if (status && status != ICE_ERR_AQ_NO_WORK)
1804 ice_debug(hw, ICE_DBG_RES, "resource acquire timed out.\n");
1806 ice_acquire_res_exit:
1807 if (status == ICE_ERR_AQ_NO_WORK) {
1808 if (access == ICE_RES_WRITE)
1809 ice_debug(hw, ICE_DBG_RES,
1810 "resource indicates no work to do.\n");
1812 ice_debug(hw, ICE_DBG_RES,
1813 "Warning: ICE_ERR_AQ_NO_WORK not expected\n");
1820 * @hw: pointer to the HW structure
1823 * This function will release a resource using the proper Admin Command.
1825 void ice_release_res(struct ice_hw *hw, enum ice_aq_res_ids res)
1827 enum ice_status status;
1828 u32 total_delay = 0;
1830 ice_debug(hw, ICE_DBG_TRACE, "ice_release_res");
1832 status = ice_aq_release_res(hw, res, 0, NULL);
1834 /* there are some rare cases when trying to release the resource
1835 * results in an admin queue timeout, so handle them correctly
1837 while ((status == ICE_ERR_AQ_TIMEOUT) &&
1838 (total_delay < hw->adminq.sq_cmd_timeout)) {
1839 ice_msec_delay(1, true);
1840 status = ice_aq_release_res(hw, res, 0, NULL);
1846 * ice_aq_alloc_free_res - command to allocate/free resources
1847 * @hw: pointer to the HW struct
1848 * @num_entries: number of resource entries in buffer
1849 * @buf: Indirect buffer to hold data parameters and response
1850 * @buf_size: size of buffer for indirect commands
1851 * @opc: pass in the command opcode
1852 * @cd: pointer to command details structure or NULL
1854 * Helper function to allocate/free resources using the admin queue commands
1857 ice_aq_alloc_free_res(struct ice_hw *hw, u16 num_entries,
1858 struct ice_aqc_alloc_free_res_elem *buf, u16 buf_size,
1859 enum ice_adminq_opc opc, struct ice_sq_cd *cd)
1861 struct ice_aqc_alloc_free_res_cmd *cmd;
1862 struct ice_aq_desc desc;
1864 ice_debug(hw, ICE_DBG_TRACE, "ice_aq_alloc_free_res");
1866 cmd = &desc.params.sw_res_ctrl;
1869 return ICE_ERR_PARAM;
1871 if (buf_size < (num_entries * sizeof(buf->elem[0])))
1872 return ICE_ERR_PARAM;
1874 ice_fill_dflt_direct_cmd_desc(&desc, opc);
1876 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
1878 cmd->num_entries = CPU_TO_LE16(num_entries);
1880 return ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);
1884 * ice_alloc_hw_res - allocate resource
1885 * @hw: pointer to the HW struct
1886 * @type: type of resource
1887 * @num: number of resources to allocate
1888 * @btm: allocate from bottom
1889 * @res: pointer to array that will receive the resources
1892 ice_alloc_hw_res(struct ice_hw *hw, u16 type, u16 num, bool btm, u16 *res)
1894 struct ice_aqc_alloc_free_res_elem *buf;
1895 enum ice_status status;
1898 buf_len = sizeof(*buf) + sizeof(buf->elem) * (num - 1);
1899 buf = (struct ice_aqc_alloc_free_res_elem *)
1900 ice_malloc(hw, buf_len);
1902 return ICE_ERR_NO_MEMORY;
1904 /* Prepare buffer to allocate resource. */
1905 buf->num_elems = CPU_TO_LE16(num);
1906 buf->res_type = CPU_TO_LE16(type | ICE_AQC_RES_TYPE_FLAG_DEDICATED |
1907 ICE_AQC_RES_TYPE_FLAG_IGNORE_INDEX);
1909 buf->res_type |= CPU_TO_LE16(ICE_AQC_RES_TYPE_FLAG_SCAN_BOTTOM);
1911 status = ice_aq_alloc_free_res(hw, 1, buf, buf_len,
1912 ice_aqc_opc_alloc_res, NULL);
1914 goto ice_alloc_res_exit;
1916 ice_memcpy(res, buf->elem, sizeof(buf->elem) * num,
1917 ICE_NONDMA_TO_NONDMA);
1925 * ice_free_hw_res - free allocated HW resource
1926 * @hw: pointer to the HW struct
1927 * @type: type of resource to free
1928 * @num: number of resources
1929 * @res: pointer to array that contains the resources to free
1932 ice_free_hw_res(struct ice_hw *hw, u16 type, u16 num, u16 *res)
1934 struct ice_aqc_alloc_free_res_elem *buf;
1935 enum ice_status status;
1938 buf_len = sizeof(*buf) + sizeof(buf->elem) * (num - 1);
1939 buf = (struct ice_aqc_alloc_free_res_elem *)ice_malloc(hw, buf_len);
1941 return ICE_ERR_NO_MEMORY;
1943 /* Prepare buffer to free resource. */
1944 buf->num_elems = CPU_TO_LE16(num);
1945 buf->res_type = CPU_TO_LE16(type);
1946 ice_memcpy(buf->elem, res, sizeof(buf->elem) * num,
1947 ICE_NONDMA_TO_NONDMA);
1949 status = ice_aq_alloc_free_res(hw, num, buf, buf_len,
1950 ice_aqc_opc_free_res, NULL);
1952 ice_debug(hw, ICE_DBG_SW, "CQ CMD Buffer:\n");
1959 * ice_get_num_per_func - determine number of resources per PF
1960 * @hw: pointer to the HW structure
1961 * @max: value to be evenly split between each PF
1963 * Determine the number of valid functions by going through the bitmap returned
1964 * from parsing capabilities and use this to calculate the number of resources
1965 * per PF based on the max value passed in.
1967 static u32 ice_get_num_per_func(struct ice_hw *hw, u32 max)
1971 #define ICE_CAPS_VALID_FUNCS_M 0xFF
1972 funcs = ice_hweight8(hw->dev_caps.common_cap.valid_functions &
1973 ICE_CAPS_VALID_FUNCS_M);
1982 * ice_parse_caps - parse function/device capabilities
1983 * @hw: pointer to the HW struct
1984 * @buf: pointer to a buffer containing function/device capability records
1985 * @cap_count: number of capability records in the list
1986 * @opc: type of capabilities list to parse
1988 * Helper function to parse function(0x000a)/device(0x000b) capabilities list.
1991 ice_parse_caps(struct ice_hw *hw, void *buf, u32 cap_count,
1992 enum ice_adminq_opc opc)
1994 struct ice_aqc_list_caps_elem *cap_resp;
1995 struct ice_hw_func_caps *func_p = NULL;
1996 struct ice_hw_dev_caps *dev_p = NULL;
1997 struct ice_hw_common_caps *caps;
2003 cap_resp = (struct ice_aqc_list_caps_elem *)buf;
2005 if (opc == ice_aqc_opc_list_dev_caps) {
2006 dev_p = &hw->dev_caps;
2007 caps = &dev_p->common_cap;
2008 } else if (opc == ice_aqc_opc_list_func_caps) {
2009 func_p = &hw->func_caps;
2010 caps = &func_p->common_cap;
2012 ice_debug(hw, ICE_DBG_INIT, "wrong opcode\n");
2016 for (i = 0; caps && i < cap_count; i++, cap_resp++) {
2017 u32 logical_id = LE32_TO_CPU(cap_resp->logical_id);
2018 u32 phys_id = LE32_TO_CPU(cap_resp->phys_id);
2019 u32 number = LE32_TO_CPU(cap_resp->number);
2020 u16 cap = LE16_TO_CPU(cap_resp->cap);
2023 case ICE_AQC_CAPS_VALID_FUNCTIONS:
2024 caps->valid_functions = number;
2025 ice_debug(hw, ICE_DBG_INIT,
2026 "HW caps: Valid Functions = %d\n",
2027 caps->valid_functions);
2029 case ICE_AQC_CAPS_VSI:
2031 dev_p->num_vsi_allocd_to_host = number;
2032 ice_debug(hw, ICE_DBG_INIT,
2033 "HW caps: Dev.VSI cnt = %d\n",
2034 dev_p->num_vsi_allocd_to_host);
2035 } else if (func_p) {
2036 func_p->guar_num_vsi =
2037 ice_get_num_per_func(hw, ICE_MAX_VSI);
2038 ice_debug(hw, ICE_DBG_INIT,
2039 "HW caps: Func.VSI cnt = %d\n",
2043 case ICE_AQC_CAPS_DCB:
2044 caps->dcb = (number == 1);
2045 caps->active_tc_bitmap = logical_id;
2046 caps->maxtc = phys_id;
2047 ice_debug(hw, ICE_DBG_INIT,
2048 "HW caps: DCB = %d\n", caps->dcb);
2049 ice_debug(hw, ICE_DBG_INIT,
2050 "HW caps: Active TC bitmap = %d\n",
2051 caps->active_tc_bitmap);
2052 ice_debug(hw, ICE_DBG_INIT,
2053 "HW caps: TC Max = %d\n", caps->maxtc);
2055 case ICE_AQC_CAPS_RSS:
2056 caps->rss_table_size = number;
2057 caps->rss_table_entry_width = logical_id;
2058 ice_debug(hw, ICE_DBG_INIT,
2059 "HW caps: RSS table size = %d\n",
2060 caps->rss_table_size);
2061 ice_debug(hw, ICE_DBG_INIT,
2062 "HW caps: RSS table width = %d\n",
2063 caps->rss_table_entry_width);
2065 case ICE_AQC_CAPS_RXQS:
2066 caps->num_rxq = number;
2067 caps->rxq_first_id = phys_id;
2068 ice_debug(hw, ICE_DBG_INIT,
2069 "HW caps: Num Rx Qs = %d\n", caps->num_rxq);
2070 ice_debug(hw, ICE_DBG_INIT,
2071 "HW caps: Rx first queue ID = %d\n",
2072 caps->rxq_first_id);
2074 case ICE_AQC_CAPS_TXQS:
2075 caps->num_txq = number;
2076 caps->txq_first_id = phys_id;
2077 ice_debug(hw, ICE_DBG_INIT,
2078 "HW caps: Num Tx Qs = %d\n", caps->num_txq);
2079 ice_debug(hw, ICE_DBG_INIT,
2080 "HW caps: Tx first queue ID = %d\n",
2081 caps->txq_first_id);
2083 case ICE_AQC_CAPS_MSIX:
2084 caps->num_msix_vectors = number;
2085 caps->msix_vector_first_id = phys_id;
2086 ice_debug(hw, ICE_DBG_INIT,
2087 "HW caps: MSIX vector count = %d\n",
2088 caps->num_msix_vectors);
2089 ice_debug(hw, ICE_DBG_INIT,
2090 "HW caps: MSIX first vector index = %d\n",
2091 caps->msix_vector_first_id);
2093 case ICE_AQC_CAPS_FD:
2098 dev_p->num_flow_director_fltr = number;
2099 ice_debug(hw, ICE_DBG_INIT,
2100 "HW caps: Dev.fd_fltr =%d\n",
2101 dev_p->num_flow_director_fltr);
2104 reg_val = rd32(hw, GLQF_FD_SIZE);
2105 val = (reg_val & GLQF_FD_SIZE_FD_GSIZE_M) >>
2106 GLQF_FD_SIZE_FD_GSIZE_S;
2107 func_p->fd_fltr_guar =
2108 ice_get_num_per_func(hw, val);
2109 val = (reg_val & GLQF_FD_SIZE_FD_BSIZE_M) >>
2110 GLQF_FD_SIZE_FD_BSIZE_S;
2111 func_p->fd_fltr_best_effort = val;
2112 ice_debug(hw, ICE_DBG_INIT,
2113 "HW:func.fd_fltr guar= %d\n",
2114 func_p->fd_fltr_guar);
2115 ice_debug(hw, ICE_DBG_INIT,
2116 "HW:func.fd_fltr best effort=%d\n",
2117 func_p->fd_fltr_best_effort);
2121 case ICE_AQC_CAPS_MAX_MTU:
2122 caps->max_mtu = number;
2124 ice_debug(hw, ICE_DBG_INIT,
2125 "HW caps: Dev.MaxMTU = %d\n",
2128 ice_debug(hw, ICE_DBG_INIT,
2129 "HW caps: func.MaxMTU = %d\n",
2133 ice_debug(hw, ICE_DBG_INIT,
2134 "HW caps: Unknown capability[%d]: 0x%x\n", i,
2142 * ice_aq_discover_caps - query function/device capabilities
2143 * @hw: pointer to the HW struct
2144 * @buf: a virtual buffer to hold the capabilities
2145 * @buf_size: Size of the virtual buffer
2146 * @cap_count: cap count needed if AQ err==ENOMEM
2147 * @opc: capabilities type to discover - pass in the command opcode
2148 * @cd: pointer to command details structure or NULL
2150 * Get the function(0x000a)/device(0x000b) capabilities description from
2153 static enum ice_status
2154 ice_aq_discover_caps(struct ice_hw *hw, void *buf, u16 buf_size, u32 *cap_count,
2155 enum ice_adminq_opc opc, struct ice_sq_cd *cd)
2157 struct ice_aqc_list_caps *cmd;
2158 struct ice_aq_desc desc;
2159 enum ice_status status;
2161 cmd = &desc.params.get_cap;
2163 if (opc != ice_aqc_opc_list_func_caps &&
2164 opc != ice_aqc_opc_list_dev_caps)
2165 return ICE_ERR_PARAM;
2167 ice_fill_dflt_direct_cmd_desc(&desc, opc);
2169 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);
2171 ice_parse_caps(hw, buf, LE32_TO_CPU(cmd->count), opc);
2172 else if (hw->adminq.sq_last_status == ICE_AQ_RC_ENOMEM)
2173 *cap_count = LE32_TO_CPU(cmd->count);
2178 * ice_discover_caps - get info about the HW
2179 * @hw: pointer to the hardware structure
2180 * @opc: capabilities type to discover - pass in the command opcode
2182 static enum ice_status
2183 ice_discover_caps(struct ice_hw *hw, enum ice_adminq_opc opc)
2185 enum ice_status status;
2190 /* The driver doesn't know how many capabilities the device will return
2191 * so the buffer size required isn't known ahead of time. The driver
2192 * starts with cbuf_len and if this turns out to be insufficient, the
2193 * device returns ICE_AQ_RC_ENOMEM and also the cap_count it needs.
2194 * The driver then allocates the buffer based on the count and retries
2195 * the operation. So it follows that the retry count is 2.
2197 #define ICE_GET_CAP_BUF_COUNT 40
2198 #define ICE_GET_CAP_RETRY_COUNT 2
2200 cap_count = ICE_GET_CAP_BUF_COUNT;
2201 retries = ICE_GET_CAP_RETRY_COUNT;
2206 cbuf_len = (u16)(cap_count *
2207 sizeof(struct ice_aqc_list_caps_elem));
2208 cbuf = ice_malloc(hw, cbuf_len);
2210 return ICE_ERR_NO_MEMORY;
2212 status = ice_aq_discover_caps(hw, cbuf, cbuf_len, &cap_count,
2216 if (!status || hw->adminq.sq_last_status != ICE_AQ_RC_ENOMEM)
2219 /* If ENOMEM is returned, try again with bigger buffer */
2220 } while (--retries);
2226 * ice_get_caps - get info about the HW
2227 * @hw: pointer to the hardware structure
2229 enum ice_status ice_get_caps(struct ice_hw *hw)
2231 enum ice_status status;
2233 status = ice_discover_caps(hw, ice_aqc_opc_list_dev_caps);
2235 status = ice_discover_caps(hw, ice_aqc_opc_list_func_caps);
2241 * ice_aq_manage_mac_write - manage MAC address write command
2242 * @hw: pointer to the HW struct
2243 * @mac_addr: MAC address to be written as LAA/LAA+WoL/Port address
2244 * @flags: flags to control write behavior
2245 * @cd: pointer to command details structure or NULL
2247 * This function is used to write MAC address to the NVM (0x0108).
2250 ice_aq_manage_mac_write(struct ice_hw *hw, const u8 *mac_addr, u8 flags,
2251 struct ice_sq_cd *cd)
2253 struct ice_aqc_manage_mac_write *cmd;
2254 struct ice_aq_desc desc;
2256 cmd = &desc.params.mac_write;
2257 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_write);
2262 /* Prep values for flags, sah, sal */
2263 cmd->sah = HTONS(*((const u16 *)mac_addr));
2264 cmd->sal = HTONL(*((const u32 *)(mac_addr + 2)));
2266 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
2270 * ice_aq_clear_pxe_mode
2271 * @hw: pointer to the HW struct
2273 * Tell the firmware that the driver is taking over from PXE (0x0110).
2275 static enum ice_status ice_aq_clear_pxe_mode(struct ice_hw *hw)
2277 struct ice_aq_desc desc;
2279 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pxe_mode);
2280 desc.params.clear_pxe.rx_cnt = ICE_AQC_CLEAR_PXE_RX_CNT;
2282 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
2286 * ice_clear_pxe_mode - clear pxe operations mode
2287 * @hw: pointer to the HW struct
2289 * Make sure all PXE mode settings are cleared, including things
2290 * like descriptor fetch/write-back mode.
2292 void ice_clear_pxe_mode(struct ice_hw *hw)
2294 if (ice_check_sq_alive(hw, &hw->adminq))
2295 ice_aq_clear_pxe_mode(hw);
2300 * ice_get_link_speed_based_on_phy_type - returns link speed
2301 * @phy_type_low: lower part of phy_type
2302 * @phy_type_high: higher part of phy_type
2304 * This helper function will convert an entry in PHY type structure
2305 * [phy_type_low, phy_type_high] to its corresponding link speed.
2306 * Note: In the structure of [phy_type_low, phy_type_high], there should
2307 * be one bit set, as this function will convert one PHY type to its
2309 * If no bit gets set, ICE_LINK_SPEED_UNKNOWN will be returned
2310 * If more than one bit gets set, ICE_LINK_SPEED_UNKNOWN will be returned
2313 ice_get_link_speed_based_on_phy_type(u64 phy_type_low, u64 phy_type_high)
2315 u16 speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN;
2316 u16 speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN;
2318 switch (phy_type_low) {
2319 case ICE_PHY_TYPE_LOW_100BASE_TX:
2320 case ICE_PHY_TYPE_LOW_100M_SGMII:
2321 speed_phy_type_low = ICE_AQ_LINK_SPEED_100MB;
2323 case ICE_PHY_TYPE_LOW_1000BASE_T:
2324 case ICE_PHY_TYPE_LOW_1000BASE_SX:
2325 case ICE_PHY_TYPE_LOW_1000BASE_LX:
2326 case ICE_PHY_TYPE_LOW_1000BASE_KX:
2327 case ICE_PHY_TYPE_LOW_1G_SGMII:
2328 speed_phy_type_low = ICE_AQ_LINK_SPEED_1000MB;
2330 case ICE_PHY_TYPE_LOW_2500BASE_T:
2331 case ICE_PHY_TYPE_LOW_2500BASE_X:
2332 case ICE_PHY_TYPE_LOW_2500BASE_KX:
2333 speed_phy_type_low = ICE_AQ_LINK_SPEED_2500MB;
2335 case ICE_PHY_TYPE_LOW_5GBASE_T:
2336 case ICE_PHY_TYPE_LOW_5GBASE_KR:
2337 speed_phy_type_low = ICE_AQ_LINK_SPEED_5GB;
2339 case ICE_PHY_TYPE_LOW_10GBASE_T:
2340 case ICE_PHY_TYPE_LOW_10G_SFI_DA:
2341 case ICE_PHY_TYPE_LOW_10GBASE_SR:
2342 case ICE_PHY_TYPE_LOW_10GBASE_LR:
2343 case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1:
2344 case ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC:
2345 case ICE_PHY_TYPE_LOW_10G_SFI_C2C:
2346 speed_phy_type_low = ICE_AQ_LINK_SPEED_10GB;
2348 case ICE_PHY_TYPE_LOW_25GBASE_T:
2349 case ICE_PHY_TYPE_LOW_25GBASE_CR:
2350 case ICE_PHY_TYPE_LOW_25GBASE_CR_S:
2351 case ICE_PHY_TYPE_LOW_25GBASE_CR1:
2352 case ICE_PHY_TYPE_LOW_25GBASE_SR:
2353 case ICE_PHY_TYPE_LOW_25GBASE_LR:
2354 case ICE_PHY_TYPE_LOW_25GBASE_KR:
2355 case ICE_PHY_TYPE_LOW_25GBASE_KR_S:
2356 case ICE_PHY_TYPE_LOW_25GBASE_KR1:
2357 case ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC:
2358 case ICE_PHY_TYPE_LOW_25G_AUI_C2C:
2359 speed_phy_type_low = ICE_AQ_LINK_SPEED_25GB;
2361 case ICE_PHY_TYPE_LOW_40GBASE_CR4:
2362 case ICE_PHY_TYPE_LOW_40GBASE_SR4:
2363 case ICE_PHY_TYPE_LOW_40GBASE_LR4:
2364 case ICE_PHY_TYPE_LOW_40GBASE_KR4:
2365 case ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC:
2366 case ICE_PHY_TYPE_LOW_40G_XLAUI:
2367 speed_phy_type_low = ICE_AQ_LINK_SPEED_40GB;
2369 case ICE_PHY_TYPE_LOW_50GBASE_CR2:
2370 case ICE_PHY_TYPE_LOW_50GBASE_SR2:
2371 case ICE_PHY_TYPE_LOW_50GBASE_LR2:
2372 case ICE_PHY_TYPE_LOW_50GBASE_KR2:
2373 case ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC:
2374 case ICE_PHY_TYPE_LOW_50G_LAUI2:
2375 case ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC:
2376 case ICE_PHY_TYPE_LOW_50G_AUI2:
2377 case ICE_PHY_TYPE_LOW_50GBASE_CP:
2378 case ICE_PHY_TYPE_LOW_50GBASE_SR:
2379 case ICE_PHY_TYPE_LOW_50GBASE_FR:
2380 case ICE_PHY_TYPE_LOW_50GBASE_LR:
2381 case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4:
2382 case ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC:
2383 case ICE_PHY_TYPE_LOW_50G_AUI1:
2384 speed_phy_type_low = ICE_AQ_LINK_SPEED_50GB;
2386 case ICE_PHY_TYPE_LOW_100GBASE_CR4:
2387 case ICE_PHY_TYPE_LOW_100GBASE_SR4:
2388 case ICE_PHY_TYPE_LOW_100GBASE_LR4:
2389 case ICE_PHY_TYPE_LOW_100GBASE_KR4:
2390 case ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC:
2391 case ICE_PHY_TYPE_LOW_100G_CAUI4:
2392 case ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC:
2393 case ICE_PHY_TYPE_LOW_100G_AUI4:
2394 case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4:
2395 case ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4:
2396 case ICE_PHY_TYPE_LOW_100GBASE_CP2:
2397 case ICE_PHY_TYPE_LOW_100GBASE_SR2:
2398 case ICE_PHY_TYPE_LOW_100GBASE_DR:
2399 speed_phy_type_low = ICE_AQ_LINK_SPEED_100GB;
2402 speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN;
2406 switch (phy_type_high) {
2407 case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4:
2408 case ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC:
2409 case ICE_PHY_TYPE_HIGH_100G_CAUI2:
2410 case ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC:
2411 case ICE_PHY_TYPE_HIGH_100G_AUI2:
2412 speed_phy_type_high = ICE_AQ_LINK_SPEED_100GB;
2415 speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN;
2419 if (speed_phy_type_low == ICE_AQ_LINK_SPEED_UNKNOWN &&
2420 speed_phy_type_high == ICE_AQ_LINK_SPEED_UNKNOWN)
2421 return ICE_AQ_LINK_SPEED_UNKNOWN;
2422 else if (speed_phy_type_low != ICE_AQ_LINK_SPEED_UNKNOWN &&
2423 speed_phy_type_high != ICE_AQ_LINK_SPEED_UNKNOWN)
2424 return ICE_AQ_LINK_SPEED_UNKNOWN;
2425 else if (speed_phy_type_low != ICE_AQ_LINK_SPEED_UNKNOWN &&
2426 speed_phy_type_high == ICE_AQ_LINK_SPEED_UNKNOWN)
2427 return speed_phy_type_low;
2429 return speed_phy_type_high;
2433 * ice_update_phy_type
2434 * @phy_type_low: pointer to the lower part of phy_type
2435 * @phy_type_high: pointer to the higher part of phy_type
2436 * @link_speeds_bitmap: targeted link speeds bitmap
2438 * Note: For the link_speeds_bitmap structure, you can check it at
2439 * [ice_aqc_get_link_status->link_speed]. Caller can pass in
2440 * link_speeds_bitmap include multiple speeds.
2442 * Each entry in this [phy_type_low, phy_type_high] structure will
2443 * present a certain link speed. This helper function will turn on bits
2444 * in [phy_type_low, phy_type_high] structure based on the value of
2445 * link_speeds_bitmap input parameter.
2448 ice_update_phy_type(u64 *phy_type_low, u64 *phy_type_high,
2449 u16 link_speeds_bitmap)
2451 u16 speed = ICE_AQ_LINK_SPEED_UNKNOWN;
2456 /* We first check with low part of phy_type */
2457 for (index = 0; index <= ICE_PHY_TYPE_LOW_MAX_INDEX; index++) {
2458 pt_low = BIT_ULL(index);
2459 speed = ice_get_link_speed_based_on_phy_type(pt_low, 0);
2461 if (link_speeds_bitmap & speed)
2462 *phy_type_low |= BIT_ULL(index);
2465 /* We then check with high part of phy_type */
2466 for (index = 0; index <= ICE_PHY_TYPE_HIGH_MAX_INDEX; index++) {
2467 pt_high = BIT_ULL(index);
2468 speed = ice_get_link_speed_based_on_phy_type(0, pt_high);
2470 if (link_speeds_bitmap & speed)
2471 *phy_type_high |= BIT_ULL(index);
2476 * ice_aq_set_phy_cfg
2477 * @hw: pointer to the HW struct
2478 * @pi: port info structure of the interested logical port
2479 * @cfg: structure with PHY configuration data to be set
2480 * @cd: pointer to command details structure or NULL
2482 * Set the various PHY configuration parameters supported on the Port.
2483 * One or more of the Set PHY config parameters may be ignored in an MFP
2484 * mode as the PF may not have the privilege to set some of the PHY Config
2485 * parameters. This status will be indicated by the command response (0x0601).
2488 ice_aq_set_phy_cfg(struct ice_hw *hw, struct ice_port_info *pi,
2489 struct ice_aqc_set_phy_cfg_data *cfg, struct ice_sq_cd *cd)
2491 struct ice_aq_desc desc;
2492 enum ice_status status;
2495 return ICE_ERR_PARAM;
2497 /* Ensure that only valid bits of cfg->caps can be turned on. */
2498 if (cfg->caps & ~ICE_AQ_PHY_ENA_VALID_MASK) {
2499 ice_debug(hw, ICE_DBG_PHY,
2500 "Invalid bit is set in ice_aqc_set_phy_cfg_data->caps : 0x%x\n",
2503 cfg->caps &= ICE_AQ_PHY_ENA_VALID_MASK;
2506 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_phy_cfg);
2507 desc.params.set_phy.lport_num = pi->lport;
2508 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
2510 ice_debug(hw, ICE_DBG_LINK, "phy_type_low = 0x%llx\n",
2511 (unsigned long long)LE64_TO_CPU(cfg->phy_type_low));
2512 ice_debug(hw, ICE_DBG_LINK, "phy_type_high = 0x%llx\n",
2513 (unsigned long long)LE64_TO_CPU(cfg->phy_type_high));
2514 ice_debug(hw, ICE_DBG_LINK, "caps = 0x%x\n", cfg->caps);
2515 ice_debug(hw, ICE_DBG_LINK, "low_power_ctrl = 0x%x\n",
2516 cfg->low_power_ctrl);
2517 ice_debug(hw, ICE_DBG_LINK, "eee_cap = 0x%x\n", cfg->eee_cap);
2518 ice_debug(hw, ICE_DBG_LINK, "eeer_value = 0x%x\n", cfg->eeer_value);
2519 ice_debug(hw, ICE_DBG_LINK, "link_fec_opt = 0x%x\n", cfg->link_fec_opt);
2521 status = ice_aq_send_cmd(hw, &desc, cfg, sizeof(*cfg), cd);
2524 pi->phy.curr_user_phy_cfg = *cfg;
2530 * ice_update_link_info - update status of the HW network link
2531 * @pi: port info structure of the interested logical port
2533 enum ice_status ice_update_link_info(struct ice_port_info *pi)
2535 struct ice_aqc_get_phy_caps_data *pcaps;
2536 struct ice_phy_info *phy_info;
2537 enum ice_status status;
2541 return ICE_ERR_PARAM;
2545 pcaps = (struct ice_aqc_get_phy_caps_data *)
2546 ice_malloc(hw, sizeof(*pcaps));
2548 return ICE_ERR_NO_MEMORY;
2550 phy_info = &pi->phy;
2551 status = ice_aq_get_link_info(pi, true, NULL, NULL);
2555 if (phy_info->link_info.link_info & ICE_AQ_MEDIA_AVAILABLE) {
2556 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_SW_CFG,
2561 ice_memcpy(phy_info->link_info.module_type, &pcaps->module_type,
2562 sizeof(phy_info->link_info.module_type),
2563 ICE_NONDMA_TO_NONDMA);
2566 ice_free(hw, pcaps);
2571 * ice_cache_phy_user_req
2572 * @pi: port information structure
2573 * @cache_data: PHY logging data
2574 * @cache_mode: PHY logging mode
2576 * Log the user request on (FC, FEC, SPEED) for later user.
2579 ice_cache_phy_user_req(struct ice_port_info *pi,
2580 struct ice_phy_cache_mode_data cache_data,
2581 enum ice_phy_cache_mode cache_mode)
2586 switch (cache_mode) {
2588 pi->phy.curr_user_fc_req = cache_data.data.curr_user_fc_req;
2590 case ICE_SPEED_MODE:
2591 pi->phy.curr_user_speed_req =
2592 cache_data.data.curr_user_speed_req;
2595 pi->phy.curr_user_fec_req = cache_data.data.curr_user_fec_req;
2604 * @pi: port information structure
2605 * @aq_failures: pointer to status code, specific to ice_set_fc routine
2606 * @ena_auto_link_update: enable automatic link update
2608 * Set the requested flow control mode.
2611 ice_set_fc(struct ice_port_info *pi, u8 *aq_failures, bool ena_auto_link_update)
2613 struct ice_aqc_set_phy_cfg_data cfg = { 0 };
2614 struct ice_phy_cache_mode_data cache_data;
2615 struct ice_aqc_get_phy_caps_data *pcaps;
2616 enum ice_status status;
2617 u8 pause_mask = 0x0;
2621 return ICE_ERR_PARAM;
2623 *aq_failures = ICE_SET_FC_AQ_FAIL_NONE;
2625 /* Cache user FC request */
2626 cache_data.data.curr_user_fc_req = pi->fc.req_mode;
2627 ice_cache_phy_user_req(pi, cache_data, ICE_FC_MODE);
2629 switch (pi->fc.req_mode) {
2631 pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE;
2632 pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE;
2634 case ICE_FC_RX_PAUSE:
2635 pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE;
2637 case ICE_FC_TX_PAUSE:
2638 pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE;
2644 pcaps = (struct ice_aqc_get_phy_caps_data *)
2645 ice_malloc(hw, sizeof(*pcaps));
2647 return ICE_ERR_NO_MEMORY;
2649 /* Get the current PHY config */
2650 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_SW_CFG, pcaps,
2653 *aq_failures = ICE_SET_FC_AQ_FAIL_GET;
2657 /* clear the old pause settings */
2658 cfg.caps = pcaps->caps & ~(ICE_AQC_PHY_EN_TX_LINK_PAUSE |
2659 ICE_AQC_PHY_EN_RX_LINK_PAUSE);
2661 /* set the new capabilities */
2662 cfg.caps |= pause_mask;
2664 /* If the capabilities have changed, then set the new config */
2665 if (cfg.caps != pcaps->caps) {
2666 int retry_count, retry_max = 10;
2668 /* Auto restart link so settings take effect */
2669 if (ena_auto_link_update)
2670 cfg.caps |= ICE_AQ_PHY_ENA_AUTO_LINK_UPDT;
2671 /* Copy over all the old settings */
2672 cfg.phy_type_high = pcaps->phy_type_high;
2673 cfg.phy_type_low = pcaps->phy_type_low;
2674 cfg.low_power_ctrl = pcaps->low_power_ctrl;
2675 cfg.eee_cap = pcaps->eee_cap;
2676 cfg.eeer_value = pcaps->eeer_value;
2677 cfg.link_fec_opt = pcaps->link_fec_options;
2679 status = ice_aq_set_phy_cfg(hw, pi, &cfg, NULL);
2681 *aq_failures = ICE_SET_FC_AQ_FAIL_SET;
2685 /* Update the link info
2686 * It sometimes takes a really long time for link to
2687 * come back from the atomic reset. Thus, we wait a
2690 for (retry_count = 0; retry_count < retry_max; retry_count++) {
2691 status = ice_update_link_info(pi);
2693 if (status == ICE_SUCCESS)
2696 ice_msec_delay(100, true);
2700 *aq_failures = ICE_SET_FC_AQ_FAIL_UPDATE;
2704 ice_free(hw, pcaps);
2709 * ice_copy_phy_caps_to_cfg - Copy PHY ability data to configuration data
2710 * @caps: PHY ability structure to copy date from
2711 * @cfg: PHY configuration structure to copy data to
2713 * Helper function to copy AQC PHY get ability data to PHY set configuration
2717 ice_copy_phy_caps_to_cfg(struct ice_aqc_get_phy_caps_data *caps,
2718 struct ice_aqc_set_phy_cfg_data *cfg)
2723 cfg->phy_type_low = caps->phy_type_low;
2724 cfg->phy_type_high = caps->phy_type_high;
2725 cfg->caps = caps->caps;
2726 cfg->low_power_ctrl = caps->low_power_ctrl;
2727 cfg->eee_cap = caps->eee_cap;
2728 cfg->eeer_value = caps->eeer_value;
2729 cfg->link_fec_opt = caps->link_fec_options;
2733 * ice_cfg_phy_fec - Configure PHY FEC data based on FEC mode
2734 * @cfg: PHY configuration data to set FEC mode
2735 * @fec: FEC mode to configure
2737 * Caller should copy ice_aqc_get_phy_caps_data.caps ICE_AQC_PHY_EN_AUTO_FEC
2738 * (bit 7) and ice_aqc_get_phy_caps_data.link_fec_options to cfg.caps
2739 * ICE_AQ_PHY_ENA_AUTO_FEC (bit 7) and cfg.link_fec_options before calling.
2742 ice_cfg_phy_fec(struct ice_aqc_set_phy_cfg_data *cfg, enum ice_fec_mode fec)
2746 /* Clear auto FEC and RS bits, and AND BASE-R ability
2747 * bits and OR request bits.
2749 cfg->caps &= ~ICE_AQC_PHY_EN_AUTO_FEC;
2750 cfg->link_fec_opt &= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN |
2751 ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN;
2752 cfg->link_fec_opt |= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ |
2753 ICE_AQC_PHY_FEC_25G_KR_REQ;
2756 /* Clear auto FEC and BASE-R bits, and AND RS ability
2757 * bits and OR request bits.
2759 cfg->caps &= ~ICE_AQC_PHY_EN_AUTO_FEC;
2760 cfg->link_fec_opt &= ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN;
2761 cfg->link_fec_opt |= ICE_AQC_PHY_FEC_25G_RS_528_REQ |
2762 ICE_AQC_PHY_FEC_25G_RS_544_REQ;
2765 /* Clear auto FEC and all FEC option bits. */
2766 cfg->caps &= ~ICE_AQC_PHY_EN_AUTO_FEC;
2767 cfg->link_fec_opt &= ~ICE_AQC_PHY_FEC_MASK;
2770 /* AND auto FEC bit, and all caps bits. */
2771 cfg->caps &= ICE_AQC_PHY_CAPS_MASK;
2777 * ice_get_link_status - get status of the HW network link
2778 * @pi: port information structure
2779 * @link_up: pointer to bool (true/false = linkup/linkdown)
2781 * Variable link_up is true if link is up, false if link is down.
2782 * The variable link_up is invalid if status is non zero. As a
2783 * result of this call, link status reporting becomes enabled
2785 enum ice_status ice_get_link_status(struct ice_port_info *pi, bool *link_up)
2787 struct ice_phy_info *phy_info;
2788 enum ice_status status = ICE_SUCCESS;
2790 if (!pi || !link_up)
2791 return ICE_ERR_PARAM;
2793 phy_info = &pi->phy;
2795 if (phy_info->get_link_info) {
2796 status = ice_update_link_info(pi);
2799 ice_debug(pi->hw, ICE_DBG_LINK,
2800 "get link status error, status = %d\n",
2804 *link_up = phy_info->link_info.link_info & ICE_AQ_LINK_UP;
2810 * ice_aq_set_link_restart_an
2811 * @pi: pointer to the port information structure
2812 * @ena_link: if true: enable link, if false: disable link
2813 * @cd: pointer to command details structure or NULL
2815 * Sets up the link and restarts the Auto-Negotiation over the link.
2818 ice_aq_set_link_restart_an(struct ice_port_info *pi, bool ena_link,
2819 struct ice_sq_cd *cd)
2821 struct ice_aqc_restart_an *cmd;
2822 struct ice_aq_desc desc;
2824 cmd = &desc.params.restart_an;
2826 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_restart_an);
2828 cmd->cmd_flags = ICE_AQC_RESTART_AN_LINK_RESTART;
2829 cmd->lport_num = pi->lport;
2831 cmd->cmd_flags |= ICE_AQC_RESTART_AN_LINK_ENABLE;
2833 cmd->cmd_flags &= ~ICE_AQC_RESTART_AN_LINK_ENABLE;
2835 return ice_aq_send_cmd(pi->hw, &desc, NULL, 0, cd);
2839 * ice_aq_set_event_mask
2840 * @hw: pointer to the HW struct
2841 * @port_num: port number of the physical function
2842 * @mask: event mask to be set
2843 * @cd: pointer to command details structure or NULL
2845 * Set event mask (0x0613)
2848 ice_aq_set_event_mask(struct ice_hw *hw, u8 port_num, u16 mask,
2849 struct ice_sq_cd *cd)
2851 struct ice_aqc_set_event_mask *cmd;
2852 struct ice_aq_desc desc;
2854 cmd = &desc.params.set_event_mask;
2856 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_event_mask);
2858 cmd->lport_num = port_num;
2860 cmd->event_mask = CPU_TO_LE16(mask);
2861 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
2865 * ice_aq_set_mac_loopback
2866 * @hw: pointer to the HW struct
2867 * @ena_lpbk: Enable or Disable loopback
2868 * @cd: pointer to command details structure or NULL
2870 * Enable/disable loopback on a given port
2873 ice_aq_set_mac_loopback(struct ice_hw *hw, bool ena_lpbk, struct ice_sq_cd *cd)
2875 struct ice_aqc_set_mac_lb *cmd;
2876 struct ice_aq_desc desc;
2878 cmd = &desc.params.set_mac_lb;
2880 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_mac_lb);
2882 cmd->lb_mode = ICE_AQ_MAC_LB_EN;
2884 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
2889 * ice_aq_set_port_id_led
2890 * @pi: pointer to the port information
2891 * @is_orig_mode: is this LED set to original mode (by the net-list)
2892 * @cd: pointer to command details structure or NULL
2894 * Set LED value for the given port (0x06e9)
2897 ice_aq_set_port_id_led(struct ice_port_info *pi, bool is_orig_mode,
2898 struct ice_sq_cd *cd)
2900 struct ice_aqc_set_port_id_led *cmd;
2901 struct ice_hw *hw = pi->hw;
2902 struct ice_aq_desc desc;
2904 cmd = &desc.params.set_port_id_led;
2906 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_port_id_led);
2910 cmd->ident_mode = ICE_AQC_PORT_IDENT_LED_ORIG;
2912 cmd->ident_mode = ICE_AQC_PORT_IDENT_LED_BLINK;
2914 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
2918 * __ice_aq_get_set_rss_lut
2919 * @hw: pointer to the hardware structure
2920 * @vsi_id: VSI FW index
2921 * @lut_type: LUT table type
2922 * @lut: pointer to the LUT buffer provided by the caller
2923 * @lut_size: size of the LUT buffer
2924 * @glob_lut_idx: global LUT index
2925 * @set: set true to set the table, false to get the table
2927 * Internal function to get (0x0B05) or set (0x0B03) RSS look up table
2929 static enum ice_status
2930 __ice_aq_get_set_rss_lut(struct ice_hw *hw, u16 vsi_id, u8 lut_type, u8 *lut,
2931 u16 lut_size, u8 glob_lut_idx, bool set)
2933 struct ice_aqc_get_set_rss_lut *cmd_resp;
2934 struct ice_aq_desc desc;
2935 enum ice_status status;
2938 cmd_resp = &desc.params.get_set_rss_lut;
2941 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_rss_lut);
2942 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
2944 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_rss_lut);
2947 cmd_resp->vsi_id = CPU_TO_LE16(((vsi_id <<
2948 ICE_AQC_GSET_RSS_LUT_VSI_ID_S) &
2949 ICE_AQC_GSET_RSS_LUT_VSI_ID_M) |
2950 ICE_AQC_GSET_RSS_LUT_VSI_VALID);
2953 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_VSI:
2954 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF:
2955 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL:
2956 flags |= ((lut_type << ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S) &
2957 ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_M);
2960 status = ICE_ERR_PARAM;
2961 goto ice_aq_get_set_rss_lut_exit;
2964 if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL) {
2965 flags |= ((glob_lut_idx << ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S) &
2966 ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_M);
2969 goto ice_aq_get_set_rss_lut_send;
2970 } else if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF) {
2972 goto ice_aq_get_set_rss_lut_send;
2974 goto ice_aq_get_set_rss_lut_send;
2977 /* LUT size is only valid for Global and PF table types */
2979 case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128:
2980 flags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128_FLAG <<
2981 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) &
2982 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M;
2984 case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512:
2985 flags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512_FLAG <<
2986 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) &
2987 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M;
2989 case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K:
2990 if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF) {
2991 flags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K_FLAG <<
2992 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) &
2993 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M;
2998 status = ICE_ERR_PARAM;
2999 goto ice_aq_get_set_rss_lut_exit;
3002 ice_aq_get_set_rss_lut_send:
3003 cmd_resp->flags = CPU_TO_LE16(flags);
3004 status = ice_aq_send_cmd(hw, &desc, lut, lut_size, NULL);
3006 ice_aq_get_set_rss_lut_exit:
3011 * ice_aq_get_rss_lut
3012 * @hw: pointer to the hardware structure
3013 * @vsi_handle: software VSI handle
3014 * @lut_type: LUT table type
3015 * @lut: pointer to the LUT buffer provided by the caller
3016 * @lut_size: size of the LUT buffer
3018 * get the RSS lookup table, PF or VSI type
3021 ice_aq_get_rss_lut(struct ice_hw *hw, u16 vsi_handle, u8 lut_type,
3022 u8 *lut, u16 lut_size)
3024 if (!ice_is_vsi_valid(hw, vsi_handle) || !lut)
3025 return ICE_ERR_PARAM;
3027 return __ice_aq_get_set_rss_lut(hw, ice_get_hw_vsi_num(hw, vsi_handle),
3028 lut_type, lut, lut_size, 0, false);
3032 * ice_aq_set_rss_lut
3033 * @hw: pointer to the hardware structure
3034 * @vsi_handle: software VSI handle
3035 * @lut_type: LUT table type
3036 * @lut: pointer to the LUT buffer provided by the caller
3037 * @lut_size: size of the LUT buffer
3039 * set the RSS lookup table, PF or VSI type
3042 ice_aq_set_rss_lut(struct ice_hw *hw, u16 vsi_handle, u8 lut_type,
3043 u8 *lut, u16 lut_size)
3045 if (!ice_is_vsi_valid(hw, vsi_handle) || !lut)
3046 return ICE_ERR_PARAM;
3048 return __ice_aq_get_set_rss_lut(hw, ice_get_hw_vsi_num(hw, vsi_handle),
3049 lut_type, lut, lut_size, 0, true);
3053 * __ice_aq_get_set_rss_key
3054 * @hw: pointer to the HW struct
3055 * @vsi_id: VSI FW index
3056 * @key: pointer to key info struct
3057 * @set: set true to set the key, false to get the key
3059 * get (0x0B04) or set (0x0B02) the RSS key per VSI
3062 ice_status __ice_aq_get_set_rss_key(struct ice_hw *hw, u16 vsi_id,
3063 struct ice_aqc_get_set_rss_keys *key,
3066 struct ice_aqc_get_set_rss_key *cmd_resp;
3067 u16 key_size = sizeof(*key);
3068 struct ice_aq_desc desc;
3070 cmd_resp = &desc.params.get_set_rss_key;
3073 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_rss_key);
3074 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
3076 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_rss_key);
3079 cmd_resp->vsi_id = CPU_TO_LE16(((vsi_id <<
3080 ICE_AQC_GSET_RSS_KEY_VSI_ID_S) &
3081 ICE_AQC_GSET_RSS_KEY_VSI_ID_M) |
3082 ICE_AQC_GSET_RSS_KEY_VSI_VALID);
3084 return ice_aq_send_cmd(hw, &desc, key, key_size, NULL);
3088 * ice_aq_get_rss_key
3089 * @hw: pointer to the HW struct
3090 * @vsi_handle: software VSI handle
3091 * @key: pointer to key info struct
3093 * get the RSS key per VSI
3096 ice_aq_get_rss_key(struct ice_hw *hw, u16 vsi_handle,
3097 struct ice_aqc_get_set_rss_keys *key)
3099 if (!ice_is_vsi_valid(hw, vsi_handle) || !key)
3100 return ICE_ERR_PARAM;
3102 return __ice_aq_get_set_rss_key(hw, ice_get_hw_vsi_num(hw, vsi_handle),
3107 * ice_aq_set_rss_key
3108 * @hw: pointer to the HW struct
3109 * @vsi_handle: software VSI handle
3110 * @keys: pointer to key info struct
3112 * set the RSS key per VSI
3115 ice_aq_set_rss_key(struct ice_hw *hw, u16 vsi_handle,
3116 struct ice_aqc_get_set_rss_keys *keys)
3118 if (!ice_is_vsi_valid(hw, vsi_handle) || !keys)
3119 return ICE_ERR_PARAM;
3121 return __ice_aq_get_set_rss_key(hw, ice_get_hw_vsi_num(hw, vsi_handle),
3126 * ice_aq_add_lan_txq
3127 * @hw: pointer to the hardware structure
3128 * @num_qgrps: Number of added queue groups
3129 * @qg_list: list of queue groups to be added
3130 * @buf_size: size of buffer for indirect command
3131 * @cd: pointer to command details structure or NULL
3133 * Add Tx LAN queue (0x0C30)
3136 * Prior to calling add Tx LAN queue:
3137 * Initialize the following as part of the Tx queue context:
3138 * Completion queue ID if the queue uses Completion queue, Quanta profile,
3139 * Cache profile and Packet shaper profile.
3141 * After add Tx LAN queue AQ command is completed:
3142 * Interrupts should be associated with specific queues,
3143 * Association of Tx queue to Doorbell queue is not part of Add LAN Tx queue
3147 ice_aq_add_lan_txq(struct ice_hw *hw, u8 num_qgrps,
3148 struct ice_aqc_add_tx_qgrp *qg_list, u16 buf_size,
3149 struct ice_sq_cd *cd)
3151 u16 i, sum_header_size, sum_q_size = 0;
3152 struct ice_aqc_add_tx_qgrp *list;
3153 struct ice_aqc_add_txqs *cmd;
3154 struct ice_aq_desc desc;
3156 ice_debug(hw, ICE_DBG_TRACE, "ice_aq_add_lan_txq");
3158 cmd = &desc.params.add_txqs;
3160 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_add_txqs);
3163 return ICE_ERR_PARAM;
3165 if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS)
3166 return ICE_ERR_PARAM;
3168 sum_header_size = num_qgrps *
3169 (sizeof(*qg_list) - sizeof(*qg_list->txqs));
3172 for (i = 0; i < num_qgrps; i++) {
3173 struct ice_aqc_add_txqs_perq *q = list->txqs;
3175 sum_q_size += list->num_txqs * sizeof(*q);
3176 list = (struct ice_aqc_add_tx_qgrp *)(q + list->num_txqs);
3179 if (buf_size != (sum_header_size + sum_q_size))
3180 return ICE_ERR_PARAM;
3182 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
3184 cmd->num_qgrps = num_qgrps;
3186 return ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd);
3190 * ice_aq_dis_lan_txq
3191 * @hw: pointer to the hardware structure
3192 * @num_qgrps: number of groups in the list
3193 * @qg_list: the list of groups to disable
3194 * @buf_size: the total size of the qg_list buffer in bytes
3195 * @rst_src: if called due to reset, specifies the reset source
3196 * @vmvf_num: the relative VM or VF number that is undergoing the reset
3197 * @cd: pointer to command details structure or NULL
3199 * Disable LAN Tx queue (0x0C31)
3201 static enum ice_status
3202 ice_aq_dis_lan_txq(struct ice_hw *hw, u8 num_qgrps,
3203 struct ice_aqc_dis_txq_item *qg_list, u16 buf_size,
3204 enum ice_disq_rst_src rst_src, u16 vmvf_num,
3205 struct ice_sq_cd *cd)
3207 struct ice_aqc_dis_txqs *cmd;
3208 struct ice_aq_desc desc;
3209 enum ice_status status;
3212 ice_debug(hw, ICE_DBG_TRACE, "ice_aq_dis_lan_txq");
3213 cmd = &desc.params.dis_txqs;
3214 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_dis_txqs);
3216 /* qg_list can be NULL only in VM/VF reset flow */
3217 if (!qg_list && !rst_src)
3218 return ICE_ERR_PARAM;
3220 if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS)
3221 return ICE_ERR_PARAM;
3223 cmd->num_entries = num_qgrps;
3225 cmd->vmvf_and_timeout = CPU_TO_LE16((5 << ICE_AQC_Q_DIS_TIMEOUT_S) &
3226 ICE_AQC_Q_DIS_TIMEOUT_M);
3230 cmd->cmd_type = ICE_AQC_Q_DIS_CMD_VM_RESET;
3231 cmd->vmvf_and_timeout |=
3232 CPU_TO_LE16(vmvf_num & ICE_AQC_Q_DIS_VMVF_NUM_M);
3239 /* flush pipe on time out */
3240 cmd->cmd_type |= ICE_AQC_Q_DIS_CMD_FLUSH_PIPE;
3241 /* If no queue group info, we are in a reset flow. Issue the AQ */
3245 /* set RD bit to indicate that command buffer is provided by the driver
3246 * and it needs to be read by the firmware
3248 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
3250 for (i = 0; i < num_qgrps; ++i) {
3251 /* Calculate the size taken up by the queue IDs in this group */
3252 sz += qg_list[i].num_qs * sizeof(qg_list[i].q_id);
3254 /* Add the size of the group header */
3255 sz += sizeof(qg_list[i]) - sizeof(qg_list[i].q_id);
3257 /* If the num of queues is even, add 2 bytes of padding */
3258 if ((qg_list[i].num_qs % 2) == 0)
3263 return ICE_ERR_PARAM;
3266 status = ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd);
3269 ice_debug(hw, ICE_DBG_SCHED, "VM%d disable failed %d\n",
3270 vmvf_num, hw->adminq.sq_last_status);
3272 ice_debug(hw, ICE_DBG_SCHED, "disable queue %d failed %d\n",
3273 LE16_TO_CPU(qg_list[0].q_id[0]),
3274 hw->adminq.sq_last_status);
3280 /* End of FW Admin Queue command wrappers */
3283 * ice_write_byte - write a byte to a packed context structure
3284 * @src_ctx: the context structure to read from
3285 * @dest_ctx: the context to be written to
3286 * @ce_info: a description of the struct to be filled
3289 ice_write_byte(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)
3291 u8 src_byte, dest_byte, mask;
3295 /* copy from the next struct field */
3296 from = src_ctx + ce_info->offset;
3298 /* prepare the bits and mask */
3299 shift_width = ce_info->lsb % 8;
3300 mask = (u8)(BIT(ce_info->width) - 1);
3305 /* shift to correct alignment */
3306 mask <<= shift_width;
3307 src_byte <<= shift_width;
3309 /* get the current bits from the target bit string */
3310 dest = dest_ctx + (ce_info->lsb / 8);
3312 ice_memcpy(&dest_byte, dest, sizeof(dest_byte), ICE_DMA_TO_NONDMA);
3314 dest_byte &= ~mask; /* get the bits not changing */
3315 dest_byte |= src_byte; /* add in the new bits */
3317 /* put it all back */
3318 ice_memcpy(dest, &dest_byte, sizeof(dest_byte), ICE_NONDMA_TO_DMA);
3322 * ice_write_word - write a word to a packed context structure
3323 * @src_ctx: the context structure to read from
3324 * @dest_ctx: the context to be written to
3325 * @ce_info: a description of the struct to be filled
3328 ice_write_word(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)
3335 /* copy from the next struct field */
3336 from = src_ctx + ce_info->offset;
3338 /* prepare the bits and mask */
3339 shift_width = ce_info->lsb % 8;
3340 mask = BIT(ce_info->width) - 1;
3342 /* don't swizzle the bits until after the mask because the mask bits
3343 * will be in a different bit position on big endian machines
3345 src_word = *(u16 *)from;
3348 /* shift to correct alignment */
3349 mask <<= shift_width;
3350 src_word <<= shift_width;
3352 /* get the current bits from the target bit string */
3353 dest = dest_ctx + (ce_info->lsb / 8);
3355 ice_memcpy(&dest_word, dest, sizeof(dest_word), ICE_DMA_TO_NONDMA);
3357 dest_word &= ~(CPU_TO_LE16(mask)); /* get the bits not changing */
3358 dest_word |= CPU_TO_LE16(src_word); /* add in the new bits */
3360 /* put it all back */
3361 ice_memcpy(dest, &dest_word, sizeof(dest_word), ICE_NONDMA_TO_DMA);
3365 * ice_write_dword - write a dword to a packed context structure
3366 * @src_ctx: the context structure to read from
3367 * @dest_ctx: the context to be written to
3368 * @ce_info: a description of the struct to be filled
3371 ice_write_dword(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)
3373 u32 src_dword, mask;
3378 /* copy from the next struct field */
3379 from = src_ctx + ce_info->offset;
3381 /* prepare the bits and mask */
3382 shift_width = ce_info->lsb % 8;
3384 /* if the field width is exactly 32 on an x86 machine, then the shift
3385 * operation will not work because the SHL instructions count is masked
3386 * to 5 bits so the shift will do nothing
3388 if (ce_info->width < 32)
3389 mask = BIT(ce_info->width) - 1;
3393 /* don't swizzle the bits until after the mask because the mask bits
3394 * will be in a different bit position on big endian machines
3396 src_dword = *(u32 *)from;
3399 /* shift to correct alignment */
3400 mask <<= shift_width;
3401 src_dword <<= shift_width;
3403 /* get the current bits from the target bit string */
3404 dest = dest_ctx + (ce_info->lsb / 8);
3406 ice_memcpy(&dest_dword, dest, sizeof(dest_dword), ICE_DMA_TO_NONDMA);
3408 dest_dword &= ~(CPU_TO_LE32(mask)); /* get the bits not changing */
3409 dest_dword |= CPU_TO_LE32(src_dword); /* add in the new bits */
3411 /* put it all back */
3412 ice_memcpy(dest, &dest_dword, sizeof(dest_dword), ICE_NONDMA_TO_DMA);
3416 * ice_write_qword - write a qword to a packed context structure
3417 * @src_ctx: the context structure to read from
3418 * @dest_ctx: the context to be written to
3419 * @ce_info: a description of the struct to be filled
3422 ice_write_qword(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)
3424 u64 src_qword, mask;
3429 /* copy from the next struct field */
3430 from = src_ctx + ce_info->offset;
3432 /* prepare the bits and mask */
3433 shift_width = ce_info->lsb % 8;
3435 /* if the field width is exactly 64 on an x86 machine, then the shift
3436 * operation will not work because the SHL instructions count is masked
3437 * to 6 bits so the shift will do nothing
3439 if (ce_info->width < 64)
3440 mask = BIT_ULL(ce_info->width) - 1;
3444 /* don't swizzle the bits until after the mask because the mask bits
3445 * will be in a different bit position on big endian machines
3447 src_qword = *(u64 *)from;
3450 /* shift to correct alignment */
3451 mask <<= shift_width;
3452 src_qword <<= shift_width;
3454 /* get the current bits from the target bit string */
3455 dest = dest_ctx + (ce_info->lsb / 8);
3457 ice_memcpy(&dest_qword, dest, sizeof(dest_qword), ICE_DMA_TO_NONDMA);
3459 dest_qword &= ~(CPU_TO_LE64(mask)); /* get the bits not changing */
3460 dest_qword |= CPU_TO_LE64(src_qword); /* add in the new bits */
3462 /* put it all back */
3463 ice_memcpy(dest, &dest_qword, sizeof(dest_qword), ICE_NONDMA_TO_DMA);
3467 * ice_set_ctx - set context bits in packed structure
3468 * @src_ctx: pointer to a generic non-packed context structure
3469 * @dest_ctx: pointer to memory for the packed structure
3470 * @ce_info: a description of the structure to be transformed
3473 ice_set_ctx(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)
3477 for (f = 0; ce_info[f].width; f++) {
3478 /* We have to deal with each element of the FW response
3479 * using the correct size so that we are correct regardless
3480 * of the endianness of the machine.
3482 switch (ce_info[f].size_of) {
3484 ice_write_byte(src_ctx, dest_ctx, &ce_info[f]);
3487 ice_write_word(src_ctx, dest_ctx, &ce_info[f]);
3490 ice_write_dword(src_ctx, dest_ctx, &ce_info[f]);
3493 ice_write_qword(src_ctx, dest_ctx, &ce_info[f]);
3496 return ICE_ERR_INVAL_SIZE;
3507 * ice_read_byte - read context byte into struct
3508 * @src_ctx: the context structure to read from
3509 * @dest_ctx: the context to be written to
3510 * @ce_info: a description of the struct to be filled
3513 ice_read_byte(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info)
3519 /* prepare the bits and mask */
3520 shift_width = ce_info->lsb % 8;
3521 mask = (u8)(BIT(ce_info->width) - 1);
3523 /* shift to correct alignment */
3524 mask <<= shift_width;
3526 /* get the current bits from the src bit string */
3527 src = src_ctx + (ce_info->lsb / 8);
3529 ice_memcpy(&dest_byte, src, sizeof(dest_byte), ICE_DMA_TO_NONDMA);
3531 dest_byte &= ~(mask);
3533 dest_byte >>= shift_width;
3535 /* get the address from the struct field */
3536 target = dest_ctx + ce_info->offset;
3538 /* put it back in the struct */
3539 ice_memcpy(target, &dest_byte, sizeof(dest_byte), ICE_NONDMA_TO_DMA);
3543 * ice_read_word - read context word into struct
3544 * @src_ctx: the context structure to read from
3545 * @dest_ctx: the context to be written to
3546 * @ce_info: a description of the struct to be filled
3549 ice_read_word(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info)
3551 u16 dest_word, mask;
3556 /* prepare the bits and mask */
3557 shift_width = ce_info->lsb % 8;
3558 mask = BIT(ce_info->width) - 1;
3560 /* shift to correct alignment */
3561 mask <<= shift_width;
3563 /* get the current bits from the src bit string */
3564 src = src_ctx + (ce_info->lsb / 8);
3566 ice_memcpy(&src_word, src, sizeof(src_word), ICE_DMA_TO_NONDMA);
3568 /* the data in the memory is stored as little endian so mask it
3571 src_word &= ~(CPU_TO_LE16(mask));
3573 /* get the data back into host order before shifting */
3574 dest_word = LE16_TO_CPU(src_word);
3576 dest_word >>= shift_width;
3578 /* get the address from the struct field */
3579 target = dest_ctx + ce_info->offset;
3581 /* put it back in the struct */
3582 ice_memcpy(target, &dest_word, sizeof(dest_word), ICE_NONDMA_TO_DMA);
3586 * ice_read_dword - read context dword into struct
3587 * @src_ctx: the context structure to read from
3588 * @dest_ctx: the context to be written to
3589 * @ce_info: a description of the struct to be filled
3592 ice_read_dword(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info)
3594 u32 dest_dword, mask;
3599 /* prepare the bits and mask */
3600 shift_width = ce_info->lsb % 8;
3602 /* if the field width is exactly 32 on an x86 machine, then the shift
3603 * operation will not work because the SHL instructions count is masked
3604 * to 5 bits so the shift will do nothing
3606 if (ce_info->width < 32)
3607 mask = BIT(ce_info->width) - 1;
3611 /* shift to correct alignment */
3612 mask <<= shift_width;
3614 /* get the current bits from the src bit string */
3615 src = src_ctx + (ce_info->lsb / 8);
3617 ice_memcpy(&src_dword, src, sizeof(src_dword), ICE_DMA_TO_NONDMA);
3619 /* the data in the memory is stored as little endian so mask it
3622 src_dword &= ~(CPU_TO_LE32(mask));
3624 /* get the data back into host order before shifting */
3625 dest_dword = LE32_TO_CPU(src_dword);
3627 dest_dword >>= shift_width;
3629 /* get the address from the struct field */
3630 target = dest_ctx + ce_info->offset;
3632 /* put it back in the struct */
3633 ice_memcpy(target, &dest_dword, sizeof(dest_dword), ICE_NONDMA_TO_DMA);
3637 * ice_read_qword - read context qword into struct
3638 * @src_ctx: the context structure to read from
3639 * @dest_ctx: the context to be written to
3640 * @ce_info: a description of the struct to be filled
3643 ice_read_qword(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info)
3645 u64 dest_qword, mask;
3650 /* prepare the bits and mask */
3651 shift_width = ce_info->lsb % 8;
3653 /* if the field width is exactly 64 on an x86 machine, then the shift
3654 * operation will not work because the SHL instructions count is masked
3655 * to 6 bits so the shift will do nothing
3657 if (ce_info->width < 64)
3658 mask = BIT_ULL(ce_info->width) - 1;
3662 /* shift to correct alignment */
3663 mask <<= shift_width;
3665 /* get the current bits from the src bit string */
3666 src = src_ctx + (ce_info->lsb / 8);
3668 ice_memcpy(&src_qword, src, sizeof(src_qword), ICE_DMA_TO_NONDMA);
3670 /* the data in the memory is stored as little endian so mask it
3673 src_qword &= ~(CPU_TO_LE64(mask));
3675 /* get the data back into host order before shifting */
3676 dest_qword = LE64_TO_CPU(src_qword);
3678 dest_qword >>= shift_width;
3680 /* get the address from the struct field */
3681 target = dest_ctx + ce_info->offset;
3683 /* put it back in the struct */
3684 ice_memcpy(target, &dest_qword, sizeof(dest_qword), ICE_NONDMA_TO_DMA);
3688 * ice_get_ctx - extract context bits from a packed structure
3689 * @src_ctx: pointer to a generic packed context structure
3690 * @dest_ctx: pointer to a generic non-packed context structure
3691 * @ce_info: a description of the structure to be read from
3694 ice_get_ctx(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info)
3698 for (f = 0; ce_info[f].width; f++) {
3699 switch (ce_info[f].size_of) {
3701 ice_read_byte(src_ctx, dest_ctx, &ce_info[f]);
3704 ice_read_word(src_ctx, dest_ctx, &ce_info[f]);
3707 ice_read_dword(src_ctx, dest_ctx, &ce_info[f]);
3710 ice_read_qword(src_ctx, dest_ctx, &ce_info[f]);
3713 /* nothing to do, just keep going */
3722 * ice_get_lan_q_ctx - get the LAN queue context for the given VSI and TC
3723 * @hw: pointer to the HW struct
3724 * @vsi_handle: software VSI handle
3726 * @q_handle: software queue handle
3729 ice_get_lan_q_ctx(struct ice_hw *hw, u16 vsi_handle, u8 tc, u16 q_handle)
3731 struct ice_vsi_ctx *vsi;
3732 struct ice_q_ctx *q_ctx;
3734 vsi = ice_get_vsi_ctx(hw, vsi_handle);
3737 if (q_handle >= vsi->num_lan_q_entries[tc])
3739 if (!vsi->lan_q_ctx[tc])
3741 q_ctx = vsi->lan_q_ctx[tc];
3742 return &q_ctx[q_handle];
3747 * @pi: port information structure
3748 * @vsi_handle: software VSI handle
3750 * @q_handle: software queue handle
3751 * @num_qgrps: Number of added queue groups
3752 * @buf: list of queue groups to be added
3753 * @buf_size: size of buffer for indirect command
3754 * @cd: pointer to command details structure or NULL
3756 * This function adds one LAN queue
3759 ice_ena_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u16 q_handle,
3760 u8 num_qgrps, struct ice_aqc_add_tx_qgrp *buf, u16 buf_size,
3761 struct ice_sq_cd *cd)
3763 struct ice_aqc_txsched_elem_data node = { 0 };
3764 struct ice_sched_node *parent;
3765 struct ice_q_ctx *q_ctx;
3766 enum ice_status status;
3769 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY)
3772 if (num_qgrps > 1 || buf->num_txqs > 1)
3773 return ICE_ERR_MAX_LIMIT;
3777 if (!ice_is_vsi_valid(hw, vsi_handle))
3778 return ICE_ERR_PARAM;
3780 ice_acquire_lock(&pi->sched_lock);
3782 q_ctx = ice_get_lan_q_ctx(hw, vsi_handle, tc, q_handle);
3784 ice_debug(hw, ICE_DBG_SCHED, "Enaq: invalid queue handle %d\n",
3786 status = ICE_ERR_PARAM;
3790 /* find a parent node */
3791 parent = ice_sched_get_free_qparent(pi, vsi_handle, tc,
3792 ICE_SCHED_NODE_OWNER_LAN);
3794 status = ICE_ERR_PARAM;
3798 buf->parent_teid = parent->info.node_teid;
3799 node.parent_teid = parent->info.node_teid;
3800 /* Mark that the values in the "generic" section as valid. The default
3801 * value in the "generic" section is zero. This means that :
3802 * - Scheduling mode is Bytes Per Second (BPS), indicated by Bit 0.
3803 * - 0 priority among siblings, indicated by Bit 1-3.
3804 * - WFQ, indicated by Bit 4.
3805 * - 0 Adjustment value is used in PSM credit update flow, indicated by
3807 * - Bit 7 is reserved.
3808 * Without setting the generic section as valid in valid_sections, the
3809 * Admin queue command will fail with error code ICE_AQ_RC_EINVAL.
3811 buf->txqs[0].info.valid_sections = ICE_AQC_ELEM_VALID_GENERIC;
3813 /* add the LAN queue */
3814 status = ice_aq_add_lan_txq(hw, num_qgrps, buf, buf_size, cd);
3815 if (status != ICE_SUCCESS) {
3816 ice_debug(hw, ICE_DBG_SCHED, "enable queue %d failed %d\n",
3817 LE16_TO_CPU(buf->txqs[0].txq_id),
3818 hw->adminq.sq_last_status);
3822 node.node_teid = buf->txqs[0].q_teid;
3823 node.data.elem_type = ICE_AQC_ELEM_TYPE_LEAF;
3824 q_ctx->q_handle = q_handle;
3825 q_ctx->q_teid = LE32_TO_CPU(node.node_teid);
3827 /* add a leaf node into scheduler tree queue layer */
3828 status = ice_sched_add_node(pi, hw->num_tx_sched_layers - 1, &node);
3830 status = ice_sched_replay_q_bw(pi, q_ctx);
3833 ice_release_lock(&pi->sched_lock);
3839 * @pi: port information structure
3840 * @vsi_handle: software VSI handle
3842 * @num_queues: number of queues
3843 * @q_handles: pointer to software queue handle array
3844 * @q_ids: pointer to the q_id array
3845 * @q_teids: pointer to queue node teids
3846 * @rst_src: if called due to reset, specifies the reset source
3847 * @vmvf_num: the relative VM or VF number that is undergoing the reset
3848 * @cd: pointer to command details structure or NULL
3850 * This function removes queues and their corresponding nodes in SW DB
3853 ice_dis_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u8 num_queues,
3854 u16 *q_handles, u16 *q_ids, u32 *q_teids,
3855 enum ice_disq_rst_src rst_src, u16 vmvf_num,
3856 struct ice_sq_cd *cd)
3858 enum ice_status status = ICE_ERR_DOES_NOT_EXIST;
3859 struct ice_aqc_dis_txq_item qg_list;
3860 struct ice_q_ctx *q_ctx;
3863 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY)
3868 /* if queue is disabled already yet the disable queue command
3869 * has to be sent to complete the VF reset, then call
3870 * ice_aq_dis_lan_txq without any queue information
3873 return ice_aq_dis_lan_txq(pi->hw, 0, NULL, 0, rst_src,
3878 ice_acquire_lock(&pi->sched_lock);
3880 for (i = 0; i < num_queues; i++) {
3881 struct ice_sched_node *node;
3883 node = ice_sched_find_node_by_teid(pi->root, q_teids[i]);
3886 q_ctx = ice_get_lan_q_ctx(pi->hw, vsi_handle, tc, q_handles[i]);
3888 ice_debug(pi->hw, ICE_DBG_SCHED, "invalid queue handle%d\n",
3892 if (q_ctx->q_handle != q_handles[i]) {
3893 ice_debug(pi->hw, ICE_DBG_SCHED, "Err:handles %d %d\n",
3894 q_ctx->q_handle, q_handles[i]);
3897 qg_list.parent_teid = node->info.parent_teid;
3899 qg_list.q_id[0] = CPU_TO_LE16(q_ids[i]);
3900 status = ice_aq_dis_lan_txq(pi->hw, 1, &qg_list,
3901 sizeof(qg_list), rst_src, vmvf_num,
3904 if (status != ICE_SUCCESS)
3906 ice_free_sched_node(pi, node);
3907 q_ctx->q_handle = ICE_INVAL_Q_HANDLE;
3909 ice_release_lock(&pi->sched_lock);
3914 * ice_cfg_vsi_qs - configure the new/existing VSI queues
3915 * @pi: port information structure
3916 * @vsi_handle: software VSI handle
3917 * @tc_bitmap: TC bitmap
3918 * @maxqs: max queues array per TC
3919 * @owner: LAN or RDMA
3921 * This function adds/updates the VSI queues per TC.
3923 static enum ice_status
3924 ice_cfg_vsi_qs(struct ice_port_info *pi, u16 vsi_handle, u8 tc_bitmap,
3925 u16 *maxqs, u8 owner)
3927 enum ice_status status = ICE_SUCCESS;
3930 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY)
3933 if (!ice_is_vsi_valid(pi->hw, vsi_handle))
3934 return ICE_ERR_PARAM;
3936 ice_acquire_lock(&pi->sched_lock);
3938 ice_for_each_traffic_class(i) {
3939 /* configuration is possible only if TC node is present */
3940 if (!ice_sched_get_tc_node(pi, i))
3943 status = ice_sched_cfg_vsi(pi, vsi_handle, i, maxqs[i], owner,
3944 ice_is_tc_ena(tc_bitmap, i));
3949 ice_release_lock(&pi->sched_lock);
3954 * ice_cfg_vsi_lan - configure VSI LAN queues
3955 * @pi: port information structure
3956 * @vsi_handle: software VSI handle
3957 * @tc_bitmap: TC bitmap
3958 * @max_lanqs: max LAN queues array per TC
3960 * This function adds/updates the VSI LAN queues per TC.
3963 ice_cfg_vsi_lan(struct ice_port_info *pi, u16 vsi_handle, u8 tc_bitmap,
3966 return ice_cfg_vsi_qs(pi, vsi_handle, tc_bitmap, max_lanqs,
3967 ICE_SCHED_NODE_OWNER_LAN);
3973 * ice_replay_pre_init - replay pre initialization
3974 * @hw: pointer to the HW struct
3976 * Initializes required config data for VSI, FD, ACL, and RSS before replay.
3978 static enum ice_status ice_replay_pre_init(struct ice_hw *hw)
3980 struct ice_switch_info *sw = hw->switch_info;
3983 /* Delete old entries from replay filter list head if there is any */
3984 ice_rm_all_sw_replay_rule_info(hw);
3985 /* In start of replay, move entries into replay_rules list, it
3986 * will allow adding rules entries back to filt_rules list,
3987 * which is operational list.
3989 for (i = 0; i < ICE_MAX_NUM_RECIPES; i++)
3990 LIST_REPLACE_INIT(&sw->recp_list[i].filt_rules,
3991 &sw->recp_list[i].filt_replay_rules);
3992 ice_sched_replay_agg_vsi_preinit(hw);
3994 return ice_sched_replay_tc_node_bw(hw);
3998 * ice_replay_vsi - replay VSI configuration
3999 * @hw: pointer to the HW struct
4000 * @vsi_handle: driver VSI handle
4002 * Restore all VSI configuration after reset. It is required to call this
4003 * function with main VSI first.
4005 enum ice_status ice_replay_vsi(struct ice_hw *hw, u16 vsi_handle)
4007 enum ice_status status;
4009 if (!ice_is_vsi_valid(hw, vsi_handle))
4010 return ICE_ERR_PARAM;
4012 /* Replay pre-initialization if there is any */
4013 if (vsi_handle == ICE_MAIN_VSI_HANDLE) {
4014 status = ice_replay_pre_init(hw);
4018 /* Replay per VSI all RSS configurations */
4019 status = ice_replay_rss_cfg(hw, vsi_handle);
4022 /* Replay per VSI all filters */
4023 status = ice_replay_vsi_all_fltr(hw, vsi_handle);
4025 status = ice_replay_vsi_agg(hw, vsi_handle);
4030 * ice_replay_post - post replay configuration cleanup
4031 * @hw: pointer to the HW struct
4033 * Post replay cleanup.
4035 void ice_replay_post(struct ice_hw *hw)
4037 /* Delete old entries from replay filter list head */
4038 ice_rm_all_sw_replay_rule_info(hw);
4039 ice_sched_replay_agg(hw);
4043 * ice_stat_update40 - read 40 bit stat from the chip and update stat values
4044 * @hw: ptr to the hardware info
4045 * @hireg: high 32 bit HW register to read from
4046 * @loreg: low 32 bit HW register to read from
4047 * @prev_stat_loaded: bool to specify if previous stats are loaded
4048 * @prev_stat: ptr to previous loaded stat value
4049 * @cur_stat: ptr to current stat value
4052 ice_stat_update40(struct ice_hw *hw, u32 hireg, u32 loreg,
4053 bool prev_stat_loaded, u64 *prev_stat, u64 *cur_stat)
4057 new_data = rd32(hw, loreg);
4058 new_data |= ((u64)(rd32(hw, hireg) & 0xFFFF)) << 32;
4060 /* device stats are not reset at PFR, they likely will not be zeroed
4061 * when the driver starts. So save the first values read and use them as
4062 * offsets to be subtracted from the raw values in order to report stats
4063 * that count from zero.
4065 if (!prev_stat_loaded)
4066 *prev_stat = new_data;
4067 if (new_data >= *prev_stat)
4068 *cur_stat = new_data - *prev_stat;
4070 /* to manage the potential roll-over */
4071 *cur_stat = (new_data + BIT_ULL(40)) - *prev_stat;
4072 *cur_stat &= 0xFFFFFFFFFFULL;
4076 * ice_stat_update32 - read 32 bit stat from the chip and update stat values
4077 * @hw: ptr to the hardware info
4078 * @reg: HW register to read from
4079 * @prev_stat_loaded: bool to specify if previous stats are loaded
4080 * @prev_stat: ptr to previous loaded stat value
4081 * @cur_stat: ptr to current stat value
4084 ice_stat_update32(struct ice_hw *hw, u32 reg, bool prev_stat_loaded,
4085 u64 *prev_stat, u64 *cur_stat)
4089 new_data = rd32(hw, reg);
4091 /* device stats are not reset at PFR, they likely will not be zeroed
4092 * when the driver starts. So save the first values read and use them as
4093 * offsets to be subtracted from the raw values in order to report stats
4094 * that count from zero.
4096 if (!prev_stat_loaded)
4097 *prev_stat = new_data;
4098 if (new_data >= *prev_stat)
4099 *cur_stat = new_data - *prev_stat;
4101 /* to manage the potential roll-over */
4102 *cur_stat = (new_data + BIT_ULL(32)) - *prev_stat;
4107 * ice_sched_query_elem - query element information from HW
4108 * @hw: pointer to the HW struct
4109 * @node_teid: node TEID to be queried
4110 * @buf: buffer to element information
4112 * This function queries HW element information
4115 ice_sched_query_elem(struct ice_hw *hw, u32 node_teid,
4116 struct ice_aqc_get_elem *buf)
4118 u16 buf_size, num_elem_ret = 0;
4119 enum ice_status status;
4121 buf_size = sizeof(*buf);
4122 ice_memset(buf, 0, buf_size, ICE_NONDMA_MEM);
4123 buf->generic[0].node_teid = CPU_TO_LE32(node_teid);
4124 status = ice_aq_query_sched_elems(hw, 1, buf, buf_size, &num_elem_ret,
4126 if (status != ICE_SUCCESS || num_elem_ret != 1)
4127 ice_debug(hw, ICE_DBG_SCHED, "query element failed\n");
4132 * ice_is_fw_in_rec_mode
4133 * @hw: pointer to the HW struct
4135 * This function returns true if fw is in recovery mode
4137 bool ice_is_fw_in_rec_mode(struct ice_hw *hw)
4141 /* check the current FW mode */
4142 reg = rd32(hw, GL_MNG_FWSM);
4143 return (reg & GL_MNG_FWSM_FW_MODES_M) > ICE_FW_MODE_DBG;