1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2001-2020 Intel Corporation
5 #include "ice_common.h"
7 #include "ice_adminq_cmd.h"
10 #include "ice_switch.h"
12 #define ICE_PF_RESET_WAIT_COUNT 300
15 * ice_set_mac_type - Sets MAC type
16 * @hw: pointer to the HW structure
18 * This function sets the MAC type of the adapter based on the
19 * vendor ID and device ID stored in the HW structure.
21 static enum ice_status ice_set_mac_type(struct ice_hw *hw)
23 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
25 if (hw->vendor_id != ICE_INTEL_VENDOR_ID)
26 return ICE_ERR_DEVICE_NOT_SUPPORTED;
28 switch (hw->device_id) {
29 case ICE_DEV_ID_E810C_BACKPLANE:
30 case ICE_DEV_ID_E810C_QSFP:
31 case ICE_DEV_ID_E810C_SFP:
32 case ICE_DEV_ID_E810_XXV_BACKPLANE:
33 case ICE_DEV_ID_E810_XXV_QSFP:
34 case ICE_DEV_ID_E810_XXV_SFP:
35 hw->mac_type = ICE_MAC_E810;
37 case ICE_DEV_ID_E822C_10G_BASE_T:
38 case ICE_DEV_ID_E822C_BACKPLANE:
39 case ICE_DEV_ID_E822C_QSFP:
40 case ICE_DEV_ID_E822C_SFP:
41 case ICE_DEV_ID_E822C_SGMII:
42 case ICE_DEV_ID_E822L_10G_BASE_T:
43 case ICE_DEV_ID_E822L_BACKPLANE:
44 case ICE_DEV_ID_E822L_SFP:
45 case ICE_DEV_ID_E822L_SGMII:
46 hw->mac_type = ICE_MAC_GENERIC;
49 hw->mac_type = ICE_MAC_UNKNOWN;
53 ice_debug(hw, ICE_DBG_INIT, "mac_type: %d\n", hw->mac_type);
58 * ice_clear_pf_cfg - Clear PF configuration
59 * @hw: pointer to the hardware structure
61 * Clears any existing PF configuration (VSIs, VSI lists, switch rules, port
62 * configuration, flow director filters, etc.).
64 enum ice_status ice_clear_pf_cfg(struct ice_hw *hw)
66 struct ice_aq_desc desc;
68 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pf_cfg);
70 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
74 * ice_aq_manage_mac_read - manage MAC address read command
75 * @hw: pointer to the HW struct
76 * @buf: a virtual buffer to hold the manage MAC read response
77 * @buf_size: Size of the virtual buffer
78 * @cd: pointer to command details structure or NULL
80 * This function is used to return per PF station MAC address (0x0107).
81 * NOTE: Upon successful completion of this command, MAC address information
82 * is returned in user specified buffer. Please interpret user specified
83 * buffer as "manage_mac_read" response.
84 * Response such as various MAC addresses are stored in HW struct (port.mac)
85 * ice_aq_discover_caps is expected to be called before this function is called.
87 static enum ice_status
88 ice_aq_manage_mac_read(struct ice_hw *hw, void *buf, u16 buf_size,
91 struct ice_aqc_manage_mac_read_resp *resp;
92 struct ice_aqc_manage_mac_read *cmd;
93 struct ice_aq_desc desc;
94 enum ice_status status;
98 cmd = &desc.params.mac_read;
100 if (buf_size < sizeof(*resp))
101 return ICE_ERR_BUF_TOO_SHORT;
103 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_read);
105 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);
109 resp = (struct ice_aqc_manage_mac_read_resp *)buf;
110 flags = LE16_TO_CPU(cmd->flags) & ICE_AQC_MAN_MAC_READ_M;
112 if (!(flags & ICE_AQC_MAN_MAC_LAN_ADDR_VALID)) {
113 ice_debug(hw, ICE_DBG_LAN, "got invalid MAC address\n");
117 /* A single port can report up to two (LAN and WoL) addresses */
118 for (i = 0; i < cmd->num_addr; i++)
119 if (resp[i].addr_type == ICE_AQC_MAN_MAC_ADDR_TYPE_LAN) {
120 ice_memcpy(hw->port_info->mac.lan_addr,
121 resp[i].mac_addr, ETH_ALEN,
123 ice_memcpy(hw->port_info->mac.perm_addr,
125 ETH_ALEN, ICE_DMA_TO_NONDMA);
132 * ice_aq_get_phy_caps - returns PHY capabilities
133 * @pi: port information structure
134 * @qual_mods: report qualified modules
135 * @report_mode: report mode capabilities
136 * @pcaps: structure for PHY capabilities to be filled
137 * @cd: pointer to command details structure or NULL
139 * Returns the various PHY capabilities supported on the Port (0x0600)
142 ice_aq_get_phy_caps(struct ice_port_info *pi, bool qual_mods, u8 report_mode,
143 struct ice_aqc_get_phy_caps_data *pcaps,
144 struct ice_sq_cd *cd)
146 struct ice_aqc_get_phy_caps *cmd;
147 u16 pcaps_size = sizeof(*pcaps);
148 struct ice_aq_desc desc;
149 enum ice_status status;
151 cmd = &desc.params.get_phy;
153 if (!pcaps || (report_mode & ~ICE_AQC_REPORT_MODE_M) || !pi)
154 return ICE_ERR_PARAM;
156 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_phy_caps);
159 cmd->param0 |= CPU_TO_LE16(ICE_AQC_GET_PHY_RQM);
161 cmd->param0 |= CPU_TO_LE16(report_mode);
162 status = ice_aq_send_cmd(pi->hw, &desc, pcaps, pcaps_size, cd);
164 if (status == ICE_SUCCESS && report_mode == ICE_AQC_REPORT_TOPO_CAP) {
165 pi->phy.phy_type_low = LE64_TO_CPU(pcaps->phy_type_low);
166 pi->phy.phy_type_high = LE64_TO_CPU(pcaps->phy_type_high);
173 * ice_aq_get_link_topo_handle - get link topology node return status
174 * @pi: port information structure
175 * @node_type: requested node type
176 * @cd: pointer to command details structure or NULL
178 * Get link topology node return status for specified node type (0x06E0)
180 * Node type cage can be used to determine if cage is present. If AQC
181 * returns error (ENOENT), then no cage present. If no cage present, then
182 * connection type is backplane or BASE-T.
184 static enum ice_status
185 ice_aq_get_link_topo_handle(struct ice_port_info *pi, u8 node_type,
186 struct ice_sq_cd *cd)
188 struct ice_aqc_get_link_topo *cmd;
189 struct ice_aq_desc desc;
191 cmd = &desc.params.get_link_topo;
193 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_topo);
195 cmd->addr.node_type_ctx = (ICE_AQC_LINK_TOPO_NODE_CTX_PORT <<
196 ICE_AQC_LINK_TOPO_NODE_CTX_S);
199 cmd->addr.node_type_ctx |= (ICE_AQC_LINK_TOPO_NODE_TYPE_M & node_type);
201 return ice_aq_send_cmd(pi->hw, &desc, NULL, 0, cd);
205 * ice_is_media_cage_present
206 * @pi: port information structure
208 * Returns true if media cage is present, else false. If no cage, then
209 * media type is backplane or BASE-T.
211 static bool ice_is_media_cage_present(struct ice_port_info *pi)
213 /* Node type cage can be used to determine if cage is present. If AQC
214 * returns error (ENOENT), then no cage present. If no cage present then
215 * connection type is backplane or BASE-T.
217 return !ice_aq_get_link_topo_handle(pi,
218 ICE_AQC_LINK_TOPO_NODE_TYPE_CAGE,
223 * ice_get_media_type - Gets media type
224 * @pi: port information structure
226 static enum ice_media_type ice_get_media_type(struct ice_port_info *pi)
228 struct ice_link_status *hw_link_info;
231 return ICE_MEDIA_UNKNOWN;
233 hw_link_info = &pi->phy.link_info;
234 if (hw_link_info->phy_type_low && hw_link_info->phy_type_high)
235 /* If more than one media type is selected, report unknown */
236 return ICE_MEDIA_UNKNOWN;
238 if (hw_link_info->phy_type_low) {
239 switch (hw_link_info->phy_type_low) {
240 case ICE_PHY_TYPE_LOW_1000BASE_SX:
241 case ICE_PHY_TYPE_LOW_1000BASE_LX:
242 case ICE_PHY_TYPE_LOW_10GBASE_SR:
243 case ICE_PHY_TYPE_LOW_10GBASE_LR:
244 case ICE_PHY_TYPE_LOW_10G_SFI_C2C:
245 case ICE_PHY_TYPE_LOW_25GBASE_SR:
246 case ICE_PHY_TYPE_LOW_25GBASE_LR:
247 case ICE_PHY_TYPE_LOW_40GBASE_SR4:
248 case ICE_PHY_TYPE_LOW_40GBASE_LR4:
249 case ICE_PHY_TYPE_LOW_50GBASE_SR2:
250 case ICE_PHY_TYPE_LOW_50GBASE_LR2:
251 case ICE_PHY_TYPE_LOW_50GBASE_SR:
252 case ICE_PHY_TYPE_LOW_50GBASE_FR:
253 case ICE_PHY_TYPE_LOW_50GBASE_LR:
254 case ICE_PHY_TYPE_LOW_100GBASE_SR4:
255 case ICE_PHY_TYPE_LOW_100GBASE_LR4:
256 case ICE_PHY_TYPE_LOW_100GBASE_SR2:
257 case ICE_PHY_TYPE_LOW_100GBASE_DR:
258 return ICE_MEDIA_FIBER;
259 case ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC:
260 case ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC:
261 case ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC:
262 case ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC:
263 case ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC:
264 case ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC:
265 case ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC:
266 case ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC:
267 return ICE_MEDIA_FIBER;
268 case ICE_PHY_TYPE_LOW_100BASE_TX:
269 case ICE_PHY_TYPE_LOW_1000BASE_T:
270 case ICE_PHY_TYPE_LOW_2500BASE_T:
271 case ICE_PHY_TYPE_LOW_5GBASE_T:
272 case ICE_PHY_TYPE_LOW_10GBASE_T:
273 case ICE_PHY_TYPE_LOW_25GBASE_T:
274 return ICE_MEDIA_BASET;
275 case ICE_PHY_TYPE_LOW_10G_SFI_DA:
276 case ICE_PHY_TYPE_LOW_25GBASE_CR:
277 case ICE_PHY_TYPE_LOW_25GBASE_CR_S:
278 case ICE_PHY_TYPE_LOW_25GBASE_CR1:
279 case ICE_PHY_TYPE_LOW_40GBASE_CR4:
280 case ICE_PHY_TYPE_LOW_50GBASE_CR2:
281 case ICE_PHY_TYPE_LOW_50GBASE_CP:
282 case ICE_PHY_TYPE_LOW_100GBASE_CR4:
283 case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4:
284 case ICE_PHY_TYPE_LOW_100GBASE_CP2:
286 case ICE_PHY_TYPE_LOW_25G_AUI_C2C:
287 case ICE_PHY_TYPE_LOW_40G_XLAUI:
288 case ICE_PHY_TYPE_LOW_50G_LAUI2:
289 case ICE_PHY_TYPE_LOW_50G_AUI2:
290 case ICE_PHY_TYPE_LOW_50G_AUI1:
291 case ICE_PHY_TYPE_LOW_100G_AUI4:
292 case ICE_PHY_TYPE_LOW_100G_CAUI4:
293 if (ice_is_media_cage_present(pi))
294 return ICE_MEDIA_AUI;
296 case ICE_PHY_TYPE_LOW_1000BASE_KX:
297 case ICE_PHY_TYPE_LOW_2500BASE_KX:
298 case ICE_PHY_TYPE_LOW_2500BASE_X:
299 case ICE_PHY_TYPE_LOW_5GBASE_KR:
300 case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1:
301 case ICE_PHY_TYPE_LOW_25GBASE_KR:
302 case ICE_PHY_TYPE_LOW_25GBASE_KR1:
303 case ICE_PHY_TYPE_LOW_25GBASE_KR_S:
304 case ICE_PHY_TYPE_LOW_40GBASE_KR4:
305 case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4:
306 case ICE_PHY_TYPE_LOW_50GBASE_KR2:
307 case ICE_PHY_TYPE_LOW_100GBASE_KR4:
308 case ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4:
309 return ICE_MEDIA_BACKPLANE;
312 switch (hw_link_info->phy_type_high) {
313 case ICE_PHY_TYPE_HIGH_100G_AUI2:
314 case ICE_PHY_TYPE_HIGH_100G_CAUI2:
315 if (ice_is_media_cage_present(pi))
316 return ICE_MEDIA_AUI;
318 case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4:
319 return ICE_MEDIA_BACKPLANE;
320 case ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC:
321 case ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC:
322 return ICE_MEDIA_FIBER;
325 return ICE_MEDIA_UNKNOWN;
329 * ice_aq_get_link_info
330 * @pi: port information structure
331 * @ena_lse: enable/disable LinkStatusEvent reporting
332 * @link: pointer to link status structure - optional
333 * @cd: pointer to command details structure or NULL
335 * Get Link Status (0x607). Returns the link status of the adapter.
338 ice_aq_get_link_info(struct ice_port_info *pi, bool ena_lse,
339 struct ice_link_status *link, struct ice_sq_cd *cd)
341 struct ice_aqc_get_link_status_data link_data = { 0 };
342 struct ice_aqc_get_link_status *resp;
343 struct ice_link_status *li_old, *li;
344 enum ice_media_type *hw_media_type;
345 struct ice_fc_info *hw_fc_info;
346 bool tx_pause, rx_pause;
347 struct ice_aq_desc desc;
348 enum ice_status status;
353 return ICE_ERR_PARAM;
355 li_old = &pi->phy.link_info_old;
356 hw_media_type = &pi->phy.media_type;
357 li = &pi->phy.link_info;
358 hw_fc_info = &pi->fc;
360 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_status);
361 cmd_flags = (ena_lse) ? ICE_AQ_LSE_ENA : ICE_AQ_LSE_DIS;
362 resp = &desc.params.get_link_status;
363 resp->cmd_flags = CPU_TO_LE16(cmd_flags);
364 resp->lport_num = pi->lport;
366 status = ice_aq_send_cmd(hw, &desc, &link_data, sizeof(link_data), cd);
368 if (status != ICE_SUCCESS)
371 /* save off old link status information */
374 /* update current link status information */
375 li->link_speed = LE16_TO_CPU(link_data.link_speed);
376 li->phy_type_low = LE64_TO_CPU(link_data.phy_type_low);
377 li->phy_type_high = LE64_TO_CPU(link_data.phy_type_high);
378 *hw_media_type = ice_get_media_type(pi);
379 li->link_info = link_data.link_info;
380 li->an_info = link_data.an_info;
381 li->ext_info = link_data.ext_info;
382 li->max_frame_size = LE16_TO_CPU(link_data.max_frame_size);
383 li->fec_info = link_data.cfg & ICE_AQ_FEC_MASK;
384 li->topo_media_conflict = link_data.topo_media_conflict;
385 li->pacing = link_data.cfg & (ICE_AQ_CFG_PACING_M |
386 ICE_AQ_CFG_PACING_TYPE_M);
389 tx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_TX);
390 rx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_RX);
391 if (tx_pause && rx_pause)
392 hw_fc_info->current_mode = ICE_FC_FULL;
394 hw_fc_info->current_mode = ICE_FC_TX_PAUSE;
396 hw_fc_info->current_mode = ICE_FC_RX_PAUSE;
398 hw_fc_info->current_mode = ICE_FC_NONE;
400 li->lse_ena = !!(resp->cmd_flags & CPU_TO_LE16(ICE_AQ_LSE_IS_ENABLED));
402 ice_debug(hw, ICE_DBG_LINK, "link_speed = 0x%x\n", li->link_speed);
403 ice_debug(hw, ICE_DBG_LINK, "phy_type_low = 0x%llx\n",
404 (unsigned long long)li->phy_type_low);
405 ice_debug(hw, ICE_DBG_LINK, "phy_type_high = 0x%llx\n",
406 (unsigned long long)li->phy_type_high);
407 ice_debug(hw, ICE_DBG_LINK, "media_type = 0x%x\n", *hw_media_type);
408 ice_debug(hw, ICE_DBG_LINK, "link_info = 0x%x\n", li->link_info);
409 ice_debug(hw, ICE_DBG_LINK, "an_info = 0x%x\n", li->an_info);
410 ice_debug(hw, ICE_DBG_LINK, "ext_info = 0x%x\n", li->ext_info);
411 ice_debug(hw, ICE_DBG_LINK, "lse_ena = 0x%x\n", li->lse_ena);
412 ice_debug(hw, ICE_DBG_LINK, "max_frame = 0x%x\n", li->max_frame_size);
413 ice_debug(hw, ICE_DBG_LINK, "pacing = 0x%x\n", li->pacing);
415 /* save link status information */
419 /* flag cleared so calling functions don't call AQ again */
420 pi->phy.get_link_info = false;
426 * ice_fill_tx_timer_and_fc_thresh
427 * @hw: pointer to the HW struct
428 * @cmd: pointer to MAC cfg structure
430 * Add Tx timer and FC refresh threshold info to Set MAC Config AQ command
434 ice_fill_tx_timer_and_fc_thresh(struct ice_hw *hw,
435 struct ice_aqc_set_mac_cfg *cmd)
437 u16 fc_thres_val, tx_timer_val;
440 /* We read back the transmit timer and fc threshold value of
441 * LFC. Thus, we will use index =
442 * PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX.
444 * Also, because we are opearating on transmit timer and fc
445 * threshold of LFC, we don't turn on any bit in tx_tmr_priority
447 #define IDX_OF_LFC PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX
449 /* Retrieve the transmit timer */
450 val = rd32(hw, PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(IDX_OF_LFC));
452 PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_HSEC_CTL_TX_PAUSE_QUANTA_M;
453 cmd->tx_tmr_value = CPU_TO_LE16(tx_timer_val);
455 /* Retrieve the fc threshold */
456 val = rd32(hw, PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(IDX_OF_LFC));
457 fc_thres_val = val & PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_M;
459 cmd->fc_refresh_threshold = CPU_TO_LE16(fc_thres_val);
464 * @hw: pointer to the HW struct
465 * @max_frame_size: Maximum Frame Size to be supported
466 * @cd: pointer to command details structure or NULL
468 * Set MAC configuration (0x0603)
471 ice_aq_set_mac_cfg(struct ice_hw *hw, u16 max_frame_size, struct ice_sq_cd *cd)
473 struct ice_aqc_set_mac_cfg *cmd;
474 struct ice_aq_desc desc;
476 cmd = &desc.params.set_mac_cfg;
478 if (max_frame_size == 0)
479 return ICE_ERR_PARAM;
481 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_mac_cfg);
483 cmd->max_frame_size = CPU_TO_LE16(max_frame_size);
485 ice_fill_tx_timer_and_fc_thresh(hw, cmd);
487 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
491 * ice_init_fltr_mgmt_struct - initializes filter management list and locks
492 * @hw: pointer to the HW struct
494 enum ice_status ice_init_fltr_mgmt_struct(struct ice_hw *hw)
496 struct ice_switch_info *sw;
497 enum ice_status status;
499 hw->switch_info = (struct ice_switch_info *)
500 ice_malloc(hw, sizeof(*hw->switch_info));
502 sw = hw->switch_info;
505 return ICE_ERR_NO_MEMORY;
507 INIT_LIST_HEAD(&sw->vsi_list_map_head);
509 status = ice_init_def_sw_recp(hw, &hw->switch_info->recp_list);
511 ice_free(hw, hw->switch_info);
518 * ice_cleanup_fltr_mgmt_single - clears single filter mngt struct
519 * @hw: pointer to the HW struct
520 * @sw: pointer to switch info struct for which function clears filters
523 ice_cleanup_fltr_mgmt_single(struct ice_hw *hw, struct ice_switch_info *sw)
525 struct ice_vsi_list_map_info *v_pos_map;
526 struct ice_vsi_list_map_info *v_tmp_map;
527 struct ice_sw_recipe *recps;
533 LIST_FOR_EACH_ENTRY_SAFE(v_pos_map, v_tmp_map, &sw->vsi_list_map_head,
534 ice_vsi_list_map_info, list_entry) {
535 LIST_DEL(&v_pos_map->list_entry);
536 ice_free(hw, v_pos_map);
538 recps = sw->recp_list;
539 for (i = 0; i < ICE_MAX_NUM_RECIPES; i++) {
540 struct ice_recp_grp_entry *rg_entry, *tmprg_entry;
542 recps[i].root_rid = i;
543 LIST_FOR_EACH_ENTRY_SAFE(rg_entry, tmprg_entry,
544 &recps[i].rg_list, ice_recp_grp_entry,
546 LIST_DEL(&rg_entry->l_entry);
547 ice_free(hw, rg_entry);
550 if (recps[i].adv_rule) {
551 struct ice_adv_fltr_mgmt_list_entry *tmp_entry;
552 struct ice_adv_fltr_mgmt_list_entry *lst_itr;
554 ice_destroy_lock(&recps[i].filt_rule_lock);
555 LIST_FOR_EACH_ENTRY_SAFE(lst_itr, tmp_entry,
556 &recps[i].filt_rules,
557 ice_adv_fltr_mgmt_list_entry,
559 LIST_DEL(&lst_itr->list_entry);
560 ice_free(hw, lst_itr->lkups);
561 ice_free(hw, lst_itr);
564 struct ice_fltr_mgmt_list_entry *lst_itr, *tmp_entry;
566 ice_destroy_lock(&recps[i].filt_rule_lock);
567 LIST_FOR_EACH_ENTRY_SAFE(lst_itr, tmp_entry,
568 &recps[i].filt_rules,
569 ice_fltr_mgmt_list_entry,
571 LIST_DEL(&lst_itr->list_entry);
572 ice_free(hw, lst_itr);
575 if (recps[i].root_buf)
576 ice_free(hw, recps[i].root_buf);
578 ice_rm_sw_replay_rule_info(hw, sw);
579 ice_free(hw, sw->recp_list);
584 * ice_cleanup_all_fltr_mgmt - cleanup filter management list and locks
585 * @hw: pointer to the HW struct
587 void ice_cleanup_fltr_mgmt_struct(struct ice_hw *hw)
589 ice_cleanup_fltr_mgmt_single(hw, hw->switch_info);
593 * ice_get_itr_intrl_gran
594 * @hw: pointer to the HW struct
596 * Determines the ITR/INTRL granularities based on the maximum aggregate
597 * bandwidth according to the device's configuration during power-on.
599 static void ice_get_itr_intrl_gran(struct ice_hw *hw)
601 u8 max_agg_bw = (rd32(hw, GL_PWR_MODE_CTL) &
602 GL_PWR_MODE_CTL_CAR_MAX_BW_M) >>
603 GL_PWR_MODE_CTL_CAR_MAX_BW_S;
605 switch (max_agg_bw) {
606 case ICE_MAX_AGG_BW_200G:
607 case ICE_MAX_AGG_BW_100G:
608 case ICE_MAX_AGG_BW_50G:
609 hw->itr_gran = ICE_ITR_GRAN_ABOVE_25;
610 hw->intrl_gran = ICE_INTRL_GRAN_ABOVE_25;
612 case ICE_MAX_AGG_BW_25G:
613 hw->itr_gran = ICE_ITR_GRAN_MAX_25;
614 hw->intrl_gran = ICE_INTRL_GRAN_MAX_25;
620 * ice_print_rollback_msg - print FW rollback message
621 * @hw: pointer to the hardware structure
623 void ice_print_rollback_msg(struct ice_hw *hw)
625 char nvm_str[ICE_NVM_VER_LEN] = { 0 };
626 struct ice_nvm_info *nvm = &hw->nvm;
627 struct ice_orom_info *orom;
631 SNPRINTF(nvm_str, sizeof(nvm_str), "%x.%02x 0x%x %d.%d.%d",
632 nvm->major_ver, nvm->minor_ver, nvm->eetrack, orom->major,
633 orom->build, orom->patch);
635 "Firmware rollback mode detected. Current version is NVM: %s, FW: %d.%d. Device may exhibit limited functionality. Refer to the Intel(R) Ethernet Adapters and Devices User Guide for details on firmware rollback mode\n",
636 nvm_str, hw->fw_maj_ver, hw->fw_min_ver);
640 * ice_init_hw - main hardware initialization routine
641 * @hw: pointer to the hardware structure
643 enum ice_status ice_init_hw(struct ice_hw *hw)
645 struct ice_aqc_get_phy_caps_data *pcaps;
646 enum ice_status status;
650 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
652 /* Set MAC type based on DeviceID */
653 status = ice_set_mac_type(hw);
657 hw->pf_id = (u8)(rd32(hw, PF_FUNC_RID) &
658 PF_FUNC_RID_FUNCTION_NUMBER_M) >>
659 PF_FUNC_RID_FUNCTION_NUMBER_S;
661 status = ice_reset(hw, ICE_RESET_PFR);
665 ice_get_itr_intrl_gran(hw);
667 status = ice_create_all_ctrlq(hw);
669 goto err_unroll_cqinit;
671 status = ice_init_nvm(hw);
673 goto err_unroll_cqinit;
675 if (ice_get_fw_mode(hw) == ICE_FW_MODE_ROLLBACK)
676 ice_print_rollback_msg(hw);
678 status = ice_clear_pf_cfg(hw);
680 goto err_unroll_cqinit;
682 /* Set bit to enable Flow Director filters */
683 wr32(hw, PFQF_FD_ENA, PFQF_FD_ENA_FD_ENA_M);
684 INIT_LIST_HEAD(&hw->fdir_list_head);
686 ice_clear_pxe_mode(hw);
688 status = ice_get_caps(hw);
690 goto err_unroll_cqinit;
692 hw->port_info = (struct ice_port_info *)
693 ice_malloc(hw, sizeof(*hw->port_info));
694 if (!hw->port_info) {
695 status = ICE_ERR_NO_MEMORY;
696 goto err_unroll_cqinit;
699 /* set the back pointer to HW */
700 hw->port_info->hw = hw;
702 /* Initialize port_info struct with switch configuration data */
703 status = ice_get_initial_sw_cfg(hw);
705 goto err_unroll_alloc;
708 /* Query the allocated resources for Tx scheduler */
709 status = ice_sched_query_res_alloc(hw);
711 ice_debug(hw, ICE_DBG_SCHED,
712 "Failed to get scheduler allocated resources\n");
713 goto err_unroll_alloc;
715 ice_sched_get_psm_clk_freq(hw);
717 /* Initialize port_info struct with scheduler data */
718 status = ice_sched_init_port(hw->port_info);
720 goto err_unroll_sched;
722 pcaps = (struct ice_aqc_get_phy_caps_data *)
723 ice_malloc(hw, sizeof(*pcaps));
725 status = ICE_ERR_NO_MEMORY;
726 goto err_unroll_sched;
729 /* Initialize port_info struct with PHY capabilities */
730 status = ice_aq_get_phy_caps(hw->port_info, false,
731 ICE_AQC_REPORT_TOPO_CAP, pcaps, NULL);
734 goto err_unroll_sched;
736 /* Initialize port_info struct with link information */
737 status = ice_aq_get_link_info(hw->port_info, false, NULL, NULL);
739 goto err_unroll_sched;
740 /* need a valid SW entry point to build a Tx tree */
741 if (!hw->sw_entry_point_layer) {
742 ice_debug(hw, ICE_DBG_SCHED, "invalid sw entry point\n");
743 status = ICE_ERR_CFG;
744 goto err_unroll_sched;
746 INIT_LIST_HEAD(&hw->agg_list);
747 /* Initialize max burst size */
748 if (!hw->max_burst_size)
749 ice_cfg_rl_burst_size(hw, ICE_SCHED_DFLT_BURST_SIZE);
750 status = ice_init_fltr_mgmt_struct(hw);
752 goto err_unroll_sched;
754 /* Get MAC information */
755 /* A single port can report up to two (LAN and WoL) addresses */
756 mac_buf = ice_calloc(hw, 2,
757 sizeof(struct ice_aqc_manage_mac_read_resp));
758 mac_buf_len = 2 * sizeof(struct ice_aqc_manage_mac_read_resp);
761 status = ICE_ERR_NO_MEMORY;
762 goto err_unroll_fltr_mgmt_struct;
765 status = ice_aq_manage_mac_read(hw, mac_buf, mac_buf_len, NULL);
766 ice_free(hw, mac_buf);
769 goto err_unroll_fltr_mgmt_struct;
770 /* enable jumbo frame support at MAC level */
771 status = ice_aq_set_mac_cfg(hw, ICE_AQ_SET_MAC_FRAME_SIZE_MAX, NULL);
773 goto err_unroll_fltr_mgmt_struct;
774 /* Obtain counter base index which would be used by flow director */
775 status = ice_alloc_fd_res_cntr(hw, &hw->fd_ctr_base);
777 goto err_unroll_fltr_mgmt_struct;
778 status = ice_init_hw_tbls(hw);
780 goto err_unroll_fltr_mgmt_struct;
781 ice_init_lock(&hw->tnl_lock);
784 err_unroll_fltr_mgmt_struct:
785 ice_cleanup_fltr_mgmt_struct(hw);
787 ice_sched_cleanup_all(hw);
789 ice_free(hw, hw->port_info);
790 hw->port_info = NULL;
792 ice_destroy_all_ctrlq(hw);
797 * ice_deinit_hw - unroll initialization operations done by ice_init_hw
798 * @hw: pointer to the hardware structure
800 * This should be called only during nominal operation, not as a result of
801 * ice_init_hw() failing since ice_init_hw() will take care of unrolling
802 * applicable initializations if it fails for any reason.
804 void ice_deinit_hw(struct ice_hw *hw)
806 ice_free_fd_res_cntr(hw, hw->fd_ctr_base);
807 ice_cleanup_fltr_mgmt_struct(hw);
809 ice_sched_cleanup_all(hw);
810 ice_sched_clear_agg(hw);
812 ice_free_hw_tbls(hw);
813 ice_destroy_lock(&hw->tnl_lock);
816 ice_free(hw, hw->port_info);
817 hw->port_info = NULL;
820 ice_destroy_all_ctrlq(hw);
822 /* Clear VSI contexts if not already cleared */
823 ice_clear_all_vsi_ctx(hw);
827 * ice_check_reset - Check to see if a global reset is complete
828 * @hw: pointer to the hardware structure
830 enum ice_status ice_check_reset(struct ice_hw *hw)
832 u32 cnt, reg = 0, grst_delay, uld_mask;
834 /* Poll for Device Active state in case a recent CORER, GLOBR,
835 * or EMPR has occurred. The grst delay value is in 100ms units.
836 * Add 1sec for outstanding AQ commands that can take a long time.
838 grst_delay = ((rd32(hw, GLGEN_RSTCTL) & GLGEN_RSTCTL_GRSTDEL_M) >>
839 GLGEN_RSTCTL_GRSTDEL_S) + 10;
841 for (cnt = 0; cnt < grst_delay; cnt++) {
842 ice_msec_delay(100, true);
843 reg = rd32(hw, GLGEN_RSTAT);
844 if (!(reg & GLGEN_RSTAT_DEVSTATE_M))
848 if (cnt == grst_delay) {
849 ice_debug(hw, ICE_DBG_INIT,
850 "Global reset polling failed to complete.\n");
851 return ICE_ERR_RESET_FAILED;
854 #define ICE_RESET_DONE_MASK (GLNVM_ULD_PCIER_DONE_M |\
855 GLNVM_ULD_PCIER_DONE_1_M |\
856 GLNVM_ULD_CORER_DONE_M |\
857 GLNVM_ULD_GLOBR_DONE_M |\
858 GLNVM_ULD_POR_DONE_M |\
859 GLNVM_ULD_POR_DONE_1_M |\
860 GLNVM_ULD_PCIER_DONE_2_M)
862 uld_mask = ICE_RESET_DONE_MASK;
864 /* Device is Active; check Global Reset processes are done */
865 for (cnt = 0; cnt < ICE_PF_RESET_WAIT_COUNT; cnt++) {
866 reg = rd32(hw, GLNVM_ULD) & uld_mask;
867 if (reg == uld_mask) {
868 ice_debug(hw, ICE_DBG_INIT,
869 "Global reset processes done. %d\n", cnt);
872 ice_msec_delay(10, true);
875 if (cnt == ICE_PF_RESET_WAIT_COUNT) {
876 ice_debug(hw, ICE_DBG_INIT,
877 "Wait for Reset Done timed out. GLNVM_ULD = 0x%x\n",
879 return ICE_ERR_RESET_FAILED;
886 * ice_pf_reset - Reset the PF
887 * @hw: pointer to the hardware structure
889 * If a global reset has been triggered, this function checks
890 * for its completion and then issues the PF reset
892 static enum ice_status ice_pf_reset(struct ice_hw *hw)
896 /* If at function entry a global reset was already in progress, i.e.
897 * state is not 'device active' or any of the reset done bits are not
898 * set in GLNVM_ULD, there is no need for a PF Reset; poll until the
899 * global reset is done.
901 if ((rd32(hw, GLGEN_RSTAT) & GLGEN_RSTAT_DEVSTATE_M) ||
902 (rd32(hw, GLNVM_ULD) & ICE_RESET_DONE_MASK) ^ ICE_RESET_DONE_MASK) {
903 /* poll on global reset currently in progress until done */
904 if (ice_check_reset(hw))
905 return ICE_ERR_RESET_FAILED;
911 reg = rd32(hw, PFGEN_CTRL);
913 wr32(hw, PFGEN_CTRL, (reg | PFGEN_CTRL_PFSWR_M));
915 for (cnt = 0; cnt < ICE_PF_RESET_WAIT_COUNT; cnt++) {
916 reg = rd32(hw, PFGEN_CTRL);
917 if (!(reg & PFGEN_CTRL_PFSWR_M))
920 ice_msec_delay(1, true);
923 if (cnt == ICE_PF_RESET_WAIT_COUNT) {
924 ice_debug(hw, ICE_DBG_INIT,
925 "PF reset polling failed to complete.\n");
926 return ICE_ERR_RESET_FAILED;
933 * ice_reset - Perform different types of reset
934 * @hw: pointer to the hardware structure
935 * @req: reset request
937 * This function triggers a reset as specified by the req parameter.
940 * If anything other than a PF reset is triggered, PXE mode is restored.
941 * This has to be cleared using ice_clear_pxe_mode again, once the AQ
942 * interface has been restored in the rebuild flow.
944 enum ice_status ice_reset(struct ice_hw *hw, enum ice_reset_req req)
950 return ice_pf_reset(hw);
951 case ICE_RESET_CORER:
952 ice_debug(hw, ICE_DBG_INIT, "CoreR requested\n");
953 val = GLGEN_RTRIG_CORER_M;
955 case ICE_RESET_GLOBR:
956 ice_debug(hw, ICE_DBG_INIT, "GlobalR requested\n");
957 val = GLGEN_RTRIG_GLOBR_M;
960 return ICE_ERR_PARAM;
963 val |= rd32(hw, GLGEN_RTRIG);
964 wr32(hw, GLGEN_RTRIG, val);
967 /* wait for the FW to be ready */
968 return ice_check_reset(hw);
972 * ice_copy_rxq_ctx_to_hw
973 * @hw: pointer to the hardware structure
974 * @ice_rxq_ctx: pointer to the rxq context
975 * @rxq_index: the index of the Rx queue
977 * Copies rxq context from dense structure to HW register space
979 static enum ice_status
980 ice_copy_rxq_ctx_to_hw(struct ice_hw *hw, u8 *ice_rxq_ctx, u32 rxq_index)
985 return ICE_ERR_BAD_PTR;
987 if (rxq_index > QRX_CTRL_MAX_INDEX)
988 return ICE_ERR_PARAM;
990 /* Copy each dword separately to HW */
991 for (i = 0; i < ICE_RXQ_CTX_SIZE_DWORDS; i++) {
992 wr32(hw, QRX_CONTEXT(i, rxq_index),
993 *((u32 *)(ice_rxq_ctx + (i * sizeof(u32)))));
995 ice_debug(hw, ICE_DBG_QCTX, "qrxdata[%d]: %08X\n", i,
996 *((u32 *)(ice_rxq_ctx + (i * sizeof(u32)))));
1002 /* LAN Rx Queue Context */
1003 static const struct ice_ctx_ele ice_rlan_ctx_info[] = {
1004 /* Field Width LSB */
1005 ICE_CTX_STORE(ice_rlan_ctx, head, 13, 0),
1006 ICE_CTX_STORE(ice_rlan_ctx, cpuid, 8, 13),
1007 ICE_CTX_STORE(ice_rlan_ctx, base, 57, 32),
1008 ICE_CTX_STORE(ice_rlan_ctx, qlen, 13, 89),
1009 ICE_CTX_STORE(ice_rlan_ctx, dbuf, 7, 102),
1010 ICE_CTX_STORE(ice_rlan_ctx, hbuf, 5, 109),
1011 ICE_CTX_STORE(ice_rlan_ctx, dtype, 2, 114),
1012 ICE_CTX_STORE(ice_rlan_ctx, dsize, 1, 116),
1013 ICE_CTX_STORE(ice_rlan_ctx, crcstrip, 1, 117),
1014 ICE_CTX_STORE(ice_rlan_ctx, l2tsel, 1, 119),
1015 ICE_CTX_STORE(ice_rlan_ctx, hsplit_0, 4, 120),
1016 ICE_CTX_STORE(ice_rlan_ctx, hsplit_1, 2, 124),
1017 ICE_CTX_STORE(ice_rlan_ctx, showiv, 1, 127),
1018 ICE_CTX_STORE(ice_rlan_ctx, rxmax, 14, 174),
1019 ICE_CTX_STORE(ice_rlan_ctx, tphrdesc_ena, 1, 193),
1020 ICE_CTX_STORE(ice_rlan_ctx, tphwdesc_ena, 1, 194),
1021 ICE_CTX_STORE(ice_rlan_ctx, tphdata_ena, 1, 195),
1022 ICE_CTX_STORE(ice_rlan_ctx, tphhead_ena, 1, 196),
1023 ICE_CTX_STORE(ice_rlan_ctx, lrxqthresh, 3, 198),
1024 ICE_CTX_STORE(ice_rlan_ctx, prefena, 1, 201),
1030 * @hw: pointer to the hardware structure
1031 * @rlan_ctx: pointer to the rxq context
1032 * @rxq_index: the index of the Rx queue
1034 * Converts rxq context from sparse to dense structure and then writes
1035 * it to HW register space and enables the hardware to prefetch descriptors
1036 * instead of only fetching them on demand
1039 ice_write_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx,
1042 u8 ctx_buf[ICE_RXQ_CTX_SZ] = { 0 };
1045 return ICE_ERR_BAD_PTR;
1047 rlan_ctx->prefena = 1;
1049 ice_set_ctx(hw, (u8 *)rlan_ctx, ctx_buf, ice_rlan_ctx_info);
1050 return ice_copy_rxq_ctx_to_hw(hw, ctx_buf, rxq_index);
1055 * @hw: pointer to the hardware structure
1056 * @rxq_index: the index of the Rx queue to clear
1058 * Clears rxq context in HW register space
1060 enum ice_status ice_clear_rxq_ctx(struct ice_hw *hw, u32 rxq_index)
1064 if (rxq_index > QRX_CTRL_MAX_INDEX)
1065 return ICE_ERR_PARAM;
1067 /* Clear each dword register separately */
1068 for (i = 0; i < ICE_RXQ_CTX_SIZE_DWORDS; i++)
1069 wr32(hw, QRX_CONTEXT(i, rxq_index), 0);
1074 /* LAN Tx Queue Context */
1075 const struct ice_ctx_ele ice_tlan_ctx_info[] = {
1076 /* Field Width LSB */
1077 ICE_CTX_STORE(ice_tlan_ctx, base, 57, 0),
1078 ICE_CTX_STORE(ice_tlan_ctx, port_num, 3, 57),
1079 ICE_CTX_STORE(ice_tlan_ctx, cgd_num, 5, 60),
1080 ICE_CTX_STORE(ice_tlan_ctx, pf_num, 3, 65),
1081 ICE_CTX_STORE(ice_tlan_ctx, vmvf_num, 10, 68),
1082 ICE_CTX_STORE(ice_tlan_ctx, vmvf_type, 2, 78),
1083 ICE_CTX_STORE(ice_tlan_ctx, src_vsi, 10, 80),
1084 ICE_CTX_STORE(ice_tlan_ctx, tsyn_ena, 1, 90),
1085 ICE_CTX_STORE(ice_tlan_ctx, internal_usage_flag, 1, 91),
1086 ICE_CTX_STORE(ice_tlan_ctx, alt_vlan, 1, 92),
1087 ICE_CTX_STORE(ice_tlan_ctx, cpuid, 8, 93),
1088 ICE_CTX_STORE(ice_tlan_ctx, wb_mode, 1, 101),
1089 ICE_CTX_STORE(ice_tlan_ctx, tphrd_desc, 1, 102),
1090 ICE_CTX_STORE(ice_tlan_ctx, tphrd, 1, 103),
1091 ICE_CTX_STORE(ice_tlan_ctx, tphwr_desc, 1, 104),
1092 ICE_CTX_STORE(ice_tlan_ctx, cmpq_id, 9, 105),
1093 ICE_CTX_STORE(ice_tlan_ctx, qnum_in_func, 14, 114),
1094 ICE_CTX_STORE(ice_tlan_ctx, itr_notification_mode, 1, 128),
1095 ICE_CTX_STORE(ice_tlan_ctx, adjust_prof_id, 6, 129),
1096 ICE_CTX_STORE(ice_tlan_ctx, qlen, 13, 135),
1097 ICE_CTX_STORE(ice_tlan_ctx, quanta_prof_idx, 4, 148),
1098 ICE_CTX_STORE(ice_tlan_ctx, tso_ena, 1, 152),
1099 ICE_CTX_STORE(ice_tlan_ctx, tso_qnum, 11, 153),
1100 ICE_CTX_STORE(ice_tlan_ctx, legacy_int, 1, 164),
1101 ICE_CTX_STORE(ice_tlan_ctx, drop_ena, 1, 165),
1102 ICE_CTX_STORE(ice_tlan_ctx, cache_prof_idx, 2, 166),
1103 ICE_CTX_STORE(ice_tlan_ctx, pkt_shaper_prof_idx, 3, 168),
1104 ICE_CTX_STORE(ice_tlan_ctx, int_q_state, 122, 171),
1109 * ice_copy_tx_cmpltnq_ctx_to_hw
1110 * @hw: pointer to the hardware structure
1111 * @ice_tx_cmpltnq_ctx: pointer to the Tx completion queue context
1112 * @tx_cmpltnq_index: the index of the completion queue
1114 * Copies Tx completion queue context from dense structure to HW register space
1116 static enum ice_status
1117 ice_copy_tx_cmpltnq_ctx_to_hw(struct ice_hw *hw, u8 *ice_tx_cmpltnq_ctx,
1118 u32 tx_cmpltnq_index)
1122 if (!ice_tx_cmpltnq_ctx)
1123 return ICE_ERR_BAD_PTR;
1125 if (tx_cmpltnq_index > GLTCLAN_CQ_CNTX0_MAX_INDEX)
1126 return ICE_ERR_PARAM;
1128 /* Copy each dword separately to HW */
1129 for (i = 0; i < ICE_TX_CMPLTNQ_CTX_SIZE_DWORDS; i++) {
1130 wr32(hw, GLTCLAN_CQ_CNTX(i, tx_cmpltnq_index),
1131 *((u32 *)(ice_tx_cmpltnq_ctx + (i * sizeof(u32)))));
1133 ice_debug(hw, ICE_DBG_QCTX, "cmpltnqdata[%d]: %08X\n", i,
1134 *((u32 *)(ice_tx_cmpltnq_ctx + (i * sizeof(u32)))));
1140 /* LAN Tx Completion Queue Context */
1141 static const struct ice_ctx_ele ice_tx_cmpltnq_ctx_info[] = {
1142 /* Field Width LSB */
1143 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, base, 57, 0),
1144 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, q_len, 18, 64),
1145 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, generation, 1, 96),
1146 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, wrt_ptr, 22, 97),
1147 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, pf_num, 3, 128),
1148 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, vmvf_num, 10, 131),
1149 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, vmvf_type, 2, 141),
1150 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, tph_desc_wr, 1, 160),
1151 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, cpuid, 8, 161),
1152 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, cmpltn_cache, 512, 192),
1157 * ice_write_tx_cmpltnq_ctx
1158 * @hw: pointer to the hardware structure
1159 * @tx_cmpltnq_ctx: pointer to the completion queue context
1160 * @tx_cmpltnq_index: the index of the completion queue
1162 * Converts completion queue context from sparse to dense structure and then
1163 * writes it to HW register space
1166 ice_write_tx_cmpltnq_ctx(struct ice_hw *hw,
1167 struct ice_tx_cmpltnq_ctx *tx_cmpltnq_ctx,
1168 u32 tx_cmpltnq_index)
1170 u8 ctx_buf[ICE_TX_CMPLTNQ_CTX_SIZE_DWORDS * sizeof(u32)] = { 0 };
1172 ice_set_ctx(hw, (u8 *)tx_cmpltnq_ctx, ctx_buf, ice_tx_cmpltnq_ctx_info);
1173 return ice_copy_tx_cmpltnq_ctx_to_hw(hw, ctx_buf, tx_cmpltnq_index);
1177 * ice_clear_tx_cmpltnq_ctx
1178 * @hw: pointer to the hardware structure
1179 * @tx_cmpltnq_index: the index of the completion queue to clear
1181 * Clears Tx completion queue context in HW register space
1184 ice_clear_tx_cmpltnq_ctx(struct ice_hw *hw, u32 tx_cmpltnq_index)
1188 if (tx_cmpltnq_index > GLTCLAN_CQ_CNTX0_MAX_INDEX)
1189 return ICE_ERR_PARAM;
1191 /* Clear each dword register separately */
1192 for (i = 0; i < ICE_TX_CMPLTNQ_CTX_SIZE_DWORDS; i++)
1193 wr32(hw, GLTCLAN_CQ_CNTX(i, tx_cmpltnq_index), 0);
1199 * ice_copy_tx_drbell_q_ctx_to_hw
1200 * @hw: pointer to the hardware structure
1201 * @ice_tx_drbell_q_ctx: pointer to the doorbell queue context
1202 * @tx_drbell_q_index: the index of the doorbell queue
1204 * Copies doorbell queue context from dense structure to HW register space
1206 static enum ice_status
1207 ice_copy_tx_drbell_q_ctx_to_hw(struct ice_hw *hw, u8 *ice_tx_drbell_q_ctx,
1208 u32 tx_drbell_q_index)
1212 if (!ice_tx_drbell_q_ctx)
1213 return ICE_ERR_BAD_PTR;
1215 if (tx_drbell_q_index > QTX_COMM_DBLQ_DBELL_MAX_INDEX)
1216 return ICE_ERR_PARAM;
1218 /* Copy each dword separately to HW */
1219 for (i = 0; i < ICE_TX_DRBELL_Q_CTX_SIZE_DWORDS; i++) {
1220 wr32(hw, QTX_COMM_DBLQ_CNTX(i, tx_drbell_q_index),
1221 *((u32 *)(ice_tx_drbell_q_ctx + (i * sizeof(u32)))));
1223 ice_debug(hw, ICE_DBG_QCTX, "tx_drbell_qdata[%d]: %08X\n", i,
1224 *((u32 *)(ice_tx_drbell_q_ctx + (i * sizeof(u32)))));
1230 /* LAN Tx Doorbell Queue Context info */
1231 static const struct ice_ctx_ele ice_tx_drbell_q_ctx_info[] = {
1232 /* Field Width LSB */
1233 ICE_CTX_STORE(ice_tx_drbell_q_ctx, base, 57, 0),
1234 ICE_CTX_STORE(ice_tx_drbell_q_ctx, ring_len, 13, 64),
1235 ICE_CTX_STORE(ice_tx_drbell_q_ctx, pf_num, 3, 80),
1236 ICE_CTX_STORE(ice_tx_drbell_q_ctx, vf_num, 8, 84),
1237 ICE_CTX_STORE(ice_tx_drbell_q_ctx, vmvf_type, 2, 94),
1238 ICE_CTX_STORE(ice_tx_drbell_q_ctx, cpuid, 8, 96),
1239 ICE_CTX_STORE(ice_tx_drbell_q_ctx, tph_desc_rd, 1, 104),
1240 ICE_CTX_STORE(ice_tx_drbell_q_ctx, tph_desc_wr, 1, 108),
1241 ICE_CTX_STORE(ice_tx_drbell_q_ctx, db_q_en, 1, 112),
1242 ICE_CTX_STORE(ice_tx_drbell_q_ctx, rd_head, 13, 128),
1243 ICE_CTX_STORE(ice_tx_drbell_q_ctx, rd_tail, 13, 144),
1248 * ice_write_tx_drbell_q_ctx
1249 * @hw: pointer to the hardware structure
1250 * @tx_drbell_q_ctx: pointer to the doorbell queue context
1251 * @tx_drbell_q_index: the index of the doorbell queue
1253 * Converts doorbell queue context from sparse to dense structure and then
1254 * writes it to HW register space
1257 ice_write_tx_drbell_q_ctx(struct ice_hw *hw,
1258 struct ice_tx_drbell_q_ctx *tx_drbell_q_ctx,
1259 u32 tx_drbell_q_index)
1261 u8 ctx_buf[ICE_TX_DRBELL_Q_CTX_SIZE_DWORDS * sizeof(u32)] = { 0 };
1263 ice_set_ctx(hw, (u8 *)tx_drbell_q_ctx, ctx_buf,
1264 ice_tx_drbell_q_ctx_info);
1265 return ice_copy_tx_drbell_q_ctx_to_hw(hw, ctx_buf, tx_drbell_q_index);
1269 * ice_clear_tx_drbell_q_ctx
1270 * @hw: pointer to the hardware structure
1271 * @tx_drbell_q_index: the index of the doorbell queue to clear
1273 * Clears doorbell queue context in HW register space
1276 ice_clear_tx_drbell_q_ctx(struct ice_hw *hw, u32 tx_drbell_q_index)
1280 if (tx_drbell_q_index > QTX_COMM_DBLQ_DBELL_MAX_INDEX)
1281 return ICE_ERR_PARAM;
1283 /* Clear each dword register separately */
1284 for (i = 0; i < ICE_TX_DRBELL_Q_CTX_SIZE_DWORDS; i++)
1285 wr32(hw, QTX_COMM_DBLQ_CNTX(i, tx_drbell_q_index), 0);
1290 /* FW Admin Queue command wrappers */
1293 * ice_aq_send_cmd - send FW Admin Queue command to FW Admin Queue
1294 * @hw: pointer to the HW struct
1295 * @desc: descriptor describing the command
1296 * @buf: buffer to use for indirect commands (NULL for direct commands)
1297 * @buf_size: size of buffer for indirect commands (0 for direct commands)
1298 * @cd: pointer to command details structure
1300 * Helper function to send FW Admin Queue commands to the FW Admin Queue.
1303 ice_aq_send_cmd(struct ice_hw *hw, struct ice_aq_desc *desc, void *buf,
1304 u16 buf_size, struct ice_sq_cd *cd)
1306 if (hw->aq_send_cmd_fn) {
1307 enum ice_status status = ICE_ERR_NOT_READY;
1308 u16 retval = ICE_AQ_RC_OK;
1310 ice_acquire_lock(&hw->adminq.sq_lock);
1311 if (!hw->aq_send_cmd_fn(hw->aq_send_cmd_param, desc,
1313 retval = LE16_TO_CPU(desc->retval);
1314 /* strip off FW internal code */
1317 if (retval == ICE_AQ_RC_OK)
1318 status = ICE_SUCCESS;
1320 status = ICE_ERR_AQ_ERROR;
1323 hw->adminq.sq_last_status = (enum ice_aq_err)retval;
1324 ice_release_lock(&hw->adminq.sq_lock);
1328 return ice_sq_send_cmd(hw, &hw->adminq, desc, buf, buf_size, cd);
1333 * @hw: pointer to the HW struct
1334 * @cd: pointer to command details structure or NULL
1336 * Get the firmware version (0x0001) from the admin queue commands
1338 enum ice_status ice_aq_get_fw_ver(struct ice_hw *hw, struct ice_sq_cd *cd)
1340 struct ice_aqc_get_ver *resp;
1341 struct ice_aq_desc desc;
1342 enum ice_status status;
1344 resp = &desc.params.get_ver;
1346 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_ver);
1348 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
1351 hw->fw_branch = resp->fw_branch;
1352 hw->fw_maj_ver = resp->fw_major;
1353 hw->fw_min_ver = resp->fw_minor;
1354 hw->fw_patch = resp->fw_patch;
1355 hw->fw_build = LE32_TO_CPU(resp->fw_build);
1356 hw->api_branch = resp->api_branch;
1357 hw->api_maj_ver = resp->api_major;
1358 hw->api_min_ver = resp->api_minor;
1359 hw->api_patch = resp->api_patch;
1366 * ice_aq_send_driver_ver
1367 * @hw: pointer to the HW struct
1368 * @dv: driver's major, minor version
1369 * @cd: pointer to command details structure or NULL
1371 * Send the driver version (0x0002) to the firmware
1374 ice_aq_send_driver_ver(struct ice_hw *hw, struct ice_driver_ver *dv,
1375 struct ice_sq_cd *cd)
1377 struct ice_aqc_driver_ver *cmd;
1378 struct ice_aq_desc desc;
1381 cmd = &desc.params.driver_ver;
1384 return ICE_ERR_PARAM;
1386 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_driver_ver);
1388 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
1389 cmd->major_ver = dv->major_ver;
1390 cmd->minor_ver = dv->minor_ver;
1391 cmd->build_ver = dv->build_ver;
1392 cmd->subbuild_ver = dv->subbuild_ver;
1395 while (len < sizeof(dv->driver_string) &&
1396 IS_ASCII(dv->driver_string[len]) && dv->driver_string[len])
1399 return ice_aq_send_cmd(hw, &desc, dv->driver_string, len, cd);
1404 * @hw: pointer to the HW struct
1405 * @unloading: is the driver unloading itself
1407 * Tell the Firmware that we're shutting down the AdminQ and whether
1408 * or not the driver is unloading as well (0x0003).
1410 enum ice_status ice_aq_q_shutdown(struct ice_hw *hw, bool unloading)
1412 struct ice_aqc_q_shutdown *cmd;
1413 struct ice_aq_desc desc;
1415 cmd = &desc.params.q_shutdown;
1417 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_q_shutdown);
1420 cmd->driver_unloading = ICE_AQC_DRIVER_UNLOADING;
1422 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
1427 * @hw: pointer to the HW struct
1429 * @access: access type
1430 * @sdp_number: resource number
1431 * @timeout: the maximum time in ms that the driver may hold the resource
1432 * @cd: pointer to command details structure or NULL
1434 * Requests common resource using the admin queue commands (0x0008).
1435 * When attempting to acquire the Global Config Lock, the driver can
1436 * learn of three states:
1437 * 1) ICE_SUCCESS - acquired lock, and can perform download package
1438 * 2) ICE_ERR_AQ_ERROR - did not get lock, driver should fail to load
1439 * 3) ICE_ERR_AQ_NO_WORK - did not get lock, but another driver has
1440 * successfully downloaded the package; the driver does
1441 * not have to download the package and can continue
1444 * Note that if the caller is in an acquire lock, perform action, release lock
1445 * phase of operation, it is possible that the FW may detect a timeout and issue
1446 * a CORER. In this case, the driver will receive a CORER interrupt and will
1447 * have to determine its cause. The calling thread that is handling this flow
1448 * will likely get an error propagated back to it indicating the Download
1449 * Package, Update Package or the Release Resource AQ commands timed out.
1451 static enum ice_status
1452 ice_aq_req_res(struct ice_hw *hw, enum ice_aq_res_ids res,
1453 enum ice_aq_res_access_type access, u8 sdp_number, u32 *timeout,
1454 struct ice_sq_cd *cd)
1456 struct ice_aqc_req_res *cmd_resp;
1457 struct ice_aq_desc desc;
1458 enum ice_status status;
1460 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
1462 cmd_resp = &desc.params.res_owner;
1464 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_req_res);
1466 cmd_resp->res_id = CPU_TO_LE16(res);
1467 cmd_resp->access_type = CPU_TO_LE16(access);
1468 cmd_resp->res_number = CPU_TO_LE32(sdp_number);
1469 cmd_resp->timeout = CPU_TO_LE32(*timeout);
1472 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
1474 /* The completion specifies the maximum time in ms that the driver
1475 * may hold the resource in the Timeout field.
1478 /* Global config lock response utilizes an additional status field.
1480 * If the Global config lock resource is held by some other driver, the
1481 * command completes with ICE_AQ_RES_GLBL_IN_PROG in the status field
1482 * and the timeout field indicates the maximum time the current owner
1483 * of the resource has to free it.
1485 if (res == ICE_GLOBAL_CFG_LOCK_RES_ID) {
1486 if (LE16_TO_CPU(cmd_resp->status) == ICE_AQ_RES_GLBL_SUCCESS) {
1487 *timeout = LE32_TO_CPU(cmd_resp->timeout);
1489 } else if (LE16_TO_CPU(cmd_resp->status) ==
1490 ICE_AQ_RES_GLBL_IN_PROG) {
1491 *timeout = LE32_TO_CPU(cmd_resp->timeout);
1492 return ICE_ERR_AQ_ERROR;
1493 } else if (LE16_TO_CPU(cmd_resp->status) ==
1494 ICE_AQ_RES_GLBL_DONE) {
1495 return ICE_ERR_AQ_NO_WORK;
1498 /* invalid FW response, force a timeout immediately */
1500 return ICE_ERR_AQ_ERROR;
1503 /* If the resource is held by some other driver, the command completes
1504 * with a busy return value and the timeout field indicates the maximum
1505 * time the current owner of the resource has to free it.
1507 if (!status || hw->adminq.sq_last_status == ICE_AQ_RC_EBUSY)
1508 *timeout = LE32_TO_CPU(cmd_resp->timeout);
1514 * ice_aq_release_res
1515 * @hw: pointer to the HW struct
1517 * @sdp_number: resource number
1518 * @cd: pointer to command details structure or NULL
1520 * release common resource using the admin queue commands (0x0009)
1522 static enum ice_status
1523 ice_aq_release_res(struct ice_hw *hw, enum ice_aq_res_ids res, u8 sdp_number,
1524 struct ice_sq_cd *cd)
1526 struct ice_aqc_req_res *cmd;
1527 struct ice_aq_desc desc;
1529 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
1531 cmd = &desc.params.res_owner;
1533 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_release_res);
1535 cmd->res_id = CPU_TO_LE16(res);
1536 cmd->res_number = CPU_TO_LE32(sdp_number);
1538 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
1543 * @hw: pointer to the HW structure
1545 * @access: access type (read or write)
1546 * @timeout: timeout in milliseconds
1548 * This function will attempt to acquire the ownership of a resource.
1551 ice_acquire_res(struct ice_hw *hw, enum ice_aq_res_ids res,
1552 enum ice_aq_res_access_type access, u32 timeout)
1554 #define ICE_RES_POLLING_DELAY_MS 10
1555 u32 delay = ICE_RES_POLLING_DELAY_MS;
1556 u32 time_left = timeout;
1557 enum ice_status status;
1559 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
1561 status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL);
1563 /* A return code of ICE_ERR_AQ_NO_WORK means that another driver has
1564 * previously acquired the resource and performed any necessary updates;
1565 * in this case the caller does not obtain the resource and has no
1566 * further work to do.
1568 if (status == ICE_ERR_AQ_NO_WORK)
1569 goto ice_acquire_res_exit;
1572 ice_debug(hw, ICE_DBG_RES,
1573 "resource %d acquire type %d failed.\n", res, access);
1575 /* If necessary, poll until the current lock owner timeouts */
1576 timeout = time_left;
1577 while (status && timeout && time_left) {
1578 ice_msec_delay(delay, true);
1579 timeout = (timeout > delay) ? timeout - delay : 0;
1580 status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL);
1582 if (status == ICE_ERR_AQ_NO_WORK)
1583 /* lock free, but no work to do */
1590 if (status && status != ICE_ERR_AQ_NO_WORK)
1591 ice_debug(hw, ICE_DBG_RES, "resource acquire timed out.\n");
1593 ice_acquire_res_exit:
1594 if (status == ICE_ERR_AQ_NO_WORK) {
1595 if (access == ICE_RES_WRITE)
1596 ice_debug(hw, ICE_DBG_RES,
1597 "resource indicates no work to do.\n");
1599 ice_debug(hw, ICE_DBG_RES,
1600 "Warning: ICE_ERR_AQ_NO_WORK not expected\n");
1607 * @hw: pointer to the HW structure
1610 * This function will release a resource using the proper Admin Command.
1612 void ice_release_res(struct ice_hw *hw, enum ice_aq_res_ids res)
1614 enum ice_status status;
1615 u32 total_delay = 0;
1617 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
1619 status = ice_aq_release_res(hw, res, 0, NULL);
1621 /* there are some rare cases when trying to release the resource
1622 * results in an admin queue timeout, so handle them correctly
1624 while ((status == ICE_ERR_AQ_TIMEOUT) &&
1625 (total_delay < hw->adminq.sq_cmd_timeout)) {
1626 ice_msec_delay(1, true);
1627 status = ice_aq_release_res(hw, res, 0, NULL);
1633 * ice_aq_alloc_free_res - command to allocate/free resources
1634 * @hw: pointer to the HW struct
1635 * @num_entries: number of resource entries in buffer
1636 * @buf: Indirect buffer to hold data parameters and response
1637 * @buf_size: size of buffer for indirect commands
1638 * @opc: pass in the command opcode
1639 * @cd: pointer to command details structure or NULL
1641 * Helper function to allocate/free resources using the admin queue commands
1644 ice_aq_alloc_free_res(struct ice_hw *hw, u16 num_entries,
1645 struct ice_aqc_alloc_free_res_elem *buf, u16 buf_size,
1646 enum ice_adminq_opc opc, struct ice_sq_cd *cd)
1648 struct ice_aqc_alloc_free_res_cmd *cmd;
1649 struct ice_aq_desc desc;
1651 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
1653 cmd = &desc.params.sw_res_ctrl;
1656 return ICE_ERR_PARAM;
1658 if (buf_size < (num_entries * sizeof(buf->elem[0])))
1659 return ICE_ERR_PARAM;
1661 ice_fill_dflt_direct_cmd_desc(&desc, opc);
1663 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
1665 cmd->num_entries = CPU_TO_LE16(num_entries);
1667 return ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);
1671 * ice_alloc_hw_res - allocate resource
1672 * @hw: pointer to the HW struct
1673 * @type: type of resource
1674 * @num: number of resources to allocate
1675 * @btm: allocate from bottom
1676 * @res: pointer to array that will receive the resources
1679 ice_alloc_hw_res(struct ice_hw *hw, u16 type, u16 num, bool btm, u16 *res)
1681 struct ice_aqc_alloc_free_res_elem *buf;
1682 enum ice_status status;
1685 buf_len = ice_struct_size(buf, elem, num - 1);
1686 buf = (struct ice_aqc_alloc_free_res_elem *)
1687 ice_malloc(hw, buf_len);
1689 return ICE_ERR_NO_MEMORY;
1691 /* Prepare buffer to allocate resource. */
1692 buf->num_elems = CPU_TO_LE16(num);
1693 buf->res_type = CPU_TO_LE16(type | ICE_AQC_RES_TYPE_FLAG_DEDICATED |
1694 ICE_AQC_RES_TYPE_FLAG_IGNORE_INDEX);
1696 buf->res_type |= CPU_TO_LE16(ICE_AQC_RES_TYPE_FLAG_SCAN_BOTTOM);
1698 status = ice_aq_alloc_free_res(hw, 1, buf, buf_len,
1699 ice_aqc_opc_alloc_res, NULL);
1701 goto ice_alloc_res_exit;
1703 ice_memcpy(res, buf->elem, sizeof(buf->elem) * num,
1704 ICE_NONDMA_TO_NONDMA);
1712 * ice_free_hw_res - free allocated HW resource
1713 * @hw: pointer to the HW struct
1714 * @type: type of resource to free
1715 * @num: number of resources
1716 * @res: pointer to array that contains the resources to free
1719 ice_free_hw_res(struct ice_hw *hw, u16 type, u16 num, u16 *res)
1721 struct ice_aqc_alloc_free_res_elem *buf;
1722 enum ice_status status;
1725 buf_len = ice_struct_size(buf, elem, num - 1);
1726 buf = (struct ice_aqc_alloc_free_res_elem *)ice_malloc(hw, buf_len);
1728 return ICE_ERR_NO_MEMORY;
1730 /* Prepare buffer to free resource. */
1731 buf->num_elems = CPU_TO_LE16(num);
1732 buf->res_type = CPU_TO_LE16(type);
1733 ice_memcpy(buf->elem, res, sizeof(buf->elem) * num,
1734 ICE_NONDMA_TO_NONDMA);
1736 status = ice_aq_alloc_free_res(hw, num, buf, buf_len,
1737 ice_aqc_opc_free_res, NULL);
1739 ice_debug(hw, ICE_DBG_SW, "CQ CMD Buffer:\n");
1746 * ice_get_num_per_func - determine number of resources per PF
1747 * @hw: pointer to the HW structure
1748 * @max: value to be evenly split between each PF
1750 * Determine the number of valid functions by going through the bitmap returned
1751 * from parsing capabilities and use this to calculate the number of resources
1752 * per PF based on the max value passed in.
1754 static u32 ice_get_num_per_func(struct ice_hw *hw, u32 max)
1758 #define ICE_CAPS_VALID_FUNCS_M 0xFF
1759 funcs = ice_hweight8(hw->dev_caps.common_cap.valid_functions &
1760 ICE_CAPS_VALID_FUNCS_M);
1769 * ice_parse_caps - parse function/device capabilities
1770 * @hw: pointer to the HW struct
1771 * @buf: pointer to a buffer containing function/device capability records
1772 * @cap_count: number of capability records in the list
1773 * @opc: type of capabilities list to parse
1775 * Helper function to parse function(0x000a)/device(0x000b) capabilities list.
1778 ice_parse_caps(struct ice_hw *hw, void *buf, u32 cap_count,
1779 enum ice_adminq_opc opc)
1781 struct ice_aqc_list_caps_elem *cap_resp;
1782 struct ice_hw_func_caps *func_p = NULL;
1783 struct ice_hw_dev_caps *dev_p = NULL;
1784 struct ice_hw_common_caps *caps;
1791 cap_resp = (struct ice_aqc_list_caps_elem *)buf;
1793 if (opc == ice_aqc_opc_list_dev_caps) {
1794 dev_p = &hw->dev_caps;
1795 caps = &dev_p->common_cap;
1797 } else if (opc == ice_aqc_opc_list_func_caps) {
1798 func_p = &hw->func_caps;
1799 caps = &func_p->common_cap;
1800 prefix = "func cap";
1802 ice_debug(hw, ICE_DBG_INIT, "wrong opcode\n");
1806 for (i = 0; caps && i < cap_count; i++, cap_resp++) {
1807 u32 logical_id = LE32_TO_CPU(cap_resp->logical_id);
1808 u32 phys_id = LE32_TO_CPU(cap_resp->phys_id);
1809 u32 number = LE32_TO_CPU(cap_resp->number);
1810 u16 cap = LE16_TO_CPU(cap_resp->cap);
1813 case ICE_AQC_CAPS_VALID_FUNCTIONS:
1814 caps->valid_functions = number;
1815 ice_debug(hw, ICE_DBG_INIT,
1816 "%s: valid_functions (bitmap) = %d\n", prefix,
1817 caps->valid_functions);
1819 /* store func count for resource management purposes */
1821 dev_p->num_funcs = ice_hweight32(number);
1823 case ICE_AQC_CAPS_VSI:
1825 dev_p->num_vsi_allocd_to_host = number;
1826 ice_debug(hw, ICE_DBG_INIT,
1827 "%s: num_vsi_allocd_to_host = %d\n",
1829 dev_p->num_vsi_allocd_to_host);
1830 } else if (func_p) {
1831 func_p->guar_num_vsi =
1832 ice_get_num_per_func(hw, ICE_MAX_VSI);
1833 ice_debug(hw, ICE_DBG_INIT,
1834 "%s: guar_num_vsi (fw) = %d\n",
1836 ice_debug(hw, ICE_DBG_INIT,
1837 "%s: guar_num_vsi = %d\n",
1838 prefix, func_p->guar_num_vsi);
1841 case ICE_AQC_CAPS_DCB:
1842 caps->dcb = (number == 1);
1843 caps->active_tc_bitmap = logical_id;
1844 caps->maxtc = phys_id;
1845 ice_debug(hw, ICE_DBG_INIT,
1846 "%s: dcb = %d\n", prefix, caps->dcb);
1847 ice_debug(hw, ICE_DBG_INIT,
1848 "%s: active_tc_bitmap = %d\n", prefix,
1849 caps->active_tc_bitmap);
1850 ice_debug(hw, ICE_DBG_INIT,
1851 "%s: maxtc = %d\n", prefix, caps->maxtc);
1853 case ICE_AQC_CAPS_RSS:
1854 caps->rss_table_size = number;
1855 caps->rss_table_entry_width = logical_id;
1856 ice_debug(hw, ICE_DBG_INIT,
1857 "%s: rss_table_size = %d\n", prefix,
1858 caps->rss_table_size);
1859 ice_debug(hw, ICE_DBG_INIT,
1860 "%s: rss_table_entry_width = %d\n", prefix,
1861 caps->rss_table_entry_width);
1863 case ICE_AQC_CAPS_RXQS:
1864 caps->num_rxq = number;
1865 caps->rxq_first_id = phys_id;
1866 ice_debug(hw, ICE_DBG_INIT,
1867 "%s: num_rxq = %d\n", prefix,
1869 ice_debug(hw, ICE_DBG_INIT,
1870 "%s: rxq_first_id = %d\n", prefix,
1871 caps->rxq_first_id);
1873 case ICE_AQC_CAPS_TXQS:
1874 caps->num_txq = number;
1875 caps->txq_first_id = phys_id;
1876 ice_debug(hw, ICE_DBG_INIT,
1877 "%s: num_txq = %d\n", prefix,
1879 ice_debug(hw, ICE_DBG_INIT,
1880 "%s: txq_first_id = %d\n", prefix,
1881 caps->txq_first_id);
1883 case ICE_AQC_CAPS_MSIX:
1884 caps->num_msix_vectors = number;
1885 caps->msix_vector_first_id = phys_id;
1886 ice_debug(hw, ICE_DBG_INIT,
1887 "%s: num_msix_vectors = %d\n", prefix,
1888 caps->num_msix_vectors);
1889 ice_debug(hw, ICE_DBG_INIT,
1890 "%s: msix_vector_first_id = %d\n", prefix,
1891 caps->msix_vector_first_id);
1893 case ICE_AQC_CAPS_FD:
1895 dev_p->num_flow_director_fltr = number;
1896 ice_debug(hw, ICE_DBG_INIT,
1897 "%s: num_flow_director_fltr = %d\n",
1899 dev_p->num_flow_director_fltr);
1904 if (hw->dcf_enabled)
1906 reg_val = rd32(hw, GLQF_FD_SIZE);
1907 val = (reg_val & GLQF_FD_SIZE_FD_GSIZE_M) >>
1908 GLQF_FD_SIZE_FD_GSIZE_S;
1909 func_p->fd_fltr_guar =
1910 ice_get_num_per_func(hw, val);
1911 val = (reg_val & GLQF_FD_SIZE_FD_BSIZE_M) >>
1912 GLQF_FD_SIZE_FD_BSIZE_S;
1913 func_p->fd_fltr_best_effort = val;
1914 ice_debug(hw, ICE_DBG_INIT,
1915 "%s: fd_fltr_guar = %d\n",
1916 prefix, func_p->fd_fltr_guar);
1917 ice_debug(hw, ICE_DBG_INIT,
1918 "%s: fd_fltr_best_effort = %d\n",
1919 prefix, func_p->fd_fltr_best_effort);
1922 case ICE_AQC_CAPS_MAX_MTU:
1923 caps->max_mtu = number;
1924 ice_debug(hw, ICE_DBG_INIT, "%s: max_mtu = %d\n",
1925 prefix, caps->max_mtu);
1928 ice_debug(hw, ICE_DBG_INIT,
1929 "%s: unknown capability[%d]: 0x%x\n", prefix,
1935 /* Re-calculate capabilities that are dependent on the number of
1936 * physical ports; i.e. some features are not supported or function
1937 * differently on devices with more than 4 ports.
1939 if (hw->dev_caps.num_funcs > 4) {
1940 /* Max 4 TCs per port */
1942 ice_debug(hw, ICE_DBG_INIT,
1943 "%s: maxtc = %d (based on #ports)\n", prefix,
1949 * ice_aq_discover_caps - query function/device capabilities
1950 * @hw: pointer to the HW struct
1951 * @buf: a virtual buffer to hold the capabilities
1952 * @buf_size: Size of the virtual buffer
1953 * @cap_count: cap count needed if AQ err==ENOMEM
1954 * @opc: capabilities type to discover - pass in the command opcode
1955 * @cd: pointer to command details structure or NULL
1957 * Get the function(0x000a)/device(0x000b) capabilities description from
1960 static enum ice_status
1961 ice_aq_discover_caps(struct ice_hw *hw, void *buf, u16 buf_size, u32 *cap_count,
1962 enum ice_adminq_opc opc, struct ice_sq_cd *cd)
1964 struct ice_aqc_list_caps *cmd;
1965 struct ice_aq_desc desc;
1966 enum ice_status status;
1968 cmd = &desc.params.get_cap;
1970 if (opc != ice_aqc_opc_list_func_caps &&
1971 opc != ice_aqc_opc_list_dev_caps)
1972 return ICE_ERR_PARAM;
1974 ice_fill_dflt_direct_cmd_desc(&desc, opc);
1976 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);
1978 ice_parse_caps(hw, buf, LE32_TO_CPU(cmd->count), opc);
1979 else if (hw->adminq.sq_last_status == ICE_AQ_RC_ENOMEM)
1980 *cap_count = LE32_TO_CPU(cmd->count);
1985 * ice_discover_caps - get info about the HW
1986 * @hw: pointer to the hardware structure
1987 * @opc: capabilities type to discover - pass in the command opcode
1989 static enum ice_status
1990 ice_discover_caps(struct ice_hw *hw, enum ice_adminq_opc opc)
1992 enum ice_status status;
1997 /* The driver doesn't know how many capabilities the device will return
1998 * so the buffer size required isn't known ahead of time. The driver
1999 * starts with cbuf_len and if this turns out to be insufficient, the
2000 * device returns ICE_AQ_RC_ENOMEM and also the cap_count it needs.
2001 * The driver then allocates the buffer based on the count and retries
2002 * the operation. So it follows that the retry count is 2.
2004 #define ICE_GET_CAP_BUF_COUNT 40
2005 #define ICE_GET_CAP_RETRY_COUNT 2
2007 cap_count = ICE_GET_CAP_BUF_COUNT;
2008 retries = ICE_GET_CAP_RETRY_COUNT;
2013 cbuf_len = (u16)(cap_count *
2014 sizeof(struct ice_aqc_list_caps_elem));
2015 cbuf = ice_malloc(hw, cbuf_len);
2017 return ICE_ERR_NO_MEMORY;
2019 status = ice_aq_discover_caps(hw, cbuf, cbuf_len, &cap_count,
2023 if (!status || hw->adminq.sq_last_status != ICE_AQ_RC_ENOMEM)
2026 /* If ENOMEM is returned, try again with bigger buffer */
2027 } while (--retries);
2033 * ice_set_safe_mode_caps - Override dev/func capabilities when in safe mode
2034 * @hw: pointer to the hardware structure
2036 void ice_set_safe_mode_caps(struct ice_hw *hw)
2038 struct ice_hw_func_caps *func_caps = &hw->func_caps;
2039 struct ice_hw_dev_caps *dev_caps = &hw->dev_caps;
2040 u32 valid_func, rxq_first_id, txq_first_id;
2041 u32 msix_vector_first_id, max_mtu;
2044 /* cache some func_caps values that should be restored after memset */
2045 valid_func = func_caps->common_cap.valid_functions;
2046 txq_first_id = func_caps->common_cap.txq_first_id;
2047 rxq_first_id = func_caps->common_cap.rxq_first_id;
2048 msix_vector_first_id = func_caps->common_cap.msix_vector_first_id;
2049 max_mtu = func_caps->common_cap.max_mtu;
2051 /* unset func capabilities */
2052 memset(func_caps, 0, sizeof(*func_caps));
2054 /* restore cached values */
2055 func_caps->common_cap.valid_functions = valid_func;
2056 func_caps->common_cap.txq_first_id = txq_first_id;
2057 func_caps->common_cap.rxq_first_id = rxq_first_id;
2058 func_caps->common_cap.msix_vector_first_id = msix_vector_first_id;
2059 func_caps->common_cap.max_mtu = max_mtu;
2061 /* one Tx and one Rx queue in safe mode */
2062 func_caps->common_cap.num_rxq = 1;
2063 func_caps->common_cap.num_txq = 1;
2065 /* two MSIX vectors, one for traffic and one for misc causes */
2066 func_caps->common_cap.num_msix_vectors = 2;
2067 func_caps->guar_num_vsi = 1;
2069 /* cache some dev_caps values that should be restored after memset */
2070 valid_func = dev_caps->common_cap.valid_functions;
2071 txq_first_id = dev_caps->common_cap.txq_first_id;
2072 rxq_first_id = dev_caps->common_cap.rxq_first_id;
2073 msix_vector_first_id = dev_caps->common_cap.msix_vector_first_id;
2074 max_mtu = dev_caps->common_cap.max_mtu;
2075 num_funcs = dev_caps->num_funcs;
2077 /* unset dev capabilities */
2078 memset(dev_caps, 0, sizeof(*dev_caps));
2080 /* restore cached values */
2081 dev_caps->common_cap.valid_functions = valid_func;
2082 dev_caps->common_cap.txq_first_id = txq_first_id;
2083 dev_caps->common_cap.rxq_first_id = rxq_first_id;
2084 dev_caps->common_cap.msix_vector_first_id = msix_vector_first_id;
2085 dev_caps->common_cap.max_mtu = max_mtu;
2086 dev_caps->num_funcs = num_funcs;
2088 /* one Tx and one Rx queue per function in safe mode */
2089 dev_caps->common_cap.num_rxq = num_funcs;
2090 dev_caps->common_cap.num_txq = num_funcs;
2092 /* two MSIX vectors per function */
2093 dev_caps->common_cap.num_msix_vectors = 2 * num_funcs;
2097 * ice_get_caps - get info about the HW
2098 * @hw: pointer to the hardware structure
2100 enum ice_status ice_get_caps(struct ice_hw *hw)
2102 enum ice_status status;
2104 status = ice_discover_caps(hw, ice_aqc_opc_list_dev_caps);
2106 status = ice_discover_caps(hw, ice_aqc_opc_list_func_caps);
2112 * ice_aq_manage_mac_write - manage MAC address write command
2113 * @hw: pointer to the HW struct
2114 * @mac_addr: MAC address to be written as LAA/LAA+WoL/Port address
2115 * @flags: flags to control write behavior
2116 * @cd: pointer to command details structure or NULL
2118 * This function is used to write MAC address to the NVM (0x0108).
2121 ice_aq_manage_mac_write(struct ice_hw *hw, const u8 *mac_addr, u8 flags,
2122 struct ice_sq_cd *cd)
2124 struct ice_aqc_manage_mac_write *cmd;
2125 struct ice_aq_desc desc;
2127 cmd = &desc.params.mac_write;
2128 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_write);
2131 ice_memcpy(cmd->mac_addr, mac_addr, ETH_ALEN, ICE_NONDMA_TO_DMA);
2133 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
2137 * ice_aq_clear_pxe_mode
2138 * @hw: pointer to the HW struct
2140 * Tell the firmware that the driver is taking over from PXE (0x0110).
2142 static enum ice_status ice_aq_clear_pxe_mode(struct ice_hw *hw)
2144 struct ice_aq_desc desc;
2146 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pxe_mode);
2147 desc.params.clear_pxe.rx_cnt = ICE_AQC_CLEAR_PXE_RX_CNT;
2149 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
2153 * ice_clear_pxe_mode - clear pxe operations mode
2154 * @hw: pointer to the HW struct
2156 * Make sure all PXE mode settings are cleared, including things
2157 * like descriptor fetch/write-back mode.
2159 void ice_clear_pxe_mode(struct ice_hw *hw)
2161 if (ice_check_sq_alive(hw, &hw->adminq))
2162 ice_aq_clear_pxe_mode(hw);
2166 * ice_get_link_speed_based_on_phy_type - returns link speed
2167 * @phy_type_low: lower part of phy_type
2168 * @phy_type_high: higher part of phy_type
2170 * This helper function will convert an entry in PHY type structure
2171 * [phy_type_low, phy_type_high] to its corresponding link speed.
2172 * Note: In the structure of [phy_type_low, phy_type_high], there should
2173 * be one bit set, as this function will convert one PHY type to its
2175 * If no bit gets set, ICE_LINK_SPEED_UNKNOWN will be returned
2176 * If more than one bit gets set, ICE_LINK_SPEED_UNKNOWN will be returned
2179 ice_get_link_speed_based_on_phy_type(u64 phy_type_low, u64 phy_type_high)
2181 u16 speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN;
2182 u16 speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN;
2184 switch (phy_type_low) {
2185 case ICE_PHY_TYPE_LOW_100BASE_TX:
2186 case ICE_PHY_TYPE_LOW_100M_SGMII:
2187 speed_phy_type_low = ICE_AQ_LINK_SPEED_100MB;
2189 case ICE_PHY_TYPE_LOW_1000BASE_T:
2190 case ICE_PHY_TYPE_LOW_1000BASE_SX:
2191 case ICE_PHY_TYPE_LOW_1000BASE_LX:
2192 case ICE_PHY_TYPE_LOW_1000BASE_KX:
2193 case ICE_PHY_TYPE_LOW_1G_SGMII:
2194 speed_phy_type_low = ICE_AQ_LINK_SPEED_1000MB;
2196 case ICE_PHY_TYPE_LOW_2500BASE_T:
2197 case ICE_PHY_TYPE_LOW_2500BASE_X:
2198 case ICE_PHY_TYPE_LOW_2500BASE_KX:
2199 speed_phy_type_low = ICE_AQ_LINK_SPEED_2500MB;
2201 case ICE_PHY_TYPE_LOW_5GBASE_T:
2202 case ICE_PHY_TYPE_LOW_5GBASE_KR:
2203 speed_phy_type_low = ICE_AQ_LINK_SPEED_5GB;
2205 case ICE_PHY_TYPE_LOW_10GBASE_T:
2206 case ICE_PHY_TYPE_LOW_10G_SFI_DA:
2207 case ICE_PHY_TYPE_LOW_10GBASE_SR:
2208 case ICE_PHY_TYPE_LOW_10GBASE_LR:
2209 case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1:
2210 case ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC:
2211 case ICE_PHY_TYPE_LOW_10G_SFI_C2C:
2212 speed_phy_type_low = ICE_AQ_LINK_SPEED_10GB;
2214 case ICE_PHY_TYPE_LOW_25GBASE_T:
2215 case ICE_PHY_TYPE_LOW_25GBASE_CR:
2216 case ICE_PHY_TYPE_LOW_25GBASE_CR_S:
2217 case ICE_PHY_TYPE_LOW_25GBASE_CR1:
2218 case ICE_PHY_TYPE_LOW_25GBASE_SR:
2219 case ICE_PHY_TYPE_LOW_25GBASE_LR:
2220 case ICE_PHY_TYPE_LOW_25GBASE_KR:
2221 case ICE_PHY_TYPE_LOW_25GBASE_KR_S:
2222 case ICE_PHY_TYPE_LOW_25GBASE_KR1:
2223 case ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC:
2224 case ICE_PHY_TYPE_LOW_25G_AUI_C2C:
2225 speed_phy_type_low = ICE_AQ_LINK_SPEED_25GB;
2227 case ICE_PHY_TYPE_LOW_40GBASE_CR4:
2228 case ICE_PHY_TYPE_LOW_40GBASE_SR4:
2229 case ICE_PHY_TYPE_LOW_40GBASE_LR4:
2230 case ICE_PHY_TYPE_LOW_40GBASE_KR4:
2231 case ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC:
2232 case ICE_PHY_TYPE_LOW_40G_XLAUI:
2233 speed_phy_type_low = ICE_AQ_LINK_SPEED_40GB;
2235 case ICE_PHY_TYPE_LOW_50GBASE_CR2:
2236 case ICE_PHY_TYPE_LOW_50GBASE_SR2:
2237 case ICE_PHY_TYPE_LOW_50GBASE_LR2:
2238 case ICE_PHY_TYPE_LOW_50GBASE_KR2:
2239 case ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC:
2240 case ICE_PHY_TYPE_LOW_50G_LAUI2:
2241 case ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC:
2242 case ICE_PHY_TYPE_LOW_50G_AUI2:
2243 case ICE_PHY_TYPE_LOW_50GBASE_CP:
2244 case ICE_PHY_TYPE_LOW_50GBASE_SR:
2245 case ICE_PHY_TYPE_LOW_50GBASE_FR:
2246 case ICE_PHY_TYPE_LOW_50GBASE_LR:
2247 case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4:
2248 case ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC:
2249 case ICE_PHY_TYPE_LOW_50G_AUI1:
2250 speed_phy_type_low = ICE_AQ_LINK_SPEED_50GB;
2252 case ICE_PHY_TYPE_LOW_100GBASE_CR4:
2253 case ICE_PHY_TYPE_LOW_100GBASE_SR4:
2254 case ICE_PHY_TYPE_LOW_100GBASE_LR4:
2255 case ICE_PHY_TYPE_LOW_100GBASE_KR4:
2256 case ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC:
2257 case ICE_PHY_TYPE_LOW_100G_CAUI4:
2258 case ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC:
2259 case ICE_PHY_TYPE_LOW_100G_AUI4:
2260 case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4:
2261 case ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4:
2262 case ICE_PHY_TYPE_LOW_100GBASE_CP2:
2263 case ICE_PHY_TYPE_LOW_100GBASE_SR2:
2264 case ICE_PHY_TYPE_LOW_100GBASE_DR:
2265 speed_phy_type_low = ICE_AQ_LINK_SPEED_100GB;
2268 speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN;
2272 switch (phy_type_high) {
2273 case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4:
2274 case ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC:
2275 case ICE_PHY_TYPE_HIGH_100G_CAUI2:
2276 case ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC:
2277 case ICE_PHY_TYPE_HIGH_100G_AUI2:
2278 speed_phy_type_high = ICE_AQ_LINK_SPEED_100GB;
2281 speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN;
2285 if (speed_phy_type_low == ICE_AQ_LINK_SPEED_UNKNOWN &&
2286 speed_phy_type_high == ICE_AQ_LINK_SPEED_UNKNOWN)
2287 return ICE_AQ_LINK_SPEED_UNKNOWN;
2288 else if (speed_phy_type_low != ICE_AQ_LINK_SPEED_UNKNOWN &&
2289 speed_phy_type_high != ICE_AQ_LINK_SPEED_UNKNOWN)
2290 return ICE_AQ_LINK_SPEED_UNKNOWN;
2291 else if (speed_phy_type_low != ICE_AQ_LINK_SPEED_UNKNOWN &&
2292 speed_phy_type_high == ICE_AQ_LINK_SPEED_UNKNOWN)
2293 return speed_phy_type_low;
2295 return speed_phy_type_high;
2299 * ice_update_phy_type
2300 * @phy_type_low: pointer to the lower part of phy_type
2301 * @phy_type_high: pointer to the higher part of phy_type
2302 * @link_speeds_bitmap: targeted link speeds bitmap
2304 * Note: For the link_speeds_bitmap structure, you can check it at
2305 * [ice_aqc_get_link_status->link_speed]. Caller can pass in
2306 * link_speeds_bitmap include multiple speeds.
2308 * Each entry in this [phy_type_low, phy_type_high] structure will
2309 * present a certain link speed. This helper function will turn on bits
2310 * in [phy_type_low, phy_type_high] structure based on the value of
2311 * link_speeds_bitmap input parameter.
2314 ice_update_phy_type(u64 *phy_type_low, u64 *phy_type_high,
2315 u16 link_speeds_bitmap)
2322 /* We first check with low part of phy_type */
2323 for (index = 0; index <= ICE_PHY_TYPE_LOW_MAX_INDEX; index++) {
2324 pt_low = BIT_ULL(index);
2325 speed = ice_get_link_speed_based_on_phy_type(pt_low, 0);
2327 if (link_speeds_bitmap & speed)
2328 *phy_type_low |= BIT_ULL(index);
2331 /* We then check with high part of phy_type */
2332 for (index = 0; index <= ICE_PHY_TYPE_HIGH_MAX_INDEX; index++) {
2333 pt_high = BIT_ULL(index);
2334 speed = ice_get_link_speed_based_on_phy_type(0, pt_high);
2336 if (link_speeds_bitmap & speed)
2337 *phy_type_high |= BIT_ULL(index);
2342 * ice_aq_set_phy_cfg
2343 * @hw: pointer to the HW struct
2344 * @pi: port info structure of the interested logical port
2345 * @cfg: structure with PHY configuration data to be set
2346 * @cd: pointer to command details structure or NULL
2348 * Set the various PHY configuration parameters supported on the Port.
2349 * One or more of the Set PHY config parameters may be ignored in an MFP
2350 * mode as the PF may not have the privilege to set some of the PHY Config
2351 * parameters. This status will be indicated by the command response (0x0601).
2354 ice_aq_set_phy_cfg(struct ice_hw *hw, struct ice_port_info *pi,
2355 struct ice_aqc_set_phy_cfg_data *cfg, struct ice_sq_cd *cd)
2357 struct ice_aq_desc desc;
2358 enum ice_status status;
2361 return ICE_ERR_PARAM;
2363 /* Ensure that only valid bits of cfg->caps can be turned on. */
2364 if (cfg->caps & ~ICE_AQ_PHY_ENA_VALID_MASK) {
2365 ice_debug(hw, ICE_DBG_PHY,
2366 "Invalid bit is set in ice_aqc_set_phy_cfg_data->caps : 0x%x\n",
2369 cfg->caps &= ICE_AQ_PHY_ENA_VALID_MASK;
2372 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_phy_cfg);
2373 desc.params.set_phy.lport_num = pi->lport;
2374 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
2376 ice_debug(hw, ICE_DBG_LINK, "phy_type_low = 0x%llx\n",
2377 (unsigned long long)LE64_TO_CPU(cfg->phy_type_low));
2378 ice_debug(hw, ICE_DBG_LINK, "phy_type_high = 0x%llx\n",
2379 (unsigned long long)LE64_TO_CPU(cfg->phy_type_high));
2380 ice_debug(hw, ICE_DBG_LINK, "caps = 0x%x\n", cfg->caps);
2381 ice_debug(hw, ICE_DBG_LINK, "low_power_ctrl_an = 0x%x\n",
2382 cfg->low_power_ctrl_an);
2383 ice_debug(hw, ICE_DBG_LINK, "eee_cap = 0x%x\n", cfg->eee_cap);
2384 ice_debug(hw, ICE_DBG_LINK, "eeer_value = 0x%x\n", cfg->eeer_value);
2385 ice_debug(hw, ICE_DBG_LINK, "link_fec_opt = 0x%x\n", cfg->link_fec_opt);
2387 status = ice_aq_send_cmd(hw, &desc, cfg, sizeof(*cfg), cd);
2389 if (hw->adminq.sq_last_status == ICE_AQ_RC_EMODE)
2390 status = ICE_SUCCESS;
2393 pi->phy.curr_user_phy_cfg = *cfg;
2399 * ice_update_link_info - update status of the HW network link
2400 * @pi: port info structure of the interested logical port
2402 enum ice_status ice_update_link_info(struct ice_port_info *pi)
2404 struct ice_link_status *li;
2405 enum ice_status status;
2408 return ICE_ERR_PARAM;
2410 li = &pi->phy.link_info;
2412 status = ice_aq_get_link_info(pi, true, NULL, NULL);
2416 if (li->link_info & ICE_AQ_MEDIA_AVAILABLE) {
2417 struct ice_aqc_get_phy_caps_data *pcaps;
2421 pcaps = (struct ice_aqc_get_phy_caps_data *)
2422 ice_malloc(hw, sizeof(*pcaps));
2424 return ICE_ERR_NO_MEMORY;
2426 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_TOPO_CAP,
2428 if (status == ICE_SUCCESS)
2429 ice_memcpy(li->module_type, &pcaps->module_type,
2430 sizeof(li->module_type),
2431 ICE_NONDMA_TO_NONDMA);
2433 ice_free(hw, pcaps);
2440 * ice_cache_phy_user_req
2441 * @pi: port information structure
2442 * @cache_data: PHY logging data
2443 * @cache_mode: PHY logging mode
2445 * Log the user request on (FC, FEC, SPEED) for later user.
2448 ice_cache_phy_user_req(struct ice_port_info *pi,
2449 struct ice_phy_cache_mode_data cache_data,
2450 enum ice_phy_cache_mode cache_mode)
2455 switch (cache_mode) {
2457 pi->phy.curr_user_fc_req = cache_data.data.curr_user_fc_req;
2459 case ICE_SPEED_MODE:
2460 pi->phy.curr_user_speed_req =
2461 cache_data.data.curr_user_speed_req;
2464 pi->phy.curr_user_fec_req = cache_data.data.curr_user_fec_req;
2472 * ice_caps_to_fc_mode
2473 * @caps: PHY capabilities
2475 * Convert PHY FC capabilities to ice FC mode
2477 enum ice_fc_mode ice_caps_to_fc_mode(u8 caps)
2479 if (caps & ICE_AQC_PHY_EN_TX_LINK_PAUSE &&
2480 caps & ICE_AQC_PHY_EN_RX_LINK_PAUSE)
2483 if (caps & ICE_AQC_PHY_EN_TX_LINK_PAUSE)
2484 return ICE_FC_TX_PAUSE;
2486 if (caps & ICE_AQC_PHY_EN_RX_LINK_PAUSE)
2487 return ICE_FC_RX_PAUSE;
2493 * ice_caps_to_fec_mode
2494 * @caps: PHY capabilities
2495 * @fec_options: Link FEC options
2497 * Convert PHY FEC capabilities to ice FEC mode
2499 enum ice_fec_mode ice_caps_to_fec_mode(u8 caps, u8 fec_options)
2501 if (caps & ICE_AQC_PHY_EN_AUTO_FEC)
2502 return ICE_FEC_AUTO;
2504 if (fec_options & (ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN |
2505 ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ |
2506 ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN |
2507 ICE_AQC_PHY_FEC_25G_KR_REQ))
2508 return ICE_FEC_BASER;
2510 if (fec_options & (ICE_AQC_PHY_FEC_25G_RS_528_REQ |
2511 ICE_AQC_PHY_FEC_25G_RS_544_REQ |
2512 ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN))
2515 return ICE_FEC_NONE;
2518 static enum ice_status
2519 ice_cfg_phy_fc(struct ice_port_info *pi, struct ice_aqc_set_phy_cfg_data *cfg,
2520 enum ice_fc_mode req_mode)
2522 struct ice_aqc_get_phy_caps_data *pcaps = NULL;
2523 struct ice_phy_cache_mode_data cache_data;
2524 enum ice_status status = ICE_SUCCESS;
2525 u8 pause_mask = 0x0;
2528 return ICE_ERR_BAD_PTR;
2530 pcaps = (struct ice_aqc_get_phy_caps_data *)
2531 ice_malloc(pi->hw, sizeof(*pcaps));
2533 return ICE_ERR_NO_MEMORY;
2535 /* Cache user FC request */
2536 cache_data.data.curr_user_fc_req = req_mode;
2537 ice_cache_phy_user_req(pi, cache_data, ICE_FC_MODE);
2541 /* Query the value of FC that both the NIC and attached media
2544 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_TOPO_CAP,
2549 pause_mask |= pcaps->caps & ICE_AQC_PHY_EN_TX_LINK_PAUSE;
2550 pause_mask |= pcaps->caps & ICE_AQC_PHY_EN_RX_LINK_PAUSE;
2553 pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE;
2554 pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE;
2556 case ICE_FC_RX_PAUSE:
2557 pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE;
2559 case ICE_FC_TX_PAUSE:
2560 pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE;
2566 /* clear the old pause settings */
2567 cfg->caps &= ~(ICE_AQC_PHY_EN_TX_LINK_PAUSE |
2568 ICE_AQC_PHY_EN_RX_LINK_PAUSE);
2570 /* set the new capabilities */
2571 cfg->caps |= pause_mask;
2574 ice_free(pi->hw, pcaps);
2580 * @pi: port information structure
2581 * @aq_failures: pointer to status code, specific to ice_set_fc routine
2582 * @ena_auto_link_update: enable automatic link update
2584 * Set the requested flow control mode.
2587 ice_set_fc(struct ice_port_info *pi, u8 *aq_failures, bool ena_auto_link_update)
2589 struct ice_aqc_set_phy_cfg_data cfg = { 0 };
2590 struct ice_aqc_get_phy_caps_data *pcaps;
2591 enum ice_status status;
2594 if (!pi || !aq_failures)
2595 return ICE_ERR_BAD_PTR;
2599 pcaps = (struct ice_aqc_get_phy_caps_data *)
2600 ice_malloc(hw, sizeof(*pcaps));
2602 return ICE_ERR_NO_MEMORY;
2604 /* Get the current PHY config */
2605 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_SW_CFG, pcaps,
2608 *aq_failures = ICE_SET_FC_AQ_FAIL_GET;
2612 ice_copy_phy_caps_to_cfg(pi, pcaps, &cfg);
2614 /* Configure the set PHY data */
2615 status = ice_cfg_phy_fc(pi, &cfg, pi->fc.req_mode);
2617 if (status != ICE_ERR_BAD_PTR)
2618 *aq_failures = ICE_SET_FC_AQ_FAIL_GET;
2623 /* If the capabilities have changed, then set the new config */
2624 if (cfg.caps != pcaps->caps) {
2625 int retry_count, retry_max = 10;
2627 /* Auto restart link so settings take effect */
2628 if (ena_auto_link_update)
2629 cfg.caps |= ICE_AQ_PHY_ENA_AUTO_LINK_UPDT;
2631 status = ice_aq_set_phy_cfg(hw, pi, &cfg, NULL);
2633 *aq_failures = ICE_SET_FC_AQ_FAIL_SET;
2637 /* Update the link info
2638 * It sometimes takes a really long time for link to
2639 * come back from the atomic reset. Thus, we wait a
2642 for (retry_count = 0; retry_count < retry_max; retry_count++) {
2643 status = ice_update_link_info(pi);
2645 if (status == ICE_SUCCESS)
2648 ice_msec_delay(100, true);
2652 *aq_failures = ICE_SET_FC_AQ_FAIL_UPDATE;
2656 ice_free(hw, pcaps);
2661 * ice_phy_caps_equals_cfg
2662 * @phy_caps: PHY capabilities
2663 * @phy_cfg: PHY configuration
2665 * Helper function to determine if PHY capabilities matches PHY
2669 ice_phy_caps_equals_cfg(struct ice_aqc_get_phy_caps_data *phy_caps,
2670 struct ice_aqc_set_phy_cfg_data *phy_cfg)
2672 u8 caps_mask, cfg_mask;
2674 if (!phy_caps || !phy_cfg)
2677 /* These bits are not common between capabilities and configuration.
2678 * Do not use them to determine equality.
2680 caps_mask = ICE_AQC_PHY_CAPS_MASK & ~(ICE_AQC_PHY_AN_MODE |
2681 ICE_AQC_PHY_EN_MOD_QUAL);
2682 cfg_mask = ICE_AQ_PHY_ENA_VALID_MASK & ~ICE_AQ_PHY_ENA_AUTO_LINK_UPDT;
2684 if (phy_caps->phy_type_low != phy_cfg->phy_type_low ||
2685 phy_caps->phy_type_high != phy_cfg->phy_type_high ||
2686 ((phy_caps->caps & caps_mask) != (phy_cfg->caps & cfg_mask)) ||
2687 phy_caps->low_power_ctrl_an != phy_cfg->low_power_ctrl_an ||
2688 phy_caps->eee_cap != phy_cfg->eee_cap ||
2689 phy_caps->eeer_value != phy_cfg->eeer_value ||
2690 phy_caps->link_fec_options != phy_cfg->link_fec_opt)
2697 * ice_copy_phy_caps_to_cfg - Copy PHY ability data to configuration data
2698 * @pi: port information structure
2699 * @caps: PHY ability structure to copy date from
2700 * @cfg: PHY configuration structure to copy data to
2702 * Helper function to copy AQC PHY get ability data to PHY set configuration
2706 ice_copy_phy_caps_to_cfg(struct ice_port_info *pi,
2707 struct ice_aqc_get_phy_caps_data *caps,
2708 struct ice_aqc_set_phy_cfg_data *cfg)
2710 if (!pi || !caps || !cfg)
2713 ice_memset(cfg, 0, sizeof(*cfg), ICE_NONDMA_MEM);
2714 cfg->phy_type_low = caps->phy_type_low;
2715 cfg->phy_type_high = caps->phy_type_high;
2716 cfg->caps = caps->caps;
2717 cfg->low_power_ctrl_an = caps->low_power_ctrl_an;
2718 cfg->eee_cap = caps->eee_cap;
2719 cfg->eeer_value = caps->eeer_value;
2720 cfg->link_fec_opt = caps->link_fec_options;
2721 cfg->module_compliance_enforcement =
2722 caps->module_compliance_enforcement;
2724 if (ice_fw_supports_link_override(pi->hw)) {
2725 struct ice_link_default_override_tlv tlv;
2727 if (ice_get_link_default_override(&tlv, pi))
2730 if (tlv.options & ICE_LINK_OVERRIDE_STRICT_MODE)
2731 cfg->module_compliance_enforcement |=
2732 ICE_LINK_OVERRIDE_STRICT_MODE;
2737 * ice_cfg_phy_fec - Configure PHY FEC data based on FEC mode
2738 * @pi: port information structure
2739 * @cfg: PHY configuration data to set FEC mode
2740 * @fec: FEC mode to configure
2743 ice_cfg_phy_fec(struct ice_port_info *pi, struct ice_aqc_set_phy_cfg_data *cfg,
2744 enum ice_fec_mode fec)
2746 struct ice_aqc_get_phy_caps_data *pcaps;
2747 enum ice_status status = ICE_SUCCESS;
2751 return ICE_ERR_BAD_PTR;
2755 pcaps = (struct ice_aqc_get_phy_caps_data *)
2756 ice_malloc(hw, sizeof(*pcaps));
2758 return ICE_ERR_NO_MEMORY;
2760 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_TOPO_CAP, pcaps,
2765 cfg->caps |= (pcaps->caps & ICE_AQC_PHY_EN_AUTO_FEC);
2766 cfg->link_fec_opt = pcaps->link_fec_options;
2770 /* Clear RS bits, and AND BASE-R ability
2771 * bits and OR request bits.
2773 cfg->link_fec_opt &= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN |
2774 ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN;
2775 cfg->link_fec_opt |= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ |
2776 ICE_AQC_PHY_FEC_25G_KR_REQ;
2779 /* Clear BASE-R bits, and AND RS ability
2780 * bits and OR request bits.
2782 cfg->link_fec_opt &= ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN;
2783 cfg->link_fec_opt |= ICE_AQC_PHY_FEC_25G_RS_528_REQ |
2784 ICE_AQC_PHY_FEC_25G_RS_544_REQ;
2787 /* Clear all FEC option bits. */
2788 cfg->link_fec_opt &= ~ICE_AQC_PHY_FEC_MASK;
2791 /* AND auto FEC bit, and all caps bits. */
2792 cfg->caps &= ICE_AQC_PHY_CAPS_MASK;
2793 cfg->link_fec_opt |= pcaps->link_fec_options;
2796 status = ICE_ERR_PARAM;
2800 if (fec == ICE_FEC_AUTO && ice_fw_supports_link_override(pi->hw)) {
2801 struct ice_link_default_override_tlv tlv;
2803 if (ice_get_link_default_override(&tlv, pi))
2806 if (!(tlv.options & ICE_LINK_OVERRIDE_STRICT_MODE) &&
2807 (tlv.options & ICE_LINK_OVERRIDE_EN))
2808 cfg->link_fec_opt = tlv.fec_options;
2812 ice_free(hw, pcaps);
2818 * ice_get_link_status - get status of the HW network link
2819 * @pi: port information structure
2820 * @link_up: pointer to bool (true/false = linkup/linkdown)
2822 * Variable link_up is true if link is up, false if link is down.
2823 * The variable link_up is invalid if status is non zero. As a
2824 * result of this call, link status reporting becomes enabled
2826 enum ice_status ice_get_link_status(struct ice_port_info *pi, bool *link_up)
2828 struct ice_phy_info *phy_info;
2829 enum ice_status status = ICE_SUCCESS;
2831 if (!pi || !link_up)
2832 return ICE_ERR_PARAM;
2834 phy_info = &pi->phy;
2836 if (phy_info->get_link_info) {
2837 status = ice_update_link_info(pi);
2840 ice_debug(pi->hw, ICE_DBG_LINK,
2841 "get link status error, status = %d\n",
2845 *link_up = phy_info->link_info.link_info & ICE_AQ_LINK_UP;
2851 * ice_aq_set_link_restart_an
2852 * @pi: pointer to the port information structure
2853 * @ena_link: if true: enable link, if false: disable link
2854 * @cd: pointer to command details structure or NULL
2856 * Sets up the link and restarts the Auto-Negotiation over the link.
2859 ice_aq_set_link_restart_an(struct ice_port_info *pi, bool ena_link,
2860 struct ice_sq_cd *cd)
2862 struct ice_aqc_restart_an *cmd;
2863 struct ice_aq_desc desc;
2865 cmd = &desc.params.restart_an;
2867 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_restart_an);
2869 cmd->cmd_flags = ICE_AQC_RESTART_AN_LINK_RESTART;
2870 cmd->lport_num = pi->lport;
2872 cmd->cmd_flags |= ICE_AQC_RESTART_AN_LINK_ENABLE;
2874 cmd->cmd_flags &= ~ICE_AQC_RESTART_AN_LINK_ENABLE;
2876 return ice_aq_send_cmd(pi->hw, &desc, NULL, 0, cd);
2880 * ice_aq_set_event_mask
2881 * @hw: pointer to the HW struct
2882 * @port_num: port number of the physical function
2883 * @mask: event mask to be set
2884 * @cd: pointer to command details structure or NULL
2886 * Set event mask (0x0613)
2889 ice_aq_set_event_mask(struct ice_hw *hw, u8 port_num, u16 mask,
2890 struct ice_sq_cd *cd)
2892 struct ice_aqc_set_event_mask *cmd;
2893 struct ice_aq_desc desc;
2895 cmd = &desc.params.set_event_mask;
2897 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_event_mask);
2899 cmd->lport_num = port_num;
2901 cmd->event_mask = CPU_TO_LE16(mask);
2902 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
2906 * ice_aq_set_mac_loopback
2907 * @hw: pointer to the HW struct
2908 * @ena_lpbk: Enable or Disable loopback
2909 * @cd: pointer to command details structure or NULL
2911 * Enable/disable loopback on a given port
2914 ice_aq_set_mac_loopback(struct ice_hw *hw, bool ena_lpbk, struct ice_sq_cd *cd)
2916 struct ice_aqc_set_mac_lb *cmd;
2917 struct ice_aq_desc desc;
2919 cmd = &desc.params.set_mac_lb;
2921 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_mac_lb);
2923 cmd->lb_mode = ICE_AQ_MAC_LB_EN;
2925 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
2929 * ice_aq_set_port_id_led
2930 * @pi: pointer to the port information
2931 * @is_orig_mode: is this LED set to original mode (by the net-list)
2932 * @cd: pointer to command details structure or NULL
2934 * Set LED value for the given port (0x06e9)
2937 ice_aq_set_port_id_led(struct ice_port_info *pi, bool is_orig_mode,
2938 struct ice_sq_cd *cd)
2940 struct ice_aqc_set_port_id_led *cmd;
2941 struct ice_hw *hw = pi->hw;
2942 struct ice_aq_desc desc;
2944 cmd = &desc.params.set_port_id_led;
2946 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_port_id_led);
2949 cmd->ident_mode = ICE_AQC_PORT_IDENT_LED_ORIG;
2951 cmd->ident_mode = ICE_AQC_PORT_IDENT_LED_BLINK;
2953 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
2958 * @hw: pointer to the HW struct
2959 * @lport: bits [7:0] = logical port, bit [8] = logical port valid
2960 * @bus_addr: I2C bus address of the eeprom (typically 0xA0, 0=topo default)
2961 * @mem_addr: I2C offset. lower 8 bits for address, 8 upper bits zero padding.
2963 * @set_page: set or ignore the page
2964 * @data: pointer to data buffer to be read/written to the I2C device.
2965 * @length: 1-16 for read, 1 for write.
2966 * @write: 0 read, 1 for write.
2967 * @cd: pointer to command details structure or NULL
2969 * Read/Write SFF EEPROM (0x06EE)
2972 ice_aq_sff_eeprom(struct ice_hw *hw, u16 lport, u8 bus_addr,
2973 u16 mem_addr, u8 page, u8 set_page, u8 *data, u8 length,
2974 bool write, struct ice_sq_cd *cd)
2976 struct ice_aqc_sff_eeprom *cmd;
2977 struct ice_aq_desc desc;
2978 enum ice_status status;
2980 if (!data || (mem_addr & 0xff00))
2981 return ICE_ERR_PARAM;
2983 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_sff_eeprom);
2984 cmd = &desc.params.read_write_sff_param;
2985 desc.flags = CPU_TO_LE16(ICE_AQ_FLAG_RD | ICE_AQ_FLAG_BUF);
2986 cmd->lport_num = (u8)(lport & 0xff);
2987 cmd->lport_num_valid = (u8)((lport >> 8) & 0x01);
2988 cmd->i2c_bus_addr = CPU_TO_LE16(((bus_addr >> 1) &
2989 ICE_AQC_SFF_I2CBUS_7BIT_M) |
2991 ICE_AQC_SFF_SET_EEPROM_PAGE_S) &
2992 ICE_AQC_SFF_SET_EEPROM_PAGE_M));
2993 cmd->i2c_mem_addr = CPU_TO_LE16(mem_addr & 0xff);
2994 cmd->eeprom_page = CPU_TO_LE16((u16)page << ICE_AQC_SFF_EEPROM_PAGE_S);
2996 cmd->i2c_bus_addr |= CPU_TO_LE16(ICE_AQC_SFF_IS_WRITE);
2998 status = ice_aq_send_cmd(hw, &desc, data, length, cd);
3003 * __ice_aq_get_set_rss_lut
3004 * @hw: pointer to the hardware structure
3005 * @vsi_id: VSI FW index
3006 * @lut_type: LUT table type
3007 * @lut: pointer to the LUT buffer provided by the caller
3008 * @lut_size: size of the LUT buffer
3009 * @glob_lut_idx: global LUT index
3010 * @set: set true to set the table, false to get the table
3012 * Internal function to get (0x0B05) or set (0x0B03) RSS look up table
3014 static enum ice_status
3015 __ice_aq_get_set_rss_lut(struct ice_hw *hw, u16 vsi_id, u8 lut_type, u8 *lut,
3016 u16 lut_size, u8 glob_lut_idx, bool set)
3018 struct ice_aqc_get_set_rss_lut *cmd_resp;
3019 struct ice_aq_desc desc;
3020 enum ice_status status;
3023 cmd_resp = &desc.params.get_set_rss_lut;
3026 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_rss_lut);
3027 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
3029 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_rss_lut);
3032 cmd_resp->vsi_id = CPU_TO_LE16(((vsi_id <<
3033 ICE_AQC_GSET_RSS_LUT_VSI_ID_S) &
3034 ICE_AQC_GSET_RSS_LUT_VSI_ID_M) |
3035 ICE_AQC_GSET_RSS_LUT_VSI_VALID);
3038 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_VSI:
3039 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF:
3040 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL:
3041 flags |= ((lut_type << ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S) &
3042 ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_M);
3045 status = ICE_ERR_PARAM;
3046 goto ice_aq_get_set_rss_lut_exit;
3049 if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL) {
3050 flags |= ((glob_lut_idx << ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S) &
3051 ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_M);
3054 goto ice_aq_get_set_rss_lut_send;
3055 } else if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF) {
3057 goto ice_aq_get_set_rss_lut_send;
3059 goto ice_aq_get_set_rss_lut_send;
3062 /* LUT size is only valid for Global and PF table types */
3064 case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128:
3065 flags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128_FLAG <<
3066 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) &
3067 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M;
3069 case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512:
3070 flags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512_FLAG <<
3071 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) &
3072 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M;
3074 case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K:
3075 if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF) {
3076 flags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K_FLAG <<
3077 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) &
3078 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M;
3083 status = ICE_ERR_PARAM;
3084 goto ice_aq_get_set_rss_lut_exit;
3087 ice_aq_get_set_rss_lut_send:
3088 cmd_resp->flags = CPU_TO_LE16(flags);
3089 status = ice_aq_send_cmd(hw, &desc, lut, lut_size, NULL);
3091 ice_aq_get_set_rss_lut_exit:
3096 * ice_aq_get_rss_lut
3097 * @hw: pointer to the hardware structure
3098 * @vsi_handle: software VSI handle
3099 * @lut_type: LUT table type
3100 * @lut: pointer to the LUT buffer provided by the caller
3101 * @lut_size: size of the LUT buffer
3103 * get the RSS lookup table, PF or VSI type
3106 ice_aq_get_rss_lut(struct ice_hw *hw, u16 vsi_handle, u8 lut_type,
3107 u8 *lut, u16 lut_size)
3109 if (!ice_is_vsi_valid(hw, vsi_handle) || !lut)
3110 return ICE_ERR_PARAM;
3112 return __ice_aq_get_set_rss_lut(hw, ice_get_hw_vsi_num(hw, vsi_handle),
3113 lut_type, lut, lut_size, 0, false);
3117 * ice_aq_set_rss_lut
3118 * @hw: pointer to the hardware structure
3119 * @vsi_handle: software VSI handle
3120 * @lut_type: LUT table type
3121 * @lut: pointer to the LUT buffer provided by the caller
3122 * @lut_size: size of the LUT buffer
3124 * set the RSS lookup table, PF or VSI type
3127 ice_aq_set_rss_lut(struct ice_hw *hw, u16 vsi_handle, u8 lut_type,
3128 u8 *lut, u16 lut_size)
3130 if (!ice_is_vsi_valid(hw, vsi_handle) || !lut)
3131 return ICE_ERR_PARAM;
3133 return __ice_aq_get_set_rss_lut(hw, ice_get_hw_vsi_num(hw, vsi_handle),
3134 lut_type, lut, lut_size, 0, true);
3138 * __ice_aq_get_set_rss_key
3139 * @hw: pointer to the HW struct
3140 * @vsi_id: VSI FW index
3141 * @key: pointer to key info struct
3142 * @set: set true to set the key, false to get the key
3144 * get (0x0B04) or set (0x0B02) the RSS key per VSI
3147 ice_status __ice_aq_get_set_rss_key(struct ice_hw *hw, u16 vsi_id,
3148 struct ice_aqc_get_set_rss_keys *key,
3151 struct ice_aqc_get_set_rss_key *cmd_resp;
3152 u16 key_size = sizeof(*key);
3153 struct ice_aq_desc desc;
3155 cmd_resp = &desc.params.get_set_rss_key;
3158 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_rss_key);
3159 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
3161 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_rss_key);
3164 cmd_resp->vsi_id = CPU_TO_LE16(((vsi_id <<
3165 ICE_AQC_GSET_RSS_KEY_VSI_ID_S) &
3166 ICE_AQC_GSET_RSS_KEY_VSI_ID_M) |
3167 ICE_AQC_GSET_RSS_KEY_VSI_VALID);
3169 return ice_aq_send_cmd(hw, &desc, key, key_size, NULL);
3173 * ice_aq_get_rss_key
3174 * @hw: pointer to the HW struct
3175 * @vsi_handle: software VSI handle
3176 * @key: pointer to key info struct
3178 * get the RSS key per VSI
3181 ice_aq_get_rss_key(struct ice_hw *hw, u16 vsi_handle,
3182 struct ice_aqc_get_set_rss_keys *key)
3184 if (!ice_is_vsi_valid(hw, vsi_handle) || !key)
3185 return ICE_ERR_PARAM;
3187 return __ice_aq_get_set_rss_key(hw, ice_get_hw_vsi_num(hw, vsi_handle),
3192 * ice_aq_set_rss_key
3193 * @hw: pointer to the HW struct
3194 * @vsi_handle: software VSI handle
3195 * @keys: pointer to key info struct
3197 * set the RSS key per VSI
3200 ice_aq_set_rss_key(struct ice_hw *hw, u16 vsi_handle,
3201 struct ice_aqc_get_set_rss_keys *keys)
3203 if (!ice_is_vsi_valid(hw, vsi_handle) || !keys)
3204 return ICE_ERR_PARAM;
3206 return __ice_aq_get_set_rss_key(hw, ice_get_hw_vsi_num(hw, vsi_handle),
3211 * ice_aq_add_lan_txq
3212 * @hw: pointer to the hardware structure
3213 * @num_qgrps: Number of added queue groups
3214 * @qg_list: list of queue groups to be added
3215 * @buf_size: size of buffer for indirect command
3216 * @cd: pointer to command details structure or NULL
3218 * Add Tx LAN queue (0x0C30)
3221 * Prior to calling add Tx LAN queue:
3222 * Initialize the following as part of the Tx queue context:
3223 * Completion queue ID if the queue uses Completion queue, Quanta profile,
3224 * Cache profile and Packet shaper profile.
3226 * After add Tx LAN queue AQ command is completed:
3227 * Interrupts should be associated with specific queues,
3228 * Association of Tx queue to Doorbell queue is not part of Add LAN Tx queue
3232 ice_aq_add_lan_txq(struct ice_hw *hw, u8 num_qgrps,
3233 struct ice_aqc_add_tx_qgrp *qg_list, u16 buf_size,
3234 struct ice_sq_cd *cd)
3236 u16 i, sum_header_size, sum_q_size = 0;
3237 struct ice_aqc_add_tx_qgrp *list;
3238 struct ice_aqc_add_txqs *cmd;
3239 struct ice_aq_desc desc;
3241 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
3243 cmd = &desc.params.add_txqs;
3245 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_add_txqs);
3248 return ICE_ERR_PARAM;
3250 if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS)
3251 return ICE_ERR_PARAM;
3253 sum_header_size = num_qgrps *
3254 (sizeof(*qg_list) - sizeof(*qg_list->txqs));
3257 for (i = 0; i < num_qgrps; i++) {
3258 struct ice_aqc_add_txqs_perq *q = list->txqs;
3260 sum_q_size += list->num_txqs * sizeof(*q);
3261 list = (struct ice_aqc_add_tx_qgrp *)(q + list->num_txqs);
3264 if (buf_size != (sum_header_size + sum_q_size))
3265 return ICE_ERR_PARAM;
3267 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
3269 cmd->num_qgrps = num_qgrps;
3271 return ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd);
3275 * ice_aq_dis_lan_txq
3276 * @hw: pointer to the hardware structure
3277 * @num_qgrps: number of groups in the list
3278 * @qg_list: the list of groups to disable
3279 * @buf_size: the total size of the qg_list buffer in bytes
3280 * @rst_src: if called due to reset, specifies the reset source
3281 * @vmvf_num: the relative VM or VF number that is undergoing the reset
3282 * @cd: pointer to command details structure or NULL
3284 * Disable LAN Tx queue (0x0C31)
3286 static enum ice_status
3287 ice_aq_dis_lan_txq(struct ice_hw *hw, u8 num_qgrps,
3288 struct ice_aqc_dis_txq_item *qg_list, u16 buf_size,
3289 enum ice_disq_rst_src rst_src, u16 vmvf_num,
3290 struct ice_sq_cd *cd)
3292 struct ice_aqc_dis_txqs *cmd;
3293 struct ice_aq_desc desc;
3294 enum ice_status status;
3297 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
3298 cmd = &desc.params.dis_txqs;
3299 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_dis_txqs);
3301 /* qg_list can be NULL only in VM/VF reset flow */
3302 if (!qg_list && !rst_src)
3303 return ICE_ERR_PARAM;
3305 if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS)
3306 return ICE_ERR_PARAM;
3308 cmd->num_entries = num_qgrps;
3310 cmd->vmvf_and_timeout = CPU_TO_LE16((5 << ICE_AQC_Q_DIS_TIMEOUT_S) &
3311 ICE_AQC_Q_DIS_TIMEOUT_M);
3315 cmd->cmd_type = ICE_AQC_Q_DIS_CMD_VM_RESET;
3316 cmd->vmvf_and_timeout |=
3317 CPU_TO_LE16(vmvf_num & ICE_AQC_Q_DIS_VMVF_NUM_M);
3324 /* flush pipe on time out */
3325 cmd->cmd_type |= ICE_AQC_Q_DIS_CMD_FLUSH_PIPE;
3326 /* If no queue group info, we are in a reset flow. Issue the AQ */
3330 /* set RD bit to indicate that command buffer is provided by the driver
3331 * and it needs to be read by the firmware
3333 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
3335 for (i = 0; i < num_qgrps; ++i) {
3336 /* Calculate the size taken up by the queue IDs in this group */
3337 sz += qg_list[i].num_qs * sizeof(qg_list[i].q_id);
3339 /* Add the size of the group header */
3340 sz += sizeof(qg_list[i]) - sizeof(qg_list[i].q_id);
3342 /* If the num of queues is even, add 2 bytes of padding */
3343 if ((qg_list[i].num_qs % 2) == 0)
3348 return ICE_ERR_PARAM;
3351 status = ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd);
3354 ice_debug(hw, ICE_DBG_SCHED, "VM%d disable failed %d\n",
3355 vmvf_num, hw->adminq.sq_last_status);
3357 ice_debug(hw, ICE_DBG_SCHED, "disable queue %d failed %d\n",
3358 LE16_TO_CPU(qg_list[0].q_id[0]),
3359 hw->adminq.sq_last_status);
3365 * ice_aq_move_recfg_lan_txq
3366 * @hw: pointer to the hardware structure
3367 * @num_qs: number of queues to move/reconfigure
3368 * @is_move: true if this operation involves node movement
3369 * @is_tc_change: true if this operation involves a TC change
3370 * @subseq_call: true if this operation is a subsequent call
3371 * @flush_pipe: on timeout, true to flush pipe, false to return EAGAIN
3372 * @timeout: timeout in units of 100 usec (valid values 0-50)
3373 * @blocked_cgds: out param, bitmap of CGDs that timed out if returning EAGAIN
3374 * @buf: struct containing src/dest TEID and per-queue info
3375 * @buf_size: size of buffer for indirect command
3376 * @txqs_moved: out param, number of queues successfully moved
3377 * @cd: pointer to command details structure or NULL
3379 * Move / Reconfigure Tx LAN queues (0x0C32)
3382 ice_aq_move_recfg_lan_txq(struct ice_hw *hw, u8 num_qs, bool is_move,
3383 bool is_tc_change, bool subseq_call, bool flush_pipe,
3384 u8 timeout, u32 *blocked_cgds,
3385 struct ice_aqc_move_txqs_data *buf, u16 buf_size,
3386 u8 *txqs_moved, struct ice_sq_cd *cd)
3388 struct ice_aqc_move_txqs *cmd;
3389 struct ice_aq_desc desc;
3390 enum ice_status status;
3392 cmd = &desc.params.move_txqs;
3393 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_move_recfg_txqs);
3395 #define ICE_LAN_TXQ_MOVE_TIMEOUT_MAX 50
3396 if (timeout > ICE_LAN_TXQ_MOVE_TIMEOUT_MAX)
3397 return ICE_ERR_PARAM;
3399 if (is_tc_change && !flush_pipe && !blocked_cgds)
3400 return ICE_ERR_PARAM;
3402 if (!is_move && !is_tc_change)
3403 return ICE_ERR_PARAM;
3405 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
3408 cmd->cmd_type |= ICE_AQC_Q_CMD_TYPE_MOVE;
3411 cmd->cmd_type |= ICE_AQC_Q_CMD_TYPE_TC_CHANGE;
3414 cmd->cmd_type |= ICE_AQC_Q_CMD_SUBSEQ_CALL;
3417 cmd->cmd_type |= ICE_AQC_Q_CMD_FLUSH_PIPE;
3419 cmd->num_qs = num_qs;
3420 cmd->timeout = ((timeout << ICE_AQC_Q_CMD_TIMEOUT_S) &
3421 ICE_AQC_Q_CMD_TIMEOUT_M);
3423 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);
3425 if (!status && txqs_moved)
3426 *txqs_moved = cmd->num_qs;
3428 if (hw->adminq.sq_last_status == ICE_AQ_RC_EAGAIN &&
3429 is_tc_change && !flush_pipe)
3430 *blocked_cgds = LE32_TO_CPU(cmd->blocked_cgds);
3435 /* End of FW Admin Queue command wrappers */
3438 * ice_write_byte - write a byte to a packed context structure
3439 * @src_ctx: the context structure to read from
3440 * @dest_ctx: the context to be written to
3441 * @ce_info: a description of the struct to be filled
3444 ice_write_byte(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)
3446 u8 src_byte, dest_byte, mask;
3450 /* copy from the next struct field */
3451 from = src_ctx + ce_info->offset;
3453 /* prepare the bits and mask */
3454 shift_width = ce_info->lsb % 8;
3455 mask = (u8)(BIT(ce_info->width) - 1);
3460 /* shift to correct alignment */
3461 mask <<= shift_width;
3462 src_byte <<= shift_width;
3464 /* get the current bits from the target bit string */
3465 dest = dest_ctx + (ce_info->lsb / 8);
3467 ice_memcpy(&dest_byte, dest, sizeof(dest_byte), ICE_DMA_TO_NONDMA);
3469 dest_byte &= ~mask; /* get the bits not changing */
3470 dest_byte |= src_byte; /* add in the new bits */
3472 /* put it all back */
3473 ice_memcpy(dest, &dest_byte, sizeof(dest_byte), ICE_NONDMA_TO_DMA);
3477 * ice_write_word - write a word to a packed context structure
3478 * @src_ctx: the context structure to read from
3479 * @dest_ctx: the context to be written to
3480 * @ce_info: a description of the struct to be filled
3483 ice_write_word(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)
3490 /* copy from the next struct field */
3491 from = src_ctx + ce_info->offset;
3493 /* prepare the bits and mask */
3494 shift_width = ce_info->lsb % 8;
3495 mask = BIT(ce_info->width) - 1;
3497 /* don't swizzle the bits until after the mask because the mask bits
3498 * will be in a different bit position on big endian machines
3500 src_word = *(u16 *)from;
3503 /* shift to correct alignment */
3504 mask <<= shift_width;
3505 src_word <<= shift_width;
3507 /* get the current bits from the target bit string */
3508 dest = dest_ctx + (ce_info->lsb / 8);
3510 ice_memcpy(&dest_word, dest, sizeof(dest_word), ICE_DMA_TO_NONDMA);
3512 dest_word &= ~(CPU_TO_LE16(mask)); /* get the bits not changing */
3513 dest_word |= CPU_TO_LE16(src_word); /* add in the new bits */
3515 /* put it all back */
3516 ice_memcpy(dest, &dest_word, sizeof(dest_word), ICE_NONDMA_TO_DMA);
3520 * ice_write_dword - write a dword to a packed context structure
3521 * @src_ctx: the context structure to read from
3522 * @dest_ctx: the context to be written to
3523 * @ce_info: a description of the struct to be filled
3526 ice_write_dword(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)
3528 u32 src_dword, mask;
3533 /* copy from the next struct field */
3534 from = src_ctx + ce_info->offset;
3536 /* prepare the bits and mask */
3537 shift_width = ce_info->lsb % 8;
3539 /* if the field width is exactly 32 on an x86 machine, then the shift
3540 * operation will not work because the SHL instructions count is masked
3541 * to 5 bits so the shift will do nothing
3543 if (ce_info->width < 32)
3544 mask = BIT(ce_info->width) - 1;
3548 /* don't swizzle the bits until after the mask because the mask bits
3549 * will be in a different bit position on big endian machines
3551 src_dword = *(u32 *)from;
3554 /* shift to correct alignment */
3555 mask <<= shift_width;
3556 src_dword <<= shift_width;
3558 /* get the current bits from the target bit string */
3559 dest = dest_ctx + (ce_info->lsb / 8);
3561 ice_memcpy(&dest_dword, dest, sizeof(dest_dword), ICE_DMA_TO_NONDMA);
3563 dest_dword &= ~(CPU_TO_LE32(mask)); /* get the bits not changing */
3564 dest_dword |= CPU_TO_LE32(src_dword); /* add in the new bits */
3566 /* put it all back */
3567 ice_memcpy(dest, &dest_dword, sizeof(dest_dword), ICE_NONDMA_TO_DMA);
3571 * ice_write_qword - write a qword to a packed context structure
3572 * @src_ctx: the context structure to read from
3573 * @dest_ctx: the context to be written to
3574 * @ce_info: a description of the struct to be filled
3577 ice_write_qword(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)
3579 u64 src_qword, mask;
3584 /* copy from the next struct field */
3585 from = src_ctx + ce_info->offset;
3587 /* prepare the bits and mask */
3588 shift_width = ce_info->lsb % 8;
3590 /* if the field width is exactly 64 on an x86 machine, then the shift
3591 * operation will not work because the SHL instructions count is masked
3592 * to 6 bits so the shift will do nothing
3594 if (ce_info->width < 64)
3595 mask = BIT_ULL(ce_info->width) - 1;
3599 /* don't swizzle the bits until after the mask because the mask bits
3600 * will be in a different bit position on big endian machines
3602 src_qword = *(u64 *)from;
3605 /* shift to correct alignment */
3606 mask <<= shift_width;
3607 src_qword <<= shift_width;
3609 /* get the current bits from the target bit string */
3610 dest = dest_ctx + (ce_info->lsb / 8);
3612 ice_memcpy(&dest_qword, dest, sizeof(dest_qword), ICE_DMA_TO_NONDMA);
3614 dest_qword &= ~(CPU_TO_LE64(mask)); /* get the bits not changing */
3615 dest_qword |= CPU_TO_LE64(src_qword); /* add in the new bits */
3617 /* put it all back */
3618 ice_memcpy(dest, &dest_qword, sizeof(dest_qword), ICE_NONDMA_TO_DMA);
3622 * ice_set_ctx - set context bits in packed structure
3623 * @hw: pointer to the hardware structure
3624 * @src_ctx: pointer to a generic non-packed context structure
3625 * @dest_ctx: pointer to memory for the packed structure
3626 * @ce_info: a description of the structure to be transformed
3629 ice_set_ctx(struct ice_hw *hw, u8 *src_ctx, u8 *dest_ctx,
3630 const struct ice_ctx_ele *ce_info)
3634 for (f = 0; ce_info[f].width; f++) {
3635 /* We have to deal with each element of the FW response
3636 * using the correct size so that we are correct regardless
3637 * of the endianness of the machine.
3639 if (ce_info[f].width > (ce_info[f].size_of * BITS_PER_BYTE)) {
3640 ice_debug(hw, ICE_DBG_QCTX,
3641 "Field %d width of %d bits larger than size of %d byte(s) ... skipping write\n",
3642 f, ce_info[f].width, ce_info[f].size_of);
3645 switch (ce_info[f].size_of) {
3647 ice_write_byte(src_ctx, dest_ctx, &ce_info[f]);
3650 ice_write_word(src_ctx, dest_ctx, &ce_info[f]);
3653 ice_write_dword(src_ctx, dest_ctx, &ce_info[f]);
3656 ice_write_qword(src_ctx, dest_ctx, &ce_info[f]);
3659 return ICE_ERR_INVAL_SIZE;
3667 * ice_read_byte - read context byte into struct
3668 * @src_ctx: the context structure to read from
3669 * @dest_ctx: the context to be written to
3670 * @ce_info: a description of the struct to be filled
3673 ice_read_byte(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info)
3679 /* prepare the bits and mask */
3680 shift_width = ce_info->lsb % 8;
3681 mask = (u8)(BIT(ce_info->width) - 1);
3683 /* shift to correct alignment */
3684 mask <<= shift_width;
3686 /* get the current bits from the src bit string */
3687 src = src_ctx + (ce_info->lsb / 8);
3689 ice_memcpy(&dest_byte, src, sizeof(dest_byte), ICE_DMA_TO_NONDMA);
3691 dest_byte &= ~(mask);
3693 dest_byte >>= shift_width;
3695 /* get the address from the struct field */
3696 target = dest_ctx + ce_info->offset;
3698 /* put it back in the struct */
3699 ice_memcpy(target, &dest_byte, sizeof(dest_byte), ICE_NONDMA_TO_DMA);
3703 * ice_read_word - read context word into struct
3704 * @src_ctx: the context structure to read from
3705 * @dest_ctx: the context to be written to
3706 * @ce_info: a description of the struct to be filled
3709 ice_read_word(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info)
3711 u16 dest_word, mask;
3716 /* prepare the bits and mask */
3717 shift_width = ce_info->lsb % 8;
3718 mask = BIT(ce_info->width) - 1;
3720 /* shift to correct alignment */
3721 mask <<= shift_width;
3723 /* get the current bits from the src bit string */
3724 src = src_ctx + (ce_info->lsb / 8);
3726 ice_memcpy(&src_word, src, sizeof(src_word), ICE_DMA_TO_NONDMA);
3728 /* the data in the memory is stored as little endian so mask it
3731 src_word &= ~(CPU_TO_LE16(mask));
3733 /* get the data back into host order before shifting */
3734 dest_word = LE16_TO_CPU(src_word);
3736 dest_word >>= shift_width;
3738 /* get the address from the struct field */
3739 target = dest_ctx + ce_info->offset;
3741 /* put it back in the struct */
3742 ice_memcpy(target, &dest_word, sizeof(dest_word), ICE_NONDMA_TO_DMA);
3746 * ice_read_dword - read context dword into struct
3747 * @src_ctx: the context structure to read from
3748 * @dest_ctx: the context to be written to
3749 * @ce_info: a description of the struct to be filled
3752 ice_read_dword(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info)
3754 u32 dest_dword, mask;
3759 /* prepare the bits and mask */
3760 shift_width = ce_info->lsb % 8;
3762 /* if the field width is exactly 32 on an x86 machine, then the shift
3763 * operation will not work because the SHL instructions count is masked
3764 * to 5 bits so the shift will do nothing
3766 if (ce_info->width < 32)
3767 mask = BIT(ce_info->width) - 1;
3771 /* shift to correct alignment */
3772 mask <<= shift_width;
3774 /* get the current bits from the src bit string */
3775 src = src_ctx + (ce_info->lsb / 8);
3777 ice_memcpy(&src_dword, src, sizeof(src_dword), ICE_DMA_TO_NONDMA);
3779 /* the data in the memory is stored as little endian so mask it
3782 src_dword &= ~(CPU_TO_LE32(mask));
3784 /* get the data back into host order before shifting */
3785 dest_dword = LE32_TO_CPU(src_dword);
3787 dest_dword >>= shift_width;
3789 /* get the address from the struct field */
3790 target = dest_ctx + ce_info->offset;
3792 /* put it back in the struct */
3793 ice_memcpy(target, &dest_dword, sizeof(dest_dword), ICE_NONDMA_TO_DMA);
3797 * ice_read_qword - read context qword into struct
3798 * @src_ctx: the context structure to read from
3799 * @dest_ctx: the context to be written to
3800 * @ce_info: a description of the struct to be filled
3803 ice_read_qword(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info)
3805 u64 dest_qword, mask;
3810 /* prepare the bits and mask */
3811 shift_width = ce_info->lsb % 8;
3813 /* if the field width is exactly 64 on an x86 machine, then the shift
3814 * operation will not work because the SHL instructions count is masked
3815 * to 6 bits so the shift will do nothing
3817 if (ce_info->width < 64)
3818 mask = BIT_ULL(ce_info->width) - 1;
3822 /* shift to correct alignment */
3823 mask <<= shift_width;
3825 /* get the current bits from the src bit string */
3826 src = src_ctx + (ce_info->lsb / 8);
3828 ice_memcpy(&src_qword, src, sizeof(src_qword), ICE_DMA_TO_NONDMA);
3830 /* the data in the memory is stored as little endian so mask it
3833 src_qword &= ~(CPU_TO_LE64(mask));
3835 /* get the data back into host order before shifting */
3836 dest_qword = LE64_TO_CPU(src_qword);
3838 dest_qword >>= shift_width;
3840 /* get the address from the struct field */
3841 target = dest_ctx + ce_info->offset;
3843 /* put it back in the struct */
3844 ice_memcpy(target, &dest_qword, sizeof(dest_qword), ICE_NONDMA_TO_DMA);
3848 * ice_get_ctx - extract context bits from a packed structure
3849 * @src_ctx: pointer to a generic packed context structure
3850 * @dest_ctx: pointer to a generic non-packed context structure
3851 * @ce_info: a description of the structure to be read from
3854 ice_get_ctx(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info)
3858 for (f = 0; ce_info[f].width; f++) {
3859 switch (ce_info[f].size_of) {
3861 ice_read_byte(src_ctx, dest_ctx, &ce_info[f]);
3864 ice_read_word(src_ctx, dest_ctx, &ce_info[f]);
3867 ice_read_dword(src_ctx, dest_ctx, &ce_info[f]);
3870 ice_read_qword(src_ctx, dest_ctx, &ce_info[f]);
3873 /* nothing to do, just keep going */
3882 * ice_get_lan_q_ctx - get the LAN queue context for the given VSI and TC
3883 * @hw: pointer to the HW struct
3884 * @vsi_handle: software VSI handle
3886 * @q_handle: software queue handle
3889 ice_get_lan_q_ctx(struct ice_hw *hw, u16 vsi_handle, u8 tc, u16 q_handle)
3891 struct ice_vsi_ctx *vsi;
3892 struct ice_q_ctx *q_ctx;
3894 vsi = ice_get_vsi_ctx(hw, vsi_handle);
3897 if (q_handle >= vsi->num_lan_q_entries[tc])
3899 if (!vsi->lan_q_ctx[tc])
3901 q_ctx = vsi->lan_q_ctx[tc];
3902 return &q_ctx[q_handle];
3907 * @pi: port information structure
3908 * @vsi_handle: software VSI handle
3910 * @q_handle: software queue handle
3911 * @num_qgrps: Number of added queue groups
3912 * @buf: list of queue groups to be added
3913 * @buf_size: size of buffer for indirect command
3914 * @cd: pointer to command details structure or NULL
3916 * This function adds one LAN queue
3919 ice_ena_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u16 q_handle,
3920 u8 num_qgrps, struct ice_aqc_add_tx_qgrp *buf, u16 buf_size,
3921 struct ice_sq_cd *cd)
3923 struct ice_aqc_txsched_elem_data node = { 0 };
3924 struct ice_sched_node *parent;
3925 struct ice_q_ctx *q_ctx;
3926 enum ice_status status;
3929 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY)
3932 if (num_qgrps > 1 || buf->num_txqs > 1)
3933 return ICE_ERR_MAX_LIMIT;
3937 if (!ice_is_vsi_valid(hw, vsi_handle))
3938 return ICE_ERR_PARAM;
3940 ice_acquire_lock(&pi->sched_lock);
3942 q_ctx = ice_get_lan_q_ctx(hw, vsi_handle, tc, q_handle);
3944 ice_debug(hw, ICE_DBG_SCHED, "Enaq: invalid queue handle %d\n",
3946 status = ICE_ERR_PARAM;
3950 /* find a parent node */
3951 parent = ice_sched_get_free_qparent(pi, vsi_handle, tc,
3952 ICE_SCHED_NODE_OWNER_LAN);
3954 status = ICE_ERR_PARAM;
3958 buf->parent_teid = parent->info.node_teid;
3959 node.parent_teid = parent->info.node_teid;
3960 /* Mark that the values in the "generic" section as valid. The default
3961 * value in the "generic" section is zero. This means that :
3962 * - Scheduling mode is Bytes Per Second (BPS), indicated by Bit 0.
3963 * - 0 priority among siblings, indicated by Bit 1-3.
3964 * - WFQ, indicated by Bit 4.
3965 * - 0 Adjustment value is used in PSM credit update flow, indicated by
3967 * - Bit 7 is reserved.
3968 * Without setting the generic section as valid in valid_sections, the
3969 * Admin queue command will fail with error code ICE_AQ_RC_EINVAL.
3971 buf->txqs[0].info.valid_sections = ICE_AQC_ELEM_VALID_GENERIC;
3973 /* add the LAN queue */
3974 status = ice_aq_add_lan_txq(hw, num_qgrps, buf, buf_size, cd);
3975 if (status != ICE_SUCCESS) {
3976 ice_debug(hw, ICE_DBG_SCHED, "enable queue %d failed %d\n",
3977 LE16_TO_CPU(buf->txqs[0].txq_id),
3978 hw->adminq.sq_last_status);
3982 node.node_teid = buf->txqs[0].q_teid;
3983 node.data.elem_type = ICE_AQC_ELEM_TYPE_LEAF;
3984 q_ctx->q_handle = q_handle;
3985 q_ctx->q_teid = LE32_TO_CPU(node.node_teid);
3987 /* add a leaf node into scheduler tree queue layer */
3988 status = ice_sched_add_node(pi, hw->num_tx_sched_layers - 1, &node);
3990 status = ice_sched_replay_q_bw(pi, q_ctx);
3993 ice_release_lock(&pi->sched_lock);
3999 * @pi: port information structure
4000 * @vsi_handle: software VSI handle
4002 * @num_queues: number of queues
4003 * @q_handles: pointer to software queue handle array
4004 * @q_ids: pointer to the q_id array
4005 * @q_teids: pointer to queue node teids
4006 * @rst_src: if called due to reset, specifies the reset source
4007 * @vmvf_num: the relative VM or VF number that is undergoing the reset
4008 * @cd: pointer to command details structure or NULL
4010 * This function removes queues and their corresponding nodes in SW DB
4013 ice_dis_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u8 num_queues,
4014 u16 *q_handles, u16 *q_ids, u32 *q_teids,
4015 enum ice_disq_rst_src rst_src, u16 vmvf_num,
4016 struct ice_sq_cd *cd)
4018 enum ice_status status = ICE_ERR_DOES_NOT_EXIST;
4019 struct ice_aqc_dis_txq_item qg_list;
4020 struct ice_q_ctx *q_ctx;
4023 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY)
4027 /* if queue is disabled already yet the disable queue command
4028 * has to be sent to complete the VF reset, then call
4029 * ice_aq_dis_lan_txq without any queue information
4032 return ice_aq_dis_lan_txq(pi->hw, 0, NULL, 0, rst_src,
4037 ice_acquire_lock(&pi->sched_lock);
4039 for (i = 0; i < num_queues; i++) {
4040 struct ice_sched_node *node;
4042 node = ice_sched_find_node_by_teid(pi->root, q_teids[i]);
4045 q_ctx = ice_get_lan_q_ctx(pi->hw, vsi_handle, tc, q_handles[i]);
4047 ice_debug(pi->hw, ICE_DBG_SCHED, "invalid queue handle%d\n",
4051 if (q_ctx->q_handle != q_handles[i]) {
4052 ice_debug(pi->hw, ICE_DBG_SCHED, "Err:handles %d %d\n",
4053 q_ctx->q_handle, q_handles[i]);
4056 qg_list.parent_teid = node->info.parent_teid;
4058 qg_list.q_id[0] = CPU_TO_LE16(q_ids[i]);
4059 status = ice_aq_dis_lan_txq(pi->hw, 1, &qg_list,
4060 sizeof(qg_list), rst_src, vmvf_num,
4063 if (status != ICE_SUCCESS)
4065 ice_free_sched_node(pi, node);
4066 q_ctx->q_handle = ICE_INVAL_Q_HANDLE;
4068 ice_release_lock(&pi->sched_lock);
4073 * ice_cfg_vsi_qs - configure the new/existing VSI queues
4074 * @pi: port information structure
4075 * @vsi_handle: software VSI handle
4076 * @tc_bitmap: TC bitmap
4077 * @maxqs: max queues array per TC
4078 * @owner: LAN or RDMA
4080 * This function adds/updates the VSI queues per TC.
4082 static enum ice_status
4083 ice_cfg_vsi_qs(struct ice_port_info *pi, u16 vsi_handle, u16 tc_bitmap,
4084 u16 *maxqs, u8 owner)
4086 enum ice_status status = ICE_SUCCESS;
4089 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY)
4092 if (!ice_is_vsi_valid(pi->hw, vsi_handle))
4093 return ICE_ERR_PARAM;
4095 ice_acquire_lock(&pi->sched_lock);
4097 ice_for_each_traffic_class(i) {
4098 /* configuration is possible only if TC node is present */
4099 if (!ice_sched_get_tc_node(pi, i))
4102 status = ice_sched_cfg_vsi(pi, vsi_handle, i, maxqs[i], owner,
4103 ice_is_tc_ena(tc_bitmap, i));
4108 ice_release_lock(&pi->sched_lock);
4113 * ice_cfg_vsi_lan - configure VSI LAN queues
4114 * @pi: port information structure
4115 * @vsi_handle: software VSI handle
4116 * @tc_bitmap: TC bitmap
4117 * @max_lanqs: max LAN queues array per TC
4119 * This function adds/updates the VSI LAN queues per TC.
4122 ice_cfg_vsi_lan(struct ice_port_info *pi, u16 vsi_handle, u16 tc_bitmap,
4125 return ice_cfg_vsi_qs(pi, vsi_handle, tc_bitmap, max_lanqs,
4126 ICE_SCHED_NODE_OWNER_LAN);
4130 * ice_is_main_vsi - checks whether the VSI is main VSI
4131 * @hw: pointer to the HW struct
4132 * @vsi_handle: VSI handle
4134 * Checks whether the VSI is the main VSI (the first PF VSI created on
4137 static bool ice_is_main_vsi(struct ice_hw *hw, u16 vsi_handle)
4139 return vsi_handle == ICE_MAIN_VSI_HANDLE && hw->vsi_ctx[vsi_handle];
4143 * ice_replay_pre_init - replay pre initialization
4144 * @hw: pointer to the HW struct
4145 * @sw: pointer to switch info struct for which function initializes filters
4147 * Initializes required config data for VSI, FD, ACL, and RSS before replay.
4149 static enum ice_status
4150 ice_replay_pre_init(struct ice_hw *hw, struct ice_switch_info *sw)
4154 /* Delete old entries from replay filter list head if there is any */
4155 ice_rm_sw_replay_rule_info(hw, sw);
4156 /* In start of replay, move entries into replay_rules list, it
4157 * will allow adding rules entries back to filt_rules list,
4158 * which is operational list.
4160 for (i = 0; i < ICE_MAX_NUM_RECIPES; i++)
4161 LIST_REPLACE_INIT(&sw->recp_list[i].filt_rules,
4162 &sw->recp_list[i].filt_replay_rules);
4163 ice_sched_replay_agg_vsi_preinit(hw);
4165 return ice_sched_replay_tc_node_bw(hw->port_info);
4169 * ice_replay_vsi - replay VSI configuration
4170 * @hw: pointer to the HW struct
4171 * @vsi_handle: driver VSI handle
4173 * Restore all VSI configuration after reset. It is required to call this
4174 * function with main VSI first.
4176 enum ice_status ice_replay_vsi(struct ice_hw *hw, u16 vsi_handle)
4178 struct ice_switch_info *sw = hw->switch_info;
4179 struct ice_port_info *pi = hw->port_info;
4180 enum ice_status status;
4182 if (!ice_is_vsi_valid(hw, vsi_handle))
4183 return ICE_ERR_PARAM;
4185 /* Replay pre-initialization if there is any */
4186 if (ice_is_main_vsi(hw, vsi_handle)) {
4187 status = ice_replay_pre_init(hw, sw);
4191 /* Replay per VSI all RSS configurations */
4192 status = ice_replay_rss_cfg(hw, vsi_handle);
4195 /* Replay per VSI all filters */
4196 status = ice_replay_vsi_all_fltr(hw, pi, vsi_handle);
4198 status = ice_replay_vsi_agg(hw, vsi_handle);
4203 * ice_replay_post - post replay configuration cleanup
4204 * @hw: pointer to the HW struct
4206 * Post replay cleanup.
4208 void ice_replay_post(struct ice_hw *hw)
4210 /* Delete old entries from replay filter list head */
4211 ice_rm_all_sw_replay_rule_info(hw);
4212 ice_sched_replay_agg(hw);
4216 * ice_stat_update40 - read 40 bit stat from the chip and update stat values
4217 * @hw: ptr to the hardware info
4218 * @reg: offset of 64 bit HW register to read from
4219 * @prev_stat_loaded: bool to specify if previous stats are loaded
4220 * @prev_stat: ptr to previous loaded stat value
4221 * @cur_stat: ptr to current stat value
4224 ice_stat_update40(struct ice_hw *hw, u32 reg, bool prev_stat_loaded,
4225 u64 *prev_stat, u64 *cur_stat)
4227 u64 new_data = rd64(hw, reg) & (BIT_ULL(40) - 1);
4229 /* device stats are not reset at PFR, they likely will not be zeroed
4230 * when the driver starts. Thus, save the value from the first read
4231 * without adding to the statistic value so that we report stats which
4232 * count up from zero.
4234 if (!prev_stat_loaded) {
4235 *prev_stat = new_data;
4239 /* Calculate the difference between the new and old values, and then
4240 * add it to the software stat value.
4242 if (new_data >= *prev_stat)
4243 *cur_stat += new_data - *prev_stat;
4245 /* to manage the potential roll-over */
4246 *cur_stat += (new_data + BIT_ULL(40)) - *prev_stat;
4248 /* Update the previously stored value to prepare for next read */
4249 *prev_stat = new_data;
4253 * ice_stat_update32 - read 32 bit stat from the chip and update stat values
4254 * @hw: ptr to the hardware info
4255 * @reg: offset of HW register to read from
4256 * @prev_stat_loaded: bool to specify if previous stats are loaded
4257 * @prev_stat: ptr to previous loaded stat value
4258 * @cur_stat: ptr to current stat value
4261 ice_stat_update32(struct ice_hw *hw, u32 reg, bool prev_stat_loaded,
4262 u64 *prev_stat, u64 *cur_stat)
4266 new_data = rd32(hw, reg);
4268 /* device stats are not reset at PFR, they likely will not be zeroed
4269 * when the driver starts. Thus, save the value from the first read
4270 * without adding to the statistic value so that we report stats which
4271 * count up from zero.
4273 if (!prev_stat_loaded) {
4274 *prev_stat = new_data;
4278 /* Calculate the difference between the new and old values, and then
4279 * add it to the software stat value.
4281 if (new_data >= *prev_stat)
4282 *cur_stat += new_data - *prev_stat;
4284 /* to manage the potential roll-over */
4285 *cur_stat += (new_data + BIT_ULL(32)) - *prev_stat;
4287 /* Update the previously stored value to prepare for next read */
4288 *prev_stat = new_data;
4292 * ice_stat_update_repc - read GLV_REPC stats from chip and update stat values
4293 * @hw: ptr to the hardware info
4294 * @vsi_handle: VSI handle
4295 * @prev_stat_loaded: bool to specify if the previous stat values are loaded
4296 * @cur_stats: ptr to current stats structure
4298 * The GLV_REPC statistic register actually tracks two 16bit statistics, and
4299 * thus cannot be read using the normal ice_stat_update32 function.
4301 * Read the GLV_REPC register associated with the given VSI, and update the
4302 * rx_no_desc and rx_error values in the ice_eth_stats structure.
4304 * Because the statistics in GLV_REPC stick at 0xFFFF, the register must be
4305 * cleared each time it's read.
4307 * Note that the GLV_RDPC register also counts the causes that would trigger
4308 * GLV_REPC. However, it does not give the finer grained detail about why the
4309 * packets are being dropped. The GLV_REPC values can be used to distinguish
4310 * whether Rx packets are dropped due to errors or due to no available
4314 ice_stat_update_repc(struct ice_hw *hw, u16 vsi_handle, bool prev_stat_loaded,
4315 struct ice_eth_stats *cur_stats)
4317 u16 vsi_num, no_desc, error_cnt;
4320 if (!ice_is_vsi_valid(hw, vsi_handle))
4323 vsi_num = ice_get_hw_vsi_num(hw, vsi_handle);
4325 /* If we haven't loaded stats yet, just clear the current value */
4326 if (!prev_stat_loaded) {
4327 wr32(hw, GLV_REPC(vsi_num), 0);
4331 repc = rd32(hw, GLV_REPC(vsi_num));
4332 no_desc = (repc & GLV_REPC_NO_DESC_CNT_M) >> GLV_REPC_NO_DESC_CNT_S;
4333 error_cnt = (repc & GLV_REPC_ERROR_CNT_M) >> GLV_REPC_ERROR_CNT_S;
4335 /* Clear the count by writing to the stats register */
4336 wr32(hw, GLV_REPC(vsi_num), 0);
4338 cur_stats->rx_no_desc += no_desc;
4339 cur_stats->rx_errors += error_cnt;
4343 * ice_sched_query_elem - query element information from HW
4344 * @hw: pointer to the HW struct
4345 * @node_teid: node TEID to be queried
4346 * @buf: buffer to element information
4348 * This function queries HW element information
4351 ice_sched_query_elem(struct ice_hw *hw, u32 node_teid,
4352 struct ice_aqc_get_elem *buf)
4354 u16 buf_size, num_elem_ret = 0;
4355 enum ice_status status;
4357 buf_size = sizeof(*buf);
4358 ice_memset(buf, 0, buf_size, ICE_NONDMA_MEM);
4359 buf->generic[0].node_teid = CPU_TO_LE32(node_teid);
4360 status = ice_aq_query_sched_elems(hw, 1, buf, buf_size, &num_elem_ret,
4362 if (status != ICE_SUCCESS || num_elem_ret != 1)
4363 ice_debug(hw, ICE_DBG_SCHED, "query element failed\n");
4368 * ice_get_fw_mode - returns FW mode
4369 * @hw: pointer to the HW struct
4371 enum ice_fw_modes ice_get_fw_mode(struct ice_hw *hw)
4373 #define ICE_FW_MODE_DBG_M BIT(0)
4374 #define ICE_FW_MODE_REC_M BIT(1)
4375 #define ICE_FW_MODE_ROLLBACK_M BIT(2)
4378 /* check the current FW mode */
4379 fw_mode = rd32(hw, GL_MNG_FWSM) & GL_MNG_FWSM_FW_MODES_M;
4381 if (fw_mode & ICE_FW_MODE_DBG_M)
4382 return ICE_FW_MODE_DBG;
4383 else if (fw_mode & ICE_FW_MODE_REC_M)
4384 return ICE_FW_MODE_REC;
4385 else if (fw_mode & ICE_FW_MODE_ROLLBACK_M)
4386 return ICE_FW_MODE_ROLLBACK;
4388 return ICE_FW_MODE_NORMAL;
4392 * ice_fw_supports_link_override
4393 * @hw: pointer to the hardware structure
4395 * Checks if the firmware supports link override
4397 bool ice_fw_supports_link_override(struct ice_hw *hw)
4399 /* Currently, only supported for E810 devices */
4400 if (hw->mac_type != ICE_MAC_E810)
4403 if (hw->api_maj_ver == ICE_FW_API_LINK_OVERRIDE_MAJ) {
4404 if (hw->api_min_ver > ICE_FW_API_LINK_OVERRIDE_MIN)
4406 if (hw->api_min_ver == ICE_FW_API_LINK_OVERRIDE_MIN &&
4407 hw->api_patch >= ICE_FW_API_LINK_OVERRIDE_PATCH)
4409 } else if (hw->api_maj_ver > ICE_FW_API_LINK_OVERRIDE_MAJ) {
4417 * ice_get_link_default_override
4418 * @ldo: pointer to the link default override struct
4419 * @pi: pointer to the port info struct
4421 * Gets the link default override for a port
4424 ice_get_link_default_override(struct ice_link_default_override_tlv *ldo,
4425 struct ice_port_info *pi)
4427 u16 i, tlv, tlv_len, tlv_start, buf, offset;
4428 struct ice_hw *hw = pi->hw;
4429 enum ice_status status;
4431 status = ice_get_pfa_module_tlv(hw, &tlv, &tlv_len,
4432 ICE_SR_LINK_DEFAULT_OVERRIDE_PTR);
4434 ice_debug(hw, ICE_DBG_INIT,
4435 "Failed to read link override TLV.\n");
4439 /* Each port has its own config; calculate for our port */
4440 tlv_start = tlv + pi->lport * ICE_SR_PFA_LINK_OVERRIDE_WORDS +
4441 ICE_SR_PFA_LINK_OVERRIDE_OFFSET;
4443 /* link options first */
4444 status = ice_read_sr_word(hw, tlv_start, &buf);
4446 ice_debug(hw, ICE_DBG_INIT,
4447 "Failed to read override link options.\n");
4450 ldo->options = buf & ICE_LINK_OVERRIDE_OPT_M;
4451 ldo->phy_config = (buf & ICE_LINK_OVERRIDE_PHY_CFG_M) >>
4452 ICE_LINK_OVERRIDE_PHY_CFG_S;
4454 /* link PHY config */
4455 offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_FEC_OFFSET;
4456 status = ice_read_sr_word(hw, offset, &buf);
4458 ice_debug(hw, ICE_DBG_INIT,
4459 "Failed to read override phy config.\n");
4462 ldo->fec_options = buf & ICE_LINK_OVERRIDE_FEC_OPT_M;
4465 offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_PHY_OFFSET;
4466 for (i = 0; i < ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS; i++) {
4467 status = ice_read_sr_word(hw, (offset + i), &buf);
4469 ice_debug(hw, ICE_DBG_INIT,
4470 "Failed to read override link options.\n");
4473 /* shift 16 bits at a time to fill 64 bits */
4474 ldo->phy_type_low |= ((u64)buf << (i * 16));
4477 /* PHY types high */
4478 offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_PHY_OFFSET +
4479 ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS;
4480 for (i = 0; i < ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS; i++) {
4481 status = ice_read_sr_word(hw, (offset + i), &buf);
4483 ice_debug(hw, ICE_DBG_INIT,
4484 "Failed to read override link options.\n");
4487 /* shift 16 bits at a time to fill 64 bits */
4488 ldo->phy_type_high |= ((u64)buf << (i * 16));