1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2001-2019
5 #include "ice_common.h"
7 #include "ice_adminq_cmd.h"
10 #include "ice_switch.h"
12 #define ICE_PF_RESET_WAIT_COUNT 200
14 #define ICE_PROG_FLEX_ENTRY(hw, rxdid, mdid, idx) \
15 wr32((hw), GLFLXP_RXDID_FLX_WRD_##idx(rxdid), \
16 ((ICE_RX_OPC_MDID << \
17 GLFLXP_RXDID_FLX_WRD_##idx##_RXDID_OPCODE_S) & \
18 GLFLXP_RXDID_FLX_WRD_##idx##_RXDID_OPCODE_M) | \
19 (((mdid) << GLFLXP_RXDID_FLX_WRD_##idx##_PROT_MDID_S) & \
20 GLFLXP_RXDID_FLX_WRD_##idx##_PROT_MDID_M))
22 #define ICE_PROG_FLG_ENTRY(hw, rxdid, flg_0, flg_1, flg_2, flg_3, idx) \
23 wr32((hw), GLFLXP_RXDID_FLAGS(rxdid, idx), \
24 (((flg_0) << GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_S) & \
25 GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_M) | \
26 (((flg_1) << GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_1_S) & \
27 GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_1_M) | \
28 (((flg_2) << GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_2_S) & \
29 GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_2_M) | \
30 (((flg_3) << GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_3_S) & \
31 GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_3_M))
35 * ice_set_mac_type - Sets MAC type
36 * @hw: pointer to the HW structure
38 * This function sets the MAC type of the adapter based on the
39 * vendor ID and device ID stored in the HW structure.
41 static enum ice_status ice_set_mac_type(struct ice_hw *hw)
43 enum ice_status status = ICE_SUCCESS;
45 ice_debug(hw, ICE_DBG_TRACE, "ice_set_mac_type\n");
47 if (hw->vendor_id == ICE_INTEL_VENDOR_ID) {
48 switch (hw->device_id) {
50 hw->mac_type = ICE_MAC_GENERIC;
54 status = ICE_ERR_DEVICE_NOT_SUPPORTED;
57 ice_debug(hw, ICE_DBG_INIT, "found mac_type: %d, status: %d\n",
58 hw->mac_type, status);
65 * ice_clear_pf_cfg - Clear PF configuration
66 * @hw: pointer to the hardware structure
68 * Clears any existing PF configuration (VSIs, VSI lists, switch rules, port
69 * configuration, flow director filters, etc.).
71 enum ice_status ice_clear_pf_cfg(struct ice_hw *hw)
73 struct ice_aq_desc desc;
75 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pf_cfg);
77 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
81 * ice_aq_manage_mac_read - manage MAC address read command
82 * @hw: pointer to the HW struct
83 * @buf: a virtual buffer to hold the manage MAC read response
84 * @buf_size: Size of the virtual buffer
85 * @cd: pointer to command details structure or NULL
87 * This function is used to return per PF station MAC address (0x0107).
88 * NOTE: Upon successful completion of this command, MAC address information
89 * is returned in user specified buffer. Please interpret user specified
90 * buffer as "manage_mac_read" response.
91 * Response such as various MAC addresses are stored in HW struct (port.mac)
92 * ice_aq_discover_caps is expected to be called before this function is called.
94 static enum ice_status
95 ice_aq_manage_mac_read(struct ice_hw *hw, void *buf, u16 buf_size,
98 struct ice_aqc_manage_mac_read_resp *resp;
99 struct ice_aqc_manage_mac_read *cmd;
100 struct ice_aq_desc desc;
101 enum ice_status status;
105 cmd = &desc.params.mac_read;
107 if (buf_size < sizeof(*resp))
108 return ICE_ERR_BUF_TOO_SHORT;
110 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_read);
112 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);
116 resp = (struct ice_aqc_manage_mac_read_resp *)buf;
117 flags = LE16_TO_CPU(cmd->flags) & ICE_AQC_MAN_MAC_READ_M;
119 if (!(flags & ICE_AQC_MAN_MAC_LAN_ADDR_VALID)) {
120 ice_debug(hw, ICE_DBG_LAN, "got invalid MAC address\n");
124 /* A single port can report up to two (LAN and WoL) addresses */
125 for (i = 0; i < cmd->num_addr; i++)
126 if (resp[i].addr_type == ICE_AQC_MAN_MAC_ADDR_TYPE_LAN) {
127 ice_memcpy(hw->port_info->mac.lan_addr,
128 resp[i].mac_addr, ETH_ALEN,
130 ice_memcpy(hw->port_info->mac.perm_addr,
132 ETH_ALEN, ICE_DMA_TO_NONDMA);
140 * ice_aq_get_phy_caps - returns PHY capabilities
141 * @pi: port information structure
142 * @qual_mods: report qualified modules
143 * @report_mode: report mode capabilities
144 * @pcaps: structure for PHY capabilities to be filled
145 * @cd: pointer to command details structure or NULL
147 * Returns the various PHY capabilities supported on the Port (0x0600)
150 ice_aq_get_phy_caps(struct ice_port_info *pi, bool qual_mods, u8 report_mode,
151 struct ice_aqc_get_phy_caps_data *pcaps,
152 struct ice_sq_cd *cd)
154 struct ice_aqc_get_phy_caps *cmd;
155 u16 pcaps_size = sizeof(*pcaps);
156 struct ice_aq_desc desc;
157 enum ice_status status;
159 cmd = &desc.params.get_phy;
161 if (!pcaps || (report_mode & ~ICE_AQC_REPORT_MODE_M) || !pi)
162 return ICE_ERR_PARAM;
164 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_phy_caps);
167 cmd->param0 |= CPU_TO_LE16(ICE_AQC_GET_PHY_RQM);
169 cmd->param0 |= CPU_TO_LE16(report_mode);
170 status = ice_aq_send_cmd(pi->hw, &desc, pcaps, pcaps_size, cd);
172 if (status == ICE_SUCCESS && report_mode == ICE_AQC_REPORT_TOPO_CAP) {
173 pi->phy.phy_type_low = LE64_TO_CPU(pcaps->phy_type_low);
174 pi->phy.phy_type_high = LE64_TO_CPU(pcaps->phy_type_high);
181 * ice_get_media_type - Gets media type
182 * @pi: port information structure
184 static enum ice_media_type ice_get_media_type(struct ice_port_info *pi)
186 struct ice_link_status *hw_link_info;
189 return ICE_MEDIA_UNKNOWN;
191 hw_link_info = &pi->phy.link_info;
192 if (hw_link_info->phy_type_low && hw_link_info->phy_type_high)
193 /* If more than one media type is selected, report unknown */
194 return ICE_MEDIA_UNKNOWN;
196 if (hw_link_info->phy_type_low) {
197 switch (hw_link_info->phy_type_low) {
198 case ICE_PHY_TYPE_LOW_1000BASE_SX:
199 case ICE_PHY_TYPE_LOW_1000BASE_LX:
200 case ICE_PHY_TYPE_LOW_10GBASE_SR:
201 case ICE_PHY_TYPE_LOW_10GBASE_LR:
202 case ICE_PHY_TYPE_LOW_10G_SFI_C2C:
203 case ICE_PHY_TYPE_LOW_25GBASE_SR:
204 case ICE_PHY_TYPE_LOW_25GBASE_LR:
205 case ICE_PHY_TYPE_LOW_25G_AUI_C2C:
206 case ICE_PHY_TYPE_LOW_40GBASE_SR4:
207 case ICE_PHY_TYPE_LOW_40GBASE_LR4:
208 case ICE_PHY_TYPE_LOW_50GBASE_SR2:
209 case ICE_PHY_TYPE_LOW_50GBASE_LR2:
210 case ICE_PHY_TYPE_LOW_50GBASE_SR:
211 case ICE_PHY_TYPE_LOW_50GBASE_FR:
212 case ICE_PHY_TYPE_LOW_50GBASE_LR:
213 case ICE_PHY_TYPE_LOW_100GBASE_SR4:
214 case ICE_PHY_TYPE_LOW_100GBASE_LR4:
215 case ICE_PHY_TYPE_LOW_100GBASE_SR2:
216 case ICE_PHY_TYPE_LOW_100GBASE_DR:
217 return ICE_MEDIA_FIBER;
218 case ICE_PHY_TYPE_LOW_100BASE_TX:
219 case ICE_PHY_TYPE_LOW_1000BASE_T:
220 case ICE_PHY_TYPE_LOW_2500BASE_T:
221 case ICE_PHY_TYPE_LOW_5GBASE_T:
222 case ICE_PHY_TYPE_LOW_10GBASE_T:
223 case ICE_PHY_TYPE_LOW_25GBASE_T:
224 return ICE_MEDIA_BASET;
225 case ICE_PHY_TYPE_LOW_10G_SFI_DA:
226 case ICE_PHY_TYPE_LOW_25GBASE_CR:
227 case ICE_PHY_TYPE_LOW_25GBASE_CR_S:
228 case ICE_PHY_TYPE_LOW_25GBASE_CR1:
229 case ICE_PHY_TYPE_LOW_40GBASE_CR4:
230 case ICE_PHY_TYPE_LOW_50GBASE_CR2:
231 case ICE_PHY_TYPE_LOW_50GBASE_CP:
232 case ICE_PHY_TYPE_LOW_100GBASE_CR4:
233 case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4:
234 case ICE_PHY_TYPE_LOW_100GBASE_CP2:
236 case ICE_PHY_TYPE_LOW_1000BASE_KX:
237 case ICE_PHY_TYPE_LOW_2500BASE_KX:
238 case ICE_PHY_TYPE_LOW_2500BASE_X:
239 case ICE_PHY_TYPE_LOW_5GBASE_KR:
240 case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1:
241 case ICE_PHY_TYPE_LOW_25GBASE_KR:
242 case ICE_PHY_TYPE_LOW_25GBASE_KR1:
243 case ICE_PHY_TYPE_LOW_25GBASE_KR_S:
244 case ICE_PHY_TYPE_LOW_40GBASE_KR4:
245 case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4:
246 case ICE_PHY_TYPE_LOW_50GBASE_KR2:
247 case ICE_PHY_TYPE_LOW_100GBASE_KR4:
248 case ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4:
249 return ICE_MEDIA_BACKPLANE;
252 switch (hw_link_info->phy_type_high) {
253 case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4:
254 return ICE_MEDIA_BACKPLANE;
257 return ICE_MEDIA_UNKNOWN;
261 * ice_aq_get_link_info
262 * @pi: port information structure
263 * @ena_lse: enable/disable LinkStatusEvent reporting
264 * @link: pointer to link status structure - optional
265 * @cd: pointer to command details structure or NULL
267 * Get Link Status (0x607). Returns the link status of the adapter.
270 ice_aq_get_link_info(struct ice_port_info *pi, bool ena_lse,
271 struct ice_link_status *link, struct ice_sq_cd *cd)
273 struct ice_aqc_get_link_status_data link_data = { 0 };
274 struct ice_aqc_get_link_status *resp;
275 struct ice_link_status *li_old, *li;
276 enum ice_media_type *hw_media_type;
277 struct ice_fc_info *hw_fc_info;
278 bool tx_pause, rx_pause;
279 struct ice_aq_desc desc;
280 enum ice_status status;
285 return ICE_ERR_PARAM;
287 li_old = &pi->phy.link_info_old;
288 hw_media_type = &pi->phy.media_type;
289 li = &pi->phy.link_info;
290 hw_fc_info = &pi->fc;
292 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_status);
293 cmd_flags = (ena_lse) ? ICE_AQ_LSE_ENA : ICE_AQ_LSE_DIS;
294 resp = &desc.params.get_link_status;
295 resp->cmd_flags = CPU_TO_LE16(cmd_flags);
296 resp->lport_num = pi->lport;
298 status = ice_aq_send_cmd(hw, &desc, &link_data, sizeof(link_data), cd);
300 if (status != ICE_SUCCESS)
303 /* save off old link status information */
306 /* update current link status information */
307 li->link_speed = LE16_TO_CPU(link_data.link_speed);
308 li->phy_type_low = LE64_TO_CPU(link_data.phy_type_low);
309 li->phy_type_high = LE64_TO_CPU(link_data.phy_type_high);
310 *hw_media_type = ice_get_media_type(pi);
311 li->link_info = link_data.link_info;
312 li->an_info = link_data.an_info;
313 li->ext_info = link_data.ext_info;
314 li->max_frame_size = LE16_TO_CPU(link_data.max_frame_size);
315 li->fec_info = link_data.cfg & ICE_AQ_FEC_MASK;
316 li->topo_media_conflict = link_data.topo_media_conflict;
317 li->pacing = link_data.cfg & (ICE_AQ_CFG_PACING_M |
318 ICE_AQ_CFG_PACING_TYPE_M);
321 tx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_TX);
322 rx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_RX);
323 if (tx_pause && rx_pause)
324 hw_fc_info->current_mode = ICE_FC_FULL;
326 hw_fc_info->current_mode = ICE_FC_TX_PAUSE;
328 hw_fc_info->current_mode = ICE_FC_RX_PAUSE;
330 hw_fc_info->current_mode = ICE_FC_NONE;
332 li->lse_ena = !!(resp->cmd_flags & CPU_TO_LE16(ICE_AQ_LSE_IS_ENABLED));
334 ice_debug(hw, ICE_DBG_LINK, "link_speed = 0x%x\n", li->link_speed);
335 ice_debug(hw, ICE_DBG_LINK, "phy_type_low = 0x%llx\n",
336 (unsigned long long)li->phy_type_low);
337 ice_debug(hw, ICE_DBG_LINK, "phy_type_high = 0x%llx\n",
338 (unsigned long long)li->phy_type_high);
339 ice_debug(hw, ICE_DBG_LINK, "media_type = 0x%x\n", *hw_media_type);
340 ice_debug(hw, ICE_DBG_LINK, "link_info = 0x%x\n", li->link_info);
341 ice_debug(hw, ICE_DBG_LINK, "an_info = 0x%x\n", li->an_info);
342 ice_debug(hw, ICE_DBG_LINK, "ext_info = 0x%x\n", li->ext_info);
343 ice_debug(hw, ICE_DBG_LINK, "lse_ena = 0x%x\n", li->lse_ena);
344 ice_debug(hw, ICE_DBG_LINK, "max_frame = 0x%x\n", li->max_frame_size);
345 ice_debug(hw, ICE_DBG_LINK, "pacing = 0x%x\n", li->pacing);
347 /* save link status information */
351 /* flag cleared so calling functions don't call AQ again */
352 pi->phy.get_link_info = false;
358 * ice_init_flex_flags
359 * @hw: pointer to the hardware structure
360 * @prof_id: Rx Descriptor Builder profile ID
362 * Function to initialize Rx flex flags
364 static void ice_init_flex_flags(struct ice_hw *hw, enum ice_rxdid prof_id)
368 /* Flex-flag fields (0-2) are programmed with FLG64 bits with layout:
369 * flexiflags0[5:0] - TCP flags, is_packet_fragmented, is_packet_UDP_GRE
370 * flexiflags1[3:0] - Not used for flag programming
371 * flexiflags2[7:0] - Tunnel and VLAN types
372 * 2 invalid fields in last index
375 /* Rx flex flags are currently programmed for the NIC profiles only.
376 * Different flag bit programming configurations can be added per
379 case ICE_RXDID_FLEX_NIC:
380 case ICE_RXDID_FLEX_NIC_2:
381 ICE_PROG_FLG_ENTRY(hw, prof_id, ICE_FLG_PKT_FRG,
382 ICE_FLG_UDP_GRE, ICE_FLG_PKT_DSI,
384 /* flex flag 1 is not used for flexi-flag programming, skipping
385 * these four FLG64 bits.
387 ICE_PROG_FLG_ENTRY(hw, prof_id, ICE_FLG_SYN, ICE_FLG_RST,
388 ICE_FLG_PKT_DSI, ICE_FLG_PKT_DSI, idx++);
389 ICE_PROG_FLG_ENTRY(hw, prof_id, ICE_FLG_PKT_DSI,
390 ICE_FLG_PKT_DSI, ICE_FLG_EVLAN_x8100,
391 ICE_FLG_EVLAN_x9100, idx++);
392 ICE_PROG_FLG_ENTRY(hw, prof_id, ICE_FLG_VLAN_x8100,
393 ICE_FLG_TNL_VLAN, ICE_FLG_TNL_MAC,
394 ICE_FLG_TNL0, idx++);
395 ICE_PROG_FLG_ENTRY(hw, prof_id, ICE_FLG_TNL1, ICE_FLG_TNL2,
396 ICE_FLG_PKT_DSI, ICE_FLG_PKT_DSI, idx);
400 ice_debug(hw, ICE_DBG_INIT,
401 "Flag programming for profile ID %d not supported\n",
408 * @hw: pointer to the hardware structure
409 * @prof_id: Rx Descriptor Builder profile ID
411 * Function to initialize flex descriptors
413 static void ice_init_flex_flds(struct ice_hw *hw, enum ice_rxdid prof_id)
415 enum ice_flex_mdid mdid;
418 case ICE_RXDID_FLEX_NIC:
419 case ICE_RXDID_FLEX_NIC_2:
420 ICE_PROG_FLEX_ENTRY(hw, prof_id, ICE_MDID_RX_HASH_LOW, 0);
421 ICE_PROG_FLEX_ENTRY(hw, prof_id, ICE_MDID_RX_HASH_HIGH, 1);
422 ICE_PROG_FLEX_ENTRY(hw, prof_id, ICE_MDID_FLOW_ID_LOWER, 2);
424 mdid = (prof_id == ICE_RXDID_FLEX_NIC_2) ?
425 ICE_MDID_SRC_VSI : ICE_MDID_FLOW_ID_HIGH;
427 ICE_PROG_FLEX_ENTRY(hw, prof_id, mdid, 3);
429 ice_init_flex_flags(hw, prof_id);
433 ice_debug(hw, ICE_DBG_INIT,
434 "Field init for profile ID %d not supported\n",
441 * @hw: pointer to the HW struct
442 * @max_frame_size: Maximum Frame Size to be supported
443 * @cd: pointer to command details structure or NULL
445 * Set MAC configuration (0x0603)
448 ice_aq_set_mac_cfg(struct ice_hw *hw, u16 max_frame_size, struct ice_sq_cd *cd)
450 u16 fc_threshold_val, tx_timer_val;
451 struct ice_aqc_set_mac_cfg *cmd;
452 struct ice_port_info *pi;
453 struct ice_aq_desc desc;
454 enum ice_status status;
459 cmd = &desc.params.set_mac_cfg;
461 if (max_frame_size == 0)
462 return ICE_ERR_PARAM;
464 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_mac_cfg);
466 cmd->max_frame_size = CPU_TO_LE16(max_frame_size);
468 /* Retrieve the current data_pacing value in FW*/
469 pi = &hw->port_info[port_num];
471 /* We turn on the get_link_info so that ice_update_link_info(...)
474 pi->phy.get_link_info = 1;
476 status = ice_get_link_status(pi, &link_up);
481 cmd->params = pi->phy.link_info.pacing;
483 /* We read back the transmit timer and fc threshold value of
484 * LFC. Thus, we will use index =
485 * PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX.
487 * Also, because we are opearating on transmit timer and fc
488 * threshold of LFC, we don't turn on any bit in tx_tmr_priority
490 #define IDX_OF_LFC PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX
492 /* Retrieve the transmit timer */
494 PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(IDX_OF_LFC));
495 tx_timer_val = reg_val &
496 PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_HSEC_CTL_TX_PAUSE_QUANTA_M;
497 cmd->tx_tmr_value = CPU_TO_LE16(tx_timer_val);
499 /* Retrieve the fc threshold */
501 PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(IDX_OF_LFC));
502 fc_threshold_val = reg_val & MAKEMASK(0xFFFF, 0);
503 cmd->fc_refresh_threshold = CPU_TO_LE16(fc_threshold_val);
505 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
509 * ice_init_fltr_mgmt_struct - initializes filter management list and locks
510 * @hw: pointer to the HW struct
512 static enum ice_status ice_init_fltr_mgmt_struct(struct ice_hw *hw)
514 struct ice_switch_info *sw;
516 hw->switch_info = (struct ice_switch_info *)
517 ice_malloc(hw, sizeof(*hw->switch_info));
518 sw = hw->switch_info;
521 return ICE_ERR_NO_MEMORY;
523 INIT_LIST_HEAD(&sw->vsi_list_map_head);
525 return ice_init_def_sw_recp(hw);
529 * ice_cleanup_fltr_mgmt_struct - cleanup filter management list and locks
530 * @hw: pointer to the HW struct
532 static void ice_cleanup_fltr_mgmt_struct(struct ice_hw *hw)
534 struct ice_switch_info *sw = hw->switch_info;
535 struct ice_vsi_list_map_info *v_pos_map;
536 struct ice_vsi_list_map_info *v_tmp_map;
537 struct ice_sw_recipe *recps;
540 LIST_FOR_EACH_ENTRY_SAFE(v_pos_map, v_tmp_map, &sw->vsi_list_map_head,
541 ice_vsi_list_map_info, list_entry) {
542 LIST_DEL(&v_pos_map->list_entry);
543 ice_free(hw, v_pos_map);
545 recps = hw->switch_info->recp_list;
546 for (i = 0; i < ICE_MAX_NUM_RECIPES; i++) {
547 recps[i].root_rid = i;
549 if (recps[i].adv_rule) {
550 struct ice_adv_fltr_mgmt_list_entry *tmp_entry;
551 struct ice_adv_fltr_mgmt_list_entry *lst_itr;
553 ice_destroy_lock(&recps[i].filt_rule_lock);
554 LIST_FOR_EACH_ENTRY_SAFE(lst_itr, tmp_entry,
555 &recps[i].filt_rules,
556 ice_adv_fltr_mgmt_list_entry,
558 LIST_DEL(&lst_itr->list_entry);
559 ice_free(hw, lst_itr->lkups);
560 ice_free(hw, lst_itr);
563 struct ice_fltr_mgmt_list_entry *lst_itr, *tmp_entry;
565 ice_destroy_lock(&recps[i].filt_rule_lock);
566 LIST_FOR_EACH_ENTRY_SAFE(lst_itr, tmp_entry,
567 &recps[i].filt_rules,
568 ice_fltr_mgmt_list_entry,
570 LIST_DEL(&lst_itr->list_entry);
571 ice_free(hw, lst_itr);
575 ice_rm_all_sw_replay_rule_info(hw);
576 ice_free(hw, sw->recp_list);
580 #define ICE_FW_LOG_DESC_SIZE(n) (sizeof(struct ice_aqc_fw_logging_data) + \
581 (((n) - 1) * sizeof(((struct ice_aqc_fw_logging_data *)0)->entry)))
582 #define ICE_FW_LOG_DESC_SIZE_MAX \
583 ICE_FW_LOG_DESC_SIZE(ICE_AQC_FW_LOG_ID_MAX)
586 * ice_cfg_fw_log - configure FW logging
587 * @hw: pointer to the HW struct
588 * @enable: enable certain FW logging events if true, disable all if false
590 * This function enables/disables the FW logging via Rx CQ events and a UART
591 * port based on predetermined configurations. FW logging via the Rx CQ can be
592 * enabled/disabled for individual PF's. However, FW logging via the UART can
593 * only be enabled/disabled for all PFs on the same device.
595 * To enable overall FW logging, the "cq_en" and "uart_en" enable bits in
596 * hw->fw_log need to be set accordingly, e.g. based on user-provided input,
597 * before initializing the device.
599 * When re/configuring FW logging, callers need to update the "cfg" elements of
600 * the hw->fw_log.evnts array with the desired logging event configurations for
601 * modules of interest. When disabling FW logging completely, the callers can
602 * just pass false in the "enable" parameter. On completion, the function will
603 * update the "cur" element of the hw->fw_log.evnts array with the resulting
604 * logging event configurations of the modules that are being re/configured. FW
605 * logging modules that are not part of a reconfiguration operation retain their
608 * Before resetting the device, it is recommended that the driver disables FW
609 * logging before shutting down the control queue. When disabling FW logging
610 * ("enable" = false), the latest configurations of FW logging events stored in
611 * hw->fw_log.evnts[] are not overridden to allow them to be reconfigured after
614 * When enabling FW logging to emit log messages via the Rx CQ during the
615 * device's initialization phase, a mechanism alternative to interrupt handlers
616 * needs to be used to extract FW log messages from the Rx CQ periodically and
617 * to prevent the Rx CQ from being full and stalling other types of control
618 * messages from FW to SW. Interrupts are typically disabled during the device's
619 * initialization phase.
621 static enum ice_status ice_cfg_fw_log(struct ice_hw *hw, bool enable)
623 struct ice_aqc_fw_logging_data *data = NULL;
624 struct ice_aqc_fw_logging *cmd;
625 enum ice_status status = ICE_SUCCESS;
626 u16 i, chgs = 0, len = 0;
627 struct ice_aq_desc desc;
631 if (!hw->fw_log.cq_en && !hw->fw_log.uart_en)
634 /* Disable FW logging only when the control queue is still responsive */
636 (!hw->fw_log.actv_evnts || !ice_check_sq_alive(hw, &hw->adminq)))
639 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_fw_logging);
640 cmd = &desc.params.fw_logging;
642 /* Indicate which controls are valid */
643 if (hw->fw_log.cq_en)
644 cmd->log_ctrl_valid |= ICE_AQC_FW_LOG_AQ_VALID;
646 if (hw->fw_log.uart_en)
647 cmd->log_ctrl_valid |= ICE_AQC_FW_LOG_UART_VALID;
650 /* Fill in an array of entries with FW logging modules and
651 * logging events being reconfigured.
653 for (i = 0; i < ICE_AQC_FW_LOG_ID_MAX; i++) {
656 /* Keep track of enabled event types */
657 actv_evnts |= hw->fw_log.evnts[i].cfg;
659 if (hw->fw_log.evnts[i].cfg == hw->fw_log.evnts[i].cur)
663 data = (struct ice_aqc_fw_logging_data *)
665 ICE_FW_LOG_DESC_SIZE_MAX);
667 return ICE_ERR_NO_MEMORY;
670 val = i << ICE_AQC_FW_LOG_ID_S;
671 val |= hw->fw_log.evnts[i].cfg << ICE_AQC_FW_LOG_EN_S;
672 data->entry[chgs++] = CPU_TO_LE16(val);
675 /* Only enable FW logging if at least one module is specified.
676 * If FW logging is currently enabled but all modules are not
677 * enabled to emit log messages, disable FW logging altogether.
680 /* Leave if there is effectively no change */
684 if (hw->fw_log.cq_en)
685 cmd->log_ctrl |= ICE_AQC_FW_LOG_AQ_EN;
687 if (hw->fw_log.uart_en)
688 cmd->log_ctrl |= ICE_AQC_FW_LOG_UART_EN;
691 len = ICE_FW_LOG_DESC_SIZE(chgs);
692 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
696 status = ice_aq_send_cmd(hw, &desc, buf, len, NULL);
698 /* Update the current configuration to reflect events enabled.
699 * hw->fw_log.cq_en and hw->fw_log.uart_en indicate if the FW
700 * logging mode is enabled for the device. They do not reflect
701 * actual modules being enabled to emit log messages. So, their
702 * values remain unchanged even when all modules are disabled.
704 u16 cnt = enable ? chgs : (u16)ICE_AQC_FW_LOG_ID_MAX;
706 hw->fw_log.actv_evnts = actv_evnts;
707 for (i = 0; i < cnt; i++) {
711 /* When disabling all FW logging events as part
712 * of device's de-initialization, the original
713 * configurations are retained, and can be used
714 * to reconfigure FW logging later if the device
717 hw->fw_log.evnts[i].cur = 0;
721 v = LE16_TO_CPU(data->entry[i]);
722 m = (v & ICE_AQC_FW_LOG_ID_M) >> ICE_AQC_FW_LOG_ID_S;
723 hw->fw_log.evnts[m].cur = hw->fw_log.evnts[m].cfg;
736 * @hw: pointer to the HW struct
737 * @desc: pointer to the AQ message descriptor
738 * @buf: pointer to the buffer accompanying the AQ message
740 * Formats a FW Log message and outputs it via the standard driver logs.
742 void ice_output_fw_log(struct ice_hw *hw, struct ice_aq_desc *desc, void *buf)
744 ice_debug(hw, ICE_DBG_AQ_MSG, "[ FW Log Msg Start ]\n");
745 ice_debug_array(hw, ICE_DBG_AQ_MSG, 16, 1, (u8 *)buf,
746 LE16_TO_CPU(desc->datalen));
747 ice_debug(hw, ICE_DBG_AQ_MSG, "[ FW Log Msg End ]\n");
751 * ice_get_itr_intrl_gran - determine int/intrl granularity
752 * @hw: pointer to the HW struct
754 * Determines the itr/intrl granularities based on the maximum aggregate
755 * bandwidth according to the device's configuration during power-on.
757 static void ice_get_itr_intrl_gran(struct ice_hw *hw)
759 u8 max_agg_bw = (rd32(hw, GL_PWR_MODE_CTL) &
760 GL_PWR_MODE_CTL_CAR_MAX_BW_M) >>
761 GL_PWR_MODE_CTL_CAR_MAX_BW_S;
763 switch (max_agg_bw) {
764 case ICE_MAX_AGG_BW_200G:
765 case ICE_MAX_AGG_BW_100G:
766 case ICE_MAX_AGG_BW_50G:
767 hw->itr_gran = ICE_ITR_GRAN_ABOVE_25;
768 hw->intrl_gran = ICE_INTRL_GRAN_ABOVE_25;
770 case ICE_MAX_AGG_BW_25G:
771 hw->itr_gran = ICE_ITR_GRAN_MAX_25;
772 hw->intrl_gran = ICE_INTRL_GRAN_MAX_25;
778 * ice_init_hw - main hardware initialization routine
779 * @hw: pointer to the hardware structure
781 enum ice_status ice_init_hw(struct ice_hw *hw)
783 struct ice_aqc_get_phy_caps_data *pcaps;
784 enum ice_status status;
788 ice_debug(hw, ICE_DBG_TRACE, "ice_init_hw");
791 /* Set MAC type based on DeviceID */
792 status = ice_set_mac_type(hw);
796 hw->pf_id = (u8)(rd32(hw, PF_FUNC_RID) &
797 PF_FUNC_RID_FUNCTION_NUMBER_M) >>
798 PF_FUNC_RID_FUNCTION_NUMBER_S;
801 status = ice_reset(hw, ICE_RESET_PFR);
805 ice_get_itr_intrl_gran(hw);
808 status = ice_init_all_ctrlq(hw);
810 goto err_unroll_cqinit;
812 /* Enable FW logging. Not fatal if this fails. */
813 status = ice_cfg_fw_log(hw, true);
815 ice_debug(hw, ICE_DBG_INIT, "Failed to enable FW logging.\n");
817 status = ice_clear_pf_cfg(hw);
819 goto err_unroll_cqinit;
821 /* Set bit to enable Flow Director filters */
822 wr32(hw, PFQF_FD_ENA, PFQF_FD_ENA_FD_ENA_M);
823 INIT_LIST_HEAD(&hw->fdir_list_head);
825 ice_clear_pxe_mode(hw);
827 status = ice_init_nvm(hw);
829 goto err_unroll_cqinit;
831 status = ice_get_caps(hw);
833 goto err_unroll_cqinit;
835 hw->port_info = (struct ice_port_info *)
836 ice_malloc(hw, sizeof(*hw->port_info));
837 if (!hw->port_info) {
838 status = ICE_ERR_NO_MEMORY;
839 goto err_unroll_cqinit;
842 /* set the back pointer to HW */
843 hw->port_info->hw = hw;
845 /* Initialize port_info struct with switch configuration data */
846 status = ice_get_initial_sw_cfg(hw);
848 goto err_unroll_alloc;
852 /* Query the allocated resources for Tx scheduler */
853 status = ice_sched_query_res_alloc(hw);
855 ice_debug(hw, ICE_DBG_SCHED,
856 "Failed to get scheduler allocated resources\n");
857 goto err_unroll_alloc;
861 /* Initialize port_info struct with scheduler data */
862 status = ice_sched_init_port(hw->port_info);
864 goto err_unroll_sched;
866 pcaps = (struct ice_aqc_get_phy_caps_data *)
867 ice_malloc(hw, sizeof(*pcaps));
869 status = ICE_ERR_NO_MEMORY;
870 goto err_unroll_sched;
873 /* Initialize port_info struct with PHY capabilities */
874 status = ice_aq_get_phy_caps(hw->port_info, false,
875 ICE_AQC_REPORT_TOPO_CAP, pcaps, NULL);
878 goto err_unroll_sched;
880 /* Initialize port_info struct with link information */
881 status = ice_aq_get_link_info(hw->port_info, false, NULL, NULL);
883 goto err_unroll_sched;
884 /* need a valid SW entry point to build a Tx tree */
885 if (!hw->sw_entry_point_layer) {
886 ice_debug(hw, ICE_DBG_SCHED, "invalid sw entry point\n");
887 status = ICE_ERR_CFG;
888 goto err_unroll_sched;
890 INIT_LIST_HEAD(&hw->agg_list);
891 /* Initialize max burst size */
892 if (!hw->max_burst_size)
893 ice_cfg_rl_burst_size(hw, ICE_SCHED_DFLT_BURST_SIZE);
895 status = ice_init_fltr_mgmt_struct(hw);
897 goto err_unroll_sched;
900 /* Get MAC information */
901 /* A single port can report up to two (LAN and WoL) addresses */
902 mac_buf = ice_calloc(hw, 2,
903 sizeof(struct ice_aqc_manage_mac_read_resp));
904 mac_buf_len = 2 * sizeof(struct ice_aqc_manage_mac_read_resp);
907 status = ICE_ERR_NO_MEMORY;
908 goto err_unroll_fltr_mgmt_struct;
911 status = ice_aq_manage_mac_read(hw, mac_buf, mac_buf_len, NULL);
912 ice_free(hw, mac_buf);
915 goto err_unroll_fltr_mgmt_struct;
917 ice_init_flex_flds(hw, ICE_RXDID_FLEX_NIC);
918 ice_init_flex_flds(hw, ICE_RXDID_FLEX_NIC_2);
920 /* Obtain counter base index which would be used by flow director */
921 status = ice_alloc_fd_res_cntr(hw, &hw->fd_ctr_base);
923 goto err_unroll_fltr_mgmt_struct;
927 err_unroll_fltr_mgmt_struct:
928 ice_cleanup_fltr_mgmt_struct(hw);
930 ice_sched_cleanup_all(hw);
932 ice_free(hw, hw->port_info);
933 hw->port_info = NULL;
935 ice_shutdown_all_ctrlq(hw);
940 * ice_deinit_hw - unroll initialization operations done by ice_init_hw
941 * @hw: pointer to the hardware structure
943 * This should be called only during nominal operation, not as a result of
944 * ice_init_hw() failing since ice_init_hw() will take care of unrolling
945 * applicable initializations if it fails for any reason.
947 void ice_deinit_hw(struct ice_hw *hw)
949 ice_free_fd_res_cntr(hw, hw->fd_ctr_base);
950 ice_cleanup_fltr_mgmt_struct(hw);
952 ice_sched_cleanup_all(hw);
953 ice_sched_clear_agg(hw);
957 ice_free(hw, hw->port_info);
958 hw->port_info = NULL;
961 /* Attempt to disable FW logging before shutting down control queues */
962 ice_cfg_fw_log(hw, false);
963 ice_shutdown_all_ctrlq(hw);
965 /* Clear VSI contexts if not already cleared */
966 ice_clear_all_vsi_ctx(hw);
970 * ice_check_reset - Check to see if a global reset is complete
971 * @hw: pointer to the hardware structure
973 enum ice_status ice_check_reset(struct ice_hw *hw)
975 u32 cnt, reg = 0, grst_delay;
977 /* Poll for Device Active state in case a recent CORER, GLOBR,
978 * or EMPR has occurred. The grst delay value is in 100ms units.
979 * Add 1sec for outstanding AQ commands that can take a long time.
981 #define GLGEN_RSTCTL 0x000B8180 /* Reset Source: POR */
982 #define GLGEN_RSTCTL_GRSTDEL_S 0
983 #define GLGEN_RSTCTL_GRSTDEL_M MAKEMASK(0x3F, GLGEN_RSTCTL_GRSTDEL_S)
984 grst_delay = ((rd32(hw, GLGEN_RSTCTL) & GLGEN_RSTCTL_GRSTDEL_M) >>
985 GLGEN_RSTCTL_GRSTDEL_S) + 10;
987 for (cnt = 0; cnt < grst_delay; cnt++) {
988 ice_msec_delay(100, true);
989 reg = rd32(hw, GLGEN_RSTAT);
990 if (!(reg & GLGEN_RSTAT_DEVSTATE_M))
994 if (cnt == grst_delay) {
995 ice_debug(hw, ICE_DBG_INIT,
996 "Global reset polling failed to complete.\n");
997 return ICE_ERR_RESET_FAILED;
1000 #define ICE_RESET_DONE_MASK (GLNVM_ULD_CORER_DONE_M | \
1001 GLNVM_ULD_GLOBR_DONE_M)
1003 /* Device is Active; check Global Reset processes are done */
1004 for (cnt = 0; cnt < ICE_PF_RESET_WAIT_COUNT; cnt++) {
1005 reg = rd32(hw, GLNVM_ULD) & ICE_RESET_DONE_MASK;
1006 if (reg == ICE_RESET_DONE_MASK) {
1007 ice_debug(hw, ICE_DBG_INIT,
1008 "Global reset processes done. %d\n", cnt);
1011 ice_msec_delay(10, true);
1014 if (cnt == ICE_PF_RESET_WAIT_COUNT) {
1015 ice_debug(hw, ICE_DBG_INIT,
1016 "Wait for Reset Done timed out. GLNVM_ULD = 0x%x\n",
1018 return ICE_ERR_RESET_FAILED;
1025 * ice_pf_reset - Reset the PF
1026 * @hw: pointer to the hardware structure
1028 * If a global reset has been triggered, this function checks
1029 * for its completion and then issues the PF reset
1031 static enum ice_status ice_pf_reset(struct ice_hw *hw)
1035 /* If at function entry a global reset was already in progress, i.e.
1036 * state is not 'device active' or any of the reset done bits are not
1037 * set in GLNVM_ULD, there is no need for a PF Reset; poll until the
1038 * global reset is done.
1040 if ((rd32(hw, GLGEN_RSTAT) & GLGEN_RSTAT_DEVSTATE_M) ||
1041 (rd32(hw, GLNVM_ULD) & ICE_RESET_DONE_MASK) ^ ICE_RESET_DONE_MASK) {
1042 /* poll on global reset currently in progress until done */
1043 if (ice_check_reset(hw))
1044 return ICE_ERR_RESET_FAILED;
1050 reg = rd32(hw, PFGEN_CTRL);
1052 wr32(hw, PFGEN_CTRL, (reg | PFGEN_CTRL_PFSWR_M));
1054 for (cnt = 0; cnt < ICE_PF_RESET_WAIT_COUNT; cnt++) {
1055 reg = rd32(hw, PFGEN_CTRL);
1056 if (!(reg & PFGEN_CTRL_PFSWR_M))
1059 ice_msec_delay(1, true);
1062 if (cnt == ICE_PF_RESET_WAIT_COUNT) {
1063 ice_debug(hw, ICE_DBG_INIT,
1064 "PF reset polling failed to complete.\n");
1065 return ICE_ERR_RESET_FAILED;
1072 * ice_reset - Perform different types of reset
1073 * @hw: pointer to the hardware structure
1074 * @req: reset request
1076 * This function triggers a reset as specified by the req parameter.
1079 * If anything other than a PF reset is triggered, PXE mode is restored.
1080 * This has to be cleared using ice_clear_pxe_mode again, once the AQ
1081 * interface has been restored in the rebuild flow.
1083 enum ice_status ice_reset(struct ice_hw *hw, enum ice_reset_req req)
1089 return ice_pf_reset(hw);
1090 case ICE_RESET_CORER:
1091 ice_debug(hw, ICE_DBG_INIT, "CoreR requested\n");
1092 val = GLGEN_RTRIG_CORER_M;
1094 case ICE_RESET_GLOBR:
1095 ice_debug(hw, ICE_DBG_INIT, "GlobalR requested\n");
1096 val = GLGEN_RTRIG_GLOBR_M;
1099 return ICE_ERR_PARAM;
1102 val |= rd32(hw, GLGEN_RTRIG);
1103 wr32(hw, GLGEN_RTRIG, val);
1107 /* wait for the FW to be ready */
1108 return ice_check_reset(hw);
1114 * ice_copy_rxq_ctx_to_hw
1115 * @hw: pointer to the hardware structure
1116 * @ice_rxq_ctx: pointer to the rxq context
1117 * @rxq_index: the index of the Rx queue
1119 * Copies rxq context from dense structure to HW register space
1121 static enum ice_status
1122 ice_copy_rxq_ctx_to_hw(struct ice_hw *hw, u8 *ice_rxq_ctx, u32 rxq_index)
1127 return ICE_ERR_BAD_PTR;
1129 if (rxq_index > QRX_CTRL_MAX_INDEX)
1130 return ICE_ERR_PARAM;
1132 /* Copy each dword separately to HW */
1133 for (i = 0; i < ICE_RXQ_CTX_SIZE_DWORDS; i++) {
1134 wr32(hw, QRX_CONTEXT(i, rxq_index),
1135 *((u32 *)(ice_rxq_ctx + (i * sizeof(u32)))));
1137 ice_debug(hw, ICE_DBG_QCTX, "qrxdata[%d]: %08X\n", i,
1138 *((u32 *)(ice_rxq_ctx + (i * sizeof(u32)))));
1144 /* LAN Rx Queue Context */
1145 static const struct ice_ctx_ele ice_rlan_ctx_info[] = {
1146 /* Field Width LSB */
1147 ICE_CTX_STORE(ice_rlan_ctx, head, 13, 0),
1148 ICE_CTX_STORE(ice_rlan_ctx, cpuid, 8, 13),
1149 ICE_CTX_STORE(ice_rlan_ctx, base, 57, 32),
1150 ICE_CTX_STORE(ice_rlan_ctx, qlen, 13, 89),
1151 ICE_CTX_STORE(ice_rlan_ctx, dbuf, 7, 102),
1152 ICE_CTX_STORE(ice_rlan_ctx, hbuf, 5, 109),
1153 ICE_CTX_STORE(ice_rlan_ctx, dtype, 2, 114),
1154 ICE_CTX_STORE(ice_rlan_ctx, dsize, 1, 116),
1155 ICE_CTX_STORE(ice_rlan_ctx, crcstrip, 1, 117),
1156 ICE_CTX_STORE(ice_rlan_ctx, l2tsel, 1, 119),
1157 ICE_CTX_STORE(ice_rlan_ctx, hsplit_0, 4, 120),
1158 ICE_CTX_STORE(ice_rlan_ctx, hsplit_1, 2, 124),
1159 ICE_CTX_STORE(ice_rlan_ctx, showiv, 1, 127),
1160 ICE_CTX_STORE(ice_rlan_ctx, rxmax, 14, 174),
1161 ICE_CTX_STORE(ice_rlan_ctx, tphrdesc_ena, 1, 193),
1162 ICE_CTX_STORE(ice_rlan_ctx, tphwdesc_ena, 1, 194),
1163 ICE_CTX_STORE(ice_rlan_ctx, tphdata_ena, 1, 195),
1164 ICE_CTX_STORE(ice_rlan_ctx, tphhead_ena, 1, 196),
1165 ICE_CTX_STORE(ice_rlan_ctx, lrxqthresh, 3, 198),
1171 * @hw: pointer to the hardware structure
1172 * @rlan_ctx: pointer to the rxq context
1173 * @rxq_index: the index of the Rx queue
1175 * Converts rxq context from sparse to dense structure and then writes
1176 * it to HW register space
1179 ice_write_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx,
1182 u8 ctx_buf[ICE_RXQ_CTX_SZ] = { 0 };
1184 ice_set_ctx((u8 *)rlan_ctx, ctx_buf, ice_rlan_ctx_info);
1185 return ice_copy_rxq_ctx_to_hw(hw, ctx_buf, rxq_index);
1188 #if !defined(NO_UNUSED_CTX_CODE) || defined(AE_DRIVER)
1191 * @hw: pointer to the hardware structure
1192 * @rxq_index: the index of the Rx queue to clear
1194 * Clears rxq context in HW register space
1196 enum ice_status ice_clear_rxq_ctx(struct ice_hw *hw, u32 rxq_index)
1200 if (rxq_index > QRX_CTRL_MAX_INDEX)
1201 return ICE_ERR_PARAM;
1203 /* Clear each dword register separately */
1204 for (i = 0; i < ICE_RXQ_CTX_SIZE_DWORDS; i++)
1205 wr32(hw, QRX_CONTEXT(i, rxq_index), 0);
1209 #endif /* !NO_UNUSED_CTX_CODE || AE_DRIVER */
1211 /* LAN Tx Queue Context */
1212 const struct ice_ctx_ele ice_tlan_ctx_info[] = {
1213 /* Field Width LSB */
1214 ICE_CTX_STORE(ice_tlan_ctx, base, 57, 0),
1215 ICE_CTX_STORE(ice_tlan_ctx, port_num, 3, 57),
1216 ICE_CTX_STORE(ice_tlan_ctx, cgd_num, 5, 60),
1217 ICE_CTX_STORE(ice_tlan_ctx, pf_num, 3, 65),
1218 ICE_CTX_STORE(ice_tlan_ctx, vmvf_num, 10, 68),
1219 ICE_CTX_STORE(ice_tlan_ctx, vmvf_type, 2, 78),
1220 ICE_CTX_STORE(ice_tlan_ctx, src_vsi, 10, 80),
1221 ICE_CTX_STORE(ice_tlan_ctx, tsyn_ena, 1, 90),
1222 ICE_CTX_STORE(ice_tlan_ctx, alt_vlan, 1, 92),
1223 ICE_CTX_STORE(ice_tlan_ctx, cpuid, 8, 93),
1224 ICE_CTX_STORE(ice_tlan_ctx, wb_mode, 1, 101),
1225 ICE_CTX_STORE(ice_tlan_ctx, tphrd_desc, 1, 102),
1226 ICE_CTX_STORE(ice_tlan_ctx, tphrd, 1, 103),
1227 ICE_CTX_STORE(ice_tlan_ctx, tphwr_desc, 1, 104),
1228 ICE_CTX_STORE(ice_tlan_ctx, cmpq_id, 9, 105),
1229 ICE_CTX_STORE(ice_tlan_ctx, qnum_in_func, 14, 114),
1230 ICE_CTX_STORE(ice_tlan_ctx, itr_notification_mode, 1, 128),
1231 ICE_CTX_STORE(ice_tlan_ctx, adjust_prof_id, 6, 129),
1232 ICE_CTX_STORE(ice_tlan_ctx, qlen, 13, 135),
1233 ICE_CTX_STORE(ice_tlan_ctx, quanta_prof_idx, 4, 148),
1234 ICE_CTX_STORE(ice_tlan_ctx, tso_ena, 1, 152),
1235 ICE_CTX_STORE(ice_tlan_ctx, tso_qnum, 11, 153),
1236 ICE_CTX_STORE(ice_tlan_ctx, legacy_int, 1, 164),
1237 ICE_CTX_STORE(ice_tlan_ctx, drop_ena, 1, 165),
1238 ICE_CTX_STORE(ice_tlan_ctx, cache_prof_idx, 2, 166),
1239 ICE_CTX_STORE(ice_tlan_ctx, pkt_shaper_prof_idx, 3, 168),
1240 ICE_CTX_STORE(ice_tlan_ctx, int_q_state, 110, 171),
1244 #if !defined(NO_UNUSED_CTX_CODE) || defined(AE_DRIVER)
1246 * ice_copy_tx_cmpltnq_ctx_to_hw
1247 * @hw: pointer to the hardware structure
1248 * @ice_tx_cmpltnq_ctx: pointer to the Tx completion queue context
1249 * @tx_cmpltnq_index: the index of the completion queue
1251 * Copies Tx completion queue context from dense structure to HW register space
1253 static enum ice_status
1254 ice_copy_tx_cmpltnq_ctx_to_hw(struct ice_hw *hw, u8 *ice_tx_cmpltnq_ctx,
1255 u32 tx_cmpltnq_index)
1259 if (!ice_tx_cmpltnq_ctx)
1260 return ICE_ERR_BAD_PTR;
1262 if (tx_cmpltnq_index > GLTCLAN_CQ_CNTX0_MAX_INDEX)
1263 return ICE_ERR_PARAM;
1265 /* Copy each dword separately to HW */
1266 for (i = 0; i < ICE_TX_CMPLTNQ_CTX_SIZE_DWORDS; i++) {
1267 wr32(hw, GLTCLAN_CQ_CNTX(i, tx_cmpltnq_index),
1268 *((u32 *)(ice_tx_cmpltnq_ctx + (i * sizeof(u32)))));
1270 ice_debug(hw, ICE_DBG_QCTX, "cmpltnqdata[%d]: %08X\n", i,
1271 *((u32 *)(ice_tx_cmpltnq_ctx + (i * sizeof(u32)))));
1277 /* LAN Tx Completion Queue Context */
1278 static const struct ice_ctx_ele ice_tx_cmpltnq_ctx_info[] = {
1279 /* Field Width LSB */
1280 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, base, 57, 0),
1281 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, q_len, 18, 64),
1282 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, generation, 1, 96),
1283 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, wrt_ptr, 22, 97),
1284 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, pf_num, 3, 128),
1285 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, vmvf_num, 10, 131),
1286 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, vmvf_type, 2, 141),
1287 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, tph_desc_wr, 1, 160),
1288 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, cpuid, 8, 161),
1289 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, cmpltn_cache, 512, 192),
1294 * ice_write_tx_cmpltnq_ctx
1295 * @hw: pointer to the hardware structure
1296 * @tx_cmpltnq_ctx: pointer to the completion queue context
1297 * @tx_cmpltnq_index: the index of the completion queue
1299 * Converts completion queue context from sparse to dense structure and then
1300 * writes it to HW register space
1303 ice_write_tx_cmpltnq_ctx(struct ice_hw *hw,
1304 struct ice_tx_cmpltnq_ctx *tx_cmpltnq_ctx,
1305 u32 tx_cmpltnq_index)
1307 u8 ctx_buf[ICE_TX_CMPLTNQ_CTX_SIZE_DWORDS * sizeof(u32)] = { 0 };
1309 ice_set_ctx((u8 *)tx_cmpltnq_ctx, ctx_buf, ice_tx_cmpltnq_ctx_info);
1310 return ice_copy_tx_cmpltnq_ctx_to_hw(hw, ctx_buf, tx_cmpltnq_index);
1314 * ice_clear_tx_cmpltnq_ctx
1315 * @hw: pointer to the hardware structure
1316 * @tx_cmpltnq_index: the index of the completion queue to clear
1318 * Clears Tx completion queue context in HW register space
1321 ice_clear_tx_cmpltnq_ctx(struct ice_hw *hw, u32 tx_cmpltnq_index)
1325 if (tx_cmpltnq_index > GLTCLAN_CQ_CNTX0_MAX_INDEX)
1326 return ICE_ERR_PARAM;
1328 /* Clear each dword register separately */
1329 for (i = 0; i < ICE_TX_CMPLTNQ_CTX_SIZE_DWORDS; i++)
1330 wr32(hw, GLTCLAN_CQ_CNTX(i, tx_cmpltnq_index), 0);
1336 * ice_copy_tx_drbell_q_ctx_to_hw
1337 * @hw: pointer to the hardware structure
1338 * @ice_tx_drbell_q_ctx: pointer to the doorbell queue context
1339 * @tx_drbell_q_index: the index of the doorbell queue
1341 * Copies doorbell queue context from dense structure to HW register space
1343 static enum ice_status
1344 ice_copy_tx_drbell_q_ctx_to_hw(struct ice_hw *hw, u8 *ice_tx_drbell_q_ctx,
1345 u32 tx_drbell_q_index)
1349 if (!ice_tx_drbell_q_ctx)
1350 return ICE_ERR_BAD_PTR;
1352 if (tx_drbell_q_index > QTX_COMM_DBLQ_DBELL_MAX_INDEX)
1353 return ICE_ERR_PARAM;
1355 /* Copy each dword separately to HW */
1356 for (i = 0; i < ICE_TX_DRBELL_Q_CTX_SIZE_DWORDS; i++) {
1357 wr32(hw, QTX_COMM_DBLQ_CNTX(i, tx_drbell_q_index),
1358 *((u32 *)(ice_tx_drbell_q_ctx + (i * sizeof(u32)))));
1360 ice_debug(hw, ICE_DBG_QCTX, "tx_drbell_qdata[%d]: %08X\n", i,
1361 *((u32 *)(ice_tx_drbell_q_ctx + (i * sizeof(u32)))));
1367 /* LAN Tx Doorbell Queue Context info */
1368 static const struct ice_ctx_ele ice_tx_drbell_q_ctx_info[] = {
1369 /* Field Width LSB */
1370 ICE_CTX_STORE(ice_tx_drbell_q_ctx, base, 57, 0),
1371 ICE_CTX_STORE(ice_tx_drbell_q_ctx, ring_len, 13, 64),
1372 ICE_CTX_STORE(ice_tx_drbell_q_ctx, pf_num, 3, 80),
1373 ICE_CTX_STORE(ice_tx_drbell_q_ctx, vf_num, 8, 84),
1374 ICE_CTX_STORE(ice_tx_drbell_q_ctx, vmvf_type, 2, 94),
1375 ICE_CTX_STORE(ice_tx_drbell_q_ctx, cpuid, 8, 96),
1376 ICE_CTX_STORE(ice_tx_drbell_q_ctx, tph_desc_rd, 1, 104),
1377 ICE_CTX_STORE(ice_tx_drbell_q_ctx, tph_desc_wr, 1, 108),
1378 ICE_CTX_STORE(ice_tx_drbell_q_ctx, db_q_en, 1, 112),
1379 ICE_CTX_STORE(ice_tx_drbell_q_ctx, rd_head, 13, 128),
1380 ICE_CTX_STORE(ice_tx_drbell_q_ctx, rd_tail, 13, 144),
1385 * ice_write_tx_drbell_q_ctx
1386 * @hw: pointer to the hardware structure
1387 * @tx_drbell_q_ctx: pointer to the doorbell queue context
1388 * @tx_drbell_q_index: the index of the doorbell queue
1390 * Converts doorbell queue context from sparse to dense structure and then
1391 * writes it to HW register space
1394 ice_write_tx_drbell_q_ctx(struct ice_hw *hw,
1395 struct ice_tx_drbell_q_ctx *tx_drbell_q_ctx,
1396 u32 tx_drbell_q_index)
1398 u8 ctx_buf[ICE_TX_DRBELL_Q_CTX_SIZE_DWORDS * sizeof(u32)] = { 0 };
1400 ice_set_ctx((u8 *)tx_drbell_q_ctx, ctx_buf, ice_tx_drbell_q_ctx_info);
1401 return ice_copy_tx_drbell_q_ctx_to_hw(hw, ctx_buf, tx_drbell_q_index);
1405 * ice_clear_tx_drbell_q_ctx
1406 * @hw: pointer to the hardware structure
1407 * @tx_drbell_q_index: the index of the doorbell queue to clear
1409 * Clears doorbell queue context in HW register space
1412 ice_clear_tx_drbell_q_ctx(struct ice_hw *hw, u32 tx_drbell_q_index)
1416 if (tx_drbell_q_index > QTX_COMM_DBLQ_DBELL_MAX_INDEX)
1417 return ICE_ERR_PARAM;
1419 /* Clear each dword register separately */
1420 for (i = 0; i < ICE_TX_DRBELL_Q_CTX_SIZE_DWORDS; i++)
1421 wr32(hw, QTX_COMM_DBLQ_CNTX(i, tx_drbell_q_index), 0);
1425 #endif /* !NO_UNUSED_CTX_CODE || AE_DRIVER */
1429 * @hw: pointer to the hardware structure
1431 * @desc: pointer to control queue descriptor
1432 * @buf: pointer to command buffer
1433 * @buf_len: max length of buf
1435 * Dumps debug log about control command with descriptor contents.
1438 ice_debug_cq(struct ice_hw *hw, u32 mask, void *desc, void *buf, u16 buf_len)
1440 struct ice_aq_desc *cq_desc = (struct ice_aq_desc *)desc;
1443 if (!(mask & hw->debug_mask))
1449 len = LE16_TO_CPU(cq_desc->datalen);
1452 "CQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
1453 LE16_TO_CPU(cq_desc->opcode),
1454 LE16_TO_CPU(cq_desc->flags),
1455 LE16_TO_CPU(cq_desc->datalen), LE16_TO_CPU(cq_desc->retval));
1456 ice_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n",
1457 LE32_TO_CPU(cq_desc->cookie_high),
1458 LE32_TO_CPU(cq_desc->cookie_low));
1459 ice_debug(hw, mask, "\tparam (0,1) 0x%08X 0x%08X\n",
1460 LE32_TO_CPU(cq_desc->params.generic.param0),
1461 LE32_TO_CPU(cq_desc->params.generic.param1));
1462 ice_debug(hw, mask, "\taddr (h,l) 0x%08X 0x%08X\n",
1463 LE32_TO_CPU(cq_desc->params.generic.addr_high),
1464 LE32_TO_CPU(cq_desc->params.generic.addr_low));
1465 if (buf && cq_desc->datalen != 0) {
1466 ice_debug(hw, mask, "Buffer:\n");
1470 ice_debug_array(hw, mask, 16, 1, (u8 *)buf, len);
1475 /* FW Admin Queue command wrappers */
1478 * ice_aq_send_cmd - send FW Admin Queue command to FW Admin Queue
1479 * @hw: pointer to the HW struct
1480 * @desc: descriptor describing the command
1481 * @buf: buffer to use for indirect commands (NULL for direct commands)
1482 * @buf_size: size of buffer for indirect commands (0 for direct commands)
1483 * @cd: pointer to command details structure
1485 * Helper function to send FW Admin Queue commands to the FW Admin Queue.
1488 ice_aq_send_cmd(struct ice_hw *hw, struct ice_aq_desc *desc, void *buf,
1489 u16 buf_size, struct ice_sq_cd *cd)
1491 return ice_sq_send_cmd(hw, &hw->adminq, desc, buf, buf_size, cd);
1496 * @hw: pointer to the HW struct
1497 * @cd: pointer to command details structure or NULL
1499 * Get the firmware version (0x0001) from the admin queue commands
1501 enum ice_status ice_aq_get_fw_ver(struct ice_hw *hw, struct ice_sq_cd *cd)
1503 struct ice_aqc_get_ver *resp;
1504 struct ice_aq_desc desc;
1505 enum ice_status status;
1507 resp = &desc.params.get_ver;
1509 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_ver);
1511 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
1514 hw->fw_branch = resp->fw_branch;
1515 hw->fw_maj_ver = resp->fw_major;
1516 hw->fw_min_ver = resp->fw_minor;
1517 hw->fw_patch = resp->fw_patch;
1518 hw->fw_build = LE32_TO_CPU(resp->fw_build);
1519 hw->api_branch = resp->api_branch;
1520 hw->api_maj_ver = resp->api_major;
1521 hw->api_min_ver = resp->api_minor;
1522 hw->api_patch = resp->api_patch;
1529 * ice_aq_send_driver_ver
1530 * @hw: pointer to the HW struct
1531 * @dv: driver's major, minor version
1532 * @cd: pointer to command details structure or NULL
1534 * Send the driver version (0x0002) to the firmware
1537 ice_aq_send_driver_ver(struct ice_hw *hw, struct ice_driver_ver *dv,
1538 struct ice_sq_cd *cd)
1540 struct ice_aqc_driver_ver *cmd;
1541 struct ice_aq_desc desc;
1544 cmd = &desc.params.driver_ver;
1547 return ICE_ERR_PARAM;
1549 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_driver_ver);
1551 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
1552 cmd->major_ver = dv->major_ver;
1553 cmd->minor_ver = dv->minor_ver;
1554 cmd->build_ver = dv->build_ver;
1555 cmd->subbuild_ver = dv->subbuild_ver;
1558 while (len < sizeof(dv->driver_string) &&
1559 IS_ASCII(dv->driver_string[len]) && dv->driver_string[len])
1562 return ice_aq_send_cmd(hw, &desc, dv->driver_string, len, cd);
1567 * @hw: pointer to the HW struct
1568 * @unloading: is the driver unloading itself
1570 * Tell the Firmware that we're shutting down the AdminQ and whether
1571 * or not the driver is unloading as well (0x0003).
1573 enum ice_status ice_aq_q_shutdown(struct ice_hw *hw, bool unloading)
1575 struct ice_aqc_q_shutdown *cmd;
1576 struct ice_aq_desc desc;
1578 cmd = &desc.params.q_shutdown;
1580 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_q_shutdown);
1583 cmd->driver_unloading = CPU_TO_LE32(ICE_AQC_DRIVER_UNLOADING);
1585 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
1590 * @hw: pointer to the HW struct
1592 * @access: access type
1593 * @sdp_number: resource number
1594 * @timeout: the maximum time in ms that the driver may hold the resource
1595 * @cd: pointer to command details structure or NULL
1597 * Requests common resource using the admin queue commands (0x0008).
1598 * When attempting to acquire the Global Config Lock, the driver can
1599 * learn of three states:
1600 * 1) ICE_SUCCESS - acquired lock, and can perform download package
1601 * 2) ICE_ERR_AQ_ERROR - did not get lock, driver should fail to load
1602 * 3) ICE_ERR_AQ_NO_WORK - did not get lock, but another driver has
1603 * successfully downloaded the package; the driver does
1604 * not have to download the package and can continue
1607 * Note that if the caller is in an acquire lock, perform action, release lock
1608 * phase of operation, it is possible that the FW may detect a timeout and issue
1609 * a CORER. In this case, the driver will receive a CORER interrupt and will
1610 * have to determine its cause. The calling thread that is handling this flow
1611 * will likely get an error propagated back to it indicating the Download
1612 * Package, Update Package or the Release Resource AQ commands timed out.
1614 static enum ice_status
1615 ice_aq_req_res(struct ice_hw *hw, enum ice_aq_res_ids res,
1616 enum ice_aq_res_access_type access, u8 sdp_number, u32 *timeout,
1617 struct ice_sq_cd *cd)
1619 struct ice_aqc_req_res *cmd_resp;
1620 struct ice_aq_desc desc;
1621 enum ice_status status;
1623 ice_debug(hw, ICE_DBG_TRACE, "ice_aq_req_res");
1625 cmd_resp = &desc.params.res_owner;
1627 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_req_res);
1629 cmd_resp->res_id = CPU_TO_LE16(res);
1630 cmd_resp->access_type = CPU_TO_LE16(access);
1631 cmd_resp->res_number = CPU_TO_LE32(sdp_number);
1632 cmd_resp->timeout = CPU_TO_LE32(*timeout);
1635 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
1637 /* The completion specifies the maximum time in ms that the driver
1638 * may hold the resource in the Timeout field.
1641 /* Global config lock response utilizes an additional status field.
1643 * If the Global config lock resource is held by some other driver, the
1644 * command completes with ICE_AQ_RES_GLBL_IN_PROG in the status field
1645 * and the timeout field indicates the maximum time the current owner
1646 * of the resource has to free it.
1648 if (res == ICE_GLOBAL_CFG_LOCK_RES_ID) {
1649 if (LE16_TO_CPU(cmd_resp->status) == ICE_AQ_RES_GLBL_SUCCESS) {
1650 *timeout = LE32_TO_CPU(cmd_resp->timeout);
1652 } else if (LE16_TO_CPU(cmd_resp->status) ==
1653 ICE_AQ_RES_GLBL_IN_PROG) {
1654 *timeout = LE32_TO_CPU(cmd_resp->timeout);
1655 return ICE_ERR_AQ_ERROR;
1656 } else if (LE16_TO_CPU(cmd_resp->status) ==
1657 ICE_AQ_RES_GLBL_DONE) {
1658 return ICE_ERR_AQ_NO_WORK;
1661 /* invalid FW response, force a timeout immediately */
1663 return ICE_ERR_AQ_ERROR;
1666 /* If the resource is held by some other driver, the command completes
1667 * with a busy return value and the timeout field indicates the maximum
1668 * time the current owner of the resource has to free it.
1670 if (!status || hw->adminq.sq_last_status == ICE_AQ_RC_EBUSY)
1671 *timeout = LE32_TO_CPU(cmd_resp->timeout);
1677 * ice_aq_release_res
1678 * @hw: pointer to the HW struct
1680 * @sdp_number: resource number
1681 * @cd: pointer to command details structure or NULL
1683 * release common resource using the admin queue commands (0x0009)
1685 static enum ice_status
1686 ice_aq_release_res(struct ice_hw *hw, enum ice_aq_res_ids res, u8 sdp_number,
1687 struct ice_sq_cd *cd)
1689 struct ice_aqc_req_res *cmd;
1690 struct ice_aq_desc desc;
1692 ice_debug(hw, ICE_DBG_TRACE, "ice_aq_release_res");
1694 cmd = &desc.params.res_owner;
1696 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_release_res);
1698 cmd->res_id = CPU_TO_LE16(res);
1699 cmd->res_number = CPU_TO_LE32(sdp_number);
1701 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
1706 * @hw: pointer to the HW structure
1708 * @access: access type (read or write)
1709 * @timeout: timeout in milliseconds
1711 * This function will attempt to acquire the ownership of a resource.
1714 ice_acquire_res(struct ice_hw *hw, enum ice_aq_res_ids res,
1715 enum ice_aq_res_access_type access, u32 timeout)
1717 #define ICE_RES_POLLING_DELAY_MS 10
1718 u32 delay = ICE_RES_POLLING_DELAY_MS;
1719 u32 time_left = timeout;
1720 enum ice_status status;
1722 ice_debug(hw, ICE_DBG_TRACE, "ice_acquire_res");
1724 status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL);
1726 /* A return code of ICE_ERR_AQ_NO_WORK means that another driver has
1727 * previously acquired the resource and performed any necessary updates;
1728 * in this case the caller does not obtain the resource and has no
1729 * further work to do.
1731 if (status == ICE_ERR_AQ_NO_WORK)
1732 goto ice_acquire_res_exit;
1735 ice_debug(hw, ICE_DBG_RES,
1736 "resource %d acquire type %d failed.\n", res, access);
1738 /* If necessary, poll until the current lock owner timeouts */
1739 timeout = time_left;
1740 while (status && timeout && time_left) {
1741 ice_msec_delay(delay, true);
1742 timeout = (timeout > delay) ? timeout - delay : 0;
1743 status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL);
1745 if (status == ICE_ERR_AQ_NO_WORK)
1746 /* lock free, but no work to do */
1753 if (status && status != ICE_ERR_AQ_NO_WORK)
1754 ice_debug(hw, ICE_DBG_RES, "resource acquire timed out.\n");
1756 ice_acquire_res_exit:
1757 if (status == ICE_ERR_AQ_NO_WORK) {
1758 if (access == ICE_RES_WRITE)
1759 ice_debug(hw, ICE_DBG_RES,
1760 "resource indicates no work to do.\n");
1762 ice_debug(hw, ICE_DBG_RES,
1763 "Warning: ICE_ERR_AQ_NO_WORK not expected\n");
1770 * @hw: pointer to the HW structure
1773 * This function will release a resource using the proper Admin Command.
1775 void ice_release_res(struct ice_hw *hw, enum ice_aq_res_ids res)
1777 enum ice_status status;
1778 u32 total_delay = 0;
1780 ice_debug(hw, ICE_DBG_TRACE, "ice_release_res");
1782 status = ice_aq_release_res(hw, res, 0, NULL);
1784 /* there are some rare cases when trying to release the resource
1785 * results in an admin queue timeout, so handle them correctly
1787 while ((status == ICE_ERR_AQ_TIMEOUT) &&
1788 (total_delay < hw->adminq.sq_cmd_timeout)) {
1789 ice_msec_delay(1, true);
1790 status = ice_aq_release_res(hw, res, 0, NULL);
1796 * ice_aq_alloc_free_res - command to allocate/free resources
1797 * @hw: pointer to the HW struct
1798 * @num_entries: number of resource entries in buffer
1799 * @buf: Indirect buffer to hold data parameters and response
1800 * @buf_size: size of buffer for indirect commands
1801 * @opc: pass in the command opcode
1802 * @cd: pointer to command details structure or NULL
1804 * Helper function to allocate/free resources using the admin queue commands
1807 ice_aq_alloc_free_res(struct ice_hw *hw, u16 num_entries,
1808 struct ice_aqc_alloc_free_res_elem *buf, u16 buf_size,
1809 enum ice_adminq_opc opc, struct ice_sq_cd *cd)
1811 struct ice_aqc_alloc_free_res_cmd *cmd;
1812 struct ice_aq_desc desc;
1814 ice_debug(hw, ICE_DBG_TRACE, "ice_aq_alloc_free_res");
1816 cmd = &desc.params.sw_res_ctrl;
1819 return ICE_ERR_PARAM;
1821 if (buf_size < (num_entries * sizeof(buf->elem[0])))
1822 return ICE_ERR_PARAM;
1824 ice_fill_dflt_direct_cmd_desc(&desc, opc);
1826 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
1828 cmd->num_entries = CPU_TO_LE16(num_entries);
1830 return ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);
1834 * ice_alloc_hw_res - allocate resource
1835 * @hw: pointer to the HW struct
1836 * @type: type of resource
1837 * @num: number of resources to allocate
1838 * @btm: allocate from bottom
1839 * @res: pointer to array that will receive the resources
1842 ice_alloc_hw_res(struct ice_hw *hw, u16 type, u16 num, bool btm, u16 *res)
1844 struct ice_aqc_alloc_free_res_elem *buf;
1845 enum ice_status status;
1848 buf_len = sizeof(*buf) + sizeof(buf->elem) * (num - 1);
1849 buf = (struct ice_aqc_alloc_free_res_elem *)
1850 ice_malloc(hw, buf_len);
1852 return ICE_ERR_NO_MEMORY;
1854 /* Prepare buffer to allocate resource. */
1855 buf->num_elems = CPU_TO_LE16(num);
1856 buf->res_type = CPU_TO_LE16(type | ICE_AQC_RES_TYPE_FLAG_DEDICATED |
1857 ICE_AQC_RES_TYPE_FLAG_IGNORE_INDEX);
1859 buf->res_type |= CPU_TO_LE16(ICE_AQC_RES_TYPE_FLAG_SCAN_BOTTOM);
1861 status = ice_aq_alloc_free_res(hw, 1, buf, buf_len,
1862 ice_aqc_opc_alloc_res, NULL);
1864 goto ice_alloc_res_exit;
1866 ice_memcpy(res, buf->elem, sizeof(buf->elem) * num,
1867 ICE_NONDMA_TO_NONDMA);
1875 * ice_free_hw_res - free allocated HW resource
1876 * @hw: pointer to the HW struct
1877 * @type: type of resource to free
1878 * @num: number of resources
1879 * @res: pointer to array that contains the resources to free
1882 ice_free_hw_res(struct ice_hw *hw, u16 type, u16 num, u16 *res)
1884 struct ice_aqc_alloc_free_res_elem *buf;
1885 enum ice_status status;
1888 buf_len = sizeof(*buf) + sizeof(buf->elem) * (num - 1);
1889 buf = (struct ice_aqc_alloc_free_res_elem *)ice_malloc(hw, buf_len);
1891 return ICE_ERR_NO_MEMORY;
1893 /* Prepare buffer to free resource. */
1894 buf->num_elems = CPU_TO_LE16(num);
1895 buf->res_type = CPU_TO_LE16(type);
1896 ice_memcpy(buf->elem, res, sizeof(buf->elem) * num,
1897 ICE_NONDMA_TO_NONDMA);
1899 status = ice_aq_alloc_free_res(hw, num, buf, buf_len,
1900 ice_aqc_opc_free_res, NULL);
1902 ice_debug(hw, ICE_DBG_SW, "CQ CMD Buffer:\n");
1909 * ice_get_num_per_func - determine number of resources per PF
1910 * @hw: pointer to the HW structure
1911 * @max: value to be evenly split between each PF
1913 * Determine the number of valid functions by going through the bitmap returned
1914 * from parsing capabilities and use this to calculate the number of resources
1915 * per PF based on the max value passed in.
1917 static u32 ice_get_num_per_func(struct ice_hw *hw, u32 max)
1921 #define ICE_CAPS_VALID_FUNCS_M 0xFF
1922 funcs = ice_hweight8(hw->dev_caps.common_cap.valid_functions &
1923 ICE_CAPS_VALID_FUNCS_M);
1932 * ice_parse_caps - parse function/device capabilities
1933 * @hw: pointer to the HW struct
1934 * @buf: pointer to a buffer containing function/device capability records
1935 * @cap_count: number of capability records in the list
1936 * @opc: type of capabilities list to parse
1938 * Helper function to parse function(0x000a)/device(0x000b) capabilities list.
1941 ice_parse_caps(struct ice_hw *hw, void *buf, u32 cap_count,
1942 enum ice_adminq_opc opc)
1944 struct ice_aqc_list_caps_elem *cap_resp;
1945 struct ice_hw_func_caps *func_p = NULL;
1946 struct ice_hw_dev_caps *dev_p = NULL;
1947 struct ice_hw_common_caps *caps;
1953 cap_resp = (struct ice_aqc_list_caps_elem *)buf;
1955 if (opc == ice_aqc_opc_list_dev_caps) {
1956 dev_p = &hw->dev_caps;
1957 caps = &dev_p->common_cap;
1958 } else if (opc == ice_aqc_opc_list_func_caps) {
1959 func_p = &hw->func_caps;
1960 caps = &func_p->common_cap;
1962 ice_debug(hw, ICE_DBG_INIT, "wrong opcode\n");
1966 for (i = 0; caps && i < cap_count; i++, cap_resp++) {
1967 u32 logical_id = LE32_TO_CPU(cap_resp->logical_id);
1968 u32 phys_id = LE32_TO_CPU(cap_resp->phys_id);
1969 u32 number = LE32_TO_CPU(cap_resp->number);
1970 u16 cap = LE16_TO_CPU(cap_resp->cap);
1973 case ICE_AQC_CAPS_VALID_FUNCTIONS:
1974 caps->valid_functions = number;
1975 ice_debug(hw, ICE_DBG_INIT,
1976 "HW caps: Valid Functions = %d\n",
1977 caps->valid_functions);
1979 case ICE_AQC_CAPS_VSI:
1981 dev_p->num_vsi_allocd_to_host = number;
1982 ice_debug(hw, ICE_DBG_INIT,
1983 "HW caps: Dev.VSI cnt = %d\n",
1984 dev_p->num_vsi_allocd_to_host);
1985 } else if (func_p) {
1986 func_p->guar_num_vsi =
1987 ice_get_num_per_func(hw, ICE_MAX_VSI);
1988 ice_debug(hw, ICE_DBG_INIT,
1989 "HW caps: Func.VSI cnt = %d\n",
1993 case ICE_AQC_CAPS_DCB:
1994 caps->dcb = (number == 1);
1995 caps->active_tc_bitmap = logical_id;
1996 caps->maxtc = phys_id;
1997 ice_debug(hw, ICE_DBG_INIT,
1998 "HW caps: DCB = %d\n", caps->dcb);
1999 ice_debug(hw, ICE_DBG_INIT,
2000 "HW caps: Active TC bitmap = %d\n",
2001 caps->active_tc_bitmap);
2002 ice_debug(hw, ICE_DBG_INIT,
2003 "HW caps: TC Max = %d\n", caps->maxtc);
2005 case ICE_AQC_CAPS_RSS:
2006 caps->rss_table_size = number;
2007 caps->rss_table_entry_width = logical_id;
2008 ice_debug(hw, ICE_DBG_INIT,
2009 "HW caps: RSS table size = %d\n",
2010 caps->rss_table_size);
2011 ice_debug(hw, ICE_DBG_INIT,
2012 "HW caps: RSS table width = %d\n",
2013 caps->rss_table_entry_width);
2015 case ICE_AQC_CAPS_RXQS:
2016 caps->num_rxq = number;
2017 caps->rxq_first_id = phys_id;
2018 ice_debug(hw, ICE_DBG_INIT,
2019 "HW caps: Num Rx Qs = %d\n", caps->num_rxq);
2020 ice_debug(hw, ICE_DBG_INIT,
2021 "HW caps: Rx first queue ID = %d\n",
2022 caps->rxq_first_id);
2024 case ICE_AQC_CAPS_TXQS:
2025 caps->num_txq = number;
2026 caps->txq_first_id = phys_id;
2027 ice_debug(hw, ICE_DBG_INIT,
2028 "HW caps: Num Tx Qs = %d\n", caps->num_txq);
2029 ice_debug(hw, ICE_DBG_INIT,
2030 "HW caps: Tx first queue ID = %d\n",
2031 caps->txq_first_id);
2033 case ICE_AQC_CAPS_MSIX:
2034 caps->num_msix_vectors = number;
2035 caps->msix_vector_first_id = phys_id;
2036 ice_debug(hw, ICE_DBG_INIT,
2037 "HW caps: MSIX vector count = %d\n",
2038 caps->num_msix_vectors);
2039 ice_debug(hw, ICE_DBG_INIT,
2040 "HW caps: MSIX first vector index = %d\n",
2041 caps->msix_vector_first_id);
2043 case ICE_AQC_CAPS_FD:
2048 dev_p->num_flow_director_fltr = number;
2049 ice_debug(hw, ICE_DBG_INIT,
2050 "HW caps: Dev.fd_fltr =%d\n",
2051 dev_p->num_flow_director_fltr);
2054 reg_val = rd32(hw, GLQF_FD_SIZE);
2055 val = (reg_val & GLQF_FD_SIZE_FD_GSIZE_M) >>
2056 GLQF_FD_SIZE_FD_GSIZE_S;
2057 func_p->fd_fltr_guar =
2058 ice_get_num_per_func(hw, val);
2059 val = (reg_val & GLQF_FD_SIZE_FD_BSIZE_M) >>
2060 GLQF_FD_SIZE_FD_BSIZE_S;
2061 func_p->fd_fltr_best_effort = val;
2062 ice_debug(hw, ICE_DBG_INIT,
2063 "HW:func.fd_fltr guar= %d\n",
2064 func_p->fd_fltr_guar);
2065 ice_debug(hw, ICE_DBG_INIT,
2066 "HW:func.fd_fltr best effort=%d\n",
2067 func_p->fd_fltr_best_effort);
2071 case ICE_AQC_CAPS_MAX_MTU:
2072 caps->max_mtu = number;
2074 ice_debug(hw, ICE_DBG_INIT,
2075 "HW caps: Dev.MaxMTU = %d\n",
2078 ice_debug(hw, ICE_DBG_INIT,
2079 "HW caps: func.MaxMTU = %d\n",
2083 ice_debug(hw, ICE_DBG_INIT,
2084 "HW caps: Unknown capability[%d]: 0x%x\n", i,
2092 * ice_aq_discover_caps - query function/device capabilities
2093 * @hw: pointer to the HW struct
2094 * @buf: a virtual buffer to hold the capabilities
2095 * @buf_size: Size of the virtual buffer
2096 * @cap_count: cap count needed if AQ err==ENOMEM
2097 * @opc: capabilities type to discover - pass in the command opcode
2098 * @cd: pointer to command details structure or NULL
2100 * Get the function(0x000a)/device(0x000b) capabilities description from
2103 static enum ice_status
2104 ice_aq_discover_caps(struct ice_hw *hw, void *buf, u16 buf_size, u32 *cap_count,
2105 enum ice_adminq_opc opc, struct ice_sq_cd *cd)
2107 struct ice_aqc_list_caps *cmd;
2108 struct ice_aq_desc desc;
2109 enum ice_status status;
2111 cmd = &desc.params.get_cap;
2113 if (opc != ice_aqc_opc_list_func_caps &&
2114 opc != ice_aqc_opc_list_dev_caps)
2115 return ICE_ERR_PARAM;
2117 ice_fill_dflt_direct_cmd_desc(&desc, opc);
2119 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);
2121 ice_parse_caps(hw, buf, LE32_TO_CPU(cmd->count), opc);
2122 else if (hw->adminq.sq_last_status == ICE_AQ_RC_ENOMEM)
2123 *cap_count = LE32_TO_CPU(cmd->count);
2128 * ice_discover_caps - get info about the HW
2129 * @hw: pointer to the hardware structure
2130 * @opc: capabilities type to discover - pass in the command opcode
2132 static enum ice_status
2133 ice_discover_caps(struct ice_hw *hw, enum ice_adminq_opc opc)
2135 enum ice_status status;
2140 /* The driver doesn't know how many capabilities the device will return
2141 * so the buffer size required isn't known ahead of time. The driver
2142 * starts with cbuf_len and if this turns out to be insufficient, the
2143 * device returns ICE_AQ_RC_ENOMEM and also the cap_count it needs.
2144 * The driver then allocates the buffer based on the count and retries
2145 * the operation. So it follows that the retry count is 2.
2147 #define ICE_GET_CAP_BUF_COUNT 40
2148 #define ICE_GET_CAP_RETRY_COUNT 2
2150 cap_count = ICE_GET_CAP_BUF_COUNT;
2151 retries = ICE_GET_CAP_RETRY_COUNT;
2156 cbuf_len = (u16)(cap_count *
2157 sizeof(struct ice_aqc_list_caps_elem));
2158 cbuf = ice_malloc(hw, cbuf_len);
2160 return ICE_ERR_NO_MEMORY;
2162 status = ice_aq_discover_caps(hw, cbuf, cbuf_len, &cap_count,
2166 if (!status || hw->adminq.sq_last_status != ICE_AQ_RC_ENOMEM)
2169 /* If ENOMEM is returned, try again with bigger buffer */
2170 } while (--retries);
2176 * ice_get_caps - get info about the HW
2177 * @hw: pointer to the hardware structure
2179 enum ice_status ice_get_caps(struct ice_hw *hw)
2181 enum ice_status status;
2183 status = ice_discover_caps(hw, ice_aqc_opc_list_dev_caps);
2185 status = ice_discover_caps(hw, ice_aqc_opc_list_func_caps);
2191 * ice_aq_manage_mac_write - manage MAC address write command
2192 * @hw: pointer to the HW struct
2193 * @mac_addr: MAC address to be written as LAA/LAA+WoL/Port address
2194 * @flags: flags to control write behavior
2195 * @cd: pointer to command details structure or NULL
2197 * This function is used to write MAC address to the NVM (0x0108).
2200 ice_aq_manage_mac_write(struct ice_hw *hw, const u8 *mac_addr, u8 flags,
2201 struct ice_sq_cd *cd)
2203 struct ice_aqc_manage_mac_write *cmd;
2204 struct ice_aq_desc desc;
2206 cmd = &desc.params.mac_write;
2207 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_write);
2212 /* Prep values for flags, sah, sal */
2213 cmd->sah = HTONS(*((const u16 *)mac_addr));
2214 cmd->sal = HTONL(*((const u32 *)(mac_addr + 2)));
2216 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
2220 * ice_aq_clear_pxe_mode
2221 * @hw: pointer to the HW struct
2223 * Tell the firmware that the driver is taking over from PXE (0x0110).
2225 static enum ice_status ice_aq_clear_pxe_mode(struct ice_hw *hw)
2227 struct ice_aq_desc desc;
2229 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pxe_mode);
2230 desc.params.clear_pxe.rx_cnt = ICE_AQC_CLEAR_PXE_RX_CNT;
2232 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
2236 * ice_clear_pxe_mode - clear pxe operations mode
2237 * @hw: pointer to the HW struct
2239 * Make sure all PXE mode settings are cleared, including things
2240 * like descriptor fetch/write-back mode.
2242 void ice_clear_pxe_mode(struct ice_hw *hw)
2244 if (ice_check_sq_alive(hw, &hw->adminq))
2245 ice_aq_clear_pxe_mode(hw);
2250 * ice_get_link_speed_based_on_phy_type - returns link speed
2251 * @phy_type_low: lower part of phy_type
2252 * @phy_type_high: higher part of phy_type
2254 * This helper function will convert an entry in PHY type structure
2255 * [phy_type_low, phy_type_high] to its corresponding link speed.
2256 * Note: In the structure of [phy_type_low, phy_type_high], there should
2257 * be one bit set, as this function will convert one PHY type to its
2259 * If no bit gets set, ICE_LINK_SPEED_UNKNOWN will be returned
2260 * If more than one bit gets set, ICE_LINK_SPEED_UNKNOWN will be returned
2263 ice_get_link_speed_based_on_phy_type(u64 phy_type_low, u64 phy_type_high)
2265 u16 speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN;
2266 u16 speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN;
2268 switch (phy_type_low) {
2269 case ICE_PHY_TYPE_LOW_100BASE_TX:
2270 case ICE_PHY_TYPE_LOW_100M_SGMII:
2271 speed_phy_type_low = ICE_AQ_LINK_SPEED_100MB;
2273 case ICE_PHY_TYPE_LOW_1000BASE_T:
2274 case ICE_PHY_TYPE_LOW_1000BASE_SX:
2275 case ICE_PHY_TYPE_LOW_1000BASE_LX:
2276 case ICE_PHY_TYPE_LOW_1000BASE_KX:
2277 case ICE_PHY_TYPE_LOW_1G_SGMII:
2278 speed_phy_type_low = ICE_AQ_LINK_SPEED_1000MB;
2280 case ICE_PHY_TYPE_LOW_2500BASE_T:
2281 case ICE_PHY_TYPE_LOW_2500BASE_X:
2282 case ICE_PHY_TYPE_LOW_2500BASE_KX:
2283 speed_phy_type_low = ICE_AQ_LINK_SPEED_2500MB;
2285 case ICE_PHY_TYPE_LOW_5GBASE_T:
2286 case ICE_PHY_TYPE_LOW_5GBASE_KR:
2287 speed_phy_type_low = ICE_AQ_LINK_SPEED_5GB;
2289 case ICE_PHY_TYPE_LOW_10GBASE_T:
2290 case ICE_PHY_TYPE_LOW_10G_SFI_DA:
2291 case ICE_PHY_TYPE_LOW_10GBASE_SR:
2292 case ICE_PHY_TYPE_LOW_10GBASE_LR:
2293 case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1:
2294 case ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC:
2295 case ICE_PHY_TYPE_LOW_10G_SFI_C2C:
2296 speed_phy_type_low = ICE_AQ_LINK_SPEED_10GB;
2298 case ICE_PHY_TYPE_LOW_25GBASE_T:
2299 case ICE_PHY_TYPE_LOW_25GBASE_CR:
2300 case ICE_PHY_TYPE_LOW_25GBASE_CR_S:
2301 case ICE_PHY_TYPE_LOW_25GBASE_CR1:
2302 case ICE_PHY_TYPE_LOW_25GBASE_SR:
2303 case ICE_PHY_TYPE_LOW_25GBASE_LR:
2304 case ICE_PHY_TYPE_LOW_25GBASE_KR:
2305 case ICE_PHY_TYPE_LOW_25GBASE_KR_S:
2306 case ICE_PHY_TYPE_LOW_25GBASE_KR1:
2307 case ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC:
2308 case ICE_PHY_TYPE_LOW_25G_AUI_C2C:
2309 speed_phy_type_low = ICE_AQ_LINK_SPEED_25GB;
2311 case ICE_PHY_TYPE_LOW_40GBASE_CR4:
2312 case ICE_PHY_TYPE_LOW_40GBASE_SR4:
2313 case ICE_PHY_TYPE_LOW_40GBASE_LR4:
2314 case ICE_PHY_TYPE_LOW_40GBASE_KR4:
2315 case ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC:
2316 case ICE_PHY_TYPE_LOW_40G_XLAUI:
2317 speed_phy_type_low = ICE_AQ_LINK_SPEED_40GB;
2319 case ICE_PHY_TYPE_LOW_50GBASE_CR2:
2320 case ICE_PHY_TYPE_LOW_50GBASE_SR2:
2321 case ICE_PHY_TYPE_LOW_50GBASE_LR2:
2322 case ICE_PHY_TYPE_LOW_50GBASE_KR2:
2323 case ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC:
2324 case ICE_PHY_TYPE_LOW_50G_LAUI2:
2325 case ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC:
2326 case ICE_PHY_TYPE_LOW_50G_AUI2:
2327 case ICE_PHY_TYPE_LOW_50GBASE_CP:
2328 case ICE_PHY_TYPE_LOW_50GBASE_SR:
2329 case ICE_PHY_TYPE_LOW_50GBASE_FR:
2330 case ICE_PHY_TYPE_LOW_50GBASE_LR:
2331 case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4:
2332 case ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC:
2333 case ICE_PHY_TYPE_LOW_50G_AUI1:
2334 speed_phy_type_low = ICE_AQ_LINK_SPEED_50GB;
2336 case ICE_PHY_TYPE_LOW_100GBASE_CR4:
2337 case ICE_PHY_TYPE_LOW_100GBASE_SR4:
2338 case ICE_PHY_TYPE_LOW_100GBASE_LR4:
2339 case ICE_PHY_TYPE_LOW_100GBASE_KR4:
2340 case ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC:
2341 case ICE_PHY_TYPE_LOW_100G_CAUI4:
2342 case ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC:
2343 case ICE_PHY_TYPE_LOW_100G_AUI4:
2344 case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4:
2345 case ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4:
2346 case ICE_PHY_TYPE_LOW_100GBASE_CP2:
2347 case ICE_PHY_TYPE_LOW_100GBASE_SR2:
2348 case ICE_PHY_TYPE_LOW_100GBASE_DR:
2349 speed_phy_type_low = ICE_AQ_LINK_SPEED_100GB;
2352 speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN;
2356 switch (phy_type_high) {
2357 case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4:
2358 case ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC:
2359 case ICE_PHY_TYPE_HIGH_100G_CAUI2:
2360 case ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC:
2361 case ICE_PHY_TYPE_HIGH_100G_AUI2:
2362 speed_phy_type_high = ICE_AQ_LINK_SPEED_100GB;
2365 speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN;
2369 if (speed_phy_type_low == ICE_AQ_LINK_SPEED_UNKNOWN &&
2370 speed_phy_type_high == ICE_AQ_LINK_SPEED_UNKNOWN)
2371 return ICE_AQ_LINK_SPEED_UNKNOWN;
2372 else if (speed_phy_type_low != ICE_AQ_LINK_SPEED_UNKNOWN &&
2373 speed_phy_type_high != ICE_AQ_LINK_SPEED_UNKNOWN)
2374 return ICE_AQ_LINK_SPEED_UNKNOWN;
2375 else if (speed_phy_type_low != ICE_AQ_LINK_SPEED_UNKNOWN &&
2376 speed_phy_type_high == ICE_AQ_LINK_SPEED_UNKNOWN)
2377 return speed_phy_type_low;
2379 return speed_phy_type_high;
2383 * ice_update_phy_type
2384 * @phy_type_low: pointer to the lower part of phy_type
2385 * @phy_type_high: pointer to the higher part of phy_type
2386 * @link_speeds_bitmap: targeted link speeds bitmap
2388 * Note: For the link_speeds_bitmap structure, you can check it at
2389 * [ice_aqc_get_link_status->link_speed]. Caller can pass in
2390 * link_speeds_bitmap include multiple speeds.
2392 * Each entry in this [phy_type_low, phy_type_high] structure will
2393 * present a certain link speed. This helper function will turn on bits
2394 * in [phy_type_low, phy_type_high] structure based on the value of
2395 * link_speeds_bitmap input parameter.
2398 ice_update_phy_type(u64 *phy_type_low, u64 *phy_type_high,
2399 u16 link_speeds_bitmap)
2401 u16 speed = ICE_AQ_LINK_SPEED_UNKNOWN;
2406 /* We first check with low part of phy_type */
2407 for (index = 0; index <= ICE_PHY_TYPE_LOW_MAX_INDEX; index++) {
2408 pt_low = BIT_ULL(index);
2409 speed = ice_get_link_speed_based_on_phy_type(pt_low, 0);
2411 if (link_speeds_bitmap & speed)
2412 *phy_type_low |= BIT_ULL(index);
2415 /* We then check with high part of phy_type */
2416 for (index = 0; index <= ICE_PHY_TYPE_HIGH_MAX_INDEX; index++) {
2417 pt_high = BIT_ULL(index);
2418 speed = ice_get_link_speed_based_on_phy_type(0, pt_high);
2420 if (link_speeds_bitmap & speed)
2421 *phy_type_high |= BIT_ULL(index);
2426 * ice_aq_set_phy_cfg
2427 * @hw: pointer to the HW struct
2428 * @pi: port info structure of the interested logical port
2429 * @cfg: structure with PHY configuration data to be set
2430 * @cd: pointer to command details structure or NULL
2432 * Set the various PHY configuration parameters supported on the Port.
2433 * One or more of the Set PHY config parameters may be ignored in an MFP
2434 * mode as the PF may not have the privilege to set some of the PHY Config
2435 * parameters. This status will be indicated by the command response (0x0601).
2438 ice_aq_set_phy_cfg(struct ice_hw *hw, struct ice_port_info *pi,
2439 struct ice_aqc_set_phy_cfg_data *cfg, struct ice_sq_cd *cd)
2441 struct ice_aq_desc desc;
2442 enum ice_status status;
2445 return ICE_ERR_PARAM;
2447 /* Ensure that only valid bits of cfg->caps can be turned on. */
2448 if (cfg->caps & ~ICE_AQ_PHY_ENA_VALID_MASK) {
2449 ice_debug(hw, ICE_DBG_PHY,
2450 "Invalid bit is set in ice_aqc_set_phy_cfg_data->caps : 0x%x\n",
2453 cfg->caps &= ICE_AQ_PHY_ENA_VALID_MASK;
2456 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_phy_cfg);
2457 desc.params.set_phy.lport_num = pi->lport;
2458 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
2460 ice_debug(hw, ICE_DBG_LINK, "phy_type_low = 0x%llx\n",
2461 (unsigned long long)LE64_TO_CPU(cfg->phy_type_low));
2462 ice_debug(hw, ICE_DBG_LINK, "phy_type_high = 0x%llx\n",
2463 (unsigned long long)LE64_TO_CPU(cfg->phy_type_high));
2464 ice_debug(hw, ICE_DBG_LINK, "caps = 0x%x\n", cfg->caps);
2465 ice_debug(hw, ICE_DBG_LINK, "low_power_ctrl = 0x%x\n",
2466 cfg->low_power_ctrl);
2467 ice_debug(hw, ICE_DBG_LINK, "eee_cap = 0x%x\n", cfg->eee_cap);
2468 ice_debug(hw, ICE_DBG_LINK, "eeer_value = 0x%x\n", cfg->eeer_value);
2469 ice_debug(hw, ICE_DBG_LINK, "link_fec_opt = 0x%x\n", cfg->link_fec_opt);
2471 status = ice_aq_send_cmd(hw, &desc, cfg, sizeof(*cfg), cd);
2474 pi->phy.curr_user_phy_cfg = *cfg;
2480 * ice_update_link_info - update status of the HW network link
2481 * @pi: port info structure of the interested logical port
2483 enum ice_status ice_update_link_info(struct ice_port_info *pi)
2485 struct ice_aqc_get_phy_caps_data *pcaps;
2486 struct ice_phy_info *phy_info;
2487 enum ice_status status;
2491 return ICE_ERR_PARAM;
2495 pcaps = (struct ice_aqc_get_phy_caps_data *)
2496 ice_malloc(hw, sizeof(*pcaps));
2498 return ICE_ERR_NO_MEMORY;
2500 phy_info = &pi->phy;
2501 status = ice_aq_get_link_info(pi, true, NULL, NULL);
2505 if (phy_info->link_info.link_info & ICE_AQ_MEDIA_AVAILABLE) {
2506 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_SW_CFG,
2511 ice_memcpy(phy_info->link_info.module_type, &pcaps->module_type,
2512 sizeof(phy_info->link_info.module_type),
2513 ICE_NONDMA_TO_NONDMA);
2516 ice_free(hw, pcaps);
2521 * ice_cache_phy_user_req
2522 * @pi: port information structure
2523 * @cache_data: PHY logging data
2524 * @cache_mode: PHY logging mode
2526 * Log the user request on (FC, FEC, SPEED) for later user.
2529 ice_cache_phy_user_req(struct ice_port_info *pi,
2530 struct ice_phy_cache_mode_data cache_data,
2531 enum ice_phy_cache_mode cache_mode)
2536 switch (cache_mode) {
2538 pi->phy.curr_user_fc_req = cache_data.data.curr_user_fc_req;
2540 case ICE_SPEED_MODE:
2541 pi->phy.curr_user_speed_req =
2542 cache_data.data.curr_user_speed_req;
2545 pi->phy.curr_user_fec_req = cache_data.data.curr_user_fec_req;
2554 * @pi: port information structure
2555 * @aq_failures: pointer to status code, specific to ice_set_fc routine
2556 * @ena_auto_link_update: enable automatic link update
2558 * Set the requested flow control mode.
2561 ice_set_fc(struct ice_port_info *pi, u8 *aq_failures, bool ena_auto_link_update)
2563 struct ice_aqc_set_phy_cfg_data cfg = { 0 };
2564 struct ice_phy_cache_mode_data cache_data;
2565 struct ice_aqc_get_phy_caps_data *pcaps;
2566 enum ice_status status;
2567 u8 pause_mask = 0x0;
2571 return ICE_ERR_PARAM;
2573 *aq_failures = ICE_SET_FC_AQ_FAIL_NONE;
2575 /* Cache user FC request */
2576 cache_data.data.curr_user_fc_req = pi->fc.req_mode;
2577 ice_cache_phy_user_req(pi, cache_data, ICE_FC_MODE);
2579 switch (pi->fc.req_mode) {
2581 pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE;
2582 pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE;
2584 case ICE_FC_RX_PAUSE:
2585 pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE;
2587 case ICE_FC_TX_PAUSE:
2588 pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE;
2594 pcaps = (struct ice_aqc_get_phy_caps_data *)
2595 ice_malloc(hw, sizeof(*pcaps));
2597 return ICE_ERR_NO_MEMORY;
2599 /* Get the current PHY config */
2600 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_SW_CFG, pcaps,
2603 *aq_failures = ICE_SET_FC_AQ_FAIL_GET;
2607 /* clear the old pause settings */
2608 cfg.caps = pcaps->caps & ~(ICE_AQC_PHY_EN_TX_LINK_PAUSE |
2609 ICE_AQC_PHY_EN_RX_LINK_PAUSE);
2611 /* set the new capabilities */
2612 cfg.caps |= pause_mask;
2614 /* If the capabilities have changed, then set the new config */
2615 if (cfg.caps != pcaps->caps) {
2616 int retry_count, retry_max = 10;
2618 /* Auto restart link so settings take effect */
2619 if (ena_auto_link_update)
2620 cfg.caps |= ICE_AQ_PHY_ENA_AUTO_LINK_UPDT;
2621 /* Copy over all the old settings */
2622 cfg.phy_type_high = pcaps->phy_type_high;
2623 cfg.phy_type_low = pcaps->phy_type_low;
2624 cfg.low_power_ctrl = pcaps->low_power_ctrl;
2625 cfg.eee_cap = pcaps->eee_cap;
2626 cfg.eeer_value = pcaps->eeer_value;
2627 cfg.link_fec_opt = pcaps->link_fec_options;
2629 status = ice_aq_set_phy_cfg(hw, pi, &cfg, NULL);
2631 *aq_failures = ICE_SET_FC_AQ_FAIL_SET;
2635 /* Update the link info
2636 * It sometimes takes a really long time for link to
2637 * come back from the atomic reset. Thus, we wait a
2640 for (retry_count = 0; retry_count < retry_max; retry_count++) {
2641 status = ice_update_link_info(pi);
2643 if (status == ICE_SUCCESS)
2646 ice_msec_delay(100, true);
2650 *aq_failures = ICE_SET_FC_AQ_FAIL_UPDATE;
2654 ice_free(hw, pcaps);
2659 * ice_copy_phy_caps_to_cfg - Copy PHY ability data to configuration data
2660 * @caps: PHY ability structure to copy date from
2661 * @cfg: PHY configuration structure to copy data to
2663 * Helper function to copy AQC PHY get ability data to PHY set configuration
2667 ice_copy_phy_caps_to_cfg(struct ice_aqc_get_phy_caps_data *caps,
2668 struct ice_aqc_set_phy_cfg_data *cfg)
2673 cfg->phy_type_low = caps->phy_type_low;
2674 cfg->phy_type_high = caps->phy_type_high;
2675 cfg->caps = caps->caps;
2676 cfg->low_power_ctrl = caps->low_power_ctrl;
2677 cfg->eee_cap = caps->eee_cap;
2678 cfg->eeer_value = caps->eeer_value;
2679 cfg->link_fec_opt = caps->link_fec_options;
2683 * ice_cfg_phy_fec - Configure PHY FEC data based on FEC mode
2684 * @cfg: PHY configuration data to set FEC mode
2685 * @fec: FEC mode to configure
2687 * Caller should copy ice_aqc_get_phy_caps_data.caps ICE_AQC_PHY_EN_AUTO_FEC
2688 * (bit 7) and ice_aqc_get_phy_caps_data.link_fec_options to cfg.caps
2689 * ICE_AQ_PHY_ENA_AUTO_FEC (bit 7) and cfg.link_fec_options before calling.
2692 ice_cfg_phy_fec(struct ice_aqc_set_phy_cfg_data *cfg, enum ice_fec_mode fec)
2696 /* Clear auto FEC and RS bits, and AND BASE-R ability
2697 * bits and OR request bits.
2699 cfg->caps &= ~ICE_AQC_PHY_EN_AUTO_FEC;
2700 cfg->link_fec_opt &= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN |
2701 ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN;
2702 cfg->link_fec_opt |= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ |
2703 ICE_AQC_PHY_FEC_25G_KR_REQ;
2706 /* Clear auto FEC and BASE-R bits, and AND RS ability
2707 * bits and OR request bits.
2709 cfg->caps &= ~ICE_AQC_PHY_EN_AUTO_FEC;
2710 cfg->link_fec_opt &= ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN;
2711 cfg->link_fec_opt |= ICE_AQC_PHY_FEC_25G_RS_528_REQ |
2712 ICE_AQC_PHY_FEC_25G_RS_544_REQ;
2715 /* Clear auto FEC and all FEC option bits. */
2716 cfg->caps &= ~ICE_AQC_PHY_EN_AUTO_FEC;
2717 cfg->link_fec_opt &= ~ICE_AQC_PHY_FEC_MASK;
2720 /* AND auto FEC bit, and all caps bits. */
2721 cfg->caps &= ICE_AQC_PHY_CAPS_MASK;
2727 * ice_get_link_status - get status of the HW network link
2728 * @pi: port information structure
2729 * @link_up: pointer to bool (true/false = linkup/linkdown)
2731 * Variable link_up is true if link is up, false if link is down.
2732 * The variable link_up is invalid if status is non zero. As a
2733 * result of this call, link status reporting becomes enabled
2735 enum ice_status ice_get_link_status(struct ice_port_info *pi, bool *link_up)
2737 struct ice_phy_info *phy_info;
2738 enum ice_status status = ICE_SUCCESS;
2740 if (!pi || !link_up)
2741 return ICE_ERR_PARAM;
2743 phy_info = &pi->phy;
2745 if (phy_info->get_link_info) {
2746 status = ice_update_link_info(pi);
2749 ice_debug(pi->hw, ICE_DBG_LINK,
2750 "get link status error, status = %d\n",
2754 *link_up = phy_info->link_info.link_info & ICE_AQ_LINK_UP;
2760 * ice_aq_set_link_restart_an
2761 * @pi: pointer to the port information structure
2762 * @ena_link: if true: enable link, if false: disable link
2763 * @cd: pointer to command details structure or NULL
2765 * Sets up the link and restarts the Auto-Negotiation over the link.
2768 ice_aq_set_link_restart_an(struct ice_port_info *pi, bool ena_link,
2769 struct ice_sq_cd *cd)
2771 struct ice_aqc_restart_an *cmd;
2772 struct ice_aq_desc desc;
2774 cmd = &desc.params.restart_an;
2776 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_restart_an);
2778 cmd->cmd_flags = ICE_AQC_RESTART_AN_LINK_RESTART;
2779 cmd->lport_num = pi->lport;
2781 cmd->cmd_flags |= ICE_AQC_RESTART_AN_LINK_ENABLE;
2783 cmd->cmd_flags &= ~ICE_AQC_RESTART_AN_LINK_ENABLE;
2785 return ice_aq_send_cmd(pi->hw, &desc, NULL, 0, cd);
2789 * ice_aq_set_event_mask
2790 * @hw: pointer to the HW struct
2791 * @port_num: port number of the physical function
2792 * @mask: event mask to be set
2793 * @cd: pointer to command details structure or NULL
2795 * Set event mask (0x0613)
2798 ice_aq_set_event_mask(struct ice_hw *hw, u8 port_num, u16 mask,
2799 struct ice_sq_cd *cd)
2801 struct ice_aqc_set_event_mask *cmd;
2802 struct ice_aq_desc desc;
2804 cmd = &desc.params.set_event_mask;
2806 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_event_mask);
2808 cmd->lport_num = port_num;
2810 cmd->event_mask = CPU_TO_LE16(mask);
2811 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
2815 * ice_aq_set_mac_loopback
2816 * @hw: pointer to the HW struct
2817 * @ena_lpbk: Enable or Disable loopback
2818 * @cd: pointer to command details structure or NULL
2820 * Enable/disable loopback on a given port
2823 ice_aq_set_mac_loopback(struct ice_hw *hw, bool ena_lpbk, struct ice_sq_cd *cd)
2825 struct ice_aqc_set_mac_lb *cmd;
2826 struct ice_aq_desc desc;
2828 cmd = &desc.params.set_mac_lb;
2830 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_mac_lb);
2832 cmd->lb_mode = ICE_AQ_MAC_LB_EN;
2834 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
2839 * ice_aq_set_port_id_led
2840 * @pi: pointer to the port information
2841 * @is_orig_mode: is this LED set to original mode (by the net-list)
2842 * @cd: pointer to command details structure or NULL
2844 * Set LED value for the given port (0x06e9)
2847 ice_aq_set_port_id_led(struct ice_port_info *pi, bool is_orig_mode,
2848 struct ice_sq_cd *cd)
2850 struct ice_aqc_set_port_id_led *cmd;
2851 struct ice_hw *hw = pi->hw;
2852 struct ice_aq_desc desc;
2854 cmd = &desc.params.set_port_id_led;
2856 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_port_id_led);
2860 cmd->ident_mode = ICE_AQC_PORT_IDENT_LED_ORIG;
2862 cmd->ident_mode = ICE_AQC_PORT_IDENT_LED_BLINK;
2864 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
2868 * __ice_aq_get_set_rss_lut
2869 * @hw: pointer to the hardware structure
2870 * @vsi_id: VSI FW index
2871 * @lut_type: LUT table type
2872 * @lut: pointer to the LUT buffer provided by the caller
2873 * @lut_size: size of the LUT buffer
2874 * @glob_lut_idx: global LUT index
2875 * @set: set true to set the table, false to get the table
2877 * Internal function to get (0x0B05) or set (0x0B03) RSS look up table
2879 static enum ice_status
2880 __ice_aq_get_set_rss_lut(struct ice_hw *hw, u16 vsi_id, u8 lut_type, u8 *lut,
2881 u16 lut_size, u8 glob_lut_idx, bool set)
2883 struct ice_aqc_get_set_rss_lut *cmd_resp;
2884 struct ice_aq_desc desc;
2885 enum ice_status status;
2888 cmd_resp = &desc.params.get_set_rss_lut;
2891 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_rss_lut);
2892 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
2894 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_rss_lut);
2897 cmd_resp->vsi_id = CPU_TO_LE16(((vsi_id <<
2898 ICE_AQC_GSET_RSS_LUT_VSI_ID_S) &
2899 ICE_AQC_GSET_RSS_LUT_VSI_ID_M) |
2900 ICE_AQC_GSET_RSS_LUT_VSI_VALID);
2903 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_VSI:
2904 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF:
2905 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL:
2906 flags |= ((lut_type << ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S) &
2907 ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_M);
2910 status = ICE_ERR_PARAM;
2911 goto ice_aq_get_set_rss_lut_exit;
2914 if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL) {
2915 flags |= ((glob_lut_idx << ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S) &
2916 ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_M);
2919 goto ice_aq_get_set_rss_lut_send;
2920 } else if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF) {
2922 goto ice_aq_get_set_rss_lut_send;
2924 goto ice_aq_get_set_rss_lut_send;
2927 /* LUT size is only valid for Global and PF table types */
2929 case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128:
2930 flags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128_FLAG <<
2931 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) &
2932 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M;
2934 case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512:
2935 flags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512_FLAG <<
2936 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) &
2937 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M;
2939 case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K:
2940 if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF) {
2941 flags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K_FLAG <<
2942 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) &
2943 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M;
2948 status = ICE_ERR_PARAM;
2949 goto ice_aq_get_set_rss_lut_exit;
2952 ice_aq_get_set_rss_lut_send:
2953 cmd_resp->flags = CPU_TO_LE16(flags);
2954 status = ice_aq_send_cmd(hw, &desc, lut, lut_size, NULL);
2956 ice_aq_get_set_rss_lut_exit:
2961 * ice_aq_get_rss_lut
2962 * @hw: pointer to the hardware structure
2963 * @vsi_handle: software VSI handle
2964 * @lut_type: LUT table type
2965 * @lut: pointer to the LUT buffer provided by the caller
2966 * @lut_size: size of the LUT buffer
2968 * get the RSS lookup table, PF or VSI type
2971 ice_aq_get_rss_lut(struct ice_hw *hw, u16 vsi_handle, u8 lut_type,
2972 u8 *lut, u16 lut_size)
2974 if (!ice_is_vsi_valid(hw, vsi_handle) || !lut)
2975 return ICE_ERR_PARAM;
2977 return __ice_aq_get_set_rss_lut(hw, ice_get_hw_vsi_num(hw, vsi_handle),
2978 lut_type, lut, lut_size, 0, false);
2982 * ice_aq_set_rss_lut
2983 * @hw: pointer to the hardware structure
2984 * @vsi_handle: software VSI handle
2985 * @lut_type: LUT table type
2986 * @lut: pointer to the LUT buffer provided by the caller
2987 * @lut_size: size of the LUT buffer
2989 * set the RSS lookup table, PF or VSI type
2992 ice_aq_set_rss_lut(struct ice_hw *hw, u16 vsi_handle, u8 lut_type,
2993 u8 *lut, u16 lut_size)
2995 if (!ice_is_vsi_valid(hw, vsi_handle) || !lut)
2996 return ICE_ERR_PARAM;
2998 return __ice_aq_get_set_rss_lut(hw, ice_get_hw_vsi_num(hw, vsi_handle),
2999 lut_type, lut, lut_size, 0, true);
3003 * __ice_aq_get_set_rss_key
3004 * @hw: pointer to the HW struct
3005 * @vsi_id: VSI FW index
3006 * @key: pointer to key info struct
3007 * @set: set true to set the key, false to get the key
3009 * get (0x0B04) or set (0x0B02) the RSS key per VSI
3012 ice_status __ice_aq_get_set_rss_key(struct ice_hw *hw, u16 vsi_id,
3013 struct ice_aqc_get_set_rss_keys *key,
3016 struct ice_aqc_get_set_rss_key *cmd_resp;
3017 u16 key_size = sizeof(*key);
3018 struct ice_aq_desc desc;
3020 cmd_resp = &desc.params.get_set_rss_key;
3023 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_rss_key);
3024 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
3026 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_rss_key);
3029 cmd_resp->vsi_id = CPU_TO_LE16(((vsi_id <<
3030 ICE_AQC_GSET_RSS_KEY_VSI_ID_S) &
3031 ICE_AQC_GSET_RSS_KEY_VSI_ID_M) |
3032 ICE_AQC_GSET_RSS_KEY_VSI_VALID);
3034 return ice_aq_send_cmd(hw, &desc, key, key_size, NULL);
3038 * ice_aq_get_rss_key
3039 * @hw: pointer to the HW struct
3040 * @vsi_handle: software VSI handle
3041 * @key: pointer to key info struct
3043 * get the RSS key per VSI
3046 ice_aq_get_rss_key(struct ice_hw *hw, u16 vsi_handle,
3047 struct ice_aqc_get_set_rss_keys *key)
3049 if (!ice_is_vsi_valid(hw, vsi_handle) || !key)
3050 return ICE_ERR_PARAM;
3052 return __ice_aq_get_set_rss_key(hw, ice_get_hw_vsi_num(hw, vsi_handle),
3057 * ice_aq_set_rss_key
3058 * @hw: pointer to the HW struct
3059 * @vsi_handle: software VSI handle
3060 * @keys: pointer to key info struct
3062 * set the RSS key per VSI
3065 ice_aq_set_rss_key(struct ice_hw *hw, u16 vsi_handle,
3066 struct ice_aqc_get_set_rss_keys *keys)
3068 if (!ice_is_vsi_valid(hw, vsi_handle) || !keys)
3069 return ICE_ERR_PARAM;
3071 return __ice_aq_get_set_rss_key(hw, ice_get_hw_vsi_num(hw, vsi_handle),
3076 * ice_aq_add_lan_txq
3077 * @hw: pointer to the hardware structure
3078 * @num_qgrps: Number of added queue groups
3079 * @qg_list: list of queue groups to be added
3080 * @buf_size: size of buffer for indirect command
3081 * @cd: pointer to command details structure or NULL
3083 * Add Tx LAN queue (0x0C30)
3086 * Prior to calling add Tx LAN queue:
3087 * Initialize the following as part of the Tx queue context:
3088 * Completion queue ID if the queue uses Completion queue, Quanta profile,
3089 * Cache profile and Packet shaper profile.
3091 * After add Tx LAN queue AQ command is completed:
3092 * Interrupts should be associated with specific queues,
3093 * Association of Tx queue to Doorbell queue is not part of Add LAN Tx queue
3097 ice_aq_add_lan_txq(struct ice_hw *hw, u8 num_qgrps,
3098 struct ice_aqc_add_tx_qgrp *qg_list, u16 buf_size,
3099 struct ice_sq_cd *cd)
3101 u16 i, sum_header_size, sum_q_size = 0;
3102 struct ice_aqc_add_tx_qgrp *list;
3103 struct ice_aqc_add_txqs *cmd;
3104 struct ice_aq_desc desc;
3106 ice_debug(hw, ICE_DBG_TRACE, "ice_aq_add_lan_txq");
3108 cmd = &desc.params.add_txqs;
3110 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_add_txqs);
3113 return ICE_ERR_PARAM;
3115 if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS)
3116 return ICE_ERR_PARAM;
3118 sum_header_size = num_qgrps *
3119 (sizeof(*qg_list) - sizeof(*qg_list->txqs));
3122 for (i = 0; i < num_qgrps; i++) {
3123 struct ice_aqc_add_txqs_perq *q = list->txqs;
3125 sum_q_size += list->num_txqs * sizeof(*q);
3126 list = (struct ice_aqc_add_tx_qgrp *)(q + list->num_txqs);
3129 if (buf_size != (sum_header_size + sum_q_size))
3130 return ICE_ERR_PARAM;
3132 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
3134 cmd->num_qgrps = num_qgrps;
3136 return ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd);
3140 * ice_aq_dis_lan_txq
3141 * @hw: pointer to the hardware structure
3142 * @num_qgrps: number of groups in the list
3143 * @qg_list: the list of groups to disable
3144 * @buf_size: the total size of the qg_list buffer in bytes
3145 * @rst_src: if called due to reset, specifies the reset source
3146 * @vmvf_num: the relative VM or VF number that is undergoing the reset
3147 * @cd: pointer to command details structure or NULL
3149 * Disable LAN Tx queue (0x0C31)
3151 static enum ice_status
3152 ice_aq_dis_lan_txq(struct ice_hw *hw, u8 num_qgrps,
3153 struct ice_aqc_dis_txq_item *qg_list, u16 buf_size,
3154 enum ice_disq_rst_src rst_src, u16 vmvf_num,
3155 struct ice_sq_cd *cd)
3157 struct ice_aqc_dis_txqs *cmd;
3158 struct ice_aq_desc desc;
3159 enum ice_status status;
3162 ice_debug(hw, ICE_DBG_TRACE, "ice_aq_dis_lan_txq");
3163 cmd = &desc.params.dis_txqs;
3164 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_dis_txqs);
3166 /* qg_list can be NULL only in VM/VF reset flow */
3167 if (!qg_list && !rst_src)
3168 return ICE_ERR_PARAM;
3170 if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS)
3171 return ICE_ERR_PARAM;
3173 cmd->num_entries = num_qgrps;
3175 cmd->vmvf_and_timeout = CPU_TO_LE16((5 << ICE_AQC_Q_DIS_TIMEOUT_S) &
3176 ICE_AQC_Q_DIS_TIMEOUT_M);
3180 cmd->cmd_type = ICE_AQC_Q_DIS_CMD_VM_RESET;
3181 cmd->vmvf_and_timeout |=
3182 CPU_TO_LE16(vmvf_num & ICE_AQC_Q_DIS_VMVF_NUM_M);
3189 /* flush pipe on time out */
3190 cmd->cmd_type |= ICE_AQC_Q_DIS_CMD_FLUSH_PIPE;
3191 /* If no queue group info, we are in a reset flow. Issue the AQ */
3195 /* set RD bit to indicate that command buffer is provided by the driver
3196 * and it needs to be read by the firmware
3198 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
3200 for (i = 0; i < num_qgrps; ++i) {
3201 /* Calculate the size taken up by the queue IDs in this group */
3202 sz += qg_list[i].num_qs * sizeof(qg_list[i].q_id);
3204 /* Add the size of the group header */
3205 sz += sizeof(qg_list[i]) - sizeof(qg_list[i].q_id);
3207 /* If the num of queues is even, add 2 bytes of padding */
3208 if ((qg_list[i].num_qs % 2) == 0)
3213 return ICE_ERR_PARAM;
3216 status = ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd);
3219 ice_debug(hw, ICE_DBG_SCHED, "VM%d disable failed %d\n",
3220 vmvf_num, hw->adminq.sq_last_status);
3222 ice_debug(hw, ICE_DBG_SCHED, "disable queue %d failed %d\n",
3223 LE16_TO_CPU(qg_list[0].q_id[0]),
3224 hw->adminq.sq_last_status);
3230 /* End of FW Admin Queue command wrappers */
3233 * ice_write_byte - write a byte to a packed context structure
3234 * @src_ctx: the context structure to read from
3235 * @dest_ctx: the context to be written to
3236 * @ce_info: a description of the struct to be filled
3239 ice_write_byte(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)
3241 u8 src_byte, dest_byte, mask;
3245 /* copy from the next struct field */
3246 from = src_ctx + ce_info->offset;
3248 /* prepare the bits and mask */
3249 shift_width = ce_info->lsb % 8;
3250 mask = (u8)(BIT(ce_info->width) - 1);
3255 /* shift to correct alignment */
3256 mask <<= shift_width;
3257 src_byte <<= shift_width;
3259 /* get the current bits from the target bit string */
3260 dest = dest_ctx + (ce_info->lsb / 8);
3262 ice_memcpy(&dest_byte, dest, sizeof(dest_byte), ICE_DMA_TO_NONDMA);
3264 dest_byte &= ~mask; /* get the bits not changing */
3265 dest_byte |= src_byte; /* add in the new bits */
3267 /* put it all back */
3268 ice_memcpy(dest, &dest_byte, sizeof(dest_byte), ICE_NONDMA_TO_DMA);
3272 * ice_write_word - write a word to a packed context structure
3273 * @src_ctx: the context structure to read from
3274 * @dest_ctx: the context to be written to
3275 * @ce_info: a description of the struct to be filled
3278 ice_write_word(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)
3285 /* copy from the next struct field */
3286 from = src_ctx + ce_info->offset;
3288 /* prepare the bits and mask */
3289 shift_width = ce_info->lsb % 8;
3290 mask = BIT(ce_info->width) - 1;
3292 /* don't swizzle the bits until after the mask because the mask bits
3293 * will be in a different bit position on big endian machines
3295 src_word = *(u16 *)from;
3298 /* shift to correct alignment */
3299 mask <<= shift_width;
3300 src_word <<= shift_width;
3302 /* get the current bits from the target bit string */
3303 dest = dest_ctx + (ce_info->lsb / 8);
3305 ice_memcpy(&dest_word, dest, sizeof(dest_word), ICE_DMA_TO_NONDMA);
3307 dest_word &= ~(CPU_TO_LE16(mask)); /* get the bits not changing */
3308 dest_word |= CPU_TO_LE16(src_word); /* add in the new bits */
3310 /* put it all back */
3311 ice_memcpy(dest, &dest_word, sizeof(dest_word), ICE_NONDMA_TO_DMA);
3315 * ice_write_dword - write a dword to a packed context structure
3316 * @src_ctx: the context structure to read from
3317 * @dest_ctx: the context to be written to
3318 * @ce_info: a description of the struct to be filled
3321 ice_write_dword(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)
3323 u32 src_dword, mask;
3328 /* copy from the next struct field */
3329 from = src_ctx + ce_info->offset;
3331 /* prepare the bits and mask */
3332 shift_width = ce_info->lsb % 8;
3334 /* if the field width is exactly 32 on an x86 machine, then the shift
3335 * operation will not work because the SHL instructions count is masked
3336 * to 5 bits so the shift will do nothing
3338 if (ce_info->width < 32)
3339 mask = BIT(ce_info->width) - 1;
3343 /* don't swizzle the bits until after the mask because the mask bits
3344 * will be in a different bit position on big endian machines
3346 src_dword = *(u32 *)from;
3349 /* shift to correct alignment */
3350 mask <<= shift_width;
3351 src_dword <<= shift_width;
3353 /* get the current bits from the target bit string */
3354 dest = dest_ctx + (ce_info->lsb / 8);
3356 ice_memcpy(&dest_dword, dest, sizeof(dest_dword), ICE_DMA_TO_NONDMA);
3358 dest_dword &= ~(CPU_TO_LE32(mask)); /* get the bits not changing */
3359 dest_dword |= CPU_TO_LE32(src_dword); /* add in the new bits */
3361 /* put it all back */
3362 ice_memcpy(dest, &dest_dword, sizeof(dest_dword), ICE_NONDMA_TO_DMA);
3366 * ice_write_qword - write a qword to a packed context structure
3367 * @src_ctx: the context structure to read from
3368 * @dest_ctx: the context to be written to
3369 * @ce_info: a description of the struct to be filled
3372 ice_write_qword(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)
3374 u64 src_qword, mask;
3379 /* copy from the next struct field */
3380 from = src_ctx + ce_info->offset;
3382 /* prepare the bits and mask */
3383 shift_width = ce_info->lsb % 8;
3385 /* if the field width is exactly 64 on an x86 machine, then the shift
3386 * operation will not work because the SHL instructions count is masked
3387 * to 6 bits so the shift will do nothing
3389 if (ce_info->width < 64)
3390 mask = BIT_ULL(ce_info->width) - 1;
3394 /* don't swizzle the bits until after the mask because the mask bits
3395 * will be in a different bit position on big endian machines
3397 src_qword = *(u64 *)from;
3400 /* shift to correct alignment */
3401 mask <<= shift_width;
3402 src_qword <<= shift_width;
3404 /* get the current bits from the target bit string */
3405 dest = dest_ctx + (ce_info->lsb / 8);
3407 ice_memcpy(&dest_qword, dest, sizeof(dest_qword), ICE_DMA_TO_NONDMA);
3409 dest_qword &= ~(CPU_TO_LE64(mask)); /* get the bits not changing */
3410 dest_qword |= CPU_TO_LE64(src_qword); /* add in the new bits */
3412 /* put it all back */
3413 ice_memcpy(dest, &dest_qword, sizeof(dest_qword), ICE_NONDMA_TO_DMA);
3417 * ice_set_ctx - set context bits in packed structure
3418 * @src_ctx: pointer to a generic non-packed context structure
3419 * @dest_ctx: pointer to memory for the packed structure
3420 * @ce_info: a description of the structure to be transformed
3423 ice_set_ctx(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)
3427 for (f = 0; ce_info[f].width; f++) {
3428 /* We have to deal with each element of the FW response
3429 * using the correct size so that we are correct regardless
3430 * of the endianness of the machine.
3432 switch (ce_info[f].size_of) {
3434 ice_write_byte(src_ctx, dest_ctx, &ce_info[f]);
3437 ice_write_word(src_ctx, dest_ctx, &ce_info[f]);
3440 ice_write_dword(src_ctx, dest_ctx, &ce_info[f]);
3443 ice_write_qword(src_ctx, dest_ctx, &ce_info[f]);
3446 return ICE_ERR_INVAL_SIZE;
3457 * ice_read_byte - read context byte into struct
3458 * @src_ctx: the context structure to read from
3459 * @dest_ctx: the context to be written to
3460 * @ce_info: a description of the struct to be filled
3463 ice_read_byte(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info)
3469 /* prepare the bits and mask */
3470 shift_width = ce_info->lsb % 8;
3471 mask = (u8)(BIT(ce_info->width) - 1);
3473 /* shift to correct alignment */
3474 mask <<= shift_width;
3476 /* get the current bits from the src bit string */
3477 src = src_ctx + (ce_info->lsb / 8);
3479 ice_memcpy(&dest_byte, src, sizeof(dest_byte), ICE_DMA_TO_NONDMA);
3481 dest_byte &= ~(mask);
3483 dest_byte >>= shift_width;
3485 /* get the address from the struct field */
3486 target = dest_ctx + ce_info->offset;
3488 /* put it back in the struct */
3489 ice_memcpy(target, &dest_byte, sizeof(dest_byte), ICE_NONDMA_TO_DMA);
3493 * ice_read_word - read context word into struct
3494 * @src_ctx: the context structure to read from
3495 * @dest_ctx: the context to be written to
3496 * @ce_info: a description of the struct to be filled
3499 ice_read_word(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info)
3501 u16 dest_word, mask;
3506 /* prepare the bits and mask */
3507 shift_width = ce_info->lsb % 8;
3508 mask = BIT(ce_info->width) - 1;
3510 /* shift to correct alignment */
3511 mask <<= shift_width;
3513 /* get the current bits from the src bit string */
3514 src = src_ctx + (ce_info->lsb / 8);
3516 ice_memcpy(&src_word, src, sizeof(src_word), ICE_DMA_TO_NONDMA);
3518 /* the data in the memory is stored as little endian so mask it
3521 src_word &= ~(CPU_TO_LE16(mask));
3523 /* get the data back into host order before shifting */
3524 dest_word = LE16_TO_CPU(src_word);
3526 dest_word >>= shift_width;
3528 /* get the address from the struct field */
3529 target = dest_ctx + ce_info->offset;
3531 /* put it back in the struct */
3532 ice_memcpy(target, &dest_word, sizeof(dest_word), ICE_NONDMA_TO_DMA);
3536 * ice_read_dword - read context dword into struct
3537 * @src_ctx: the context structure to read from
3538 * @dest_ctx: the context to be written to
3539 * @ce_info: a description of the struct to be filled
3542 ice_read_dword(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info)
3544 u32 dest_dword, mask;
3549 /* prepare the bits and mask */
3550 shift_width = ce_info->lsb % 8;
3552 /* if the field width is exactly 32 on an x86 machine, then the shift
3553 * operation will not work because the SHL instructions count is masked
3554 * to 5 bits so the shift will do nothing
3556 if (ce_info->width < 32)
3557 mask = BIT(ce_info->width) - 1;
3561 /* shift to correct alignment */
3562 mask <<= shift_width;
3564 /* get the current bits from the src bit string */
3565 src = src_ctx + (ce_info->lsb / 8);
3567 ice_memcpy(&src_dword, src, sizeof(src_dword), ICE_DMA_TO_NONDMA);
3569 /* the data in the memory is stored as little endian so mask it
3572 src_dword &= ~(CPU_TO_LE32(mask));
3574 /* get the data back into host order before shifting */
3575 dest_dword = LE32_TO_CPU(src_dword);
3577 dest_dword >>= shift_width;
3579 /* get the address from the struct field */
3580 target = dest_ctx + ce_info->offset;
3582 /* put it back in the struct */
3583 ice_memcpy(target, &dest_dword, sizeof(dest_dword), ICE_NONDMA_TO_DMA);
3587 * ice_read_qword - read context qword into struct
3588 * @src_ctx: the context structure to read from
3589 * @dest_ctx: the context to be written to
3590 * @ce_info: a description of the struct to be filled
3593 ice_read_qword(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info)
3595 u64 dest_qword, mask;
3600 /* prepare the bits and mask */
3601 shift_width = ce_info->lsb % 8;
3603 /* if the field width is exactly 64 on an x86 machine, then the shift
3604 * operation will not work because the SHL instructions count is masked
3605 * to 6 bits so the shift will do nothing
3607 if (ce_info->width < 64)
3608 mask = BIT_ULL(ce_info->width) - 1;
3612 /* shift to correct alignment */
3613 mask <<= shift_width;
3615 /* get the current bits from the src bit string */
3616 src = src_ctx + (ce_info->lsb / 8);
3618 ice_memcpy(&src_qword, src, sizeof(src_qword), ICE_DMA_TO_NONDMA);
3620 /* the data in the memory is stored as little endian so mask it
3623 src_qword &= ~(CPU_TO_LE64(mask));
3625 /* get the data back into host order before shifting */
3626 dest_qword = LE64_TO_CPU(src_qword);
3628 dest_qword >>= shift_width;
3630 /* get the address from the struct field */
3631 target = dest_ctx + ce_info->offset;
3633 /* put it back in the struct */
3634 ice_memcpy(target, &dest_qword, sizeof(dest_qword), ICE_NONDMA_TO_DMA);
3638 * ice_get_ctx - extract context bits from a packed structure
3639 * @src_ctx: pointer to a generic packed context structure
3640 * @dest_ctx: pointer to a generic non-packed context structure
3641 * @ce_info: a description of the structure to be read from
3644 ice_get_ctx(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info)
3648 for (f = 0; ce_info[f].width; f++) {
3649 switch (ce_info[f].size_of) {
3651 ice_read_byte(src_ctx, dest_ctx, &ce_info[f]);
3654 ice_read_word(src_ctx, dest_ctx, &ce_info[f]);
3657 ice_read_dword(src_ctx, dest_ctx, &ce_info[f]);
3660 ice_read_qword(src_ctx, dest_ctx, &ce_info[f]);
3663 /* nothing to do, just keep going */
3672 * ice_get_lan_q_ctx - get the LAN queue context for the given VSI and TC
3673 * @hw: pointer to the HW struct
3674 * @vsi_handle: software VSI handle
3676 * @q_handle: software queue handle
3679 ice_get_lan_q_ctx(struct ice_hw *hw, u16 vsi_handle, u8 tc, u16 q_handle)
3681 struct ice_vsi_ctx *vsi;
3682 struct ice_q_ctx *q_ctx;
3684 vsi = ice_get_vsi_ctx(hw, vsi_handle);
3687 if (q_handle >= vsi->num_lan_q_entries[tc])
3689 if (!vsi->lan_q_ctx[tc])
3691 q_ctx = vsi->lan_q_ctx[tc];
3692 return &q_ctx[q_handle];
3697 * @pi: port information structure
3698 * @vsi_handle: software VSI handle
3700 * @q_handle: software queue handle
3701 * @num_qgrps: Number of added queue groups
3702 * @buf: list of queue groups to be added
3703 * @buf_size: size of buffer for indirect command
3704 * @cd: pointer to command details structure or NULL
3706 * This function adds one LAN queue
3709 ice_ena_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u16 q_handle,
3710 u8 num_qgrps, struct ice_aqc_add_tx_qgrp *buf, u16 buf_size,
3711 struct ice_sq_cd *cd)
3713 struct ice_aqc_txsched_elem_data node = { 0 };
3714 struct ice_sched_node *parent;
3715 struct ice_q_ctx *q_ctx;
3716 enum ice_status status;
3719 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY)
3722 if (num_qgrps > 1 || buf->num_txqs > 1)
3723 return ICE_ERR_MAX_LIMIT;
3727 if (!ice_is_vsi_valid(hw, vsi_handle))
3728 return ICE_ERR_PARAM;
3730 ice_acquire_lock(&pi->sched_lock);
3732 q_ctx = ice_get_lan_q_ctx(hw, vsi_handle, tc, q_handle);
3734 ice_debug(hw, ICE_DBG_SCHED, "Enaq: invalid queue handle %d\n",
3736 status = ICE_ERR_PARAM;
3740 /* find a parent node */
3741 parent = ice_sched_get_free_qparent(pi, vsi_handle, tc,
3742 ICE_SCHED_NODE_OWNER_LAN);
3744 status = ICE_ERR_PARAM;
3748 buf->parent_teid = parent->info.node_teid;
3749 node.parent_teid = parent->info.node_teid;
3750 /* Mark that the values in the "generic" section as valid. The default
3751 * value in the "generic" section is zero. This means that :
3752 * - Scheduling mode is Bytes Per Second (BPS), indicated by Bit 0.
3753 * - 0 priority among siblings, indicated by Bit 1-3.
3754 * - WFQ, indicated by Bit 4.
3755 * - 0 Adjustment value is used in PSM credit update flow, indicated by
3757 * - Bit 7 is reserved.
3758 * Without setting the generic section as valid in valid_sections, the
3759 * Admin queue command will fail with error code ICE_AQ_RC_EINVAL.
3761 buf->txqs[0].info.valid_sections = ICE_AQC_ELEM_VALID_GENERIC;
3763 /* add the LAN queue */
3764 status = ice_aq_add_lan_txq(hw, num_qgrps, buf, buf_size, cd);
3765 if (status != ICE_SUCCESS) {
3766 ice_debug(hw, ICE_DBG_SCHED, "enable queue %d failed %d\n",
3767 LE16_TO_CPU(buf->txqs[0].txq_id),
3768 hw->adminq.sq_last_status);
3772 node.node_teid = buf->txqs[0].q_teid;
3773 node.data.elem_type = ICE_AQC_ELEM_TYPE_LEAF;
3774 q_ctx->q_handle = q_handle;
3775 q_ctx->q_teid = LE32_TO_CPU(node.node_teid);
3777 /* add a leaf node into scheduler tree queue layer */
3778 status = ice_sched_add_node(pi, hw->num_tx_sched_layers - 1, &node);
3780 status = ice_sched_replay_q_bw(pi, q_ctx);
3783 ice_release_lock(&pi->sched_lock);
3789 * @pi: port information structure
3790 * @vsi_handle: software VSI handle
3792 * @num_queues: number of queues
3793 * @q_handles: pointer to software queue handle array
3794 * @q_ids: pointer to the q_id array
3795 * @q_teids: pointer to queue node teids
3796 * @rst_src: if called due to reset, specifies the reset source
3797 * @vmvf_num: the relative VM or VF number that is undergoing the reset
3798 * @cd: pointer to command details structure or NULL
3800 * This function removes queues and their corresponding nodes in SW DB
3803 ice_dis_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u8 num_queues,
3804 u16 *q_handles, u16 *q_ids, u32 *q_teids,
3805 enum ice_disq_rst_src rst_src, u16 vmvf_num,
3806 struct ice_sq_cd *cd)
3808 enum ice_status status = ICE_ERR_DOES_NOT_EXIST;
3809 struct ice_aqc_dis_txq_item qg_list;
3810 struct ice_q_ctx *q_ctx;
3813 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY)
3818 /* if queue is disabled already yet the disable queue command
3819 * has to be sent to complete the VF reset, then call
3820 * ice_aq_dis_lan_txq without any queue information
3823 return ice_aq_dis_lan_txq(pi->hw, 0, NULL, 0, rst_src,
3828 ice_acquire_lock(&pi->sched_lock);
3830 for (i = 0; i < num_queues; i++) {
3831 struct ice_sched_node *node;
3833 node = ice_sched_find_node_by_teid(pi->root, q_teids[i]);
3836 q_ctx = ice_get_lan_q_ctx(pi->hw, vsi_handle, tc, q_handles[i]);
3838 ice_debug(pi->hw, ICE_DBG_SCHED, "invalid queue handle%d\n",
3842 if (q_ctx->q_handle != q_handles[i]) {
3843 ice_debug(pi->hw, ICE_DBG_SCHED, "Err:handles %d %d\n",
3844 q_ctx->q_handle, q_handles[i]);
3847 qg_list.parent_teid = node->info.parent_teid;
3849 qg_list.q_id[0] = CPU_TO_LE16(q_ids[i]);
3850 status = ice_aq_dis_lan_txq(pi->hw, 1, &qg_list,
3851 sizeof(qg_list), rst_src, vmvf_num,
3854 if (status != ICE_SUCCESS)
3856 ice_free_sched_node(pi, node);
3857 q_ctx->q_handle = ICE_INVAL_Q_HANDLE;
3859 ice_release_lock(&pi->sched_lock);
3864 * ice_cfg_vsi_qs - configure the new/existing VSI queues
3865 * @pi: port information structure
3866 * @vsi_handle: software VSI handle
3867 * @tc_bitmap: TC bitmap
3868 * @maxqs: max queues array per TC
3869 * @owner: LAN or RDMA
3871 * This function adds/updates the VSI queues per TC.
3873 static enum ice_status
3874 ice_cfg_vsi_qs(struct ice_port_info *pi, u16 vsi_handle, u8 tc_bitmap,
3875 u16 *maxqs, u8 owner)
3877 enum ice_status status = ICE_SUCCESS;
3880 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY)
3883 if (!ice_is_vsi_valid(pi->hw, vsi_handle))
3884 return ICE_ERR_PARAM;
3886 ice_acquire_lock(&pi->sched_lock);
3888 ice_for_each_traffic_class(i) {
3889 /* configuration is possible only if TC node is present */
3890 if (!ice_sched_get_tc_node(pi, i))
3893 status = ice_sched_cfg_vsi(pi, vsi_handle, i, maxqs[i], owner,
3894 ice_is_tc_ena(tc_bitmap, i));
3899 ice_release_lock(&pi->sched_lock);
3904 * ice_cfg_vsi_lan - configure VSI LAN queues
3905 * @pi: port information structure
3906 * @vsi_handle: software VSI handle
3907 * @tc_bitmap: TC bitmap
3908 * @max_lanqs: max LAN queues array per TC
3910 * This function adds/updates the VSI LAN queues per TC.
3913 ice_cfg_vsi_lan(struct ice_port_info *pi, u16 vsi_handle, u8 tc_bitmap,
3916 return ice_cfg_vsi_qs(pi, vsi_handle, tc_bitmap, max_lanqs,
3917 ICE_SCHED_NODE_OWNER_LAN);
3923 * ice_replay_pre_init - replay pre initialization
3924 * @hw: pointer to the HW struct
3926 * Initializes required config data for VSI, FD, ACL, and RSS before replay.
3928 static enum ice_status ice_replay_pre_init(struct ice_hw *hw)
3930 struct ice_switch_info *sw = hw->switch_info;
3933 /* Delete old entries from replay filter list head if there is any */
3934 ice_rm_all_sw_replay_rule_info(hw);
3935 /* In start of replay, move entries into replay_rules list, it
3936 * will allow adding rules entries back to filt_rules list,
3937 * which is operational list.
3939 for (i = 0; i < ICE_MAX_NUM_RECIPES; i++)
3940 LIST_REPLACE_INIT(&sw->recp_list[i].filt_rules,
3941 &sw->recp_list[i].filt_replay_rules);
3942 ice_sched_replay_agg_vsi_preinit(hw);
3944 return ice_sched_replay_tc_node_bw(hw);
3948 * ice_replay_vsi - replay VSI configuration
3949 * @hw: pointer to the HW struct
3950 * @vsi_handle: driver VSI handle
3952 * Restore all VSI configuration after reset. It is required to call this
3953 * function with main VSI first.
3955 enum ice_status ice_replay_vsi(struct ice_hw *hw, u16 vsi_handle)
3957 enum ice_status status;
3959 if (!ice_is_vsi_valid(hw, vsi_handle))
3960 return ICE_ERR_PARAM;
3962 /* Replay pre-initialization if there is any */
3963 if (vsi_handle == ICE_MAIN_VSI_HANDLE) {
3964 status = ice_replay_pre_init(hw);
3968 /* Replay per VSI all RSS configurations */
3969 status = ice_replay_rss_cfg(hw, vsi_handle);
3972 /* Replay per VSI all filters */
3973 status = ice_replay_vsi_all_fltr(hw, vsi_handle);
3975 status = ice_replay_vsi_agg(hw, vsi_handle);
3980 * ice_replay_post - post replay configuration cleanup
3981 * @hw: pointer to the HW struct
3983 * Post replay cleanup.
3985 void ice_replay_post(struct ice_hw *hw)
3987 /* Delete old entries from replay filter list head */
3988 ice_rm_all_sw_replay_rule_info(hw);
3989 ice_sched_replay_agg(hw);
3993 * ice_stat_update40 - read 40 bit stat from the chip and update stat values
3994 * @hw: ptr to the hardware info
3995 * @hireg: high 32 bit HW register to read from
3996 * @loreg: low 32 bit HW register to read from
3997 * @prev_stat_loaded: bool to specify if previous stats are loaded
3998 * @prev_stat: ptr to previous loaded stat value
3999 * @cur_stat: ptr to current stat value
4002 ice_stat_update40(struct ice_hw *hw, u32 hireg, u32 loreg,
4003 bool prev_stat_loaded, u64 *prev_stat, u64 *cur_stat)
4007 new_data = rd32(hw, loreg);
4008 new_data |= ((u64)(rd32(hw, hireg) & 0xFFFF)) << 32;
4010 /* device stats are not reset at PFR, they likely will not be zeroed
4011 * when the driver starts. So save the first values read and use them as
4012 * offsets to be subtracted from the raw values in order to report stats
4013 * that count from zero.
4015 if (!prev_stat_loaded)
4016 *prev_stat = new_data;
4017 if (new_data >= *prev_stat)
4018 *cur_stat = new_data - *prev_stat;
4020 /* to manage the potential roll-over */
4021 *cur_stat = (new_data + BIT_ULL(40)) - *prev_stat;
4022 *cur_stat &= 0xFFFFFFFFFFULL;
4026 * ice_stat_update32 - read 32 bit stat from the chip and update stat values
4027 * @hw: ptr to the hardware info
4028 * @reg: HW register to read from
4029 * @prev_stat_loaded: bool to specify if previous stats are loaded
4030 * @prev_stat: ptr to previous loaded stat value
4031 * @cur_stat: ptr to current stat value
4034 ice_stat_update32(struct ice_hw *hw, u32 reg, bool prev_stat_loaded,
4035 u64 *prev_stat, u64 *cur_stat)
4039 new_data = rd32(hw, reg);
4041 /* device stats are not reset at PFR, they likely will not be zeroed
4042 * when the driver starts. So save the first values read and use them as
4043 * offsets to be subtracted from the raw values in order to report stats
4044 * that count from zero.
4046 if (!prev_stat_loaded)
4047 *prev_stat = new_data;
4048 if (new_data >= *prev_stat)
4049 *cur_stat = new_data - *prev_stat;
4051 /* to manage the potential roll-over */
4052 *cur_stat = (new_data + BIT_ULL(32)) - *prev_stat;
4057 * ice_sched_query_elem - query element information from HW
4058 * @hw: pointer to the HW struct
4059 * @node_teid: node TEID to be queried
4060 * @buf: buffer to element information
4062 * This function queries HW element information
4065 ice_sched_query_elem(struct ice_hw *hw, u32 node_teid,
4066 struct ice_aqc_get_elem *buf)
4068 u16 buf_size, num_elem_ret = 0;
4069 enum ice_status status;
4071 buf_size = sizeof(*buf);
4072 ice_memset(buf, 0, buf_size, ICE_NONDMA_MEM);
4073 buf->generic[0].node_teid = CPU_TO_LE32(node_teid);
4074 status = ice_aq_query_sched_elems(hw, 1, buf, buf_size, &num_elem_ret,
4076 if (status != ICE_SUCCESS || num_elem_ret != 1)
4077 ice_debug(hw, ICE_DBG_SCHED, "query element failed\n");
4082 * ice_is_fw_in_rec_mode
4083 * @hw: pointer to the HW struct
4085 * This function returns true if fw is in recovery mode
4087 bool ice_is_fw_in_rec_mode(struct ice_hw *hw)
4091 /* check the current FW mode */
4092 reg = rd32(hw, GL_MNG_FWSM);
4093 return (reg & GL_MNG_FWSM_FW_MODES_M) > ICE_FW_MODE_DBG;