1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2001-2020 Intel Corporation
5 #include "ice_common.h"
7 #include "ice_adminq_cmd.h"
10 #include "ice_switch.h"
12 #define ICE_PF_RESET_WAIT_COUNT 300
15 * ice_set_mac_type - Sets MAC type
16 * @hw: pointer to the HW structure
18 * This function sets the MAC type of the adapter based on the
19 * vendor ID and device ID stored in the HW structure.
21 static enum ice_status ice_set_mac_type(struct ice_hw *hw)
23 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
25 if (hw->vendor_id != ICE_INTEL_VENDOR_ID)
26 return ICE_ERR_DEVICE_NOT_SUPPORTED;
28 switch (hw->device_id) {
29 case ICE_DEV_ID_E810C_BACKPLANE:
30 case ICE_DEV_ID_E810C_QSFP:
31 case ICE_DEV_ID_E810C_SFP:
32 case ICE_DEV_ID_E810_XXV_BACKPLANE:
33 case ICE_DEV_ID_E810_XXV_QSFP:
34 case ICE_DEV_ID_E810_XXV_SFP:
35 hw->mac_type = ICE_MAC_E810;
37 case ICE_DEV_ID_E822C_10G_BASE_T:
38 case ICE_DEV_ID_E822C_BACKPLANE:
39 case ICE_DEV_ID_E822C_QSFP:
40 case ICE_DEV_ID_E822C_SFP:
41 case ICE_DEV_ID_E822C_SGMII:
42 case ICE_DEV_ID_E822L_10G_BASE_T:
43 case ICE_DEV_ID_E822L_BACKPLANE:
44 case ICE_DEV_ID_E822L_SFP:
45 case ICE_DEV_ID_E822L_SGMII:
46 hw->mac_type = ICE_MAC_GENERIC;
49 hw->mac_type = ICE_MAC_UNKNOWN;
53 ice_debug(hw, ICE_DBG_INIT, "mac_type: %d\n", hw->mac_type);
58 * ice_clear_pf_cfg - Clear PF configuration
59 * @hw: pointer to the hardware structure
61 * Clears any existing PF configuration (VSIs, VSI lists, switch rules, port
62 * configuration, flow director filters, etc.).
64 enum ice_status ice_clear_pf_cfg(struct ice_hw *hw)
66 struct ice_aq_desc desc;
68 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pf_cfg);
70 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
74 * ice_aq_manage_mac_read - manage MAC address read command
75 * @hw: pointer to the HW struct
76 * @buf: a virtual buffer to hold the manage MAC read response
77 * @buf_size: Size of the virtual buffer
78 * @cd: pointer to command details structure or NULL
80 * This function is used to return per PF station MAC address (0x0107).
81 * NOTE: Upon successful completion of this command, MAC address information
82 * is returned in user specified buffer. Please interpret user specified
83 * buffer as "manage_mac_read" response.
84 * Response such as various MAC addresses are stored in HW struct (port.mac)
85 * ice_aq_discover_caps is expected to be called before this function is called.
87 static enum ice_status
88 ice_aq_manage_mac_read(struct ice_hw *hw, void *buf, u16 buf_size,
91 struct ice_aqc_manage_mac_read_resp *resp;
92 struct ice_aqc_manage_mac_read *cmd;
93 struct ice_aq_desc desc;
94 enum ice_status status;
98 cmd = &desc.params.mac_read;
100 if (buf_size < sizeof(*resp))
101 return ICE_ERR_BUF_TOO_SHORT;
103 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_read);
105 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);
109 resp = (struct ice_aqc_manage_mac_read_resp *)buf;
110 flags = LE16_TO_CPU(cmd->flags) & ICE_AQC_MAN_MAC_READ_M;
112 if (!(flags & ICE_AQC_MAN_MAC_LAN_ADDR_VALID)) {
113 ice_debug(hw, ICE_DBG_LAN, "got invalid MAC address\n");
117 /* A single port can report up to two (LAN and WoL) addresses */
118 for (i = 0; i < cmd->num_addr; i++)
119 if (resp[i].addr_type == ICE_AQC_MAN_MAC_ADDR_TYPE_LAN) {
120 ice_memcpy(hw->port_info->mac.lan_addr,
121 resp[i].mac_addr, ETH_ALEN,
123 ice_memcpy(hw->port_info->mac.perm_addr,
125 ETH_ALEN, ICE_DMA_TO_NONDMA);
132 * ice_aq_get_phy_caps - returns PHY capabilities
133 * @pi: port information structure
134 * @qual_mods: report qualified modules
135 * @report_mode: report mode capabilities
136 * @pcaps: structure for PHY capabilities to be filled
137 * @cd: pointer to command details structure or NULL
139 * Returns the various PHY capabilities supported on the Port (0x0600)
142 ice_aq_get_phy_caps(struct ice_port_info *pi, bool qual_mods, u8 report_mode,
143 struct ice_aqc_get_phy_caps_data *pcaps,
144 struct ice_sq_cd *cd)
146 struct ice_aqc_get_phy_caps *cmd;
147 u16 pcaps_size = sizeof(*pcaps);
148 struct ice_aq_desc desc;
149 enum ice_status status;
151 cmd = &desc.params.get_phy;
153 if (!pcaps || (report_mode & ~ICE_AQC_REPORT_MODE_M) || !pi)
154 return ICE_ERR_PARAM;
156 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_phy_caps);
159 cmd->param0 |= CPU_TO_LE16(ICE_AQC_GET_PHY_RQM);
161 cmd->param0 |= CPU_TO_LE16(report_mode);
162 status = ice_aq_send_cmd(pi->hw, &desc, pcaps, pcaps_size, cd);
164 if (status == ICE_SUCCESS && report_mode == ICE_AQC_REPORT_TOPO_CAP) {
165 pi->phy.phy_type_low = LE64_TO_CPU(pcaps->phy_type_low);
166 pi->phy.phy_type_high = LE64_TO_CPU(pcaps->phy_type_high);
173 * ice_aq_get_link_topo_handle - get link topology node return status
174 * @pi: port information structure
175 * @node_type: requested node type
176 * @cd: pointer to command details structure or NULL
178 * Get link topology node return status for specified node type (0x06E0)
180 * Node type cage can be used to determine if cage is present. If AQC
181 * returns error (ENOENT), then no cage present. If no cage present, then
182 * connection type is backplane or BASE-T.
184 static enum ice_status
185 ice_aq_get_link_topo_handle(struct ice_port_info *pi, u8 node_type,
186 struct ice_sq_cd *cd)
188 struct ice_aqc_get_link_topo *cmd;
189 struct ice_aq_desc desc;
191 cmd = &desc.params.get_link_topo;
193 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_topo);
195 cmd->addr.node_type_ctx = (ICE_AQC_LINK_TOPO_NODE_CTX_PORT <<
196 ICE_AQC_LINK_TOPO_NODE_CTX_S);
199 cmd->addr.node_type_ctx |= (ICE_AQC_LINK_TOPO_NODE_TYPE_M & node_type);
201 return ice_aq_send_cmd(pi->hw, &desc, NULL, 0, cd);
205 * ice_is_media_cage_present
206 * @pi: port information structure
208 * Returns true if media cage is present, else false. If no cage, then
209 * media type is backplane or BASE-T.
211 static bool ice_is_media_cage_present(struct ice_port_info *pi)
213 /* Node type cage can be used to determine if cage is present. If AQC
214 * returns error (ENOENT), then no cage present. If no cage present then
215 * connection type is backplane or BASE-T.
217 return !ice_aq_get_link_topo_handle(pi,
218 ICE_AQC_LINK_TOPO_NODE_TYPE_CAGE,
223 * ice_get_media_type - Gets media type
224 * @pi: port information structure
226 static enum ice_media_type ice_get_media_type(struct ice_port_info *pi)
228 struct ice_link_status *hw_link_info;
231 return ICE_MEDIA_UNKNOWN;
233 hw_link_info = &pi->phy.link_info;
234 if (hw_link_info->phy_type_low && hw_link_info->phy_type_high)
235 /* If more than one media type is selected, report unknown */
236 return ICE_MEDIA_UNKNOWN;
238 if (hw_link_info->phy_type_low) {
239 switch (hw_link_info->phy_type_low) {
240 case ICE_PHY_TYPE_LOW_1000BASE_SX:
241 case ICE_PHY_TYPE_LOW_1000BASE_LX:
242 case ICE_PHY_TYPE_LOW_10GBASE_SR:
243 case ICE_PHY_TYPE_LOW_10GBASE_LR:
244 case ICE_PHY_TYPE_LOW_10G_SFI_C2C:
245 case ICE_PHY_TYPE_LOW_25GBASE_SR:
246 case ICE_PHY_TYPE_LOW_25GBASE_LR:
247 case ICE_PHY_TYPE_LOW_40GBASE_SR4:
248 case ICE_PHY_TYPE_LOW_40GBASE_LR4:
249 case ICE_PHY_TYPE_LOW_50GBASE_SR2:
250 case ICE_PHY_TYPE_LOW_50GBASE_LR2:
251 case ICE_PHY_TYPE_LOW_50GBASE_SR:
252 case ICE_PHY_TYPE_LOW_50GBASE_FR:
253 case ICE_PHY_TYPE_LOW_50GBASE_LR:
254 case ICE_PHY_TYPE_LOW_100GBASE_SR4:
255 case ICE_PHY_TYPE_LOW_100GBASE_LR4:
256 case ICE_PHY_TYPE_LOW_100GBASE_SR2:
257 case ICE_PHY_TYPE_LOW_100GBASE_DR:
258 return ICE_MEDIA_FIBER;
259 case ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC:
260 case ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC:
261 case ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC:
262 case ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC:
263 case ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC:
264 case ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC:
265 case ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC:
266 case ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC:
267 return ICE_MEDIA_FIBER;
268 case ICE_PHY_TYPE_LOW_100BASE_TX:
269 case ICE_PHY_TYPE_LOW_1000BASE_T:
270 case ICE_PHY_TYPE_LOW_2500BASE_T:
271 case ICE_PHY_TYPE_LOW_5GBASE_T:
272 case ICE_PHY_TYPE_LOW_10GBASE_T:
273 case ICE_PHY_TYPE_LOW_25GBASE_T:
274 return ICE_MEDIA_BASET;
275 case ICE_PHY_TYPE_LOW_10G_SFI_DA:
276 case ICE_PHY_TYPE_LOW_25GBASE_CR:
277 case ICE_PHY_TYPE_LOW_25GBASE_CR_S:
278 case ICE_PHY_TYPE_LOW_25GBASE_CR1:
279 case ICE_PHY_TYPE_LOW_40GBASE_CR4:
280 case ICE_PHY_TYPE_LOW_50GBASE_CR2:
281 case ICE_PHY_TYPE_LOW_50GBASE_CP:
282 case ICE_PHY_TYPE_LOW_100GBASE_CR4:
283 case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4:
284 case ICE_PHY_TYPE_LOW_100GBASE_CP2:
286 case ICE_PHY_TYPE_LOW_25G_AUI_C2C:
287 case ICE_PHY_TYPE_LOW_40G_XLAUI:
288 case ICE_PHY_TYPE_LOW_50G_LAUI2:
289 case ICE_PHY_TYPE_LOW_50G_AUI2:
290 case ICE_PHY_TYPE_LOW_50G_AUI1:
291 case ICE_PHY_TYPE_LOW_100G_AUI4:
292 case ICE_PHY_TYPE_LOW_100G_CAUI4:
293 if (ice_is_media_cage_present(pi))
294 return ICE_MEDIA_AUI;
296 case ICE_PHY_TYPE_LOW_1000BASE_KX:
297 case ICE_PHY_TYPE_LOW_2500BASE_KX:
298 case ICE_PHY_TYPE_LOW_2500BASE_X:
299 case ICE_PHY_TYPE_LOW_5GBASE_KR:
300 case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1:
301 case ICE_PHY_TYPE_LOW_25GBASE_KR:
302 case ICE_PHY_TYPE_LOW_25GBASE_KR1:
303 case ICE_PHY_TYPE_LOW_25GBASE_KR_S:
304 case ICE_PHY_TYPE_LOW_40GBASE_KR4:
305 case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4:
306 case ICE_PHY_TYPE_LOW_50GBASE_KR2:
307 case ICE_PHY_TYPE_LOW_100GBASE_KR4:
308 case ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4:
309 return ICE_MEDIA_BACKPLANE;
312 switch (hw_link_info->phy_type_high) {
313 case ICE_PHY_TYPE_HIGH_100G_AUI2:
314 case ICE_PHY_TYPE_HIGH_100G_CAUI2:
315 if (ice_is_media_cage_present(pi))
316 return ICE_MEDIA_AUI;
318 case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4:
319 return ICE_MEDIA_BACKPLANE;
320 case ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC:
321 case ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC:
322 return ICE_MEDIA_FIBER;
325 return ICE_MEDIA_UNKNOWN;
329 * ice_aq_get_link_info
330 * @pi: port information structure
331 * @ena_lse: enable/disable LinkStatusEvent reporting
332 * @link: pointer to link status structure - optional
333 * @cd: pointer to command details structure or NULL
335 * Get Link Status (0x607). Returns the link status of the adapter.
338 ice_aq_get_link_info(struct ice_port_info *pi, bool ena_lse,
339 struct ice_link_status *link, struct ice_sq_cd *cd)
341 struct ice_aqc_get_link_status_data link_data = { 0 };
342 struct ice_aqc_get_link_status *resp;
343 struct ice_link_status *li_old, *li;
344 enum ice_media_type *hw_media_type;
345 struct ice_fc_info *hw_fc_info;
346 bool tx_pause, rx_pause;
347 struct ice_aq_desc desc;
348 enum ice_status status;
353 return ICE_ERR_PARAM;
355 li_old = &pi->phy.link_info_old;
356 hw_media_type = &pi->phy.media_type;
357 li = &pi->phy.link_info;
358 hw_fc_info = &pi->fc;
360 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_status);
361 cmd_flags = (ena_lse) ? ICE_AQ_LSE_ENA : ICE_AQ_LSE_DIS;
362 resp = &desc.params.get_link_status;
363 resp->cmd_flags = CPU_TO_LE16(cmd_flags);
364 resp->lport_num = pi->lport;
366 status = ice_aq_send_cmd(hw, &desc, &link_data, sizeof(link_data), cd);
368 if (status != ICE_SUCCESS)
371 /* save off old link status information */
374 /* update current link status information */
375 li->link_speed = LE16_TO_CPU(link_data.link_speed);
376 li->phy_type_low = LE64_TO_CPU(link_data.phy_type_low);
377 li->phy_type_high = LE64_TO_CPU(link_data.phy_type_high);
378 *hw_media_type = ice_get_media_type(pi);
379 li->link_info = link_data.link_info;
380 li->an_info = link_data.an_info;
381 li->ext_info = link_data.ext_info;
382 li->max_frame_size = LE16_TO_CPU(link_data.max_frame_size);
383 li->fec_info = link_data.cfg & ICE_AQ_FEC_MASK;
384 li->topo_media_conflict = link_data.topo_media_conflict;
385 li->pacing = link_data.cfg & (ICE_AQ_CFG_PACING_M |
386 ICE_AQ_CFG_PACING_TYPE_M);
389 tx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_TX);
390 rx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_RX);
391 if (tx_pause && rx_pause)
392 hw_fc_info->current_mode = ICE_FC_FULL;
394 hw_fc_info->current_mode = ICE_FC_TX_PAUSE;
396 hw_fc_info->current_mode = ICE_FC_RX_PAUSE;
398 hw_fc_info->current_mode = ICE_FC_NONE;
400 li->lse_ena = !!(resp->cmd_flags & CPU_TO_LE16(ICE_AQ_LSE_IS_ENABLED));
402 ice_debug(hw, ICE_DBG_LINK, "link_speed = 0x%x\n", li->link_speed);
403 ice_debug(hw, ICE_DBG_LINK, "phy_type_low = 0x%llx\n",
404 (unsigned long long)li->phy_type_low);
405 ice_debug(hw, ICE_DBG_LINK, "phy_type_high = 0x%llx\n",
406 (unsigned long long)li->phy_type_high);
407 ice_debug(hw, ICE_DBG_LINK, "media_type = 0x%x\n", *hw_media_type);
408 ice_debug(hw, ICE_DBG_LINK, "link_info = 0x%x\n", li->link_info);
409 ice_debug(hw, ICE_DBG_LINK, "an_info = 0x%x\n", li->an_info);
410 ice_debug(hw, ICE_DBG_LINK, "ext_info = 0x%x\n", li->ext_info);
411 ice_debug(hw, ICE_DBG_LINK, "lse_ena = 0x%x\n", li->lse_ena);
412 ice_debug(hw, ICE_DBG_LINK, "max_frame = 0x%x\n", li->max_frame_size);
413 ice_debug(hw, ICE_DBG_LINK, "pacing = 0x%x\n", li->pacing);
415 /* save link status information */
419 /* flag cleared so calling functions don't call AQ again */
420 pi->phy.get_link_info = false;
426 * ice_fill_tx_timer_and_fc_thresh
427 * @hw: pointer to the HW struct
428 * @cmd: pointer to MAC cfg structure
430 * Add Tx timer and FC refresh threshold info to Set MAC Config AQ command
434 ice_fill_tx_timer_and_fc_thresh(struct ice_hw *hw,
435 struct ice_aqc_set_mac_cfg *cmd)
437 u16 fc_thres_val, tx_timer_val;
440 /* We read back the transmit timer and fc threshold value of
441 * LFC. Thus, we will use index =
442 * PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX.
444 * Also, because we are opearating on transmit timer and fc
445 * threshold of LFC, we don't turn on any bit in tx_tmr_priority
447 #define IDX_OF_LFC PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX
449 /* Retrieve the transmit timer */
450 val = rd32(hw, PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(IDX_OF_LFC));
452 PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_HSEC_CTL_TX_PAUSE_QUANTA_M;
453 cmd->tx_tmr_value = CPU_TO_LE16(tx_timer_val);
455 /* Retrieve the fc threshold */
456 val = rd32(hw, PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(IDX_OF_LFC));
457 fc_thres_val = val & PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_M;
459 cmd->fc_refresh_threshold = CPU_TO_LE16(fc_thres_val);
464 * @hw: pointer to the HW struct
465 * @max_frame_size: Maximum Frame Size to be supported
466 * @cd: pointer to command details structure or NULL
468 * Set MAC configuration (0x0603)
471 ice_aq_set_mac_cfg(struct ice_hw *hw, u16 max_frame_size, struct ice_sq_cd *cd)
473 struct ice_aqc_set_mac_cfg *cmd;
474 struct ice_aq_desc desc;
476 cmd = &desc.params.set_mac_cfg;
478 if (max_frame_size == 0)
479 return ICE_ERR_PARAM;
481 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_mac_cfg);
483 cmd->max_frame_size = CPU_TO_LE16(max_frame_size);
485 ice_fill_tx_timer_and_fc_thresh(hw, cmd);
487 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
491 * ice_init_fltr_mgmt_struct - initializes filter management list and locks
492 * @hw: pointer to the HW struct
494 enum ice_status ice_init_fltr_mgmt_struct(struct ice_hw *hw)
496 struct ice_switch_info *sw;
497 enum ice_status status;
499 hw->switch_info = (struct ice_switch_info *)
500 ice_malloc(hw, sizeof(*hw->switch_info));
502 sw = hw->switch_info;
505 return ICE_ERR_NO_MEMORY;
507 INIT_LIST_HEAD(&sw->vsi_list_map_head);
509 status = ice_init_def_sw_recp(hw, &hw->switch_info->recp_list);
511 ice_free(hw, hw->switch_info);
518 * ice_cleanup_fltr_mgmt_single - clears single filter mngt struct
519 * @hw: pointer to the HW struct
520 * @sw: pointer to switch info struct for which function clears filters
523 ice_cleanup_fltr_mgmt_single(struct ice_hw *hw, struct ice_switch_info *sw)
525 struct ice_vsi_list_map_info *v_pos_map;
526 struct ice_vsi_list_map_info *v_tmp_map;
527 struct ice_sw_recipe *recps;
533 LIST_FOR_EACH_ENTRY_SAFE(v_pos_map, v_tmp_map, &sw->vsi_list_map_head,
534 ice_vsi_list_map_info, list_entry) {
535 LIST_DEL(&v_pos_map->list_entry);
536 ice_free(hw, v_pos_map);
538 recps = sw->recp_list;
539 for (i = 0; i < ICE_MAX_NUM_RECIPES; i++) {
540 struct ice_recp_grp_entry *rg_entry, *tmprg_entry;
542 recps[i].root_rid = i;
543 LIST_FOR_EACH_ENTRY_SAFE(rg_entry, tmprg_entry,
544 &recps[i].rg_list, ice_recp_grp_entry,
546 LIST_DEL(&rg_entry->l_entry);
547 ice_free(hw, rg_entry);
550 if (recps[i].adv_rule) {
551 struct ice_adv_fltr_mgmt_list_entry *tmp_entry;
552 struct ice_adv_fltr_mgmt_list_entry *lst_itr;
554 ice_destroy_lock(&recps[i].filt_rule_lock);
555 LIST_FOR_EACH_ENTRY_SAFE(lst_itr, tmp_entry,
556 &recps[i].filt_rules,
557 ice_adv_fltr_mgmt_list_entry,
559 LIST_DEL(&lst_itr->list_entry);
560 ice_free(hw, lst_itr->lkups);
561 ice_free(hw, lst_itr);
564 struct ice_fltr_mgmt_list_entry *lst_itr, *tmp_entry;
566 ice_destroy_lock(&recps[i].filt_rule_lock);
567 LIST_FOR_EACH_ENTRY_SAFE(lst_itr, tmp_entry,
568 &recps[i].filt_rules,
569 ice_fltr_mgmt_list_entry,
571 LIST_DEL(&lst_itr->list_entry);
572 ice_free(hw, lst_itr);
575 if (recps[i].root_buf)
576 ice_free(hw, recps[i].root_buf);
578 ice_rm_sw_replay_rule_info(hw, sw);
579 ice_free(hw, sw->recp_list);
584 * ice_cleanup_all_fltr_mgmt - cleanup filter management list and locks
585 * @hw: pointer to the HW struct
587 void ice_cleanup_fltr_mgmt_struct(struct ice_hw *hw)
589 ice_cleanup_fltr_mgmt_single(hw, hw->switch_info);
593 * ice_get_itr_intrl_gran
594 * @hw: pointer to the HW struct
596 * Determines the ITR/INTRL granularities based on the maximum aggregate
597 * bandwidth according to the device's configuration during power-on.
599 static void ice_get_itr_intrl_gran(struct ice_hw *hw)
601 u8 max_agg_bw = (rd32(hw, GL_PWR_MODE_CTL) &
602 GL_PWR_MODE_CTL_CAR_MAX_BW_M) >>
603 GL_PWR_MODE_CTL_CAR_MAX_BW_S;
605 switch (max_agg_bw) {
606 case ICE_MAX_AGG_BW_200G:
607 case ICE_MAX_AGG_BW_100G:
608 case ICE_MAX_AGG_BW_50G:
609 hw->itr_gran = ICE_ITR_GRAN_ABOVE_25;
610 hw->intrl_gran = ICE_INTRL_GRAN_ABOVE_25;
612 case ICE_MAX_AGG_BW_25G:
613 hw->itr_gran = ICE_ITR_GRAN_MAX_25;
614 hw->intrl_gran = ICE_INTRL_GRAN_MAX_25;
620 * ice_print_rollback_msg - print FW rollback message
621 * @hw: pointer to the hardware structure
623 void ice_print_rollback_msg(struct ice_hw *hw)
625 char nvm_str[ICE_NVM_VER_LEN] = { 0 };
626 struct ice_nvm_info *nvm = &hw->nvm;
627 struct ice_orom_info *orom;
631 SNPRINTF(nvm_str, sizeof(nvm_str), "%x.%02x 0x%x %d.%d.%d",
632 nvm->major_ver, nvm->minor_ver, nvm->eetrack, orom->major,
633 orom->build, orom->patch);
635 "Firmware rollback mode detected. Current version is NVM: %s, FW: %d.%d. Device may exhibit limited functionality. Refer to the Intel(R) Ethernet Adapters and Devices User Guide for details on firmware rollback mode\n",
636 nvm_str, hw->fw_maj_ver, hw->fw_min_ver);
640 * ice_init_hw - main hardware initialization routine
641 * @hw: pointer to the hardware structure
643 enum ice_status ice_init_hw(struct ice_hw *hw)
645 struct ice_aqc_get_phy_caps_data *pcaps;
646 enum ice_status status;
650 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
652 /* Set MAC type based on DeviceID */
653 status = ice_set_mac_type(hw);
657 hw->pf_id = (u8)(rd32(hw, PF_FUNC_RID) &
658 PF_FUNC_RID_FUNCTION_NUMBER_M) >>
659 PF_FUNC_RID_FUNCTION_NUMBER_S;
661 status = ice_reset(hw, ICE_RESET_PFR);
665 ice_get_itr_intrl_gran(hw);
667 status = ice_create_all_ctrlq(hw);
669 goto err_unroll_cqinit;
671 status = ice_init_nvm(hw);
673 goto err_unroll_cqinit;
675 if (ice_get_fw_mode(hw) == ICE_FW_MODE_ROLLBACK)
676 ice_print_rollback_msg(hw);
678 status = ice_clear_pf_cfg(hw);
680 goto err_unroll_cqinit;
682 /* Set bit to enable Flow Director filters */
683 wr32(hw, PFQF_FD_ENA, PFQF_FD_ENA_FD_ENA_M);
684 INIT_LIST_HEAD(&hw->fdir_list_head);
686 ice_clear_pxe_mode(hw);
688 status = ice_get_caps(hw);
690 goto err_unroll_cqinit;
692 hw->port_info = (struct ice_port_info *)
693 ice_malloc(hw, sizeof(*hw->port_info));
694 if (!hw->port_info) {
695 status = ICE_ERR_NO_MEMORY;
696 goto err_unroll_cqinit;
699 /* set the back pointer to HW */
700 hw->port_info->hw = hw;
702 /* Initialize port_info struct with switch configuration data */
703 status = ice_get_initial_sw_cfg(hw);
705 goto err_unroll_alloc;
708 /* Query the allocated resources for Tx scheduler */
709 status = ice_sched_query_res_alloc(hw);
711 ice_debug(hw, ICE_DBG_SCHED,
712 "Failed to get scheduler allocated resources\n");
713 goto err_unroll_alloc;
715 ice_sched_get_psm_clk_freq(hw);
717 /* Initialize port_info struct with scheduler data */
718 status = ice_sched_init_port(hw->port_info);
720 goto err_unroll_sched;
722 pcaps = (struct ice_aqc_get_phy_caps_data *)
723 ice_malloc(hw, sizeof(*pcaps));
725 status = ICE_ERR_NO_MEMORY;
726 goto err_unroll_sched;
729 /* Initialize port_info struct with PHY capabilities */
730 status = ice_aq_get_phy_caps(hw->port_info, false,
731 ICE_AQC_REPORT_TOPO_CAP, pcaps, NULL);
734 goto err_unroll_sched;
736 /* Initialize port_info struct with link information */
737 status = ice_aq_get_link_info(hw->port_info, false, NULL, NULL);
739 goto err_unroll_sched;
740 /* need a valid SW entry point to build a Tx tree */
741 if (!hw->sw_entry_point_layer) {
742 ice_debug(hw, ICE_DBG_SCHED, "invalid sw entry point\n");
743 status = ICE_ERR_CFG;
744 goto err_unroll_sched;
746 INIT_LIST_HEAD(&hw->agg_list);
747 /* Initialize max burst size */
748 if (!hw->max_burst_size)
749 ice_cfg_rl_burst_size(hw, ICE_SCHED_DFLT_BURST_SIZE);
750 status = ice_init_fltr_mgmt_struct(hw);
752 goto err_unroll_sched;
754 /* Get MAC information */
755 /* A single port can report up to two (LAN and WoL) addresses */
756 mac_buf = ice_calloc(hw, 2,
757 sizeof(struct ice_aqc_manage_mac_read_resp));
758 mac_buf_len = 2 * sizeof(struct ice_aqc_manage_mac_read_resp);
761 status = ICE_ERR_NO_MEMORY;
762 goto err_unroll_fltr_mgmt_struct;
765 status = ice_aq_manage_mac_read(hw, mac_buf, mac_buf_len, NULL);
766 ice_free(hw, mac_buf);
769 goto err_unroll_fltr_mgmt_struct;
770 /* enable jumbo frame support at MAC level */
771 status = ice_aq_set_mac_cfg(hw, ICE_AQ_SET_MAC_FRAME_SIZE_MAX, NULL);
773 goto err_unroll_fltr_mgmt_struct;
774 /* Obtain counter base index which would be used by flow director */
775 status = ice_alloc_fd_res_cntr(hw, &hw->fd_ctr_base);
777 goto err_unroll_fltr_mgmt_struct;
778 status = ice_init_hw_tbls(hw);
780 goto err_unroll_fltr_mgmt_struct;
781 ice_init_lock(&hw->tnl_lock);
784 err_unroll_fltr_mgmt_struct:
785 ice_cleanup_fltr_mgmt_struct(hw);
787 ice_sched_cleanup_all(hw);
789 ice_free(hw, hw->port_info);
790 hw->port_info = NULL;
792 ice_destroy_all_ctrlq(hw);
797 * ice_deinit_hw - unroll initialization operations done by ice_init_hw
798 * @hw: pointer to the hardware structure
800 * This should be called only during nominal operation, not as a result of
801 * ice_init_hw() failing since ice_init_hw() will take care of unrolling
802 * applicable initializations if it fails for any reason.
804 void ice_deinit_hw(struct ice_hw *hw)
806 ice_free_fd_res_cntr(hw, hw->fd_ctr_base);
807 ice_cleanup_fltr_mgmt_struct(hw);
809 ice_sched_cleanup_all(hw);
810 ice_sched_clear_agg(hw);
812 ice_free_hw_tbls(hw);
813 ice_destroy_lock(&hw->tnl_lock);
816 ice_free(hw, hw->port_info);
817 hw->port_info = NULL;
820 ice_destroy_all_ctrlq(hw);
822 /* Clear VSI contexts if not already cleared */
823 ice_clear_all_vsi_ctx(hw);
827 * ice_check_reset - Check to see if a global reset is complete
828 * @hw: pointer to the hardware structure
830 enum ice_status ice_check_reset(struct ice_hw *hw)
832 u32 cnt, reg = 0, grst_delay, uld_mask;
834 /* Poll for Device Active state in case a recent CORER, GLOBR,
835 * or EMPR has occurred. The grst delay value is in 100ms units.
836 * Add 1sec for outstanding AQ commands that can take a long time.
838 grst_delay = ((rd32(hw, GLGEN_RSTCTL) & GLGEN_RSTCTL_GRSTDEL_M) >>
839 GLGEN_RSTCTL_GRSTDEL_S) + 10;
841 for (cnt = 0; cnt < grst_delay; cnt++) {
842 ice_msec_delay(100, true);
843 reg = rd32(hw, GLGEN_RSTAT);
844 if (!(reg & GLGEN_RSTAT_DEVSTATE_M))
848 if (cnt == grst_delay) {
849 ice_debug(hw, ICE_DBG_INIT,
850 "Global reset polling failed to complete.\n");
851 return ICE_ERR_RESET_FAILED;
854 #define ICE_RESET_DONE_MASK (GLNVM_ULD_PCIER_DONE_M |\
855 GLNVM_ULD_PCIER_DONE_1_M |\
856 GLNVM_ULD_CORER_DONE_M |\
857 GLNVM_ULD_GLOBR_DONE_M |\
858 GLNVM_ULD_POR_DONE_M |\
859 GLNVM_ULD_POR_DONE_1_M |\
860 GLNVM_ULD_PCIER_DONE_2_M)
862 uld_mask = ICE_RESET_DONE_MASK;
864 /* Device is Active; check Global Reset processes are done */
865 for (cnt = 0; cnt < ICE_PF_RESET_WAIT_COUNT; cnt++) {
866 reg = rd32(hw, GLNVM_ULD) & uld_mask;
867 if (reg == uld_mask) {
868 ice_debug(hw, ICE_DBG_INIT,
869 "Global reset processes done. %d\n", cnt);
872 ice_msec_delay(10, true);
875 if (cnt == ICE_PF_RESET_WAIT_COUNT) {
876 ice_debug(hw, ICE_DBG_INIT,
877 "Wait for Reset Done timed out. GLNVM_ULD = 0x%x\n",
879 return ICE_ERR_RESET_FAILED;
886 * ice_pf_reset - Reset the PF
887 * @hw: pointer to the hardware structure
889 * If a global reset has been triggered, this function checks
890 * for its completion and then issues the PF reset
892 static enum ice_status ice_pf_reset(struct ice_hw *hw)
896 /* If at function entry a global reset was already in progress, i.e.
897 * state is not 'device active' or any of the reset done bits are not
898 * set in GLNVM_ULD, there is no need for a PF Reset; poll until the
899 * global reset is done.
901 if ((rd32(hw, GLGEN_RSTAT) & GLGEN_RSTAT_DEVSTATE_M) ||
902 (rd32(hw, GLNVM_ULD) & ICE_RESET_DONE_MASK) ^ ICE_RESET_DONE_MASK) {
903 /* poll on global reset currently in progress until done */
904 if (ice_check_reset(hw))
905 return ICE_ERR_RESET_FAILED;
911 reg = rd32(hw, PFGEN_CTRL);
913 wr32(hw, PFGEN_CTRL, (reg | PFGEN_CTRL_PFSWR_M));
915 /* Wait for the PFR to complete. The wait time is the global config lock
916 * timeout plus the PFR timeout which will account for a possible reset
917 * that is occurring during a download package operation.
919 for (cnt = 0; cnt < ICE_GLOBAL_CFG_LOCK_TIMEOUT +
920 ICE_PF_RESET_WAIT_COUNT; cnt++) {
921 reg = rd32(hw, PFGEN_CTRL);
922 if (!(reg & PFGEN_CTRL_PFSWR_M))
925 ice_msec_delay(1, true);
928 if (cnt == ICE_PF_RESET_WAIT_COUNT) {
929 ice_debug(hw, ICE_DBG_INIT,
930 "PF reset polling failed to complete.\n");
931 return ICE_ERR_RESET_FAILED;
938 * ice_reset - Perform different types of reset
939 * @hw: pointer to the hardware structure
940 * @req: reset request
942 * This function triggers a reset as specified by the req parameter.
945 * If anything other than a PF reset is triggered, PXE mode is restored.
946 * This has to be cleared using ice_clear_pxe_mode again, once the AQ
947 * interface has been restored in the rebuild flow.
949 enum ice_status ice_reset(struct ice_hw *hw, enum ice_reset_req req)
955 return ice_pf_reset(hw);
956 case ICE_RESET_CORER:
957 ice_debug(hw, ICE_DBG_INIT, "CoreR requested\n");
958 val = GLGEN_RTRIG_CORER_M;
960 case ICE_RESET_GLOBR:
961 ice_debug(hw, ICE_DBG_INIT, "GlobalR requested\n");
962 val = GLGEN_RTRIG_GLOBR_M;
965 return ICE_ERR_PARAM;
968 val |= rd32(hw, GLGEN_RTRIG);
969 wr32(hw, GLGEN_RTRIG, val);
972 /* wait for the FW to be ready */
973 return ice_check_reset(hw);
977 * ice_copy_rxq_ctx_to_hw
978 * @hw: pointer to the hardware structure
979 * @ice_rxq_ctx: pointer to the rxq context
980 * @rxq_index: the index of the Rx queue
982 * Copies rxq context from dense structure to HW register space
984 static enum ice_status
985 ice_copy_rxq_ctx_to_hw(struct ice_hw *hw, u8 *ice_rxq_ctx, u32 rxq_index)
990 return ICE_ERR_BAD_PTR;
992 if (rxq_index > QRX_CTRL_MAX_INDEX)
993 return ICE_ERR_PARAM;
995 /* Copy each dword separately to HW */
996 for (i = 0; i < ICE_RXQ_CTX_SIZE_DWORDS; i++) {
997 wr32(hw, QRX_CONTEXT(i, rxq_index),
998 *((u32 *)(ice_rxq_ctx + (i * sizeof(u32)))));
1000 ice_debug(hw, ICE_DBG_QCTX, "qrxdata[%d]: %08X\n", i,
1001 *((u32 *)(ice_rxq_ctx + (i * sizeof(u32)))));
1007 /* LAN Rx Queue Context */
1008 static const struct ice_ctx_ele ice_rlan_ctx_info[] = {
1009 /* Field Width LSB */
1010 ICE_CTX_STORE(ice_rlan_ctx, head, 13, 0),
1011 ICE_CTX_STORE(ice_rlan_ctx, cpuid, 8, 13),
1012 ICE_CTX_STORE(ice_rlan_ctx, base, 57, 32),
1013 ICE_CTX_STORE(ice_rlan_ctx, qlen, 13, 89),
1014 ICE_CTX_STORE(ice_rlan_ctx, dbuf, 7, 102),
1015 ICE_CTX_STORE(ice_rlan_ctx, hbuf, 5, 109),
1016 ICE_CTX_STORE(ice_rlan_ctx, dtype, 2, 114),
1017 ICE_CTX_STORE(ice_rlan_ctx, dsize, 1, 116),
1018 ICE_CTX_STORE(ice_rlan_ctx, crcstrip, 1, 117),
1019 ICE_CTX_STORE(ice_rlan_ctx, l2tsel, 1, 119),
1020 ICE_CTX_STORE(ice_rlan_ctx, hsplit_0, 4, 120),
1021 ICE_CTX_STORE(ice_rlan_ctx, hsplit_1, 2, 124),
1022 ICE_CTX_STORE(ice_rlan_ctx, showiv, 1, 127),
1023 ICE_CTX_STORE(ice_rlan_ctx, rxmax, 14, 174),
1024 ICE_CTX_STORE(ice_rlan_ctx, tphrdesc_ena, 1, 193),
1025 ICE_CTX_STORE(ice_rlan_ctx, tphwdesc_ena, 1, 194),
1026 ICE_CTX_STORE(ice_rlan_ctx, tphdata_ena, 1, 195),
1027 ICE_CTX_STORE(ice_rlan_ctx, tphhead_ena, 1, 196),
1028 ICE_CTX_STORE(ice_rlan_ctx, lrxqthresh, 3, 198),
1029 ICE_CTX_STORE(ice_rlan_ctx, prefena, 1, 201),
1035 * @hw: pointer to the hardware structure
1036 * @rlan_ctx: pointer to the rxq context
1037 * @rxq_index: the index of the Rx queue
1039 * Converts rxq context from sparse to dense structure and then writes
1040 * it to HW register space and enables the hardware to prefetch descriptors
1041 * instead of only fetching them on demand
1044 ice_write_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx,
1047 u8 ctx_buf[ICE_RXQ_CTX_SZ] = { 0 };
1050 return ICE_ERR_BAD_PTR;
1052 rlan_ctx->prefena = 1;
1054 ice_set_ctx(hw, (u8 *)rlan_ctx, ctx_buf, ice_rlan_ctx_info);
1055 return ice_copy_rxq_ctx_to_hw(hw, ctx_buf, rxq_index);
1060 * @hw: pointer to the hardware structure
1061 * @rxq_index: the index of the Rx queue to clear
1063 * Clears rxq context in HW register space
1065 enum ice_status ice_clear_rxq_ctx(struct ice_hw *hw, u32 rxq_index)
1069 if (rxq_index > QRX_CTRL_MAX_INDEX)
1070 return ICE_ERR_PARAM;
1072 /* Clear each dword register separately */
1073 for (i = 0; i < ICE_RXQ_CTX_SIZE_DWORDS; i++)
1074 wr32(hw, QRX_CONTEXT(i, rxq_index), 0);
1079 /* LAN Tx Queue Context */
1080 const struct ice_ctx_ele ice_tlan_ctx_info[] = {
1081 /* Field Width LSB */
1082 ICE_CTX_STORE(ice_tlan_ctx, base, 57, 0),
1083 ICE_CTX_STORE(ice_tlan_ctx, port_num, 3, 57),
1084 ICE_CTX_STORE(ice_tlan_ctx, cgd_num, 5, 60),
1085 ICE_CTX_STORE(ice_tlan_ctx, pf_num, 3, 65),
1086 ICE_CTX_STORE(ice_tlan_ctx, vmvf_num, 10, 68),
1087 ICE_CTX_STORE(ice_tlan_ctx, vmvf_type, 2, 78),
1088 ICE_CTX_STORE(ice_tlan_ctx, src_vsi, 10, 80),
1089 ICE_CTX_STORE(ice_tlan_ctx, tsyn_ena, 1, 90),
1090 ICE_CTX_STORE(ice_tlan_ctx, internal_usage_flag, 1, 91),
1091 ICE_CTX_STORE(ice_tlan_ctx, alt_vlan, 1, 92),
1092 ICE_CTX_STORE(ice_tlan_ctx, cpuid, 8, 93),
1093 ICE_CTX_STORE(ice_tlan_ctx, wb_mode, 1, 101),
1094 ICE_CTX_STORE(ice_tlan_ctx, tphrd_desc, 1, 102),
1095 ICE_CTX_STORE(ice_tlan_ctx, tphrd, 1, 103),
1096 ICE_CTX_STORE(ice_tlan_ctx, tphwr_desc, 1, 104),
1097 ICE_CTX_STORE(ice_tlan_ctx, cmpq_id, 9, 105),
1098 ICE_CTX_STORE(ice_tlan_ctx, qnum_in_func, 14, 114),
1099 ICE_CTX_STORE(ice_tlan_ctx, itr_notification_mode, 1, 128),
1100 ICE_CTX_STORE(ice_tlan_ctx, adjust_prof_id, 6, 129),
1101 ICE_CTX_STORE(ice_tlan_ctx, qlen, 13, 135),
1102 ICE_CTX_STORE(ice_tlan_ctx, quanta_prof_idx, 4, 148),
1103 ICE_CTX_STORE(ice_tlan_ctx, tso_ena, 1, 152),
1104 ICE_CTX_STORE(ice_tlan_ctx, tso_qnum, 11, 153),
1105 ICE_CTX_STORE(ice_tlan_ctx, legacy_int, 1, 164),
1106 ICE_CTX_STORE(ice_tlan_ctx, drop_ena, 1, 165),
1107 ICE_CTX_STORE(ice_tlan_ctx, cache_prof_idx, 2, 166),
1108 ICE_CTX_STORE(ice_tlan_ctx, pkt_shaper_prof_idx, 3, 168),
1109 ICE_CTX_STORE(ice_tlan_ctx, int_q_state, 122, 171),
1114 * ice_copy_tx_cmpltnq_ctx_to_hw
1115 * @hw: pointer to the hardware structure
1116 * @ice_tx_cmpltnq_ctx: pointer to the Tx completion queue context
1117 * @tx_cmpltnq_index: the index of the completion queue
1119 * Copies Tx completion queue context from dense structure to HW register space
1121 static enum ice_status
1122 ice_copy_tx_cmpltnq_ctx_to_hw(struct ice_hw *hw, u8 *ice_tx_cmpltnq_ctx,
1123 u32 tx_cmpltnq_index)
1127 if (!ice_tx_cmpltnq_ctx)
1128 return ICE_ERR_BAD_PTR;
1130 if (tx_cmpltnq_index > GLTCLAN_CQ_CNTX0_MAX_INDEX)
1131 return ICE_ERR_PARAM;
1133 /* Copy each dword separately to HW */
1134 for (i = 0; i < ICE_TX_CMPLTNQ_CTX_SIZE_DWORDS; i++) {
1135 wr32(hw, GLTCLAN_CQ_CNTX(i, tx_cmpltnq_index),
1136 *((u32 *)(ice_tx_cmpltnq_ctx + (i * sizeof(u32)))));
1138 ice_debug(hw, ICE_DBG_QCTX, "cmpltnqdata[%d]: %08X\n", i,
1139 *((u32 *)(ice_tx_cmpltnq_ctx + (i * sizeof(u32)))));
1145 /* LAN Tx Completion Queue Context */
1146 static const struct ice_ctx_ele ice_tx_cmpltnq_ctx_info[] = {
1147 /* Field Width LSB */
1148 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, base, 57, 0),
1149 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, q_len, 18, 64),
1150 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, generation, 1, 96),
1151 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, wrt_ptr, 22, 97),
1152 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, pf_num, 3, 128),
1153 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, vmvf_num, 10, 131),
1154 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, vmvf_type, 2, 141),
1155 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, tph_desc_wr, 1, 160),
1156 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, cpuid, 8, 161),
1157 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, cmpltn_cache, 512, 192),
1162 * ice_write_tx_cmpltnq_ctx
1163 * @hw: pointer to the hardware structure
1164 * @tx_cmpltnq_ctx: pointer to the completion queue context
1165 * @tx_cmpltnq_index: the index of the completion queue
1167 * Converts completion queue context from sparse to dense structure and then
1168 * writes it to HW register space
1171 ice_write_tx_cmpltnq_ctx(struct ice_hw *hw,
1172 struct ice_tx_cmpltnq_ctx *tx_cmpltnq_ctx,
1173 u32 tx_cmpltnq_index)
1175 u8 ctx_buf[ICE_TX_CMPLTNQ_CTX_SIZE_DWORDS * sizeof(u32)] = { 0 };
1177 ice_set_ctx(hw, (u8 *)tx_cmpltnq_ctx, ctx_buf, ice_tx_cmpltnq_ctx_info);
1178 return ice_copy_tx_cmpltnq_ctx_to_hw(hw, ctx_buf, tx_cmpltnq_index);
1182 * ice_clear_tx_cmpltnq_ctx
1183 * @hw: pointer to the hardware structure
1184 * @tx_cmpltnq_index: the index of the completion queue to clear
1186 * Clears Tx completion queue context in HW register space
1189 ice_clear_tx_cmpltnq_ctx(struct ice_hw *hw, u32 tx_cmpltnq_index)
1193 if (tx_cmpltnq_index > GLTCLAN_CQ_CNTX0_MAX_INDEX)
1194 return ICE_ERR_PARAM;
1196 /* Clear each dword register separately */
1197 for (i = 0; i < ICE_TX_CMPLTNQ_CTX_SIZE_DWORDS; i++)
1198 wr32(hw, GLTCLAN_CQ_CNTX(i, tx_cmpltnq_index), 0);
1204 * ice_copy_tx_drbell_q_ctx_to_hw
1205 * @hw: pointer to the hardware structure
1206 * @ice_tx_drbell_q_ctx: pointer to the doorbell queue context
1207 * @tx_drbell_q_index: the index of the doorbell queue
1209 * Copies doorbell queue context from dense structure to HW register space
1211 static enum ice_status
1212 ice_copy_tx_drbell_q_ctx_to_hw(struct ice_hw *hw, u8 *ice_tx_drbell_q_ctx,
1213 u32 tx_drbell_q_index)
1217 if (!ice_tx_drbell_q_ctx)
1218 return ICE_ERR_BAD_PTR;
1220 if (tx_drbell_q_index > QTX_COMM_DBLQ_DBELL_MAX_INDEX)
1221 return ICE_ERR_PARAM;
1223 /* Copy each dword separately to HW */
1224 for (i = 0; i < ICE_TX_DRBELL_Q_CTX_SIZE_DWORDS; i++) {
1225 wr32(hw, QTX_COMM_DBLQ_CNTX(i, tx_drbell_q_index),
1226 *((u32 *)(ice_tx_drbell_q_ctx + (i * sizeof(u32)))));
1228 ice_debug(hw, ICE_DBG_QCTX, "tx_drbell_qdata[%d]: %08X\n", i,
1229 *((u32 *)(ice_tx_drbell_q_ctx + (i * sizeof(u32)))));
1235 /* LAN Tx Doorbell Queue Context info */
1236 static const struct ice_ctx_ele ice_tx_drbell_q_ctx_info[] = {
1237 /* Field Width LSB */
1238 ICE_CTX_STORE(ice_tx_drbell_q_ctx, base, 57, 0),
1239 ICE_CTX_STORE(ice_tx_drbell_q_ctx, ring_len, 13, 64),
1240 ICE_CTX_STORE(ice_tx_drbell_q_ctx, pf_num, 3, 80),
1241 ICE_CTX_STORE(ice_tx_drbell_q_ctx, vf_num, 8, 84),
1242 ICE_CTX_STORE(ice_tx_drbell_q_ctx, vmvf_type, 2, 94),
1243 ICE_CTX_STORE(ice_tx_drbell_q_ctx, cpuid, 8, 96),
1244 ICE_CTX_STORE(ice_tx_drbell_q_ctx, tph_desc_rd, 1, 104),
1245 ICE_CTX_STORE(ice_tx_drbell_q_ctx, tph_desc_wr, 1, 108),
1246 ICE_CTX_STORE(ice_tx_drbell_q_ctx, db_q_en, 1, 112),
1247 ICE_CTX_STORE(ice_tx_drbell_q_ctx, rd_head, 13, 128),
1248 ICE_CTX_STORE(ice_tx_drbell_q_ctx, rd_tail, 13, 144),
1253 * ice_write_tx_drbell_q_ctx
1254 * @hw: pointer to the hardware structure
1255 * @tx_drbell_q_ctx: pointer to the doorbell queue context
1256 * @tx_drbell_q_index: the index of the doorbell queue
1258 * Converts doorbell queue context from sparse to dense structure and then
1259 * writes it to HW register space
1262 ice_write_tx_drbell_q_ctx(struct ice_hw *hw,
1263 struct ice_tx_drbell_q_ctx *tx_drbell_q_ctx,
1264 u32 tx_drbell_q_index)
1266 u8 ctx_buf[ICE_TX_DRBELL_Q_CTX_SIZE_DWORDS * sizeof(u32)] = { 0 };
1268 ice_set_ctx(hw, (u8 *)tx_drbell_q_ctx, ctx_buf,
1269 ice_tx_drbell_q_ctx_info);
1270 return ice_copy_tx_drbell_q_ctx_to_hw(hw, ctx_buf, tx_drbell_q_index);
1274 * ice_clear_tx_drbell_q_ctx
1275 * @hw: pointer to the hardware structure
1276 * @tx_drbell_q_index: the index of the doorbell queue to clear
1278 * Clears doorbell queue context in HW register space
1281 ice_clear_tx_drbell_q_ctx(struct ice_hw *hw, u32 tx_drbell_q_index)
1285 if (tx_drbell_q_index > QTX_COMM_DBLQ_DBELL_MAX_INDEX)
1286 return ICE_ERR_PARAM;
1288 /* Clear each dword register separately */
1289 for (i = 0; i < ICE_TX_DRBELL_Q_CTX_SIZE_DWORDS; i++)
1290 wr32(hw, QTX_COMM_DBLQ_CNTX(i, tx_drbell_q_index), 0);
1295 /* FW Admin Queue command wrappers */
1298 * ice_aq_send_cmd - send FW Admin Queue command to FW Admin Queue
1299 * @hw: pointer to the HW struct
1300 * @desc: descriptor describing the command
1301 * @buf: buffer to use for indirect commands (NULL for direct commands)
1302 * @buf_size: size of buffer for indirect commands (0 for direct commands)
1303 * @cd: pointer to command details structure
1305 * Helper function to send FW Admin Queue commands to the FW Admin Queue.
1308 ice_aq_send_cmd(struct ice_hw *hw, struct ice_aq_desc *desc, void *buf,
1309 u16 buf_size, struct ice_sq_cd *cd)
1311 if (hw->aq_send_cmd_fn) {
1312 enum ice_status status = ICE_ERR_NOT_READY;
1313 u16 retval = ICE_AQ_RC_OK;
1315 ice_acquire_lock(&hw->adminq.sq_lock);
1316 if (!hw->aq_send_cmd_fn(hw->aq_send_cmd_param, desc,
1318 retval = LE16_TO_CPU(desc->retval);
1319 /* strip off FW internal code */
1322 if (retval == ICE_AQ_RC_OK)
1323 status = ICE_SUCCESS;
1325 status = ICE_ERR_AQ_ERROR;
1328 hw->adminq.sq_last_status = (enum ice_aq_err)retval;
1329 ice_release_lock(&hw->adminq.sq_lock);
1333 return ice_sq_send_cmd(hw, &hw->adminq, desc, buf, buf_size, cd);
1338 * @hw: pointer to the HW struct
1339 * @cd: pointer to command details structure or NULL
1341 * Get the firmware version (0x0001) from the admin queue commands
1343 enum ice_status ice_aq_get_fw_ver(struct ice_hw *hw, struct ice_sq_cd *cd)
1345 struct ice_aqc_get_ver *resp;
1346 struct ice_aq_desc desc;
1347 enum ice_status status;
1349 resp = &desc.params.get_ver;
1351 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_ver);
1353 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
1356 hw->fw_branch = resp->fw_branch;
1357 hw->fw_maj_ver = resp->fw_major;
1358 hw->fw_min_ver = resp->fw_minor;
1359 hw->fw_patch = resp->fw_patch;
1360 hw->fw_build = LE32_TO_CPU(resp->fw_build);
1361 hw->api_branch = resp->api_branch;
1362 hw->api_maj_ver = resp->api_major;
1363 hw->api_min_ver = resp->api_minor;
1364 hw->api_patch = resp->api_patch;
1371 * ice_aq_send_driver_ver
1372 * @hw: pointer to the HW struct
1373 * @dv: driver's major, minor version
1374 * @cd: pointer to command details structure or NULL
1376 * Send the driver version (0x0002) to the firmware
1379 ice_aq_send_driver_ver(struct ice_hw *hw, struct ice_driver_ver *dv,
1380 struct ice_sq_cd *cd)
1382 struct ice_aqc_driver_ver *cmd;
1383 struct ice_aq_desc desc;
1386 cmd = &desc.params.driver_ver;
1389 return ICE_ERR_PARAM;
1391 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_driver_ver);
1393 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
1394 cmd->major_ver = dv->major_ver;
1395 cmd->minor_ver = dv->minor_ver;
1396 cmd->build_ver = dv->build_ver;
1397 cmd->subbuild_ver = dv->subbuild_ver;
1400 while (len < sizeof(dv->driver_string) &&
1401 IS_ASCII(dv->driver_string[len]) && dv->driver_string[len])
1404 return ice_aq_send_cmd(hw, &desc, dv->driver_string, len, cd);
1409 * @hw: pointer to the HW struct
1410 * @unloading: is the driver unloading itself
1412 * Tell the Firmware that we're shutting down the AdminQ and whether
1413 * or not the driver is unloading as well (0x0003).
1415 enum ice_status ice_aq_q_shutdown(struct ice_hw *hw, bool unloading)
1417 struct ice_aqc_q_shutdown *cmd;
1418 struct ice_aq_desc desc;
1420 cmd = &desc.params.q_shutdown;
1422 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_q_shutdown);
1425 cmd->driver_unloading = ICE_AQC_DRIVER_UNLOADING;
1427 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
1432 * @hw: pointer to the HW struct
1434 * @access: access type
1435 * @sdp_number: resource number
1436 * @timeout: the maximum time in ms that the driver may hold the resource
1437 * @cd: pointer to command details structure or NULL
1439 * Requests common resource using the admin queue commands (0x0008).
1440 * When attempting to acquire the Global Config Lock, the driver can
1441 * learn of three states:
1442 * 1) ICE_SUCCESS - acquired lock, and can perform download package
1443 * 2) ICE_ERR_AQ_ERROR - did not get lock, driver should fail to load
1444 * 3) ICE_ERR_AQ_NO_WORK - did not get lock, but another driver has
1445 * successfully downloaded the package; the driver does
1446 * not have to download the package and can continue
1449 * Note that if the caller is in an acquire lock, perform action, release lock
1450 * phase of operation, it is possible that the FW may detect a timeout and issue
1451 * a CORER. In this case, the driver will receive a CORER interrupt and will
1452 * have to determine its cause. The calling thread that is handling this flow
1453 * will likely get an error propagated back to it indicating the Download
1454 * Package, Update Package or the Release Resource AQ commands timed out.
1456 static enum ice_status
1457 ice_aq_req_res(struct ice_hw *hw, enum ice_aq_res_ids res,
1458 enum ice_aq_res_access_type access, u8 sdp_number, u32 *timeout,
1459 struct ice_sq_cd *cd)
1461 struct ice_aqc_req_res *cmd_resp;
1462 struct ice_aq_desc desc;
1463 enum ice_status status;
1465 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
1467 cmd_resp = &desc.params.res_owner;
1469 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_req_res);
1471 cmd_resp->res_id = CPU_TO_LE16(res);
1472 cmd_resp->access_type = CPU_TO_LE16(access);
1473 cmd_resp->res_number = CPU_TO_LE32(sdp_number);
1474 cmd_resp->timeout = CPU_TO_LE32(*timeout);
1477 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
1479 /* The completion specifies the maximum time in ms that the driver
1480 * may hold the resource in the Timeout field.
1483 /* Global config lock response utilizes an additional status field.
1485 * If the Global config lock resource is held by some other driver, the
1486 * command completes with ICE_AQ_RES_GLBL_IN_PROG in the status field
1487 * and the timeout field indicates the maximum time the current owner
1488 * of the resource has to free it.
1490 if (res == ICE_GLOBAL_CFG_LOCK_RES_ID) {
1491 if (LE16_TO_CPU(cmd_resp->status) == ICE_AQ_RES_GLBL_SUCCESS) {
1492 *timeout = LE32_TO_CPU(cmd_resp->timeout);
1494 } else if (LE16_TO_CPU(cmd_resp->status) ==
1495 ICE_AQ_RES_GLBL_IN_PROG) {
1496 *timeout = LE32_TO_CPU(cmd_resp->timeout);
1497 return ICE_ERR_AQ_ERROR;
1498 } else if (LE16_TO_CPU(cmd_resp->status) ==
1499 ICE_AQ_RES_GLBL_DONE) {
1500 return ICE_ERR_AQ_NO_WORK;
1503 /* invalid FW response, force a timeout immediately */
1505 return ICE_ERR_AQ_ERROR;
1508 /* If the resource is held by some other driver, the command completes
1509 * with a busy return value and the timeout field indicates the maximum
1510 * time the current owner of the resource has to free it.
1512 if (!status || hw->adminq.sq_last_status == ICE_AQ_RC_EBUSY)
1513 *timeout = LE32_TO_CPU(cmd_resp->timeout);
1519 * ice_aq_release_res
1520 * @hw: pointer to the HW struct
1522 * @sdp_number: resource number
1523 * @cd: pointer to command details structure or NULL
1525 * release common resource using the admin queue commands (0x0009)
1527 static enum ice_status
1528 ice_aq_release_res(struct ice_hw *hw, enum ice_aq_res_ids res, u8 sdp_number,
1529 struct ice_sq_cd *cd)
1531 struct ice_aqc_req_res *cmd;
1532 struct ice_aq_desc desc;
1534 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
1536 cmd = &desc.params.res_owner;
1538 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_release_res);
1540 cmd->res_id = CPU_TO_LE16(res);
1541 cmd->res_number = CPU_TO_LE32(sdp_number);
1543 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
1548 * @hw: pointer to the HW structure
1550 * @access: access type (read or write)
1551 * @timeout: timeout in milliseconds
1553 * This function will attempt to acquire the ownership of a resource.
1556 ice_acquire_res(struct ice_hw *hw, enum ice_aq_res_ids res,
1557 enum ice_aq_res_access_type access, u32 timeout)
1559 #define ICE_RES_POLLING_DELAY_MS 10
1560 u32 delay = ICE_RES_POLLING_DELAY_MS;
1561 u32 time_left = timeout;
1562 enum ice_status status;
1564 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
1566 status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL);
1568 /* A return code of ICE_ERR_AQ_NO_WORK means that another driver has
1569 * previously acquired the resource and performed any necessary updates;
1570 * in this case the caller does not obtain the resource and has no
1571 * further work to do.
1573 if (status == ICE_ERR_AQ_NO_WORK)
1574 goto ice_acquire_res_exit;
1577 ice_debug(hw, ICE_DBG_RES,
1578 "resource %d acquire type %d failed.\n", res, access);
1580 /* If necessary, poll until the current lock owner timeouts */
1581 timeout = time_left;
1582 while (status && timeout && time_left) {
1583 ice_msec_delay(delay, true);
1584 timeout = (timeout > delay) ? timeout - delay : 0;
1585 status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL);
1587 if (status == ICE_ERR_AQ_NO_WORK)
1588 /* lock free, but no work to do */
1595 if (status && status != ICE_ERR_AQ_NO_WORK)
1596 ice_debug(hw, ICE_DBG_RES, "resource acquire timed out.\n");
1598 ice_acquire_res_exit:
1599 if (status == ICE_ERR_AQ_NO_WORK) {
1600 if (access == ICE_RES_WRITE)
1601 ice_debug(hw, ICE_DBG_RES,
1602 "resource indicates no work to do.\n");
1604 ice_debug(hw, ICE_DBG_RES,
1605 "Warning: ICE_ERR_AQ_NO_WORK not expected\n");
1612 * @hw: pointer to the HW structure
1615 * This function will release a resource using the proper Admin Command.
1617 void ice_release_res(struct ice_hw *hw, enum ice_aq_res_ids res)
1619 enum ice_status status;
1620 u32 total_delay = 0;
1622 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
1624 status = ice_aq_release_res(hw, res, 0, NULL);
1626 /* there are some rare cases when trying to release the resource
1627 * results in an admin queue timeout, so handle them correctly
1629 while ((status == ICE_ERR_AQ_TIMEOUT) &&
1630 (total_delay < hw->adminq.sq_cmd_timeout)) {
1631 ice_msec_delay(1, true);
1632 status = ice_aq_release_res(hw, res, 0, NULL);
1638 * ice_aq_alloc_free_res - command to allocate/free resources
1639 * @hw: pointer to the HW struct
1640 * @num_entries: number of resource entries in buffer
1641 * @buf: Indirect buffer to hold data parameters and response
1642 * @buf_size: size of buffer for indirect commands
1643 * @opc: pass in the command opcode
1644 * @cd: pointer to command details structure or NULL
1646 * Helper function to allocate/free resources using the admin queue commands
1649 ice_aq_alloc_free_res(struct ice_hw *hw, u16 num_entries,
1650 struct ice_aqc_alloc_free_res_elem *buf, u16 buf_size,
1651 enum ice_adminq_opc opc, struct ice_sq_cd *cd)
1653 struct ice_aqc_alloc_free_res_cmd *cmd;
1654 struct ice_aq_desc desc;
1656 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
1658 cmd = &desc.params.sw_res_ctrl;
1661 return ICE_ERR_PARAM;
1663 if (buf_size < (num_entries * sizeof(buf->elem[0])))
1664 return ICE_ERR_PARAM;
1666 ice_fill_dflt_direct_cmd_desc(&desc, opc);
1668 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
1670 cmd->num_entries = CPU_TO_LE16(num_entries);
1672 return ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);
1676 * ice_alloc_hw_res - allocate resource
1677 * @hw: pointer to the HW struct
1678 * @type: type of resource
1679 * @num: number of resources to allocate
1680 * @btm: allocate from bottom
1681 * @res: pointer to array that will receive the resources
1684 ice_alloc_hw_res(struct ice_hw *hw, u16 type, u16 num, bool btm, u16 *res)
1686 struct ice_aqc_alloc_free_res_elem *buf;
1687 enum ice_status status;
1690 buf_len = ice_struct_size(buf, elem, num - 1);
1691 buf = (struct ice_aqc_alloc_free_res_elem *)
1692 ice_malloc(hw, buf_len);
1694 return ICE_ERR_NO_MEMORY;
1696 /* Prepare buffer to allocate resource. */
1697 buf->num_elems = CPU_TO_LE16(num);
1698 buf->res_type = CPU_TO_LE16(type | ICE_AQC_RES_TYPE_FLAG_DEDICATED |
1699 ICE_AQC_RES_TYPE_FLAG_IGNORE_INDEX);
1701 buf->res_type |= CPU_TO_LE16(ICE_AQC_RES_TYPE_FLAG_SCAN_BOTTOM);
1703 status = ice_aq_alloc_free_res(hw, 1, buf, buf_len,
1704 ice_aqc_opc_alloc_res, NULL);
1706 goto ice_alloc_res_exit;
1708 ice_memcpy(res, buf->elem, sizeof(buf->elem) * num,
1709 ICE_NONDMA_TO_NONDMA);
1717 * ice_free_hw_res - free allocated HW resource
1718 * @hw: pointer to the HW struct
1719 * @type: type of resource to free
1720 * @num: number of resources
1721 * @res: pointer to array that contains the resources to free
1724 ice_free_hw_res(struct ice_hw *hw, u16 type, u16 num, u16 *res)
1726 struct ice_aqc_alloc_free_res_elem *buf;
1727 enum ice_status status;
1730 buf_len = ice_struct_size(buf, elem, num - 1);
1731 buf = (struct ice_aqc_alloc_free_res_elem *)ice_malloc(hw, buf_len);
1733 return ICE_ERR_NO_MEMORY;
1735 /* Prepare buffer to free resource. */
1736 buf->num_elems = CPU_TO_LE16(num);
1737 buf->res_type = CPU_TO_LE16(type);
1738 ice_memcpy(buf->elem, res, sizeof(buf->elem) * num,
1739 ICE_NONDMA_TO_NONDMA);
1741 status = ice_aq_alloc_free_res(hw, num, buf, buf_len,
1742 ice_aqc_opc_free_res, NULL);
1744 ice_debug(hw, ICE_DBG_SW, "CQ CMD Buffer:\n");
1751 * ice_get_num_per_func - determine number of resources per PF
1752 * @hw: pointer to the HW structure
1753 * @max: value to be evenly split between each PF
1755 * Determine the number of valid functions by going through the bitmap returned
1756 * from parsing capabilities and use this to calculate the number of resources
1757 * per PF based on the max value passed in.
1759 static u32 ice_get_num_per_func(struct ice_hw *hw, u32 max)
1763 #define ICE_CAPS_VALID_FUNCS_M 0xFF
1764 funcs = ice_hweight8(hw->dev_caps.common_cap.valid_functions &
1765 ICE_CAPS_VALID_FUNCS_M);
1774 * ice_parse_caps - parse function/device capabilities
1775 * @hw: pointer to the HW struct
1776 * @buf: pointer to a buffer containing function/device capability records
1777 * @cap_count: number of capability records in the list
1778 * @opc: type of capabilities list to parse
1780 * Helper function to parse function(0x000a)/device(0x000b) capabilities list.
1783 ice_parse_caps(struct ice_hw *hw, void *buf, u32 cap_count,
1784 enum ice_adminq_opc opc)
1786 struct ice_aqc_list_caps_elem *cap_resp;
1787 struct ice_hw_func_caps *func_p = NULL;
1788 struct ice_hw_dev_caps *dev_p = NULL;
1789 struct ice_hw_common_caps *caps;
1796 cap_resp = (struct ice_aqc_list_caps_elem *)buf;
1798 if (opc == ice_aqc_opc_list_dev_caps) {
1799 dev_p = &hw->dev_caps;
1800 caps = &dev_p->common_cap;
1802 } else if (opc == ice_aqc_opc_list_func_caps) {
1803 func_p = &hw->func_caps;
1804 caps = &func_p->common_cap;
1805 prefix = "func cap";
1807 ice_debug(hw, ICE_DBG_INIT, "wrong opcode\n");
1811 for (i = 0; caps && i < cap_count; i++, cap_resp++) {
1812 u32 logical_id = LE32_TO_CPU(cap_resp->logical_id);
1813 u32 phys_id = LE32_TO_CPU(cap_resp->phys_id);
1814 u32 number = LE32_TO_CPU(cap_resp->number);
1815 u16 cap = LE16_TO_CPU(cap_resp->cap);
1818 case ICE_AQC_CAPS_VALID_FUNCTIONS:
1819 caps->valid_functions = number;
1820 ice_debug(hw, ICE_DBG_INIT,
1821 "%s: valid_functions (bitmap) = %d\n", prefix,
1822 caps->valid_functions);
1824 /* store func count for resource management purposes */
1826 dev_p->num_funcs = ice_hweight32(number);
1828 case ICE_AQC_CAPS_VSI:
1830 dev_p->num_vsi_allocd_to_host = number;
1831 ice_debug(hw, ICE_DBG_INIT,
1832 "%s: num_vsi_allocd_to_host = %d\n",
1834 dev_p->num_vsi_allocd_to_host);
1835 } else if (func_p) {
1836 func_p->guar_num_vsi =
1837 ice_get_num_per_func(hw, ICE_MAX_VSI);
1838 ice_debug(hw, ICE_DBG_INIT,
1839 "%s: guar_num_vsi (fw) = %d\n",
1841 ice_debug(hw, ICE_DBG_INIT,
1842 "%s: guar_num_vsi = %d\n",
1843 prefix, func_p->guar_num_vsi);
1846 case ICE_AQC_CAPS_DCB:
1847 caps->dcb = (number == 1);
1848 caps->active_tc_bitmap = logical_id;
1849 caps->maxtc = phys_id;
1850 ice_debug(hw, ICE_DBG_INIT,
1851 "%s: dcb = %d\n", prefix, caps->dcb);
1852 ice_debug(hw, ICE_DBG_INIT,
1853 "%s: active_tc_bitmap = %d\n", prefix,
1854 caps->active_tc_bitmap);
1855 ice_debug(hw, ICE_DBG_INIT,
1856 "%s: maxtc = %d\n", prefix, caps->maxtc);
1858 case ICE_AQC_CAPS_RSS:
1859 caps->rss_table_size = number;
1860 caps->rss_table_entry_width = logical_id;
1861 ice_debug(hw, ICE_DBG_INIT,
1862 "%s: rss_table_size = %d\n", prefix,
1863 caps->rss_table_size);
1864 ice_debug(hw, ICE_DBG_INIT,
1865 "%s: rss_table_entry_width = %d\n", prefix,
1866 caps->rss_table_entry_width);
1868 case ICE_AQC_CAPS_RXQS:
1869 caps->num_rxq = number;
1870 caps->rxq_first_id = phys_id;
1871 ice_debug(hw, ICE_DBG_INIT,
1872 "%s: num_rxq = %d\n", prefix,
1874 ice_debug(hw, ICE_DBG_INIT,
1875 "%s: rxq_first_id = %d\n", prefix,
1876 caps->rxq_first_id);
1878 case ICE_AQC_CAPS_TXQS:
1879 caps->num_txq = number;
1880 caps->txq_first_id = phys_id;
1881 ice_debug(hw, ICE_DBG_INIT,
1882 "%s: num_txq = %d\n", prefix,
1884 ice_debug(hw, ICE_DBG_INIT,
1885 "%s: txq_first_id = %d\n", prefix,
1886 caps->txq_first_id);
1888 case ICE_AQC_CAPS_MSIX:
1889 caps->num_msix_vectors = number;
1890 caps->msix_vector_first_id = phys_id;
1891 ice_debug(hw, ICE_DBG_INIT,
1892 "%s: num_msix_vectors = %d\n", prefix,
1893 caps->num_msix_vectors);
1894 ice_debug(hw, ICE_DBG_INIT,
1895 "%s: msix_vector_first_id = %d\n", prefix,
1896 caps->msix_vector_first_id);
1898 case ICE_AQC_CAPS_FD:
1900 dev_p->num_flow_director_fltr = number;
1901 ice_debug(hw, ICE_DBG_INIT,
1902 "%s: num_flow_director_fltr = %d\n",
1904 dev_p->num_flow_director_fltr);
1909 if (hw->dcf_enabled)
1911 reg_val = rd32(hw, GLQF_FD_SIZE);
1912 val = (reg_val & GLQF_FD_SIZE_FD_GSIZE_M) >>
1913 GLQF_FD_SIZE_FD_GSIZE_S;
1914 func_p->fd_fltr_guar =
1915 ice_get_num_per_func(hw, val);
1916 val = (reg_val & GLQF_FD_SIZE_FD_BSIZE_M) >>
1917 GLQF_FD_SIZE_FD_BSIZE_S;
1918 func_p->fd_fltr_best_effort = val;
1919 ice_debug(hw, ICE_DBG_INIT,
1920 "%s: fd_fltr_guar = %d\n",
1921 prefix, func_p->fd_fltr_guar);
1922 ice_debug(hw, ICE_DBG_INIT,
1923 "%s: fd_fltr_best_effort = %d\n",
1924 prefix, func_p->fd_fltr_best_effort);
1927 case ICE_AQC_CAPS_MAX_MTU:
1928 caps->max_mtu = number;
1929 ice_debug(hw, ICE_DBG_INIT, "%s: max_mtu = %d\n",
1930 prefix, caps->max_mtu);
1933 ice_debug(hw, ICE_DBG_INIT,
1934 "%s: unknown capability[%d]: 0x%x\n", prefix,
1940 /* Re-calculate capabilities that are dependent on the number of
1941 * physical ports; i.e. some features are not supported or function
1942 * differently on devices with more than 4 ports.
1944 if (hw->dev_caps.num_funcs > 4) {
1945 /* Max 4 TCs per port */
1947 ice_debug(hw, ICE_DBG_INIT,
1948 "%s: maxtc = %d (based on #ports)\n", prefix,
1954 * ice_aq_discover_caps - query function/device capabilities
1955 * @hw: pointer to the HW struct
1956 * @buf: a virtual buffer to hold the capabilities
1957 * @buf_size: Size of the virtual buffer
1958 * @cap_count: cap count needed if AQ err==ENOMEM
1959 * @opc: capabilities type to discover - pass in the command opcode
1960 * @cd: pointer to command details structure or NULL
1962 * Get the function(0x000a)/device(0x000b) capabilities description from
1965 static enum ice_status
1966 ice_aq_discover_caps(struct ice_hw *hw, void *buf, u16 buf_size, u32 *cap_count,
1967 enum ice_adminq_opc opc, struct ice_sq_cd *cd)
1969 struct ice_aqc_list_caps *cmd;
1970 struct ice_aq_desc desc;
1971 enum ice_status status;
1973 cmd = &desc.params.get_cap;
1975 if (opc != ice_aqc_opc_list_func_caps &&
1976 opc != ice_aqc_opc_list_dev_caps)
1977 return ICE_ERR_PARAM;
1979 ice_fill_dflt_direct_cmd_desc(&desc, opc);
1981 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);
1983 ice_parse_caps(hw, buf, LE32_TO_CPU(cmd->count), opc);
1984 else if (hw->adminq.sq_last_status == ICE_AQ_RC_ENOMEM)
1985 *cap_count = LE32_TO_CPU(cmd->count);
1990 * ice_discover_caps - get info about the HW
1991 * @hw: pointer to the hardware structure
1992 * @opc: capabilities type to discover - pass in the command opcode
1994 static enum ice_status
1995 ice_discover_caps(struct ice_hw *hw, enum ice_adminq_opc opc)
1997 enum ice_status status;
2002 /* The driver doesn't know how many capabilities the device will return
2003 * so the buffer size required isn't known ahead of time. The driver
2004 * starts with cbuf_len and if this turns out to be insufficient, the
2005 * device returns ICE_AQ_RC_ENOMEM and also the cap_count it needs.
2006 * The driver then allocates the buffer based on the count and retries
2007 * the operation. So it follows that the retry count is 2.
2009 #define ICE_GET_CAP_BUF_COUNT 40
2010 #define ICE_GET_CAP_RETRY_COUNT 2
2012 cap_count = ICE_GET_CAP_BUF_COUNT;
2013 retries = ICE_GET_CAP_RETRY_COUNT;
2018 cbuf_len = (u16)(cap_count *
2019 sizeof(struct ice_aqc_list_caps_elem));
2020 cbuf = ice_malloc(hw, cbuf_len);
2022 return ICE_ERR_NO_MEMORY;
2024 status = ice_aq_discover_caps(hw, cbuf, cbuf_len, &cap_count,
2028 if (!status || hw->adminq.sq_last_status != ICE_AQ_RC_ENOMEM)
2031 /* If ENOMEM is returned, try again with bigger buffer */
2032 } while (--retries);
2038 * ice_set_safe_mode_caps - Override dev/func capabilities when in safe mode
2039 * @hw: pointer to the hardware structure
2041 void ice_set_safe_mode_caps(struct ice_hw *hw)
2043 struct ice_hw_func_caps *func_caps = &hw->func_caps;
2044 struct ice_hw_dev_caps *dev_caps = &hw->dev_caps;
2045 u32 valid_func, rxq_first_id, txq_first_id;
2046 u32 msix_vector_first_id, max_mtu;
2049 /* cache some func_caps values that should be restored after memset */
2050 valid_func = func_caps->common_cap.valid_functions;
2051 txq_first_id = func_caps->common_cap.txq_first_id;
2052 rxq_first_id = func_caps->common_cap.rxq_first_id;
2053 msix_vector_first_id = func_caps->common_cap.msix_vector_first_id;
2054 max_mtu = func_caps->common_cap.max_mtu;
2056 /* unset func capabilities */
2057 memset(func_caps, 0, sizeof(*func_caps));
2059 /* restore cached values */
2060 func_caps->common_cap.valid_functions = valid_func;
2061 func_caps->common_cap.txq_first_id = txq_first_id;
2062 func_caps->common_cap.rxq_first_id = rxq_first_id;
2063 func_caps->common_cap.msix_vector_first_id = msix_vector_first_id;
2064 func_caps->common_cap.max_mtu = max_mtu;
2066 /* one Tx and one Rx queue in safe mode */
2067 func_caps->common_cap.num_rxq = 1;
2068 func_caps->common_cap.num_txq = 1;
2070 /* two MSIX vectors, one for traffic and one for misc causes */
2071 func_caps->common_cap.num_msix_vectors = 2;
2072 func_caps->guar_num_vsi = 1;
2074 /* cache some dev_caps values that should be restored after memset */
2075 valid_func = dev_caps->common_cap.valid_functions;
2076 txq_first_id = dev_caps->common_cap.txq_first_id;
2077 rxq_first_id = dev_caps->common_cap.rxq_first_id;
2078 msix_vector_first_id = dev_caps->common_cap.msix_vector_first_id;
2079 max_mtu = dev_caps->common_cap.max_mtu;
2080 num_funcs = dev_caps->num_funcs;
2082 /* unset dev capabilities */
2083 memset(dev_caps, 0, sizeof(*dev_caps));
2085 /* restore cached values */
2086 dev_caps->common_cap.valid_functions = valid_func;
2087 dev_caps->common_cap.txq_first_id = txq_first_id;
2088 dev_caps->common_cap.rxq_first_id = rxq_first_id;
2089 dev_caps->common_cap.msix_vector_first_id = msix_vector_first_id;
2090 dev_caps->common_cap.max_mtu = max_mtu;
2091 dev_caps->num_funcs = num_funcs;
2093 /* one Tx and one Rx queue per function in safe mode */
2094 dev_caps->common_cap.num_rxq = num_funcs;
2095 dev_caps->common_cap.num_txq = num_funcs;
2097 /* two MSIX vectors per function */
2098 dev_caps->common_cap.num_msix_vectors = 2 * num_funcs;
2102 * ice_get_caps - get info about the HW
2103 * @hw: pointer to the hardware structure
2105 enum ice_status ice_get_caps(struct ice_hw *hw)
2107 enum ice_status status;
2109 status = ice_discover_caps(hw, ice_aqc_opc_list_dev_caps);
2111 status = ice_discover_caps(hw, ice_aqc_opc_list_func_caps);
2117 * ice_aq_manage_mac_write - manage MAC address write command
2118 * @hw: pointer to the HW struct
2119 * @mac_addr: MAC address to be written as LAA/LAA+WoL/Port address
2120 * @flags: flags to control write behavior
2121 * @cd: pointer to command details structure or NULL
2123 * This function is used to write MAC address to the NVM (0x0108).
2126 ice_aq_manage_mac_write(struct ice_hw *hw, const u8 *mac_addr, u8 flags,
2127 struct ice_sq_cd *cd)
2129 struct ice_aqc_manage_mac_write *cmd;
2130 struct ice_aq_desc desc;
2132 cmd = &desc.params.mac_write;
2133 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_write);
2136 ice_memcpy(cmd->mac_addr, mac_addr, ETH_ALEN, ICE_NONDMA_TO_DMA);
2138 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
2142 * ice_aq_clear_pxe_mode
2143 * @hw: pointer to the HW struct
2145 * Tell the firmware that the driver is taking over from PXE (0x0110).
2147 static enum ice_status ice_aq_clear_pxe_mode(struct ice_hw *hw)
2149 struct ice_aq_desc desc;
2151 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pxe_mode);
2152 desc.params.clear_pxe.rx_cnt = ICE_AQC_CLEAR_PXE_RX_CNT;
2154 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
2158 * ice_clear_pxe_mode - clear pxe operations mode
2159 * @hw: pointer to the HW struct
2161 * Make sure all PXE mode settings are cleared, including things
2162 * like descriptor fetch/write-back mode.
2164 void ice_clear_pxe_mode(struct ice_hw *hw)
2166 if (ice_check_sq_alive(hw, &hw->adminq))
2167 ice_aq_clear_pxe_mode(hw);
2171 * ice_get_link_speed_based_on_phy_type - returns link speed
2172 * @phy_type_low: lower part of phy_type
2173 * @phy_type_high: higher part of phy_type
2175 * This helper function will convert an entry in PHY type structure
2176 * [phy_type_low, phy_type_high] to its corresponding link speed.
2177 * Note: In the structure of [phy_type_low, phy_type_high], there should
2178 * be one bit set, as this function will convert one PHY type to its
2180 * If no bit gets set, ICE_LINK_SPEED_UNKNOWN will be returned
2181 * If more than one bit gets set, ICE_LINK_SPEED_UNKNOWN will be returned
2184 ice_get_link_speed_based_on_phy_type(u64 phy_type_low, u64 phy_type_high)
2186 u16 speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN;
2187 u16 speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN;
2189 switch (phy_type_low) {
2190 case ICE_PHY_TYPE_LOW_100BASE_TX:
2191 case ICE_PHY_TYPE_LOW_100M_SGMII:
2192 speed_phy_type_low = ICE_AQ_LINK_SPEED_100MB;
2194 case ICE_PHY_TYPE_LOW_1000BASE_T:
2195 case ICE_PHY_TYPE_LOW_1000BASE_SX:
2196 case ICE_PHY_TYPE_LOW_1000BASE_LX:
2197 case ICE_PHY_TYPE_LOW_1000BASE_KX:
2198 case ICE_PHY_TYPE_LOW_1G_SGMII:
2199 speed_phy_type_low = ICE_AQ_LINK_SPEED_1000MB;
2201 case ICE_PHY_TYPE_LOW_2500BASE_T:
2202 case ICE_PHY_TYPE_LOW_2500BASE_X:
2203 case ICE_PHY_TYPE_LOW_2500BASE_KX:
2204 speed_phy_type_low = ICE_AQ_LINK_SPEED_2500MB;
2206 case ICE_PHY_TYPE_LOW_5GBASE_T:
2207 case ICE_PHY_TYPE_LOW_5GBASE_KR:
2208 speed_phy_type_low = ICE_AQ_LINK_SPEED_5GB;
2210 case ICE_PHY_TYPE_LOW_10GBASE_T:
2211 case ICE_PHY_TYPE_LOW_10G_SFI_DA:
2212 case ICE_PHY_TYPE_LOW_10GBASE_SR:
2213 case ICE_PHY_TYPE_LOW_10GBASE_LR:
2214 case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1:
2215 case ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC:
2216 case ICE_PHY_TYPE_LOW_10G_SFI_C2C:
2217 speed_phy_type_low = ICE_AQ_LINK_SPEED_10GB;
2219 case ICE_PHY_TYPE_LOW_25GBASE_T:
2220 case ICE_PHY_TYPE_LOW_25GBASE_CR:
2221 case ICE_PHY_TYPE_LOW_25GBASE_CR_S:
2222 case ICE_PHY_TYPE_LOW_25GBASE_CR1:
2223 case ICE_PHY_TYPE_LOW_25GBASE_SR:
2224 case ICE_PHY_TYPE_LOW_25GBASE_LR:
2225 case ICE_PHY_TYPE_LOW_25GBASE_KR:
2226 case ICE_PHY_TYPE_LOW_25GBASE_KR_S:
2227 case ICE_PHY_TYPE_LOW_25GBASE_KR1:
2228 case ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC:
2229 case ICE_PHY_TYPE_LOW_25G_AUI_C2C:
2230 speed_phy_type_low = ICE_AQ_LINK_SPEED_25GB;
2232 case ICE_PHY_TYPE_LOW_40GBASE_CR4:
2233 case ICE_PHY_TYPE_LOW_40GBASE_SR4:
2234 case ICE_PHY_TYPE_LOW_40GBASE_LR4:
2235 case ICE_PHY_TYPE_LOW_40GBASE_KR4:
2236 case ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC:
2237 case ICE_PHY_TYPE_LOW_40G_XLAUI:
2238 speed_phy_type_low = ICE_AQ_LINK_SPEED_40GB;
2240 case ICE_PHY_TYPE_LOW_50GBASE_CR2:
2241 case ICE_PHY_TYPE_LOW_50GBASE_SR2:
2242 case ICE_PHY_TYPE_LOW_50GBASE_LR2:
2243 case ICE_PHY_TYPE_LOW_50GBASE_KR2:
2244 case ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC:
2245 case ICE_PHY_TYPE_LOW_50G_LAUI2:
2246 case ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC:
2247 case ICE_PHY_TYPE_LOW_50G_AUI2:
2248 case ICE_PHY_TYPE_LOW_50GBASE_CP:
2249 case ICE_PHY_TYPE_LOW_50GBASE_SR:
2250 case ICE_PHY_TYPE_LOW_50GBASE_FR:
2251 case ICE_PHY_TYPE_LOW_50GBASE_LR:
2252 case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4:
2253 case ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC:
2254 case ICE_PHY_TYPE_LOW_50G_AUI1:
2255 speed_phy_type_low = ICE_AQ_LINK_SPEED_50GB;
2257 case ICE_PHY_TYPE_LOW_100GBASE_CR4:
2258 case ICE_PHY_TYPE_LOW_100GBASE_SR4:
2259 case ICE_PHY_TYPE_LOW_100GBASE_LR4:
2260 case ICE_PHY_TYPE_LOW_100GBASE_KR4:
2261 case ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC:
2262 case ICE_PHY_TYPE_LOW_100G_CAUI4:
2263 case ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC:
2264 case ICE_PHY_TYPE_LOW_100G_AUI4:
2265 case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4:
2266 case ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4:
2267 case ICE_PHY_TYPE_LOW_100GBASE_CP2:
2268 case ICE_PHY_TYPE_LOW_100GBASE_SR2:
2269 case ICE_PHY_TYPE_LOW_100GBASE_DR:
2270 speed_phy_type_low = ICE_AQ_LINK_SPEED_100GB;
2273 speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN;
2277 switch (phy_type_high) {
2278 case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4:
2279 case ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC:
2280 case ICE_PHY_TYPE_HIGH_100G_CAUI2:
2281 case ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC:
2282 case ICE_PHY_TYPE_HIGH_100G_AUI2:
2283 speed_phy_type_high = ICE_AQ_LINK_SPEED_100GB;
2286 speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN;
2290 if (speed_phy_type_low == ICE_AQ_LINK_SPEED_UNKNOWN &&
2291 speed_phy_type_high == ICE_AQ_LINK_SPEED_UNKNOWN)
2292 return ICE_AQ_LINK_SPEED_UNKNOWN;
2293 else if (speed_phy_type_low != ICE_AQ_LINK_SPEED_UNKNOWN &&
2294 speed_phy_type_high != ICE_AQ_LINK_SPEED_UNKNOWN)
2295 return ICE_AQ_LINK_SPEED_UNKNOWN;
2296 else if (speed_phy_type_low != ICE_AQ_LINK_SPEED_UNKNOWN &&
2297 speed_phy_type_high == ICE_AQ_LINK_SPEED_UNKNOWN)
2298 return speed_phy_type_low;
2300 return speed_phy_type_high;
2304 * ice_update_phy_type
2305 * @phy_type_low: pointer to the lower part of phy_type
2306 * @phy_type_high: pointer to the higher part of phy_type
2307 * @link_speeds_bitmap: targeted link speeds bitmap
2309 * Note: For the link_speeds_bitmap structure, you can check it at
2310 * [ice_aqc_get_link_status->link_speed]. Caller can pass in
2311 * link_speeds_bitmap include multiple speeds.
2313 * Each entry in this [phy_type_low, phy_type_high] structure will
2314 * present a certain link speed. This helper function will turn on bits
2315 * in [phy_type_low, phy_type_high] structure based on the value of
2316 * link_speeds_bitmap input parameter.
2319 ice_update_phy_type(u64 *phy_type_low, u64 *phy_type_high,
2320 u16 link_speeds_bitmap)
2327 /* We first check with low part of phy_type */
2328 for (index = 0; index <= ICE_PHY_TYPE_LOW_MAX_INDEX; index++) {
2329 pt_low = BIT_ULL(index);
2330 speed = ice_get_link_speed_based_on_phy_type(pt_low, 0);
2332 if (link_speeds_bitmap & speed)
2333 *phy_type_low |= BIT_ULL(index);
2336 /* We then check with high part of phy_type */
2337 for (index = 0; index <= ICE_PHY_TYPE_HIGH_MAX_INDEX; index++) {
2338 pt_high = BIT_ULL(index);
2339 speed = ice_get_link_speed_based_on_phy_type(0, pt_high);
2341 if (link_speeds_bitmap & speed)
2342 *phy_type_high |= BIT_ULL(index);
2347 * ice_aq_set_phy_cfg
2348 * @hw: pointer to the HW struct
2349 * @pi: port info structure of the interested logical port
2350 * @cfg: structure with PHY configuration data to be set
2351 * @cd: pointer to command details structure or NULL
2353 * Set the various PHY configuration parameters supported on the Port.
2354 * One or more of the Set PHY config parameters may be ignored in an MFP
2355 * mode as the PF may not have the privilege to set some of the PHY Config
2356 * parameters. This status will be indicated by the command response (0x0601).
2359 ice_aq_set_phy_cfg(struct ice_hw *hw, struct ice_port_info *pi,
2360 struct ice_aqc_set_phy_cfg_data *cfg, struct ice_sq_cd *cd)
2362 struct ice_aq_desc desc;
2363 enum ice_status status;
2366 return ICE_ERR_PARAM;
2368 /* Ensure that only valid bits of cfg->caps can be turned on. */
2369 if (cfg->caps & ~ICE_AQ_PHY_ENA_VALID_MASK) {
2370 ice_debug(hw, ICE_DBG_PHY,
2371 "Invalid bit is set in ice_aqc_set_phy_cfg_data->caps : 0x%x\n",
2374 cfg->caps &= ICE_AQ_PHY_ENA_VALID_MASK;
2377 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_phy_cfg);
2378 desc.params.set_phy.lport_num = pi->lport;
2379 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
2381 ice_debug(hw, ICE_DBG_LINK, "phy_type_low = 0x%llx\n",
2382 (unsigned long long)LE64_TO_CPU(cfg->phy_type_low));
2383 ice_debug(hw, ICE_DBG_LINK, "phy_type_high = 0x%llx\n",
2384 (unsigned long long)LE64_TO_CPU(cfg->phy_type_high));
2385 ice_debug(hw, ICE_DBG_LINK, "caps = 0x%x\n", cfg->caps);
2386 ice_debug(hw, ICE_DBG_LINK, "low_power_ctrl_an = 0x%x\n",
2387 cfg->low_power_ctrl_an);
2388 ice_debug(hw, ICE_DBG_LINK, "eee_cap = 0x%x\n", cfg->eee_cap);
2389 ice_debug(hw, ICE_DBG_LINK, "eeer_value = 0x%x\n", cfg->eeer_value);
2390 ice_debug(hw, ICE_DBG_LINK, "link_fec_opt = 0x%x\n", cfg->link_fec_opt);
2392 status = ice_aq_send_cmd(hw, &desc, cfg, sizeof(*cfg), cd);
2394 if (hw->adminq.sq_last_status == ICE_AQ_RC_EMODE)
2395 status = ICE_SUCCESS;
2398 pi->phy.curr_user_phy_cfg = *cfg;
2404 * ice_update_link_info - update status of the HW network link
2405 * @pi: port info structure of the interested logical port
2407 enum ice_status ice_update_link_info(struct ice_port_info *pi)
2409 struct ice_link_status *li;
2410 enum ice_status status;
2413 return ICE_ERR_PARAM;
2415 li = &pi->phy.link_info;
2417 status = ice_aq_get_link_info(pi, true, NULL, NULL);
2421 if (li->link_info & ICE_AQ_MEDIA_AVAILABLE) {
2422 struct ice_aqc_get_phy_caps_data *pcaps;
2426 pcaps = (struct ice_aqc_get_phy_caps_data *)
2427 ice_malloc(hw, sizeof(*pcaps));
2429 return ICE_ERR_NO_MEMORY;
2431 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_TOPO_CAP,
2433 if (status == ICE_SUCCESS)
2434 ice_memcpy(li->module_type, &pcaps->module_type,
2435 sizeof(li->module_type),
2436 ICE_NONDMA_TO_NONDMA);
2438 ice_free(hw, pcaps);
2445 * ice_cache_phy_user_req
2446 * @pi: port information structure
2447 * @cache_data: PHY logging data
2448 * @cache_mode: PHY logging mode
2450 * Log the user request on (FC, FEC, SPEED) for later user.
2453 ice_cache_phy_user_req(struct ice_port_info *pi,
2454 struct ice_phy_cache_mode_data cache_data,
2455 enum ice_phy_cache_mode cache_mode)
2460 switch (cache_mode) {
2462 pi->phy.curr_user_fc_req = cache_data.data.curr_user_fc_req;
2464 case ICE_SPEED_MODE:
2465 pi->phy.curr_user_speed_req =
2466 cache_data.data.curr_user_speed_req;
2469 pi->phy.curr_user_fec_req = cache_data.data.curr_user_fec_req;
2477 * ice_caps_to_fc_mode
2478 * @caps: PHY capabilities
2480 * Convert PHY FC capabilities to ice FC mode
2482 enum ice_fc_mode ice_caps_to_fc_mode(u8 caps)
2484 if (caps & ICE_AQC_PHY_EN_TX_LINK_PAUSE &&
2485 caps & ICE_AQC_PHY_EN_RX_LINK_PAUSE)
2488 if (caps & ICE_AQC_PHY_EN_TX_LINK_PAUSE)
2489 return ICE_FC_TX_PAUSE;
2491 if (caps & ICE_AQC_PHY_EN_RX_LINK_PAUSE)
2492 return ICE_FC_RX_PAUSE;
2498 * ice_caps_to_fec_mode
2499 * @caps: PHY capabilities
2500 * @fec_options: Link FEC options
2502 * Convert PHY FEC capabilities to ice FEC mode
2504 enum ice_fec_mode ice_caps_to_fec_mode(u8 caps, u8 fec_options)
2506 if (caps & ICE_AQC_PHY_EN_AUTO_FEC)
2507 return ICE_FEC_AUTO;
2509 if (fec_options & (ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN |
2510 ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ |
2511 ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN |
2512 ICE_AQC_PHY_FEC_25G_KR_REQ))
2513 return ICE_FEC_BASER;
2515 if (fec_options & (ICE_AQC_PHY_FEC_25G_RS_528_REQ |
2516 ICE_AQC_PHY_FEC_25G_RS_544_REQ |
2517 ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN))
2520 return ICE_FEC_NONE;
2523 static enum ice_status
2524 ice_cfg_phy_fc(struct ice_port_info *pi, struct ice_aqc_set_phy_cfg_data *cfg,
2525 enum ice_fc_mode req_mode)
2527 struct ice_aqc_get_phy_caps_data *pcaps = NULL;
2528 struct ice_phy_cache_mode_data cache_data;
2529 enum ice_status status = ICE_SUCCESS;
2530 u8 pause_mask = 0x0;
2533 return ICE_ERR_BAD_PTR;
2535 pcaps = (struct ice_aqc_get_phy_caps_data *)
2536 ice_malloc(pi->hw, sizeof(*pcaps));
2538 return ICE_ERR_NO_MEMORY;
2540 /* Cache user FC request */
2541 cache_data.data.curr_user_fc_req = req_mode;
2542 ice_cache_phy_user_req(pi, cache_data, ICE_FC_MODE);
2546 /* Query the value of FC that both the NIC and attached media
2549 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_TOPO_CAP,
2554 pause_mask |= pcaps->caps & ICE_AQC_PHY_EN_TX_LINK_PAUSE;
2555 pause_mask |= pcaps->caps & ICE_AQC_PHY_EN_RX_LINK_PAUSE;
2558 pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE;
2559 pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE;
2561 case ICE_FC_RX_PAUSE:
2562 pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE;
2564 case ICE_FC_TX_PAUSE:
2565 pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE;
2571 /* clear the old pause settings */
2572 cfg->caps &= ~(ICE_AQC_PHY_EN_TX_LINK_PAUSE |
2573 ICE_AQC_PHY_EN_RX_LINK_PAUSE);
2575 /* set the new capabilities */
2576 cfg->caps |= pause_mask;
2579 ice_free(pi->hw, pcaps);
2585 * @pi: port information structure
2586 * @aq_failures: pointer to status code, specific to ice_set_fc routine
2587 * @ena_auto_link_update: enable automatic link update
2589 * Set the requested flow control mode.
2592 ice_set_fc(struct ice_port_info *pi, u8 *aq_failures, bool ena_auto_link_update)
2594 struct ice_aqc_set_phy_cfg_data cfg = { 0 };
2595 struct ice_aqc_get_phy_caps_data *pcaps;
2596 enum ice_status status;
2599 if (!pi || !aq_failures)
2600 return ICE_ERR_BAD_PTR;
2604 pcaps = (struct ice_aqc_get_phy_caps_data *)
2605 ice_malloc(hw, sizeof(*pcaps));
2607 return ICE_ERR_NO_MEMORY;
2609 /* Get the current PHY config */
2610 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_SW_CFG, pcaps,
2613 *aq_failures = ICE_SET_FC_AQ_FAIL_GET;
2617 ice_copy_phy_caps_to_cfg(pi, pcaps, &cfg);
2619 /* Configure the set PHY data */
2620 status = ice_cfg_phy_fc(pi, &cfg, pi->fc.req_mode);
2622 if (status != ICE_ERR_BAD_PTR)
2623 *aq_failures = ICE_SET_FC_AQ_FAIL_GET;
2628 /* If the capabilities have changed, then set the new config */
2629 if (cfg.caps != pcaps->caps) {
2630 int retry_count, retry_max = 10;
2632 /* Auto restart link so settings take effect */
2633 if (ena_auto_link_update)
2634 cfg.caps |= ICE_AQ_PHY_ENA_AUTO_LINK_UPDT;
2636 status = ice_aq_set_phy_cfg(hw, pi, &cfg, NULL);
2638 *aq_failures = ICE_SET_FC_AQ_FAIL_SET;
2642 /* Update the link info
2643 * It sometimes takes a really long time for link to
2644 * come back from the atomic reset. Thus, we wait a
2647 for (retry_count = 0; retry_count < retry_max; retry_count++) {
2648 status = ice_update_link_info(pi);
2650 if (status == ICE_SUCCESS)
2653 ice_msec_delay(100, true);
2657 *aq_failures = ICE_SET_FC_AQ_FAIL_UPDATE;
2661 ice_free(hw, pcaps);
2666 * ice_phy_caps_equals_cfg
2667 * @phy_caps: PHY capabilities
2668 * @phy_cfg: PHY configuration
2670 * Helper function to determine if PHY capabilities matches PHY
2674 ice_phy_caps_equals_cfg(struct ice_aqc_get_phy_caps_data *phy_caps,
2675 struct ice_aqc_set_phy_cfg_data *phy_cfg)
2677 u8 caps_mask, cfg_mask;
2679 if (!phy_caps || !phy_cfg)
2682 /* These bits are not common between capabilities and configuration.
2683 * Do not use them to determine equality.
2685 caps_mask = ICE_AQC_PHY_CAPS_MASK & ~(ICE_AQC_PHY_AN_MODE |
2686 ICE_AQC_PHY_EN_MOD_QUAL);
2687 cfg_mask = ICE_AQ_PHY_ENA_VALID_MASK & ~ICE_AQ_PHY_ENA_AUTO_LINK_UPDT;
2689 if (phy_caps->phy_type_low != phy_cfg->phy_type_low ||
2690 phy_caps->phy_type_high != phy_cfg->phy_type_high ||
2691 ((phy_caps->caps & caps_mask) != (phy_cfg->caps & cfg_mask)) ||
2692 phy_caps->low_power_ctrl_an != phy_cfg->low_power_ctrl_an ||
2693 phy_caps->eee_cap != phy_cfg->eee_cap ||
2694 phy_caps->eeer_value != phy_cfg->eeer_value ||
2695 phy_caps->link_fec_options != phy_cfg->link_fec_opt)
2702 * ice_copy_phy_caps_to_cfg - Copy PHY ability data to configuration data
2703 * @pi: port information structure
2704 * @caps: PHY ability structure to copy date from
2705 * @cfg: PHY configuration structure to copy data to
2707 * Helper function to copy AQC PHY get ability data to PHY set configuration
2711 ice_copy_phy_caps_to_cfg(struct ice_port_info *pi,
2712 struct ice_aqc_get_phy_caps_data *caps,
2713 struct ice_aqc_set_phy_cfg_data *cfg)
2715 if (!pi || !caps || !cfg)
2718 ice_memset(cfg, 0, sizeof(*cfg), ICE_NONDMA_MEM);
2719 cfg->phy_type_low = caps->phy_type_low;
2720 cfg->phy_type_high = caps->phy_type_high;
2721 cfg->caps = caps->caps;
2722 cfg->low_power_ctrl_an = caps->low_power_ctrl_an;
2723 cfg->eee_cap = caps->eee_cap;
2724 cfg->eeer_value = caps->eeer_value;
2725 cfg->link_fec_opt = caps->link_fec_options;
2726 cfg->module_compliance_enforcement =
2727 caps->module_compliance_enforcement;
2729 if (ice_fw_supports_link_override(pi->hw)) {
2730 struct ice_link_default_override_tlv tlv;
2732 if (ice_get_link_default_override(&tlv, pi))
2735 if (tlv.options & ICE_LINK_OVERRIDE_STRICT_MODE)
2736 cfg->module_compliance_enforcement |=
2737 ICE_LINK_OVERRIDE_STRICT_MODE;
2742 * ice_cfg_phy_fec - Configure PHY FEC data based on FEC mode
2743 * @pi: port information structure
2744 * @cfg: PHY configuration data to set FEC mode
2745 * @fec: FEC mode to configure
2748 ice_cfg_phy_fec(struct ice_port_info *pi, struct ice_aqc_set_phy_cfg_data *cfg,
2749 enum ice_fec_mode fec)
2751 struct ice_aqc_get_phy_caps_data *pcaps;
2752 enum ice_status status = ICE_SUCCESS;
2756 return ICE_ERR_BAD_PTR;
2760 pcaps = (struct ice_aqc_get_phy_caps_data *)
2761 ice_malloc(hw, sizeof(*pcaps));
2763 return ICE_ERR_NO_MEMORY;
2765 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_TOPO_CAP, pcaps,
2770 cfg->caps |= (pcaps->caps & ICE_AQC_PHY_EN_AUTO_FEC);
2771 cfg->link_fec_opt = pcaps->link_fec_options;
2775 /* Clear RS bits, and AND BASE-R ability
2776 * bits and OR request bits.
2778 cfg->link_fec_opt &= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN |
2779 ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN;
2780 cfg->link_fec_opt |= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ |
2781 ICE_AQC_PHY_FEC_25G_KR_REQ;
2784 /* Clear BASE-R bits, and AND RS ability
2785 * bits and OR request bits.
2787 cfg->link_fec_opt &= ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN;
2788 cfg->link_fec_opt |= ICE_AQC_PHY_FEC_25G_RS_528_REQ |
2789 ICE_AQC_PHY_FEC_25G_RS_544_REQ;
2792 /* Clear all FEC option bits. */
2793 cfg->link_fec_opt &= ~ICE_AQC_PHY_FEC_MASK;
2796 /* AND auto FEC bit, and all caps bits. */
2797 cfg->caps &= ICE_AQC_PHY_CAPS_MASK;
2798 cfg->link_fec_opt |= pcaps->link_fec_options;
2801 status = ICE_ERR_PARAM;
2805 if (fec == ICE_FEC_AUTO && ice_fw_supports_link_override(pi->hw)) {
2806 struct ice_link_default_override_tlv tlv;
2808 if (ice_get_link_default_override(&tlv, pi))
2811 if (!(tlv.options & ICE_LINK_OVERRIDE_STRICT_MODE) &&
2812 (tlv.options & ICE_LINK_OVERRIDE_EN))
2813 cfg->link_fec_opt = tlv.fec_options;
2817 ice_free(hw, pcaps);
2823 * ice_get_link_status - get status of the HW network link
2824 * @pi: port information structure
2825 * @link_up: pointer to bool (true/false = linkup/linkdown)
2827 * Variable link_up is true if link is up, false if link is down.
2828 * The variable link_up is invalid if status is non zero. As a
2829 * result of this call, link status reporting becomes enabled
2831 enum ice_status ice_get_link_status(struct ice_port_info *pi, bool *link_up)
2833 struct ice_phy_info *phy_info;
2834 enum ice_status status = ICE_SUCCESS;
2836 if (!pi || !link_up)
2837 return ICE_ERR_PARAM;
2839 phy_info = &pi->phy;
2841 if (phy_info->get_link_info) {
2842 status = ice_update_link_info(pi);
2845 ice_debug(pi->hw, ICE_DBG_LINK,
2846 "get link status error, status = %d\n",
2850 *link_up = phy_info->link_info.link_info & ICE_AQ_LINK_UP;
2856 * ice_aq_set_link_restart_an
2857 * @pi: pointer to the port information structure
2858 * @ena_link: if true: enable link, if false: disable link
2859 * @cd: pointer to command details structure or NULL
2861 * Sets up the link and restarts the Auto-Negotiation over the link.
2864 ice_aq_set_link_restart_an(struct ice_port_info *pi, bool ena_link,
2865 struct ice_sq_cd *cd)
2867 struct ice_aqc_restart_an *cmd;
2868 struct ice_aq_desc desc;
2870 cmd = &desc.params.restart_an;
2872 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_restart_an);
2874 cmd->cmd_flags = ICE_AQC_RESTART_AN_LINK_RESTART;
2875 cmd->lport_num = pi->lport;
2877 cmd->cmd_flags |= ICE_AQC_RESTART_AN_LINK_ENABLE;
2879 cmd->cmd_flags &= ~ICE_AQC_RESTART_AN_LINK_ENABLE;
2881 return ice_aq_send_cmd(pi->hw, &desc, NULL, 0, cd);
2885 * ice_aq_set_event_mask
2886 * @hw: pointer to the HW struct
2887 * @port_num: port number of the physical function
2888 * @mask: event mask to be set
2889 * @cd: pointer to command details structure or NULL
2891 * Set event mask (0x0613)
2894 ice_aq_set_event_mask(struct ice_hw *hw, u8 port_num, u16 mask,
2895 struct ice_sq_cd *cd)
2897 struct ice_aqc_set_event_mask *cmd;
2898 struct ice_aq_desc desc;
2900 cmd = &desc.params.set_event_mask;
2902 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_event_mask);
2904 cmd->lport_num = port_num;
2906 cmd->event_mask = CPU_TO_LE16(mask);
2907 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
2911 * ice_aq_set_mac_loopback
2912 * @hw: pointer to the HW struct
2913 * @ena_lpbk: Enable or Disable loopback
2914 * @cd: pointer to command details structure or NULL
2916 * Enable/disable loopback on a given port
2919 ice_aq_set_mac_loopback(struct ice_hw *hw, bool ena_lpbk, struct ice_sq_cd *cd)
2921 struct ice_aqc_set_mac_lb *cmd;
2922 struct ice_aq_desc desc;
2924 cmd = &desc.params.set_mac_lb;
2926 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_mac_lb);
2928 cmd->lb_mode = ICE_AQ_MAC_LB_EN;
2930 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
2934 * ice_aq_set_port_id_led
2935 * @pi: pointer to the port information
2936 * @is_orig_mode: is this LED set to original mode (by the net-list)
2937 * @cd: pointer to command details structure or NULL
2939 * Set LED value for the given port (0x06e9)
2942 ice_aq_set_port_id_led(struct ice_port_info *pi, bool is_orig_mode,
2943 struct ice_sq_cd *cd)
2945 struct ice_aqc_set_port_id_led *cmd;
2946 struct ice_hw *hw = pi->hw;
2947 struct ice_aq_desc desc;
2949 cmd = &desc.params.set_port_id_led;
2951 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_port_id_led);
2954 cmd->ident_mode = ICE_AQC_PORT_IDENT_LED_ORIG;
2956 cmd->ident_mode = ICE_AQC_PORT_IDENT_LED_BLINK;
2958 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
2963 * @hw: pointer to the HW struct
2964 * @lport: bits [7:0] = logical port, bit [8] = logical port valid
2965 * @bus_addr: I2C bus address of the eeprom (typically 0xA0, 0=topo default)
2966 * @mem_addr: I2C offset. lower 8 bits for address, 8 upper bits zero padding.
2968 * @set_page: set or ignore the page
2969 * @data: pointer to data buffer to be read/written to the I2C device.
2970 * @length: 1-16 for read, 1 for write.
2971 * @write: 0 read, 1 for write.
2972 * @cd: pointer to command details structure or NULL
2974 * Read/Write SFF EEPROM (0x06EE)
2977 ice_aq_sff_eeprom(struct ice_hw *hw, u16 lport, u8 bus_addr,
2978 u16 mem_addr, u8 page, u8 set_page, u8 *data, u8 length,
2979 bool write, struct ice_sq_cd *cd)
2981 struct ice_aqc_sff_eeprom *cmd;
2982 struct ice_aq_desc desc;
2983 enum ice_status status;
2985 if (!data || (mem_addr & 0xff00))
2986 return ICE_ERR_PARAM;
2988 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_sff_eeprom);
2989 cmd = &desc.params.read_write_sff_param;
2990 desc.flags = CPU_TO_LE16(ICE_AQ_FLAG_RD | ICE_AQ_FLAG_BUF);
2991 cmd->lport_num = (u8)(lport & 0xff);
2992 cmd->lport_num_valid = (u8)((lport >> 8) & 0x01);
2993 cmd->i2c_bus_addr = CPU_TO_LE16(((bus_addr >> 1) &
2994 ICE_AQC_SFF_I2CBUS_7BIT_M) |
2996 ICE_AQC_SFF_SET_EEPROM_PAGE_S) &
2997 ICE_AQC_SFF_SET_EEPROM_PAGE_M));
2998 cmd->i2c_mem_addr = CPU_TO_LE16(mem_addr & 0xff);
2999 cmd->eeprom_page = CPU_TO_LE16((u16)page << ICE_AQC_SFF_EEPROM_PAGE_S);
3001 cmd->i2c_bus_addr |= CPU_TO_LE16(ICE_AQC_SFF_IS_WRITE);
3003 status = ice_aq_send_cmd(hw, &desc, data, length, cd);
3008 * __ice_aq_get_set_rss_lut
3009 * @hw: pointer to the hardware structure
3010 * @vsi_id: VSI FW index
3011 * @lut_type: LUT table type
3012 * @lut: pointer to the LUT buffer provided by the caller
3013 * @lut_size: size of the LUT buffer
3014 * @glob_lut_idx: global LUT index
3015 * @set: set true to set the table, false to get the table
3017 * Internal function to get (0x0B05) or set (0x0B03) RSS look up table
3019 static enum ice_status
3020 __ice_aq_get_set_rss_lut(struct ice_hw *hw, u16 vsi_id, u8 lut_type, u8 *lut,
3021 u16 lut_size, u8 glob_lut_idx, bool set)
3023 struct ice_aqc_get_set_rss_lut *cmd_resp;
3024 struct ice_aq_desc desc;
3025 enum ice_status status;
3028 cmd_resp = &desc.params.get_set_rss_lut;
3031 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_rss_lut);
3032 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
3034 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_rss_lut);
3037 cmd_resp->vsi_id = CPU_TO_LE16(((vsi_id <<
3038 ICE_AQC_GSET_RSS_LUT_VSI_ID_S) &
3039 ICE_AQC_GSET_RSS_LUT_VSI_ID_M) |
3040 ICE_AQC_GSET_RSS_LUT_VSI_VALID);
3043 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_VSI:
3044 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF:
3045 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL:
3046 flags |= ((lut_type << ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S) &
3047 ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_M);
3050 status = ICE_ERR_PARAM;
3051 goto ice_aq_get_set_rss_lut_exit;
3054 if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL) {
3055 flags |= ((glob_lut_idx << ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S) &
3056 ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_M);
3059 goto ice_aq_get_set_rss_lut_send;
3060 } else if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF) {
3062 goto ice_aq_get_set_rss_lut_send;
3064 goto ice_aq_get_set_rss_lut_send;
3067 /* LUT size is only valid for Global and PF table types */
3069 case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128:
3070 flags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128_FLAG <<
3071 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) &
3072 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M;
3074 case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512:
3075 flags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512_FLAG <<
3076 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) &
3077 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M;
3079 case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K:
3080 if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF) {
3081 flags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K_FLAG <<
3082 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) &
3083 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M;
3088 status = ICE_ERR_PARAM;
3089 goto ice_aq_get_set_rss_lut_exit;
3092 ice_aq_get_set_rss_lut_send:
3093 cmd_resp->flags = CPU_TO_LE16(flags);
3094 status = ice_aq_send_cmd(hw, &desc, lut, lut_size, NULL);
3096 ice_aq_get_set_rss_lut_exit:
3101 * ice_aq_get_rss_lut
3102 * @hw: pointer to the hardware structure
3103 * @vsi_handle: software VSI handle
3104 * @lut_type: LUT table type
3105 * @lut: pointer to the LUT buffer provided by the caller
3106 * @lut_size: size of the LUT buffer
3108 * get the RSS lookup table, PF or VSI type
3111 ice_aq_get_rss_lut(struct ice_hw *hw, u16 vsi_handle, u8 lut_type,
3112 u8 *lut, u16 lut_size)
3114 if (!ice_is_vsi_valid(hw, vsi_handle) || !lut)
3115 return ICE_ERR_PARAM;
3117 return __ice_aq_get_set_rss_lut(hw, ice_get_hw_vsi_num(hw, vsi_handle),
3118 lut_type, lut, lut_size, 0, false);
3122 * ice_aq_set_rss_lut
3123 * @hw: pointer to the hardware structure
3124 * @vsi_handle: software VSI handle
3125 * @lut_type: LUT table type
3126 * @lut: pointer to the LUT buffer provided by the caller
3127 * @lut_size: size of the LUT buffer
3129 * set the RSS lookup table, PF or VSI type
3132 ice_aq_set_rss_lut(struct ice_hw *hw, u16 vsi_handle, u8 lut_type,
3133 u8 *lut, u16 lut_size)
3135 if (!ice_is_vsi_valid(hw, vsi_handle) || !lut)
3136 return ICE_ERR_PARAM;
3138 return __ice_aq_get_set_rss_lut(hw, ice_get_hw_vsi_num(hw, vsi_handle),
3139 lut_type, lut, lut_size, 0, true);
3143 * __ice_aq_get_set_rss_key
3144 * @hw: pointer to the HW struct
3145 * @vsi_id: VSI FW index
3146 * @key: pointer to key info struct
3147 * @set: set true to set the key, false to get the key
3149 * get (0x0B04) or set (0x0B02) the RSS key per VSI
3152 ice_status __ice_aq_get_set_rss_key(struct ice_hw *hw, u16 vsi_id,
3153 struct ice_aqc_get_set_rss_keys *key,
3156 struct ice_aqc_get_set_rss_key *cmd_resp;
3157 u16 key_size = sizeof(*key);
3158 struct ice_aq_desc desc;
3160 cmd_resp = &desc.params.get_set_rss_key;
3163 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_rss_key);
3164 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
3166 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_rss_key);
3169 cmd_resp->vsi_id = CPU_TO_LE16(((vsi_id <<
3170 ICE_AQC_GSET_RSS_KEY_VSI_ID_S) &
3171 ICE_AQC_GSET_RSS_KEY_VSI_ID_M) |
3172 ICE_AQC_GSET_RSS_KEY_VSI_VALID);
3174 return ice_aq_send_cmd(hw, &desc, key, key_size, NULL);
3178 * ice_aq_get_rss_key
3179 * @hw: pointer to the HW struct
3180 * @vsi_handle: software VSI handle
3181 * @key: pointer to key info struct
3183 * get the RSS key per VSI
3186 ice_aq_get_rss_key(struct ice_hw *hw, u16 vsi_handle,
3187 struct ice_aqc_get_set_rss_keys *key)
3189 if (!ice_is_vsi_valid(hw, vsi_handle) || !key)
3190 return ICE_ERR_PARAM;
3192 return __ice_aq_get_set_rss_key(hw, ice_get_hw_vsi_num(hw, vsi_handle),
3197 * ice_aq_set_rss_key
3198 * @hw: pointer to the HW struct
3199 * @vsi_handle: software VSI handle
3200 * @keys: pointer to key info struct
3202 * set the RSS key per VSI
3205 ice_aq_set_rss_key(struct ice_hw *hw, u16 vsi_handle,
3206 struct ice_aqc_get_set_rss_keys *keys)
3208 if (!ice_is_vsi_valid(hw, vsi_handle) || !keys)
3209 return ICE_ERR_PARAM;
3211 return __ice_aq_get_set_rss_key(hw, ice_get_hw_vsi_num(hw, vsi_handle),
3216 * ice_aq_add_lan_txq
3217 * @hw: pointer to the hardware structure
3218 * @num_qgrps: Number of added queue groups
3219 * @qg_list: list of queue groups to be added
3220 * @buf_size: size of buffer for indirect command
3221 * @cd: pointer to command details structure or NULL
3223 * Add Tx LAN queue (0x0C30)
3226 * Prior to calling add Tx LAN queue:
3227 * Initialize the following as part of the Tx queue context:
3228 * Completion queue ID if the queue uses Completion queue, Quanta profile,
3229 * Cache profile and Packet shaper profile.
3231 * After add Tx LAN queue AQ command is completed:
3232 * Interrupts should be associated with specific queues,
3233 * Association of Tx queue to Doorbell queue is not part of Add LAN Tx queue
3237 ice_aq_add_lan_txq(struct ice_hw *hw, u8 num_qgrps,
3238 struct ice_aqc_add_tx_qgrp *qg_list, u16 buf_size,
3239 struct ice_sq_cd *cd)
3241 u16 i, sum_header_size, sum_q_size = 0;
3242 struct ice_aqc_add_tx_qgrp *list;
3243 struct ice_aqc_add_txqs *cmd;
3244 struct ice_aq_desc desc;
3246 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
3248 cmd = &desc.params.add_txqs;
3250 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_add_txqs);
3253 return ICE_ERR_PARAM;
3255 if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS)
3256 return ICE_ERR_PARAM;
3258 sum_header_size = num_qgrps *
3259 (sizeof(*qg_list) - sizeof(*qg_list->txqs));
3262 for (i = 0; i < num_qgrps; i++) {
3263 struct ice_aqc_add_txqs_perq *q = list->txqs;
3265 sum_q_size += list->num_txqs * sizeof(*q);
3266 list = (struct ice_aqc_add_tx_qgrp *)(q + list->num_txqs);
3269 if (buf_size != (sum_header_size + sum_q_size))
3270 return ICE_ERR_PARAM;
3272 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
3274 cmd->num_qgrps = num_qgrps;
3276 return ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd);
3280 * ice_aq_dis_lan_txq
3281 * @hw: pointer to the hardware structure
3282 * @num_qgrps: number of groups in the list
3283 * @qg_list: the list of groups to disable
3284 * @buf_size: the total size of the qg_list buffer in bytes
3285 * @rst_src: if called due to reset, specifies the reset source
3286 * @vmvf_num: the relative VM or VF number that is undergoing the reset
3287 * @cd: pointer to command details structure or NULL
3289 * Disable LAN Tx queue (0x0C31)
3291 static enum ice_status
3292 ice_aq_dis_lan_txq(struct ice_hw *hw, u8 num_qgrps,
3293 struct ice_aqc_dis_txq_item *qg_list, u16 buf_size,
3294 enum ice_disq_rst_src rst_src, u16 vmvf_num,
3295 struct ice_sq_cd *cd)
3297 struct ice_aqc_dis_txqs *cmd;
3298 struct ice_aq_desc desc;
3299 enum ice_status status;
3302 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
3303 cmd = &desc.params.dis_txqs;
3304 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_dis_txqs);
3306 /* qg_list can be NULL only in VM/VF reset flow */
3307 if (!qg_list && !rst_src)
3308 return ICE_ERR_PARAM;
3310 if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS)
3311 return ICE_ERR_PARAM;
3313 cmd->num_entries = num_qgrps;
3315 cmd->vmvf_and_timeout = CPU_TO_LE16((5 << ICE_AQC_Q_DIS_TIMEOUT_S) &
3316 ICE_AQC_Q_DIS_TIMEOUT_M);
3320 cmd->cmd_type = ICE_AQC_Q_DIS_CMD_VM_RESET;
3321 cmd->vmvf_and_timeout |=
3322 CPU_TO_LE16(vmvf_num & ICE_AQC_Q_DIS_VMVF_NUM_M);
3329 /* flush pipe on time out */
3330 cmd->cmd_type |= ICE_AQC_Q_DIS_CMD_FLUSH_PIPE;
3331 /* If no queue group info, we are in a reset flow. Issue the AQ */
3335 /* set RD bit to indicate that command buffer is provided by the driver
3336 * and it needs to be read by the firmware
3338 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
3340 for (i = 0; i < num_qgrps; ++i) {
3341 /* Calculate the size taken up by the queue IDs in this group */
3342 sz += qg_list[i].num_qs * sizeof(qg_list[i].q_id);
3344 /* Add the size of the group header */
3345 sz += sizeof(qg_list[i]) - sizeof(qg_list[i].q_id);
3347 /* If the num of queues is even, add 2 bytes of padding */
3348 if ((qg_list[i].num_qs % 2) == 0)
3353 return ICE_ERR_PARAM;
3356 status = ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd);
3359 ice_debug(hw, ICE_DBG_SCHED, "VM%d disable failed %d\n",
3360 vmvf_num, hw->adminq.sq_last_status);
3362 ice_debug(hw, ICE_DBG_SCHED, "disable queue %d failed %d\n",
3363 LE16_TO_CPU(qg_list[0].q_id[0]),
3364 hw->adminq.sq_last_status);
3370 * ice_aq_move_recfg_lan_txq
3371 * @hw: pointer to the hardware structure
3372 * @num_qs: number of queues to move/reconfigure
3373 * @is_move: true if this operation involves node movement
3374 * @is_tc_change: true if this operation involves a TC change
3375 * @subseq_call: true if this operation is a subsequent call
3376 * @flush_pipe: on timeout, true to flush pipe, false to return EAGAIN
3377 * @timeout: timeout in units of 100 usec (valid values 0-50)
3378 * @blocked_cgds: out param, bitmap of CGDs that timed out if returning EAGAIN
3379 * @buf: struct containing src/dest TEID and per-queue info
3380 * @buf_size: size of buffer for indirect command
3381 * @txqs_moved: out param, number of queues successfully moved
3382 * @cd: pointer to command details structure or NULL
3384 * Move / Reconfigure Tx LAN queues (0x0C32)
3387 ice_aq_move_recfg_lan_txq(struct ice_hw *hw, u8 num_qs, bool is_move,
3388 bool is_tc_change, bool subseq_call, bool flush_pipe,
3389 u8 timeout, u32 *blocked_cgds,
3390 struct ice_aqc_move_txqs_data *buf, u16 buf_size,
3391 u8 *txqs_moved, struct ice_sq_cd *cd)
3393 struct ice_aqc_move_txqs *cmd;
3394 struct ice_aq_desc desc;
3395 enum ice_status status;
3397 cmd = &desc.params.move_txqs;
3398 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_move_recfg_txqs);
3400 #define ICE_LAN_TXQ_MOVE_TIMEOUT_MAX 50
3401 if (timeout > ICE_LAN_TXQ_MOVE_TIMEOUT_MAX)
3402 return ICE_ERR_PARAM;
3404 if (is_tc_change && !flush_pipe && !blocked_cgds)
3405 return ICE_ERR_PARAM;
3407 if (!is_move && !is_tc_change)
3408 return ICE_ERR_PARAM;
3410 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
3413 cmd->cmd_type |= ICE_AQC_Q_CMD_TYPE_MOVE;
3416 cmd->cmd_type |= ICE_AQC_Q_CMD_TYPE_TC_CHANGE;
3419 cmd->cmd_type |= ICE_AQC_Q_CMD_SUBSEQ_CALL;
3422 cmd->cmd_type |= ICE_AQC_Q_CMD_FLUSH_PIPE;
3424 cmd->num_qs = num_qs;
3425 cmd->timeout = ((timeout << ICE_AQC_Q_CMD_TIMEOUT_S) &
3426 ICE_AQC_Q_CMD_TIMEOUT_M);
3428 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);
3430 if (!status && txqs_moved)
3431 *txqs_moved = cmd->num_qs;
3433 if (hw->adminq.sq_last_status == ICE_AQ_RC_EAGAIN &&
3434 is_tc_change && !flush_pipe)
3435 *blocked_cgds = LE32_TO_CPU(cmd->blocked_cgds);
3440 /* End of FW Admin Queue command wrappers */
3443 * ice_write_byte - write a byte to a packed context structure
3444 * @src_ctx: the context structure to read from
3445 * @dest_ctx: the context to be written to
3446 * @ce_info: a description of the struct to be filled
3449 ice_write_byte(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)
3451 u8 src_byte, dest_byte, mask;
3455 /* copy from the next struct field */
3456 from = src_ctx + ce_info->offset;
3458 /* prepare the bits and mask */
3459 shift_width = ce_info->lsb % 8;
3460 mask = (u8)(BIT(ce_info->width) - 1);
3465 /* shift to correct alignment */
3466 mask <<= shift_width;
3467 src_byte <<= shift_width;
3469 /* get the current bits from the target bit string */
3470 dest = dest_ctx + (ce_info->lsb / 8);
3472 ice_memcpy(&dest_byte, dest, sizeof(dest_byte), ICE_DMA_TO_NONDMA);
3474 dest_byte &= ~mask; /* get the bits not changing */
3475 dest_byte |= src_byte; /* add in the new bits */
3477 /* put it all back */
3478 ice_memcpy(dest, &dest_byte, sizeof(dest_byte), ICE_NONDMA_TO_DMA);
3482 * ice_write_word - write a word to a packed context structure
3483 * @src_ctx: the context structure to read from
3484 * @dest_ctx: the context to be written to
3485 * @ce_info: a description of the struct to be filled
3488 ice_write_word(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)
3495 /* copy from the next struct field */
3496 from = src_ctx + ce_info->offset;
3498 /* prepare the bits and mask */
3499 shift_width = ce_info->lsb % 8;
3500 mask = BIT(ce_info->width) - 1;
3502 /* don't swizzle the bits until after the mask because the mask bits
3503 * will be in a different bit position on big endian machines
3505 src_word = *(u16 *)from;
3508 /* shift to correct alignment */
3509 mask <<= shift_width;
3510 src_word <<= shift_width;
3512 /* get the current bits from the target bit string */
3513 dest = dest_ctx + (ce_info->lsb / 8);
3515 ice_memcpy(&dest_word, dest, sizeof(dest_word), ICE_DMA_TO_NONDMA);
3517 dest_word &= ~(CPU_TO_LE16(mask)); /* get the bits not changing */
3518 dest_word |= CPU_TO_LE16(src_word); /* add in the new bits */
3520 /* put it all back */
3521 ice_memcpy(dest, &dest_word, sizeof(dest_word), ICE_NONDMA_TO_DMA);
3525 * ice_write_dword - write a dword to a packed context structure
3526 * @src_ctx: the context structure to read from
3527 * @dest_ctx: the context to be written to
3528 * @ce_info: a description of the struct to be filled
3531 ice_write_dword(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)
3533 u32 src_dword, mask;
3538 /* copy from the next struct field */
3539 from = src_ctx + ce_info->offset;
3541 /* prepare the bits and mask */
3542 shift_width = ce_info->lsb % 8;
3544 /* if the field width is exactly 32 on an x86 machine, then the shift
3545 * operation will not work because the SHL instructions count is masked
3546 * to 5 bits so the shift will do nothing
3548 if (ce_info->width < 32)
3549 mask = BIT(ce_info->width) - 1;
3553 /* don't swizzle the bits until after the mask because the mask bits
3554 * will be in a different bit position on big endian machines
3556 src_dword = *(u32 *)from;
3559 /* shift to correct alignment */
3560 mask <<= shift_width;
3561 src_dword <<= shift_width;
3563 /* get the current bits from the target bit string */
3564 dest = dest_ctx + (ce_info->lsb / 8);
3566 ice_memcpy(&dest_dword, dest, sizeof(dest_dword), ICE_DMA_TO_NONDMA);
3568 dest_dword &= ~(CPU_TO_LE32(mask)); /* get the bits not changing */
3569 dest_dword |= CPU_TO_LE32(src_dword); /* add in the new bits */
3571 /* put it all back */
3572 ice_memcpy(dest, &dest_dword, sizeof(dest_dword), ICE_NONDMA_TO_DMA);
3576 * ice_write_qword - write a qword to a packed context structure
3577 * @src_ctx: the context structure to read from
3578 * @dest_ctx: the context to be written to
3579 * @ce_info: a description of the struct to be filled
3582 ice_write_qword(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)
3584 u64 src_qword, mask;
3589 /* copy from the next struct field */
3590 from = src_ctx + ce_info->offset;
3592 /* prepare the bits and mask */
3593 shift_width = ce_info->lsb % 8;
3595 /* if the field width is exactly 64 on an x86 machine, then the shift
3596 * operation will not work because the SHL instructions count is masked
3597 * to 6 bits so the shift will do nothing
3599 if (ce_info->width < 64)
3600 mask = BIT_ULL(ce_info->width) - 1;
3604 /* don't swizzle the bits until after the mask because the mask bits
3605 * will be in a different bit position on big endian machines
3607 src_qword = *(u64 *)from;
3610 /* shift to correct alignment */
3611 mask <<= shift_width;
3612 src_qword <<= shift_width;
3614 /* get the current bits from the target bit string */
3615 dest = dest_ctx + (ce_info->lsb / 8);
3617 ice_memcpy(&dest_qword, dest, sizeof(dest_qword), ICE_DMA_TO_NONDMA);
3619 dest_qword &= ~(CPU_TO_LE64(mask)); /* get the bits not changing */
3620 dest_qword |= CPU_TO_LE64(src_qword); /* add in the new bits */
3622 /* put it all back */
3623 ice_memcpy(dest, &dest_qword, sizeof(dest_qword), ICE_NONDMA_TO_DMA);
3627 * ice_set_ctx - set context bits in packed structure
3628 * @hw: pointer to the hardware structure
3629 * @src_ctx: pointer to a generic non-packed context structure
3630 * @dest_ctx: pointer to memory for the packed structure
3631 * @ce_info: a description of the structure to be transformed
3634 ice_set_ctx(struct ice_hw *hw, u8 *src_ctx, u8 *dest_ctx,
3635 const struct ice_ctx_ele *ce_info)
3639 for (f = 0; ce_info[f].width; f++) {
3640 /* We have to deal with each element of the FW response
3641 * using the correct size so that we are correct regardless
3642 * of the endianness of the machine.
3644 if (ce_info[f].width > (ce_info[f].size_of * BITS_PER_BYTE)) {
3645 ice_debug(hw, ICE_DBG_QCTX,
3646 "Field %d width of %d bits larger than size of %d byte(s) ... skipping write\n",
3647 f, ce_info[f].width, ce_info[f].size_of);
3650 switch (ce_info[f].size_of) {
3652 ice_write_byte(src_ctx, dest_ctx, &ce_info[f]);
3655 ice_write_word(src_ctx, dest_ctx, &ce_info[f]);
3658 ice_write_dword(src_ctx, dest_ctx, &ce_info[f]);
3661 ice_write_qword(src_ctx, dest_ctx, &ce_info[f]);
3664 return ICE_ERR_INVAL_SIZE;
3672 * ice_read_byte - read context byte into struct
3673 * @src_ctx: the context structure to read from
3674 * @dest_ctx: the context to be written to
3675 * @ce_info: a description of the struct to be filled
3678 ice_read_byte(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info)
3684 /* prepare the bits and mask */
3685 shift_width = ce_info->lsb % 8;
3686 mask = (u8)(BIT(ce_info->width) - 1);
3688 /* shift to correct alignment */
3689 mask <<= shift_width;
3691 /* get the current bits from the src bit string */
3692 src = src_ctx + (ce_info->lsb / 8);
3694 ice_memcpy(&dest_byte, src, sizeof(dest_byte), ICE_DMA_TO_NONDMA);
3696 dest_byte &= ~(mask);
3698 dest_byte >>= shift_width;
3700 /* get the address from the struct field */
3701 target = dest_ctx + ce_info->offset;
3703 /* put it back in the struct */
3704 ice_memcpy(target, &dest_byte, sizeof(dest_byte), ICE_NONDMA_TO_DMA);
3708 * ice_read_word - read context word into struct
3709 * @src_ctx: the context structure to read from
3710 * @dest_ctx: the context to be written to
3711 * @ce_info: a description of the struct to be filled
3714 ice_read_word(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info)
3716 u16 dest_word, mask;
3721 /* prepare the bits and mask */
3722 shift_width = ce_info->lsb % 8;
3723 mask = BIT(ce_info->width) - 1;
3725 /* shift to correct alignment */
3726 mask <<= shift_width;
3728 /* get the current bits from the src bit string */
3729 src = src_ctx + (ce_info->lsb / 8);
3731 ice_memcpy(&src_word, src, sizeof(src_word), ICE_DMA_TO_NONDMA);
3733 /* the data in the memory is stored as little endian so mask it
3736 src_word &= ~(CPU_TO_LE16(mask));
3738 /* get the data back into host order before shifting */
3739 dest_word = LE16_TO_CPU(src_word);
3741 dest_word >>= shift_width;
3743 /* get the address from the struct field */
3744 target = dest_ctx + ce_info->offset;
3746 /* put it back in the struct */
3747 ice_memcpy(target, &dest_word, sizeof(dest_word), ICE_NONDMA_TO_DMA);
3751 * ice_read_dword - read context dword into struct
3752 * @src_ctx: the context structure to read from
3753 * @dest_ctx: the context to be written to
3754 * @ce_info: a description of the struct to be filled
3757 ice_read_dword(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info)
3759 u32 dest_dword, mask;
3764 /* prepare the bits and mask */
3765 shift_width = ce_info->lsb % 8;
3767 /* if the field width is exactly 32 on an x86 machine, then the shift
3768 * operation will not work because the SHL instructions count is masked
3769 * to 5 bits so the shift will do nothing
3771 if (ce_info->width < 32)
3772 mask = BIT(ce_info->width) - 1;
3776 /* shift to correct alignment */
3777 mask <<= shift_width;
3779 /* get the current bits from the src bit string */
3780 src = src_ctx + (ce_info->lsb / 8);
3782 ice_memcpy(&src_dword, src, sizeof(src_dword), ICE_DMA_TO_NONDMA);
3784 /* the data in the memory is stored as little endian so mask it
3787 src_dword &= ~(CPU_TO_LE32(mask));
3789 /* get the data back into host order before shifting */
3790 dest_dword = LE32_TO_CPU(src_dword);
3792 dest_dword >>= shift_width;
3794 /* get the address from the struct field */
3795 target = dest_ctx + ce_info->offset;
3797 /* put it back in the struct */
3798 ice_memcpy(target, &dest_dword, sizeof(dest_dword), ICE_NONDMA_TO_DMA);
3802 * ice_read_qword - read context qword into struct
3803 * @src_ctx: the context structure to read from
3804 * @dest_ctx: the context to be written to
3805 * @ce_info: a description of the struct to be filled
3808 ice_read_qword(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info)
3810 u64 dest_qword, mask;
3815 /* prepare the bits and mask */
3816 shift_width = ce_info->lsb % 8;
3818 /* if the field width is exactly 64 on an x86 machine, then the shift
3819 * operation will not work because the SHL instructions count is masked
3820 * to 6 bits so the shift will do nothing
3822 if (ce_info->width < 64)
3823 mask = BIT_ULL(ce_info->width) - 1;
3827 /* shift to correct alignment */
3828 mask <<= shift_width;
3830 /* get the current bits from the src bit string */
3831 src = src_ctx + (ce_info->lsb / 8);
3833 ice_memcpy(&src_qword, src, sizeof(src_qword), ICE_DMA_TO_NONDMA);
3835 /* the data in the memory is stored as little endian so mask it
3838 src_qword &= ~(CPU_TO_LE64(mask));
3840 /* get the data back into host order before shifting */
3841 dest_qword = LE64_TO_CPU(src_qword);
3843 dest_qword >>= shift_width;
3845 /* get the address from the struct field */
3846 target = dest_ctx + ce_info->offset;
3848 /* put it back in the struct */
3849 ice_memcpy(target, &dest_qword, sizeof(dest_qword), ICE_NONDMA_TO_DMA);
3853 * ice_get_ctx - extract context bits from a packed structure
3854 * @src_ctx: pointer to a generic packed context structure
3855 * @dest_ctx: pointer to a generic non-packed context structure
3856 * @ce_info: a description of the structure to be read from
3859 ice_get_ctx(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info)
3863 for (f = 0; ce_info[f].width; f++) {
3864 switch (ce_info[f].size_of) {
3866 ice_read_byte(src_ctx, dest_ctx, &ce_info[f]);
3869 ice_read_word(src_ctx, dest_ctx, &ce_info[f]);
3872 ice_read_dword(src_ctx, dest_ctx, &ce_info[f]);
3875 ice_read_qword(src_ctx, dest_ctx, &ce_info[f]);
3878 /* nothing to do, just keep going */
3887 * ice_get_lan_q_ctx - get the LAN queue context for the given VSI and TC
3888 * @hw: pointer to the HW struct
3889 * @vsi_handle: software VSI handle
3891 * @q_handle: software queue handle
3894 ice_get_lan_q_ctx(struct ice_hw *hw, u16 vsi_handle, u8 tc, u16 q_handle)
3896 struct ice_vsi_ctx *vsi;
3897 struct ice_q_ctx *q_ctx;
3899 vsi = ice_get_vsi_ctx(hw, vsi_handle);
3902 if (q_handle >= vsi->num_lan_q_entries[tc])
3904 if (!vsi->lan_q_ctx[tc])
3906 q_ctx = vsi->lan_q_ctx[tc];
3907 return &q_ctx[q_handle];
3912 * @pi: port information structure
3913 * @vsi_handle: software VSI handle
3915 * @q_handle: software queue handle
3916 * @num_qgrps: Number of added queue groups
3917 * @buf: list of queue groups to be added
3918 * @buf_size: size of buffer for indirect command
3919 * @cd: pointer to command details structure or NULL
3921 * This function adds one LAN queue
3924 ice_ena_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u16 q_handle,
3925 u8 num_qgrps, struct ice_aqc_add_tx_qgrp *buf, u16 buf_size,
3926 struct ice_sq_cd *cd)
3928 struct ice_aqc_txsched_elem_data node = { 0 };
3929 struct ice_sched_node *parent;
3930 struct ice_q_ctx *q_ctx;
3931 enum ice_status status;
3934 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY)
3937 if (num_qgrps > 1 || buf->num_txqs > 1)
3938 return ICE_ERR_MAX_LIMIT;
3942 if (!ice_is_vsi_valid(hw, vsi_handle))
3943 return ICE_ERR_PARAM;
3945 ice_acquire_lock(&pi->sched_lock);
3947 q_ctx = ice_get_lan_q_ctx(hw, vsi_handle, tc, q_handle);
3949 ice_debug(hw, ICE_DBG_SCHED, "Enaq: invalid queue handle %d\n",
3951 status = ICE_ERR_PARAM;
3955 /* find a parent node */
3956 parent = ice_sched_get_free_qparent(pi, vsi_handle, tc,
3957 ICE_SCHED_NODE_OWNER_LAN);
3959 status = ICE_ERR_PARAM;
3963 buf->parent_teid = parent->info.node_teid;
3964 node.parent_teid = parent->info.node_teid;
3965 /* Mark that the values in the "generic" section as valid. The default
3966 * value in the "generic" section is zero. This means that :
3967 * - Scheduling mode is Bytes Per Second (BPS), indicated by Bit 0.
3968 * - 0 priority among siblings, indicated by Bit 1-3.
3969 * - WFQ, indicated by Bit 4.
3970 * - 0 Adjustment value is used in PSM credit update flow, indicated by
3972 * - Bit 7 is reserved.
3973 * Without setting the generic section as valid in valid_sections, the
3974 * Admin queue command will fail with error code ICE_AQ_RC_EINVAL.
3976 buf->txqs[0].info.valid_sections = ICE_AQC_ELEM_VALID_GENERIC;
3978 /* add the LAN queue */
3979 status = ice_aq_add_lan_txq(hw, num_qgrps, buf, buf_size, cd);
3980 if (status != ICE_SUCCESS) {
3981 ice_debug(hw, ICE_DBG_SCHED, "enable queue %d failed %d\n",
3982 LE16_TO_CPU(buf->txqs[0].txq_id),
3983 hw->adminq.sq_last_status);
3987 node.node_teid = buf->txqs[0].q_teid;
3988 node.data.elem_type = ICE_AQC_ELEM_TYPE_LEAF;
3989 q_ctx->q_handle = q_handle;
3990 q_ctx->q_teid = LE32_TO_CPU(node.node_teid);
3992 /* add a leaf node into scheduler tree queue layer */
3993 status = ice_sched_add_node(pi, hw->num_tx_sched_layers - 1, &node);
3995 status = ice_sched_replay_q_bw(pi, q_ctx);
3998 ice_release_lock(&pi->sched_lock);
4004 * @pi: port information structure
4005 * @vsi_handle: software VSI handle
4007 * @num_queues: number of queues
4008 * @q_handles: pointer to software queue handle array
4009 * @q_ids: pointer to the q_id array
4010 * @q_teids: pointer to queue node teids
4011 * @rst_src: if called due to reset, specifies the reset source
4012 * @vmvf_num: the relative VM or VF number that is undergoing the reset
4013 * @cd: pointer to command details structure or NULL
4015 * This function removes queues and their corresponding nodes in SW DB
4018 ice_dis_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u8 num_queues,
4019 u16 *q_handles, u16 *q_ids, u32 *q_teids,
4020 enum ice_disq_rst_src rst_src, u16 vmvf_num,
4021 struct ice_sq_cd *cd)
4023 enum ice_status status = ICE_ERR_DOES_NOT_EXIST;
4024 struct ice_aqc_dis_txq_item qg_list;
4025 struct ice_q_ctx *q_ctx;
4028 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY)
4032 /* if queue is disabled already yet the disable queue command
4033 * has to be sent to complete the VF reset, then call
4034 * ice_aq_dis_lan_txq without any queue information
4037 return ice_aq_dis_lan_txq(pi->hw, 0, NULL, 0, rst_src,
4042 ice_acquire_lock(&pi->sched_lock);
4044 for (i = 0; i < num_queues; i++) {
4045 struct ice_sched_node *node;
4047 node = ice_sched_find_node_by_teid(pi->root, q_teids[i]);
4050 q_ctx = ice_get_lan_q_ctx(pi->hw, vsi_handle, tc, q_handles[i]);
4052 ice_debug(pi->hw, ICE_DBG_SCHED, "invalid queue handle%d\n",
4056 if (q_ctx->q_handle != q_handles[i]) {
4057 ice_debug(pi->hw, ICE_DBG_SCHED, "Err:handles %d %d\n",
4058 q_ctx->q_handle, q_handles[i]);
4061 qg_list.parent_teid = node->info.parent_teid;
4063 qg_list.q_id[0] = CPU_TO_LE16(q_ids[i]);
4064 status = ice_aq_dis_lan_txq(pi->hw, 1, &qg_list,
4065 sizeof(qg_list), rst_src, vmvf_num,
4068 if (status != ICE_SUCCESS)
4070 ice_free_sched_node(pi, node);
4071 q_ctx->q_handle = ICE_INVAL_Q_HANDLE;
4073 ice_release_lock(&pi->sched_lock);
4078 * ice_cfg_vsi_qs - configure the new/existing VSI queues
4079 * @pi: port information structure
4080 * @vsi_handle: software VSI handle
4081 * @tc_bitmap: TC bitmap
4082 * @maxqs: max queues array per TC
4083 * @owner: LAN or RDMA
4085 * This function adds/updates the VSI queues per TC.
4087 static enum ice_status
4088 ice_cfg_vsi_qs(struct ice_port_info *pi, u16 vsi_handle, u16 tc_bitmap,
4089 u16 *maxqs, u8 owner)
4091 enum ice_status status = ICE_SUCCESS;
4094 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY)
4097 if (!ice_is_vsi_valid(pi->hw, vsi_handle))
4098 return ICE_ERR_PARAM;
4100 ice_acquire_lock(&pi->sched_lock);
4102 ice_for_each_traffic_class(i) {
4103 /* configuration is possible only if TC node is present */
4104 if (!ice_sched_get_tc_node(pi, i))
4107 status = ice_sched_cfg_vsi(pi, vsi_handle, i, maxqs[i], owner,
4108 ice_is_tc_ena(tc_bitmap, i));
4113 ice_release_lock(&pi->sched_lock);
4118 * ice_cfg_vsi_lan - configure VSI LAN queues
4119 * @pi: port information structure
4120 * @vsi_handle: software VSI handle
4121 * @tc_bitmap: TC bitmap
4122 * @max_lanqs: max LAN queues array per TC
4124 * This function adds/updates the VSI LAN queues per TC.
4127 ice_cfg_vsi_lan(struct ice_port_info *pi, u16 vsi_handle, u16 tc_bitmap,
4130 return ice_cfg_vsi_qs(pi, vsi_handle, tc_bitmap, max_lanqs,
4131 ICE_SCHED_NODE_OWNER_LAN);
4135 * ice_is_main_vsi - checks whether the VSI is main VSI
4136 * @hw: pointer to the HW struct
4137 * @vsi_handle: VSI handle
4139 * Checks whether the VSI is the main VSI (the first PF VSI created on
4142 static bool ice_is_main_vsi(struct ice_hw *hw, u16 vsi_handle)
4144 return vsi_handle == ICE_MAIN_VSI_HANDLE && hw->vsi_ctx[vsi_handle];
4148 * ice_replay_pre_init - replay pre initialization
4149 * @hw: pointer to the HW struct
4150 * @sw: pointer to switch info struct for which function initializes filters
4152 * Initializes required config data for VSI, FD, ACL, and RSS before replay.
4154 static enum ice_status
4155 ice_replay_pre_init(struct ice_hw *hw, struct ice_switch_info *sw)
4159 /* Delete old entries from replay filter list head if there is any */
4160 ice_rm_sw_replay_rule_info(hw, sw);
4161 /* In start of replay, move entries into replay_rules list, it
4162 * will allow adding rules entries back to filt_rules list,
4163 * which is operational list.
4165 for (i = 0; i < ICE_MAX_NUM_RECIPES; i++)
4166 LIST_REPLACE_INIT(&sw->recp_list[i].filt_rules,
4167 &sw->recp_list[i].filt_replay_rules);
4168 ice_sched_replay_agg_vsi_preinit(hw);
4170 return ice_sched_replay_tc_node_bw(hw->port_info);
4174 * ice_replay_vsi - replay VSI configuration
4175 * @hw: pointer to the HW struct
4176 * @vsi_handle: driver VSI handle
4178 * Restore all VSI configuration after reset. It is required to call this
4179 * function with main VSI first.
4181 enum ice_status ice_replay_vsi(struct ice_hw *hw, u16 vsi_handle)
4183 struct ice_switch_info *sw = hw->switch_info;
4184 struct ice_port_info *pi = hw->port_info;
4185 enum ice_status status;
4187 if (!ice_is_vsi_valid(hw, vsi_handle))
4188 return ICE_ERR_PARAM;
4190 /* Replay pre-initialization if there is any */
4191 if (ice_is_main_vsi(hw, vsi_handle)) {
4192 status = ice_replay_pre_init(hw, sw);
4196 /* Replay per VSI all RSS configurations */
4197 status = ice_replay_rss_cfg(hw, vsi_handle);
4200 /* Replay per VSI all filters */
4201 status = ice_replay_vsi_all_fltr(hw, pi, vsi_handle);
4203 status = ice_replay_vsi_agg(hw, vsi_handle);
4208 * ice_replay_post - post replay configuration cleanup
4209 * @hw: pointer to the HW struct
4211 * Post replay cleanup.
4213 void ice_replay_post(struct ice_hw *hw)
4215 /* Delete old entries from replay filter list head */
4216 ice_rm_all_sw_replay_rule_info(hw);
4217 ice_sched_replay_agg(hw);
4221 * ice_stat_update40 - read 40 bit stat from the chip and update stat values
4222 * @hw: ptr to the hardware info
4223 * @reg: offset of 64 bit HW register to read from
4224 * @prev_stat_loaded: bool to specify if previous stats are loaded
4225 * @prev_stat: ptr to previous loaded stat value
4226 * @cur_stat: ptr to current stat value
4229 ice_stat_update40(struct ice_hw *hw, u32 reg, bool prev_stat_loaded,
4230 u64 *prev_stat, u64 *cur_stat)
4232 u64 new_data = rd64(hw, reg) & (BIT_ULL(40) - 1);
4234 /* device stats are not reset at PFR, they likely will not be zeroed
4235 * when the driver starts. Thus, save the value from the first read
4236 * without adding to the statistic value so that we report stats which
4237 * count up from zero.
4239 if (!prev_stat_loaded) {
4240 *prev_stat = new_data;
4244 /* Calculate the difference between the new and old values, and then
4245 * add it to the software stat value.
4247 if (new_data >= *prev_stat)
4248 *cur_stat += new_data - *prev_stat;
4250 /* to manage the potential roll-over */
4251 *cur_stat += (new_data + BIT_ULL(40)) - *prev_stat;
4253 /* Update the previously stored value to prepare for next read */
4254 *prev_stat = new_data;
4258 * ice_stat_update32 - read 32 bit stat from the chip and update stat values
4259 * @hw: ptr to the hardware info
4260 * @reg: offset of HW register to read from
4261 * @prev_stat_loaded: bool to specify if previous stats are loaded
4262 * @prev_stat: ptr to previous loaded stat value
4263 * @cur_stat: ptr to current stat value
4266 ice_stat_update32(struct ice_hw *hw, u32 reg, bool prev_stat_loaded,
4267 u64 *prev_stat, u64 *cur_stat)
4271 new_data = rd32(hw, reg);
4273 /* device stats are not reset at PFR, they likely will not be zeroed
4274 * when the driver starts. Thus, save the value from the first read
4275 * without adding to the statistic value so that we report stats which
4276 * count up from zero.
4278 if (!prev_stat_loaded) {
4279 *prev_stat = new_data;
4283 /* Calculate the difference between the new and old values, and then
4284 * add it to the software stat value.
4286 if (new_data >= *prev_stat)
4287 *cur_stat += new_data - *prev_stat;
4289 /* to manage the potential roll-over */
4290 *cur_stat += (new_data + BIT_ULL(32)) - *prev_stat;
4292 /* Update the previously stored value to prepare for next read */
4293 *prev_stat = new_data;
4297 * ice_stat_update_repc - read GLV_REPC stats from chip and update stat values
4298 * @hw: ptr to the hardware info
4299 * @vsi_handle: VSI handle
4300 * @prev_stat_loaded: bool to specify if the previous stat values are loaded
4301 * @cur_stats: ptr to current stats structure
4303 * The GLV_REPC statistic register actually tracks two 16bit statistics, and
4304 * thus cannot be read using the normal ice_stat_update32 function.
4306 * Read the GLV_REPC register associated with the given VSI, and update the
4307 * rx_no_desc and rx_error values in the ice_eth_stats structure.
4309 * Because the statistics in GLV_REPC stick at 0xFFFF, the register must be
4310 * cleared each time it's read.
4312 * Note that the GLV_RDPC register also counts the causes that would trigger
4313 * GLV_REPC. However, it does not give the finer grained detail about why the
4314 * packets are being dropped. The GLV_REPC values can be used to distinguish
4315 * whether Rx packets are dropped due to errors or due to no available
4319 ice_stat_update_repc(struct ice_hw *hw, u16 vsi_handle, bool prev_stat_loaded,
4320 struct ice_eth_stats *cur_stats)
4322 u16 vsi_num, no_desc, error_cnt;
4325 if (!ice_is_vsi_valid(hw, vsi_handle))
4328 vsi_num = ice_get_hw_vsi_num(hw, vsi_handle);
4330 /* If we haven't loaded stats yet, just clear the current value */
4331 if (!prev_stat_loaded) {
4332 wr32(hw, GLV_REPC(vsi_num), 0);
4336 repc = rd32(hw, GLV_REPC(vsi_num));
4337 no_desc = (repc & GLV_REPC_NO_DESC_CNT_M) >> GLV_REPC_NO_DESC_CNT_S;
4338 error_cnt = (repc & GLV_REPC_ERROR_CNT_M) >> GLV_REPC_ERROR_CNT_S;
4340 /* Clear the count by writing to the stats register */
4341 wr32(hw, GLV_REPC(vsi_num), 0);
4343 cur_stats->rx_no_desc += no_desc;
4344 cur_stats->rx_errors += error_cnt;
4348 * ice_sched_query_elem - query element information from HW
4349 * @hw: pointer to the HW struct
4350 * @node_teid: node TEID to be queried
4351 * @buf: buffer to element information
4353 * This function queries HW element information
4356 ice_sched_query_elem(struct ice_hw *hw, u32 node_teid,
4357 struct ice_aqc_get_elem *buf)
4359 u16 buf_size, num_elem_ret = 0;
4360 enum ice_status status;
4362 buf_size = sizeof(*buf);
4363 ice_memset(buf, 0, buf_size, ICE_NONDMA_MEM);
4364 buf->generic[0].node_teid = CPU_TO_LE32(node_teid);
4365 status = ice_aq_query_sched_elems(hw, 1, buf, buf_size, &num_elem_ret,
4367 if (status != ICE_SUCCESS || num_elem_ret != 1)
4368 ice_debug(hw, ICE_DBG_SCHED, "query element failed\n");
4373 * ice_get_fw_mode - returns FW mode
4374 * @hw: pointer to the HW struct
4376 enum ice_fw_modes ice_get_fw_mode(struct ice_hw *hw)
4378 #define ICE_FW_MODE_DBG_M BIT(0)
4379 #define ICE_FW_MODE_REC_M BIT(1)
4380 #define ICE_FW_MODE_ROLLBACK_M BIT(2)
4383 /* check the current FW mode */
4384 fw_mode = rd32(hw, GL_MNG_FWSM) & GL_MNG_FWSM_FW_MODES_M;
4386 if (fw_mode & ICE_FW_MODE_DBG_M)
4387 return ICE_FW_MODE_DBG;
4388 else if (fw_mode & ICE_FW_MODE_REC_M)
4389 return ICE_FW_MODE_REC;
4390 else if (fw_mode & ICE_FW_MODE_ROLLBACK_M)
4391 return ICE_FW_MODE_ROLLBACK;
4393 return ICE_FW_MODE_NORMAL;
4397 * ice_fw_supports_link_override
4398 * @hw: pointer to the hardware structure
4400 * Checks if the firmware supports link override
4402 bool ice_fw_supports_link_override(struct ice_hw *hw)
4404 /* Currently, only supported for E810 devices */
4405 if (hw->mac_type != ICE_MAC_E810)
4408 if (hw->api_maj_ver == ICE_FW_API_LINK_OVERRIDE_MAJ) {
4409 if (hw->api_min_ver > ICE_FW_API_LINK_OVERRIDE_MIN)
4411 if (hw->api_min_ver == ICE_FW_API_LINK_OVERRIDE_MIN &&
4412 hw->api_patch >= ICE_FW_API_LINK_OVERRIDE_PATCH)
4414 } else if (hw->api_maj_ver > ICE_FW_API_LINK_OVERRIDE_MAJ) {
4422 * ice_get_link_default_override
4423 * @ldo: pointer to the link default override struct
4424 * @pi: pointer to the port info struct
4426 * Gets the link default override for a port
4429 ice_get_link_default_override(struct ice_link_default_override_tlv *ldo,
4430 struct ice_port_info *pi)
4432 u16 i, tlv, tlv_len, tlv_start, buf, offset;
4433 struct ice_hw *hw = pi->hw;
4434 enum ice_status status;
4436 status = ice_get_pfa_module_tlv(hw, &tlv, &tlv_len,
4437 ICE_SR_LINK_DEFAULT_OVERRIDE_PTR);
4439 ice_debug(hw, ICE_DBG_INIT,
4440 "Failed to read link override TLV.\n");
4444 /* Each port has its own config; calculate for our port */
4445 tlv_start = tlv + pi->lport * ICE_SR_PFA_LINK_OVERRIDE_WORDS +
4446 ICE_SR_PFA_LINK_OVERRIDE_OFFSET;
4448 /* link options first */
4449 status = ice_read_sr_word(hw, tlv_start, &buf);
4451 ice_debug(hw, ICE_DBG_INIT,
4452 "Failed to read override link options.\n");
4455 ldo->options = buf & ICE_LINK_OVERRIDE_OPT_M;
4456 ldo->phy_config = (buf & ICE_LINK_OVERRIDE_PHY_CFG_M) >>
4457 ICE_LINK_OVERRIDE_PHY_CFG_S;
4459 /* link PHY config */
4460 offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_FEC_OFFSET;
4461 status = ice_read_sr_word(hw, offset, &buf);
4463 ice_debug(hw, ICE_DBG_INIT,
4464 "Failed to read override phy config.\n");
4467 ldo->fec_options = buf & ICE_LINK_OVERRIDE_FEC_OPT_M;
4470 offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_PHY_OFFSET;
4471 for (i = 0; i < ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS; i++) {
4472 status = ice_read_sr_word(hw, (offset + i), &buf);
4474 ice_debug(hw, ICE_DBG_INIT,
4475 "Failed to read override link options.\n");
4478 /* shift 16 bits at a time to fill 64 bits */
4479 ldo->phy_type_low |= ((u64)buf << (i * 16));
4482 /* PHY types high */
4483 offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_PHY_OFFSET +
4484 ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS;
4485 for (i = 0; i < ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS; i++) {
4486 status = ice_read_sr_word(hw, (offset + i), &buf);
4488 ice_debug(hw, ICE_DBG_INIT,
4489 "Failed to read override link options.\n");
4492 /* shift 16 bits at a time to fill 64 bits */
4493 ldo->phy_type_high |= ((u64)buf << (i * 16));