1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2001-2021 Intel Corporation
5 #include "ice_common.h"
7 #include "ice_adminq_cmd.h"
10 #include "ice_switch.h"
12 #define ICE_PF_RESET_WAIT_COUNT 300
15 * dump_phy_type - helper function that prints PHY type strings
16 * @hw: pointer to the HW structure
17 * @phy: 64 bit PHY type to decipher
18 * @i: bit index within phy
19 * @phy_string: string corresponding to bit i in phy
20 * @prefix: prefix string to differentiate multiple dumps
23 dump_phy_type(struct ice_hw *hw, u64 phy, u8 i, const char *phy_string,
27 ice_debug(hw, ICE_DBG_PHY, "%s: bit(%d): %s\n", prefix, i,
32 * ice_dump_phy_type_low - helper function to dump phy_type_low
33 * @hw: pointer to the HW structure
34 * @low: 64 bit value for phy_type_low
35 * @prefix: prefix string to differentiate multiple dumps
38 ice_dump_phy_type_low(struct ice_hw *hw, u64 low, const char *prefix)
40 ice_debug(hw, ICE_DBG_PHY, "%s: phy_type_low: 0x%016llx\n", prefix,
41 (unsigned long long)low);
43 dump_phy_type(hw, low, 0, "100BASE_TX", prefix);
44 dump_phy_type(hw, low, 1, "100M_SGMII", prefix);
45 dump_phy_type(hw, low, 2, "1000BASE_T", prefix);
46 dump_phy_type(hw, low, 3, "1000BASE_SX", prefix);
47 dump_phy_type(hw, low, 4, "1000BASE_LX", prefix);
48 dump_phy_type(hw, low, 5, "1000BASE_KX", prefix);
49 dump_phy_type(hw, low, 6, "1G_SGMII", prefix);
50 dump_phy_type(hw, low, 7, "2500BASE_T", prefix);
51 dump_phy_type(hw, low, 8, "2500BASE_X", prefix);
52 dump_phy_type(hw, low, 9, "2500BASE_KX", prefix);
53 dump_phy_type(hw, low, 10, "5GBASE_T", prefix);
54 dump_phy_type(hw, low, 11, "5GBASE_KR", prefix);
55 dump_phy_type(hw, low, 12, "10GBASE_T", prefix);
56 dump_phy_type(hw, low, 13, "10G_SFI_DA", prefix);
57 dump_phy_type(hw, low, 14, "10GBASE_SR", prefix);
58 dump_phy_type(hw, low, 15, "10GBASE_LR", prefix);
59 dump_phy_type(hw, low, 16, "10GBASE_KR_CR1", prefix);
60 dump_phy_type(hw, low, 17, "10G_SFI_AOC_ACC", prefix);
61 dump_phy_type(hw, low, 18, "10G_SFI_C2C", prefix);
62 dump_phy_type(hw, low, 19, "25GBASE_T", prefix);
63 dump_phy_type(hw, low, 20, "25GBASE_CR", prefix);
64 dump_phy_type(hw, low, 21, "25GBASE_CR_S", prefix);
65 dump_phy_type(hw, low, 22, "25GBASE_CR1", prefix);
66 dump_phy_type(hw, low, 23, "25GBASE_SR", prefix);
67 dump_phy_type(hw, low, 24, "25GBASE_LR", prefix);
68 dump_phy_type(hw, low, 25, "25GBASE_KR", prefix);
69 dump_phy_type(hw, low, 26, "25GBASE_KR_S", prefix);
70 dump_phy_type(hw, low, 27, "25GBASE_KR1", prefix);
71 dump_phy_type(hw, low, 28, "25G_AUI_AOC_ACC", prefix);
72 dump_phy_type(hw, low, 29, "25G_AUI_C2C", prefix);
73 dump_phy_type(hw, low, 30, "40GBASE_CR4", prefix);
74 dump_phy_type(hw, low, 31, "40GBASE_SR4", prefix);
75 dump_phy_type(hw, low, 32, "40GBASE_LR4", prefix);
76 dump_phy_type(hw, low, 33, "40GBASE_KR4", prefix);
77 dump_phy_type(hw, low, 34, "40G_XLAUI_AOC_ACC", prefix);
78 dump_phy_type(hw, low, 35, "40G_XLAUI", prefix);
79 dump_phy_type(hw, low, 36, "50GBASE_CR2", prefix);
80 dump_phy_type(hw, low, 37, "50GBASE_SR2", prefix);
81 dump_phy_type(hw, low, 38, "50GBASE_LR2", prefix);
82 dump_phy_type(hw, low, 39, "50GBASE_KR2", prefix);
83 dump_phy_type(hw, low, 40, "50G_LAUI2_AOC_ACC", prefix);
84 dump_phy_type(hw, low, 41, "50G_LAUI2", prefix);
85 dump_phy_type(hw, low, 42, "50G_AUI2_AOC_ACC", prefix);
86 dump_phy_type(hw, low, 43, "50G_AUI2", prefix);
87 dump_phy_type(hw, low, 44, "50GBASE_CP", prefix);
88 dump_phy_type(hw, low, 45, "50GBASE_SR", prefix);
89 dump_phy_type(hw, low, 46, "50GBASE_FR", prefix);
90 dump_phy_type(hw, low, 47, "50GBASE_LR", prefix);
91 dump_phy_type(hw, low, 48, "50GBASE_KR_PAM4", prefix);
92 dump_phy_type(hw, low, 49, "50G_AUI1_AOC_ACC", prefix);
93 dump_phy_type(hw, low, 50, "50G_AUI1", prefix);
94 dump_phy_type(hw, low, 51, "100GBASE_CR4", prefix);
95 dump_phy_type(hw, low, 52, "100GBASE_SR4", prefix);
96 dump_phy_type(hw, low, 53, "100GBASE_LR4", prefix);
97 dump_phy_type(hw, low, 54, "100GBASE_KR4", prefix);
98 dump_phy_type(hw, low, 55, "100G_CAUI4_AOC_ACC", prefix);
99 dump_phy_type(hw, low, 56, "100G_CAUI4", prefix);
100 dump_phy_type(hw, low, 57, "100G_AUI4_AOC_ACC", prefix);
101 dump_phy_type(hw, low, 58, "100G_AUI4", prefix);
102 dump_phy_type(hw, low, 59, "100GBASE_CR_PAM4", prefix);
103 dump_phy_type(hw, low, 60, "100GBASE_KR_PAM4", prefix);
104 dump_phy_type(hw, low, 61, "100GBASE_CP2", prefix);
105 dump_phy_type(hw, low, 62, "100GBASE_SR2", prefix);
106 dump_phy_type(hw, low, 63, "100GBASE_DR", prefix);
110 * ice_dump_phy_type_high - helper function to dump phy_type_high
111 * @hw: pointer to the HW structure
112 * @high: 64 bit value for phy_type_high
113 * @prefix: prefix string to differentiate multiple dumps
116 ice_dump_phy_type_high(struct ice_hw *hw, u64 high, const char *prefix)
118 ice_debug(hw, ICE_DBG_PHY, "%s: phy_type_high: 0x%016llx\n", prefix,
119 (unsigned long long)high);
121 dump_phy_type(hw, high, 0, "100GBASE_KR2_PAM4", prefix);
122 dump_phy_type(hw, high, 1, "100G_CAUI2_AOC_ACC", prefix);
123 dump_phy_type(hw, high, 2, "100G_CAUI2", prefix);
124 dump_phy_type(hw, high, 3, "100G_AUI2_AOC_ACC", prefix);
125 dump_phy_type(hw, high, 4, "100G_AUI2", prefix);
129 * ice_set_mac_type - Sets MAC type
130 * @hw: pointer to the HW structure
132 * This function sets the MAC type of the adapter based on the
133 * vendor ID and device ID stored in the HW structure.
135 static enum ice_status ice_set_mac_type(struct ice_hw *hw)
137 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
139 if (hw->vendor_id != ICE_INTEL_VENDOR_ID)
140 return ICE_ERR_DEVICE_NOT_SUPPORTED;
142 switch (hw->device_id) {
143 case ICE_DEV_ID_E810C_BACKPLANE:
144 case ICE_DEV_ID_E810C_QSFP:
145 case ICE_DEV_ID_E810C_SFP:
146 case ICE_DEV_ID_E810_XXV_BACKPLANE:
147 case ICE_DEV_ID_E810_XXV_QSFP:
148 case ICE_DEV_ID_E810_XXV_SFP:
149 hw->mac_type = ICE_MAC_E810;
151 case ICE_DEV_ID_E822C_10G_BASE_T:
152 case ICE_DEV_ID_E822C_BACKPLANE:
153 case ICE_DEV_ID_E822C_QSFP:
154 case ICE_DEV_ID_E822C_SFP:
155 case ICE_DEV_ID_E822C_SGMII:
156 case ICE_DEV_ID_E822L_10G_BASE_T:
157 case ICE_DEV_ID_E822L_BACKPLANE:
158 case ICE_DEV_ID_E822L_SFP:
159 case ICE_DEV_ID_E822L_SGMII:
160 case ICE_DEV_ID_E823L_10G_BASE_T:
161 case ICE_DEV_ID_E823L_1GBE:
162 case ICE_DEV_ID_E823L_BACKPLANE:
163 case ICE_DEV_ID_E823L_QSFP:
164 case ICE_DEV_ID_E823L_SFP:
165 case ICE_DEV_ID_E823C_10G_BASE_T:
166 case ICE_DEV_ID_E823C_BACKPLANE:
167 case ICE_DEV_ID_E823C_QSFP:
168 case ICE_DEV_ID_E823C_SFP:
169 case ICE_DEV_ID_E823C_SGMII:
170 hw->mac_type = ICE_MAC_GENERIC;
173 hw->mac_type = ICE_MAC_UNKNOWN;
177 ice_debug(hw, ICE_DBG_INIT, "mac_type: %d\n", hw->mac_type);
183 * @hw: pointer to the hardware structure
185 * returns true if mac_type is ICE_MAC_GENERIC, false if not
187 bool ice_is_generic_mac(struct ice_hw *hw)
189 return hw->mac_type == ICE_MAC_GENERIC;
194 * @hw: pointer to the hardware structure
196 * returns true if the device is E810 based, false if not.
198 bool ice_is_e810(struct ice_hw *hw)
200 return hw->mac_type == ICE_MAC_E810;
205 * @hw: pointer to the hardware structure
207 * returns true if the device is E810T based, false if not.
209 bool ice_is_e810t(struct ice_hw *hw)
211 switch (hw->device_id) {
212 case ICE_DEV_ID_E810C_SFP:
213 if (hw->subsystem_device_id == ICE_SUBDEV_ID_E810T ||
214 hw->subsystem_device_id == ICE_SUBDEV_ID_E810T2)
217 case ICE_DEV_ID_E810C_QSFP:
218 if (hw->subsystem_device_id == ICE_SUBDEV_ID_E810T2)
229 * ice_clear_pf_cfg - Clear PF configuration
230 * @hw: pointer to the hardware structure
232 * Clears any existing PF configuration (VSIs, VSI lists, switch rules, port
233 * configuration, flow director filters, etc.).
235 enum ice_status ice_clear_pf_cfg(struct ice_hw *hw)
237 struct ice_aq_desc desc;
239 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pf_cfg);
241 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
245 * ice_aq_manage_mac_read - manage MAC address read command
246 * @hw: pointer to the HW struct
247 * @buf: a virtual buffer to hold the manage MAC read response
248 * @buf_size: Size of the virtual buffer
249 * @cd: pointer to command details structure or NULL
251 * This function is used to return per PF station MAC address (0x0107).
252 * NOTE: Upon successful completion of this command, MAC address information
253 * is returned in user specified buffer. Please interpret user specified
254 * buffer as "manage_mac_read" response.
255 * Response such as various MAC addresses are stored in HW struct (port.mac)
256 * ice_discover_dev_caps is expected to be called before this function is
259 static enum ice_status
260 ice_aq_manage_mac_read(struct ice_hw *hw, void *buf, u16 buf_size,
261 struct ice_sq_cd *cd)
263 struct ice_aqc_manage_mac_read_resp *resp;
264 struct ice_aqc_manage_mac_read *cmd;
265 struct ice_aq_desc desc;
266 enum ice_status status;
270 cmd = &desc.params.mac_read;
272 if (buf_size < sizeof(*resp))
273 return ICE_ERR_BUF_TOO_SHORT;
275 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_read);
277 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);
281 resp = (struct ice_aqc_manage_mac_read_resp *)buf;
282 flags = LE16_TO_CPU(cmd->flags) & ICE_AQC_MAN_MAC_READ_M;
284 if (!(flags & ICE_AQC_MAN_MAC_LAN_ADDR_VALID)) {
285 ice_debug(hw, ICE_DBG_LAN, "got invalid MAC address\n");
289 /* A single port can report up to two (LAN and WoL) addresses */
290 for (i = 0; i < cmd->num_addr; i++)
291 if (resp[i].addr_type == ICE_AQC_MAN_MAC_ADDR_TYPE_LAN) {
292 ice_memcpy(hw->port_info->mac.lan_addr,
293 resp[i].mac_addr, ETH_ALEN,
295 ice_memcpy(hw->port_info->mac.perm_addr,
297 ETH_ALEN, ICE_DMA_TO_NONDMA);
304 * ice_aq_get_phy_caps - returns PHY capabilities
305 * @pi: port information structure
306 * @qual_mods: report qualified modules
307 * @report_mode: report mode capabilities
308 * @pcaps: structure for PHY capabilities to be filled
309 * @cd: pointer to command details structure or NULL
311 * Returns the various PHY capabilities supported on the Port (0x0600)
314 ice_aq_get_phy_caps(struct ice_port_info *pi, bool qual_mods, u8 report_mode,
315 struct ice_aqc_get_phy_caps_data *pcaps,
316 struct ice_sq_cd *cd)
318 struct ice_aqc_get_phy_caps *cmd;
319 u16 pcaps_size = sizeof(*pcaps);
320 struct ice_aq_desc desc;
321 enum ice_status status;
325 cmd = &desc.params.get_phy;
327 if (!pcaps || (report_mode & ~ICE_AQC_REPORT_MODE_M) || !pi)
328 return ICE_ERR_PARAM;
331 if (report_mode == ICE_AQC_REPORT_DFLT_CFG &&
332 !ice_fw_supports_report_dflt_cfg(hw))
333 return ICE_ERR_PARAM;
335 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_phy_caps);
338 cmd->param0 |= CPU_TO_LE16(ICE_AQC_GET_PHY_RQM);
340 cmd->param0 |= CPU_TO_LE16(report_mode);
341 status = ice_aq_send_cmd(hw, &desc, pcaps, pcaps_size, cd);
343 ice_debug(hw, ICE_DBG_LINK, "get phy caps dump\n");
345 if (report_mode == ICE_AQC_REPORT_TOPO_CAP_MEDIA)
346 prefix = "phy_caps_media";
347 else if (report_mode == ICE_AQC_REPORT_TOPO_CAP_NO_MEDIA)
348 prefix = "phy_caps_no_media";
349 else if (report_mode == ICE_AQC_REPORT_ACTIVE_CFG)
350 prefix = "phy_caps_active";
351 else if (report_mode == ICE_AQC_REPORT_DFLT_CFG)
352 prefix = "phy_caps_default";
354 prefix = "phy_caps_invalid";
356 ice_dump_phy_type_low(hw, LE64_TO_CPU(pcaps->phy_type_low), prefix);
357 ice_dump_phy_type_high(hw, LE64_TO_CPU(pcaps->phy_type_high), prefix);
359 ice_debug(hw, ICE_DBG_LINK, "%s: report_mode = 0x%x\n",
360 prefix, report_mode);
361 ice_debug(hw, ICE_DBG_LINK, "%s: caps = 0x%x\n", prefix, pcaps->caps);
362 ice_debug(hw, ICE_DBG_LINK, "%s: low_power_ctrl_an = 0x%x\n", prefix,
363 pcaps->low_power_ctrl_an);
364 ice_debug(hw, ICE_DBG_LINK, "%s: eee_cap = 0x%x\n", prefix,
366 ice_debug(hw, ICE_DBG_LINK, "%s: eeer_value = 0x%x\n", prefix,
368 ice_debug(hw, ICE_DBG_LINK, "%s: link_fec_options = 0x%x\n", prefix,
369 pcaps->link_fec_options);
370 ice_debug(hw, ICE_DBG_LINK, "%s: module_compliance_enforcement = 0x%x\n",
371 prefix, pcaps->module_compliance_enforcement);
372 ice_debug(hw, ICE_DBG_LINK, "%s: extended_compliance_code = 0x%x\n",
373 prefix, pcaps->extended_compliance_code);
374 ice_debug(hw, ICE_DBG_LINK, "%s: module_type[0] = 0x%x\n", prefix,
375 pcaps->module_type[0]);
376 ice_debug(hw, ICE_DBG_LINK, "%s: module_type[1] = 0x%x\n", prefix,
377 pcaps->module_type[1]);
378 ice_debug(hw, ICE_DBG_LINK, "%s: module_type[2] = 0x%x\n", prefix,
379 pcaps->module_type[2]);
381 if (status == ICE_SUCCESS && report_mode == ICE_AQC_REPORT_TOPO_CAP_MEDIA) {
382 pi->phy.phy_type_low = LE64_TO_CPU(pcaps->phy_type_low);
383 pi->phy.phy_type_high = LE64_TO_CPU(pcaps->phy_type_high);
384 ice_memcpy(pi->phy.link_info.module_type, &pcaps->module_type,
385 sizeof(pi->phy.link_info.module_type),
386 ICE_NONDMA_TO_NONDMA);
393 * ice_aq_get_link_topo_handle - get link topology node return status
394 * @pi: port information structure
395 * @node_type: requested node type
396 * @cd: pointer to command details structure or NULL
398 * Get link topology node return status for specified node type (0x06E0)
400 * Node type cage can be used to determine if cage is present. If AQC
401 * returns error (ENOENT), then no cage present. If no cage present, then
402 * connection type is backplane or BASE-T.
404 static enum ice_status
405 ice_aq_get_link_topo_handle(struct ice_port_info *pi, u8 node_type,
406 struct ice_sq_cd *cd)
408 struct ice_aqc_get_link_topo *cmd;
409 struct ice_aq_desc desc;
411 cmd = &desc.params.get_link_topo;
413 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_topo);
415 cmd->addr.topo_params.node_type_ctx =
416 (ICE_AQC_LINK_TOPO_NODE_CTX_PORT <<
417 ICE_AQC_LINK_TOPO_NODE_CTX_S);
420 cmd->addr.topo_params.node_type_ctx |=
421 (ICE_AQC_LINK_TOPO_NODE_TYPE_M & node_type);
423 return ice_aq_send_cmd(pi->hw, &desc, NULL, 0, cd);
427 * ice_is_media_cage_present
428 * @pi: port information structure
430 * Returns true if media cage is present, else false. If no cage, then
431 * media type is backplane or BASE-T.
433 static bool ice_is_media_cage_present(struct ice_port_info *pi)
435 /* Node type cage can be used to determine if cage is present. If AQC
436 * returns error (ENOENT), then no cage present. If no cage present then
437 * connection type is backplane or BASE-T.
439 return !ice_aq_get_link_topo_handle(pi,
440 ICE_AQC_LINK_TOPO_NODE_TYPE_CAGE,
445 * ice_get_media_type - Gets media type
446 * @pi: port information structure
448 static enum ice_media_type ice_get_media_type(struct ice_port_info *pi)
450 struct ice_link_status *hw_link_info;
453 return ICE_MEDIA_UNKNOWN;
455 hw_link_info = &pi->phy.link_info;
456 if (hw_link_info->phy_type_low && hw_link_info->phy_type_high)
457 /* If more than one media type is selected, report unknown */
458 return ICE_MEDIA_UNKNOWN;
460 if (hw_link_info->phy_type_low) {
461 /* 1G SGMII is a special case where some DA cable PHYs
462 * may show this as an option when it really shouldn't
463 * be since SGMII is meant to be between a MAC and a PHY
464 * in a backplane. Try to detect this case and handle it
466 if (hw_link_info->phy_type_low == ICE_PHY_TYPE_LOW_1G_SGMII &&
467 (hw_link_info->module_type[ICE_AQC_MOD_TYPE_IDENT] ==
468 ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_ACTIVE ||
469 hw_link_info->module_type[ICE_AQC_MOD_TYPE_IDENT] ==
470 ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_PASSIVE))
473 switch (hw_link_info->phy_type_low) {
474 case ICE_PHY_TYPE_LOW_1000BASE_SX:
475 case ICE_PHY_TYPE_LOW_1000BASE_LX:
476 case ICE_PHY_TYPE_LOW_10GBASE_SR:
477 case ICE_PHY_TYPE_LOW_10GBASE_LR:
478 case ICE_PHY_TYPE_LOW_10G_SFI_C2C:
479 case ICE_PHY_TYPE_LOW_25GBASE_SR:
480 case ICE_PHY_TYPE_LOW_25GBASE_LR:
481 case ICE_PHY_TYPE_LOW_40GBASE_SR4:
482 case ICE_PHY_TYPE_LOW_40GBASE_LR4:
483 case ICE_PHY_TYPE_LOW_50GBASE_SR2:
484 case ICE_PHY_TYPE_LOW_50GBASE_LR2:
485 case ICE_PHY_TYPE_LOW_50GBASE_SR:
486 case ICE_PHY_TYPE_LOW_50GBASE_FR:
487 case ICE_PHY_TYPE_LOW_50GBASE_LR:
488 case ICE_PHY_TYPE_LOW_100GBASE_SR4:
489 case ICE_PHY_TYPE_LOW_100GBASE_LR4:
490 case ICE_PHY_TYPE_LOW_100GBASE_SR2:
491 case ICE_PHY_TYPE_LOW_100GBASE_DR:
492 return ICE_MEDIA_FIBER;
493 case ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC:
494 case ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC:
495 case ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC:
496 case ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC:
497 case ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC:
498 case ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC:
499 case ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC:
500 case ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC:
501 return ICE_MEDIA_FIBER;
502 case ICE_PHY_TYPE_LOW_100BASE_TX:
503 case ICE_PHY_TYPE_LOW_1000BASE_T:
504 case ICE_PHY_TYPE_LOW_2500BASE_T:
505 case ICE_PHY_TYPE_LOW_5GBASE_T:
506 case ICE_PHY_TYPE_LOW_10GBASE_T:
507 case ICE_PHY_TYPE_LOW_25GBASE_T:
508 return ICE_MEDIA_BASET;
509 case ICE_PHY_TYPE_LOW_10G_SFI_DA:
510 case ICE_PHY_TYPE_LOW_25GBASE_CR:
511 case ICE_PHY_TYPE_LOW_25GBASE_CR_S:
512 case ICE_PHY_TYPE_LOW_25GBASE_CR1:
513 case ICE_PHY_TYPE_LOW_40GBASE_CR4:
514 case ICE_PHY_TYPE_LOW_50GBASE_CR2:
515 case ICE_PHY_TYPE_LOW_50GBASE_CP:
516 case ICE_PHY_TYPE_LOW_100GBASE_CR4:
517 case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4:
518 case ICE_PHY_TYPE_LOW_100GBASE_CP2:
520 case ICE_PHY_TYPE_LOW_25G_AUI_C2C:
521 case ICE_PHY_TYPE_LOW_40G_XLAUI:
522 case ICE_PHY_TYPE_LOW_50G_LAUI2:
523 case ICE_PHY_TYPE_LOW_50G_AUI2:
524 case ICE_PHY_TYPE_LOW_50G_AUI1:
525 case ICE_PHY_TYPE_LOW_100G_AUI4:
526 case ICE_PHY_TYPE_LOW_100G_CAUI4:
527 if (ice_is_media_cage_present(pi))
528 return ICE_MEDIA_AUI;
530 case ICE_PHY_TYPE_LOW_1000BASE_KX:
531 case ICE_PHY_TYPE_LOW_2500BASE_KX:
532 case ICE_PHY_TYPE_LOW_2500BASE_X:
533 case ICE_PHY_TYPE_LOW_5GBASE_KR:
534 case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1:
535 case ICE_PHY_TYPE_LOW_25GBASE_KR:
536 case ICE_PHY_TYPE_LOW_25GBASE_KR1:
537 case ICE_PHY_TYPE_LOW_25GBASE_KR_S:
538 case ICE_PHY_TYPE_LOW_40GBASE_KR4:
539 case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4:
540 case ICE_PHY_TYPE_LOW_50GBASE_KR2:
541 case ICE_PHY_TYPE_LOW_100GBASE_KR4:
542 case ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4:
543 return ICE_MEDIA_BACKPLANE;
546 switch (hw_link_info->phy_type_high) {
547 case ICE_PHY_TYPE_HIGH_100G_AUI2:
548 case ICE_PHY_TYPE_HIGH_100G_CAUI2:
549 if (ice_is_media_cage_present(pi))
550 return ICE_MEDIA_AUI;
552 case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4:
553 return ICE_MEDIA_BACKPLANE;
554 case ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC:
555 case ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC:
556 return ICE_MEDIA_FIBER;
559 return ICE_MEDIA_UNKNOWN;
563 * ice_aq_get_link_info
564 * @pi: port information structure
565 * @ena_lse: enable/disable LinkStatusEvent reporting
566 * @link: pointer to link status structure - optional
567 * @cd: pointer to command details structure or NULL
569 * Get Link Status (0x607). Returns the link status of the adapter.
572 ice_aq_get_link_info(struct ice_port_info *pi, bool ena_lse,
573 struct ice_link_status *link, struct ice_sq_cd *cd)
575 struct ice_aqc_get_link_status_data link_data = { 0 };
576 struct ice_aqc_get_link_status *resp;
577 struct ice_link_status *li_old, *li;
578 enum ice_media_type *hw_media_type;
579 struct ice_fc_info *hw_fc_info;
580 bool tx_pause, rx_pause;
581 struct ice_aq_desc desc;
582 enum ice_status status;
587 return ICE_ERR_PARAM;
589 li_old = &pi->phy.link_info_old;
590 hw_media_type = &pi->phy.media_type;
591 li = &pi->phy.link_info;
592 hw_fc_info = &pi->fc;
594 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_status);
595 cmd_flags = (ena_lse) ? ICE_AQ_LSE_ENA : ICE_AQ_LSE_DIS;
596 resp = &desc.params.get_link_status;
597 resp->cmd_flags = CPU_TO_LE16(cmd_flags);
598 resp->lport_num = pi->lport;
600 status = ice_aq_send_cmd(hw, &desc, &link_data, sizeof(link_data), cd);
602 if (status != ICE_SUCCESS)
605 /* save off old link status information */
608 /* update current link status information */
609 li->link_speed = LE16_TO_CPU(link_data.link_speed);
610 li->phy_type_low = LE64_TO_CPU(link_data.phy_type_low);
611 li->phy_type_high = LE64_TO_CPU(link_data.phy_type_high);
612 *hw_media_type = ice_get_media_type(pi);
613 li->link_info = link_data.link_info;
614 li->link_cfg_err = link_data.link_cfg_err;
615 li->an_info = link_data.an_info;
616 li->ext_info = link_data.ext_info;
617 li->max_frame_size = LE16_TO_CPU(link_data.max_frame_size);
618 li->fec_info = link_data.cfg & ICE_AQ_FEC_MASK;
619 li->topo_media_conflict = link_data.topo_media_conflict;
620 li->pacing = link_data.cfg & (ICE_AQ_CFG_PACING_M |
621 ICE_AQ_CFG_PACING_TYPE_M);
624 tx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_TX);
625 rx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_RX);
626 if (tx_pause && rx_pause)
627 hw_fc_info->current_mode = ICE_FC_FULL;
629 hw_fc_info->current_mode = ICE_FC_TX_PAUSE;
631 hw_fc_info->current_mode = ICE_FC_RX_PAUSE;
633 hw_fc_info->current_mode = ICE_FC_NONE;
635 li->lse_ena = !!(resp->cmd_flags & CPU_TO_LE16(ICE_AQ_LSE_IS_ENABLED));
637 ice_debug(hw, ICE_DBG_LINK, "get link info\n");
638 ice_debug(hw, ICE_DBG_LINK, " link_speed = 0x%x\n", li->link_speed);
639 ice_debug(hw, ICE_DBG_LINK, " phy_type_low = 0x%llx\n",
640 (unsigned long long)li->phy_type_low);
641 ice_debug(hw, ICE_DBG_LINK, " phy_type_high = 0x%llx\n",
642 (unsigned long long)li->phy_type_high);
643 ice_debug(hw, ICE_DBG_LINK, " media_type = 0x%x\n", *hw_media_type);
644 ice_debug(hw, ICE_DBG_LINK, " link_info = 0x%x\n", li->link_info);
645 ice_debug(hw, ICE_DBG_LINK, " link_cfg_err = 0x%x\n", li->link_cfg_err);
646 ice_debug(hw, ICE_DBG_LINK, " an_info = 0x%x\n", li->an_info);
647 ice_debug(hw, ICE_DBG_LINK, " ext_info = 0x%x\n", li->ext_info);
648 ice_debug(hw, ICE_DBG_LINK, " fec_info = 0x%x\n", li->fec_info);
649 ice_debug(hw, ICE_DBG_LINK, " lse_ena = 0x%x\n", li->lse_ena);
650 ice_debug(hw, ICE_DBG_LINK, " max_frame = 0x%x\n",
652 ice_debug(hw, ICE_DBG_LINK, " pacing = 0x%x\n", li->pacing);
654 /* save link status information */
658 /* flag cleared so calling functions don't call AQ again */
659 pi->phy.get_link_info = false;
665 * ice_fill_tx_timer_and_fc_thresh
666 * @hw: pointer to the HW struct
667 * @cmd: pointer to MAC cfg structure
669 * Add Tx timer and FC refresh threshold info to Set MAC Config AQ command
673 ice_fill_tx_timer_and_fc_thresh(struct ice_hw *hw,
674 struct ice_aqc_set_mac_cfg *cmd)
676 u16 fc_thres_val, tx_timer_val;
679 /* We read back the transmit timer and fc threshold value of
680 * LFC. Thus, we will use index =
681 * PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX.
683 * Also, because we are opearating on transmit timer and fc
684 * threshold of LFC, we don't turn on any bit in tx_tmr_priority
686 #define IDX_OF_LFC PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX
688 /* Retrieve the transmit timer */
689 val = rd32(hw, PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(IDX_OF_LFC));
691 PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_HSEC_CTL_TX_PAUSE_QUANTA_M;
692 cmd->tx_tmr_value = CPU_TO_LE16(tx_timer_val);
694 /* Retrieve the fc threshold */
695 val = rd32(hw, PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(IDX_OF_LFC));
696 fc_thres_val = val & PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_M;
698 cmd->fc_refresh_threshold = CPU_TO_LE16(fc_thres_val);
703 * @hw: pointer to the HW struct
704 * @max_frame_size: Maximum Frame Size to be supported
705 * @cd: pointer to command details structure or NULL
707 * Set MAC configuration (0x0603)
710 ice_aq_set_mac_cfg(struct ice_hw *hw, u16 max_frame_size, struct ice_sq_cd *cd)
712 struct ice_aqc_set_mac_cfg *cmd;
713 struct ice_aq_desc desc;
715 cmd = &desc.params.set_mac_cfg;
717 if (max_frame_size == 0)
718 return ICE_ERR_PARAM;
720 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_mac_cfg);
722 cmd->max_frame_size = CPU_TO_LE16(max_frame_size);
724 ice_fill_tx_timer_and_fc_thresh(hw, cmd);
726 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
730 * ice_init_fltr_mgmt_struct - initializes filter management list and locks
731 * @hw: pointer to the HW struct
733 enum ice_status ice_init_fltr_mgmt_struct(struct ice_hw *hw)
735 struct ice_switch_info *sw;
736 enum ice_status status;
738 hw->switch_info = (struct ice_switch_info *)
739 ice_malloc(hw, sizeof(*hw->switch_info));
741 sw = hw->switch_info;
744 return ICE_ERR_NO_MEMORY;
746 INIT_LIST_HEAD(&sw->vsi_list_map_head);
747 sw->prof_res_bm_init = 0;
749 status = ice_init_def_sw_recp(hw, &hw->switch_info->recp_list);
751 ice_free(hw, hw->switch_info);
758 * ice_cleanup_fltr_mgmt_single - clears single filter mngt struct
759 * @hw: pointer to the HW struct
760 * @sw: pointer to switch info struct for which function clears filters
763 ice_cleanup_fltr_mgmt_single(struct ice_hw *hw, struct ice_switch_info *sw)
765 struct ice_vsi_list_map_info *v_pos_map;
766 struct ice_vsi_list_map_info *v_tmp_map;
767 struct ice_sw_recipe *recps;
773 LIST_FOR_EACH_ENTRY_SAFE(v_pos_map, v_tmp_map, &sw->vsi_list_map_head,
774 ice_vsi_list_map_info, list_entry) {
775 LIST_DEL(&v_pos_map->list_entry);
776 ice_free(hw, v_pos_map);
778 recps = sw->recp_list;
779 for (i = 0; i < ICE_MAX_NUM_RECIPES; i++) {
780 struct ice_recp_grp_entry *rg_entry, *tmprg_entry;
782 recps[i].root_rid = i;
783 LIST_FOR_EACH_ENTRY_SAFE(rg_entry, tmprg_entry,
784 &recps[i].rg_list, ice_recp_grp_entry,
786 LIST_DEL(&rg_entry->l_entry);
787 ice_free(hw, rg_entry);
790 if (recps[i].adv_rule) {
791 struct ice_adv_fltr_mgmt_list_entry *tmp_entry;
792 struct ice_adv_fltr_mgmt_list_entry *lst_itr;
794 ice_destroy_lock(&recps[i].filt_rule_lock);
795 LIST_FOR_EACH_ENTRY_SAFE(lst_itr, tmp_entry,
796 &recps[i].filt_rules,
797 ice_adv_fltr_mgmt_list_entry,
799 LIST_DEL(&lst_itr->list_entry);
800 ice_free(hw, lst_itr->lkups);
801 ice_free(hw, lst_itr);
804 struct ice_fltr_mgmt_list_entry *lst_itr, *tmp_entry;
806 ice_destroy_lock(&recps[i].filt_rule_lock);
807 LIST_FOR_EACH_ENTRY_SAFE(lst_itr, tmp_entry,
808 &recps[i].filt_rules,
809 ice_fltr_mgmt_list_entry,
811 LIST_DEL(&lst_itr->list_entry);
812 ice_free(hw, lst_itr);
815 if (recps[i].root_buf)
816 ice_free(hw, recps[i].root_buf);
818 ice_rm_sw_replay_rule_info(hw, sw);
819 ice_free(hw, sw->recp_list);
824 * ice_cleanup_fltr_mgmt_struct - cleanup filter management list and locks
825 * @hw: pointer to the HW struct
827 void ice_cleanup_fltr_mgmt_struct(struct ice_hw *hw)
829 ice_cleanup_fltr_mgmt_single(hw, hw->switch_info);
833 * ice_get_itr_intrl_gran
834 * @hw: pointer to the HW struct
836 * Determines the ITR/INTRL granularities based on the maximum aggregate
837 * bandwidth according to the device's configuration during power-on.
839 static void ice_get_itr_intrl_gran(struct ice_hw *hw)
841 u8 max_agg_bw = (rd32(hw, GL_PWR_MODE_CTL) &
842 GL_PWR_MODE_CTL_CAR_MAX_BW_M) >>
843 GL_PWR_MODE_CTL_CAR_MAX_BW_S;
845 switch (max_agg_bw) {
846 case ICE_MAX_AGG_BW_200G:
847 case ICE_MAX_AGG_BW_100G:
848 case ICE_MAX_AGG_BW_50G:
849 hw->itr_gran = ICE_ITR_GRAN_ABOVE_25;
850 hw->intrl_gran = ICE_INTRL_GRAN_ABOVE_25;
852 case ICE_MAX_AGG_BW_25G:
853 hw->itr_gran = ICE_ITR_GRAN_MAX_25;
854 hw->intrl_gran = ICE_INTRL_GRAN_MAX_25;
860 * ice_print_rollback_msg - print FW rollback message
861 * @hw: pointer to the hardware structure
863 void ice_print_rollback_msg(struct ice_hw *hw)
865 char nvm_str[ICE_NVM_VER_LEN] = { 0 };
866 struct ice_orom_info *orom;
867 struct ice_nvm_info *nvm;
869 orom = &hw->flash.orom;
870 nvm = &hw->flash.nvm;
872 SNPRINTF(nvm_str, sizeof(nvm_str), "%x.%02x 0x%x %d.%d.%d",
873 nvm->major, nvm->minor, nvm->eetrack, orom->major,
874 orom->build, orom->patch);
876 "Firmware rollback mode detected. Current version is NVM: %s, FW: %d.%d. Device may exhibit limited functionality. Refer to the Intel(R) Ethernet Adapters and Devices User Guide for details on firmware rollback mode\n",
877 nvm_str, hw->fw_maj_ver, hw->fw_min_ver);
881 * ice_set_umac_shared
882 * @hw: pointer to the hw struct
884 * Set boolean flag to allow unicast MAC sharing
886 void ice_set_umac_shared(struct ice_hw *hw)
888 hw->umac_shared = true;
892 * ice_init_hw - main hardware initialization routine
893 * @hw: pointer to the hardware structure
895 enum ice_status ice_init_hw(struct ice_hw *hw)
897 struct ice_aqc_get_phy_caps_data *pcaps;
898 enum ice_status status;
902 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
904 /* Set MAC type based on DeviceID */
905 status = ice_set_mac_type(hw);
909 hw->pf_id = (u8)(rd32(hw, PF_FUNC_RID) &
910 PF_FUNC_RID_FUNCTION_NUMBER_M) >>
911 PF_FUNC_RID_FUNCTION_NUMBER_S;
913 status = ice_reset(hw, ICE_RESET_PFR);
917 ice_get_itr_intrl_gran(hw);
919 status = ice_create_all_ctrlq(hw);
921 goto err_unroll_cqinit;
923 status = ice_init_nvm(hw);
925 goto err_unroll_cqinit;
927 if (ice_get_fw_mode(hw) == ICE_FW_MODE_ROLLBACK)
928 ice_print_rollback_msg(hw);
930 status = ice_clear_pf_cfg(hw);
932 goto err_unroll_cqinit;
934 /* Set bit to enable Flow Director filters */
935 wr32(hw, PFQF_FD_ENA, PFQF_FD_ENA_FD_ENA_M);
936 INIT_LIST_HEAD(&hw->fdir_list_head);
938 ice_clear_pxe_mode(hw);
940 status = ice_get_caps(hw);
942 goto err_unroll_cqinit;
944 hw->port_info = (struct ice_port_info *)
945 ice_malloc(hw, sizeof(*hw->port_info));
946 if (!hw->port_info) {
947 status = ICE_ERR_NO_MEMORY;
948 goto err_unroll_cqinit;
951 /* set the back pointer to HW */
952 hw->port_info->hw = hw;
954 /* Initialize port_info struct with switch configuration data */
955 status = ice_get_initial_sw_cfg(hw);
957 goto err_unroll_alloc;
960 /* Query the allocated resources for Tx scheduler */
961 status = ice_sched_query_res_alloc(hw);
963 ice_debug(hw, ICE_DBG_SCHED, "Failed to get scheduler allocated resources\n");
964 goto err_unroll_alloc;
966 ice_sched_get_psm_clk_freq(hw);
968 /* Initialize port_info struct with scheduler data */
969 status = ice_sched_init_port(hw->port_info);
971 goto err_unroll_sched;
972 pcaps = (struct ice_aqc_get_phy_caps_data *)
973 ice_malloc(hw, sizeof(*pcaps));
975 status = ICE_ERR_NO_MEMORY;
976 goto err_unroll_sched;
979 /* Initialize port_info struct with PHY capabilities */
980 status = ice_aq_get_phy_caps(hw->port_info, false,
981 ICE_AQC_REPORT_TOPO_CAP_MEDIA, pcaps, NULL);
984 ice_warn(hw, "Get PHY capabilities failed status = %d, continuing anyway\n",
987 /* Initialize port_info struct with link information */
988 status = ice_aq_get_link_info(hw->port_info, false, NULL, NULL);
990 goto err_unroll_sched;
991 /* need a valid SW entry point to build a Tx tree */
992 if (!hw->sw_entry_point_layer) {
993 ice_debug(hw, ICE_DBG_SCHED, "invalid sw entry point\n");
994 status = ICE_ERR_CFG;
995 goto err_unroll_sched;
997 INIT_LIST_HEAD(&hw->agg_list);
998 /* Initialize max burst size */
999 if (!hw->max_burst_size)
1000 ice_cfg_rl_burst_size(hw, ICE_SCHED_DFLT_BURST_SIZE);
1001 status = ice_init_fltr_mgmt_struct(hw);
1003 goto err_unroll_sched;
1005 /* Get MAC information */
1006 /* A single port can report up to two (LAN and WoL) addresses */
1007 mac_buf = ice_calloc(hw, 2,
1008 sizeof(struct ice_aqc_manage_mac_read_resp));
1009 mac_buf_len = 2 * sizeof(struct ice_aqc_manage_mac_read_resp);
1012 status = ICE_ERR_NO_MEMORY;
1013 goto err_unroll_fltr_mgmt_struct;
1016 status = ice_aq_manage_mac_read(hw, mac_buf, mac_buf_len, NULL);
1017 ice_free(hw, mac_buf);
1020 goto err_unroll_fltr_mgmt_struct;
1022 /* enable jumbo frame support at MAC level */
1023 status = ice_aq_set_mac_cfg(hw, ICE_AQ_SET_MAC_FRAME_SIZE_MAX, NULL);
1025 goto err_unroll_fltr_mgmt_struct;
1027 /* Obtain counter base index which would be used by flow director */
1028 status = ice_alloc_fd_res_cntr(hw, &hw->fd_ctr_base);
1030 goto err_unroll_fltr_mgmt_struct;
1031 status = ice_init_hw_tbls(hw);
1033 goto err_unroll_fltr_mgmt_struct;
1034 ice_init_lock(&hw->tnl_lock);
1038 err_unroll_fltr_mgmt_struct:
1039 ice_cleanup_fltr_mgmt_struct(hw);
1041 ice_sched_cleanup_all(hw);
1043 ice_free(hw, hw->port_info);
1044 hw->port_info = NULL;
1046 ice_destroy_all_ctrlq(hw);
1051 * ice_deinit_hw - unroll initialization operations done by ice_init_hw
1052 * @hw: pointer to the hardware structure
1054 * This should be called only during nominal operation, not as a result of
1055 * ice_init_hw() failing since ice_init_hw() will take care of unrolling
1056 * applicable initializations if it fails for any reason.
1058 void ice_deinit_hw(struct ice_hw *hw)
1060 ice_free_fd_res_cntr(hw, hw->fd_ctr_base);
1061 ice_cleanup_fltr_mgmt_struct(hw);
1063 ice_sched_cleanup_all(hw);
1064 ice_sched_clear_agg(hw);
1066 ice_free_hw_tbls(hw);
1067 ice_destroy_lock(&hw->tnl_lock);
1069 if (hw->port_info) {
1070 ice_free(hw, hw->port_info);
1071 hw->port_info = NULL;
1074 ice_destroy_all_ctrlq(hw);
1076 /* Clear VSI contexts if not already cleared */
1077 ice_clear_all_vsi_ctx(hw);
1081 * ice_check_reset - Check to see if a global reset is complete
1082 * @hw: pointer to the hardware structure
1084 enum ice_status ice_check_reset(struct ice_hw *hw)
1086 u32 cnt, reg = 0, grst_timeout, uld_mask;
1088 /* Poll for Device Active state in case a recent CORER, GLOBR,
1089 * or EMPR has occurred. The grst delay value is in 100ms units.
1090 * Add 1sec for outstanding AQ commands that can take a long time.
1092 grst_timeout = ((rd32(hw, GLGEN_RSTCTL) & GLGEN_RSTCTL_GRSTDEL_M) >>
1093 GLGEN_RSTCTL_GRSTDEL_S) + 10;
1095 for (cnt = 0; cnt < grst_timeout; cnt++) {
1096 ice_msec_delay(100, true);
1097 reg = rd32(hw, GLGEN_RSTAT);
1098 if (!(reg & GLGEN_RSTAT_DEVSTATE_M))
1102 if (cnt == grst_timeout) {
1103 ice_debug(hw, ICE_DBG_INIT, "Global reset polling failed to complete.\n");
1104 return ICE_ERR_RESET_FAILED;
1107 #define ICE_RESET_DONE_MASK (GLNVM_ULD_PCIER_DONE_M |\
1108 GLNVM_ULD_PCIER_DONE_1_M |\
1109 GLNVM_ULD_CORER_DONE_M |\
1110 GLNVM_ULD_GLOBR_DONE_M |\
1111 GLNVM_ULD_POR_DONE_M |\
1112 GLNVM_ULD_POR_DONE_1_M |\
1113 GLNVM_ULD_PCIER_DONE_2_M)
1115 uld_mask = ICE_RESET_DONE_MASK;
1117 /* Device is Active; check Global Reset processes are done */
1118 for (cnt = 0; cnt < ICE_PF_RESET_WAIT_COUNT; cnt++) {
1119 reg = rd32(hw, GLNVM_ULD) & uld_mask;
1120 if (reg == uld_mask) {
1121 ice_debug(hw, ICE_DBG_INIT, "Global reset processes done. %d\n", cnt);
1124 ice_msec_delay(10, true);
1127 if (cnt == ICE_PF_RESET_WAIT_COUNT) {
1128 ice_debug(hw, ICE_DBG_INIT, "Wait for Reset Done timed out. GLNVM_ULD = 0x%x\n",
1130 return ICE_ERR_RESET_FAILED;
1137 * ice_pf_reset - Reset the PF
1138 * @hw: pointer to the hardware structure
1140 * If a global reset has been triggered, this function checks
1141 * for its completion and then issues the PF reset
1143 static enum ice_status ice_pf_reset(struct ice_hw *hw)
1147 /* If at function entry a global reset was already in progress, i.e.
1148 * state is not 'device active' or any of the reset done bits are not
1149 * set in GLNVM_ULD, there is no need for a PF Reset; poll until the
1150 * global reset is done.
1152 if ((rd32(hw, GLGEN_RSTAT) & GLGEN_RSTAT_DEVSTATE_M) ||
1153 (rd32(hw, GLNVM_ULD) & ICE_RESET_DONE_MASK) ^ ICE_RESET_DONE_MASK) {
1154 /* poll on global reset currently in progress until done */
1155 if (ice_check_reset(hw))
1156 return ICE_ERR_RESET_FAILED;
1162 reg = rd32(hw, PFGEN_CTRL);
1164 wr32(hw, PFGEN_CTRL, (reg | PFGEN_CTRL_PFSWR_M));
1166 /* Wait for the PFR to complete. The wait time is the global config lock
1167 * timeout plus the PFR timeout which will account for a possible reset
1168 * that is occurring during a download package operation.
1170 for (cnt = 0; cnt < ICE_GLOBAL_CFG_LOCK_TIMEOUT +
1171 ICE_PF_RESET_WAIT_COUNT; cnt++) {
1172 reg = rd32(hw, PFGEN_CTRL);
1173 if (!(reg & PFGEN_CTRL_PFSWR_M))
1176 ice_msec_delay(1, true);
1179 if (cnt == ICE_PF_RESET_WAIT_COUNT) {
1180 ice_debug(hw, ICE_DBG_INIT, "PF reset polling failed to complete.\n");
1181 return ICE_ERR_RESET_FAILED;
1188 * ice_reset - Perform different types of reset
1189 * @hw: pointer to the hardware structure
1190 * @req: reset request
1192 * This function triggers a reset as specified by the req parameter.
1195 * If anything other than a PF reset is triggered, PXE mode is restored.
1196 * This has to be cleared using ice_clear_pxe_mode again, once the AQ
1197 * interface has been restored in the rebuild flow.
1199 enum ice_status ice_reset(struct ice_hw *hw, enum ice_reset_req req)
1205 return ice_pf_reset(hw);
1206 case ICE_RESET_CORER:
1207 ice_debug(hw, ICE_DBG_INIT, "CoreR requested\n");
1208 val = GLGEN_RTRIG_CORER_M;
1210 case ICE_RESET_GLOBR:
1211 ice_debug(hw, ICE_DBG_INIT, "GlobalR requested\n");
1212 val = GLGEN_RTRIG_GLOBR_M;
1215 return ICE_ERR_PARAM;
1218 val |= rd32(hw, GLGEN_RTRIG);
1219 wr32(hw, GLGEN_RTRIG, val);
1222 /* wait for the FW to be ready */
1223 return ice_check_reset(hw);
1227 * ice_copy_rxq_ctx_to_hw
1228 * @hw: pointer to the hardware structure
1229 * @ice_rxq_ctx: pointer to the rxq context
1230 * @rxq_index: the index of the Rx queue
1232 * Copies rxq context from dense structure to HW register space
1234 static enum ice_status
1235 ice_copy_rxq_ctx_to_hw(struct ice_hw *hw, u8 *ice_rxq_ctx, u32 rxq_index)
1240 return ICE_ERR_BAD_PTR;
1242 if (rxq_index > QRX_CTRL_MAX_INDEX)
1243 return ICE_ERR_PARAM;
1245 /* Copy each dword separately to HW */
1246 for (i = 0; i < ICE_RXQ_CTX_SIZE_DWORDS; i++) {
1247 wr32(hw, QRX_CONTEXT(i, rxq_index),
1248 *((u32 *)(ice_rxq_ctx + (i * sizeof(u32)))));
1250 ice_debug(hw, ICE_DBG_QCTX, "qrxdata[%d]: %08X\n", i,
1251 *((u32 *)(ice_rxq_ctx + (i * sizeof(u32)))));
1257 /* LAN Rx Queue Context */
1258 static const struct ice_ctx_ele ice_rlan_ctx_info[] = {
1259 /* Field Width LSB */
1260 ICE_CTX_STORE(ice_rlan_ctx, head, 13, 0),
1261 ICE_CTX_STORE(ice_rlan_ctx, cpuid, 8, 13),
1262 ICE_CTX_STORE(ice_rlan_ctx, base, 57, 32),
1263 ICE_CTX_STORE(ice_rlan_ctx, qlen, 13, 89),
1264 ICE_CTX_STORE(ice_rlan_ctx, dbuf, 7, 102),
1265 ICE_CTX_STORE(ice_rlan_ctx, hbuf, 5, 109),
1266 ICE_CTX_STORE(ice_rlan_ctx, dtype, 2, 114),
1267 ICE_CTX_STORE(ice_rlan_ctx, dsize, 1, 116),
1268 ICE_CTX_STORE(ice_rlan_ctx, crcstrip, 1, 117),
1269 ICE_CTX_STORE(ice_rlan_ctx, l2tsel, 1, 119),
1270 ICE_CTX_STORE(ice_rlan_ctx, hsplit_0, 4, 120),
1271 ICE_CTX_STORE(ice_rlan_ctx, hsplit_1, 2, 124),
1272 ICE_CTX_STORE(ice_rlan_ctx, showiv, 1, 127),
1273 ICE_CTX_STORE(ice_rlan_ctx, rxmax, 14, 174),
1274 ICE_CTX_STORE(ice_rlan_ctx, tphrdesc_ena, 1, 193),
1275 ICE_CTX_STORE(ice_rlan_ctx, tphwdesc_ena, 1, 194),
1276 ICE_CTX_STORE(ice_rlan_ctx, tphdata_ena, 1, 195),
1277 ICE_CTX_STORE(ice_rlan_ctx, tphhead_ena, 1, 196),
1278 ICE_CTX_STORE(ice_rlan_ctx, lrxqthresh, 3, 198),
1279 ICE_CTX_STORE(ice_rlan_ctx, prefena, 1, 201),
1285 * @hw: pointer to the hardware structure
1286 * @rlan_ctx: pointer to the rxq context
1287 * @rxq_index: the index of the Rx queue
1289 * Converts rxq context from sparse to dense structure and then writes
1290 * it to HW register space and enables the hardware to prefetch descriptors
1291 * instead of only fetching them on demand
1294 ice_write_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx,
1297 u8 ctx_buf[ICE_RXQ_CTX_SZ] = { 0 };
1300 return ICE_ERR_BAD_PTR;
1302 rlan_ctx->prefena = 1;
1304 ice_set_ctx(hw, (u8 *)rlan_ctx, ctx_buf, ice_rlan_ctx_info);
1305 return ice_copy_rxq_ctx_to_hw(hw, ctx_buf, rxq_index);
1310 * @hw: pointer to the hardware structure
1311 * @rxq_index: the index of the Rx queue to clear
1313 * Clears rxq context in HW register space
1315 enum ice_status ice_clear_rxq_ctx(struct ice_hw *hw, u32 rxq_index)
1319 if (rxq_index > QRX_CTRL_MAX_INDEX)
1320 return ICE_ERR_PARAM;
1322 /* Clear each dword register separately */
1323 for (i = 0; i < ICE_RXQ_CTX_SIZE_DWORDS; i++)
1324 wr32(hw, QRX_CONTEXT(i, rxq_index), 0);
1329 /* LAN Tx Queue Context */
1330 const struct ice_ctx_ele ice_tlan_ctx_info[] = {
1331 /* Field Width LSB */
1332 ICE_CTX_STORE(ice_tlan_ctx, base, 57, 0),
1333 ICE_CTX_STORE(ice_tlan_ctx, port_num, 3, 57),
1334 ICE_CTX_STORE(ice_tlan_ctx, cgd_num, 5, 60),
1335 ICE_CTX_STORE(ice_tlan_ctx, pf_num, 3, 65),
1336 ICE_CTX_STORE(ice_tlan_ctx, vmvf_num, 10, 68),
1337 ICE_CTX_STORE(ice_tlan_ctx, vmvf_type, 2, 78),
1338 ICE_CTX_STORE(ice_tlan_ctx, src_vsi, 10, 80),
1339 ICE_CTX_STORE(ice_tlan_ctx, tsyn_ena, 1, 90),
1340 ICE_CTX_STORE(ice_tlan_ctx, internal_usage_flag, 1, 91),
1341 ICE_CTX_STORE(ice_tlan_ctx, alt_vlan, 1, 92),
1342 ICE_CTX_STORE(ice_tlan_ctx, cpuid, 8, 93),
1343 ICE_CTX_STORE(ice_tlan_ctx, wb_mode, 1, 101),
1344 ICE_CTX_STORE(ice_tlan_ctx, tphrd_desc, 1, 102),
1345 ICE_CTX_STORE(ice_tlan_ctx, tphrd, 1, 103),
1346 ICE_CTX_STORE(ice_tlan_ctx, tphwr_desc, 1, 104),
1347 ICE_CTX_STORE(ice_tlan_ctx, cmpq_id, 9, 105),
1348 ICE_CTX_STORE(ice_tlan_ctx, qnum_in_func, 14, 114),
1349 ICE_CTX_STORE(ice_tlan_ctx, itr_notification_mode, 1, 128),
1350 ICE_CTX_STORE(ice_tlan_ctx, adjust_prof_id, 6, 129),
1351 ICE_CTX_STORE(ice_tlan_ctx, qlen, 13, 135),
1352 ICE_CTX_STORE(ice_tlan_ctx, quanta_prof_idx, 4, 148),
1353 ICE_CTX_STORE(ice_tlan_ctx, tso_ena, 1, 152),
1354 ICE_CTX_STORE(ice_tlan_ctx, tso_qnum, 11, 153),
1355 ICE_CTX_STORE(ice_tlan_ctx, legacy_int, 1, 164),
1356 ICE_CTX_STORE(ice_tlan_ctx, drop_ena, 1, 165),
1357 ICE_CTX_STORE(ice_tlan_ctx, cache_prof_idx, 2, 166),
1358 ICE_CTX_STORE(ice_tlan_ctx, pkt_shaper_prof_idx, 3, 168),
1359 ICE_CTX_STORE(ice_tlan_ctx, int_q_state, 122, 171),
1364 * ice_copy_tx_cmpltnq_ctx_to_hw
1365 * @hw: pointer to the hardware structure
1366 * @ice_tx_cmpltnq_ctx: pointer to the Tx completion queue context
1367 * @tx_cmpltnq_index: the index of the completion queue
1369 * Copies Tx completion queue context from dense structure to HW register space
1371 static enum ice_status
1372 ice_copy_tx_cmpltnq_ctx_to_hw(struct ice_hw *hw, u8 *ice_tx_cmpltnq_ctx,
1373 u32 tx_cmpltnq_index)
1377 if (!ice_tx_cmpltnq_ctx)
1378 return ICE_ERR_BAD_PTR;
1380 if (tx_cmpltnq_index > GLTCLAN_CQ_CNTX0_MAX_INDEX)
1381 return ICE_ERR_PARAM;
1383 /* Copy each dword separately to HW */
1384 for (i = 0; i < ICE_TX_CMPLTNQ_CTX_SIZE_DWORDS; i++) {
1385 wr32(hw, GLTCLAN_CQ_CNTX(i, tx_cmpltnq_index),
1386 *((u32 *)(ice_tx_cmpltnq_ctx + (i * sizeof(u32)))));
1388 ice_debug(hw, ICE_DBG_QCTX, "cmpltnqdata[%d]: %08X\n", i,
1389 *((u32 *)(ice_tx_cmpltnq_ctx + (i * sizeof(u32)))));
1395 /* LAN Tx Completion Queue Context */
1396 static const struct ice_ctx_ele ice_tx_cmpltnq_ctx_info[] = {
1397 /* Field Width LSB */
1398 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, base, 57, 0),
1399 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, q_len, 18, 64),
1400 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, generation, 1, 96),
1401 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, wrt_ptr, 22, 97),
1402 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, pf_num, 3, 128),
1403 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, vmvf_num, 10, 131),
1404 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, vmvf_type, 2, 141),
1405 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, tph_desc_wr, 1, 160),
1406 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, cpuid, 8, 161),
1407 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, cmpltn_cache, 512, 192),
1412 * ice_write_tx_cmpltnq_ctx
1413 * @hw: pointer to the hardware structure
1414 * @tx_cmpltnq_ctx: pointer to the completion queue context
1415 * @tx_cmpltnq_index: the index of the completion queue
1417 * Converts completion queue context from sparse to dense structure and then
1418 * writes it to HW register space
1421 ice_write_tx_cmpltnq_ctx(struct ice_hw *hw,
1422 struct ice_tx_cmpltnq_ctx *tx_cmpltnq_ctx,
1423 u32 tx_cmpltnq_index)
1425 u8 ctx_buf[ICE_TX_CMPLTNQ_CTX_SIZE_DWORDS * sizeof(u32)] = { 0 };
1427 ice_set_ctx(hw, (u8 *)tx_cmpltnq_ctx, ctx_buf, ice_tx_cmpltnq_ctx_info);
1428 return ice_copy_tx_cmpltnq_ctx_to_hw(hw, ctx_buf, tx_cmpltnq_index);
1432 * ice_clear_tx_cmpltnq_ctx
1433 * @hw: pointer to the hardware structure
1434 * @tx_cmpltnq_index: the index of the completion queue to clear
1436 * Clears Tx completion queue context in HW register space
1439 ice_clear_tx_cmpltnq_ctx(struct ice_hw *hw, u32 tx_cmpltnq_index)
1443 if (tx_cmpltnq_index > GLTCLAN_CQ_CNTX0_MAX_INDEX)
1444 return ICE_ERR_PARAM;
1446 /* Clear each dword register separately */
1447 for (i = 0; i < ICE_TX_CMPLTNQ_CTX_SIZE_DWORDS; i++)
1448 wr32(hw, GLTCLAN_CQ_CNTX(i, tx_cmpltnq_index), 0);
1454 * ice_copy_tx_drbell_q_ctx_to_hw
1455 * @hw: pointer to the hardware structure
1456 * @ice_tx_drbell_q_ctx: pointer to the doorbell queue context
1457 * @tx_drbell_q_index: the index of the doorbell queue
1459 * Copies doorbell queue context from dense structure to HW register space
1461 static enum ice_status
1462 ice_copy_tx_drbell_q_ctx_to_hw(struct ice_hw *hw, u8 *ice_tx_drbell_q_ctx,
1463 u32 tx_drbell_q_index)
1467 if (!ice_tx_drbell_q_ctx)
1468 return ICE_ERR_BAD_PTR;
1470 if (tx_drbell_q_index > QTX_COMM_DBLQ_DBELL_MAX_INDEX)
1471 return ICE_ERR_PARAM;
1473 /* Copy each dword separately to HW */
1474 for (i = 0; i < ICE_TX_DRBELL_Q_CTX_SIZE_DWORDS; i++) {
1475 wr32(hw, QTX_COMM_DBLQ_CNTX(i, tx_drbell_q_index),
1476 *((u32 *)(ice_tx_drbell_q_ctx + (i * sizeof(u32)))));
1478 ice_debug(hw, ICE_DBG_QCTX, "tx_drbell_qdata[%d]: %08X\n", i,
1479 *((u32 *)(ice_tx_drbell_q_ctx + (i * sizeof(u32)))));
1485 /* LAN Tx Doorbell Queue Context info */
1486 static const struct ice_ctx_ele ice_tx_drbell_q_ctx_info[] = {
1487 /* Field Width LSB */
1488 ICE_CTX_STORE(ice_tx_drbell_q_ctx, base, 57, 0),
1489 ICE_CTX_STORE(ice_tx_drbell_q_ctx, ring_len, 13, 64),
1490 ICE_CTX_STORE(ice_tx_drbell_q_ctx, pf_num, 3, 80),
1491 ICE_CTX_STORE(ice_tx_drbell_q_ctx, vf_num, 8, 84),
1492 ICE_CTX_STORE(ice_tx_drbell_q_ctx, vmvf_type, 2, 94),
1493 ICE_CTX_STORE(ice_tx_drbell_q_ctx, cpuid, 8, 96),
1494 ICE_CTX_STORE(ice_tx_drbell_q_ctx, tph_desc_rd, 1, 104),
1495 ICE_CTX_STORE(ice_tx_drbell_q_ctx, tph_desc_wr, 1, 108),
1496 ICE_CTX_STORE(ice_tx_drbell_q_ctx, db_q_en, 1, 112),
1497 ICE_CTX_STORE(ice_tx_drbell_q_ctx, rd_head, 13, 128),
1498 ICE_CTX_STORE(ice_tx_drbell_q_ctx, rd_tail, 13, 144),
1503 * ice_write_tx_drbell_q_ctx
1504 * @hw: pointer to the hardware structure
1505 * @tx_drbell_q_ctx: pointer to the doorbell queue context
1506 * @tx_drbell_q_index: the index of the doorbell queue
1508 * Converts doorbell queue context from sparse to dense structure and then
1509 * writes it to HW register space
1512 ice_write_tx_drbell_q_ctx(struct ice_hw *hw,
1513 struct ice_tx_drbell_q_ctx *tx_drbell_q_ctx,
1514 u32 tx_drbell_q_index)
1516 u8 ctx_buf[ICE_TX_DRBELL_Q_CTX_SIZE_DWORDS * sizeof(u32)] = { 0 };
1518 ice_set_ctx(hw, (u8 *)tx_drbell_q_ctx, ctx_buf,
1519 ice_tx_drbell_q_ctx_info);
1520 return ice_copy_tx_drbell_q_ctx_to_hw(hw, ctx_buf, tx_drbell_q_index);
1524 * ice_clear_tx_drbell_q_ctx
1525 * @hw: pointer to the hardware structure
1526 * @tx_drbell_q_index: the index of the doorbell queue to clear
1528 * Clears doorbell queue context in HW register space
1531 ice_clear_tx_drbell_q_ctx(struct ice_hw *hw, u32 tx_drbell_q_index)
1535 if (tx_drbell_q_index > QTX_COMM_DBLQ_DBELL_MAX_INDEX)
1536 return ICE_ERR_PARAM;
1538 /* Clear each dword register separately */
1539 for (i = 0; i < ICE_TX_DRBELL_Q_CTX_SIZE_DWORDS; i++)
1540 wr32(hw, QTX_COMM_DBLQ_CNTX(i, tx_drbell_q_index), 0);
1545 /* Sideband Queue command wrappers */
1548 * ice_get_sbq - returns the right control queue to use for sideband
1549 * @hw: pointer to the hardware structure
1551 static struct ice_ctl_q_info *ice_get_sbq(struct ice_hw *hw)
1553 if (!ice_is_generic_mac(hw))
1559 * ice_sbq_send_cmd - send Sideband Queue command to Sideband Queue
1560 * @hw: pointer to the HW struct
1561 * @desc: descriptor describing the command
1562 * @buf: buffer to use for indirect commands (NULL for direct commands)
1563 * @buf_size: size of buffer for indirect commands (0 for direct commands)
1564 * @cd: pointer to command details structure
1566 static enum ice_status
1567 ice_sbq_send_cmd(struct ice_hw *hw, struct ice_sbq_cmd_desc *desc,
1568 void *buf, u16 buf_size, struct ice_sq_cd *cd)
1570 return ice_sq_send_cmd(hw, ice_get_sbq(hw), (struct ice_aq_desc *)desc,
1575 * ice_sbq_send_cmd_nolock - send Sideband Queue command to Sideband Queue
1576 * but do not lock sq_lock
1577 * @hw: pointer to the HW struct
1578 * @desc: descriptor describing the command
1579 * @buf: buffer to use for indirect commands (NULL for direct commands)
1580 * @buf_size: size of buffer for indirect commands (0 for direct commands)
1581 * @cd: pointer to command details structure
1583 static enum ice_status
1584 ice_sbq_send_cmd_nolock(struct ice_hw *hw, struct ice_sbq_cmd_desc *desc,
1585 void *buf, u16 buf_size, struct ice_sq_cd *cd)
1587 return ice_sq_send_cmd_nolock(hw, ice_get_sbq(hw),
1588 (struct ice_aq_desc *)desc, buf,
1593 * ice_sbq_rw_reg_lp - Fill Sideband Queue command, with lock parameter
1594 * @hw: pointer to the HW struct
1595 * @in: message info to be filled in descriptor
1596 * @lock: true to lock the sq_lock (the usual case); false if the sq_lock has
1597 * already been locked at a higher level
1599 enum ice_status ice_sbq_rw_reg_lp(struct ice_hw *hw,
1600 struct ice_sbq_msg_input *in, bool lock)
1602 struct ice_sbq_cmd_desc desc = {0};
1603 struct ice_sbq_msg_req msg = {0};
1604 enum ice_status status;
1607 msg_len = sizeof(msg);
1609 msg.dest_dev = in->dest_dev;
1610 msg.opcode = in->opcode;
1611 msg.flags = ICE_SBQ_MSG_FLAGS;
1612 msg.sbe_fbe = ICE_SBQ_MSG_SBE_FBE;
1613 msg.msg_addr_low = CPU_TO_LE16(in->msg_addr_low);
1614 msg.msg_addr_high = CPU_TO_LE32(in->msg_addr_high);
1617 msg.data = CPU_TO_LE32(in->data);
1619 /* data read comes back in completion, so shorten the struct by
1622 msg_len -= sizeof(msg.data);
1624 desc.flags = CPU_TO_LE16(ICE_AQ_FLAG_RD);
1625 desc.opcode = CPU_TO_LE16(ice_sbq_opc_neigh_dev_req);
1626 desc.param0.cmd_len = CPU_TO_LE16(msg_len);
1628 status = ice_sbq_send_cmd(hw, &desc, &msg, msg_len, NULL);
1630 status = ice_sbq_send_cmd_nolock(hw, &desc, &msg, msg_len,
1632 if (!status && !in->opcode)
1633 in->data = LE32_TO_CPU
1634 (((struct ice_sbq_msg_cmpl *)&msg)->data);
1639 * ice_sbq_rw_reg - Fill Sideband Queue command
1640 * @hw: pointer to the HW struct
1641 * @in: message info to be filled in descriptor
1643 enum ice_status ice_sbq_rw_reg(struct ice_hw *hw, struct ice_sbq_msg_input *in)
1645 return ice_sbq_rw_reg_lp(hw, in, true);
1649 * ice_sbq_lock - Lock the sideband queue's sq_lock
1650 * @hw: pointer to the HW struct
1652 void ice_sbq_lock(struct ice_hw *hw)
1654 ice_acquire_lock(&ice_get_sbq(hw)->sq_lock);
1658 * ice_sbq_unlock - Unlock the sideband queue's sq_lock
1659 * @hw: pointer to the HW struct
1661 void ice_sbq_unlock(struct ice_hw *hw)
1663 ice_release_lock(&ice_get_sbq(hw)->sq_lock);
1666 /* FW Admin Queue command wrappers */
1669 * ice_should_retry_sq_send_cmd
1670 * @opcode: AQ opcode
1672 * Decide if we should retry the send command routine for the ATQ, depending
1675 static bool ice_should_retry_sq_send_cmd(u16 opcode)
1678 case ice_aqc_opc_get_link_topo:
1679 case ice_aqc_opc_lldp_stop:
1680 case ice_aqc_opc_lldp_start:
1681 case ice_aqc_opc_lldp_filter_ctrl:
1689 * ice_sq_send_cmd_retry - send command to Control Queue (ATQ)
1690 * @hw: pointer to the HW struct
1691 * @cq: pointer to the specific Control queue
1692 * @desc: prefilled descriptor describing the command
1693 * @buf: buffer to use for indirect commands (or NULL for direct commands)
1694 * @buf_size: size of buffer for indirect commands (or 0 for direct commands)
1695 * @cd: pointer to command details structure
1697 * Retry sending the FW Admin Queue command, multiple times, to the FW Admin
1698 * Queue if the EBUSY AQ error is returned.
1700 static enum ice_status
1701 ice_sq_send_cmd_retry(struct ice_hw *hw, struct ice_ctl_q_info *cq,
1702 struct ice_aq_desc *desc, void *buf, u16 buf_size,
1703 struct ice_sq_cd *cd)
1705 struct ice_aq_desc desc_cpy;
1706 enum ice_status status;
1707 bool is_cmd_for_retry;
1712 opcode = LE16_TO_CPU(desc->opcode);
1713 is_cmd_for_retry = ice_should_retry_sq_send_cmd(opcode);
1714 ice_memset(&desc_cpy, 0, sizeof(desc_cpy), ICE_NONDMA_MEM);
1716 if (is_cmd_for_retry) {
1718 buf_cpy = (u8 *)ice_malloc(hw, buf_size);
1720 return ICE_ERR_NO_MEMORY;
1723 ice_memcpy(&desc_cpy, desc, sizeof(desc_cpy),
1724 ICE_NONDMA_TO_NONDMA);
1728 status = ice_sq_send_cmd(hw, cq, desc, buf, buf_size, cd);
1730 if (!is_cmd_for_retry || status == ICE_SUCCESS ||
1731 hw->adminq.sq_last_status != ICE_AQ_RC_EBUSY)
1735 ice_memcpy(buf, buf_cpy, buf_size,
1736 ICE_NONDMA_TO_NONDMA);
1738 ice_memcpy(desc, &desc_cpy, sizeof(desc_cpy),
1739 ICE_NONDMA_TO_NONDMA);
1741 ice_msec_delay(ICE_SQ_SEND_DELAY_TIME_MS, false);
1743 } while (++idx < ICE_SQ_SEND_MAX_EXECUTE);
1746 ice_free(hw, buf_cpy);
1752 * ice_aq_send_cmd - send FW Admin Queue command to FW Admin Queue
1753 * @hw: pointer to the HW struct
1754 * @desc: descriptor describing the command
1755 * @buf: buffer to use for indirect commands (NULL for direct commands)
1756 * @buf_size: size of buffer for indirect commands (0 for direct commands)
1757 * @cd: pointer to command details structure
1759 * Helper function to send FW Admin Queue commands to the FW Admin Queue.
1762 ice_aq_send_cmd(struct ice_hw *hw, struct ice_aq_desc *desc, void *buf,
1763 u16 buf_size, struct ice_sq_cd *cd)
1765 if (hw->aq_send_cmd_fn) {
1766 enum ice_status status = ICE_ERR_NOT_READY;
1767 u16 retval = ICE_AQ_RC_OK;
1769 ice_acquire_lock(&hw->adminq.sq_lock);
1770 if (!hw->aq_send_cmd_fn(hw->aq_send_cmd_param, desc,
1772 retval = LE16_TO_CPU(desc->retval);
1773 /* strip off FW internal code */
1776 if (retval == ICE_AQ_RC_OK)
1777 status = ICE_SUCCESS;
1779 status = ICE_ERR_AQ_ERROR;
1782 hw->adminq.sq_last_status = (enum ice_aq_err)retval;
1783 ice_release_lock(&hw->adminq.sq_lock);
1787 return ice_sq_send_cmd_retry(hw, &hw->adminq, desc, buf, buf_size, cd);
1792 * @hw: pointer to the HW struct
1793 * @cd: pointer to command details structure or NULL
1795 * Get the firmware version (0x0001) from the admin queue commands
1797 enum ice_status ice_aq_get_fw_ver(struct ice_hw *hw, struct ice_sq_cd *cd)
1799 struct ice_aqc_get_ver *resp;
1800 struct ice_aq_desc desc;
1801 enum ice_status status;
1803 resp = &desc.params.get_ver;
1805 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_ver);
1807 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
1810 hw->fw_branch = resp->fw_branch;
1811 hw->fw_maj_ver = resp->fw_major;
1812 hw->fw_min_ver = resp->fw_minor;
1813 hw->fw_patch = resp->fw_patch;
1814 hw->fw_build = LE32_TO_CPU(resp->fw_build);
1815 hw->api_branch = resp->api_branch;
1816 hw->api_maj_ver = resp->api_major;
1817 hw->api_min_ver = resp->api_minor;
1818 hw->api_patch = resp->api_patch;
1825 * ice_aq_send_driver_ver
1826 * @hw: pointer to the HW struct
1827 * @dv: driver's major, minor version
1828 * @cd: pointer to command details structure or NULL
1830 * Send the driver version (0x0002) to the firmware
1833 ice_aq_send_driver_ver(struct ice_hw *hw, struct ice_driver_ver *dv,
1834 struct ice_sq_cd *cd)
1836 struct ice_aqc_driver_ver *cmd;
1837 struct ice_aq_desc desc;
1840 cmd = &desc.params.driver_ver;
1843 return ICE_ERR_PARAM;
1845 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_driver_ver);
1847 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
1848 cmd->major_ver = dv->major_ver;
1849 cmd->minor_ver = dv->minor_ver;
1850 cmd->build_ver = dv->build_ver;
1851 cmd->subbuild_ver = dv->subbuild_ver;
1854 while (len < sizeof(dv->driver_string) &&
1855 IS_ASCII(dv->driver_string[len]) && dv->driver_string[len])
1858 return ice_aq_send_cmd(hw, &desc, dv->driver_string, len, cd);
1863 * @hw: pointer to the HW struct
1864 * @unloading: is the driver unloading itself
1866 * Tell the Firmware that we're shutting down the AdminQ and whether
1867 * or not the driver is unloading as well (0x0003).
1869 enum ice_status ice_aq_q_shutdown(struct ice_hw *hw, bool unloading)
1871 struct ice_aqc_q_shutdown *cmd;
1872 struct ice_aq_desc desc;
1874 cmd = &desc.params.q_shutdown;
1876 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_q_shutdown);
1879 cmd->driver_unloading = ICE_AQC_DRIVER_UNLOADING;
1881 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
1886 * @hw: pointer to the HW struct
1888 * @access: access type
1889 * @sdp_number: resource number
1890 * @timeout: the maximum time in ms that the driver may hold the resource
1891 * @cd: pointer to command details structure or NULL
1893 * Requests common resource using the admin queue commands (0x0008).
1894 * When attempting to acquire the Global Config Lock, the driver can
1895 * learn of three states:
1896 * 1) ICE_SUCCESS - acquired lock, and can perform download package
1897 * 2) ICE_ERR_AQ_ERROR - did not get lock, driver should fail to load
1898 * 3) ICE_ERR_AQ_NO_WORK - did not get lock, but another driver has
1899 * successfully downloaded the package; the driver does
1900 * not have to download the package and can continue
1903 * Note that if the caller is in an acquire lock, perform action, release lock
1904 * phase of operation, it is possible that the FW may detect a timeout and issue
1905 * a CORER. In this case, the driver will receive a CORER interrupt and will
1906 * have to determine its cause. The calling thread that is handling this flow
1907 * will likely get an error propagated back to it indicating the Download
1908 * Package, Update Package or the Release Resource AQ commands timed out.
1910 static enum ice_status
1911 ice_aq_req_res(struct ice_hw *hw, enum ice_aq_res_ids res,
1912 enum ice_aq_res_access_type access, u8 sdp_number, u32 *timeout,
1913 struct ice_sq_cd *cd)
1915 struct ice_aqc_req_res *cmd_resp;
1916 struct ice_aq_desc desc;
1917 enum ice_status status;
1919 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
1921 cmd_resp = &desc.params.res_owner;
1923 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_req_res);
1925 cmd_resp->res_id = CPU_TO_LE16(res);
1926 cmd_resp->access_type = CPU_TO_LE16(access);
1927 cmd_resp->res_number = CPU_TO_LE32(sdp_number);
1928 cmd_resp->timeout = CPU_TO_LE32(*timeout);
1931 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
1933 /* The completion specifies the maximum time in ms that the driver
1934 * may hold the resource in the Timeout field.
1937 /* Global config lock response utilizes an additional status field.
1939 * If the Global config lock resource is held by some other driver, the
1940 * command completes with ICE_AQ_RES_GLBL_IN_PROG in the status field
1941 * and the timeout field indicates the maximum time the current owner
1942 * of the resource has to free it.
1944 if (res == ICE_GLOBAL_CFG_LOCK_RES_ID) {
1945 if (LE16_TO_CPU(cmd_resp->status) == ICE_AQ_RES_GLBL_SUCCESS) {
1946 *timeout = LE32_TO_CPU(cmd_resp->timeout);
1948 } else if (LE16_TO_CPU(cmd_resp->status) ==
1949 ICE_AQ_RES_GLBL_IN_PROG) {
1950 *timeout = LE32_TO_CPU(cmd_resp->timeout);
1951 return ICE_ERR_AQ_ERROR;
1952 } else if (LE16_TO_CPU(cmd_resp->status) ==
1953 ICE_AQ_RES_GLBL_DONE) {
1954 return ICE_ERR_AQ_NO_WORK;
1957 /* invalid FW response, force a timeout immediately */
1959 return ICE_ERR_AQ_ERROR;
1962 /* If the resource is held by some other driver, the command completes
1963 * with a busy return value and the timeout field indicates the maximum
1964 * time the current owner of the resource has to free it.
1966 if (!status || hw->adminq.sq_last_status == ICE_AQ_RC_EBUSY)
1967 *timeout = LE32_TO_CPU(cmd_resp->timeout);
1973 * ice_aq_release_res
1974 * @hw: pointer to the HW struct
1976 * @sdp_number: resource number
1977 * @cd: pointer to command details structure or NULL
1979 * release common resource using the admin queue commands (0x0009)
1981 static enum ice_status
1982 ice_aq_release_res(struct ice_hw *hw, enum ice_aq_res_ids res, u8 sdp_number,
1983 struct ice_sq_cd *cd)
1985 struct ice_aqc_req_res *cmd;
1986 struct ice_aq_desc desc;
1988 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
1990 cmd = &desc.params.res_owner;
1992 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_release_res);
1994 cmd->res_id = CPU_TO_LE16(res);
1995 cmd->res_number = CPU_TO_LE32(sdp_number);
1997 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
2002 * @hw: pointer to the HW structure
2004 * @access: access type (read or write)
2005 * @timeout: timeout in milliseconds
2007 * This function will attempt to acquire the ownership of a resource.
2010 ice_acquire_res(struct ice_hw *hw, enum ice_aq_res_ids res,
2011 enum ice_aq_res_access_type access, u32 timeout)
2013 #define ICE_RES_POLLING_DELAY_MS 10
2014 u32 delay = ICE_RES_POLLING_DELAY_MS;
2015 u32 time_left = timeout;
2016 enum ice_status status;
2018 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
2020 status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL);
2022 /* A return code of ICE_ERR_AQ_NO_WORK means that another driver has
2023 * previously acquired the resource and performed any necessary updates;
2024 * in this case the caller does not obtain the resource and has no
2025 * further work to do.
2027 if (status == ICE_ERR_AQ_NO_WORK)
2028 goto ice_acquire_res_exit;
2031 ice_debug(hw, ICE_DBG_RES, "resource %d acquire type %d failed.\n", res, access);
2033 /* If necessary, poll until the current lock owner timeouts */
2034 timeout = time_left;
2035 while (status && timeout && time_left) {
2036 ice_msec_delay(delay, true);
2037 timeout = (timeout > delay) ? timeout - delay : 0;
2038 status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL);
2040 if (status == ICE_ERR_AQ_NO_WORK)
2041 /* lock free, but no work to do */
2048 if (status && status != ICE_ERR_AQ_NO_WORK)
2049 ice_debug(hw, ICE_DBG_RES, "resource acquire timed out.\n");
2051 ice_acquire_res_exit:
2052 if (status == ICE_ERR_AQ_NO_WORK) {
2053 if (access == ICE_RES_WRITE)
2054 ice_debug(hw, ICE_DBG_RES, "resource indicates no work to do.\n");
2056 ice_debug(hw, ICE_DBG_RES, "Warning: ICE_ERR_AQ_NO_WORK not expected\n");
2063 * @hw: pointer to the HW structure
2066 * This function will release a resource using the proper Admin Command.
2068 void ice_release_res(struct ice_hw *hw, enum ice_aq_res_ids res)
2070 enum ice_status status;
2071 u32 total_delay = 0;
2073 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
2075 status = ice_aq_release_res(hw, res, 0, NULL);
2077 /* there are some rare cases when trying to release the resource
2078 * results in an admin queue timeout, so handle them correctly
2080 while ((status == ICE_ERR_AQ_TIMEOUT) &&
2081 (total_delay < hw->adminq.sq_cmd_timeout)) {
2082 ice_msec_delay(1, true);
2083 status = ice_aq_release_res(hw, res, 0, NULL);
2089 * ice_aq_alloc_free_res - command to allocate/free resources
2090 * @hw: pointer to the HW struct
2091 * @num_entries: number of resource entries in buffer
2092 * @buf: Indirect buffer to hold data parameters and response
2093 * @buf_size: size of buffer for indirect commands
2094 * @opc: pass in the command opcode
2095 * @cd: pointer to command details structure or NULL
2097 * Helper function to allocate/free resources using the admin queue commands
2100 ice_aq_alloc_free_res(struct ice_hw *hw, u16 num_entries,
2101 struct ice_aqc_alloc_free_res_elem *buf, u16 buf_size,
2102 enum ice_adminq_opc opc, struct ice_sq_cd *cd)
2104 struct ice_aqc_alloc_free_res_cmd *cmd;
2105 struct ice_aq_desc desc;
2107 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
2109 cmd = &desc.params.sw_res_ctrl;
2112 return ICE_ERR_PARAM;
2114 if (buf_size < FLEX_ARRAY_SIZE(buf, elem, num_entries))
2115 return ICE_ERR_PARAM;
2117 ice_fill_dflt_direct_cmd_desc(&desc, opc);
2119 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
2121 cmd->num_entries = CPU_TO_LE16(num_entries);
2123 return ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);
2127 * ice_alloc_hw_res - allocate resource
2128 * @hw: pointer to the HW struct
2129 * @type: type of resource
2130 * @num: number of resources to allocate
2131 * @btm: allocate from bottom
2132 * @res: pointer to array that will receive the resources
2135 ice_alloc_hw_res(struct ice_hw *hw, u16 type, u16 num, bool btm, u16 *res)
2137 struct ice_aqc_alloc_free_res_elem *buf;
2138 enum ice_status status;
2141 buf_len = ice_struct_size(buf, elem, num);
2142 buf = (struct ice_aqc_alloc_free_res_elem *)ice_malloc(hw, buf_len);
2144 return ICE_ERR_NO_MEMORY;
2146 /* Prepare buffer to allocate resource. */
2147 buf->num_elems = CPU_TO_LE16(num);
2148 buf->res_type = CPU_TO_LE16(type | ICE_AQC_RES_TYPE_FLAG_DEDICATED |
2149 ICE_AQC_RES_TYPE_FLAG_IGNORE_INDEX);
2151 buf->res_type |= CPU_TO_LE16(ICE_AQC_RES_TYPE_FLAG_SCAN_BOTTOM);
2153 status = ice_aq_alloc_free_res(hw, 1, buf, buf_len,
2154 ice_aqc_opc_alloc_res, NULL);
2156 goto ice_alloc_res_exit;
2158 ice_memcpy(res, buf->elem, sizeof(*buf->elem) * num,
2159 ICE_NONDMA_TO_NONDMA);
2167 * ice_free_hw_res - free allocated HW resource
2168 * @hw: pointer to the HW struct
2169 * @type: type of resource to free
2170 * @num: number of resources
2171 * @res: pointer to array that contains the resources to free
2173 enum ice_status ice_free_hw_res(struct ice_hw *hw, u16 type, u16 num, u16 *res)
2175 struct ice_aqc_alloc_free_res_elem *buf;
2176 enum ice_status status;
2179 buf_len = ice_struct_size(buf, elem, num);
2180 buf = (struct ice_aqc_alloc_free_res_elem *)ice_malloc(hw, buf_len);
2182 return ICE_ERR_NO_MEMORY;
2184 /* Prepare buffer to free resource. */
2185 buf->num_elems = CPU_TO_LE16(num);
2186 buf->res_type = CPU_TO_LE16(type);
2187 ice_memcpy(buf->elem, res, sizeof(*buf->elem) * num,
2188 ICE_NONDMA_TO_NONDMA);
2190 status = ice_aq_alloc_free_res(hw, num, buf, buf_len,
2191 ice_aqc_opc_free_res, NULL);
2193 ice_debug(hw, ICE_DBG_SW, "CQ CMD Buffer:\n");
2200 * ice_get_num_per_func - determine number of resources per PF
2201 * @hw: pointer to the HW structure
2202 * @max: value to be evenly split between each PF
2204 * Determine the number of valid functions by going through the bitmap returned
2205 * from parsing capabilities and use this to calculate the number of resources
2206 * per PF based on the max value passed in.
2208 static u32 ice_get_num_per_func(struct ice_hw *hw, u32 max)
2212 #define ICE_CAPS_VALID_FUNCS_M 0xFF
2213 funcs = ice_hweight8(hw->dev_caps.common_cap.valid_functions &
2214 ICE_CAPS_VALID_FUNCS_M);
2223 * ice_parse_common_caps - parse common device/function capabilities
2224 * @hw: pointer to the HW struct
2225 * @caps: pointer to common capabilities structure
2226 * @elem: the capability element to parse
2227 * @prefix: message prefix for tracing capabilities
2229 * Given a capability element, extract relevant details into the common
2230 * capability structure.
2232 * Returns: true if the capability matches one of the common capability ids,
2236 ice_parse_common_caps(struct ice_hw *hw, struct ice_hw_common_caps *caps,
2237 struct ice_aqc_list_caps_elem *elem, const char *prefix)
2239 u32 logical_id = LE32_TO_CPU(elem->logical_id);
2240 u32 phys_id = LE32_TO_CPU(elem->phys_id);
2241 u32 number = LE32_TO_CPU(elem->number);
2242 u16 cap = LE16_TO_CPU(elem->cap);
2246 case ICE_AQC_CAPS_VALID_FUNCTIONS:
2247 caps->valid_functions = number;
2248 ice_debug(hw, ICE_DBG_INIT, "%s: valid_functions (bitmap) = %d\n", prefix,
2249 caps->valid_functions);
2251 case ICE_AQC_CAPS_DCB:
2252 caps->dcb = (number == 1);
2253 caps->active_tc_bitmap = logical_id;
2254 caps->maxtc = phys_id;
2255 ice_debug(hw, ICE_DBG_INIT, "%s: dcb = %d\n", prefix, caps->dcb);
2256 ice_debug(hw, ICE_DBG_INIT, "%s: active_tc_bitmap = %d\n", prefix,
2257 caps->active_tc_bitmap);
2258 ice_debug(hw, ICE_DBG_INIT, "%s: maxtc = %d\n", prefix, caps->maxtc);
2260 case ICE_AQC_CAPS_RSS:
2261 caps->rss_table_size = number;
2262 caps->rss_table_entry_width = logical_id;
2263 ice_debug(hw, ICE_DBG_INIT, "%s: rss_table_size = %d\n", prefix,
2264 caps->rss_table_size);
2265 ice_debug(hw, ICE_DBG_INIT, "%s: rss_table_entry_width = %d\n", prefix,
2266 caps->rss_table_entry_width);
2268 case ICE_AQC_CAPS_RXQS:
2269 caps->num_rxq = number;
2270 caps->rxq_first_id = phys_id;
2271 ice_debug(hw, ICE_DBG_INIT, "%s: num_rxq = %d\n", prefix,
2273 ice_debug(hw, ICE_DBG_INIT, "%s: rxq_first_id = %d\n", prefix,
2274 caps->rxq_first_id);
2276 case ICE_AQC_CAPS_TXQS:
2277 caps->num_txq = number;
2278 caps->txq_first_id = phys_id;
2279 ice_debug(hw, ICE_DBG_INIT, "%s: num_txq = %d\n", prefix,
2281 ice_debug(hw, ICE_DBG_INIT, "%s: txq_first_id = %d\n", prefix,
2282 caps->txq_first_id);
2284 case ICE_AQC_CAPS_MSIX:
2285 caps->num_msix_vectors = number;
2286 caps->msix_vector_first_id = phys_id;
2287 ice_debug(hw, ICE_DBG_INIT, "%s: num_msix_vectors = %d\n", prefix,
2288 caps->num_msix_vectors);
2289 ice_debug(hw, ICE_DBG_INIT, "%s: msix_vector_first_id = %d\n", prefix,
2290 caps->msix_vector_first_id);
2292 case ICE_AQC_CAPS_NVM_MGMT:
2293 caps->sec_rev_disabled =
2294 (number & ICE_NVM_MGMT_SEC_REV_DISABLED) ?
2296 ice_debug(hw, ICE_DBG_INIT, "%s: sec_rev_disabled = %d\n", prefix,
2297 caps->sec_rev_disabled);
2298 caps->update_disabled =
2299 (number & ICE_NVM_MGMT_UPDATE_DISABLED) ?
2301 ice_debug(hw, ICE_DBG_INIT, "%s: update_disabled = %d\n", prefix,
2302 caps->update_disabled);
2303 caps->nvm_unified_update =
2304 (number & ICE_NVM_MGMT_UNIFIED_UPD_SUPPORT) ?
2306 ice_debug(hw, ICE_DBG_INIT, "%s: nvm_unified_update = %d\n", prefix,
2307 caps->nvm_unified_update);
2309 case ICE_AQC_CAPS_MAX_MTU:
2310 caps->max_mtu = number;
2311 ice_debug(hw, ICE_DBG_INIT, "%s: max_mtu = %d\n",
2312 prefix, caps->max_mtu);
2314 case ICE_AQC_CAPS_PCIE_RESET_AVOIDANCE:
2315 caps->pcie_reset_avoidance = (number > 0);
2316 ice_debug(hw, ICE_DBG_INIT,
2317 "%s: pcie_reset_avoidance = %d\n", prefix,
2318 caps->pcie_reset_avoidance);
2320 case ICE_AQC_CAPS_POST_UPDATE_RESET_RESTRICT:
2321 caps->reset_restrict_support = (number == 1);
2322 ice_debug(hw, ICE_DBG_INIT,
2323 "%s: reset_restrict_support = %d\n", prefix,
2324 caps->reset_restrict_support);
2326 case ICE_AQC_CAPS_EXT_TOPO_DEV_IMG0:
2327 case ICE_AQC_CAPS_EXT_TOPO_DEV_IMG1:
2328 case ICE_AQC_CAPS_EXT_TOPO_DEV_IMG2:
2329 case ICE_AQC_CAPS_EXT_TOPO_DEV_IMG3:
2331 u8 index = cap - ICE_AQC_CAPS_EXT_TOPO_DEV_IMG0;
2333 caps->ext_topo_dev_img_ver_high[index] = number;
2334 caps->ext_topo_dev_img_ver_low[index] = logical_id;
2335 caps->ext_topo_dev_img_part_num[index] =
2336 (phys_id & ICE_EXT_TOPO_DEV_IMG_PART_NUM_M) >>
2337 ICE_EXT_TOPO_DEV_IMG_PART_NUM_S;
2338 caps->ext_topo_dev_img_load_en[index] =
2339 (phys_id & ICE_EXT_TOPO_DEV_IMG_LOAD_EN) != 0;
2340 caps->ext_topo_dev_img_prog_en[index] =
2341 (phys_id & ICE_EXT_TOPO_DEV_IMG_PROG_EN) != 0;
2342 ice_debug(hw, ICE_DBG_INIT,
2343 "%s: ext_topo_dev_img_ver_high[%d] = %d\n",
2345 caps->ext_topo_dev_img_ver_high[index]);
2346 ice_debug(hw, ICE_DBG_INIT,
2347 "%s: ext_topo_dev_img_ver_low[%d] = %d\n",
2349 caps->ext_topo_dev_img_ver_low[index]);
2350 ice_debug(hw, ICE_DBG_INIT,
2351 "%s: ext_topo_dev_img_part_num[%d] = %d\n",
2353 caps->ext_topo_dev_img_part_num[index]);
2354 ice_debug(hw, ICE_DBG_INIT,
2355 "%s: ext_topo_dev_img_load_en[%d] = %d\n",
2357 caps->ext_topo_dev_img_load_en[index]);
2358 ice_debug(hw, ICE_DBG_INIT,
2359 "%s: ext_topo_dev_img_prog_en[%d] = %d\n",
2361 caps->ext_topo_dev_img_prog_en[index]);
2365 /* Not one of the recognized common capabilities */
2373 * ice_recalc_port_limited_caps - Recalculate port limited capabilities
2374 * @hw: pointer to the HW structure
2375 * @caps: pointer to capabilities structure to fix
2377 * Re-calculate the capabilities that are dependent on the number of physical
2378 * ports; i.e. some features are not supported or function differently on
2379 * devices with more than 4 ports.
2382 ice_recalc_port_limited_caps(struct ice_hw *hw, struct ice_hw_common_caps *caps)
2384 /* This assumes device capabilities are always scanned before function
2385 * capabilities during the initialization flow.
2387 if (hw->dev_caps.num_funcs > 4) {
2388 /* Max 4 TCs per port */
2390 ice_debug(hw, ICE_DBG_INIT, "reducing maxtc to %d (based on #ports)\n",
2396 * ice_parse_vsi_func_caps - Parse ICE_AQC_CAPS_VSI function caps
2397 * @hw: pointer to the HW struct
2398 * @func_p: pointer to function capabilities structure
2399 * @cap: pointer to the capability element to parse
2401 * Extract function capabilities for ICE_AQC_CAPS_VSI.
2404 ice_parse_vsi_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p,
2405 struct ice_aqc_list_caps_elem *cap)
2407 func_p->guar_num_vsi = ice_get_num_per_func(hw, ICE_MAX_VSI);
2408 ice_debug(hw, ICE_DBG_INIT, "func caps: guar_num_vsi (fw) = %d\n",
2409 LE32_TO_CPU(cap->number));
2410 ice_debug(hw, ICE_DBG_INIT, "func caps: guar_num_vsi = %d\n",
2411 func_p->guar_num_vsi);
2415 * ice_parse_1588_func_caps - Parse ICE_AQC_CAPS_1588 function caps
2416 * @hw: pointer to the HW struct
2417 * @func_p: pointer to function capabilities structure
2418 * @cap: pointer to the capability element to parse
2420 * Extract function capabilities for ICE_AQC_CAPS_1588.
2423 ice_parse_1588_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p,
2424 struct ice_aqc_list_caps_elem *cap)
2426 struct ice_ts_func_info *info = &func_p->ts_func_info;
2427 u32 number = LE32_TO_CPU(cap->number);
2429 info->ena = ((number & ICE_TS_FUNC_ENA_M) != 0);
2430 func_p->common_cap.ieee_1588 = info->ena;
2432 info->src_tmr_owned = ((number & ICE_TS_SRC_TMR_OWND_M) != 0);
2433 info->tmr_ena = ((number & ICE_TS_TMR_ENA_M) != 0);
2434 info->tmr_index_owned = ((number & ICE_TS_TMR_IDX_OWND_M) != 0);
2435 info->tmr_index_assoc = ((number & ICE_TS_TMR_IDX_ASSOC_M) != 0);
2437 info->clk_freq = (number & ICE_TS_CLK_FREQ_M) >> ICE_TS_CLK_FREQ_S;
2438 info->clk_src = ((number & ICE_TS_CLK_SRC_M) != 0);
2440 if (info->clk_freq < NUM_ICE_TIME_REF_FREQ) {
2441 info->time_ref = (enum ice_time_ref_freq)info->clk_freq;
2443 /* Unknown clock frequency, so assume a (probably incorrect)
2444 * default to avoid out-of-bounds look ups of frequency
2445 * related information.
2447 ice_debug(hw, ICE_DBG_INIT, "1588 func caps: unknown clock frequency %u\n",
2449 info->time_ref = ICE_TIME_REF_FREQ_25_000;
2452 ice_debug(hw, ICE_DBG_INIT, "func caps: ieee_1588 = %u\n",
2453 func_p->common_cap.ieee_1588);
2454 ice_debug(hw, ICE_DBG_INIT, "func caps: src_tmr_owned = %u\n",
2455 info->src_tmr_owned);
2456 ice_debug(hw, ICE_DBG_INIT, "func caps: tmr_ena = %u\n",
2458 ice_debug(hw, ICE_DBG_INIT, "func caps: tmr_index_owned = %u\n",
2459 info->tmr_index_owned);
2460 ice_debug(hw, ICE_DBG_INIT, "func caps: tmr_index_assoc = %u\n",
2461 info->tmr_index_assoc);
2462 ice_debug(hw, ICE_DBG_INIT, "func caps: clk_freq = %u\n",
2464 ice_debug(hw, ICE_DBG_INIT, "func caps: clk_src = %u\n",
2469 * ice_parse_fdir_func_caps - Parse ICE_AQC_CAPS_FD function caps
2470 * @hw: pointer to the HW struct
2471 * @func_p: pointer to function capabilities structure
2473 * Extract function capabilities for ICE_AQC_CAPS_FD.
2476 ice_parse_fdir_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p)
2480 if (hw->dcf_enabled)
2482 reg_val = rd32(hw, GLQF_FD_SIZE);
2483 val = (reg_val & GLQF_FD_SIZE_FD_GSIZE_M) >>
2484 GLQF_FD_SIZE_FD_GSIZE_S;
2485 func_p->fd_fltr_guar =
2486 ice_get_num_per_func(hw, val);
2487 val = (reg_val & GLQF_FD_SIZE_FD_BSIZE_M) >>
2488 GLQF_FD_SIZE_FD_BSIZE_S;
2489 func_p->fd_fltr_best_effort = val;
2491 ice_debug(hw, ICE_DBG_INIT, "func caps: fd_fltr_guar = %d\n",
2492 func_p->fd_fltr_guar);
2493 ice_debug(hw, ICE_DBG_INIT, "func caps: fd_fltr_best_effort = %d\n",
2494 func_p->fd_fltr_best_effort);
2498 * ice_parse_func_caps - Parse function capabilities
2499 * @hw: pointer to the HW struct
2500 * @func_p: pointer to function capabilities structure
2501 * @buf: buffer containing the function capability records
2502 * @cap_count: the number of capabilities
2504 * Helper function to parse function (0x000A) capabilities list. For
2505 * capabilities shared between device and function, this relies on
2506 * ice_parse_common_caps.
2508 * Loop through the list of provided capabilities and extract the relevant
2509 * data into the function capabilities structured.
2512 ice_parse_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p,
2513 void *buf, u32 cap_count)
2515 struct ice_aqc_list_caps_elem *cap_resp;
2518 cap_resp = (struct ice_aqc_list_caps_elem *)buf;
2520 ice_memset(func_p, 0, sizeof(*func_p), ICE_NONDMA_MEM);
2522 for (i = 0; i < cap_count; i++) {
2523 u16 cap = LE16_TO_CPU(cap_resp[i].cap);
2526 found = ice_parse_common_caps(hw, &func_p->common_cap,
2527 &cap_resp[i], "func caps");
2530 case ICE_AQC_CAPS_VSI:
2531 ice_parse_vsi_func_caps(hw, func_p, &cap_resp[i]);
2533 case ICE_AQC_CAPS_1588:
2534 ice_parse_1588_func_caps(hw, func_p, &cap_resp[i]);
2536 case ICE_AQC_CAPS_FD:
2537 ice_parse_fdir_func_caps(hw, func_p);
2540 /* Don't list common capabilities as unknown */
2542 ice_debug(hw, ICE_DBG_INIT, "func caps: unknown capability[%d]: 0x%x\n",
2548 ice_recalc_port_limited_caps(hw, &func_p->common_cap);
2552 * ice_func_id_to_logical_id - map from function id to logical pf id
2553 * @active_function_bitmap: active function bitmap
2554 * @pf_id: function number of device
2556 static int ice_func_id_to_logical_id(u32 active_function_bitmap, u8 pf_id)
2561 for (i = 0; i < pf_id; i++)
2562 if (active_function_bitmap & BIT(i))
2569 * ice_parse_valid_functions_cap - Parse ICE_AQC_CAPS_VALID_FUNCTIONS caps
2570 * @hw: pointer to the HW struct
2571 * @dev_p: pointer to device capabilities structure
2572 * @cap: capability element to parse
2574 * Parse ICE_AQC_CAPS_VALID_FUNCTIONS for device capabilities.
2577 ice_parse_valid_functions_cap(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p,
2578 struct ice_aqc_list_caps_elem *cap)
2580 u32 number = LE32_TO_CPU(cap->number);
2582 dev_p->num_funcs = ice_hweight32(number);
2583 ice_debug(hw, ICE_DBG_INIT, "dev caps: num_funcs = %d\n",
2586 hw->logical_pf_id = ice_func_id_to_logical_id(number, hw->pf_id);
2590 * ice_parse_vsi_dev_caps - Parse ICE_AQC_CAPS_VSI device caps
2591 * @hw: pointer to the HW struct
2592 * @dev_p: pointer to device capabilities structure
2593 * @cap: capability element to parse
2595 * Parse ICE_AQC_CAPS_VSI for device capabilities.
2598 ice_parse_vsi_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p,
2599 struct ice_aqc_list_caps_elem *cap)
2601 u32 number = LE32_TO_CPU(cap->number);
2603 dev_p->num_vsi_allocd_to_host = number;
2604 ice_debug(hw, ICE_DBG_INIT, "dev caps: num_vsi_allocd_to_host = %d\n",
2605 dev_p->num_vsi_allocd_to_host);
2609 * ice_parse_1588_dev_caps - Parse ICE_AQC_CAPS_1588 device caps
2610 * @hw: pointer to the HW struct
2611 * @dev_p: pointer to device capabilities structure
2612 * @cap: capability element to parse
2614 * Parse ICE_AQC_CAPS_1588 for device capabilities.
2617 ice_parse_1588_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p,
2618 struct ice_aqc_list_caps_elem *cap)
2620 struct ice_ts_dev_info *info = &dev_p->ts_dev_info;
2621 u32 logical_id = LE32_TO_CPU(cap->logical_id);
2622 u32 phys_id = LE32_TO_CPU(cap->phys_id);
2623 u32 number = LE32_TO_CPU(cap->number);
2625 info->ena = ((number & ICE_TS_DEV_ENA_M) != 0);
2626 dev_p->common_cap.ieee_1588 = info->ena;
2628 info->tmr0_owner = number & ICE_TS_TMR0_OWNR_M;
2629 info->tmr0_owned = ((number & ICE_TS_TMR0_OWND_M) != 0);
2630 info->tmr0_ena = ((number & ICE_TS_TMR0_ENA_M) != 0);
2632 info->tmr1_owner = (number & ICE_TS_TMR1_OWNR_M) >> ICE_TS_TMR1_OWNR_S;
2633 info->tmr1_owned = ((number & ICE_TS_TMR1_OWND_M) != 0);
2634 info->tmr1_ena = ((number & ICE_TS_TMR1_ENA_M) != 0);
2636 info->ena_ports = logical_id;
2637 info->tmr_own_map = phys_id;
2639 ice_debug(hw, ICE_DBG_INIT, "dev caps: ieee_1588 = %u\n",
2640 dev_p->common_cap.ieee_1588);
2641 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr0_owner = %u\n",
2643 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr0_owned = %u\n",
2645 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr0_ena = %u\n",
2647 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr1_owner = %u\n",
2649 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr1_owned = %u\n",
2651 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr1_ena = %u\n",
2653 ice_debug(hw, ICE_DBG_INIT, "dev caps: ieee_1588 ena_ports = %u\n",
2655 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr_own_map = %u\n",
2660 * ice_parse_fdir_dev_caps - Parse ICE_AQC_CAPS_FD device caps
2661 * @hw: pointer to the HW struct
2662 * @dev_p: pointer to device capabilities structure
2663 * @cap: capability element to parse
2665 * Parse ICE_AQC_CAPS_FD for device capabilities.
2668 ice_parse_fdir_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p,
2669 struct ice_aqc_list_caps_elem *cap)
2671 u32 number = LE32_TO_CPU(cap->number);
2673 dev_p->num_flow_director_fltr = number;
2674 ice_debug(hw, ICE_DBG_INIT, "dev caps: num_flow_director_fltr = %d\n",
2675 dev_p->num_flow_director_fltr);
2679 * ice_parse_dev_caps - Parse device capabilities
2680 * @hw: pointer to the HW struct
2681 * @dev_p: pointer to device capabilities structure
2682 * @buf: buffer containing the device capability records
2683 * @cap_count: the number of capabilities
2685 * Helper device to parse device (0x000B) capabilities list. For
2686 * capabilities shared between device and function, this relies on
2687 * ice_parse_common_caps.
2689 * Loop through the list of provided capabilities and extract the relevant
2690 * data into the device capabilities structured.
2693 ice_parse_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p,
2694 void *buf, u32 cap_count)
2696 struct ice_aqc_list_caps_elem *cap_resp;
2699 cap_resp = (struct ice_aqc_list_caps_elem *)buf;
2701 ice_memset(dev_p, 0, sizeof(*dev_p), ICE_NONDMA_MEM);
2703 for (i = 0; i < cap_count; i++) {
2704 u16 cap = LE16_TO_CPU(cap_resp[i].cap);
2707 found = ice_parse_common_caps(hw, &dev_p->common_cap,
2708 &cap_resp[i], "dev caps");
2711 case ICE_AQC_CAPS_VALID_FUNCTIONS:
2712 ice_parse_valid_functions_cap(hw, dev_p, &cap_resp[i]);
2714 case ICE_AQC_CAPS_VSI:
2715 ice_parse_vsi_dev_caps(hw, dev_p, &cap_resp[i]);
2717 case ICE_AQC_CAPS_1588:
2718 ice_parse_1588_dev_caps(hw, dev_p, &cap_resp[i]);
2720 case ICE_AQC_CAPS_FD:
2721 ice_parse_fdir_dev_caps(hw, dev_p, &cap_resp[i]);
2724 /* Don't list common capabilities as unknown */
2726 ice_debug(hw, ICE_DBG_INIT, "dev caps: unknown capability[%d]: 0x%x\n",
2732 ice_recalc_port_limited_caps(hw, &dev_p->common_cap);
2736 * ice_aq_list_caps - query function/device capabilities
2737 * @hw: pointer to the HW struct
2738 * @buf: a buffer to hold the capabilities
2739 * @buf_size: size of the buffer
2740 * @cap_count: if not NULL, set to the number of capabilities reported
2741 * @opc: capabilities type to discover, device or function
2742 * @cd: pointer to command details structure or NULL
2744 * Get the function (0x000A) or device (0x000B) capabilities description from
2745 * firmware and store it in the buffer.
2747 * If the cap_count pointer is not NULL, then it is set to the number of
2748 * capabilities firmware will report. Note that if the buffer size is too
2749 * small, it is possible the command will return ICE_AQ_ERR_ENOMEM. The
2750 * cap_count will still be updated in this case. It is recommended that the
2751 * buffer size be set to ICE_AQ_MAX_BUF_LEN (the largest possible buffer that
2752 * firmware could return) to avoid this.
2754 static enum ice_status
2755 ice_aq_list_caps(struct ice_hw *hw, void *buf, u16 buf_size, u32 *cap_count,
2756 enum ice_adminq_opc opc, struct ice_sq_cd *cd)
2758 struct ice_aqc_list_caps *cmd;
2759 struct ice_aq_desc desc;
2760 enum ice_status status;
2762 cmd = &desc.params.get_cap;
2764 if (opc != ice_aqc_opc_list_func_caps &&
2765 opc != ice_aqc_opc_list_dev_caps)
2766 return ICE_ERR_PARAM;
2768 ice_fill_dflt_direct_cmd_desc(&desc, opc);
2769 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);
2772 *cap_count = LE32_TO_CPU(cmd->count);
2778 * ice_discover_dev_caps - Read and extract device capabilities
2779 * @hw: pointer to the hardware structure
2780 * @dev_caps: pointer to device capabilities structure
2782 * Read the device capabilities and extract them into the dev_caps structure
2785 static enum ice_status
2786 ice_discover_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_caps)
2788 enum ice_status status;
2792 cbuf = ice_malloc(hw, ICE_AQ_MAX_BUF_LEN);
2794 return ICE_ERR_NO_MEMORY;
2796 /* Although the driver doesn't know the number of capabilities the
2797 * device will return, we can simply send a 4KB buffer, the maximum
2798 * possible size that firmware can return.
2800 cap_count = ICE_AQ_MAX_BUF_LEN / sizeof(struct ice_aqc_list_caps_elem);
2802 status = ice_aq_list_caps(hw, cbuf, ICE_AQ_MAX_BUF_LEN, &cap_count,
2803 ice_aqc_opc_list_dev_caps, NULL);
2805 ice_parse_dev_caps(hw, dev_caps, cbuf, cap_count);
2812 * ice_discover_func_caps - Read and extract function capabilities
2813 * @hw: pointer to the hardware structure
2814 * @func_caps: pointer to function capabilities structure
2816 * Read the function capabilities and extract them into the func_caps structure
2819 static enum ice_status
2820 ice_discover_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_caps)
2822 enum ice_status status;
2826 cbuf = ice_malloc(hw, ICE_AQ_MAX_BUF_LEN);
2828 return ICE_ERR_NO_MEMORY;
2830 /* Although the driver doesn't know the number of capabilities the
2831 * device will return, we can simply send a 4KB buffer, the maximum
2832 * possible size that firmware can return.
2834 cap_count = ICE_AQ_MAX_BUF_LEN / sizeof(struct ice_aqc_list_caps_elem);
2836 status = ice_aq_list_caps(hw, cbuf, ICE_AQ_MAX_BUF_LEN, &cap_count,
2837 ice_aqc_opc_list_func_caps, NULL);
2839 ice_parse_func_caps(hw, func_caps, cbuf, cap_count);
2846 * ice_set_safe_mode_caps - Override dev/func capabilities when in safe mode
2847 * @hw: pointer to the hardware structure
2849 void ice_set_safe_mode_caps(struct ice_hw *hw)
2851 struct ice_hw_func_caps *func_caps = &hw->func_caps;
2852 struct ice_hw_dev_caps *dev_caps = &hw->dev_caps;
2853 struct ice_hw_common_caps cached_caps;
2856 /* cache some func_caps values that should be restored after memset */
2857 cached_caps = func_caps->common_cap;
2859 /* unset func capabilities */
2860 memset(func_caps, 0, sizeof(*func_caps));
2862 #define ICE_RESTORE_FUNC_CAP(name) \
2863 func_caps->common_cap.name = cached_caps.name
2865 /* restore cached values */
2866 ICE_RESTORE_FUNC_CAP(valid_functions);
2867 ICE_RESTORE_FUNC_CAP(txq_first_id);
2868 ICE_RESTORE_FUNC_CAP(rxq_first_id);
2869 ICE_RESTORE_FUNC_CAP(msix_vector_first_id);
2870 ICE_RESTORE_FUNC_CAP(max_mtu);
2871 ICE_RESTORE_FUNC_CAP(nvm_unified_update);
2873 /* one Tx and one Rx queue in safe mode */
2874 func_caps->common_cap.num_rxq = 1;
2875 func_caps->common_cap.num_txq = 1;
2877 /* two MSIX vectors, one for traffic and one for misc causes */
2878 func_caps->common_cap.num_msix_vectors = 2;
2879 func_caps->guar_num_vsi = 1;
2881 /* cache some dev_caps values that should be restored after memset */
2882 cached_caps = dev_caps->common_cap;
2883 num_funcs = dev_caps->num_funcs;
2885 /* unset dev capabilities */
2886 memset(dev_caps, 0, sizeof(*dev_caps));
2888 #define ICE_RESTORE_DEV_CAP(name) \
2889 dev_caps->common_cap.name = cached_caps.name
2891 /* restore cached values */
2892 ICE_RESTORE_DEV_CAP(valid_functions);
2893 ICE_RESTORE_DEV_CAP(txq_first_id);
2894 ICE_RESTORE_DEV_CAP(rxq_first_id);
2895 ICE_RESTORE_DEV_CAP(msix_vector_first_id);
2896 ICE_RESTORE_DEV_CAP(max_mtu);
2897 ICE_RESTORE_DEV_CAP(nvm_unified_update);
2898 dev_caps->num_funcs = num_funcs;
2900 /* one Tx and one Rx queue per function in safe mode */
2901 dev_caps->common_cap.num_rxq = num_funcs;
2902 dev_caps->common_cap.num_txq = num_funcs;
2904 /* two MSIX vectors per function */
2905 dev_caps->common_cap.num_msix_vectors = 2 * num_funcs;
2909 * ice_get_caps - get info about the HW
2910 * @hw: pointer to the hardware structure
2912 enum ice_status ice_get_caps(struct ice_hw *hw)
2914 enum ice_status status;
2916 status = ice_discover_dev_caps(hw, &hw->dev_caps);
2920 return ice_discover_func_caps(hw, &hw->func_caps);
2924 * ice_aq_manage_mac_write - manage MAC address write command
2925 * @hw: pointer to the HW struct
2926 * @mac_addr: MAC address to be written as LAA/LAA+WoL/Port address
2927 * @flags: flags to control write behavior
2928 * @cd: pointer to command details structure or NULL
2930 * This function is used to write MAC address to the NVM (0x0108).
2933 ice_aq_manage_mac_write(struct ice_hw *hw, const u8 *mac_addr, u8 flags,
2934 struct ice_sq_cd *cd)
2936 struct ice_aqc_manage_mac_write *cmd;
2937 struct ice_aq_desc desc;
2939 cmd = &desc.params.mac_write;
2940 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_write);
2943 ice_memcpy(cmd->mac_addr, mac_addr, ETH_ALEN, ICE_NONDMA_TO_NONDMA);
2945 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
2949 * ice_aq_clear_pxe_mode
2950 * @hw: pointer to the HW struct
2952 * Tell the firmware that the driver is taking over from PXE (0x0110).
2954 static enum ice_status ice_aq_clear_pxe_mode(struct ice_hw *hw)
2956 struct ice_aq_desc desc;
2958 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pxe_mode);
2959 desc.params.clear_pxe.rx_cnt = ICE_AQC_CLEAR_PXE_RX_CNT;
2961 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
2965 * ice_clear_pxe_mode - clear pxe operations mode
2966 * @hw: pointer to the HW struct
2968 * Make sure all PXE mode settings are cleared, including things
2969 * like descriptor fetch/write-back mode.
2971 void ice_clear_pxe_mode(struct ice_hw *hw)
2973 if (ice_check_sq_alive(hw, &hw->adminq))
2974 ice_aq_clear_pxe_mode(hw);
2978 * ice_aq_set_port_params - set physical port parameters.
2979 * @pi: pointer to the port info struct
2980 * @bad_frame_vsi: defines the VSI to which bad frames are forwarded
2981 * @save_bad_pac: if set packets with errors are forwarded to the bad frames VSI
2982 * @pad_short_pac: if set transmit packets smaller than 60 bytes are padded
2983 * @double_vlan: if set double VLAN is enabled
2984 * @cd: pointer to command details structure or NULL
2986 * Set Physical port parameters (0x0203)
2989 ice_aq_set_port_params(struct ice_port_info *pi, u16 bad_frame_vsi,
2990 bool save_bad_pac, bool pad_short_pac, bool double_vlan,
2991 struct ice_sq_cd *cd)
2994 struct ice_aqc_set_port_params *cmd;
2995 struct ice_hw *hw = pi->hw;
2996 struct ice_aq_desc desc;
2999 cmd = &desc.params.set_port_params;
3001 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_port_params);
3002 cmd->bad_frame_vsi = CPU_TO_LE16(bad_frame_vsi);
3004 cmd_flags |= ICE_AQC_SET_P_PARAMS_SAVE_BAD_PACKETS;
3006 cmd_flags |= ICE_AQC_SET_P_PARAMS_PAD_SHORT_PACKETS;
3008 cmd_flags |= ICE_AQC_SET_P_PARAMS_DOUBLE_VLAN_ENA;
3009 cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
3011 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
3015 * ice_get_link_speed_based_on_phy_type - returns link speed
3016 * @phy_type_low: lower part of phy_type
3017 * @phy_type_high: higher part of phy_type
3019 * This helper function will convert an entry in PHY type structure
3020 * [phy_type_low, phy_type_high] to its corresponding link speed.
3021 * Note: In the structure of [phy_type_low, phy_type_high], there should
3022 * be one bit set, as this function will convert one PHY type to its
3024 * If no bit gets set, ICE_LINK_SPEED_UNKNOWN will be returned
3025 * If more than one bit gets set, ICE_LINK_SPEED_UNKNOWN will be returned
3028 ice_get_link_speed_based_on_phy_type(u64 phy_type_low, u64 phy_type_high)
3030 u16 speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN;
3031 u16 speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN;
3033 switch (phy_type_low) {
3034 case ICE_PHY_TYPE_LOW_100BASE_TX:
3035 case ICE_PHY_TYPE_LOW_100M_SGMII:
3036 speed_phy_type_low = ICE_AQ_LINK_SPEED_100MB;
3038 case ICE_PHY_TYPE_LOW_1000BASE_T:
3039 case ICE_PHY_TYPE_LOW_1000BASE_SX:
3040 case ICE_PHY_TYPE_LOW_1000BASE_LX:
3041 case ICE_PHY_TYPE_LOW_1000BASE_KX:
3042 case ICE_PHY_TYPE_LOW_1G_SGMII:
3043 speed_phy_type_low = ICE_AQ_LINK_SPEED_1000MB;
3045 case ICE_PHY_TYPE_LOW_2500BASE_T:
3046 case ICE_PHY_TYPE_LOW_2500BASE_X:
3047 case ICE_PHY_TYPE_LOW_2500BASE_KX:
3048 speed_phy_type_low = ICE_AQ_LINK_SPEED_2500MB;
3050 case ICE_PHY_TYPE_LOW_5GBASE_T:
3051 case ICE_PHY_TYPE_LOW_5GBASE_KR:
3052 speed_phy_type_low = ICE_AQ_LINK_SPEED_5GB;
3054 case ICE_PHY_TYPE_LOW_10GBASE_T:
3055 case ICE_PHY_TYPE_LOW_10G_SFI_DA:
3056 case ICE_PHY_TYPE_LOW_10GBASE_SR:
3057 case ICE_PHY_TYPE_LOW_10GBASE_LR:
3058 case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1:
3059 case ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC:
3060 case ICE_PHY_TYPE_LOW_10G_SFI_C2C:
3061 speed_phy_type_low = ICE_AQ_LINK_SPEED_10GB;
3063 case ICE_PHY_TYPE_LOW_25GBASE_T:
3064 case ICE_PHY_TYPE_LOW_25GBASE_CR:
3065 case ICE_PHY_TYPE_LOW_25GBASE_CR_S:
3066 case ICE_PHY_TYPE_LOW_25GBASE_CR1:
3067 case ICE_PHY_TYPE_LOW_25GBASE_SR:
3068 case ICE_PHY_TYPE_LOW_25GBASE_LR:
3069 case ICE_PHY_TYPE_LOW_25GBASE_KR:
3070 case ICE_PHY_TYPE_LOW_25GBASE_KR_S:
3071 case ICE_PHY_TYPE_LOW_25GBASE_KR1:
3072 case ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC:
3073 case ICE_PHY_TYPE_LOW_25G_AUI_C2C:
3074 speed_phy_type_low = ICE_AQ_LINK_SPEED_25GB;
3076 case ICE_PHY_TYPE_LOW_40GBASE_CR4:
3077 case ICE_PHY_TYPE_LOW_40GBASE_SR4:
3078 case ICE_PHY_TYPE_LOW_40GBASE_LR4:
3079 case ICE_PHY_TYPE_LOW_40GBASE_KR4:
3080 case ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC:
3081 case ICE_PHY_TYPE_LOW_40G_XLAUI:
3082 speed_phy_type_low = ICE_AQ_LINK_SPEED_40GB;
3084 case ICE_PHY_TYPE_LOW_50GBASE_CR2:
3085 case ICE_PHY_TYPE_LOW_50GBASE_SR2:
3086 case ICE_PHY_TYPE_LOW_50GBASE_LR2:
3087 case ICE_PHY_TYPE_LOW_50GBASE_KR2:
3088 case ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC:
3089 case ICE_PHY_TYPE_LOW_50G_LAUI2:
3090 case ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC:
3091 case ICE_PHY_TYPE_LOW_50G_AUI2:
3092 case ICE_PHY_TYPE_LOW_50GBASE_CP:
3093 case ICE_PHY_TYPE_LOW_50GBASE_SR:
3094 case ICE_PHY_TYPE_LOW_50GBASE_FR:
3095 case ICE_PHY_TYPE_LOW_50GBASE_LR:
3096 case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4:
3097 case ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC:
3098 case ICE_PHY_TYPE_LOW_50G_AUI1:
3099 speed_phy_type_low = ICE_AQ_LINK_SPEED_50GB;
3101 case ICE_PHY_TYPE_LOW_100GBASE_CR4:
3102 case ICE_PHY_TYPE_LOW_100GBASE_SR4:
3103 case ICE_PHY_TYPE_LOW_100GBASE_LR4:
3104 case ICE_PHY_TYPE_LOW_100GBASE_KR4:
3105 case ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC:
3106 case ICE_PHY_TYPE_LOW_100G_CAUI4:
3107 case ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC:
3108 case ICE_PHY_TYPE_LOW_100G_AUI4:
3109 case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4:
3110 case ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4:
3111 case ICE_PHY_TYPE_LOW_100GBASE_CP2:
3112 case ICE_PHY_TYPE_LOW_100GBASE_SR2:
3113 case ICE_PHY_TYPE_LOW_100GBASE_DR:
3114 speed_phy_type_low = ICE_AQ_LINK_SPEED_100GB;
3117 speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN;
3121 switch (phy_type_high) {
3122 case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4:
3123 case ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC:
3124 case ICE_PHY_TYPE_HIGH_100G_CAUI2:
3125 case ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC:
3126 case ICE_PHY_TYPE_HIGH_100G_AUI2:
3127 speed_phy_type_high = ICE_AQ_LINK_SPEED_100GB;
3130 speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN;
3134 if (speed_phy_type_low == ICE_AQ_LINK_SPEED_UNKNOWN &&
3135 speed_phy_type_high == ICE_AQ_LINK_SPEED_UNKNOWN)
3136 return ICE_AQ_LINK_SPEED_UNKNOWN;
3137 else if (speed_phy_type_low != ICE_AQ_LINK_SPEED_UNKNOWN &&
3138 speed_phy_type_high != ICE_AQ_LINK_SPEED_UNKNOWN)
3139 return ICE_AQ_LINK_SPEED_UNKNOWN;
3140 else if (speed_phy_type_low != ICE_AQ_LINK_SPEED_UNKNOWN &&
3141 speed_phy_type_high == ICE_AQ_LINK_SPEED_UNKNOWN)
3142 return speed_phy_type_low;
3144 return speed_phy_type_high;
3148 * ice_update_phy_type
3149 * @phy_type_low: pointer to the lower part of phy_type
3150 * @phy_type_high: pointer to the higher part of phy_type
3151 * @link_speeds_bitmap: targeted link speeds bitmap
3153 * Note: For the link_speeds_bitmap structure, you can check it at
3154 * [ice_aqc_get_link_status->link_speed]. Caller can pass in
3155 * link_speeds_bitmap include multiple speeds.
3157 * Each entry in this [phy_type_low, phy_type_high] structure will
3158 * present a certain link speed. This helper function will turn on bits
3159 * in [phy_type_low, phy_type_high] structure based on the value of
3160 * link_speeds_bitmap input parameter.
3163 ice_update_phy_type(u64 *phy_type_low, u64 *phy_type_high,
3164 u16 link_speeds_bitmap)
3171 /* We first check with low part of phy_type */
3172 for (index = 0; index <= ICE_PHY_TYPE_LOW_MAX_INDEX; index++) {
3173 pt_low = BIT_ULL(index);
3174 speed = ice_get_link_speed_based_on_phy_type(pt_low, 0);
3176 if (link_speeds_bitmap & speed)
3177 *phy_type_low |= BIT_ULL(index);
3180 /* We then check with high part of phy_type */
3181 for (index = 0; index <= ICE_PHY_TYPE_HIGH_MAX_INDEX; index++) {
3182 pt_high = BIT_ULL(index);
3183 speed = ice_get_link_speed_based_on_phy_type(0, pt_high);
3185 if (link_speeds_bitmap & speed)
3186 *phy_type_high |= BIT_ULL(index);
3191 * ice_aq_set_phy_cfg
3192 * @hw: pointer to the HW struct
3193 * @pi: port info structure of the interested logical port
3194 * @cfg: structure with PHY configuration data to be set
3195 * @cd: pointer to command details structure or NULL
3197 * Set the various PHY configuration parameters supported on the Port.
3198 * One or more of the Set PHY config parameters may be ignored in an MFP
3199 * mode as the PF may not have the privilege to set some of the PHY Config
3200 * parameters. This status will be indicated by the command response (0x0601).
3203 ice_aq_set_phy_cfg(struct ice_hw *hw, struct ice_port_info *pi,
3204 struct ice_aqc_set_phy_cfg_data *cfg, struct ice_sq_cd *cd)
3206 struct ice_aq_desc desc;
3207 enum ice_status status;
3210 return ICE_ERR_PARAM;
3212 /* Ensure that only valid bits of cfg->caps can be turned on. */
3213 if (cfg->caps & ~ICE_AQ_PHY_ENA_VALID_MASK) {
3214 ice_debug(hw, ICE_DBG_PHY, "Invalid bit is set in ice_aqc_set_phy_cfg_data->caps : 0x%x\n",
3217 cfg->caps &= ICE_AQ_PHY_ENA_VALID_MASK;
3220 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_phy_cfg);
3221 desc.params.set_phy.lport_num = pi->lport;
3222 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
3224 ice_debug(hw, ICE_DBG_LINK, "set phy cfg\n");
3225 ice_debug(hw, ICE_DBG_LINK, " phy_type_low = 0x%llx\n",
3226 (unsigned long long)LE64_TO_CPU(cfg->phy_type_low));
3227 ice_debug(hw, ICE_DBG_LINK, " phy_type_high = 0x%llx\n",
3228 (unsigned long long)LE64_TO_CPU(cfg->phy_type_high));
3229 ice_debug(hw, ICE_DBG_LINK, " caps = 0x%x\n", cfg->caps);
3230 ice_debug(hw, ICE_DBG_LINK, " low_power_ctrl_an = 0x%x\n",
3231 cfg->low_power_ctrl_an);
3232 ice_debug(hw, ICE_DBG_LINK, " eee_cap = 0x%x\n", cfg->eee_cap);
3233 ice_debug(hw, ICE_DBG_LINK, " eeer_value = 0x%x\n", cfg->eeer_value);
3234 ice_debug(hw, ICE_DBG_LINK, " link_fec_opt = 0x%x\n",
3237 status = ice_aq_send_cmd(hw, &desc, cfg, sizeof(*cfg), cd);
3239 if (hw->adminq.sq_last_status == ICE_AQ_RC_EMODE)
3240 status = ICE_SUCCESS;
3243 pi->phy.curr_user_phy_cfg = *cfg;
3249 * ice_update_link_info - update status of the HW network link
3250 * @pi: port info structure of the interested logical port
3252 enum ice_status ice_update_link_info(struct ice_port_info *pi)
3254 struct ice_link_status *li;
3255 enum ice_status status;
3258 return ICE_ERR_PARAM;
3260 li = &pi->phy.link_info;
3262 status = ice_aq_get_link_info(pi, true, NULL, NULL);
3266 if (li->link_info & ICE_AQ_MEDIA_AVAILABLE) {
3267 struct ice_aqc_get_phy_caps_data *pcaps;
3271 pcaps = (struct ice_aqc_get_phy_caps_data *)
3272 ice_malloc(hw, sizeof(*pcaps));
3274 return ICE_ERR_NO_MEMORY;
3276 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_TOPO_CAP_MEDIA,
3279 if (status == ICE_SUCCESS)
3280 ice_memcpy(li->module_type, &pcaps->module_type,
3281 sizeof(li->module_type),
3282 ICE_NONDMA_TO_NONDMA);
3284 ice_free(hw, pcaps);
3291 * ice_cache_phy_user_req
3292 * @pi: port information structure
3293 * @cache_data: PHY logging data
3294 * @cache_mode: PHY logging mode
3296 * Log the user request on (FC, FEC, SPEED) for later user.
3299 ice_cache_phy_user_req(struct ice_port_info *pi,
3300 struct ice_phy_cache_mode_data cache_data,
3301 enum ice_phy_cache_mode cache_mode)
3306 switch (cache_mode) {
3308 pi->phy.curr_user_fc_req = cache_data.data.curr_user_fc_req;
3310 case ICE_SPEED_MODE:
3311 pi->phy.curr_user_speed_req =
3312 cache_data.data.curr_user_speed_req;
3315 pi->phy.curr_user_fec_req = cache_data.data.curr_user_fec_req;
3323 * ice_caps_to_fc_mode
3324 * @caps: PHY capabilities
3326 * Convert PHY FC capabilities to ice FC mode
3328 enum ice_fc_mode ice_caps_to_fc_mode(u8 caps)
3330 if (caps & ICE_AQC_PHY_EN_TX_LINK_PAUSE &&
3331 caps & ICE_AQC_PHY_EN_RX_LINK_PAUSE)
3334 if (caps & ICE_AQC_PHY_EN_TX_LINK_PAUSE)
3335 return ICE_FC_TX_PAUSE;
3337 if (caps & ICE_AQC_PHY_EN_RX_LINK_PAUSE)
3338 return ICE_FC_RX_PAUSE;
3344 * ice_caps_to_fec_mode
3345 * @caps: PHY capabilities
3346 * @fec_options: Link FEC options
3348 * Convert PHY FEC capabilities to ice FEC mode
3350 enum ice_fec_mode ice_caps_to_fec_mode(u8 caps, u8 fec_options)
3352 if (caps & ICE_AQC_PHY_EN_AUTO_FEC)
3353 return ICE_FEC_AUTO;
3355 if (fec_options & (ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN |
3356 ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ |
3357 ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN |
3358 ICE_AQC_PHY_FEC_25G_KR_REQ))
3359 return ICE_FEC_BASER;
3361 if (fec_options & (ICE_AQC_PHY_FEC_25G_RS_528_REQ |
3362 ICE_AQC_PHY_FEC_25G_RS_544_REQ |
3363 ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN))
3366 return ICE_FEC_NONE;
3370 * ice_cfg_phy_fc - Configure PHY FC data based on FC mode
3371 * @pi: port information structure
3372 * @cfg: PHY configuration data to set FC mode
3373 * @req_mode: FC mode to configure
3375 static enum ice_status
3376 ice_cfg_phy_fc(struct ice_port_info *pi, struct ice_aqc_set_phy_cfg_data *cfg,
3377 enum ice_fc_mode req_mode)
3379 struct ice_phy_cache_mode_data cache_data;
3380 u8 pause_mask = 0x0;
3383 return ICE_ERR_BAD_PTR;
3388 struct ice_aqc_get_phy_caps_data *pcaps;
3389 enum ice_status status;
3391 pcaps = (struct ice_aqc_get_phy_caps_data *)
3392 ice_malloc(pi->hw, sizeof(*pcaps));
3394 return ICE_ERR_NO_MEMORY;
3396 /* Query the value of FC that both the NIC and attached media
3399 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_TOPO_CAP_MEDIA,
3402 ice_free(pi->hw, pcaps);
3406 pause_mask |= pcaps->caps & ICE_AQC_PHY_EN_TX_LINK_PAUSE;
3407 pause_mask |= pcaps->caps & ICE_AQC_PHY_EN_RX_LINK_PAUSE;
3409 ice_free(pi->hw, pcaps);
3413 pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE;
3414 pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE;
3416 case ICE_FC_RX_PAUSE:
3417 pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE;
3419 case ICE_FC_TX_PAUSE:
3420 pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE;
3426 /* clear the old pause settings */
3427 cfg->caps &= ~(ICE_AQC_PHY_EN_TX_LINK_PAUSE |
3428 ICE_AQC_PHY_EN_RX_LINK_PAUSE);
3430 /* set the new capabilities */
3431 cfg->caps |= pause_mask;
3433 /* Cache user FC request */
3434 cache_data.data.curr_user_fc_req = req_mode;
3435 ice_cache_phy_user_req(pi, cache_data, ICE_FC_MODE);
3442 * @pi: port information structure
3443 * @aq_failures: pointer to status code, specific to ice_set_fc routine
3444 * @ena_auto_link_update: enable automatic link update
3446 * Set the requested flow control mode.
3449 ice_set_fc(struct ice_port_info *pi, u8 *aq_failures, bool ena_auto_link_update)
3451 struct ice_aqc_set_phy_cfg_data cfg = { 0 };
3452 struct ice_aqc_get_phy_caps_data *pcaps;
3453 enum ice_status status;
3456 if (!pi || !aq_failures)
3457 return ICE_ERR_BAD_PTR;
3462 pcaps = (struct ice_aqc_get_phy_caps_data *)
3463 ice_malloc(hw, sizeof(*pcaps));
3465 return ICE_ERR_NO_MEMORY;
3467 /* Get the current PHY config */
3468 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_ACTIVE_CFG,
3472 *aq_failures = ICE_SET_FC_AQ_FAIL_GET;
3476 ice_copy_phy_caps_to_cfg(pi, pcaps, &cfg);
3478 /* Configure the set PHY data */
3479 status = ice_cfg_phy_fc(pi, &cfg, pi->fc.req_mode);
3481 if (status != ICE_ERR_BAD_PTR)
3482 *aq_failures = ICE_SET_FC_AQ_FAIL_GET;
3487 /* If the capabilities have changed, then set the new config */
3488 if (cfg.caps != pcaps->caps) {
3489 int retry_count, retry_max = 10;
3491 /* Auto restart link so settings take effect */
3492 if (ena_auto_link_update)
3493 cfg.caps |= ICE_AQ_PHY_ENA_AUTO_LINK_UPDT;
3495 status = ice_aq_set_phy_cfg(hw, pi, &cfg, NULL);
3497 *aq_failures = ICE_SET_FC_AQ_FAIL_SET;
3501 /* Update the link info
3502 * It sometimes takes a really long time for link to
3503 * come back from the atomic reset. Thus, we wait a
3506 for (retry_count = 0; retry_count < retry_max; retry_count++) {
3507 status = ice_update_link_info(pi);
3509 if (status == ICE_SUCCESS)
3512 ice_msec_delay(100, true);
3516 *aq_failures = ICE_SET_FC_AQ_FAIL_UPDATE;
3520 ice_free(hw, pcaps);
3525 * ice_phy_caps_equals_cfg
3526 * @phy_caps: PHY capabilities
3527 * @phy_cfg: PHY configuration
3529 * Helper function to determine if PHY capabilities matches PHY
3533 ice_phy_caps_equals_cfg(struct ice_aqc_get_phy_caps_data *phy_caps,
3534 struct ice_aqc_set_phy_cfg_data *phy_cfg)
3536 u8 caps_mask, cfg_mask;
3538 if (!phy_caps || !phy_cfg)
3541 /* These bits are not common between capabilities and configuration.
3542 * Do not use them to determine equality.
3544 caps_mask = ICE_AQC_PHY_CAPS_MASK & ~(ICE_AQC_PHY_AN_MODE |
3545 ICE_AQC_PHY_EN_MOD_QUAL);
3546 cfg_mask = ICE_AQ_PHY_ENA_VALID_MASK & ~ICE_AQ_PHY_ENA_AUTO_LINK_UPDT;
3548 if (phy_caps->phy_type_low != phy_cfg->phy_type_low ||
3549 phy_caps->phy_type_high != phy_cfg->phy_type_high ||
3550 ((phy_caps->caps & caps_mask) != (phy_cfg->caps & cfg_mask)) ||
3551 phy_caps->low_power_ctrl_an != phy_cfg->low_power_ctrl_an ||
3552 phy_caps->eee_cap != phy_cfg->eee_cap ||
3553 phy_caps->eeer_value != phy_cfg->eeer_value ||
3554 phy_caps->link_fec_options != phy_cfg->link_fec_opt)
3561 * ice_copy_phy_caps_to_cfg - Copy PHY ability data to configuration data
3562 * @pi: port information structure
3563 * @caps: PHY ability structure to copy data from
3564 * @cfg: PHY configuration structure to copy data to
3566 * Helper function to copy AQC PHY get ability data to PHY set configuration
3570 ice_copy_phy_caps_to_cfg(struct ice_port_info *pi,
3571 struct ice_aqc_get_phy_caps_data *caps,
3572 struct ice_aqc_set_phy_cfg_data *cfg)
3574 if (!pi || !caps || !cfg)
3577 ice_memset(cfg, 0, sizeof(*cfg), ICE_NONDMA_MEM);
3578 cfg->phy_type_low = caps->phy_type_low;
3579 cfg->phy_type_high = caps->phy_type_high;
3580 cfg->caps = caps->caps;
3581 cfg->low_power_ctrl_an = caps->low_power_ctrl_an;
3582 cfg->eee_cap = caps->eee_cap;
3583 cfg->eeer_value = caps->eeer_value;
3584 cfg->link_fec_opt = caps->link_fec_options;
3585 cfg->module_compliance_enforcement =
3586 caps->module_compliance_enforcement;
3590 * ice_cfg_phy_fec - Configure PHY FEC data based on FEC mode
3591 * @pi: port information structure
3592 * @cfg: PHY configuration data to set FEC mode
3593 * @fec: FEC mode to configure
3596 ice_cfg_phy_fec(struct ice_port_info *pi, struct ice_aqc_set_phy_cfg_data *cfg,
3597 enum ice_fec_mode fec)
3599 struct ice_aqc_get_phy_caps_data *pcaps;
3600 enum ice_status status = ICE_SUCCESS;
3604 return ICE_ERR_BAD_PTR;
3608 pcaps = (struct ice_aqc_get_phy_caps_data *)
3609 ice_malloc(hw, sizeof(*pcaps));
3611 return ICE_ERR_NO_MEMORY;
3613 status = ice_aq_get_phy_caps(pi, false,
3614 (ice_fw_supports_report_dflt_cfg(hw) ?
3615 ICE_AQC_REPORT_DFLT_CFG :
3616 ICE_AQC_REPORT_TOPO_CAP_MEDIA), pcaps, NULL);
3621 cfg->caps |= (pcaps->caps & ICE_AQC_PHY_EN_AUTO_FEC);
3622 cfg->link_fec_opt = pcaps->link_fec_options;
3626 /* Clear RS bits, and AND BASE-R ability
3627 * bits and OR request bits.
3629 cfg->link_fec_opt &= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN |
3630 ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN;
3631 cfg->link_fec_opt |= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ |
3632 ICE_AQC_PHY_FEC_25G_KR_REQ;
3635 /* Clear BASE-R bits, and AND RS ability
3636 * bits and OR request bits.
3638 cfg->link_fec_opt &= ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN;
3639 cfg->link_fec_opt |= ICE_AQC_PHY_FEC_25G_RS_528_REQ |
3640 ICE_AQC_PHY_FEC_25G_RS_544_REQ;
3643 /* Clear all FEC option bits. */
3644 cfg->link_fec_opt &= ~ICE_AQC_PHY_FEC_MASK;
3647 /* AND auto FEC bit, and all caps bits. */
3648 cfg->caps &= ICE_AQC_PHY_CAPS_MASK;
3649 cfg->link_fec_opt |= pcaps->link_fec_options;
3652 status = ICE_ERR_PARAM;
3656 if (fec == ICE_FEC_AUTO && ice_fw_supports_link_override(pi->hw) &&
3657 !ice_fw_supports_report_dflt_cfg(pi->hw)) {
3658 struct ice_link_default_override_tlv tlv;
3660 if (ice_get_link_default_override(&tlv, pi))
3663 if (!(tlv.options & ICE_LINK_OVERRIDE_STRICT_MODE) &&
3664 (tlv.options & ICE_LINK_OVERRIDE_EN))
3665 cfg->link_fec_opt = tlv.fec_options;
3669 ice_free(hw, pcaps);
3675 * ice_get_link_status - get status of the HW network link
3676 * @pi: port information structure
3677 * @link_up: pointer to bool (true/false = linkup/linkdown)
3679 * Variable link_up is true if link is up, false if link is down.
3680 * The variable link_up is invalid if status is non zero. As a
3681 * result of this call, link status reporting becomes enabled
3683 enum ice_status ice_get_link_status(struct ice_port_info *pi, bool *link_up)
3685 struct ice_phy_info *phy_info;
3686 enum ice_status status = ICE_SUCCESS;
3688 if (!pi || !link_up)
3689 return ICE_ERR_PARAM;
3691 phy_info = &pi->phy;
3693 if (phy_info->get_link_info) {
3694 status = ice_update_link_info(pi);
3697 ice_debug(pi->hw, ICE_DBG_LINK, "get link status error, status = %d\n",
3701 *link_up = phy_info->link_info.link_info & ICE_AQ_LINK_UP;
3707 * ice_aq_set_link_restart_an
3708 * @pi: pointer to the port information structure
3709 * @ena_link: if true: enable link, if false: disable link
3710 * @cd: pointer to command details structure or NULL
3712 * Sets up the link and restarts the Auto-Negotiation over the link.
3715 ice_aq_set_link_restart_an(struct ice_port_info *pi, bool ena_link,
3716 struct ice_sq_cd *cd)
3718 struct ice_aqc_restart_an *cmd;
3719 struct ice_aq_desc desc;
3721 cmd = &desc.params.restart_an;
3723 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_restart_an);
3725 cmd->cmd_flags = ICE_AQC_RESTART_AN_LINK_RESTART;
3726 cmd->lport_num = pi->lport;
3728 cmd->cmd_flags |= ICE_AQC_RESTART_AN_LINK_ENABLE;
3730 cmd->cmd_flags &= ~ICE_AQC_RESTART_AN_LINK_ENABLE;
3732 return ice_aq_send_cmd(pi->hw, &desc, NULL, 0, cd);
3736 * ice_aq_set_event_mask
3737 * @hw: pointer to the HW struct
3738 * @port_num: port number of the physical function
3739 * @mask: event mask to be set
3740 * @cd: pointer to command details structure or NULL
3742 * Set event mask (0x0613)
3745 ice_aq_set_event_mask(struct ice_hw *hw, u8 port_num, u16 mask,
3746 struct ice_sq_cd *cd)
3748 struct ice_aqc_set_event_mask *cmd;
3749 struct ice_aq_desc desc;
3751 cmd = &desc.params.set_event_mask;
3753 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_event_mask);
3755 cmd->lport_num = port_num;
3757 cmd->event_mask = CPU_TO_LE16(mask);
3758 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
3762 * ice_aq_set_mac_loopback
3763 * @hw: pointer to the HW struct
3764 * @ena_lpbk: Enable or Disable loopback
3765 * @cd: pointer to command details structure or NULL
3767 * Enable/disable loopback on a given port
3770 ice_aq_set_mac_loopback(struct ice_hw *hw, bool ena_lpbk, struct ice_sq_cd *cd)
3772 struct ice_aqc_set_mac_lb *cmd;
3773 struct ice_aq_desc desc;
3775 cmd = &desc.params.set_mac_lb;
3777 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_mac_lb);
3779 cmd->lb_mode = ICE_AQ_MAC_LB_EN;
3781 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
3785 * ice_aq_set_port_id_led
3786 * @pi: pointer to the port information
3787 * @is_orig_mode: is this LED set to original mode (by the net-list)
3788 * @cd: pointer to command details structure or NULL
3790 * Set LED value for the given port (0x06e9)
3793 ice_aq_set_port_id_led(struct ice_port_info *pi, bool is_orig_mode,
3794 struct ice_sq_cd *cd)
3796 struct ice_aqc_set_port_id_led *cmd;
3797 struct ice_hw *hw = pi->hw;
3798 struct ice_aq_desc desc;
3800 cmd = &desc.params.set_port_id_led;
3802 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_port_id_led);
3805 cmd->ident_mode = ICE_AQC_PORT_IDENT_LED_ORIG;
3807 cmd->ident_mode = ICE_AQC_PORT_IDENT_LED_BLINK;
3809 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
3814 * @hw: pointer to the HW struct
3815 * @lport: bits [7:0] = logical port, bit [8] = logical port valid
3816 * @bus_addr: I2C bus address of the eeprom (typically 0xA0, 0=topo default)
3817 * @mem_addr: I2C offset. lower 8 bits for address, 8 upper bits zero padding.
3819 * @set_page: set or ignore the page
3820 * @data: pointer to data buffer to be read/written to the I2C device.
3821 * @length: 1-16 for read, 1 for write.
3822 * @write: 0 read, 1 for write.
3823 * @cd: pointer to command details structure or NULL
3825 * Read/Write SFF EEPROM (0x06EE)
3828 ice_aq_sff_eeprom(struct ice_hw *hw, u16 lport, u8 bus_addr,
3829 u16 mem_addr, u8 page, u8 set_page, u8 *data, u8 length,
3830 bool write, struct ice_sq_cd *cd)
3832 struct ice_aqc_sff_eeprom *cmd;
3833 struct ice_aq_desc desc;
3834 enum ice_status status;
3836 if (!data || (mem_addr & 0xff00))
3837 return ICE_ERR_PARAM;
3839 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_sff_eeprom);
3840 cmd = &desc.params.read_write_sff_param;
3841 desc.flags = CPU_TO_LE16(ICE_AQ_FLAG_RD);
3842 cmd->lport_num = (u8)(lport & 0xff);
3843 cmd->lport_num_valid = (u8)((lport >> 8) & 0x01);
3844 cmd->i2c_bus_addr = CPU_TO_LE16(((bus_addr >> 1) &
3845 ICE_AQC_SFF_I2CBUS_7BIT_M) |
3847 ICE_AQC_SFF_SET_EEPROM_PAGE_S) &
3848 ICE_AQC_SFF_SET_EEPROM_PAGE_M));
3849 cmd->i2c_mem_addr = CPU_TO_LE16(mem_addr & 0xff);
3850 cmd->eeprom_page = CPU_TO_LE16((u16)page << ICE_AQC_SFF_EEPROM_PAGE_S);
3852 cmd->i2c_bus_addr |= CPU_TO_LE16(ICE_AQC_SFF_IS_WRITE);
3854 status = ice_aq_send_cmd(hw, &desc, data, length, cd);
3859 * ice_aq_prog_topo_dev_nvm
3860 * @hw: pointer to the hardware structure
3861 * @topo_params: pointer to structure storing topology parameters for a device
3862 * @cd: pointer to command details structure or NULL
3864 * Program Topology Device NVM (0x06F2)
3868 ice_aq_prog_topo_dev_nvm(struct ice_hw *hw,
3869 struct ice_aqc_link_topo_params *topo_params,
3870 struct ice_sq_cd *cd)
3872 struct ice_aqc_prog_topo_dev_nvm *cmd;
3873 struct ice_aq_desc desc;
3875 cmd = &desc.params.prog_topo_dev_nvm;
3877 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_prog_topo_dev_nvm);
3879 ice_memcpy(&cmd->topo_params, topo_params, sizeof(*topo_params),
3880 ICE_NONDMA_TO_NONDMA);
3882 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
3886 * ice_aq_read_topo_dev_nvm
3887 * @hw: pointer to the hardware structure
3888 * @topo_params: pointer to structure storing topology parameters for a device
3889 * @start_address: byte offset in the topology device NVM
3890 * @data: pointer to data buffer
3891 * @data_size: number of bytes to be read from the topology device NVM
3892 * @cd: pointer to command details structure or NULL
3893 * Read Topology Device NVM (0x06F3)
3897 ice_aq_read_topo_dev_nvm(struct ice_hw *hw,
3898 struct ice_aqc_link_topo_params *topo_params,
3899 u32 start_address, u8 *data, u8 data_size,
3900 struct ice_sq_cd *cd)
3902 struct ice_aqc_read_topo_dev_nvm *cmd;
3903 struct ice_aq_desc desc;
3904 enum ice_status status;
3906 if (!data || data_size == 0 ||
3907 data_size > ICE_AQC_READ_TOPO_DEV_NVM_DATA_READ_SIZE)
3908 return ICE_ERR_PARAM;
3910 cmd = &desc.params.read_topo_dev_nvm;
3912 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_read_topo_dev_nvm);
3914 desc.datalen = data_size;
3915 ice_memcpy(&cmd->topo_params, topo_params, sizeof(*topo_params),
3916 ICE_NONDMA_TO_NONDMA);
3917 cmd->start_address = CPU_TO_LE32(start_address);
3919 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
3923 ice_memcpy(data, cmd->data_read, data_size, ICE_NONDMA_TO_NONDMA);
3929 * __ice_aq_get_set_rss_lut
3930 * @hw: pointer to the hardware structure
3931 * @params: RSS LUT parameters
3932 * @set: set true to set the table, false to get the table
3934 * Internal function to get (0x0B05) or set (0x0B03) RSS look up table
3936 static enum ice_status
3937 __ice_aq_get_set_rss_lut(struct ice_hw *hw, struct ice_aq_get_set_rss_lut_params *params, bool set)
3939 u16 flags = 0, vsi_id, lut_type, lut_size, glob_lut_idx, vsi_handle;
3940 struct ice_aqc_get_set_rss_lut *cmd_resp;
3941 struct ice_aq_desc desc;
3942 enum ice_status status;
3946 return ICE_ERR_PARAM;
3948 vsi_handle = params->vsi_handle;
3951 if (!ice_is_vsi_valid(hw, vsi_handle) || !lut)
3952 return ICE_ERR_PARAM;
3954 lut_size = params->lut_size;
3955 lut_type = params->lut_type;
3956 glob_lut_idx = params->global_lut_id;
3957 vsi_id = ice_get_hw_vsi_num(hw, vsi_handle);
3959 cmd_resp = &desc.params.get_set_rss_lut;
3962 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_rss_lut);
3963 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
3965 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_rss_lut);
3968 cmd_resp->vsi_id = CPU_TO_LE16(((vsi_id <<
3969 ICE_AQC_GSET_RSS_LUT_VSI_ID_S) &
3970 ICE_AQC_GSET_RSS_LUT_VSI_ID_M) |
3971 ICE_AQC_GSET_RSS_LUT_VSI_VALID);
3974 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_VSI:
3975 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF:
3976 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL:
3977 flags |= ((lut_type << ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S) &
3978 ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_M);
3981 status = ICE_ERR_PARAM;
3982 goto ice_aq_get_set_rss_lut_exit;
3985 if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL) {
3986 flags |= ((glob_lut_idx << ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S) &
3987 ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_M);
3990 goto ice_aq_get_set_rss_lut_send;
3991 } else if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF) {
3993 goto ice_aq_get_set_rss_lut_send;
3995 goto ice_aq_get_set_rss_lut_send;
3998 /* LUT size is only valid for Global and PF table types */
4000 case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128:
4001 flags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128_FLAG <<
4002 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) &
4003 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M;
4005 case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512:
4006 flags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512_FLAG <<
4007 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) &
4008 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M;
4010 case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K:
4011 if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF) {
4012 flags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K_FLAG <<
4013 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) &
4014 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M;
4019 status = ICE_ERR_PARAM;
4020 goto ice_aq_get_set_rss_lut_exit;
4023 ice_aq_get_set_rss_lut_send:
4024 cmd_resp->flags = CPU_TO_LE16(flags);
4025 status = ice_aq_send_cmd(hw, &desc, lut, lut_size, NULL);
4027 ice_aq_get_set_rss_lut_exit:
4032 * ice_aq_get_rss_lut
4033 * @hw: pointer to the hardware structure
4034 * @get_params: RSS LUT parameters used to specify which RSS LUT to get
4036 * get the RSS lookup table, PF or VSI type
4039 ice_aq_get_rss_lut(struct ice_hw *hw, struct ice_aq_get_set_rss_lut_params *get_params)
4041 return __ice_aq_get_set_rss_lut(hw, get_params, false);
4045 * ice_aq_set_rss_lut
4046 * @hw: pointer to the hardware structure
4047 * @set_params: RSS LUT parameters used to specify how to set the RSS LUT
4049 * set the RSS lookup table, PF or VSI type
4052 ice_aq_set_rss_lut(struct ice_hw *hw, struct ice_aq_get_set_rss_lut_params *set_params)
4054 return __ice_aq_get_set_rss_lut(hw, set_params, true);
4058 * __ice_aq_get_set_rss_key
4059 * @hw: pointer to the HW struct
4060 * @vsi_id: VSI FW index
4061 * @key: pointer to key info struct
4062 * @set: set true to set the key, false to get the key
4064 * get (0x0B04) or set (0x0B02) the RSS key per VSI
4067 ice_status __ice_aq_get_set_rss_key(struct ice_hw *hw, u16 vsi_id,
4068 struct ice_aqc_get_set_rss_keys *key,
4071 struct ice_aqc_get_set_rss_key *cmd_resp;
4072 u16 key_size = sizeof(*key);
4073 struct ice_aq_desc desc;
4075 cmd_resp = &desc.params.get_set_rss_key;
4078 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_rss_key);
4079 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
4081 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_rss_key);
4084 cmd_resp->vsi_id = CPU_TO_LE16(((vsi_id <<
4085 ICE_AQC_GSET_RSS_KEY_VSI_ID_S) &
4086 ICE_AQC_GSET_RSS_KEY_VSI_ID_M) |
4087 ICE_AQC_GSET_RSS_KEY_VSI_VALID);
4089 return ice_aq_send_cmd(hw, &desc, key, key_size, NULL);
4093 * ice_aq_get_rss_key
4094 * @hw: pointer to the HW struct
4095 * @vsi_handle: software VSI handle
4096 * @key: pointer to key info struct
4098 * get the RSS key per VSI
4101 ice_aq_get_rss_key(struct ice_hw *hw, u16 vsi_handle,
4102 struct ice_aqc_get_set_rss_keys *key)
4104 if (!ice_is_vsi_valid(hw, vsi_handle) || !key)
4105 return ICE_ERR_PARAM;
4107 return __ice_aq_get_set_rss_key(hw, ice_get_hw_vsi_num(hw, vsi_handle),
4112 * ice_aq_set_rss_key
4113 * @hw: pointer to the HW struct
4114 * @vsi_handle: software VSI handle
4115 * @keys: pointer to key info struct
4117 * set the RSS key per VSI
4120 ice_aq_set_rss_key(struct ice_hw *hw, u16 vsi_handle,
4121 struct ice_aqc_get_set_rss_keys *keys)
4123 if (!ice_is_vsi_valid(hw, vsi_handle) || !keys)
4124 return ICE_ERR_PARAM;
4126 return __ice_aq_get_set_rss_key(hw, ice_get_hw_vsi_num(hw, vsi_handle),
4131 * ice_aq_add_lan_txq
4132 * @hw: pointer to the hardware structure
4133 * @num_qgrps: Number of added queue groups
4134 * @qg_list: list of queue groups to be added
4135 * @buf_size: size of buffer for indirect command
4136 * @cd: pointer to command details structure or NULL
4138 * Add Tx LAN queue (0x0C30)
4141 * Prior to calling add Tx LAN queue:
4142 * Initialize the following as part of the Tx queue context:
4143 * Completion queue ID if the queue uses Completion queue, Quanta profile,
4144 * Cache profile and Packet shaper profile.
4146 * After add Tx LAN queue AQ command is completed:
4147 * Interrupts should be associated with specific queues,
4148 * Association of Tx queue to Doorbell queue is not part of Add LAN Tx queue
4152 ice_aq_add_lan_txq(struct ice_hw *hw, u8 num_qgrps,
4153 struct ice_aqc_add_tx_qgrp *qg_list, u16 buf_size,
4154 struct ice_sq_cd *cd)
4156 struct ice_aqc_add_tx_qgrp *list;
4157 struct ice_aqc_add_txqs *cmd;
4158 struct ice_aq_desc desc;
4159 u16 i, sum_size = 0;
4161 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
4163 cmd = &desc.params.add_txqs;
4165 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_add_txqs);
4168 return ICE_ERR_PARAM;
4170 if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS)
4171 return ICE_ERR_PARAM;
4173 for (i = 0, list = qg_list; i < num_qgrps; i++) {
4174 sum_size += ice_struct_size(list, txqs, list->num_txqs);
4175 list = (struct ice_aqc_add_tx_qgrp *)(list->txqs +
4179 if (buf_size != sum_size)
4180 return ICE_ERR_PARAM;
4182 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
4184 cmd->num_qgrps = num_qgrps;
4186 return ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd);
4190 * ice_aq_dis_lan_txq
4191 * @hw: pointer to the hardware structure
4192 * @num_qgrps: number of groups in the list
4193 * @qg_list: the list of groups to disable
4194 * @buf_size: the total size of the qg_list buffer in bytes
4195 * @rst_src: if called due to reset, specifies the reset source
4196 * @vmvf_num: the relative VM or VF number that is undergoing the reset
4197 * @cd: pointer to command details structure or NULL
4199 * Disable LAN Tx queue (0x0C31)
4201 static enum ice_status
4202 ice_aq_dis_lan_txq(struct ice_hw *hw, u8 num_qgrps,
4203 struct ice_aqc_dis_txq_item *qg_list, u16 buf_size,
4204 enum ice_disq_rst_src rst_src, u16 vmvf_num,
4205 struct ice_sq_cd *cd)
4207 struct ice_aqc_dis_txq_item *item;
4208 struct ice_aqc_dis_txqs *cmd;
4209 struct ice_aq_desc desc;
4210 enum ice_status status;
4213 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
4214 cmd = &desc.params.dis_txqs;
4215 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_dis_txqs);
4217 /* qg_list can be NULL only in VM/VF reset flow */
4218 if (!qg_list && !rst_src)
4219 return ICE_ERR_PARAM;
4221 if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS)
4222 return ICE_ERR_PARAM;
4224 cmd->num_entries = num_qgrps;
4226 cmd->vmvf_and_timeout = CPU_TO_LE16((5 << ICE_AQC_Q_DIS_TIMEOUT_S) &
4227 ICE_AQC_Q_DIS_TIMEOUT_M);
4231 cmd->cmd_type = ICE_AQC_Q_DIS_CMD_VM_RESET;
4232 cmd->vmvf_and_timeout |=
4233 CPU_TO_LE16(vmvf_num & ICE_AQC_Q_DIS_VMVF_NUM_M);
4240 /* flush pipe on time out */
4241 cmd->cmd_type |= ICE_AQC_Q_DIS_CMD_FLUSH_PIPE;
4242 /* If no queue group info, we are in a reset flow. Issue the AQ */
4246 /* set RD bit to indicate that command buffer is provided by the driver
4247 * and it needs to be read by the firmware
4249 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
4251 for (i = 0, item = qg_list; i < num_qgrps; i++) {
4252 u16 item_size = ice_struct_size(item, q_id, item->num_qs);
4254 /* If the num of queues is even, add 2 bytes of padding */
4255 if ((item->num_qs % 2) == 0)
4260 item = (struct ice_aqc_dis_txq_item *)((u8 *)item + item_size);
4264 return ICE_ERR_PARAM;
4267 status = ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd);
4270 ice_debug(hw, ICE_DBG_SCHED, "VM%d disable failed %d\n",
4271 vmvf_num, hw->adminq.sq_last_status);
4273 ice_debug(hw, ICE_DBG_SCHED, "disable queue %d failed %d\n",
4274 LE16_TO_CPU(qg_list[0].q_id[0]),
4275 hw->adminq.sq_last_status);
4281 * ice_aq_move_recfg_lan_txq
4282 * @hw: pointer to the hardware structure
4283 * @num_qs: number of queues to move/reconfigure
4284 * @is_move: true if this operation involves node movement
4285 * @is_tc_change: true if this operation involves a TC change
4286 * @subseq_call: true if this operation is a subsequent call
4287 * @flush_pipe: on timeout, true to flush pipe, false to return EAGAIN
4288 * @timeout: timeout in units of 100 usec (valid values 0-50)
4289 * @blocked_cgds: out param, bitmap of CGDs that timed out if returning EAGAIN
4290 * @buf: struct containing src/dest TEID and per-queue info
4291 * @buf_size: size of buffer for indirect command
4292 * @txqs_moved: out param, number of queues successfully moved
4293 * @cd: pointer to command details structure or NULL
4295 * Move / Reconfigure Tx LAN queues (0x0C32)
4298 ice_aq_move_recfg_lan_txq(struct ice_hw *hw, u8 num_qs, bool is_move,
4299 bool is_tc_change, bool subseq_call, bool flush_pipe,
4300 u8 timeout, u32 *blocked_cgds,
4301 struct ice_aqc_move_txqs_data *buf, u16 buf_size,
4302 u8 *txqs_moved, struct ice_sq_cd *cd)
4304 struct ice_aqc_move_txqs *cmd;
4305 struct ice_aq_desc desc;
4306 enum ice_status status;
4308 cmd = &desc.params.move_txqs;
4309 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_move_recfg_txqs);
4311 #define ICE_LAN_TXQ_MOVE_TIMEOUT_MAX 50
4312 if (timeout > ICE_LAN_TXQ_MOVE_TIMEOUT_MAX)
4313 return ICE_ERR_PARAM;
4315 if (is_tc_change && !flush_pipe && !blocked_cgds)
4316 return ICE_ERR_PARAM;
4318 if (!is_move && !is_tc_change)
4319 return ICE_ERR_PARAM;
4321 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
4324 cmd->cmd_type |= ICE_AQC_Q_CMD_TYPE_MOVE;
4327 cmd->cmd_type |= ICE_AQC_Q_CMD_TYPE_TC_CHANGE;
4330 cmd->cmd_type |= ICE_AQC_Q_CMD_SUBSEQ_CALL;
4333 cmd->cmd_type |= ICE_AQC_Q_CMD_FLUSH_PIPE;
4335 cmd->num_qs = num_qs;
4336 cmd->timeout = ((timeout << ICE_AQC_Q_CMD_TIMEOUT_S) &
4337 ICE_AQC_Q_CMD_TIMEOUT_M);
4339 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);
4341 if (!status && txqs_moved)
4342 *txqs_moved = cmd->num_qs;
4344 if (hw->adminq.sq_last_status == ICE_AQ_RC_EAGAIN &&
4345 is_tc_change && !flush_pipe)
4346 *blocked_cgds = LE32_TO_CPU(cmd->blocked_cgds);
4351 /* End of FW Admin Queue command wrappers */
4354 * ice_write_byte - write a byte to a packed context structure
4355 * @src_ctx: the context structure to read from
4356 * @dest_ctx: the context to be written to
4357 * @ce_info: a description of the struct to be filled
4360 ice_write_byte(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)
4362 u8 src_byte, dest_byte, mask;
4366 /* copy from the next struct field */
4367 from = src_ctx + ce_info->offset;
4369 /* prepare the bits and mask */
4370 shift_width = ce_info->lsb % 8;
4371 mask = (u8)(BIT(ce_info->width) - 1);
4376 /* shift to correct alignment */
4377 mask <<= shift_width;
4378 src_byte <<= shift_width;
4380 /* get the current bits from the target bit string */
4381 dest = dest_ctx + (ce_info->lsb / 8);
4383 ice_memcpy(&dest_byte, dest, sizeof(dest_byte), ICE_DMA_TO_NONDMA);
4385 dest_byte &= ~mask; /* get the bits not changing */
4386 dest_byte |= src_byte; /* add in the new bits */
4388 /* put it all back */
4389 ice_memcpy(dest, &dest_byte, sizeof(dest_byte), ICE_NONDMA_TO_DMA);
4393 * ice_write_word - write a word to a packed context structure
4394 * @src_ctx: the context structure to read from
4395 * @dest_ctx: the context to be written to
4396 * @ce_info: a description of the struct to be filled
4399 ice_write_word(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)
4406 /* copy from the next struct field */
4407 from = src_ctx + ce_info->offset;
4409 /* prepare the bits and mask */
4410 shift_width = ce_info->lsb % 8;
4411 mask = BIT(ce_info->width) - 1;
4413 /* don't swizzle the bits until after the mask because the mask bits
4414 * will be in a different bit position on big endian machines
4416 src_word = *(u16 *)from;
4419 /* shift to correct alignment */
4420 mask <<= shift_width;
4421 src_word <<= shift_width;
4423 /* get the current bits from the target bit string */
4424 dest = dest_ctx + (ce_info->lsb / 8);
4426 ice_memcpy(&dest_word, dest, sizeof(dest_word), ICE_DMA_TO_NONDMA);
4428 dest_word &= ~(CPU_TO_LE16(mask)); /* get the bits not changing */
4429 dest_word |= CPU_TO_LE16(src_word); /* add in the new bits */
4431 /* put it all back */
4432 ice_memcpy(dest, &dest_word, sizeof(dest_word), ICE_NONDMA_TO_DMA);
4436 * ice_write_dword - write a dword to a packed context structure
4437 * @src_ctx: the context structure to read from
4438 * @dest_ctx: the context to be written to
4439 * @ce_info: a description of the struct to be filled
4442 ice_write_dword(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)
4444 u32 src_dword, mask;
4449 /* copy from the next struct field */
4450 from = src_ctx + ce_info->offset;
4452 /* prepare the bits and mask */
4453 shift_width = ce_info->lsb % 8;
4455 /* if the field width is exactly 32 on an x86 machine, then the shift
4456 * operation will not work because the SHL instructions count is masked
4457 * to 5 bits so the shift will do nothing
4459 if (ce_info->width < 32)
4460 mask = BIT(ce_info->width) - 1;
4464 /* don't swizzle the bits until after the mask because the mask bits
4465 * will be in a different bit position on big endian machines
4467 src_dword = *(u32 *)from;
4470 /* shift to correct alignment */
4471 mask <<= shift_width;
4472 src_dword <<= shift_width;
4474 /* get the current bits from the target bit string */
4475 dest = dest_ctx + (ce_info->lsb / 8);
4477 ice_memcpy(&dest_dword, dest, sizeof(dest_dword), ICE_DMA_TO_NONDMA);
4479 dest_dword &= ~(CPU_TO_LE32(mask)); /* get the bits not changing */
4480 dest_dword |= CPU_TO_LE32(src_dword); /* add in the new bits */
4482 /* put it all back */
4483 ice_memcpy(dest, &dest_dword, sizeof(dest_dword), ICE_NONDMA_TO_DMA);
4487 * ice_write_qword - write a qword to a packed context structure
4488 * @src_ctx: the context structure to read from
4489 * @dest_ctx: the context to be written to
4490 * @ce_info: a description of the struct to be filled
4493 ice_write_qword(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)
4495 u64 src_qword, mask;
4500 /* copy from the next struct field */
4501 from = src_ctx + ce_info->offset;
4503 /* prepare the bits and mask */
4504 shift_width = ce_info->lsb % 8;
4506 /* if the field width is exactly 64 on an x86 machine, then the shift
4507 * operation will not work because the SHL instructions count is masked
4508 * to 6 bits so the shift will do nothing
4510 if (ce_info->width < 64)
4511 mask = BIT_ULL(ce_info->width) - 1;
4515 /* don't swizzle the bits until after the mask because the mask bits
4516 * will be in a different bit position on big endian machines
4518 src_qword = *(u64 *)from;
4521 /* shift to correct alignment */
4522 mask <<= shift_width;
4523 src_qword <<= shift_width;
4525 /* get the current bits from the target bit string */
4526 dest = dest_ctx + (ce_info->lsb / 8);
4528 ice_memcpy(&dest_qword, dest, sizeof(dest_qword), ICE_DMA_TO_NONDMA);
4530 dest_qword &= ~(CPU_TO_LE64(mask)); /* get the bits not changing */
4531 dest_qword |= CPU_TO_LE64(src_qword); /* add in the new bits */
4533 /* put it all back */
4534 ice_memcpy(dest, &dest_qword, sizeof(dest_qword), ICE_NONDMA_TO_DMA);
4538 * ice_set_ctx - set context bits in packed structure
4539 * @hw: pointer to the hardware structure
4540 * @src_ctx: pointer to a generic non-packed context structure
4541 * @dest_ctx: pointer to memory for the packed structure
4542 * @ce_info: a description of the structure to be transformed
4545 ice_set_ctx(struct ice_hw *hw, u8 *src_ctx, u8 *dest_ctx,
4546 const struct ice_ctx_ele *ce_info)
4550 for (f = 0; ce_info[f].width; f++) {
4551 /* We have to deal with each element of the FW response
4552 * using the correct size so that we are correct regardless
4553 * of the endianness of the machine.
4555 if (ce_info[f].width > (ce_info[f].size_of * BITS_PER_BYTE)) {
4556 ice_debug(hw, ICE_DBG_QCTX, "Field %d width of %d bits larger than size of %d byte(s) ... skipping write\n",
4557 f, ce_info[f].width, ce_info[f].size_of);
4560 switch (ce_info[f].size_of) {
4562 ice_write_byte(src_ctx, dest_ctx, &ce_info[f]);
4565 ice_write_word(src_ctx, dest_ctx, &ce_info[f]);
4568 ice_write_dword(src_ctx, dest_ctx, &ce_info[f]);
4571 ice_write_qword(src_ctx, dest_ctx, &ce_info[f]);
4574 return ICE_ERR_INVAL_SIZE;
4582 * ice_aq_get_internal_data
4583 * @hw: pointer to the hardware structure
4584 * @cluster_id: specific cluster to dump
4585 * @table_id: table ID within cluster
4586 * @start: index of line in the block to read
4588 * @buf_size: dump buffer size
4589 * @ret_buf_size: return buffer size (returned by FW)
4590 * @ret_next_table: next block to read (returned by FW)
4591 * @ret_next_index: next index to read (returned by FW)
4592 * @cd: pointer to command details structure
4594 * Get internal FW/HW data (0xFF08) for debug purposes.
4597 ice_aq_get_internal_data(struct ice_hw *hw, u8 cluster_id, u16 table_id,
4598 u32 start, void *buf, u16 buf_size, u16 *ret_buf_size,
4599 u16 *ret_next_table, u32 *ret_next_index,
4600 struct ice_sq_cd *cd)
4602 struct ice_aqc_debug_dump_internals *cmd;
4603 struct ice_aq_desc desc;
4604 enum ice_status status;
4606 cmd = &desc.params.debug_dump;
4608 if (buf_size == 0 || !buf)
4609 return ICE_ERR_PARAM;
4611 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_debug_dump_internals);
4613 cmd->cluster_id = cluster_id;
4614 cmd->table_id = CPU_TO_LE16(table_id);
4615 cmd->idx = CPU_TO_LE32(start);
4617 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);
4621 *ret_buf_size = LE16_TO_CPU(desc.datalen);
4623 *ret_next_table = LE16_TO_CPU(cmd->table_id);
4625 *ret_next_index = LE32_TO_CPU(cmd->idx);
4632 * ice_read_byte - read context byte into struct
4633 * @src_ctx: the context structure to read from
4634 * @dest_ctx: the context to be written to
4635 * @ce_info: a description of the struct to be filled
4638 ice_read_byte(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info)
4644 /* prepare the bits and mask */
4645 shift_width = ce_info->lsb % 8;
4646 mask = (u8)(BIT(ce_info->width) - 1);
4648 /* shift to correct alignment */
4649 mask <<= shift_width;
4651 /* get the current bits from the src bit string */
4652 src = src_ctx + (ce_info->lsb / 8);
4654 ice_memcpy(&dest_byte, src, sizeof(dest_byte), ICE_DMA_TO_NONDMA);
4656 dest_byte &= ~(mask);
4658 dest_byte >>= shift_width;
4660 /* get the address from the struct field */
4661 target = dest_ctx + ce_info->offset;
4663 /* put it back in the struct */
4664 ice_memcpy(target, &dest_byte, sizeof(dest_byte), ICE_NONDMA_TO_DMA);
4668 * ice_read_word - read context word into struct
4669 * @src_ctx: the context structure to read from
4670 * @dest_ctx: the context to be written to
4671 * @ce_info: a description of the struct to be filled
4674 ice_read_word(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info)
4676 u16 dest_word, mask;
4681 /* prepare the bits and mask */
4682 shift_width = ce_info->lsb % 8;
4683 mask = BIT(ce_info->width) - 1;
4685 /* shift to correct alignment */
4686 mask <<= shift_width;
4688 /* get the current bits from the src bit string */
4689 src = src_ctx + (ce_info->lsb / 8);
4691 ice_memcpy(&src_word, src, sizeof(src_word), ICE_DMA_TO_NONDMA);
4693 /* the data in the memory is stored as little endian so mask it
4696 src_word &= ~(CPU_TO_LE16(mask));
4698 /* get the data back into host order before shifting */
4699 dest_word = LE16_TO_CPU(src_word);
4701 dest_word >>= shift_width;
4703 /* get the address from the struct field */
4704 target = dest_ctx + ce_info->offset;
4706 /* put it back in the struct */
4707 ice_memcpy(target, &dest_word, sizeof(dest_word), ICE_NONDMA_TO_DMA);
4711 * ice_read_dword - read context dword into struct
4712 * @src_ctx: the context structure to read from
4713 * @dest_ctx: the context to be written to
4714 * @ce_info: a description of the struct to be filled
4717 ice_read_dword(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info)
4719 u32 dest_dword, mask;
4724 /* prepare the bits and mask */
4725 shift_width = ce_info->lsb % 8;
4727 /* if the field width is exactly 32 on an x86 machine, then the shift
4728 * operation will not work because the SHL instructions count is masked
4729 * to 5 bits so the shift will do nothing
4731 if (ce_info->width < 32)
4732 mask = BIT(ce_info->width) - 1;
4736 /* shift to correct alignment */
4737 mask <<= shift_width;
4739 /* get the current bits from the src bit string */
4740 src = src_ctx + (ce_info->lsb / 8);
4742 ice_memcpy(&src_dword, src, sizeof(src_dword), ICE_DMA_TO_NONDMA);
4744 /* the data in the memory is stored as little endian so mask it
4747 src_dword &= ~(CPU_TO_LE32(mask));
4749 /* get the data back into host order before shifting */
4750 dest_dword = LE32_TO_CPU(src_dword);
4752 dest_dword >>= shift_width;
4754 /* get the address from the struct field */
4755 target = dest_ctx + ce_info->offset;
4757 /* put it back in the struct */
4758 ice_memcpy(target, &dest_dword, sizeof(dest_dword), ICE_NONDMA_TO_DMA);
4762 * ice_read_qword - read context qword into struct
4763 * @src_ctx: the context structure to read from
4764 * @dest_ctx: the context to be written to
4765 * @ce_info: a description of the struct to be filled
4768 ice_read_qword(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info)
4770 u64 dest_qword, mask;
4775 /* prepare the bits and mask */
4776 shift_width = ce_info->lsb % 8;
4778 /* if the field width is exactly 64 on an x86 machine, then the shift
4779 * operation will not work because the SHL instructions count is masked
4780 * to 6 bits so the shift will do nothing
4782 if (ce_info->width < 64)
4783 mask = BIT_ULL(ce_info->width) - 1;
4787 /* shift to correct alignment */
4788 mask <<= shift_width;
4790 /* get the current bits from the src bit string */
4791 src = src_ctx + (ce_info->lsb / 8);
4793 ice_memcpy(&src_qword, src, sizeof(src_qword), ICE_DMA_TO_NONDMA);
4795 /* the data in the memory is stored as little endian so mask it
4798 src_qword &= ~(CPU_TO_LE64(mask));
4800 /* get the data back into host order before shifting */
4801 dest_qword = LE64_TO_CPU(src_qword);
4803 dest_qword >>= shift_width;
4805 /* get the address from the struct field */
4806 target = dest_ctx + ce_info->offset;
4808 /* put it back in the struct */
4809 ice_memcpy(target, &dest_qword, sizeof(dest_qword), ICE_NONDMA_TO_DMA);
4813 * ice_get_ctx - extract context bits from a packed structure
4814 * @src_ctx: pointer to a generic packed context structure
4815 * @dest_ctx: pointer to a generic non-packed context structure
4816 * @ce_info: a description of the structure to be read from
4819 ice_get_ctx(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info)
4823 for (f = 0; ce_info[f].width; f++) {
4824 switch (ce_info[f].size_of) {
4826 ice_read_byte(src_ctx, dest_ctx, &ce_info[f]);
4829 ice_read_word(src_ctx, dest_ctx, &ce_info[f]);
4832 ice_read_dword(src_ctx, dest_ctx, &ce_info[f]);
4835 ice_read_qword(src_ctx, dest_ctx, &ce_info[f]);
4838 /* nothing to do, just keep going */
4847 * ice_get_lan_q_ctx - get the LAN queue context for the given VSI and TC
4848 * @hw: pointer to the HW struct
4849 * @vsi_handle: software VSI handle
4851 * @q_handle: software queue handle
4854 ice_get_lan_q_ctx(struct ice_hw *hw, u16 vsi_handle, u8 tc, u16 q_handle)
4856 struct ice_vsi_ctx *vsi;
4857 struct ice_q_ctx *q_ctx;
4859 vsi = ice_get_vsi_ctx(hw, vsi_handle);
4862 if (q_handle >= vsi->num_lan_q_entries[tc])
4864 if (!vsi->lan_q_ctx[tc])
4866 q_ctx = vsi->lan_q_ctx[tc];
4867 return &q_ctx[q_handle];
4872 * @pi: port information structure
4873 * @vsi_handle: software VSI handle
4875 * @q_handle: software queue handle
4876 * @num_qgrps: Number of added queue groups
4877 * @buf: list of queue groups to be added
4878 * @buf_size: size of buffer for indirect command
4879 * @cd: pointer to command details structure or NULL
4881 * This function adds one LAN queue
4884 ice_ena_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u16 q_handle,
4885 u8 num_qgrps, struct ice_aqc_add_tx_qgrp *buf, u16 buf_size,
4886 struct ice_sq_cd *cd)
4888 struct ice_aqc_txsched_elem_data node = { 0 };
4889 struct ice_sched_node *parent;
4890 struct ice_q_ctx *q_ctx;
4891 enum ice_status status;
4894 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY)
4897 if (num_qgrps > 1 || buf->num_txqs > 1)
4898 return ICE_ERR_MAX_LIMIT;
4902 if (!ice_is_vsi_valid(hw, vsi_handle))
4903 return ICE_ERR_PARAM;
4905 ice_acquire_lock(&pi->sched_lock);
4907 q_ctx = ice_get_lan_q_ctx(hw, vsi_handle, tc, q_handle);
4909 ice_debug(hw, ICE_DBG_SCHED, "Enaq: invalid queue handle %d\n",
4911 status = ICE_ERR_PARAM;
4915 /* find a parent node */
4916 parent = ice_sched_get_free_qparent(pi, vsi_handle, tc,
4917 ICE_SCHED_NODE_OWNER_LAN);
4919 status = ICE_ERR_PARAM;
4923 buf->parent_teid = parent->info.node_teid;
4924 node.parent_teid = parent->info.node_teid;
4925 /* Mark that the values in the "generic" section as valid. The default
4926 * value in the "generic" section is zero. This means that :
4927 * - Scheduling mode is Bytes Per Second (BPS), indicated by Bit 0.
4928 * - 0 priority among siblings, indicated by Bit 1-3.
4929 * - WFQ, indicated by Bit 4.
4930 * - 0 Adjustment value is used in PSM credit update flow, indicated by
4932 * - Bit 7 is reserved.
4933 * Without setting the generic section as valid in valid_sections, the
4934 * Admin queue command will fail with error code ICE_AQ_RC_EINVAL.
4936 buf->txqs[0].info.valid_sections =
4937 ICE_AQC_ELEM_VALID_GENERIC | ICE_AQC_ELEM_VALID_CIR |
4938 ICE_AQC_ELEM_VALID_EIR;
4939 buf->txqs[0].info.generic = 0;
4940 buf->txqs[0].info.cir_bw.bw_profile_idx =
4941 CPU_TO_LE16(ICE_SCHED_DFLT_RL_PROF_ID);
4942 buf->txqs[0].info.cir_bw.bw_alloc =
4943 CPU_TO_LE16(ICE_SCHED_DFLT_BW_WT);
4944 buf->txqs[0].info.eir_bw.bw_profile_idx =
4945 CPU_TO_LE16(ICE_SCHED_DFLT_RL_PROF_ID);
4946 buf->txqs[0].info.eir_bw.bw_alloc =
4947 CPU_TO_LE16(ICE_SCHED_DFLT_BW_WT);
4949 /* add the LAN queue */
4950 status = ice_aq_add_lan_txq(hw, num_qgrps, buf, buf_size, cd);
4951 if (status != ICE_SUCCESS) {
4952 ice_debug(hw, ICE_DBG_SCHED, "enable queue %d failed %d\n",
4953 LE16_TO_CPU(buf->txqs[0].txq_id),
4954 hw->adminq.sq_last_status);
4958 node.node_teid = buf->txqs[0].q_teid;
4959 node.data.elem_type = ICE_AQC_ELEM_TYPE_LEAF;
4960 q_ctx->q_handle = q_handle;
4961 q_ctx->q_teid = LE32_TO_CPU(node.node_teid);
4963 /* add a leaf node into scheduler tree queue layer */
4964 status = ice_sched_add_node(pi, hw->num_tx_sched_layers - 1, &node);
4966 status = ice_sched_replay_q_bw(pi, q_ctx);
4969 ice_release_lock(&pi->sched_lock);
4975 * @pi: port information structure
4976 * @vsi_handle: software VSI handle
4978 * @num_queues: number of queues
4979 * @q_handles: pointer to software queue handle array
4980 * @q_ids: pointer to the q_id array
4981 * @q_teids: pointer to queue node teids
4982 * @rst_src: if called due to reset, specifies the reset source
4983 * @vmvf_num: the relative VM or VF number that is undergoing the reset
4984 * @cd: pointer to command details structure or NULL
4986 * This function removes queues and their corresponding nodes in SW DB
4989 ice_dis_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u8 num_queues,
4990 u16 *q_handles, u16 *q_ids, u32 *q_teids,
4991 enum ice_disq_rst_src rst_src, u16 vmvf_num,
4992 struct ice_sq_cd *cd)
4994 enum ice_status status = ICE_ERR_DOES_NOT_EXIST;
4995 struct ice_aqc_dis_txq_item *qg_list;
4996 struct ice_q_ctx *q_ctx;
5000 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY)
5006 /* if queue is disabled already yet the disable queue command
5007 * has to be sent to complete the VF reset, then call
5008 * ice_aq_dis_lan_txq without any queue information
5011 return ice_aq_dis_lan_txq(hw, 0, NULL, 0, rst_src,
5016 buf_size = ice_struct_size(qg_list, q_id, 1);
5017 qg_list = (struct ice_aqc_dis_txq_item *)ice_malloc(hw, buf_size);
5019 return ICE_ERR_NO_MEMORY;
5021 ice_acquire_lock(&pi->sched_lock);
5023 for (i = 0; i < num_queues; i++) {
5024 struct ice_sched_node *node;
5026 node = ice_sched_find_node_by_teid(pi->root, q_teids[i]);
5029 q_ctx = ice_get_lan_q_ctx(hw, vsi_handle, tc, q_handles[i]);
5031 ice_debug(hw, ICE_DBG_SCHED, "invalid queue handle%d\n",
5035 if (q_ctx->q_handle != q_handles[i]) {
5036 ice_debug(hw, ICE_DBG_SCHED, "Err:handles %d %d\n",
5037 q_ctx->q_handle, q_handles[i]);
5040 qg_list->parent_teid = node->info.parent_teid;
5041 qg_list->num_qs = 1;
5042 qg_list->q_id[0] = CPU_TO_LE16(q_ids[i]);
5043 status = ice_aq_dis_lan_txq(hw, 1, qg_list, buf_size, rst_src,
5046 if (status != ICE_SUCCESS)
5048 ice_free_sched_node(pi, node);
5049 q_ctx->q_handle = ICE_INVAL_Q_HANDLE;
5051 ice_release_lock(&pi->sched_lock);
5052 ice_free(hw, qg_list);
5057 * ice_cfg_vsi_qs - configure the new/existing VSI queues
5058 * @pi: port information structure
5059 * @vsi_handle: software VSI handle
5060 * @tc_bitmap: TC bitmap
5061 * @maxqs: max queues array per TC
5062 * @owner: LAN or RDMA
5064 * This function adds/updates the VSI queues per TC.
5066 static enum ice_status
5067 ice_cfg_vsi_qs(struct ice_port_info *pi, u16 vsi_handle, u16 tc_bitmap,
5068 u16 *maxqs, u8 owner)
5070 enum ice_status status = ICE_SUCCESS;
5073 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY)
5076 if (!ice_is_vsi_valid(pi->hw, vsi_handle))
5077 return ICE_ERR_PARAM;
5079 ice_acquire_lock(&pi->sched_lock);
5081 ice_for_each_traffic_class(i) {
5082 /* configuration is possible only if TC node is present */
5083 if (!ice_sched_get_tc_node(pi, i))
5086 status = ice_sched_cfg_vsi(pi, vsi_handle, i, maxqs[i], owner,
5087 ice_is_tc_ena(tc_bitmap, i));
5092 ice_release_lock(&pi->sched_lock);
5097 * ice_cfg_vsi_lan - configure VSI LAN queues
5098 * @pi: port information structure
5099 * @vsi_handle: software VSI handle
5100 * @tc_bitmap: TC bitmap
5101 * @max_lanqs: max LAN queues array per TC
5103 * This function adds/updates the VSI LAN queues per TC.
5106 ice_cfg_vsi_lan(struct ice_port_info *pi, u16 vsi_handle, u16 tc_bitmap,
5109 return ice_cfg_vsi_qs(pi, vsi_handle, tc_bitmap, max_lanqs,
5110 ICE_SCHED_NODE_OWNER_LAN);
5114 * ice_is_main_vsi - checks whether the VSI is main VSI
5115 * @hw: pointer to the HW struct
5116 * @vsi_handle: VSI handle
5118 * Checks whether the VSI is the main VSI (the first PF VSI created on
5121 static bool ice_is_main_vsi(struct ice_hw *hw, u16 vsi_handle)
5123 return vsi_handle == ICE_MAIN_VSI_HANDLE && hw->vsi_ctx[vsi_handle];
5127 * ice_replay_pre_init - replay pre initialization
5128 * @hw: pointer to the HW struct
5129 * @sw: pointer to switch info struct for which function initializes filters
5131 * Initializes required config data for VSI, FD, ACL, and RSS before replay.
5134 ice_replay_pre_init(struct ice_hw *hw, struct ice_switch_info *sw)
5136 enum ice_status status;
5139 /* Delete old entries from replay filter list head if there is any */
5140 ice_rm_sw_replay_rule_info(hw, sw);
5141 /* In start of replay, move entries into replay_rules list, it
5142 * will allow adding rules entries back to filt_rules list,
5143 * which is operational list.
5145 for (i = 0; i < ICE_MAX_NUM_RECIPES; i++)
5146 LIST_REPLACE_INIT(&sw->recp_list[i].filt_rules,
5147 &sw->recp_list[i].filt_replay_rules);
5148 ice_sched_replay_agg_vsi_preinit(hw);
5150 status = ice_sched_replay_root_node_bw(hw->port_info);
5154 return ice_sched_replay_tc_node_bw(hw->port_info);
5158 * ice_replay_vsi - replay VSI configuration
5159 * @hw: pointer to the HW struct
5160 * @vsi_handle: driver VSI handle
5162 * Restore all VSI configuration after reset. It is required to call this
5163 * function with main VSI first.
5165 enum ice_status ice_replay_vsi(struct ice_hw *hw, u16 vsi_handle)
5167 struct ice_switch_info *sw = hw->switch_info;
5168 struct ice_port_info *pi = hw->port_info;
5169 enum ice_status status;
5171 if (!ice_is_vsi_valid(hw, vsi_handle))
5172 return ICE_ERR_PARAM;
5174 /* Replay pre-initialization if there is any */
5175 if (ice_is_main_vsi(hw, vsi_handle)) {
5176 status = ice_replay_pre_init(hw, sw);
5180 /* Replay per VSI all RSS configurations */
5181 status = ice_replay_rss_cfg(hw, vsi_handle);
5184 /* Replay per VSI all filters */
5185 status = ice_replay_vsi_all_fltr(hw, pi, vsi_handle);
5187 status = ice_replay_vsi_agg(hw, vsi_handle);
5192 * ice_replay_post - post replay configuration cleanup
5193 * @hw: pointer to the HW struct
5195 * Post replay cleanup.
5197 void ice_replay_post(struct ice_hw *hw)
5199 /* Delete old entries from replay filter list head */
5200 ice_rm_all_sw_replay_rule_info(hw);
5201 ice_sched_replay_agg(hw);
5205 * ice_stat_update40 - read 40 bit stat from the chip and update stat values
5206 * @hw: ptr to the hardware info
5207 * @reg: offset of 64 bit HW register to read from
5208 * @prev_stat_loaded: bool to specify if previous stats are loaded
5209 * @prev_stat: ptr to previous loaded stat value
5210 * @cur_stat: ptr to current stat value
5213 ice_stat_update40(struct ice_hw *hw, u32 reg, bool prev_stat_loaded,
5214 u64 *prev_stat, u64 *cur_stat)
5216 u64 new_data = rd64(hw, reg) & (BIT_ULL(40) - 1);
5218 /* device stats are not reset at PFR, they likely will not be zeroed
5219 * when the driver starts. Thus, save the value from the first read
5220 * without adding to the statistic value so that we report stats which
5221 * count up from zero.
5223 if (!prev_stat_loaded) {
5224 *prev_stat = new_data;
5228 /* Calculate the difference between the new and old values, and then
5229 * add it to the software stat value.
5231 if (new_data >= *prev_stat)
5232 *cur_stat += new_data - *prev_stat;
5234 /* to manage the potential roll-over */
5235 *cur_stat += (new_data + BIT_ULL(40)) - *prev_stat;
5237 /* Update the previously stored value to prepare for next read */
5238 *prev_stat = new_data;
5242 * ice_stat_update32 - read 32 bit stat from the chip and update stat values
5243 * @hw: ptr to the hardware info
5244 * @reg: offset of HW register to read from
5245 * @prev_stat_loaded: bool to specify if previous stats are loaded
5246 * @prev_stat: ptr to previous loaded stat value
5247 * @cur_stat: ptr to current stat value
5250 ice_stat_update32(struct ice_hw *hw, u32 reg, bool prev_stat_loaded,
5251 u64 *prev_stat, u64 *cur_stat)
5255 new_data = rd32(hw, reg);
5257 /* device stats are not reset at PFR, they likely will not be zeroed
5258 * when the driver starts. Thus, save the value from the first read
5259 * without adding to the statistic value so that we report stats which
5260 * count up from zero.
5262 if (!prev_stat_loaded) {
5263 *prev_stat = new_data;
5267 /* Calculate the difference between the new and old values, and then
5268 * add it to the software stat value.
5270 if (new_data >= *prev_stat)
5271 *cur_stat += new_data - *prev_stat;
5273 /* to manage the potential roll-over */
5274 *cur_stat += (new_data + BIT_ULL(32)) - *prev_stat;
5276 /* Update the previously stored value to prepare for next read */
5277 *prev_stat = new_data;
5281 * ice_stat_update_repc - read GLV_REPC stats from chip and update stat values
5282 * @hw: ptr to the hardware info
5283 * @vsi_handle: VSI handle
5284 * @prev_stat_loaded: bool to specify if the previous stat values are loaded
5285 * @cur_stats: ptr to current stats structure
5287 * The GLV_REPC statistic register actually tracks two 16bit statistics, and
5288 * thus cannot be read using the normal ice_stat_update32 function.
5290 * Read the GLV_REPC register associated with the given VSI, and update the
5291 * rx_no_desc and rx_error values in the ice_eth_stats structure.
5293 * Because the statistics in GLV_REPC stick at 0xFFFF, the register must be
5294 * cleared each time it's read.
5296 * Note that the GLV_RDPC register also counts the causes that would trigger
5297 * GLV_REPC. However, it does not give the finer grained detail about why the
5298 * packets are being dropped. The GLV_REPC values can be used to distinguish
5299 * whether Rx packets are dropped due to errors or due to no available
5303 ice_stat_update_repc(struct ice_hw *hw, u16 vsi_handle, bool prev_stat_loaded,
5304 struct ice_eth_stats *cur_stats)
5306 u16 vsi_num, no_desc, error_cnt;
5309 if (!ice_is_vsi_valid(hw, vsi_handle))
5312 vsi_num = ice_get_hw_vsi_num(hw, vsi_handle);
5314 /* If we haven't loaded stats yet, just clear the current value */
5315 if (!prev_stat_loaded) {
5316 wr32(hw, GLV_REPC(vsi_num), 0);
5320 repc = rd32(hw, GLV_REPC(vsi_num));
5321 no_desc = (repc & GLV_REPC_NO_DESC_CNT_M) >> GLV_REPC_NO_DESC_CNT_S;
5322 error_cnt = (repc & GLV_REPC_ERROR_CNT_M) >> GLV_REPC_ERROR_CNT_S;
5324 /* Clear the count by writing to the stats register */
5325 wr32(hw, GLV_REPC(vsi_num), 0);
5327 cur_stats->rx_no_desc += no_desc;
5328 cur_stats->rx_errors += error_cnt;
5332 * ice_sched_query_elem - query element information from HW
5333 * @hw: pointer to the HW struct
5334 * @node_teid: node TEID to be queried
5335 * @buf: buffer to element information
5337 * This function queries HW element information
5340 ice_sched_query_elem(struct ice_hw *hw, u32 node_teid,
5341 struct ice_aqc_txsched_elem_data *buf)
5343 u16 buf_size, num_elem_ret = 0;
5344 enum ice_status status;
5346 buf_size = sizeof(*buf);
5347 ice_memset(buf, 0, buf_size, ICE_NONDMA_MEM);
5348 buf->node_teid = CPU_TO_LE32(node_teid);
5349 status = ice_aq_query_sched_elems(hw, 1, buf, buf_size, &num_elem_ret,
5351 if (status != ICE_SUCCESS || num_elem_ret != 1)
5352 ice_debug(hw, ICE_DBG_SCHED, "query element failed\n");
5357 * ice_get_fw_mode - returns FW mode
5358 * @hw: pointer to the HW struct
5360 enum ice_fw_modes ice_get_fw_mode(struct ice_hw *hw)
5362 #define ICE_FW_MODE_DBG_M BIT(0)
5363 #define ICE_FW_MODE_REC_M BIT(1)
5364 #define ICE_FW_MODE_ROLLBACK_M BIT(2)
5367 /* check the current FW mode */
5368 fw_mode = rd32(hw, GL_MNG_FWSM) & GL_MNG_FWSM_FW_MODES_M;
5370 if (fw_mode & ICE_FW_MODE_DBG_M)
5371 return ICE_FW_MODE_DBG;
5372 else if (fw_mode & ICE_FW_MODE_REC_M)
5373 return ICE_FW_MODE_REC;
5374 else if (fw_mode & ICE_FW_MODE_ROLLBACK_M)
5375 return ICE_FW_MODE_ROLLBACK;
5377 return ICE_FW_MODE_NORMAL;
5382 * @hw: pointer to the hw struct
5383 * @topo_addr: topology address for a device to communicate with
5384 * @bus_addr: 7-bit I2C bus address
5385 * @addr: I2C memory address (I2C offset) with up to 16 bits
5386 * @params: I2C parameters: bit [7] - Repeated start, bits [6:5] data offset size,
5387 * bit [4] - I2C address type, bits [3:0] - data size to read (0-16 bytes)
5388 * @data: pointer to data (0 to 16 bytes) to be read from the I2C device
5389 * @cd: pointer to command details structure or NULL
5394 ice_aq_read_i2c(struct ice_hw *hw, struct ice_aqc_link_topo_addr topo_addr,
5395 u16 bus_addr, __le16 addr, u8 params, u8 *data,
5396 struct ice_sq_cd *cd)
5398 struct ice_aq_desc desc = { 0 };
5399 struct ice_aqc_i2c *cmd;
5400 enum ice_status status;
5403 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_read_i2c);
5404 cmd = &desc.params.read_write_i2c;
5407 return ICE_ERR_PARAM;
5409 data_size = (params & ICE_AQC_I2C_DATA_SIZE_M) >> ICE_AQC_I2C_DATA_SIZE_S;
5411 cmd->i2c_bus_addr = CPU_TO_LE16(bus_addr);
5412 cmd->topo_addr = topo_addr;
5413 cmd->i2c_params = params;
5414 cmd->i2c_addr = addr;
5416 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
5418 struct ice_aqc_read_i2c_resp *resp;
5421 resp = &desc.params.read_i2c_resp;
5422 for (i = 0; i < data_size; i++) {
5423 *data = resp->i2c_data[i];
5433 * @hw: pointer to the hw struct
5434 * @topo_addr: topology address for a device to communicate with
5435 * @bus_addr: 7-bit I2C bus address
5436 * @addr: I2C memory address (I2C offset) with up to 16 bits
5437 * @params: I2C parameters: bit [4] - I2C address type, bits [3:0] - data size to write (0-7 bytes)
5438 * @data: pointer to data (0 to 4 bytes) to be written to the I2C device
5439 * @cd: pointer to command details structure or NULL
5441 * Write I2C (0x06E3)
5444 ice_aq_write_i2c(struct ice_hw *hw, struct ice_aqc_link_topo_addr topo_addr,
5445 u16 bus_addr, __le16 addr, u8 params, u8 *data,
5446 struct ice_sq_cd *cd)
5448 struct ice_aq_desc desc = { 0 };
5449 struct ice_aqc_i2c *cmd;
5452 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_write_i2c);
5453 cmd = &desc.params.read_write_i2c;
5455 data_size = (params & ICE_AQC_I2C_DATA_SIZE_M) >> ICE_AQC_I2C_DATA_SIZE_S;
5457 /* data_size limited to 4 */
5459 return ICE_ERR_PARAM;
5461 cmd->i2c_bus_addr = CPU_TO_LE16(bus_addr);
5462 cmd->topo_addr = topo_addr;
5463 cmd->i2c_params = params;
5464 cmd->i2c_addr = addr;
5466 for (i = 0; i < data_size; i++) {
5467 cmd->i2c_data[i] = *data;
5471 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
5476 * @hw: pointer to the hw struct
5477 * @gpio_ctrl_handle: GPIO controller node handle
5478 * @pin_idx: IO Number of the GPIO that needs to be set
5479 * @value: SW provide IO value to set in the LSB
5480 * @cd: pointer to command details structure or NULL
5482 * Sends 0x06EC AQ command to set the GPIO pin state that's part of the topology
5485 ice_aq_set_gpio(struct ice_hw *hw, u16 gpio_ctrl_handle, u8 pin_idx, bool value,
5486 struct ice_sq_cd *cd)
5488 struct ice_aqc_gpio *cmd;
5489 struct ice_aq_desc desc;
5491 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_gpio);
5492 cmd = &desc.params.read_write_gpio;
5493 cmd->gpio_ctrl_handle = gpio_ctrl_handle;
5494 cmd->gpio_num = pin_idx;
5495 cmd->gpio_val = value ? 1 : 0;
5497 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
5502 * @hw: pointer to the hw struct
5503 * @gpio_ctrl_handle: GPIO controller node handle
5504 * @pin_idx: IO Number of the GPIO that needs to be set
5505 * @value: IO value read
5506 * @cd: pointer to command details structure or NULL
5508 * Sends 0x06ED AQ command to get the value of a GPIO signal which is part of
5512 ice_aq_get_gpio(struct ice_hw *hw, u16 gpio_ctrl_handle, u8 pin_idx,
5513 bool *value, struct ice_sq_cd *cd)
5515 struct ice_aqc_gpio *cmd;
5516 struct ice_aq_desc desc;
5517 enum ice_status status;
5519 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_gpio);
5520 cmd = &desc.params.read_write_gpio;
5521 cmd->gpio_ctrl_handle = gpio_ctrl_handle;
5522 cmd->gpio_num = pin_idx;
5524 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
5528 *value = !!cmd->gpio_val;
5533 * ice_fw_supports_link_override
5534 * @hw: pointer to the hardware structure
5536 * Checks if the firmware supports link override
5538 bool ice_fw_supports_link_override(struct ice_hw *hw)
5540 if (hw->api_maj_ver == ICE_FW_API_LINK_OVERRIDE_MAJ) {
5541 if (hw->api_min_ver > ICE_FW_API_LINK_OVERRIDE_MIN)
5543 if (hw->api_min_ver == ICE_FW_API_LINK_OVERRIDE_MIN &&
5544 hw->api_patch >= ICE_FW_API_LINK_OVERRIDE_PATCH)
5546 } else if (hw->api_maj_ver > ICE_FW_API_LINK_OVERRIDE_MAJ) {
5554 * ice_get_link_default_override
5555 * @ldo: pointer to the link default override struct
5556 * @pi: pointer to the port info struct
5558 * Gets the link default override for a port
5561 ice_get_link_default_override(struct ice_link_default_override_tlv *ldo,
5562 struct ice_port_info *pi)
5564 u16 i, tlv, tlv_len, tlv_start, buf, offset;
5565 struct ice_hw *hw = pi->hw;
5566 enum ice_status status;
5568 status = ice_get_pfa_module_tlv(hw, &tlv, &tlv_len,
5569 ICE_SR_LINK_DEFAULT_OVERRIDE_PTR);
5571 ice_debug(hw, ICE_DBG_INIT, "Failed to read link override TLV.\n");
5575 /* Each port has its own config; calculate for our port */
5576 tlv_start = tlv + pi->lport * ICE_SR_PFA_LINK_OVERRIDE_WORDS +
5577 ICE_SR_PFA_LINK_OVERRIDE_OFFSET;
5579 /* link options first */
5580 status = ice_read_sr_word(hw, tlv_start, &buf);
5582 ice_debug(hw, ICE_DBG_INIT, "Failed to read override link options.\n");
5585 ldo->options = buf & ICE_LINK_OVERRIDE_OPT_M;
5586 ldo->phy_config = (buf & ICE_LINK_OVERRIDE_PHY_CFG_M) >>
5587 ICE_LINK_OVERRIDE_PHY_CFG_S;
5589 /* link PHY config */
5590 offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_FEC_OFFSET;
5591 status = ice_read_sr_word(hw, offset, &buf);
5593 ice_debug(hw, ICE_DBG_INIT, "Failed to read override phy config.\n");
5596 ldo->fec_options = buf & ICE_LINK_OVERRIDE_FEC_OPT_M;
5599 offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_PHY_OFFSET;
5600 for (i = 0; i < ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS; i++) {
5601 status = ice_read_sr_word(hw, (offset + i), &buf);
5603 ice_debug(hw, ICE_DBG_INIT, "Failed to read override link options.\n");
5606 /* shift 16 bits at a time to fill 64 bits */
5607 ldo->phy_type_low |= ((u64)buf << (i * 16));
5610 /* PHY types high */
5611 offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_PHY_OFFSET +
5612 ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS;
5613 for (i = 0; i < ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS; i++) {
5614 status = ice_read_sr_word(hw, (offset + i), &buf);
5616 ice_debug(hw, ICE_DBG_INIT, "Failed to read override link options.\n");
5619 /* shift 16 bits at a time to fill 64 bits */
5620 ldo->phy_type_high |= ((u64)buf << (i * 16));
5627 * ice_is_phy_caps_an_enabled - check if PHY capabilities autoneg is enabled
5628 * @caps: get PHY capability data
5630 bool ice_is_phy_caps_an_enabled(struct ice_aqc_get_phy_caps_data *caps)
5632 if (caps->caps & ICE_AQC_PHY_AN_MODE ||
5633 caps->low_power_ctrl_an & (ICE_AQC_PHY_AN_EN_CLAUSE28 |
5634 ICE_AQC_PHY_AN_EN_CLAUSE73 |
5635 ICE_AQC_PHY_AN_EN_CLAUSE37))
5642 * ice_aq_set_lldp_mib - Set the LLDP MIB
5643 * @hw: pointer to the HW struct
5644 * @mib_type: Local, Remote or both Local and Remote MIBs
5645 * @buf: pointer to the caller-supplied buffer to store the MIB block
5646 * @buf_size: size of the buffer (in bytes)
5647 * @cd: pointer to command details structure or NULL
5649 * Set the LLDP MIB. (0x0A08)
5652 ice_aq_set_lldp_mib(struct ice_hw *hw, u8 mib_type, void *buf, u16 buf_size,
5653 struct ice_sq_cd *cd)
5655 struct ice_aqc_lldp_set_local_mib *cmd;
5656 struct ice_aq_desc desc;
5658 cmd = &desc.params.lldp_set_mib;
5660 if (buf_size == 0 || !buf)
5661 return ICE_ERR_PARAM;
5663 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_lldp_set_local_mib);
5665 desc.flags |= CPU_TO_LE16((u16)ICE_AQ_FLAG_RD);
5666 desc.datalen = CPU_TO_LE16(buf_size);
5668 cmd->type = mib_type;
5669 cmd->length = CPU_TO_LE16(buf_size);
5671 return ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);
5675 * ice_fw_supports_lldp_fltr_ctrl - check NVM version supports lldp_fltr_ctrl
5676 * @hw: pointer to HW struct
5678 bool ice_fw_supports_lldp_fltr_ctrl(struct ice_hw *hw)
5680 if (hw->mac_type != ICE_MAC_E810)
5683 if (hw->api_maj_ver == ICE_FW_API_LLDP_FLTR_MAJ) {
5684 if (hw->api_min_ver > ICE_FW_API_LLDP_FLTR_MIN)
5686 if (hw->api_min_ver == ICE_FW_API_LLDP_FLTR_MIN &&
5687 hw->api_patch >= ICE_FW_API_LLDP_FLTR_PATCH)
5689 } else if (hw->api_maj_ver > ICE_FW_API_LLDP_FLTR_MAJ) {
5696 * ice_lldp_fltr_add_remove - add or remove a LLDP Rx switch filter
5697 * @hw: pointer to HW struct
5698 * @vsi_num: absolute HW index for VSI
5699 * @add: boolean for if adding or removing a filter
5702 ice_lldp_fltr_add_remove(struct ice_hw *hw, u16 vsi_num, bool add)
5704 struct ice_aqc_lldp_filter_ctrl *cmd;
5705 struct ice_aq_desc desc;
5707 cmd = &desc.params.lldp_filter_ctrl;
5709 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_lldp_filter_ctrl);
5712 cmd->cmd_flags = ICE_AQC_LLDP_FILTER_ACTION_ADD;
5714 cmd->cmd_flags = ICE_AQC_LLDP_FILTER_ACTION_DELETE;
5716 cmd->vsi_num = CPU_TO_LE16(vsi_num);
5718 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
5722 * ice_fw_supports_report_dflt_cfg
5723 * @hw: pointer to the hardware structure
5725 * Checks if the firmware supports report default configuration
5727 bool ice_fw_supports_report_dflt_cfg(struct ice_hw *hw)
5729 if (hw->api_maj_ver == ICE_FW_API_REPORT_DFLT_CFG_MAJ) {
5730 if (hw->api_min_ver > ICE_FW_API_REPORT_DFLT_CFG_MIN)
5732 if (hw->api_min_ver == ICE_FW_API_REPORT_DFLT_CFG_MIN &&
5733 hw->api_patch >= ICE_FW_API_REPORT_DFLT_CFG_PATCH)
5735 } else if (hw->api_maj_ver > ICE_FW_API_REPORT_DFLT_CFG_MAJ) {