1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2001-2020 Intel Corporation
5 #include "ice_common.h"
7 #include "ice_adminq_cmd.h"
10 #include "ice_switch.h"
12 #define ICE_PF_RESET_WAIT_COUNT 300
15 * ice_set_mac_type - Sets MAC type
16 * @hw: pointer to the HW structure
18 * This function sets the MAC type of the adapter based on the
19 * vendor ID and device ID stored in the HW structure.
21 static enum ice_status ice_set_mac_type(struct ice_hw *hw)
23 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
25 if (hw->vendor_id != ICE_INTEL_VENDOR_ID)
26 return ICE_ERR_DEVICE_NOT_SUPPORTED;
28 switch (hw->device_id) {
29 case ICE_DEV_ID_E810C_BACKPLANE:
30 case ICE_DEV_ID_E810C_QSFP:
31 case ICE_DEV_ID_E810C_SFP:
32 case ICE_DEV_ID_E810_XXV_BACKPLANE:
33 case ICE_DEV_ID_E810_XXV_QSFP:
34 case ICE_DEV_ID_E810_XXV_SFP:
35 hw->mac_type = ICE_MAC_E810;
37 case ICE_DEV_ID_E822C_10G_BASE_T:
38 case ICE_DEV_ID_E822C_BACKPLANE:
39 case ICE_DEV_ID_E822C_QSFP:
40 case ICE_DEV_ID_E822C_SFP:
41 case ICE_DEV_ID_E822C_SGMII:
42 case ICE_DEV_ID_E822L_10G_BASE_T:
43 case ICE_DEV_ID_E822L_BACKPLANE:
44 case ICE_DEV_ID_E822L_SFP:
45 case ICE_DEV_ID_E822L_SGMII:
46 case ICE_DEV_ID_E823L_10G_BASE_T:
47 case ICE_DEV_ID_E823L_1GBE:
48 case ICE_DEV_ID_E823L_BACKPLANE:
49 case ICE_DEV_ID_E823L_QSFP:
50 case ICE_DEV_ID_E823L_SFP:
51 hw->mac_type = ICE_MAC_GENERIC;
54 hw->mac_type = ICE_MAC_UNKNOWN;
58 ice_debug(hw, ICE_DBG_INIT, "mac_type: %d\n", hw->mac_type);
63 * ice_clear_pf_cfg - Clear PF configuration
64 * @hw: pointer to the hardware structure
66 * Clears any existing PF configuration (VSIs, VSI lists, switch rules, port
67 * configuration, flow director filters, etc.).
69 enum ice_status ice_clear_pf_cfg(struct ice_hw *hw)
71 struct ice_aq_desc desc;
73 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pf_cfg);
75 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
79 * ice_aq_manage_mac_read - manage MAC address read command
80 * @hw: pointer to the HW struct
81 * @buf: a virtual buffer to hold the manage MAC read response
82 * @buf_size: Size of the virtual buffer
83 * @cd: pointer to command details structure or NULL
85 * This function is used to return per PF station MAC address (0x0107).
86 * NOTE: Upon successful completion of this command, MAC address information
87 * is returned in user specified buffer. Please interpret user specified
88 * buffer as "manage_mac_read" response.
89 * Response such as various MAC addresses are stored in HW struct (port.mac)
90 * ice_discover_dev_caps is expected to be called before this function is
93 static enum ice_status
94 ice_aq_manage_mac_read(struct ice_hw *hw, void *buf, u16 buf_size,
97 struct ice_aqc_manage_mac_read_resp *resp;
98 struct ice_aqc_manage_mac_read *cmd;
99 struct ice_aq_desc desc;
100 enum ice_status status;
104 cmd = &desc.params.mac_read;
106 if (buf_size < sizeof(*resp))
107 return ICE_ERR_BUF_TOO_SHORT;
109 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_read);
111 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);
115 resp = (struct ice_aqc_manage_mac_read_resp *)buf;
116 flags = LE16_TO_CPU(cmd->flags) & ICE_AQC_MAN_MAC_READ_M;
118 if (!(flags & ICE_AQC_MAN_MAC_LAN_ADDR_VALID)) {
119 ice_debug(hw, ICE_DBG_LAN, "got invalid MAC address\n");
123 /* A single port can report up to two (LAN and WoL) addresses */
124 for (i = 0; i < cmd->num_addr; i++)
125 if (resp[i].addr_type == ICE_AQC_MAN_MAC_ADDR_TYPE_LAN) {
126 ice_memcpy(hw->port_info->mac.lan_addr,
127 resp[i].mac_addr, ETH_ALEN,
129 ice_memcpy(hw->port_info->mac.perm_addr,
131 ETH_ALEN, ICE_DMA_TO_NONDMA);
138 * ice_aq_get_phy_caps - returns PHY capabilities
139 * @pi: port information structure
140 * @qual_mods: report qualified modules
141 * @report_mode: report mode capabilities
142 * @pcaps: structure for PHY capabilities to be filled
143 * @cd: pointer to command details structure or NULL
145 * Returns the various PHY capabilities supported on the Port (0x0600)
148 ice_aq_get_phy_caps(struct ice_port_info *pi, bool qual_mods, u8 report_mode,
149 struct ice_aqc_get_phy_caps_data *pcaps,
150 struct ice_sq_cd *cd)
152 struct ice_aqc_get_phy_caps *cmd;
153 u16 pcaps_size = sizeof(*pcaps);
154 struct ice_aq_desc desc;
155 enum ice_status status;
158 cmd = &desc.params.get_phy;
160 if (!pcaps || (report_mode & ~ICE_AQC_REPORT_MODE_M) || !pi)
161 return ICE_ERR_PARAM;
164 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_phy_caps);
167 cmd->param0 |= CPU_TO_LE16(ICE_AQC_GET_PHY_RQM);
169 cmd->param0 |= CPU_TO_LE16(report_mode);
170 status = ice_aq_send_cmd(hw, &desc, pcaps, pcaps_size, cd);
172 ice_debug(hw, ICE_DBG_LINK, "get phy caps - report_mode = 0x%x\n",
174 ice_debug(hw, ICE_DBG_LINK, " phy_type_low = 0x%llx\n",
175 (unsigned long long)LE64_TO_CPU(pcaps->phy_type_low));
176 ice_debug(hw, ICE_DBG_LINK, " phy_type_high = 0x%llx\n",
177 (unsigned long long)LE64_TO_CPU(pcaps->phy_type_high));
178 ice_debug(hw, ICE_DBG_LINK, " caps = 0x%x\n", pcaps->caps);
179 ice_debug(hw, ICE_DBG_LINK, " low_power_ctrl_an = 0x%x\n",
180 pcaps->low_power_ctrl_an);
181 ice_debug(hw, ICE_DBG_LINK, " eee_cap = 0x%x\n", pcaps->eee_cap);
182 ice_debug(hw, ICE_DBG_LINK, " eeer_value = 0x%x\n",
184 ice_debug(hw, ICE_DBG_LINK, " link_fec_options = 0x%x\n",
185 pcaps->link_fec_options);
186 ice_debug(hw, ICE_DBG_LINK, " module_compliance_enforcement = 0x%x\n",
187 pcaps->module_compliance_enforcement);
188 ice_debug(hw, ICE_DBG_LINK, " extended_compliance_code = 0x%x\n",
189 pcaps->extended_compliance_code);
190 ice_debug(hw, ICE_DBG_LINK, " module_type[0] = 0x%x\n",
191 pcaps->module_type[0]);
192 ice_debug(hw, ICE_DBG_LINK, " module_type[1] = 0x%x\n",
193 pcaps->module_type[1]);
194 ice_debug(hw, ICE_DBG_LINK, " module_type[2] = 0x%x\n",
195 pcaps->module_type[2]);
197 if (status == ICE_SUCCESS && report_mode == ICE_AQC_REPORT_TOPO_CAP) {
198 pi->phy.phy_type_low = LE64_TO_CPU(pcaps->phy_type_low);
199 pi->phy.phy_type_high = LE64_TO_CPU(pcaps->phy_type_high);
200 ice_memcpy(pi->phy.link_info.module_type, &pcaps->module_type,
201 sizeof(pi->phy.link_info.module_type),
202 ICE_NONDMA_TO_NONDMA);
209 * ice_aq_get_link_topo_handle - get link topology node return status
210 * @pi: port information structure
211 * @node_type: requested node type
212 * @cd: pointer to command details structure or NULL
214 * Get link topology node return status for specified node type (0x06E0)
216 * Node type cage can be used to determine if cage is present. If AQC
217 * returns error (ENOENT), then no cage present. If no cage present, then
218 * connection type is backplane or BASE-T.
220 static enum ice_status
221 ice_aq_get_link_topo_handle(struct ice_port_info *pi, u8 node_type,
222 struct ice_sq_cd *cd)
224 struct ice_aqc_get_link_topo *cmd;
225 struct ice_aq_desc desc;
227 cmd = &desc.params.get_link_topo;
229 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_topo);
231 cmd->addr.node_type_ctx = (ICE_AQC_LINK_TOPO_NODE_CTX_PORT <<
232 ICE_AQC_LINK_TOPO_NODE_CTX_S);
235 cmd->addr.node_type_ctx |= (ICE_AQC_LINK_TOPO_NODE_TYPE_M & node_type);
237 return ice_aq_send_cmd(pi->hw, &desc, NULL, 0, cd);
241 * ice_is_media_cage_present
242 * @pi: port information structure
244 * Returns true if media cage is present, else false. If no cage, then
245 * media type is backplane or BASE-T.
247 static bool ice_is_media_cage_present(struct ice_port_info *pi)
249 /* Node type cage can be used to determine if cage is present. If AQC
250 * returns error (ENOENT), then no cage present. If no cage present then
251 * connection type is backplane or BASE-T.
253 return !ice_aq_get_link_topo_handle(pi,
254 ICE_AQC_LINK_TOPO_NODE_TYPE_CAGE,
259 * ice_get_media_type - Gets media type
260 * @pi: port information structure
262 static enum ice_media_type ice_get_media_type(struct ice_port_info *pi)
264 struct ice_link_status *hw_link_info;
267 return ICE_MEDIA_UNKNOWN;
269 hw_link_info = &pi->phy.link_info;
270 if (hw_link_info->phy_type_low && hw_link_info->phy_type_high)
271 /* If more than one media type is selected, report unknown */
272 return ICE_MEDIA_UNKNOWN;
274 if (hw_link_info->phy_type_low) {
275 /* 1G SGMII is a special case where some DA cable PHYs
276 * may show this as an option when it really shouldn't
277 * be since SGMII is meant to be between a MAC and a PHY
278 * in a backplane. Try to detect this case and handle it
280 if (hw_link_info->phy_type_low == ICE_PHY_TYPE_LOW_1G_SGMII &&
281 (hw_link_info->module_type[ICE_AQC_MOD_TYPE_IDENT] ==
282 ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_ACTIVE ||
283 hw_link_info->module_type[ICE_AQC_MOD_TYPE_IDENT] ==
284 ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_PASSIVE))
287 switch (hw_link_info->phy_type_low) {
288 case ICE_PHY_TYPE_LOW_1000BASE_SX:
289 case ICE_PHY_TYPE_LOW_1000BASE_LX:
290 case ICE_PHY_TYPE_LOW_10GBASE_SR:
291 case ICE_PHY_TYPE_LOW_10GBASE_LR:
292 case ICE_PHY_TYPE_LOW_10G_SFI_C2C:
293 case ICE_PHY_TYPE_LOW_25GBASE_SR:
294 case ICE_PHY_TYPE_LOW_25GBASE_LR:
295 case ICE_PHY_TYPE_LOW_40GBASE_SR4:
296 case ICE_PHY_TYPE_LOW_40GBASE_LR4:
297 case ICE_PHY_TYPE_LOW_50GBASE_SR2:
298 case ICE_PHY_TYPE_LOW_50GBASE_LR2:
299 case ICE_PHY_TYPE_LOW_50GBASE_SR:
300 case ICE_PHY_TYPE_LOW_50GBASE_FR:
301 case ICE_PHY_TYPE_LOW_50GBASE_LR:
302 case ICE_PHY_TYPE_LOW_100GBASE_SR4:
303 case ICE_PHY_TYPE_LOW_100GBASE_LR4:
304 case ICE_PHY_TYPE_LOW_100GBASE_SR2:
305 case ICE_PHY_TYPE_LOW_100GBASE_DR:
306 return ICE_MEDIA_FIBER;
307 case ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC:
308 case ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC:
309 case ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC:
310 case ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC:
311 case ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC:
312 case ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC:
313 case ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC:
314 case ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC:
315 return ICE_MEDIA_FIBER;
316 case ICE_PHY_TYPE_LOW_100BASE_TX:
317 case ICE_PHY_TYPE_LOW_1000BASE_T:
318 case ICE_PHY_TYPE_LOW_2500BASE_T:
319 case ICE_PHY_TYPE_LOW_5GBASE_T:
320 case ICE_PHY_TYPE_LOW_10GBASE_T:
321 case ICE_PHY_TYPE_LOW_25GBASE_T:
322 return ICE_MEDIA_BASET;
323 case ICE_PHY_TYPE_LOW_10G_SFI_DA:
324 case ICE_PHY_TYPE_LOW_25GBASE_CR:
325 case ICE_PHY_TYPE_LOW_25GBASE_CR_S:
326 case ICE_PHY_TYPE_LOW_25GBASE_CR1:
327 case ICE_PHY_TYPE_LOW_40GBASE_CR4:
328 case ICE_PHY_TYPE_LOW_50GBASE_CR2:
329 case ICE_PHY_TYPE_LOW_50GBASE_CP:
330 case ICE_PHY_TYPE_LOW_100GBASE_CR4:
331 case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4:
332 case ICE_PHY_TYPE_LOW_100GBASE_CP2:
334 case ICE_PHY_TYPE_LOW_25G_AUI_C2C:
335 case ICE_PHY_TYPE_LOW_40G_XLAUI:
336 case ICE_PHY_TYPE_LOW_50G_LAUI2:
337 case ICE_PHY_TYPE_LOW_50G_AUI2:
338 case ICE_PHY_TYPE_LOW_50G_AUI1:
339 case ICE_PHY_TYPE_LOW_100G_AUI4:
340 case ICE_PHY_TYPE_LOW_100G_CAUI4:
341 if (ice_is_media_cage_present(pi))
342 return ICE_MEDIA_AUI;
344 case ICE_PHY_TYPE_LOW_1000BASE_KX:
345 case ICE_PHY_TYPE_LOW_2500BASE_KX:
346 case ICE_PHY_TYPE_LOW_2500BASE_X:
347 case ICE_PHY_TYPE_LOW_5GBASE_KR:
348 case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1:
349 case ICE_PHY_TYPE_LOW_25GBASE_KR:
350 case ICE_PHY_TYPE_LOW_25GBASE_KR1:
351 case ICE_PHY_TYPE_LOW_25GBASE_KR_S:
352 case ICE_PHY_TYPE_LOW_40GBASE_KR4:
353 case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4:
354 case ICE_PHY_TYPE_LOW_50GBASE_KR2:
355 case ICE_PHY_TYPE_LOW_100GBASE_KR4:
356 case ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4:
357 return ICE_MEDIA_BACKPLANE;
360 switch (hw_link_info->phy_type_high) {
361 case ICE_PHY_TYPE_HIGH_100G_AUI2:
362 case ICE_PHY_TYPE_HIGH_100G_CAUI2:
363 if (ice_is_media_cage_present(pi))
364 return ICE_MEDIA_AUI;
366 case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4:
367 return ICE_MEDIA_BACKPLANE;
368 case ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC:
369 case ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC:
370 return ICE_MEDIA_FIBER;
373 return ICE_MEDIA_UNKNOWN;
377 * ice_aq_get_link_info
378 * @pi: port information structure
379 * @ena_lse: enable/disable LinkStatusEvent reporting
380 * @link: pointer to link status structure - optional
381 * @cd: pointer to command details structure or NULL
383 * Get Link Status (0x607). Returns the link status of the adapter.
386 ice_aq_get_link_info(struct ice_port_info *pi, bool ena_lse,
387 struct ice_link_status *link, struct ice_sq_cd *cd)
389 struct ice_aqc_get_link_status_data link_data = { 0 };
390 struct ice_aqc_get_link_status *resp;
391 struct ice_link_status *li_old, *li;
392 enum ice_media_type *hw_media_type;
393 struct ice_fc_info *hw_fc_info;
394 bool tx_pause, rx_pause;
395 struct ice_aq_desc desc;
396 enum ice_status status;
401 return ICE_ERR_PARAM;
403 li_old = &pi->phy.link_info_old;
404 hw_media_type = &pi->phy.media_type;
405 li = &pi->phy.link_info;
406 hw_fc_info = &pi->fc;
408 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_status);
409 cmd_flags = (ena_lse) ? ICE_AQ_LSE_ENA : ICE_AQ_LSE_DIS;
410 resp = &desc.params.get_link_status;
411 resp->cmd_flags = CPU_TO_LE16(cmd_flags);
412 resp->lport_num = pi->lport;
414 status = ice_aq_send_cmd(hw, &desc, &link_data, sizeof(link_data), cd);
416 if (status != ICE_SUCCESS)
419 /* save off old link status information */
422 /* update current link status information */
423 li->link_speed = LE16_TO_CPU(link_data.link_speed);
424 li->phy_type_low = LE64_TO_CPU(link_data.phy_type_low);
425 li->phy_type_high = LE64_TO_CPU(link_data.phy_type_high);
426 *hw_media_type = ice_get_media_type(pi);
427 li->link_info = link_data.link_info;
428 li->an_info = link_data.an_info;
429 li->ext_info = link_data.ext_info;
430 li->max_frame_size = LE16_TO_CPU(link_data.max_frame_size);
431 li->fec_info = link_data.cfg & ICE_AQ_FEC_MASK;
432 li->topo_media_conflict = link_data.topo_media_conflict;
433 li->pacing = link_data.cfg & (ICE_AQ_CFG_PACING_M |
434 ICE_AQ_CFG_PACING_TYPE_M);
437 tx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_TX);
438 rx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_RX);
439 if (tx_pause && rx_pause)
440 hw_fc_info->current_mode = ICE_FC_FULL;
442 hw_fc_info->current_mode = ICE_FC_TX_PAUSE;
444 hw_fc_info->current_mode = ICE_FC_RX_PAUSE;
446 hw_fc_info->current_mode = ICE_FC_NONE;
448 li->lse_ena = !!(resp->cmd_flags & CPU_TO_LE16(ICE_AQ_LSE_IS_ENABLED));
450 ice_debug(hw, ICE_DBG_LINK, "get link info\n");
451 ice_debug(hw, ICE_DBG_LINK, " link_speed = 0x%x\n", li->link_speed);
452 ice_debug(hw, ICE_DBG_LINK, " phy_type_low = 0x%llx\n",
453 (unsigned long long)li->phy_type_low);
454 ice_debug(hw, ICE_DBG_LINK, " phy_type_high = 0x%llx\n",
455 (unsigned long long)li->phy_type_high);
456 ice_debug(hw, ICE_DBG_LINK, " media_type = 0x%x\n", *hw_media_type);
457 ice_debug(hw, ICE_DBG_LINK, " link_info = 0x%x\n", li->link_info);
458 ice_debug(hw, ICE_DBG_LINK, " an_info = 0x%x\n", li->an_info);
459 ice_debug(hw, ICE_DBG_LINK, " ext_info = 0x%x\n", li->ext_info);
460 ice_debug(hw, ICE_DBG_LINK, " fec_info = 0x%x\n", li->fec_info);
461 ice_debug(hw, ICE_DBG_LINK, " lse_ena = 0x%x\n", li->lse_ena);
462 ice_debug(hw, ICE_DBG_LINK, " max_frame = 0x%x\n",
464 ice_debug(hw, ICE_DBG_LINK, " pacing = 0x%x\n", li->pacing);
466 /* save link status information */
470 /* flag cleared so calling functions don't call AQ again */
471 pi->phy.get_link_info = false;
477 * ice_fill_tx_timer_and_fc_thresh
478 * @hw: pointer to the HW struct
479 * @cmd: pointer to MAC cfg structure
481 * Add Tx timer and FC refresh threshold info to Set MAC Config AQ command
485 ice_fill_tx_timer_and_fc_thresh(struct ice_hw *hw,
486 struct ice_aqc_set_mac_cfg *cmd)
488 u16 fc_thres_val, tx_timer_val;
491 /* We read back the transmit timer and fc threshold value of
492 * LFC. Thus, we will use index =
493 * PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX.
495 * Also, because we are opearating on transmit timer and fc
496 * threshold of LFC, we don't turn on any bit in tx_tmr_priority
498 #define IDX_OF_LFC PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX
500 /* Retrieve the transmit timer */
501 val = rd32(hw, PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(IDX_OF_LFC));
503 PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_HSEC_CTL_TX_PAUSE_QUANTA_M;
504 cmd->tx_tmr_value = CPU_TO_LE16(tx_timer_val);
506 /* Retrieve the fc threshold */
507 val = rd32(hw, PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(IDX_OF_LFC));
508 fc_thres_val = val & PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_M;
510 cmd->fc_refresh_threshold = CPU_TO_LE16(fc_thres_val);
515 * @hw: pointer to the HW struct
516 * @max_frame_size: Maximum Frame Size to be supported
517 * @cd: pointer to command details structure or NULL
519 * Set MAC configuration (0x0603)
522 ice_aq_set_mac_cfg(struct ice_hw *hw, u16 max_frame_size, struct ice_sq_cd *cd)
524 struct ice_aqc_set_mac_cfg *cmd;
525 struct ice_aq_desc desc;
527 cmd = &desc.params.set_mac_cfg;
529 if (max_frame_size == 0)
530 return ICE_ERR_PARAM;
532 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_mac_cfg);
534 cmd->max_frame_size = CPU_TO_LE16(max_frame_size);
536 ice_fill_tx_timer_and_fc_thresh(hw, cmd);
538 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
542 * ice_init_fltr_mgmt_struct - initializes filter management list and locks
543 * @hw: pointer to the HW struct
545 enum ice_status ice_init_fltr_mgmt_struct(struct ice_hw *hw)
547 struct ice_switch_info *sw;
548 enum ice_status status;
550 hw->switch_info = (struct ice_switch_info *)
551 ice_malloc(hw, sizeof(*hw->switch_info));
553 sw = hw->switch_info;
556 return ICE_ERR_NO_MEMORY;
558 INIT_LIST_HEAD(&sw->vsi_list_map_head);
559 sw->prof_res_bm_init = 0;
561 status = ice_init_def_sw_recp(hw, &hw->switch_info->recp_list);
563 ice_free(hw, hw->switch_info);
570 * ice_cleanup_fltr_mgmt_single - clears single filter mngt struct
571 * @hw: pointer to the HW struct
572 * @sw: pointer to switch info struct for which function clears filters
575 ice_cleanup_fltr_mgmt_single(struct ice_hw *hw, struct ice_switch_info *sw)
577 struct ice_vsi_list_map_info *v_pos_map;
578 struct ice_vsi_list_map_info *v_tmp_map;
579 struct ice_sw_recipe *recps;
585 LIST_FOR_EACH_ENTRY_SAFE(v_pos_map, v_tmp_map, &sw->vsi_list_map_head,
586 ice_vsi_list_map_info, list_entry) {
587 LIST_DEL(&v_pos_map->list_entry);
588 ice_free(hw, v_pos_map);
590 recps = sw->recp_list;
591 for (i = 0; i < ICE_MAX_NUM_RECIPES; i++) {
592 struct ice_recp_grp_entry *rg_entry, *tmprg_entry;
594 recps[i].root_rid = i;
595 LIST_FOR_EACH_ENTRY_SAFE(rg_entry, tmprg_entry,
596 &recps[i].rg_list, ice_recp_grp_entry,
598 LIST_DEL(&rg_entry->l_entry);
599 ice_free(hw, rg_entry);
602 if (recps[i].adv_rule) {
603 struct ice_adv_fltr_mgmt_list_entry *tmp_entry;
604 struct ice_adv_fltr_mgmt_list_entry *lst_itr;
606 ice_destroy_lock(&recps[i].filt_rule_lock);
607 LIST_FOR_EACH_ENTRY_SAFE(lst_itr, tmp_entry,
608 &recps[i].filt_rules,
609 ice_adv_fltr_mgmt_list_entry,
611 LIST_DEL(&lst_itr->list_entry);
612 ice_free(hw, lst_itr->lkups);
613 ice_free(hw, lst_itr);
616 struct ice_fltr_mgmt_list_entry *lst_itr, *tmp_entry;
618 ice_destroy_lock(&recps[i].filt_rule_lock);
619 LIST_FOR_EACH_ENTRY_SAFE(lst_itr, tmp_entry,
620 &recps[i].filt_rules,
621 ice_fltr_mgmt_list_entry,
623 LIST_DEL(&lst_itr->list_entry);
624 ice_free(hw, lst_itr);
627 if (recps[i].root_buf)
628 ice_free(hw, recps[i].root_buf);
630 ice_rm_sw_replay_rule_info(hw, sw);
631 ice_free(hw, sw->recp_list);
636 * ice_cleanup_all_fltr_mgmt - cleanup filter management list and locks
637 * @hw: pointer to the HW struct
639 void ice_cleanup_fltr_mgmt_struct(struct ice_hw *hw)
641 ice_cleanup_fltr_mgmt_single(hw, hw->switch_info);
645 * ice_get_itr_intrl_gran
646 * @hw: pointer to the HW struct
648 * Determines the ITR/INTRL granularities based on the maximum aggregate
649 * bandwidth according to the device's configuration during power-on.
651 static void ice_get_itr_intrl_gran(struct ice_hw *hw)
653 u8 max_agg_bw = (rd32(hw, GL_PWR_MODE_CTL) &
654 GL_PWR_MODE_CTL_CAR_MAX_BW_M) >>
655 GL_PWR_MODE_CTL_CAR_MAX_BW_S;
657 switch (max_agg_bw) {
658 case ICE_MAX_AGG_BW_200G:
659 case ICE_MAX_AGG_BW_100G:
660 case ICE_MAX_AGG_BW_50G:
661 hw->itr_gran = ICE_ITR_GRAN_ABOVE_25;
662 hw->intrl_gran = ICE_INTRL_GRAN_ABOVE_25;
664 case ICE_MAX_AGG_BW_25G:
665 hw->itr_gran = ICE_ITR_GRAN_MAX_25;
666 hw->intrl_gran = ICE_INTRL_GRAN_MAX_25;
672 * ice_print_rollback_msg - print FW rollback message
673 * @hw: pointer to the hardware structure
675 void ice_print_rollback_msg(struct ice_hw *hw)
677 char nvm_str[ICE_NVM_VER_LEN] = { 0 };
678 struct ice_orom_info *orom;
679 struct ice_nvm_info *nvm;
681 orom = &hw->flash.orom;
682 nvm = &hw->flash.nvm;
684 SNPRINTF(nvm_str, sizeof(nvm_str), "%x.%02x 0x%x %d.%d.%d",
685 nvm->major, nvm->minor, nvm->eetrack, orom->major,
686 orom->build, orom->patch);
688 "Firmware rollback mode detected. Current version is NVM: %s, FW: %d.%d. Device may exhibit limited functionality. Refer to the Intel(R) Ethernet Adapters and Devices User Guide for details on firmware rollback mode\n",
689 nvm_str, hw->fw_maj_ver, hw->fw_min_ver);
693 * ice_init_hw - main hardware initialization routine
694 * @hw: pointer to the hardware structure
696 enum ice_status ice_init_hw(struct ice_hw *hw)
698 struct ice_aqc_get_phy_caps_data *pcaps;
699 enum ice_status status;
703 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
705 /* Set MAC type based on DeviceID */
706 status = ice_set_mac_type(hw);
710 hw->pf_id = (u8)(rd32(hw, PF_FUNC_RID) &
711 PF_FUNC_RID_FUNCTION_NUMBER_M) >>
712 PF_FUNC_RID_FUNCTION_NUMBER_S;
714 status = ice_reset(hw, ICE_RESET_PFR);
718 ice_get_itr_intrl_gran(hw);
720 status = ice_create_all_ctrlq(hw);
722 goto err_unroll_cqinit;
724 status = ice_init_nvm(hw);
726 goto err_unroll_cqinit;
728 if (ice_get_fw_mode(hw) == ICE_FW_MODE_ROLLBACK)
729 ice_print_rollback_msg(hw);
731 status = ice_clear_pf_cfg(hw);
733 goto err_unroll_cqinit;
735 /* Set bit to enable Flow Director filters */
736 wr32(hw, PFQF_FD_ENA, PFQF_FD_ENA_FD_ENA_M);
737 INIT_LIST_HEAD(&hw->fdir_list_head);
739 ice_clear_pxe_mode(hw);
741 status = ice_get_caps(hw);
743 goto err_unroll_cqinit;
745 hw->port_info = (struct ice_port_info *)
746 ice_malloc(hw, sizeof(*hw->port_info));
747 if (!hw->port_info) {
748 status = ICE_ERR_NO_MEMORY;
749 goto err_unroll_cqinit;
752 /* set the back pointer to HW */
753 hw->port_info->hw = hw;
755 /* Initialize port_info struct with switch configuration data */
756 status = ice_get_initial_sw_cfg(hw);
758 goto err_unroll_alloc;
761 /* Query the allocated resources for Tx scheduler */
762 status = ice_sched_query_res_alloc(hw);
764 ice_debug(hw, ICE_DBG_SCHED, "Failed to get scheduler allocated resources\n");
765 goto err_unroll_alloc;
767 ice_sched_get_psm_clk_freq(hw);
769 /* Initialize port_info struct with scheduler data */
770 status = ice_sched_init_port(hw->port_info);
772 goto err_unroll_sched;
773 pcaps = (struct ice_aqc_get_phy_caps_data *)
774 ice_malloc(hw, sizeof(*pcaps));
776 status = ICE_ERR_NO_MEMORY;
777 goto err_unroll_sched;
780 /* Initialize port_info struct with PHY capabilities */
781 status = ice_aq_get_phy_caps(hw->port_info, false,
782 ICE_AQC_REPORT_TOPO_CAP, pcaps, NULL);
785 ice_debug(hw, ICE_DBG_PHY, "Get PHY capabilities failed, continuing anyway\n");
787 /* Initialize port_info struct with link information */
788 status = ice_aq_get_link_info(hw->port_info, false, NULL, NULL);
790 goto err_unroll_sched;
791 /* need a valid SW entry point to build a Tx tree */
792 if (!hw->sw_entry_point_layer) {
793 ice_debug(hw, ICE_DBG_SCHED, "invalid sw entry point\n");
794 status = ICE_ERR_CFG;
795 goto err_unroll_sched;
797 INIT_LIST_HEAD(&hw->agg_list);
798 /* Initialize max burst size */
799 if (!hw->max_burst_size)
800 ice_cfg_rl_burst_size(hw, ICE_SCHED_DFLT_BURST_SIZE);
801 status = ice_init_fltr_mgmt_struct(hw);
803 goto err_unroll_sched;
805 /* Get MAC information */
806 /* A single port can report up to two (LAN and WoL) addresses */
807 mac_buf = ice_calloc(hw, 2,
808 sizeof(struct ice_aqc_manage_mac_read_resp));
809 mac_buf_len = 2 * sizeof(struct ice_aqc_manage_mac_read_resp);
812 status = ICE_ERR_NO_MEMORY;
813 goto err_unroll_fltr_mgmt_struct;
816 status = ice_aq_manage_mac_read(hw, mac_buf, mac_buf_len, NULL);
817 ice_free(hw, mac_buf);
820 goto err_unroll_fltr_mgmt_struct;
821 /* enable jumbo frame support at MAC level */
822 status = ice_aq_set_mac_cfg(hw, ICE_AQ_SET_MAC_FRAME_SIZE_MAX, NULL);
824 goto err_unroll_fltr_mgmt_struct;
825 /* Obtain counter base index which would be used by flow director */
826 status = ice_alloc_fd_res_cntr(hw, &hw->fd_ctr_base);
828 goto err_unroll_fltr_mgmt_struct;
829 status = ice_init_hw_tbls(hw);
831 goto err_unroll_fltr_mgmt_struct;
832 ice_init_lock(&hw->tnl_lock);
835 err_unroll_fltr_mgmt_struct:
836 ice_cleanup_fltr_mgmt_struct(hw);
838 ice_sched_cleanup_all(hw);
840 ice_free(hw, hw->port_info);
841 hw->port_info = NULL;
843 ice_destroy_all_ctrlq(hw);
848 * ice_deinit_hw - unroll initialization operations done by ice_init_hw
849 * @hw: pointer to the hardware structure
851 * This should be called only during nominal operation, not as a result of
852 * ice_init_hw() failing since ice_init_hw() will take care of unrolling
853 * applicable initializations if it fails for any reason.
855 void ice_deinit_hw(struct ice_hw *hw)
857 ice_free_fd_res_cntr(hw, hw->fd_ctr_base);
858 ice_cleanup_fltr_mgmt_struct(hw);
860 ice_sched_cleanup_all(hw);
861 ice_sched_clear_agg(hw);
863 ice_free_hw_tbls(hw);
864 ice_destroy_lock(&hw->tnl_lock);
867 ice_free(hw, hw->port_info);
868 hw->port_info = NULL;
871 ice_destroy_all_ctrlq(hw);
873 /* Clear VSI contexts if not already cleared */
874 ice_clear_all_vsi_ctx(hw);
878 * ice_check_reset - Check to see if a global reset is complete
879 * @hw: pointer to the hardware structure
881 enum ice_status ice_check_reset(struct ice_hw *hw)
883 u32 cnt, reg = 0, grst_timeout, uld_mask;
885 /* Poll for Device Active state in case a recent CORER, GLOBR,
886 * or EMPR has occurred. The grst delay value is in 100ms units.
887 * Add 1sec for outstanding AQ commands that can take a long time.
889 grst_timeout = ((rd32(hw, GLGEN_RSTCTL) & GLGEN_RSTCTL_GRSTDEL_M) >>
890 GLGEN_RSTCTL_GRSTDEL_S) + 10;
892 for (cnt = 0; cnt < grst_timeout; cnt++) {
893 ice_msec_delay(100, true);
894 reg = rd32(hw, GLGEN_RSTAT);
895 if (!(reg & GLGEN_RSTAT_DEVSTATE_M))
899 if (cnt == grst_timeout) {
900 ice_debug(hw, ICE_DBG_INIT, "Global reset polling failed to complete.\n");
901 return ICE_ERR_RESET_FAILED;
904 #define ICE_RESET_DONE_MASK (GLNVM_ULD_PCIER_DONE_M |\
905 GLNVM_ULD_PCIER_DONE_1_M |\
906 GLNVM_ULD_CORER_DONE_M |\
907 GLNVM_ULD_GLOBR_DONE_M |\
908 GLNVM_ULD_POR_DONE_M |\
909 GLNVM_ULD_POR_DONE_1_M |\
910 GLNVM_ULD_PCIER_DONE_2_M)
912 uld_mask = ICE_RESET_DONE_MASK;
914 /* Device is Active; check Global Reset processes are done */
915 for (cnt = 0; cnt < ICE_PF_RESET_WAIT_COUNT; cnt++) {
916 reg = rd32(hw, GLNVM_ULD) & uld_mask;
917 if (reg == uld_mask) {
918 ice_debug(hw, ICE_DBG_INIT, "Global reset processes done. %d\n", cnt);
921 ice_msec_delay(10, true);
924 if (cnt == ICE_PF_RESET_WAIT_COUNT) {
925 ice_debug(hw, ICE_DBG_INIT, "Wait for Reset Done timed out. GLNVM_ULD = 0x%x\n",
927 return ICE_ERR_RESET_FAILED;
934 * ice_pf_reset - Reset the PF
935 * @hw: pointer to the hardware structure
937 * If a global reset has been triggered, this function checks
938 * for its completion and then issues the PF reset
940 static enum ice_status ice_pf_reset(struct ice_hw *hw)
944 /* If at function entry a global reset was already in progress, i.e.
945 * state is not 'device active' or any of the reset done bits are not
946 * set in GLNVM_ULD, there is no need for a PF Reset; poll until the
947 * global reset is done.
949 if ((rd32(hw, GLGEN_RSTAT) & GLGEN_RSTAT_DEVSTATE_M) ||
950 (rd32(hw, GLNVM_ULD) & ICE_RESET_DONE_MASK) ^ ICE_RESET_DONE_MASK) {
951 /* poll on global reset currently in progress until done */
952 if (ice_check_reset(hw))
953 return ICE_ERR_RESET_FAILED;
959 reg = rd32(hw, PFGEN_CTRL);
961 wr32(hw, PFGEN_CTRL, (reg | PFGEN_CTRL_PFSWR_M));
963 /* Wait for the PFR to complete. The wait time is the global config lock
964 * timeout plus the PFR timeout which will account for a possible reset
965 * that is occurring during a download package operation.
967 for (cnt = 0; cnt < ICE_GLOBAL_CFG_LOCK_TIMEOUT +
968 ICE_PF_RESET_WAIT_COUNT; cnt++) {
969 reg = rd32(hw, PFGEN_CTRL);
970 if (!(reg & PFGEN_CTRL_PFSWR_M))
973 ice_msec_delay(1, true);
976 if (cnt == ICE_PF_RESET_WAIT_COUNT) {
977 ice_debug(hw, ICE_DBG_INIT, "PF reset polling failed to complete.\n");
978 return ICE_ERR_RESET_FAILED;
985 * ice_reset - Perform different types of reset
986 * @hw: pointer to the hardware structure
987 * @req: reset request
989 * This function triggers a reset as specified by the req parameter.
992 * If anything other than a PF reset is triggered, PXE mode is restored.
993 * This has to be cleared using ice_clear_pxe_mode again, once the AQ
994 * interface has been restored in the rebuild flow.
996 enum ice_status ice_reset(struct ice_hw *hw, enum ice_reset_req req)
1002 return ice_pf_reset(hw);
1003 case ICE_RESET_CORER:
1004 ice_debug(hw, ICE_DBG_INIT, "CoreR requested\n");
1005 val = GLGEN_RTRIG_CORER_M;
1007 case ICE_RESET_GLOBR:
1008 ice_debug(hw, ICE_DBG_INIT, "GlobalR requested\n");
1009 val = GLGEN_RTRIG_GLOBR_M;
1012 return ICE_ERR_PARAM;
1015 val |= rd32(hw, GLGEN_RTRIG);
1016 wr32(hw, GLGEN_RTRIG, val);
1019 /* wait for the FW to be ready */
1020 return ice_check_reset(hw);
1024 * ice_copy_rxq_ctx_to_hw
1025 * @hw: pointer to the hardware structure
1026 * @ice_rxq_ctx: pointer to the rxq context
1027 * @rxq_index: the index of the Rx queue
1029 * Copies rxq context from dense structure to HW register space
1031 static enum ice_status
1032 ice_copy_rxq_ctx_to_hw(struct ice_hw *hw, u8 *ice_rxq_ctx, u32 rxq_index)
1037 return ICE_ERR_BAD_PTR;
1039 if (rxq_index > QRX_CTRL_MAX_INDEX)
1040 return ICE_ERR_PARAM;
1042 /* Copy each dword separately to HW */
1043 for (i = 0; i < ICE_RXQ_CTX_SIZE_DWORDS; i++) {
1044 wr32(hw, QRX_CONTEXT(i, rxq_index),
1045 *((u32 *)(ice_rxq_ctx + (i * sizeof(u32)))));
1047 ice_debug(hw, ICE_DBG_QCTX, "qrxdata[%d]: %08X\n", i,
1048 *((u32 *)(ice_rxq_ctx + (i * sizeof(u32)))));
1054 /* LAN Rx Queue Context */
1055 static const struct ice_ctx_ele ice_rlan_ctx_info[] = {
1056 /* Field Width LSB */
1057 ICE_CTX_STORE(ice_rlan_ctx, head, 13, 0),
1058 ICE_CTX_STORE(ice_rlan_ctx, cpuid, 8, 13),
1059 ICE_CTX_STORE(ice_rlan_ctx, base, 57, 32),
1060 ICE_CTX_STORE(ice_rlan_ctx, qlen, 13, 89),
1061 ICE_CTX_STORE(ice_rlan_ctx, dbuf, 7, 102),
1062 ICE_CTX_STORE(ice_rlan_ctx, hbuf, 5, 109),
1063 ICE_CTX_STORE(ice_rlan_ctx, dtype, 2, 114),
1064 ICE_CTX_STORE(ice_rlan_ctx, dsize, 1, 116),
1065 ICE_CTX_STORE(ice_rlan_ctx, crcstrip, 1, 117),
1066 ICE_CTX_STORE(ice_rlan_ctx, l2tsel, 1, 119),
1067 ICE_CTX_STORE(ice_rlan_ctx, hsplit_0, 4, 120),
1068 ICE_CTX_STORE(ice_rlan_ctx, hsplit_1, 2, 124),
1069 ICE_CTX_STORE(ice_rlan_ctx, showiv, 1, 127),
1070 ICE_CTX_STORE(ice_rlan_ctx, rxmax, 14, 174),
1071 ICE_CTX_STORE(ice_rlan_ctx, tphrdesc_ena, 1, 193),
1072 ICE_CTX_STORE(ice_rlan_ctx, tphwdesc_ena, 1, 194),
1073 ICE_CTX_STORE(ice_rlan_ctx, tphdata_ena, 1, 195),
1074 ICE_CTX_STORE(ice_rlan_ctx, tphhead_ena, 1, 196),
1075 ICE_CTX_STORE(ice_rlan_ctx, lrxqthresh, 3, 198),
1076 ICE_CTX_STORE(ice_rlan_ctx, prefena, 1, 201),
1082 * @hw: pointer to the hardware structure
1083 * @rlan_ctx: pointer to the rxq context
1084 * @rxq_index: the index of the Rx queue
1086 * Converts rxq context from sparse to dense structure and then writes
1087 * it to HW register space and enables the hardware to prefetch descriptors
1088 * instead of only fetching them on demand
1091 ice_write_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx,
1094 u8 ctx_buf[ICE_RXQ_CTX_SZ] = { 0 };
1097 return ICE_ERR_BAD_PTR;
1099 rlan_ctx->prefena = 1;
1101 ice_set_ctx(hw, (u8 *)rlan_ctx, ctx_buf, ice_rlan_ctx_info);
1102 return ice_copy_rxq_ctx_to_hw(hw, ctx_buf, rxq_index);
1107 * @hw: pointer to the hardware structure
1108 * @rxq_index: the index of the Rx queue to clear
1110 * Clears rxq context in HW register space
1112 enum ice_status ice_clear_rxq_ctx(struct ice_hw *hw, u32 rxq_index)
1116 if (rxq_index > QRX_CTRL_MAX_INDEX)
1117 return ICE_ERR_PARAM;
1119 /* Clear each dword register separately */
1120 for (i = 0; i < ICE_RXQ_CTX_SIZE_DWORDS; i++)
1121 wr32(hw, QRX_CONTEXT(i, rxq_index), 0);
1126 /* LAN Tx Queue Context */
1127 const struct ice_ctx_ele ice_tlan_ctx_info[] = {
1128 /* Field Width LSB */
1129 ICE_CTX_STORE(ice_tlan_ctx, base, 57, 0),
1130 ICE_CTX_STORE(ice_tlan_ctx, port_num, 3, 57),
1131 ICE_CTX_STORE(ice_tlan_ctx, cgd_num, 5, 60),
1132 ICE_CTX_STORE(ice_tlan_ctx, pf_num, 3, 65),
1133 ICE_CTX_STORE(ice_tlan_ctx, vmvf_num, 10, 68),
1134 ICE_CTX_STORE(ice_tlan_ctx, vmvf_type, 2, 78),
1135 ICE_CTX_STORE(ice_tlan_ctx, src_vsi, 10, 80),
1136 ICE_CTX_STORE(ice_tlan_ctx, tsyn_ena, 1, 90),
1137 ICE_CTX_STORE(ice_tlan_ctx, internal_usage_flag, 1, 91),
1138 ICE_CTX_STORE(ice_tlan_ctx, alt_vlan, 1, 92),
1139 ICE_CTX_STORE(ice_tlan_ctx, cpuid, 8, 93),
1140 ICE_CTX_STORE(ice_tlan_ctx, wb_mode, 1, 101),
1141 ICE_CTX_STORE(ice_tlan_ctx, tphrd_desc, 1, 102),
1142 ICE_CTX_STORE(ice_tlan_ctx, tphrd, 1, 103),
1143 ICE_CTX_STORE(ice_tlan_ctx, tphwr_desc, 1, 104),
1144 ICE_CTX_STORE(ice_tlan_ctx, cmpq_id, 9, 105),
1145 ICE_CTX_STORE(ice_tlan_ctx, qnum_in_func, 14, 114),
1146 ICE_CTX_STORE(ice_tlan_ctx, itr_notification_mode, 1, 128),
1147 ICE_CTX_STORE(ice_tlan_ctx, adjust_prof_id, 6, 129),
1148 ICE_CTX_STORE(ice_tlan_ctx, qlen, 13, 135),
1149 ICE_CTX_STORE(ice_tlan_ctx, quanta_prof_idx, 4, 148),
1150 ICE_CTX_STORE(ice_tlan_ctx, tso_ena, 1, 152),
1151 ICE_CTX_STORE(ice_tlan_ctx, tso_qnum, 11, 153),
1152 ICE_CTX_STORE(ice_tlan_ctx, legacy_int, 1, 164),
1153 ICE_CTX_STORE(ice_tlan_ctx, drop_ena, 1, 165),
1154 ICE_CTX_STORE(ice_tlan_ctx, cache_prof_idx, 2, 166),
1155 ICE_CTX_STORE(ice_tlan_ctx, pkt_shaper_prof_idx, 3, 168),
1156 ICE_CTX_STORE(ice_tlan_ctx, int_q_state, 122, 171),
1161 * ice_copy_tx_cmpltnq_ctx_to_hw
1162 * @hw: pointer to the hardware structure
1163 * @ice_tx_cmpltnq_ctx: pointer to the Tx completion queue context
1164 * @tx_cmpltnq_index: the index of the completion queue
1166 * Copies Tx completion queue context from dense structure to HW register space
1168 static enum ice_status
1169 ice_copy_tx_cmpltnq_ctx_to_hw(struct ice_hw *hw, u8 *ice_tx_cmpltnq_ctx,
1170 u32 tx_cmpltnq_index)
1174 if (!ice_tx_cmpltnq_ctx)
1175 return ICE_ERR_BAD_PTR;
1177 if (tx_cmpltnq_index > GLTCLAN_CQ_CNTX0_MAX_INDEX)
1178 return ICE_ERR_PARAM;
1180 /* Copy each dword separately to HW */
1181 for (i = 0; i < ICE_TX_CMPLTNQ_CTX_SIZE_DWORDS; i++) {
1182 wr32(hw, GLTCLAN_CQ_CNTX(i, tx_cmpltnq_index),
1183 *((u32 *)(ice_tx_cmpltnq_ctx + (i * sizeof(u32)))));
1185 ice_debug(hw, ICE_DBG_QCTX, "cmpltnqdata[%d]: %08X\n", i,
1186 *((u32 *)(ice_tx_cmpltnq_ctx + (i * sizeof(u32)))));
1192 /* LAN Tx Completion Queue Context */
1193 static const struct ice_ctx_ele ice_tx_cmpltnq_ctx_info[] = {
1194 /* Field Width LSB */
1195 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, base, 57, 0),
1196 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, q_len, 18, 64),
1197 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, generation, 1, 96),
1198 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, wrt_ptr, 22, 97),
1199 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, pf_num, 3, 128),
1200 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, vmvf_num, 10, 131),
1201 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, vmvf_type, 2, 141),
1202 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, tph_desc_wr, 1, 160),
1203 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, cpuid, 8, 161),
1204 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, cmpltn_cache, 512, 192),
1209 * ice_write_tx_cmpltnq_ctx
1210 * @hw: pointer to the hardware structure
1211 * @tx_cmpltnq_ctx: pointer to the completion queue context
1212 * @tx_cmpltnq_index: the index of the completion queue
1214 * Converts completion queue context from sparse to dense structure and then
1215 * writes it to HW register space
1218 ice_write_tx_cmpltnq_ctx(struct ice_hw *hw,
1219 struct ice_tx_cmpltnq_ctx *tx_cmpltnq_ctx,
1220 u32 tx_cmpltnq_index)
1222 u8 ctx_buf[ICE_TX_CMPLTNQ_CTX_SIZE_DWORDS * sizeof(u32)] = { 0 };
1224 ice_set_ctx(hw, (u8 *)tx_cmpltnq_ctx, ctx_buf, ice_tx_cmpltnq_ctx_info);
1225 return ice_copy_tx_cmpltnq_ctx_to_hw(hw, ctx_buf, tx_cmpltnq_index);
1229 * ice_clear_tx_cmpltnq_ctx
1230 * @hw: pointer to the hardware structure
1231 * @tx_cmpltnq_index: the index of the completion queue to clear
1233 * Clears Tx completion queue context in HW register space
1236 ice_clear_tx_cmpltnq_ctx(struct ice_hw *hw, u32 tx_cmpltnq_index)
1240 if (tx_cmpltnq_index > GLTCLAN_CQ_CNTX0_MAX_INDEX)
1241 return ICE_ERR_PARAM;
1243 /* Clear each dword register separately */
1244 for (i = 0; i < ICE_TX_CMPLTNQ_CTX_SIZE_DWORDS; i++)
1245 wr32(hw, GLTCLAN_CQ_CNTX(i, tx_cmpltnq_index), 0);
1251 * ice_copy_tx_drbell_q_ctx_to_hw
1252 * @hw: pointer to the hardware structure
1253 * @ice_tx_drbell_q_ctx: pointer to the doorbell queue context
1254 * @tx_drbell_q_index: the index of the doorbell queue
1256 * Copies doorbell queue context from dense structure to HW register space
1258 static enum ice_status
1259 ice_copy_tx_drbell_q_ctx_to_hw(struct ice_hw *hw, u8 *ice_tx_drbell_q_ctx,
1260 u32 tx_drbell_q_index)
1264 if (!ice_tx_drbell_q_ctx)
1265 return ICE_ERR_BAD_PTR;
1267 if (tx_drbell_q_index > QTX_COMM_DBLQ_DBELL_MAX_INDEX)
1268 return ICE_ERR_PARAM;
1270 /* Copy each dword separately to HW */
1271 for (i = 0; i < ICE_TX_DRBELL_Q_CTX_SIZE_DWORDS; i++) {
1272 wr32(hw, QTX_COMM_DBLQ_CNTX(i, tx_drbell_q_index),
1273 *((u32 *)(ice_tx_drbell_q_ctx + (i * sizeof(u32)))));
1275 ice_debug(hw, ICE_DBG_QCTX, "tx_drbell_qdata[%d]: %08X\n", i,
1276 *((u32 *)(ice_tx_drbell_q_ctx + (i * sizeof(u32)))));
1282 /* LAN Tx Doorbell Queue Context info */
1283 static const struct ice_ctx_ele ice_tx_drbell_q_ctx_info[] = {
1284 /* Field Width LSB */
1285 ICE_CTX_STORE(ice_tx_drbell_q_ctx, base, 57, 0),
1286 ICE_CTX_STORE(ice_tx_drbell_q_ctx, ring_len, 13, 64),
1287 ICE_CTX_STORE(ice_tx_drbell_q_ctx, pf_num, 3, 80),
1288 ICE_CTX_STORE(ice_tx_drbell_q_ctx, vf_num, 8, 84),
1289 ICE_CTX_STORE(ice_tx_drbell_q_ctx, vmvf_type, 2, 94),
1290 ICE_CTX_STORE(ice_tx_drbell_q_ctx, cpuid, 8, 96),
1291 ICE_CTX_STORE(ice_tx_drbell_q_ctx, tph_desc_rd, 1, 104),
1292 ICE_CTX_STORE(ice_tx_drbell_q_ctx, tph_desc_wr, 1, 108),
1293 ICE_CTX_STORE(ice_tx_drbell_q_ctx, db_q_en, 1, 112),
1294 ICE_CTX_STORE(ice_tx_drbell_q_ctx, rd_head, 13, 128),
1295 ICE_CTX_STORE(ice_tx_drbell_q_ctx, rd_tail, 13, 144),
1300 * ice_write_tx_drbell_q_ctx
1301 * @hw: pointer to the hardware structure
1302 * @tx_drbell_q_ctx: pointer to the doorbell queue context
1303 * @tx_drbell_q_index: the index of the doorbell queue
1305 * Converts doorbell queue context from sparse to dense structure and then
1306 * writes it to HW register space
1309 ice_write_tx_drbell_q_ctx(struct ice_hw *hw,
1310 struct ice_tx_drbell_q_ctx *tx_drbell_q_ctx,
1311 u32 tx_drbell_q_index)
1313 u8 ctx_buf[ICE_TX_DRBELL_Q_CTX_SIZE_DWORDS * sizeof(u32)] = { 0 };
1315 ice_set_ctx(hw, (u8 *)tx_drbell_q_ctx, ctx_buf,
1316 ice_tx_drbell_q_ctx_info);
1317 return ice_copy_tx_drbell_q_ctx_to_hw(hw, ctx_buf, tx_drbell_q_index);
1321 * ice_clear_tx_drbell_q_ctx
1322 * @hw: pointer to the hardware structure
1323 * @tx_drbell_q_index: the index of the doorbell queue to clear
1325 * Clears doorbell queue context in HW register space
1328 ice_clear_tx_drbell_q_ctx(struct ice_hw *hw, u32 tx_drbell_q_index)
1332 if (tx_drbell_q_index > QTX_COMM_DBLQ_DBELL_MAX_INDEX)
1333 return ICE_ERR_PARAM;
1335 /* Clear each dword register separately */
1336 for (i = 0; i < ICE_TX_DRBELL_Q_CTX_SIZE_DWORDS; i++)
1337 wr32(hw, QTX_COMM_DBLQ_CNTX(i, tx_drbell_q_index), 0);
1342 /* FW Admin Queue command wrappers */
1345 * ice_aq_send_cmd - send FW Admin Queue command to FW Admin Queue
1346 * @hw: pointer to the HW struct
1347 * @desc: descriptor describing the command
1348 * @buf: buffer to use for indirect commands (NULL for direct commands)
1349 * @buf_size: size of buffer for indirect commands (0 for direct commands)
1350 * @cd: pointer to command details structure
1352 * Helper function to send FW Admin Queue commands to the FW Admin Queue.
1355 ice_aq_send_cmd(struct ice_hw *hw, struct ice_aq_desc *desc, void *buf,
1356 u16 buf_size, struct ice_sq_cd *cd)
1358 if (hw->aq_send_cmd_fn) {
1359 enum ice_status status = ICE_ERR_NOT_READY;
1360 u16 retval = ICE_AQ_RC_OK;
1362 ice_acquire_lock(&hw->adminq.sq_lock);
1363 if (!hw->aq_send_cmd_fn(hw->aq_send_cmd_param, desc,
1365 retval = LE16_TO_CPU(desc->retval);
1366 /* strip off FW internal code */
1369 if (retval == ICE_AQ_RC_OK)
1370 status = ICE_SUCCESS;
1372 status = ICE_ERR_AQ_ERROR;
1375 hw->adminq.sq_last_status = (enum ice_aq_err)retval;
1376 ice_release_lock(&hw->adminq.sq_lock);
1380 return ice_sq_send_cmd(hw, &hw->adminq, desc, buf, buf_size, cd);
1385 * @hw: pointer to the HW struct
1386 * @cd: pointer to command details structure or NULL
1388 * Get the firmware version (0x0001) from the admin queue commands
1390 enum ice_status ice_aq_get_fw_ver(struct ice_hw *hw, struct ice_sq_cd *cd)
1392 struct ice_aqc_get_ver *resp;
1393 struct ice_aq_desc desc;
1394 enum ice_status status;
1396 resp = &desc.params.get_ver;
1398 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_ver);
1400 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
1403 hw->fw_branch = resp->fw_branch;
1404 hw->fw_maj_ver = resp->fw_major;
1405 hw->fw_min_ver = resp->fw_minor;
1406 hw->fw_patch = resp->fw_patch;
1407 hw->fw_build = LE32_TO_CPU(resp->fw_build);
1408 hw->api_branch = resp->api_branch;
1409 hw->api_maj_ver = resp->api_major;
1410 hw->api_min_ver = resp->api_minor;
1411 hw->api_patch = resp->api_patch;
1418 * ice_aq_send_driver_ver
1419 * @hw: pointer to the HW struct
1420 * @dv: driver's major, minor version
1421 * @cd: pointer to command details structure or NULL
1423 * Send the driver version (0x0002) to the firmware
1426 ice_aq_send_driver_ver(struct ice_hw *hw, struct ice_driver_ver *dv,
1427 struct ice_sq_cd *cd)
1429 struct ice_aqc_driver_ver *cmd;
1430 struct ice_aq_desc desc;
1433 cmd = &desc.params.driver_ver;
1436 return ICE_ERR_PARAM;
1438 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_driver_ver);
1440 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
1441 cmd->major_ver = dv->major_ver;
1442 cmd->minor_ver = dv->minor_ver;
1443 cmd->build_ver = dv->build_ver;
1444 cmd->subbuild_ver = dv->subbuild_ver;
1447 while (len < sizeof(dv->driver_string) &&
1448 IS_ASCII(dv->driver_string[len]) && dv->driver_string[len])
1451 return ice_aq_send_cmd(hw, &desc, dv->driver_string, len, cd);
1456 * @hw: pointer to the HW struct
1457 * @unloading: is the driver unloading itself
1459 * Tell the Firmware that we're shutting down the AdminQ and whether
1460 * or not the driver is unloading as well (0x0003).
1462 enum ice_status ice_aq_q_shutdown(struct ice_hw *hw, bool unloading)
1464 struct ice_aqc_q_shutdown *cmd;
1465 struct ice_aq_desc desc;
1467 cmd = &desc.params.q_shutdown;
1469 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_q_shutdown);
1472 cmd->driver_unloading = ICE_AQC_DRIVER_UNLOADING;
1474 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
1479 * @hw: pointer to the HW struct
1481 * @access: access type
1482 * @sdp_number: resource number
1483 * @timeout: the maximum time in ms that the driver may hold the resource
1484 * @cd: pointer to command details structure or NULL
1486 * Requests common resource using the admin queue commands (0x0008).
1487 * When attempting to acquire the Global Config Lock, the driver can
1488 * learn of three states:
1489 * 1) ICE_SUCCESS - acquired lock, and can perform download package
1490 * 2) ICE_ERR_AQ_ERROR - did not get lock, driver should fail to load
1491 * 3) ICE_ERR_AQ_NO_WORK - did not get lock, but another driver has
1492 * successfully downloaded the package; the driver does
1493 * not have to download the package and can continue
1496 * Note that if the caller is in an acquire lock, perform action, release lock
1497 * phase of operation, it is possible that the FW may detect a timeout and issue
1498 * a CORER. In this case, the driver will receive a CORER interrupt and will
1499 * have to determine its cause. The calling thread that is handling this flow
1500 * will likely get an error propagated back to it indicating the Download
1501 * Package, Update Package or the Release Resource AQ commands timed out.
1503 static enum ice_status
1504 ice_aq_req_res(struct ice_hw *hw, enum ice_aq_res_ids res,
1505 enum ice_aq_res_access_type access, u8 sdp_number, u32 *timeout,
1506 struct ice_sq_cd *cd)
1508 struct ice_aqc_req_res *cmd_resp;
1509 struct ice_aq_desc desc;
1510 enum ice_status status;
1512 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
1514 cmd_resp = &desc.params.res_owner;
1516 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_req_res);
1518 cmd_resp->res_id = CPU_TO_LE16(res);
1519 cmd_resp->access_type = CPU_TO_LE16(access);
1520 cmd_resp->res_number = CPU_TO_LE32(sdp_number);
1521 cmd_resp->timeout = CPU_TO_LE32(*timeout);
1524 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
1526 /* The completion specifies the maximum time in ms that the driver
1527 * may hold the resource in the Timeout field.
1530 /* Global config lock response utilizes an additional status field.
1532 * If the Global config lock resource is held by some other driver, the
1533 * command completes with ICE_AQ_RES_GLBL_IN_PROG in the status field
1534 * and the timeout field indicates the maximum time the current owner
1535 * of the resource has to free it.
1537 if (res == ICE_GLOBAL_CFG_LOCK_RES_ID) {
1538 if (LE16_TO_CPU(cmd_resp->status) == ICE_AQ_RES_GLBL_SUCCESS) {
1539 *timeout = LE32_TO_CPU(cmd_resp->timeout);
1541 } else if (LE16_TO_CPU(cmd_resp->status) ==
1542 ICE_AQ_RES_GLBL_IN_PROG) {
1543 *timeout = LE32_TO_CPU(cmd_resp->timeout);
1544 return ICE_ERR_AQ_ERROR;
1545 } else if (LE16_TO_CPU(cmd_resp->status) ==
1546 ICE_AQ_RES_GLBL_DONE) {
1547 return ICE_ERR_AQ_NO_WORK;
1550 /* invalid FW response, force a timeout immediately */
1552 return ICE_ERR_AQ_ERROR;
1555 /* If the resource is held by some other driver, the command completes
1556 * with a busy return value and the timeout field indicates the maximum
1557 * time the current owner of the resource has to free it.
1559 if (!status || hw->adminq.sq_last_status == ICE_AQ_RC_EBUSY)
1560 *timeout = LE32_TO_CPU(cmd_resp->timeout);
1566 * ice_aq_release_res
1567 * @hw: pointer to the HW struct
1569 * @sdp_number: resource number
1570 * @cd: pointer to command details structure or NULL
1572 * release common resource using the admin queue commands (0x0009)
1574 static enum ice_status
1575 ice_aq_release_res(struct ice_hw *hw, enum ice_aq_res_ids res, u8 sdp_number,
1576 struct ice_sq_cd *cd)
1578 struct ice_aqc_req_res *cmd;
1579 struct ice_aq_desc desc;
1581 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
1583 cmd = &desc.params.res_owner;
1585 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_release_res);
1587 cmd->res_id = CPU_TO_LE16(res);
1588 cmd->res_number = CPU_TO_LE32(sdp_number);
1590 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
1595 * @hw: pointer to the HW structure
1597 * @access: access type (read or write)
1598 * @timeout: timeout in milliseconds
1600 * This function will attempt to acquire the ownership of a resource.
1603 ice_acquire_res(struct ice_hw *hw, enum ice_aq_res_ids res,
1604 enum ice_aq_res_access_type access, u32 timeout)
1606 #define ICE_RES_POLLING_DELAY_MS 10
1607 u32 delay = ICE_RES_POLLING_DELAY_MS;
1608 u32 time_left = timeout;
1609 enum ice_status status;
1611 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
1613 status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL);
1615 /* A return code of ICE_ERR_AQ_NO_WORK means that another driver has
1616 * previously acquired the resource and performed any necessary updates;
1617 * in this case the caller does not obtain the resource and has no
1618 * further work to do.
1620 if (status == ICE_ERR_AQ_NO_WORK)
1621 goto ice_acquire_res_exit;
1624 ice_debug(hw, ICE_DBG_RES, "resource %d acquire type %d failed.\n", res, access);
1626 /* If necessary, poll until the current lock owner timeouts */
1627 timeout = time_left;
1628 while (status && timeout && time_left) {
1629 ice_msec_delay(delay, true);
1630 timeout = (timeout > delay) ? timeout - delay : 0;
1631 status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL);
1633 if (status == ICE_ERR_AQ_NO_WORK)
1634 /* lock free, but no work to do */
1641 if (status && status != ICE_ERR_AQ_NO_WORK)
1642 ice_debug(hw, ICE_DBG_RES, "resource acquire timed out.\n");
1644 ice_acquire_res_exit:
1645 if (status == ICE_ERR_AQ_NO_WORK) {
1646 if (access == ICE_RES_WRITE)
1647 ice_debug(hw, ICE_DBG_RES, "resource indicates no work to do.\n");
1649 ice_debug(hw, ICE_DBG_RES, "Warning: ICE_ERR_AQ_NO_WORK not expected\n");
1656 * @hw: pointer to the HW structure
1659 * This function will release a resource using the proper Admin Command.
1661 void ice_release_res(struct ice_hw *hw, enum ice_aq_res_ids res)
1663 enum ice_status status;
1664 u32 total_delay = 0;
1666 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
1668 status = ice_aq_release_res(hw, res, 0, NULL);
1670 /* there are some rare cases when trying to release the resource
1671 * results in an admin queue timeout, so handle them correctly
1673 while ((status == ICE_ERR_AQ_TIMEOUT) &&
1674 (total_delay < hw->adminq.sq_cmd_timeout)) {
1675 ice_msec_delay(1, true);
1676 status = ice_aq_release_res(hw, res, 0, NULL);
1682 * ice_aq_alloc_free_res - command to allocate/free resources
1683 * @hw: pointer to the HW struct
1684 * @num_entries: number of resource entries in buffer
1685 * @buf: Indirect buffer to hold data parameters and response
1686 * @buf_size: size of buffer for indirect commands
1687 * @opc: pass in the command opcode
1688 * @cd: pointer to command details structure or NULL
1690 * Helper function to allocate/free resources using the admin queue commands
1693 ice_aq_alloc_free_res(struct ice_hw *hw, u16 num_entries,
1694 struct ice_aqc_alloc_free_res_elem *buf, u16 buf_size,
1695 enum ice_adminq_opc opc, struct ice_sq_cd *cd)
1697 struct ice_aqc_alloc_free_res_cmd *cmd;
1698 struct ice_aq_desc desc;
1700 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
1702 cmd = &desc.params.sw_res_ctrl;
1705 return ICE_ERR_PARAM;
1707 if (buf_size < FLEX_ARRAY_SIZE(buf, elem, num_entries))
1708 return ICE_ERR_PARAM;
1710 ice_fill_dflt_direct_cmd_desc(&desc, opc);
1712 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
1714 cmd->num_entries = CPU_TO_LE16(num_entries);
1716 return ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);
1720 * ice_alloc_hw_res - allocate resource
1721 * @hw: pointer to the HW struct
1722 * @type: type of resource
1723 * @num: number of resources to allocate
1724 * @btm: allocate from bottom
1725 * @res: pointer to array that will receive the resources
1728 ice_alloc_hw_res(struct ice_hw *hw, u16 type, u16 num, bool btm, u16 *res)
1730 struct ice_aqc_alloc_free_res_elem *buf;
1731 enum ice_status status;
1734 buf_len = ice_struct_size(buf, elem, num);
1735 buf = (struct ice_aqc_alloc_free_res_elem *)ice_malloc(hw, buf_len);
1737 return ICE_ERR_NO_MEMORY;
1739 /* Prepare buffer to allocate resource. */
1740 buf->num_elems = CPU_TO_LE16(num);
1741 buf->res_type = CPU_TO_LE16(type | ICE_AQC_RES_TYPE_FLAG_DEDICATED |
1742 ICE_AQC_RES_TYPE_FLAG_IGNORE_INDEX);
1744 buf->res_type |= CPU_TO_LE16(ICE_AQC_RES_TYPE_FLAG_SCAN_BOTTOM);
1746 status = ice_aq_alloc_free_res(hw, 1, buf, buf_len,
1747 ice_aqc_opc_alloc_res, NULL);
1749 goto ice_alloc_res_exit;
1751 ice_memcpy(res, buf->elem, sizeof(*buf->elem) * num,
1752 ICE_NONDMA_TO_NONDMA);
1760 * ice_free_hw_res - free allocated HW resource
1761 * @hw: pointer to the HW struct
1762 * @type: type of resource to free
1763 * @num: number of resources
1764 * @res: pointer to array that contains the resources to free
1766 enum ice_status ice_free_hw_res(struct ice_hw *hw, u16 type, u16 num, u16 *res)
1768 struct ice_aqc_alloc_free_res_elem *buf;
1769 enum ice_status status;
1772 buf_len = ice_struct_size(buf, elem, num);
1773 buf = (struct ice_aqc_alloc_free_res_elem *)ice_malloc(hw, buf_len);
1775 return ICE_ERR_NO_MEMORY;
1777 /* Prepare buffer to free resource. */
1778 buf->num_elems = CPU_TO_LE16(num);
1779 buf->res_type = CPU_TO_LE16(type);
1780 ice_memcpy(buf->elem, res, sizeof(*buf->elem) * num,
1781 ICE_NONDMA_TO_NONDMA);
1783 status = ice_aq_alloc_free_res(hw, num, buf, buf_len,
1784 ice_aqc_opc_free_res, NULL);
1786 ice_debug(hw, ICE_DBG_SW, "CQ CMD Buffer:\n");
1793 * ice_get_num_per_func - determine number of resources per PF
1794 * @hw: pointer to the HW structure
1795 * @max: value to be evenly split between each PF
1797 * Determine the number of valid functions by going through the bitmap returned
1798 * from parsing capabilities and use this to calculate the number of resources
1799 * per PF based on the max value passed in.
1801 static u32 ice_get_num_per_func(struct ice_hw *hw, u32 max)
1805 #define ICE_CAPS_VALID_FUNCS_M 0xFF
1806 funcs = ice_hweight8(hw->dev_caps.common_cap.valid_functions &
1807 ICE_CAPS_VALID_FUNCS_M);
1816 * ice_parse_common_caps - parse common device/function capabilities
1817 * @hw: pointer to the HW struct
1818 * @caps: pointer to common capabilities structure
1819 * @elem: the capability element to parse
1820 * @prefix: message prefix for tracing capabilities
1822 * Given a capability element, extract relevant details into the common
1823 * capability structure.
1825 * Returns: true if the capability matches one of the common capability ids,
1829 ice_parse_common_caps(struct ice_hw *hw, struct ice_hw_common_caps *caps,
1830 struct ice_aqc_list_caps_elem *elem, const char *prefix)
1832 u32 logical_id = LE32_TO_CPU(elem->logical_id);
1833 u32 phys_id = LE32_TO_CPU(elem->phys_id);
1834 u32 number = LE32_TO_CPU(elem->number);
1835 u16 cap = LE16_TO_CPU(elem->cap);
1839 case ICE_AQC_CAPS_VALID_FUNCTIONS:
1840 caps->valid_functions = number;
1841 ice_debug(hw, ICE_DBG_INIT, "%s: valid_functions (bitmap) = %d\n", prefix,
1842 caps->valid_functions);
1844 case ICE_AQC_CAPS_DCB:
1845 caps->dcb = (number == 1);
1846 caps->active_tc_bitmap = logical_id;
1847 caps->maxtc = phys_id;
1848 ice_debug(hw, ICE_DBG_INIT, "%s: dcb = %d\n", prefix, caps->dcb);
1849 ice_debug(hw, ICE_DBG_INIT, "%s: active_tc_bitmap = %d\n", prefix,
1850 caps->active_tc_bitmap);
1851 ice_debug(hw, ICE_DBG_INIT, "%s: maxtc = %d\n", prefix, caps->maxtc);
1853 case ICE_AQC_CAPS_RSS:
1854 caps->rss_table_size = number;
1855 caps->rss_table_entry_width = logical_id;
1856 ice_debug(hw, ICE_DBG_INIT, "%s: rss_table_size = %d\n", prefix,
1857 caps->rss_table_size);
1858 ice_debug(hw, ICE_DBG_INIT, "%s: rss_table_entry_width = %d\n", prefix,
1859 caps->rss_table_entry_width);
1861 case ICE_AQC_CAPS_RXQS:
1862 caps->num_rxq = number;
1863 caps->rxq_first_id = phys_id;
1864 ice_debug(hw, ICE_DBG_INIT, "%s: num_rxq = %d\n", prefix,
1866 ice_debug(hw, ICE_DBG_INIT, "%s: rxq_first_id = %d\n", prefix,
1867 caps->rxq_first_id);
1869 case ICE_AQC_CAPS_TXQS:
1870 caps->num_txq = number;
1871 caps->txq_first_id = phys_id;
1872 ice_debug(hw, ICE_DBG_INIT, "%s: num_txq = %d\n", prefix,
1874 ice_debug(hw, ICE_DBG_INIT, "%s: txq_first_id = %d\n", prefix,
1875 caps->txq_first_id);
1877 case ICE_AQC_CAPS_MSIX:
1878 caps->num_msix_vectors = number;
1879 caps->msix_vector_first_id = phys_id;
1880 ice_debug(hw, ICE_DBG_INIT, "%s: num_msix_vectors = %d\n", prefix,
1881 caps->num_msix_vectors);
1882 ice_debug(hw, ICE_DBG_INIT, "%s: msix_vector_first_id = %d\n", prefix,
1883 caps->msix_vector_first_id);
1885 case ICE_AQC_CAPS_NVM_MGMT:
1886 caps->sec_rev_disabled =
1887 (number & ICE_NVM_MGMT_SEC_REV_DISABLED) ?
1889 ice_debug(hw, ICE_DBG_INIT, "%s: sec_rev_disabled = %d\n", prefix,
1890 caps->sec_rev_disabled);
1891 caps->update_disabled =
1892 (number & ICE_NVM_MGMT_UPDATE_DISABLED) ?
1894 ice_debug(hw, ICE_DBG_INIT, "%s: update_disabled = %d\n", prefix,
1895 caps->update_disabled);
1896 caps->nvm_unified_update =
1897 (number & ICE_NVM_MGMT_UNIFIED_UPD_SUPPORT) ?
1899 ice_debug(hw, ICE_DBG_INIT, "%s: nvm_unified_update = %d\n", prefix,
1900 caps->nvm_unified_update);
1902 case ICE_AQC_CAPS_MAX_MTU:
1903 caps->max_mtu = number;
1904 ice_debug(hw, ICE_DBG_INIT, "%s: max_mtu = %d\n",
1905 prefix, caps->max_mtu);
1908 /* Not one of the recognized common capabilities */
1916 * ice_recalc_port_limited_caps - Recalculate port limited capabilities
1917 * @hw: pointer to the HW structure
1918 * @caps: pointer to capabilities structure to fix
1920 * Re-calculate the capabilities that are dependent on the number of physical
1921 * ports; i.e. some features are not supported or function differently on
1922 * devices with more than 4 ports.
1925 ice_recalc_port_limited_caps(struct ice_hw *hw, struct ice_hw_common_caps *caps)
1927 /* This assumes device capabilities are always scanned before function
1928 * capabilities during the initialization flow.
1930 if (hw->dev_caps.num_funcs > 4) {
1931 /* Max 4 TCs per port */
1933 ice_debug(hw, ICE_DBG_INIT, "reducing maxtc to %d (based on #ports)\n",
1939 * ice_parse_vsi_func_caps - Parse ICE_AQC_CAPS_VSI function caps
1940 * @hw: pointer to the HW struct
1941 * @func_p: pointer to function capabilities structure
1942 * @cap: pointer to the capability element to parse
1944 * Extract function capabilities for ICE_AQC_CAPS_VSI.
1947 ice_parse_vsi_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p,
1948 struct ice_aqc_list_caps_elem *cap)
1950 func_p->guar_num_vsi = ice_get_num_per_func(hw, ICE_MAX_VSI);
1951 ice_debug(hw, ICE_DBG_INIT, "func caps: guar_num_vsi (fw) = %d\n",
1952 LE32_TO_CPU(cap->number));
1953 ice_debug(hw, ICE_DBG_INIT, "func caps: guar_num_vsi = %d\n",
1954 func_p->guar_num_vsi);
1958 * ice_parse_fdir_func_caps - Parse ICE_AQC_CAPS_FD function caps
1959 * @hw: pointer to the HW struct
1960 * @func_p: pointer to function capabilities structure
1962 * Extract function capabilities for ICE_AQC_CAPS_FD.
1965 ice_parse_fdir_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p)
1969 if (hw->dcf_enabled)
1971 reg_val = rd32(hw, GLQF_FD_SIZE);
1972 val = (reg_val & GLQF_FD_SIZE_FD_GSIZE_M) >>
1973 GLQF_FD_SIZE_FD_GSIZE_S;
1974 func_p->fd_fltr_guar =
1975 ice_get_num_per_func(hw, val);
1976 val = (reg_val & GLQF_FD_SIZE_FD_BSIZE_M) >>
1977 GLQF_FD_SIZE_FD_BSIZE_S;
1978 func_p->fd_fltr_best_effort = val;
1980 ice_debug(hw, ICE_DBG_INIT, "func caps: fd_fltr_guar = %d\n",
1981 func_p->fd_fltr_guar);
1982 ice_debug(hw, ICE_DBG_INIT, "func caps: fd_fltr_best_effort = %d\n",
1983 func_p->fd_fltr_best_effort);
1987 * ice_parse_func_caps - Parse function capabilities
1988 * @hw: pointer to the HW struct
1989 * @func_p: pointer to function capabilities structure
1990 * @buf: buffer containing the function capability records
1991 * @cap_count: the number of capabilities
1993 * Helper function to parse function (0x000A) capabilities list. For
1994 * capabilities shared between device and function, this relies on
1995 * ice_parse_common_caps.
1997 * Loop through the list of provided capabilities and extract the relevant
1998 * data into the function capabilities structured.
2001 ice_parse_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p,
2002 void *buf, u32 cap_count)
2004 struct ice_aqc_list_caps_elem *cap_resp;
2007 cap_resp = (struct ice_aqc_list_caps_elem *)buf;
2009 ice_memset(func_p, 0, sizeof(*func_p), ICE_NONDMA_MEM);
2011 for (i = 0; i < cap_count; i++) {
2012 u16 cap = LE16_TO_CPU(cap_resp[i].cap);
2015 found = ice_parse_common_caps(hw, &func_p->common_cap,
2016 &cap_resp[i], "func caps");
2019 case ICE_AQC_CAPS_VSI:
2020 ice_parse_vsi_func_caps(hw, func_p, &cap_resp[i]);
2022 case ICE_AQC_CAPS_FD:
2023 ice_parse_fdir_func_caps(hw, func_p);
2026 /* Don't list common capabilities as unknown */
2028 ice_debug(hw, ICE_DBG_INIT, "func caps: unknown capability[%d]: 0x%x\n",
2034 ice_recalc_port_limited_caps(hw, &func_p->common_cap);
2038 * ice_parse_valid_functions_cap - Parse ICE_AQC_CAPS_VALID_FUNCTIONS caps
2039 * @hw: pointer to the HW struct
2040 * @dev_p: pointer to device capabilities structure
2041 * @cap: capability element to parse
2043 * Parse ICE_AQC_CAPS_VALID_FUNCTIONS for device capabilities.
2046 ice_parse_valid_functions_cap(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p,
2047 struct ice_aqc_list_caps_elem *cap)
2049 u32 number = LE32_TO_CPU(cap->number);
2051 dev_p->num_funcs = ice_hweight32(number);
2052 ice_debug(hw, ICE_DBG_INIT, "dev caps: num_funcs = %d\n",
2057 * ice_parse_vsi_dev_caps - Parse ICE_AQC_CAPS_VSI device caps
2058 * @hw: pointer to the HW struct
2059 * @dev_p: pointer to device capabilities structure
2060 * @cap: capability element to parse
2062 * Parse ICE_AQC_CAPS_VSI for device capabilities.
2065 ice_parse_vsi_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p,
2066 struct ice_aqc_list_caps_elem *cap)
2068 u32 number = LE32_TO_CPU(cap->number);
2070 dev_p->num_vsi_allocd_to_host = number;
2071 ice_debug(hw, ICE_DBG_INIT, "dev caps: num_vsi_allocd_to_host = %d\n",
2072 dev_p->num_vsi_allocd_to_host);
2076 * ice_parse_fdir_dev_caps - Parse ICE_AQC_CAPS_FD device caps
2077 * @hw: pointer to the HW struct
2078 * @dev_p: pointer to device capabilities structure
2079 * @cap: capability element to parse
2081 * Parse ICE_AQC_CAPS_FD for device capabilities.
2084 ice_parse_fdir_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p,
2085 struct ice_aqc_list_caps_elem *cap)
2087 u32 number = LE32_TO_CPU(cap->number);
2089 dev_p->num_flow_director_fltr = number;
2090 ice_debug(hw, ICE_DBG_INIT, "dev caps: num_flow_director_fltr = %d\n",
2091 dev_p->num_flow_director_fltr);
2095 * ice_parse_dev_caps - Parse device capabilities
2096 * @hw: pointer to the HW struct
2097 * @dev_p: pointer to device capabilities structure
2098 * @buf: buffer containing the device capability records
2099 * @cap_count: the number of capabilities
2101 * Helper device to parse device (0x000B) capabilities list. For
2102 * capabilities shared between device and function, this relies on
2103 * ice_parse_common_caps.
2105 * Loop through the list of provided capabilities and extract the relevant
2106 * data into the device capabilities structured.
2109 ice_parse_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p,
2110 void *buf, u32 cap_count)
2112 struct ice_aqc_list_caps_elem *cap_resp;
2115 cap_resp = (struct ice_aqc_list_caps_elem *)buf;
2117 ice_memset(dev_p, 0, sizeof(*dev_p), ICE_NONDMA_MEM);
2119 for (i = 0; i < cap_count; i++) {
2120 u16 cap = LE16_TO_CPU(cap_resp[i].cap);
2123 found = ice_parse_common_caps(hw, &dev_p->common_cap,
2124 &cap_resp[i], "dev caps");
2127 case ICE_AQC_CAPS_VALID_FUNCTIONS:
2128 ice_parse_valid_functions_cap(hw, dev_p, &cap_resp[i]);
2130 case ICE_AQC_CAPS_VSI:
2131 ice_parse_vsi_dev_caps(hw, dev_p, &cap_resp[i]);
2133 case ICE_AQC_CAPS_FD:
2134 ice_parse_fdir_dev_caps(hw, dev_p, &cap_resp[i]);
2137 /* Don't list common capabilities as unknown */
2139 ice_debug(hw, ICE_DBG_INIT, "dev caps: unknown capability[%d]: 0x%x\n",
2145 ice_recalc_port_limited_caps(hw, &dev_p->common_cap);
2149 * ice_aq_list_caps - query function/device capabilities
2150 * @hw: pointer to the HW struct
2151 * @buf: a buffer to hold the capabilities
2152 * @buf_size: size of the buffer
2153 * @cap_count: if not NULL, set to the number of capabilities reported
2154 * @opc: capabilities type to discover, device or function
2155 * @cd: pointer to command details structure or NULL
2157 * Get the function (0x000A) or device (0x000B) capabilities description from
2158 * firmware and store it in the buffer.
2160 * If the cap_count pointer is not NULL, then it is set to the number of
2161 * capabilities firmware will report. Note that if the buffer size is too
2162 * small, it is possible the command will return ICE_AQ_ERR_ENOMEM. The
2163 * cap_count will still be updated in this case. It is recommended that the
2164 * buffer size be set to ICE_AQ_MAX_BUF_LEN (the largest possible buffer that
2165 * firmware could return) to avoid this.
2167 static enum ice_status
2168 ice_aq_list_caps(struct ice_hw *hw, void *buf, u16 buf_size, u32 *cap_count,
2169 enum ice_adminq_opc opc, struct ice_sq_cd *cd)
2171 struct ice_aqc_list_caps *cmd;
2172 struct ice_aq_desc desc;
2173 enum ice_status status;
2175 cmd = &desc.params.get_cap;
2177 if (opc != ice_aqc_opc_list_func_caps &&
2178 opc != ice_aqc_opc_list_dev_caps)
2179 return ICE_ERR_PARAM;
2181 ice_fill_dflt_direct_cmd_desc(&desc, opc);
2182 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);
2185 *cap_count = LE32_TO_CPU(cmd->count);
2191 * ice_discover_dev_caps - Read and extract device capabilities
2192 * @hw: pointer to the hardware structure
2193 * @dev_caps: pointer to device capabilities structure
2195 * Read the device capabilities and extract them into the dev_caps structure
2198 static enum ice_status
2199 ice_discover_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_caps)
2201 enum ice_status status;
2205 cbuf = ice_malloc(hw, ICE_AQ_MAX_BUF_LEN);
2207 return ICE_ERR_NO_MEMORY;
2209 /* Although the driver doesn't know the number of capabilities the
2210 * device will return, we can simply send a 4KB buffer, the maximum
2211 * possible size that firmware can return.
2213 cap_count = ICE_AQ_MAX_BUF_LEN / sizeof(struct ice_aqc_list_caps_elem);
2215 status = ice_aq_list_caps(hw, cbuf, ICE_AQ_MAX_BUF_LEN, &cap_count,
2216 ice_aqc_opc_list_dev_caps, NULL);
2218 ice_parse_dev_caps(hw, dev_caps, cbuf, cap_count);
2225 * ice_discover_func_caps - Read and extract function capabilities
2226 * @hw: pointer to the hardware structure
2227 * @func_caps: pointer to function capabilities structure
2229 * Read the function capabilities and extract them into the func_caps structure
2232 static enum ice_status
2233 ice_discover_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_caps)
2235 enum ice_status status;
2239 cbuf = ice_malloc(hw, ICE_AQ_MAX_BUF_LEN);
2241 return ICE_ERR_NO_MEMORY;
2243 /* Although the driver doesn't know the number of capabilities the
2244 * device will return, we can simply send a 4KB buffer, the maximum
2245 * possible size that firmware can return.
2247 cap_count = ICE_AQ_MAX_BUF_LEN / sizeof(struct ice_aqc_list_caps_elem);
2249 status = ice_aq_list_caps(hw, cbuf, ICE_AQ_MAX_BUF_LEN, &cap_count,
2250 ice_aqc_opc_list_func_caps, NULL);
2252 ice_parse_func_caps(hw, func_caps, cbuf, cap_count);
2259 * ice_set_safe_mode_caps - Override dev/func capabilities when in safe mode
2260 * @hw: pointer to the hardware structure
2262 void ice_set_safe_mode_caps(struct ice_hw *hw)
2264 struct ice_hw_func_caps *func_caps = &hw->func_caps;
2265 struct ice_hw_dev_caps *dev_caps = &hw->dev_caps;
2266 struct ice_hw_common_caps cached_caps;
2269 /* cache some func_caps values that should be restored after memset */
2270 cached_caps = func_caps->common_cap;
2272 /* unset func capabilities */
2273 memset(func_caps, 0, sizeof(*func_caps));
2275 #define ICE_RESTORE_FUNC_CAP(name) \
2276 func_caps->common_cap.name = cached_caps.name
2278 /* restore cached values */
2279 ICE_RESTORE_FUNC_CAP(valid_functions);
2280 ICE_RESTORE_FUNC_CAP(txq_first_id);
2281 ICE_RESTORE_FUNC_CAP(rxq_first_id);
2282 ICE_RESTORE_FUNC_CAP(msix_vector_first_id);
2283 ICE_RESTORE_FUNC_CAP(max_mtu);
2284 ICE_RESTORE_FUNC_CAP(nvm_unified_update);
2286 /* one Tx and one Rx queue in safe mode */
2287 func_caps->common_cap.num_rxq = 1;
2288 func_caps->common_cap.num_txq = 1;
2290 /* two MSIX vectors, one for traffic and one for misc causes */
2291 func_caps->common_cap.num_msix_vectors = 2;
2292 func_caps->guar_num_vsi = 1;
2294 /* cache some dev_caps values that should be restored after memset */
2295 cached_caps = dev_caps->common_cap;
2296 num_funcs = dev_caps->num_funcs;
2298 /* unset dev capabilities */
2299 memset(dev_caps, 0, sizeof(*dev_caps));
2301 #define ICE_RESTORE_DEV_CAP(name) \
2302 dev_caps->common_cap.name = cached_caps.name
2304 /* restore cached values */
2305 ICE_RESTORE_DEV_CAP(valid_functions);
2306 ICE_RESTORE_DEV_CAP(txq_first_id);
2307 ICE_RESTORE_DEV_CAP(rxq_first_id);
2308 ICE_RESTORE_DEV_CAP(msix_vector_first_id);
2309 ICE_RESTORE_DEV_CAP(max_mtu);
2310 ICE_RESTORE_DEV_CAP(nvm_unified_update);
2311 dev_caps->num_funcs = num_funcs;
2313 /* one Tx and one Rx queue per function in safe mode */
2314 dev_caps->common_cap.num_rxq = num_funcs;
2315 dev_caps->common_cap.num_txq = num_funcs;
2317 /* two MSIX vectors per function */
2318 dev_caps->common_cap.num_msix_vectors = 2 * num_funcs;
2322 * ice_get_caps - get info about the HW
2323 * @hw: pointer to the hardware structure
2325 enum ice_status ice_get_caps(struct ice_hw *hw)
2327 enum ice_status status;
2329 status = ice_discover_dev_caps(hw, &hw->dev_caps);
2333 return ice_discover_func_caps(hw, &hw->func_caps);
2337 * ice_aq_manage_mac_write - manage MAC address write command
2338 * @hw: pointer to the HW struct
2339 * @mac_addr: MAC address to be written as LAA/LAA+WoL/Port address
2340 * @flags: flags to control write behavior
2341 * @cd: pointer to command details structure or NULL
2343 * This function is used to write MAC address to the NVM (0x0108).
2346 ice_aq_manage_mac_write(struct ice_hw *hw, const u8 *mac_addr, u8 flags,
2347 struct ice_sq_cd *cd)
2349 struct ice_aqc_manage_mac_write *cmd;
2350 struct ice_aq_desc desc;
2352 cmd = &desc.params.mac_write;
2353 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_write);
2356 ice_memcpy(cmd->mac_addr, mac_addr, ETH_ALEN, ICE_NONDMA_TO_DMA);
2358 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
2362 * ice_aq_clear_pxe_mode
2363 * @hw: pointer to the HW struct
2365 * Tell the firmware that the driver is taking over from PXE (0x0110).
2367 static enum ice_status ice_aq_clear_pxe_mode(struct ice_hw *hw)
2369 struct ice_aq_desc desc;
2371 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pxe_mode);
2372 desc.params.clear_pxe.rx_cnt = ICE_AQC_CLEAR_PXE_RX_CNT;
2374 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
2378 * ice_clear_pxe_mode - clear pxe operations mode
2379 * @hw: pointer to the HW struct
2381 * Make sure all PXE mode settings are cleared, including things
2382 * like descriptor fetch/write-back mode.
2384 void ice_clear_pxe_mode(struct ice_hw *hw)
2386 if (ice_check_sq_alive(hw, &hw->adminq))
2387 ice_aq_clear_pxe_mode(hw);
2391 * ice_get_link_speed_based_on_phy_type - returns link speed
2392 * @phy_type_low: lower part of phy_type
2393 * @phy_type_high: higher part of phy_type
2395 * This helper function will convert an entry in PHY type structure
2396 * [phy_type_low, phy_type_high] to its corresponding link speed.
2397 * Note: In the structure of [phy_type_low, phy_type_high], there should
2398 * be one bit set, as this function will convert one PHY type to its
2400 * If no bit gets set, ICE_LINK_SPEED_UNKNOWN will be returned
2401 * If more than one bit gets set, ICE_LINK_SPEED_UNKNOWN will be returned
2404 ice_get_link_speed_based_on_phy_type(u64 phy_type_low, u64 phy_type_high)
2406 u16 speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN;
2407 u16 speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN;
2409 switch (phy_type_low) {
2410 case ICE_PHY_TYPE_LOW_100BASE_TX:
2411 case ICE_PHY_TYPE_LOW_100M_SGMII:
2412 speed_phy_type_low = ICE_AQ_LINK_SPEED_100MB;
2414 case ICE_PHY_TYPE_LOW_1000BASE_T:
2415 case ICE_PHY_TYPE_LOW_1000BASE_SX:
2416 case ICE_PHY_TYPE_LOW_1000BASE_LX:
2417 case ICE_PHY_TYPE_LOW_1000BASE_KX:
2418 case ICE_PHY_TYPE_LOW_1G_SGMII:
2419 speed_phy_type_low = ICE_AQ_LINK_SPEED_1000MB;
2421 case ICE_PHY_TYPE_LOW_2500BASE_T:
2422 case ICE_PHY_TYPE_LOW_2500BASE_X:
2423 case ICE_PHY_TYPE_LOW_2500BASE_KX:
2424 speed_phy_type_low = ICE_AQ_LINK_SPEED_2500MB;
2426 case ICE_PHY_TYPE_LOW_5GBASE_T:
2427 case ICE_PHY_TYPE_LOW_5GBASE_KR:
2428 speed_phy_type_low = ICE_AQ_LINK_SPEED_5GB;
2430 case ICE_PHY_TYPE_LOW_10GBASE_T:
2431 case ICE_PHY_TYPE_LOW_10G_SFI_DA:
2432 case ICE_PHY_TYPE_LOW_10GBASE_SR:
2433 case ICE_PHY_TYPE_LOW_10GBASE_LR:
2434 case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1:
2435 case ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC:
2436 case ICE_PHY_TYPE_LOW_10G_SFI_C2C:
2437 speed_phy_type_low = ICE_AQ_LINK_SPEED_10GB;
2439 case ICE_PHY_TYPE_LOW_25GBASE_T:
2440 case ICE_PHY_TYPE_LOW_25GBASE_CR:
2441 case ICE_PHY_TYPE_LOW_25GBASE_CR_S:
2442 case ICE_PHY_TYPE_LOW_25GBASE_CR1:
2443 case ICE_PHY_TYPE_LOW_25GBASE_SR:
2444 case ICE_PHY_TYPE_LOW_25GBASE_LR:
2445 case ICE_PHY_TYPE_LOW_25GBASE_KR:
2446 case ICE_PHY_TYPE_LOW_25GBASE_KR_S:
2447 case ICE_PHY_TYPE_LOW_25GBASE_KR1:
2448 case ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC:
2449 case ICE_PHY_TYPE_LOW_25G_AUI_C2C:
2450 speed_phy_type_low = ICE_AQ_LINK_SPEED_25GB;
2452 case ICE_PHY_TYPE_LOW_40GBASE_CR4:
2453 case ICE_PHY_TYPE_LOW_40GBASE_SR4:
2454 case ICE_PHY_TYPE_LOW_40GBASE_LR4:
2455 case ICE_PHY_TYPE_LOW_40GBASE_KR4:
2456 case ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC:
2457 case ICE_PHY_TYPE_LOW_40G_XLAUI:
2458 speed_phy_type_low = ICE_AQ_LINK_SPEED_40GB;
2460 case ICE_PHY_TYPE_LOW_50GBASE_CR2:
2461 case ICE_PHY_TYPE_LOW_50GBASE_SR2:
2462 case ICE_PHY_TYPE_LOW_50GBASE_LR2:
2463 case ICE_PHY_TYPE_LOW_50GBASE_KR2:
2464 case ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC:
2465 case ICE_PHY_TYPE_LOW_50G_LAUI2:
2466 case ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC:
2467 case ICE_PHY_TYPE_LOW_50G_AUI2:
2468 case ICE_PHY_TYPE_LOW_50GBASE_CP:
2469 case ICE_PHY_TYPE_LOW_50GBASE_SR:
2470 case ICE_PHY_TYPE_LOW_50GBASE_FR:
2471 case ICE_PHY_TYPE_LOW_50GBASE_LR:
2472 case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4:
2473 case ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC:
2474 case ICE_PHY_TYPE_LOW_50G_AUI1:
2475 speed_phy_type_low = ICE_AQ_LINK_SPEED_50GB;
2477 case ICE_PHY_TYPE_LOW_100GBASE_CR4:
2478 case ICE_PHY_TYPE_LOW_100GBASE_SR4:
2479 case ICE_PHY_TYPE_LOW_100GBASE_LR4:
2480 case ICE_PHY_TYPE_LOW_100GBASE_KR4:
2481 case ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC:
2482 case ICE_PHY_TYPE_LOW_100G_CAUI4:
2483 case ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC:
2484 case ICE_PHY_TYPE_LOW_100G_AUI4:
2485 case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4:
2486 case ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4:
2487 case ICE_PHY_TYPE_LOW_100GBASE_CP2:
2488 case ICE_PHY_TYPE_LOW_100GBASE_SR2:
2489 case ICE_PHY_TYPE_LOW_100GBASE_DR:
2490 speed_phy_type_low = ICE_AQ_LINK_SPEED_100GB;
2493 speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN;
2497 switch (phy_type_high) {
2498 case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4:
2499 case ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC:
2500 case ICE_PHY_TYPE_HIGH_100G_CAUI2:
2501 case ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC:
2502 case ICE_PHY_TYPE_HIGH_100G_AUI2:
2503 speed_phy_type_high = ICE_AQ_LINK_SPEED_100GB;
2506 speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN;
2510 if (speed_phy_type_low == ICE_AQ_LINK_SPEED_UNKNOWN &&
2511 speed_phy_type_high == ICE_AQ_LINK_SPEED_UNKNOWN)
2512 return ICE_AQ_LINK_SPEED_UNKNOWN;
2513 else if (speed_phy_type_low != ICE_AQ_LINK_SPEED_UNKNOWN &&
2514 speed_phy_type_high != ICE_AQ_LINK_SPEED_UNKNOWN)
2515 return ICE_AQ_LINK_SPEED_UNKNOWN;
2516 else if (speed_phy_type_low != ICE_AQ_LINK_SPEED_UNKNOWN &&
2517 speed_phy_type_high == ICE_AQ_LINK_SPEED_UNKNOWN)
2518 return speed_phy_type_low;
2520 return speed_phy_type_high;
2524 * ice_update_phy_type
2525 * @phy_type_low: pointer to the lower part of phy_type
2526 * @phy_type_high: pointer to the higher part of phy_type
2527 * @link_speeds_bitmap: targeted link speeds bitmap
2529 * Note: For the link_speeds_bitmap structure, you can check it at
2530 * [ice_aqc_get_link_status->link_speed]. Caller can pass in
2531 * link_speeds_bitmap include multiple speeds.
2533 * Each entry in this [phy_type_low, phy_type_high] structure will
2534 * present a certain link speed. This helper function will turn on bits
2535 * in [phy_type_low, phy_type_high] structure based on the value of
2536 * link_speeds_bitmap input parameter.
2539 ice_update_phy_type(u64 *phy_type_low, u64 *phy_type_high,
2540 u16 link_speeds_bitmap)
2547 /* We first check with low part of phy_type */
2548 for (index = 0; index <= ICE_PHY_TYPE_LOW_MAX_INDEX; index++) {
2549 pt_low = BIT_ULL(index);
2550 speed = ice_get_link_speed_based_on_phy_type(pt_low, 0);
2552 if (link_speeds_bitmap & speed)
2553 *phy_type_low |= BIT_ULL(index);
2556 /* We then check with high part of phy_type */
2557 for (index = 0; index <= ICE_PHY_TYPE_HIGH_MAX_INDEX; index++) {
2558 pt_high = BIT_ULL(index);
2559 speed = ice_get_link_speed_based_on_phy_type(0, pt_high);
2561 if (link_speeds_bitmap & speed)
2562 *phy_type_high |= BIT_ULL(index);
2567 * ice_aq_set_phy_cfg
2568 * @hw: pointer to the HW struct
2569 * @pi: port info structure of the interested logical port
2570 * @cfg: structure with PHY configuration data to be set
2571 * @cd: pointer to command details structure or NULL
2573 * Set the various PHY configuration parameters supported on the Port.
2574 * One or more of the Set PHY config parameters may be ignored in an MFP
2575 * mode as the PF may not have the privilege to set some of the PHY Config
2576 * parameters. This status will be indicated by the command response (0x0601).
2579 ice_aq_set_phy_cfg(struct ice_hw *hw, struct ice_port_info *pi,
2580 struct ice_aqc_set_phy_cfg_data *cfg, struct ice_sq_cd *cd)
2582 struct ice_aq_desc desc;
2583 enum ice_status status;
2586 return ICE_ERR_PARAM;
2588 /* Ensure that only valid bits of cfg->caps can be turned on. */
2589 if (cfg->caps & ~ICE_AQ_PHY_ENA_VALID_MASK) {
2590 ice_debug(hw, ICE_DBG_PHY, "Invalid bit is set in ice_aqc_set_phy_cfg_data->caps : 0x%x\n",
2593 cfg->caps &= ICE_AQ_PHY_ENA_VALID_MASK;
2596 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_phy_cfg);
2597 desc.params.set_phy.lport_num = pi->lport;
2598 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
2600 ice_debug(hw, ICE_DBG_LINK, "set phy cfg\n");
2601 ice_debug(hw, ICE_DBG_LINK, " phy_type_low = 0x%llx\n",
2602 (unsigned long long)LE64_TO_CPU(cfg->phy_type_low));
2603 ice_debug(hw, ICE_DBG_LINK, " phy_type_high = 0x%llx\n",
2604 (unsigned long long)LE64_TO_CPU(cfg->phy_type_high));
2605 ice_debug(hw, ICE_DBG_LINK, " caps = 0x%x\n", cfg->caps);
2606 ice_debug(hw, ICE_DBG_LINK, " low_power_ctrl_an = 0x%x\n",
2607 cfg->low_power_ctrl_an);
2608 ice_debug(hw, ICE_DBG_LINK, " eee_cap = 0x%x\n", cfg->eee_cap);
2609 ice_debug(hw, ICE_DBG_LINK, " eeer_value = 0x%x\n", cfg->eeer_value);
2610 ice_debug(hw, ICE_DBG_LINK, " link_fec_opt = 0x%x\n",
2613 status = ice_aq_send_cmd(hw, &desc, cfg, sizeof(*cfg), cd);
2615 if (hw->adminq.sq_last_status == ICE_AQ_RC_EMODE)
2616 status = ICE_SUCCESS;
2619 pi->phy.curr_user_phy_cfg = *cfg;
2625 * ice_update_link_info - update status of the HW network link
2626 * @pi: port info structure of the interested logical port
2628 enum ice_status ice_update_link_info(struct ice_port_info *pi)
2630 struct ice_link_status *li;
2631 enum ice_status status;
2634 return ICE_ERR_PARAM;
2636 li = &pi->phy.link_info;
2638 status = ice_aq_get_link_info(pi, true, NULL, NULL);
2642 if (li->link_info & ICE_AQ_MEDIA_AVAILABLE) {
2643 struct ice_aqc_get_phy_caps_data *pcaps;
2647 pcaps = (struct ice_aqc_get_phy_caps_data *)
2648 ice_malloc(hw, sizeof(*pcaps));
2650 return ICE_ERR_NO_MEMORY;
2652 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_TOPO_CAP,
2655 ice_free(hw, pcaps);
2662 * ice_cache_phy_user_req
2663 * @pi: port information structure
2664 * @cache_data: PHY logging data
2665 * @cache_mode: PHY logging mode
2667 * Log the user request on (FC, FEC, SPEED) for later user.
2670 ice_cache_phy_user_req(struct ice_port_info *pi,
2671 struct ice_phy_cache_mode_data cache_data,
2672 enum ice_phy_cache_mode cache_mode)
2677 switch (cache_mode) {
2679 pi->phy.curr_user_fc_req = cache_data.data.curr_user_fc_req;
2681 case ICE_SPEED_MODE:
2682 pi->phy.curr_user_speed_req =
2683 cache_data.data.curr_user_speed_req;
2686 pi->phy.curr_user_fec_req = cache_data.data.curr_user_fec_req;
2694 * ice_caps_to_fc_mode
2695 * @caps: PHY capabilities
2697 * Convert PHY FC capabilities to ice FC mode
2699 enum ice_fc_mode ice_caps_to_fc_mode(u8 caps)
2701 if (caps & ICE_AQC_PHY_EN_TX_LINK_PAUSE &&
2702 caps & ICE_AQC_PHY_EN_RX_LINK_PAUSE)
2705 if (caps & ICE_AQC_PHY_EN_TX_LINK_PAUSE)
2706 return ICE_FC_TX_PAUSE;
2708 if (caps & ICE_AQC_PHY_EN_RX_LINK_PAUSE)
2709 return ICE_FC_RX_PAUSE;
2715 * ice_caps_to_fec_mode
2716 * @caps: PHY capabilities
2717 * @fec_options: Link FEC options
2719 * Convert PHY FEC capabilities to ice FEC mode
2721 enum ice_fec_mode ice_caps_to_fec_mode(u8 caps, u8 fec_options)
2723 if (caps & ICE_AQC_PHY_EN_AUTO_FEC)
2724 return ICE_FEC_AUTO;
2726 if (fec_options & (ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN |
2727 ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ |
2728 ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN |
2729 ICE_AQC_PHY_FEC_25G_KR_REQ))
2730 return ICE_FEC_BASER;
2732 if (fec_options & (ICE_AQC_PHY_FEC_25G_RS_528_REQ |
2733 ICE_AQC_PHY_FEC_25G_RS_544_REQ |
2734 ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN))
2737 return ICE_FEC_NONE;
2741 * ice_cfg_phy_fc - Configure PHY FC data based on FC mode
2742 * @pi: port information structure
2743 * @cfg: PHY configuration data to set FC mode
2744 * @req_mode: FC mode to configure
2746 static enum ice_status
2747 ice_cfg_phy_fc(struct ice_port_info *pi, struct ice_aqc_set_phy_cfg_data *cfg,
2748 enum ice_fc_mode req_mode)
2750 struct ice_phy_cache_mode_data cache_data;
2751 u8 pause_mask = 0x0;
2754 return ICE_ERR_BAD_PTR;
2759 struct ice_aqc_get_phy_caps_data *pcaps;
2760 enum ice_status status;
2762 pcaps = (struct ice_aqc_get_phy_caps_data *)
2763 ice_malloc(pi->hw, sizeof(*pcaps));
2765 return ICE_ERR_NO_MEMORY;
2767 /* Query the value of FC that both the NIC and attached media
2770 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_TOPO_CAP,
2773 ice_free(pi->hw, pcaps);
2777 pause_mask |= pcaps->caps & ICE_AQC_PHY_EN_TX_LINK_PAUSE;
2778 pause_mask |= pcaps->caps & ICE_AQC_PHY_EN_RX_LINK_PAUSE;
2780 ice_free(pi->hw, pcaps);
2784 pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE;
2785 pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE;
2787 case ICE_FC_RX_PAUSE:
2788 pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE;
2790 case ICE_FC_TX_PAUSE:
2791 pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE;
2797 /* clear the old pause settings */
2798 cfg->caps &= ~(ICE_AQC_PHY_EN_TX_LINK_PAUSE |
2799 ICE_AQC_PHY_EN_RX_LINK_PAUSE);
2801 /* set the new capabilities */
2802 cfg->caps |= pause_mask;
2804 /* Cache user FC request */
2805 cache_data.data.curr_user_fc_req = req_mode;
2806 ice_cache_phy_user_req(pi, cache_data, ICE_FC_MODE);
2813 * @pi: port information structure
2814 * @aq_failures: pointer to status code, specific to ice_set_fc routine
2815 * @ena_auto_link_update: enable automatic link update
2817 * Set the requested flow control mode.
2820 ice_set_fc(struct ice_port_info *pi, u8 *aq_failures, bool ena_auto_link_update)
2822 struct ice_aqc_set_phy_cfg_data cfg = { 0 };
2823 struct ice_aqc_get_phy_caps_data *pcaps;
2824 enum ice_status status;
2827 if (!pi || !aq_failures)
2828 return ICE_ERR_BAD_PTR;
2833 pcaps = (struct ice_aqc_get_phy_caps_data *)
2834 ice_malloc(hw, sizeof(*pcaps));
2836 return ICE_ERR_NO_MEMORY;
2838 /* Get the current PHY config */
2839 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_SW_CFG, pcaps,
2842 *aq_failures = ICE_SET_FC_AQ_FAIL_GET;
2846 ice_copy_phy_caps_to_cfg(pi, pcaps, &cfg);
2848 /* Configure the set PHY data */
2849 status = ice_cfg_phy_fc(pi, &cfg, pi->fc.req_mode);
2851 if (status != ICE_ERR_BAD_PTR)
2852 *aq_failures = ICE_SET_FC_AQ_FAIL_GET;
2857 /* If the capabilities have changed, then set the new config */
2858 if (cfg.caps != pcaps->caps) {
2859 int retry_count, retry_max = 10;
2861 /* Auto restart link so settings take effect */
2862 if (ena_auto_link_update)
2863 cfg.caps |= ICE_AQ_PHY_ENA_AUTO_LINK_UPDT;
2865 status = ice_aq_set_phy_cfg(hw, pi, &cfg, NULL);
2867 *aq_failures = ICE_SET_FC_AQ_FAIL_SET;
2871 /* Update the link info
2872 * It sometimes takes a really long time for link to
2873 * come back from the atomic reset. Thus, we wait a
2876 for (retry_count = 0; retry_count < retry_max; retry_count++) {
2877 status = ice_update_link_info(pi);
2879 if (status == ICE_SUCCESS)
2882 ice_msec_delay(100, true);
2886 *aq_failures = ICE_SET_FC_AQ_FAIL_UPDATE;
2890 ice_free(hw, pcaps);
2895 * ice_phy_caps_equals_cfg
2896 * @phy_caps: PHY capabilities
2897 * @phy_cfg: PHY configuration
2899 * Helper function to determine if PHY capabilities matches PHY
2903 ice_phy_caps_equals_cfg(struct ice_aqc_get_phy_caps_data *phy_caps,
2904 struct ice_aqc_set_phy_cfg_data *phy_cfg)
2906 u8 caps_mask, cfg_mask;
2908 if (!phy_caps || !phy_cfg)
2911 /* These bits are not common between capabilities and configuration.
2912 * Do not use them to determine equality.
2914 caps_mask = ICE_AQC_PHY_CAPS_MASK & ~(ICE_AQC_PHY_AN_MODE |
2915 ICE_AQC_PHY_EN_MOD_QUAL);
2916 cfg_mask = ICE_AQ_PHY_ENA_VALID_MASK & ~ICE_AQ_PHY_ENA_AUTO_LINK_UPDT;
2918 if (phy_caps->phy_type_low != phy_cfg->phy_type_low ||
2919 phy_caps->phy_type_high != phy_cfg->phy_type_high ||
2920 ((phy_caps->caps & caps_mask) != (phy_cfg->caps & cfg_mask)) ||
2921 phy_caps->low_power_ctrl_an != phy_cfg->low_power_ctrl_an ||
2922 phy_caps->eee_cap != phy_cfg->eee_cap ||
2923 phy_caps->eeer_value != phy_cfg->eeer_value ||
2924 phy_caps->link_fec_options != phy_cfg->link_fec_opt)
2931 * ice_copy_phy_caps_to_cfg - Copy PHY ability data to configuration data
2932 * @pi: port information structure
2933 * @caps: PHY ability structure to copy date from
2934 * @cfg: PHY configuration structure to copy data to
2936 * Helper function to copy AQC PHY get ability data to PHY set configuration
2940 ice_copy_phy_caps_to_cfg(struct ice_port_info *pi,
2941 struct ice_aqc_get_phy_caps_data *caps,
2942 struct ice_aqc_set_phy_cfg_data *cfg)
2944 if (!pi || !caps || !cfg)
2947 ice_memset(cfg, 0, sizeof(*cfg), ICE_NONDMA_MEM);
2948 cfg->phy_type_low = caps->phy_type_low;
2949 cfg->phy_type_high = caps->phy_type_high;
2950 cfg->caps = caps->caps;
2951 cfg->low_power_ctrl_an = caps->low_power_ctrl_an;
2952 cfg->eee_cap = caps->eee_cap;
2953 cfg->eeer_value = caps->eeer_value;
2954 cfg->link_fec_opt = caps->link_fec_options;
2955 cfg->module_compliance_enforcement =
2956 caps->module_compliance_enforcement;
2958 if (ice_fw_supports_link_override(pi->hw)) {
2959 struct ice_link_default_override_tlv tlv;
2961 if (ice_get_link_default_override(&tlv, pi))
2964 if (tlv.options & ICE_LINK_OVERRIDE_STRICT_MODE)
2965 cfg->module_compliance_enforcement |=
2966 ICE_LINK_OVERRIDE_STRICT_MODE;
2971 * ice_cfg_phy_fec - Configure PHY FEC data based on FEC mode
2972 * @pi: port information structure
2973 * @cfg: PHY configuration data to set FEC mode
2974 * @fec: FEC mode to configure
2977 ice_cfg_phy_fec(struct ice_port_info *pi, struct ice_aqc_set_phy_cfg_data *cfg,
2978 enum ice_fec_mode fec)
2980 struct ice_aqc_get_phy_caps_data *pcaps;
2981 enum ice_status status = ICE_SUCCESS;
2985 return ICE_ERR_BAD_PTR;
2989 pcaps = (struct ice_aqc_get_phy_caps_data *)
2990 ice_malloc(hw, sizeof(*pcaps));
2992 return ICE_ERR_NO_MEMORY;
2994 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_TOPO_CAP, pcaps,
2999 cfg->caps |= (pcaps->caps & ICE_AQC_PHY_EN_AUTO_FEC);
3000 cfg->link_fec_opt = pcaps->link_fec_options;
3004 /* Clear RS bits, and AND BASE-R ability
3005 * bits and OR request bits.
3007 cfg->link_fec_opt &= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN |
3008 ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN;
3009 cfg->link_fec_opt |= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ |
3010 ICE_AQC_PHY_FEC_25G_KR_REQ;
3013 /* Clear BASE-R bits, and AND RS ability
3014 * bits and OR request bits.
3016 cfg->link_fec_opt &= ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN;
3017 cfg->link_fec_opt |= ICE_AQC_PHY_FEC_25G_RS_528_REQ |
3018 ICE_AQC_PHY_FEC_25G_RS_544_REQ;
3021 /* Clear all FEC option bits. */
3022 cfg->link_fec_opt &= ~ICE_AQC_PHY_FEC_MASK;
3025 /* AND auto FEC bit, and all caps bits. */
3026 cfg->caps &= ICE_AQC_PHY_CAPS_MASK;
3027 cfg->link_fec_opt |= pcaps->link_fec_options;
3030 status = ICE_ERR_PARAM;
3034 if (fec == ICE_FEC_AUTO && ice_fw_supports_link_override(pi->hw)) {
3035 struct ice_link_default_override_tlv tlv;
3037 if (ice_get_link_default_override(&tlv, pi))
3040 if (!(tlv.options & ICE_LINK_OVERRIDE_STRICT_MODE) &&
3041 (tlv.options & ICE_LINK_OVERRIDE_EN))
3042 cfg->link_fec_opt = tlv.fec_options;
3046 ice_free(hw, pcaps);
3052 * ice_get_link_status - get status of the HW network link
3053 * @pi: port information structure
3054 * @link_up: pointer to bool (true/false = linkup/linkdown)
3056 * Variable link_up is true if link is up, false if link is down.
3057 * The variable link_up is invalid if status is non zero. As a
3058 * result of this call, link status reporting becomes enabled
3060 enum ice_status ice_get_link_status(struct ice_port_info *pi, bool *link_up)
3062 struct ice_phy_info *phy_info;
3063 enum ice_status status = ICE_SUCCESS;
3065 if (!pi || !link_up)
3066 return ICE_ERR_PARAM;
3068 phy_info = &pi->phy;
3070 if (phy_info->get_link_info) {
3071 status = ice_update_link_info(pi);
3074 ice_debug(pi->hw, ICE_DBG_LINK, "get link status error, status = %d\n",
3078 *link_up = phy_info->link_info.link_info & ICE_AQ_LINK_UP;
3084 * ice_aq_set_link_restart_an
3085 * @pi: pointer to the port information structure
3086 * @ena_link: if true: enable link, if false: disable link
3087 * @cd: pointer to command details structure or NULL
3089 * Sets up the link and restarts the Auto-Negotiation over the link.
3092 ice_aq_set_link_restart_an(struct ice_port_info *pi, bool ena_link,
3093 struct ice_sq_cd *cd)
3095 struct ice_aqc_restart_an *cmd;
3096 struct ice_aq_desc desc;
3098 cmd = &desc.params.restart_an;
3100 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_restart_an);
3102 cmd->cmd_flags = ICE_AQC_RESTART_AN_LINK_RESTART;
3103 cmd->lport_num = pi->lport;
3105 cmd->cmd_flags |= ICE_AQC_RESTART_AN_LINK_ENABLE;
3107 cmd->cmd_flags &= ~ICE_AQC_RESTART_AN_LINK_ENABLE;
3109 return ice_aq_send_cmd(pi->hw, &desc, NULL, 0, cd);
3113 * ice_aq_set_event_mask
3114 * @hw: pointer to the HW struct
3115 * @port_num: port number of the physical function
3116 * @mask: event mask to be set
3117 * @cd: pointer to command details structure or NULL
3119 * Set event mask (0x0613)
3122 ice_aq_set_event_mask(struct ice_hw *hw, u8 port_num, u16 mask,
3123 struct ice_sq_cd *cd)
3125 struct ice_aqc_set_event_mask *cmd;
3126 struct ice_aq_desc desc;
3128 cmd = &desc.params.set_event_mask;
3130 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_event_mask);
3132 cmd->lport_num = port_num;
3134 cmd->event_mask = CPU_TO_LE16(mask);
3135 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
3139 * ice_aq_set_mac_loopback
3140 * @hw: pointer to the HW struct
3141 * @ena_lpbk: Enable or Disable loopback
3142 * @cd: pointer to command details structure or NULL
3144 * Enable/disable loopback on a given port
3147 ice_aq_set_mac_loopback(struct ice_hw *hw, bool ena_lpbk, struct ice_sq_cd *cd)
3149 struct ice_aqc_set_mac_lb *cmd;
3150 struct ice_aq_desc desc;
3152 cmd = &desc.params.set_mac_lb;
3154 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_mac_lb);
3156 cmd->lb_mode = ICE_AQ_MAC_LB_EN;
3158 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
3162 * ice_aq_set_port_id_led
3163 * @pi: pointer to the port information
3164 * @is_orig_mode: is this LED set to original mode (by the net-list)
3165 * @cd: pointer to command details structure or NULL
3167 * Set LED value for the given port (0x06e9)
3170 ice_aq_set_port_id_led(struct ice_port_info *pi, bool is_orig_mode,
3171 struct ice_sq_cd *cd)
3173 struct ice_aqc_set_port_id_led *cmd;
3174 struct ice_hw *hw = pi->hw;
3175 struct ice_aq_desc desc;
3177 cmd = &desc.params.set_port_id_led;
3179 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_port_id_led);
3182 cmd->ident_mode = ICE_AQC_PORT_IDENT_LED_ORIG;
3184 cmd->ident_mode = ICE_AQC_PORT_IDENT_LED_BLINK;
3186 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
3191 * @hw: pointer to the HW struct
3192 * @lport: bits [7:0] = logical port, bit [8] = logical port valid
3193 * @bus_addr: I2C bus address of the eeprom (typically 0xA0, 0=topo default)
3194 * @mem_addr: I2C offset. lower 8 bits for address, 8 upper bits zero padding.
3196 * @set_page: set or ignore the page
3197 * @data: pointer to data buffer to be read/written to the I2C device.
3198 * @length: 1-16 for read, 1 for write.
3199 * @write: 0 read, 1 for write.
3200 * @cd: pointer to command details structure or NULL
3202 * Read/Write SFF EEPROM (0x06EE)
3205 ice_aq_sff_eeprom(struct ice_hw *hw, u16 lport, u8 bus_addr,
3206 u16 mem_addr, u8 page, u8 set_page, u8 *data, u8 length,
3207 bool write, struct ice_sq_cd *cd)
3209 struct ice_aqc_sff_eeprom *cmd;
3210 struct ice_aq_desc desc;
3211 enum ice_status status;
3213 if (!data || (mem_addr & 0xff00))
3214 return ICE_ERR_PARAM;
3216 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_sff_eeprom);
3217 cmd = &desc.params.read_write_sff_param;
3218 desc.flags = CPU_TO_LE16(ICE_AQ_FLAG_RD);
3219 cmd->lport_num = (u8)(lport & 0xff);
3220 cmd->lport_num_valid = (u8)((lport >> 8) & 0x01);
3221 cmd->i2c_bus_addr = CPU_TO_LE16(((bus_addr >> 1) &
3222 ICE_AQC_SFF_I2CBUS_7BIT_M) |
3224 ICE_AQC_SFF_SET_EEPROM_PAGE_S) &
3225 ICE_AQC_SFF_SET_EEPROM_PAGE_M));
3226 cmd->i2c_mem_addr = CPU_TO_LE16(mem_addr & 0xff);
3227 cmd->eeprom_page = CPU_TO_LE16((u16)page << ICE_AQC_SFF_EEPROM_PAGE_S);
3229 cmd->i2c_bus_addr |= CPU_TO_LE16(ICE_AQC_SFF_IS_WRITE);
3231 status = ice_aq_send_cmd(hw, &desc, data, length, cd);
3236 * __ice_aq_get_set_rss_lut
3237 * @hw: pointer to the hardware structure
3238 * @params: RSS LUT parameters
3239 * @set: set true to set the table, false to get the table
3241 * Internal function to get (0x0B05) or set (0x0B03) RSS look up table
3243 static enum ice_status
3244 __ice_aq_get_set_rss_lut(struct ice_hw *hw, struct ice_aq_get_set_rss_lut_params *params, bool set)
3246 u16 flags = 0, vsi_id, lut_type, lut_size, glob_lut_idx, vsi_handle;
3247 struct ice_aqc_get_set_rss_lut *cmd_resp;
3248 struct ice_aq_desc desc;
3249 enum ice_status status;
3253 return ICE_ERR_PARAM;
3255 vsi_handle = params->vsi_handle;
3258 if (!ice_is_vsi_valid(hw, vsi_handle) || !lut)
3259 return ICE_ERR_PARAM;
3261 lut_size = params->lut_size;
3262 lut_type = params->lut_type;
3263 glob_lut_idx = params->global_lut_id;
3264 vsi_id = ice_get_hw_vsi_num(hw, vsi_handle);
3266 cmd_resp = &desc.params.get_set_rss_lut;
3269 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_rss_lut);
3270 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
3272 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_rss_lut);
3275 cmd_resp->vsi_id = CPU_TO_LE16(((vsi_id <<
3276 ICE_AQC_GSET_RSS_LUT_VSI_ID_S) &
3277 ICE_AQC_GSET_RSS_LUT_VSI_ID_M) |
3278 ICE_AQC_GSET_RSS_LUT_VSI_VALID);
3281 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_VSI:
3282 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF:
3283 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL:
3284 flags |= ((lut_type << ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S) &
3285 ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_M);
3288 status = ICE_ERR_PARAM;
3289 goto ice_aq_get_set_rss_lut_exit;
3292 if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL) {
3293 flags |= ((glob_lut_idx << ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S) &
3294 ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_M);
3297 goto ice_aq_get_set_rss_lut_send;
3298 } else if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF) {
3300 goto ice_aq_get_set_rss_lut_send;
3302 goto ice_aq_get_set_rss_lut_send;
3305 /* LUT size is only valid for Global and PF table types */
3307 case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128:
3308 flags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128_FLAG <<
3309 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) &
3310 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M;
3312 case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512:
3313 flags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512_FLAG <<
3314 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) &
3315 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M;
3317 case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K:
3318 if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF) {
3319 flags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K_FLAG <<
3320 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) &
3321 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M;
3326 status = ICE_ERR_PARAM;
3327 goto ice_aq_get_set_rss_lut_exit;
3330 ice_aq_get_set_rss_lut_send:
3331 cmd_resp->flags = CPU_TO_LE16(flags);
3332 status = ice_aq_send_cmd(hw, &desc, lut, lut_size, NULL);
3334 ice_aq_get_set_rss_lut_exit:
3339 * ice_aq_get_rss_lut
3340 * @hw: pointer to the hardware structure
3341 * @get_params: RSS LUT parameters used to specify which RSS LUT to get
3343 * get the RSS lookup table, PF or VSI type
3346 ice_aq_get_rss_lut(struct ice_hw *hw, struct ice_aq_get_set_rss_lut_params *get_params)
3348 return __ice_aq_get_set_rss_lut(hw, get_params, false);
3352 * ice_aq_set_rss_lut
3353 * @hw: pointer to the hardware structure
3354 * @set_params: RSS LUT parameters used to specify how to set the RSS LUT
3356 * set the RSS lookup table, PF or VSI type
3359 ice_aq_set_rss_lut(struct ice_hw *hw, struct ice_aq_get_set_rss_lut_params *set_params)
3361 return __ice_aq_get_set_rss_lut(hw, set_params, true);
3365 * __ice_aq_get_set_rss_key
3366 * @hw: pointer to the HW struct
3367 * @vsi_id: VSI FW index
3368 * @key: pointer to key info struct
3369 * @set: set true to set the key, false to get the key
3371 * get (0x0B04) or set (0x0B02) the RSS key per VSI
3374 ice_status __ice_aq_get_set_rss_key(struct ice_hw *hw, u16 vsi_id,
3375 struct ice_aqc_get_set_rss_keys *key,
3378 struct ice_aqc_get_set_rss_key *cmd_resp;
3379 u16 key_size = sizeof(*key);
3380 struct ice_aq_desc desc;
3382 cmd_resp = &desc.params.get_set_rss_key;
3385 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_rss_key);
3386 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
3388 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_rss_key);
3391 cmd_resp->vsi_id = CPU_TO_LE16(((vsi_id <<
3392 ICE_AQC_GSET_RSS_KEY_VSI_ID_S) &
3393 ICE_AQC_GSET_RSS_KEY_VSI_ID_M) |
3394 ICE_AQC_GSET_RSS_KEY_VSI_VALID);
3396 return ice_aq_send_cmd(hw, &desc, key, key_size, NULL);
3400 * ice_aq_get_rss_key
3401 * @hw: pointer to the HW struct
3402 * @vsi_handle: software VSI handle
3403 * @key: pointer to key info struct
3405 * get the RSS key per VSI
3408 ice_aq_get_rss_key(struct ice_hw *hw, u16 vsi_handle,
3409 struct ice_aqc_get_set_rss_keys *key)
3411 if (!ice_is_vsi_valid(hw, vsi_handle) || !key)
3412 return ICE_ERR_PARAM;
3414 return __ice_aq_get_set_rss_key(hw, ice_get_hw_vsi_num(hw, vsi_handle),
3419 * ice_aq_set_rss_key
3420 * @hw: pointer to the HW struct
3421 * @vsi_handle: software VSI handle
3422 * @keys: pointer to key info struct
3424 * set the RSS key per VSI
3427 ice_aq_set_rss_key(struct ice_hw *hw, u16 vsi_handle,
3428 struct ice_aqc_get_set_rss_keys *keys)
3430 if (!ice_is_vsi_valid(hw, vsi_handle) || !keys)
3431 return ICE_ERR_PARAM;
3433 return __ice_aq_get_set_rss_key(hw, ice_get_hw_vsi_num(hw, vsi_handle),
3438 * ice_aq_add_lan_txq
3439 * @hw: pointer to the hardware structure
3440 * @num_qgrps: Number of added queue groups
3441 * @qg_list: list of queue groups to be added
3442 * @buf_size: size of buffer for indirect command
3443 * @cd: pointer to command details structure or NULL
3445 * Add Tx LAN queue (0x0C30)
3448 * Prior to calling add Tx LAN queue:
3449 * Initialize the following as part of the Tx queue context:
3450 * Completion queue ID if the queue uses Completion queue, Quanta profile,
3451 * Cache profile and Packet shaper profile.
3453 * After add Tx LAN queue AQ command is completed:
3454 * Interrupts should be associated with specific queues,
3455 * Association of Tx queue to Doorbell queue is not part of Add LAN Tx queue
3459 ice_aq_add_lan_txq(struct ice_hw *hw, u8 num_qgrps,
3460 struct ice_aqc_add_tx_qgrp *qg_list, u16 buf_size,
3461 struct ice_sq_cd *cd)
3463 struct ice_aqc_add_tx_qgrp *list;
3464 struct ice_aqc_add_txqs *cmd;
3465 struct ice_aq_desc desc;
3466 u16 i, sum_size = 0;
3468 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
3470 cmd = &desc.params.add_txqs;
3472 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_add_txqs);
3475 return ICE_ERR_PARAM;
3477 if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS)
3478 return ICE_ERR_PARAM;
3480 for (i = 0, list = qg_list; i < num_qgrps; i++) {
3481 sum_size += ice_struct_size(list, txqs, list->num_txqs);
3482 list = (struct ice_aqc_add_tx_qgrp *)(list->txqs +
3486 if (buf_size != sum_size)
3487 return ICE_ERR_PARAM;
3489 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
3491 cmd->num_qgrps = num_qgrps;
3493 return ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd);
3497 * ice_aq_dis_lan_txq
3498 * @hw: pointer to the hardware structure
3499 * @num_qgrps: number of groups in the list
3500 * @qg_list: the list of groups to disable
3501 * @buf_size: the total size of the qg_list buffer in bytes
3502 * @rst_src: if called due to reset, specifies the reset source
3503 * @vmvf_num: the relative VM or VF number that is undergoing the reset
3504 * @cd: pointer to command details structure or NULL
3506 * Disable LAN Tx queue (0x0C31)
3508 static enum ice_status
3509 ice_aq_dis_lan_txq(struct ice_hw *hw, u8 num_qgrps,
3510 struct ice_aqc_dis_txq_item *qg_list, u16 buf_size,
3511 enum ice_disq_rst_src rst_src, u16 vmvf_num,
3512 struct ice_sq_cd *cd)
3514 struct ice_aqc_dis_txq_item *item;
3515 struct ice_aqc_dis_txqs *cmd;
3516 struct ice_aq_desc desc;
3517 enum ice_status status;
3520 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
3521 cmd = &desc.params.dis_txqs;
3522 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_dis_txqs);
3524 /* qg_list can be NULL only in VM/VF reset flow */
3525 if (!qg_list && !rst_src)
3526 return ICE_ERR_PARAM;
3528 if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS)
3529 return ICE_ERR_PARAM;
3531 cmd->num_entries = num_qgrps;
3533 cmd->vmvf_and_timeout = CPU_TO_LE16((5 << ICE_AQC_Q_DIS_TIMEOUT_S) &
3534 ICE_AQC_Q_DIS_TIMEOUT_M);
3538 cmd->cmd_type = ICE_AQC_Q_DIS_CMD_VM_RESET;
3539 cmd->vmvf_and_timeout |=
3540 CPU_TO_LE16(vmvf_num & ICE_AQC_Q_DIS_VMVF_NUM_M);
3547 /* flush pipe on time out */
3548 cmd->cmd_type |= ICE_AQC_Q_DIS_CMD_FLUSH_PIPE;
3549 /* If no queue group info, we are in a reset flow. Issue the AQ */
3553 /* set RD bit to indicate that command buffer is provided by the driver
3554 * and it needs to be read by the firmware
3556 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
3558 for (i = 0, item = qg_list; i < num_qgrps; i++) {
3559 u16 item_size = ice_struct_size(item, q_id, item->num_qs);
3561 /* If the num of queues is even, add 2 bytes of padding */
3562 if ((item->num_qs % 2) == 0)
3567 item = (struct ice_aqc_dis_txq_item *)((u8 *)item + item_size);
3571 return ICE_ERR_PARAM;
3574 status = ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd);
3577 ice_debug(hw, ICE_DBG_SCHED, "VM%d disable failed %d\n",
3578 vmvf_num, hw->adminq.sq_last_status);
3580 ice_debug(hw, ICE_DBG_SCHED, "disable queue %d failed %d\n",
3581 LE16_TO_CPU(qg_list[0].q_id[0]),
3582 hw->adminq.sq_last_status);
3588 * ice_aq_move_recfg_lan_txq
3589 * @hw: pointer to the hardware structure
3590 * @num_qs: number of queues to move/reconfigure
3591 * @is_move: true if this operation involves node movement
3592 * @is_tc_change: true if this operation involves a TC change
3593 * @subseq_call: true if this operation is a subsequent call
3594 * @flush_pipe: on timeout, true to flush pipe, false to return EAGAIN
3595 * @timeout: timeout in units of 100 usec (valid values 0-50)
3596 * @blocked_cgds: out param, bitmap of CGDs that timed out if returning EAGAIN
3597 * @buf: struct containing src/dest TEID and per-queue info
3598 * @buf_size: size of buffer for indirect command
3599 * @txqs_moved: out param, number of queues successfully moved
3600 * @cd: pointer to command details structure or NULL
3602 * Move / Reconfigure Tx LAN queues (0x0C32)
3605 ice_aq_move_recfg_lan_txq(struct ice_hw *hw, u8 num_qs, bool is_move,
3606 bool is_tc_change, bool subseq_call, bool flush_pipe,
3607 u8 timeout, u32 *blocked_cgds,
3608 struct ice_aqc_move_txqs_data *buf, u16 buf_size,
3609 u8 *txqs_moved, struct ice_sq_cd *cd)
3611 struct ice_aqc_move_txqs *cmd;
3612 struct ice_aq_desc desc;
3613 enum ice_status status;
3615 cmd = &desc.params.move_txqs;
3616 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_move_recfg_txqs);
3618 #define ICE_LAN_TXQ_MOVE_TIMEOUT_MAX 50
3619 if (timeout > ICE_LAN_TXQ_MOVE_TIMEOUT_MAX)
3620 return ICE_ERR_PARAM;
3622 if (is_tc_change && !flush_pipe && !blocked_cgds)
3623 return ICE_ERR_PARAM;
3625 if (!is_move && !is_tc_change)
3626 return ICE_ERR_PARAM;
3628 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
3631 cmd->cmd_type |= ICE_AQC_Q_CMD_TYPE_MOVE;
3634 cmd->cmd_type |= ICE_AQC_Q_CMD_TYPE_TC_CHANGE;
3637 cmd->cmd_type |= ICE_AQC_Q_CMD_SUBSEQ_CALL;
3640 cmd->cmd_type |= ICE_AQC_Q_CMD_FLUSH_PIPE;
3642 cmd->num_qs = num_qs;
3643 cmd->timeout = ((timeout << ICE_AQC_Q_CMD_TIMEOUT_S) &
3644 ICE_AQC_Q_CMD_TIMEOUT_M);
3646 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);
3648 if (!status && txqs_moved)
3649 *txqs_moved = cmd->num_qs;
3651 if (hw->adminq.sq_last_status == ICE_AQ_RC_EAGAIN &&
3652 is_tc_change && !flush_pipe)
3653 *blocked_cgds = LE32_TO_CPU(cmd->blocked_cgds);
3658 /* End of FW Admin Queue command wrappers */
3661 * ice_write_byte - write a byte to a packed context structure
3662 * @src_ctx: the context structure to read from
3663 * @dest_ctx: the context to be written to
3664 * @ce_info: a description of the struct to be filled
3667 ice_write_byte(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)
3669 u8 src_byte, dest_byte, mask;
3673 /* copy from the next struct field */
3674 from = src_ctx + ce_info->offset;
3676 /* prepare the bits and mask */
3677 shift_width = ce_info->lsb % 8;
3678 mask = (u8)(BIT(ce_info->width) - 1);
3683 /* shift to correct alignment */
3684 mask <<= shift_width;
3685 src_byte <<= shift_width;
3687 /* get the current bits from the target bit string */
3688 dest = dest_ctx + (ce_info->lsb / 8);
3690 ice_memcpy(&dest_byte, dest, sizeof(dest_byte), ICE_DMA_TO_NONDMA);
3692 dest_byte &= ~mask; /* get the bits not changing */
3693 dest_byte |= src_byte; /* add in the new bits */
3695 /* put it all back */
3696 ice_memcpy(dest, &dest_byte, sizeof(dest_byte), ICE_NONDMA_TO_DMA);
3700 * ice_write_word - write a word to a packed context structure
3701 * @src_ctx: the context structure to read from
3702 * @dest_ctx: the context to be written to
3703 * @ce_info: a description of the struct to be filled
3706 ice_write_word(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)
3713 /* copy from the next struct field */
3714 from = src_ctx + ce_info->offset;
3716 /* prepare the bits and mask */
3717 shift_width = ce_info->lsb % 8;
3718 mask = BIT(ce_info->width) - 1;
3720 /* don't swizzle the bits until after the mask because the mask bits
3721 * will be in a different bit position on big endian machines
3723 src_word = *(u16 *)from;
3726 /* shift to correct alignment */
3727 mask <<= shift_width;
3728 src_word <<= shift_width;
3730 /* get the current bits from the target bit string */
3731 dest = dest_ctx + (ce_info->lsb / 8);
3733 ice_memcpy(&dest_word, dest, sizeof(dest_word), ICE_DMA_TO_NONDMA);
3735 dest_word &= ~(CPU_TO_LE16(mask)); /* get the bits not changing */
3736 dest_word |= CPU_TO_LE16(src_word); /* add in the new bits */
3738 /* put it all back */
3739 ice_memcpy(dest, &dest_word, sizeof(dest_word), ICE_NONDMA_TO_DMA);
3743 * ice_write_dword - write a dword to a packed context structure
3744 * @src_ctx: the context structure to read from
3745 * @dest_ctx: the context to be written to
3746 * @ce_info: a description of the struct to be filled
3749 ice_write_dword(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)
3751 u32 src_dword, mask;
3756 /* copy from the next struct field */
3757 from = src_ctx + ce_info->offset;
3759 /* prepare the bits and mask */
3760 shift_width = ce_info->lsb % 8;
3762 /* if the field width is exactly 32 on an x86 machine, then the shift
3763 * operation will not work because the SHL instructions count is masked
3764 * to 5 bits so the shift will do nothing
3766 if (ce_info->width < 32)
3767 mask = BIT(ce_info->width) - 1;
3771 /* don't swizzle the bits until after the mask because the mask bits
3772 * will be in a different bit position on big endian machines
3774 src_dword = *(u32 *)from;
3777 /* shift to correct alignment */
3778 mask <<= shift_width;
3779 src_dword <<= shift_width;
3781 /* get the current bits from the target bit string */
3782 dest = dest_ctx + (ce_info->lsb / 8);
3784 ice_memcpy(&dest_dword, dest, sizeof(dest_dword), ICE_DMA_TO_NONDMA);
3786 dest_dword &= ~(CPU_TO_LE32(mask)); /* get the bits not changing */
3787 dest_dword |= CPU_TO_LE32(src_dword); /* add in the new bits */
3789 /* put it all back */
3790 ice_memcpy(dest, &dest_dword, sizeof(dest_dword), ICE_NONDMA_TO_DMA);
3794 * ice_write_qword - write a qword to a packed context structure
3795 * @src_ctx: the context structure to read from
3796 * @dest_ctx: the context to be written to
3797 * @ce_info: a description of the struct to be filled
3800 ice_write_qword(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)
3802 u64 src_qword, mask;
3807 /* copy from the next struct field */
3808 from = src_ctx + ce_info->offset;
3810 /* prepare the bits and mask */
3811 shift_width = ce_info->lsb % 8;
3813 /* if the field width is exactly 64 on an x86 machine, then the shift
3814 * operation will not work because the SHL instructions count is masked
3815 * to 6 bits so the shift will do nothing
3817 if (ce_info->width < 64)
3818 mask = BIT_ULL(ce_info->width) - 1;
3822 /* don't swizzle the bits until after the mask because the mask bits
3823 * will be in a different bit position on big endian machines
3825 src_qword = *(u64 *)from;
3828 /* shift to correct alignment */
3829 mask <<= shift_width;
3830 src_qword <<= shift_width;
3832 /* get the current bits from the target bit string */
3833 dest = dest_ctx + (ce_info->lsb / 8);
3835 ice_memcpy(&dest_qword, dest, sizeof(dest_qword), ICE_DMA_TO_NONDMA);
3837 dest_qword &= ~(CPU_TO_LE64(mask)); /* get the bits not changing */
3838 dest_qword |= CPU_TO_LE64(src_qword); /* add in the new bits */
3840 /* put it all back */
3841 ice_memcpy(dest, &dest_qword, sizeof(dest_qword), ICE_NONDMA_TO_DMA);
3845 * ice_set_ctx - set context bits in packed structure
3846 * @hw: pointer to the hardware structure
3847 * @src_ctx: pointer to a generic non-packed context structure
3848 * @dest_ctx: pointer to memory for the packed structure
3849 * @ce_info: a description of the structure to be transformed
3852 ice_set_ctx(struct ice_hw *hw, u8 *src_ctx, u8 *dest_ctx,
3853 const struct ice_ctx_ele *ce_info)
3857 for (f = 0; ce_info[f].width; f++) {
3858 /* We have to deal with each element of the FW response
3859 * using the correct size so that we are correct regardless
3860 * of the endianness of the machine.
3862 if (ce_info[f].width > (ce_info[f].size_of * BITS_PER_BYTE)) {
3863 ice_debug(hw, ICE_DBG_QCTX, "Field %d width of %d bits larger than size of %d byte(s) ... skipping write\n",
3864 f, ce_info[f].width, ce_info[f].size_of);
3867 switch (ce_info[f].size_of) {
3869 ice_write_byte(src_ctx, dest_ctx, &ce_info[f]);
3872 ice_write_word(src_ctx, dest_ctx, &ce_info[f]);
3875 ice_write_dword(src_ctx, dest_ctx, &ce_info[f]);
3878 ice_write_qword(src_ctx, dest_ctx, &ce_info[f]);
3881 return ICE_ERR_INVAL_SIZE;
3889 * ice_read_byte - read context byte into struct
3890 * @src_ctx: the context structure to read from
3891 * @dest_ctx: the context to be written to
3892 * @ce_info: a description of the struct to be filled
3895 ice_read_byte(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info)
3901 /* prepare the bits and mask */
3902 shift_width = ce_info->lsb % 8;
3903 mask = (u8)(BIT(ce_info->width) - 1);
3905 /* shift to correct alignment */
3906 mask <<= shift_width;
3908 /* get the current bits from the src bit string */
3909 src = src_ctx + (ce_info->lsb / 8);
3911 ice_memcpy(&dest_byte, src, sizeof(dest_byte), ICE_DMA_TO_NONDMA);
3913 dest_byte &= ~(mask);
3915 dest_byte >>= shift_width;
3917 /* get the address from the struct field */
3918 target = dest_ctx + ce_info->offset;
3920 /* put it back in the struct */
3921 ice_memcpy(target, &dest_byte, sizeof(dest_byte), ICE_NONDMA_TO_DMA);
3925 * ice_read_word - read context word into struct
3926 * @src_ctx: the context structure to read from
3927 * @dest_ctx: the context to be written to
3928 * @ce_info: a description of the struct to be filled
3931 ice_read_word(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info)
3933 u16 dest_word, mask;
3938 /* prepare the bits and mask */
3939 shift_width = ce_info->lsb % 8;
3940 mask = BIT(ce_info->width) - 1;
3942 /* shift to correct alignment */
3943 mask <<= shift_width;
3945 /* get the current bits from the src bit string */
3946 src = src_ctx + (ce_info->lsb / 8);
3948 ice_memcpy(&src_word, src, sizeof(src_word), ICE_DMA_TO_NONDMA);
3950 /* the data in the memory is stored as little endian so mask it
3953 src_word &= ~(CPU_TO_LE16(mask));
3955 /* get the data back into host order before shifting */
3956 dest_word = LE16_TO_CPU(src_word);
3958 dest_word >>= shift_width;
3960 /* get the address from the struct field */
3961 target = dest_ctx + ce_info->offset;
3963 /* put it back in the struct */
3964 ice_memcpy(target, &dest_word, sizeof(dest_word), ICE_NONDMA_TO_DMA);
3968 * ice_read_dword - read context dword into struct
3969 * @src_ctx: the context structure to read from
3970 * @dest_ctx: the context to be written to
3971 * @ce_info: a description of the struct to be filled
3974 ice_read_dword(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info)
3976 u32 dest_dword, mask;
3981 /* prepare the bits and mask */
3982 shift_width = ce_info->lsb % 8;
3984 /* if the field width is exactly 32 on an x86 machine, then the shift
3985 * operation will not work because the SHL instructions count is masked
3986 * to 5 bits so the shift will do nothing
3988 if (ce_info->width < 32)
3989 mask = BIT(ce_info->width) - 1;
3993 /* shift to correct alignment */
3994 mask <<= shift_width;
3996 /* get the current bits from the src bit string */
3997 src = src_ctx + (ce_info->lsb / 8);
3999 ice_memcpy(&src_dword, src, sizeof(src_dword), ICE_DMA_TO_NONDMA);
4001 /* the data in the memory is stored as little endian so mask it
4004 src_dword &= ~(CPU_TO_LE32(mask));
4006 /* get the data back into host order before shifting */
4007 dest_dword = LE32_TO_CPU(src_dword);
4009 dest_dword >>= shift_width;
4011 /* get the address from the struct field */
4012 target = dest_ctx + ce_info->offset;
4014 /* put it back in the struct */
4015 ice_memcpy(target, &dest_dword, sizeof(dest_dword), ICE_NONDMA_TO_DMA);
4019 * ice_read_qword - read context qword into struct
4020 * @src_ctx: the context structure to read from
4021 * @dest_ctx: the context to be written to
4022 * @ce_info: a description of the struct to be filled
4025 ice_read_qword(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info)
4027 u64 dest_qword, mask;
4032 /* prepare the bits and mask */
4033 shift_width = ce_info->lsb % 8;
4035 /* if the field width is exactly 64 on an x86 machine, then the shift
4036 * operation will not work because the SHL instructions count is masked
4037 * to 6 bits so the shift will do nothing
4039 if (ce_info->width < 64)
4040 mask = BIT_ULL(ce_info->width) - 1;
4044 /* shift to correct alignment */
4045 mask <<= shift_width;
4047 /* get the current bits from the src bit string */
4048 src = src_ctx + (ce_info->lsb / 8);
4050 ice_memcpy(&src_qword, src, sizeof(src_qword), ICE_DMA_TO_NONDMA);
4052 /* the data in the memory is stored as little endian so mask it
4055 src_qword &= ~(CPU_TO_LE64(mask));
4057 /* get the data back into host order before shifting */
4058 dest_qword = LE64_TO_CPU(src_qword);
4060 dest_qword >>= shift_width;
4062 /* get the address from the struct field */
4063 target = dest_ctx + ce_info->offset;
4065 /* put it back in the struct */
4066 ice_memcpy(target, &dest_qword, sizeof(dest_qword), ICE_NONDMA_TO_DMA);
4070 * ice_get_ctx - extract context bits from a packed structure
4071 * @src_ctx: pointer to a generic packed context structure
4072 * @dest_ctx: pointer to a generic non-packed context structure
4073 * @ce_info: a description of the structure to be read from
4076 ice_get_ctx(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info)
4080 for (f = 0; ce_info[f].width; f++) {
4081 switch (ce_info[f].size_of) {
4083 ice_read_byte(src_ctx, dest_ctx, &ce_info[f]);
4086 ice_read_word(src_ctx, dest_ctx, &ce_info[f]);
4089 ice_read_dword(src_ctx, dest_ctx, &ce_info[f]);
4092 ice_read_qword(src_ctx, dest_ctx, &ce_info[f]);
4095 /* nothing to do, just keep going */
4104 * ice_get_lan_q_ctx - get the LAN queue context for the given VSI and TC
4105 * @hw: pointer to the HW struct
4106 * @vsi_handle: software VSI handle
4108 * @q_handle: software queue handle
4111 ice_get_lan_q_ctx(struct ice_hw *hw, u16 vsi_handle, u8 tc, u16 q_handle)
4113 struct ice_vsi_ctx *vsi;
4114 struct ice_q_ctx *q_ctx;
4116 vsi = ice_get_vsi_ctx(hw, vsi_handle);
4119 if (q_handle >= vsi->num_lan_q_entries[tc])
4121 if (!vsi->lan_q_ctx[tc])
4123 q_ctx = vsi->lan_q_ctx[tc];
4124 return &q_ctx[q_handle];
4129 * @pi: port information structure
4130 * @vsi_handle: software VSI handle
4132 * @q_handle: software queue handle
4133 * @num_qgrps: Number of added queue groups
4134 * @buf: list of queue groups to be added
4135 * @buf_size: size of buffer for indirect command
4136 * @cd: pointer to command details structure or NULL
4138 * This function adds one LAN queue
4141 ice_ena_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u16 q_handle,
4142 u8 num_qgrps, struct ice_aqc_add_tx_qgrp *buf, u16 buf_size,
4143 struct ice_sq_cd *cd)
4145 struct ice_aqc_txsched_elem_data node = { 0 };
4146 struct ice_sched_node *parent;
4147 struct ice_q_ctx *q_ctx;
4148 enum ice_status status;
4151 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY)
4154 if (num_qgrps > 1 || buf->num_txqs > 1)
4155 return ICE_ERR_MAX_LIMIT;
4159 if (!ice_is_vsi_valid(hw, vsi_handle))
4160 return ICE_ERR_PARAM;
4162 ice_acquire_lock(&pi->sched_lock);
4164 q_ctx = ice_get_lan_q_ctx(hw, vsi_handle, tc, q_handle);
4166 ice_debug(hw, ICE_DBG_SCHED, "Enaq: invalid queue handle %d\n",
4168 status = ICE_ERR_PARAM;
4172 /* find a parent node */
4173 parent = ice_sched_get_free_qparent(pi, vsi_handle, tc,
4174 ICE_SCHED_NODE_OWNER_LAN);
4176 status = ICE_ERR_PARAM;
4180 buf->parent_teid = parent->info.node_teid;
4181 node.parent_teid = parent->info.node_teid;
4182 /* Mark that the values in the "generic" section as valid. The default
4183 * value in the "generic" section is zero. This means that :
4184 * - Scheduling mode is Bytes Per Second (BPS), indicated by Bit 0.
4185 * - 0 priority among siblings, indicated by Bit 1-3.
4186 * - WFQ, indicated by Bit 4.
4187 * - 0 Adjustment value is used in PSM credit update flow, indicated by
4189 * - Bit 7 is reserved.
4190 * Without setting the generic section as valid in valid_sections, the
4191 * Admin queue command will fail with error code ICE_AQ_RC_EINVAL.
4193 buf->txqs[0].info.valid_sections =
4194 ICE_AQC_ELEM_VALID_GENERIC | ICE_AQC_ELEM_VALID_CIR |
4195 ICE_AQC_ELEM_VALID_EIR;
4196 buf->txqs[0].info.generic = 0;
4197 buf->txqs[0].info.cir_bw.bw_profile_idx =
4198 CPU_TO_LE16(ICE_SCHED_DFLT_RL_PROF_ID);
4199 buf->txqs[0].info.cir_bw.bw_alloc =
4200 CPU_TO_LE16(ICE_SCHED_DFLT_BW_WT);
4201 buf->txqs[0].info.eir_bw.bw_profile_idx =
4202 CPU_TO_LE16(ICE_SCHED_DFLT_RL_PROF_ID);
4203 buf->txqs[0].info.eir_bw.bw_alloc =
4204 CPU_TO_LE16(ICE_SCHED_DFLT_BW_WT);
4206 /* add the LAN queue */
4207 status = ice_aq_add_lan_txq(hw, num_qgrps, buf, buf_size, cd);
4208 if (status != ICE_SUCCESS) {
4209 ice_debug(hw, ICE_DBG_SCHED, "enable queue %d failed %d\n",
4210 LE16_TO_CPU(buf->txqs[0].txq_id),
4211 hw->adminq.sq_last_status);
4215 node.node_teid = buf->txqs[0].q_teid;
4216 node.data.elem_type = ICE_AQC_ELEM_TYPE_LEAF;
4217 q_ctx->q_handle = q_handle;
4218 q_ctx->q_teid = LE32_TO_CPU(node.node_teid);
4220 /* add a leaf node into scheduler tree queue layer */
4221 status = ice_sched_add_node(pi, hw->num_tx_sched_layers - 1, &node);
4223 status = ice_sched_replay_q_bw(pi, q_ctx);
4226 ice_release_lock(&pi->sched_lock);
4232 * @pi: port information structure
4233 * @vsi_handle: software VSI handle
4235 * @num_queues: number of queues
4236 * @q_handles: pointer to software queue handle array
4237 * @q_ids: pointer to the q_id array
4238 * @q_teids: pointer to queue node teids
4239 * @rst_src: if called due to reset, specifies the reset source
4240 * @vmvf_num: the relative VM or VF number that is undergoing the reset
4241 * @cd: pointer to command details structure or NULL
4243 * This function removes queues and their corresponding nodes in SW DB
4246 ice_dis_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u8 num_queues,
4247 u16 *q_handles, u16 *q_ids, u32 *q_teids,
4248 enum ice_disq_rst_src rst_src, u16 vmvf_num,
4249 struct ice_sq_cd *cd)
4251 enum ice_status status = ICE_ERR_DOES_NOT_EXIST;
4252 struct ice_aqc_dis_txq_item *qg_list;
4253 struct ice_q_ctx *q_ctx;
4257 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY)
4263 /* if queue is disabled already yet the disable queue command
4264 * has to be sent to complete the VF reset, then call
4265 * ice_aq_dis_lan_txq without any queue information
4268 return ice_aq_dis_lan_txq(hw, 0, NULL, 0, rst_src,
4273 buf_size = ice_struct_size(qg_list, q_id, 1);
4274 qg_list = (struct ice_aqc_dis_txq_item *)ice_malloc(hw, buf_size);
4276 return ICE_ERR_NO_MEMORY;
4278 ice_acquire_lock(&pi->sched_lock);
4280 for (i = 0; i < num_queues; i++) {
4281 struct ice_sched_node *node;
4283 node = ice_sched_find_node_by_teid(pi->root, q_teids[i]);
4286 q_ctx = ice_get_lan_q_ctx(hw, vsi_handle, tc, q_handles[i]);
4288 ice_debug(hw, ICE_DBG_SCHED, "invalid queue handle%d\n",
4292 if (q_ctx->q_handle != q_handles[i]) {
4293 ice_debug(hw, ICE_DBG_SCHED, "Err:handles %d %d\n",
4294 q_ctx->q_handle, q_handles[i]);
4297 qg_list->parent_teid = node->info.parent_teid;
4298 qg_list->num_qs = 1;
4299 qg_list->q_id[0] = CPU_TO_LE16(q_ids[i]);
4300 status = ice_aq_dis_lan_txq(hw, 1, qg_list, buf_size, rst_src,
4303 if (status != ICE_SUCCESS)
4305 ice_free_sched_node(pi, node);
4306 q_ctx->q_handle = ICE_INVAL_Q_HANDLE;
4308 ice_release_lock(&pi->sched_lock);
4309 ice_free(hw, qg_list);
4314 * ice_cfg_vsi_qs - configure the new/existing VSI queues
4315 * @pi: port information structure
4316 * @vsi_handle: software VSI handle
4317 * @tc_bitmap: TC bitmap
4318 * @maxqs: max queues array per TC
4319 * @owner: LAN or RDMA
4321 * This function adds/updates the VSI queues per TC.
4323 static enum ice_status
4324 ice_cfg_vsi_qs(struct ice_port_info *pi, u16 vsi_handle, u16 tc_bitmap,
4325 u16 *maxqs, u8 owner)
4327 enum ice_status status = ICE_SUCCESS;
4330 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY)
4333 if (!ice_is_vsi_valid(pi->hw, vsi_handle))
4334 return ICE_ERR_PARAM;
4336 ice_acquire_lock(&pi->sched_lock);
4338 ice_for_each_traffic_class(i) {
4339 /* configuration is possible only if TC node is present */
4340 if (!ice_sched_get_tc_node(pi, i))
4343 status = ice_sched_cfg_vsi(pi, vsi_handle, i, maxqs[i], owner,
4344 ice_is_tc_ena(tc_bitmap, i));
4349 ice_release_lock(&pi->sched_lock);
4354 * ice_cfg_vsi_lan - configure VSI LAN queues
4355 * @pi: port information structure
4356 * @vsi_handle: software VSI handle
4357 * @tc_bitmap: TC bitmap
4358 * @max_lanqs: max LAN queues array per TC
4360 * This function adds/updates the VSI LAN queues per TC.
4363 ice_cfg_vsi_lan(struct ice_port_info *pi, u16 vsi_handle, u16 tc_bitmap,
4366 return ice_cfg_vsi_qs(pi, vsi_handle, tc_bitmap, max_lanqs,
4367 ICE_SCHED_NODE_OWNER_LAN);
4371 * ice_is_main_vsi - checks whether the VSI is main VSI
4372 * @hw: pointer to the HW struct
4373 * @vsi_handle: VSI handle
4375 * Checks whether the VSI is the main VSI (the first PF VSI created on
4378 static bool ice_is_main_vsi(struct ice_hw *hw, u16 vsi_handle)
4380 return vsi_handle == ICE_MAIN_VSI_HANDLE && hw->vsi_ctx[vsi_handle];
4384 * ice_replay_pre_init - replay pre initialization
4385 * @hw: pointer to the HW struct
4386 * @sw: pointer to switch info struct for which function initializes filters
4388 * Initializes required config data for VSI, FD, ACL, and RSS before replay.
4390 static enum ice_status
4391 ice_replay_pre_init(struct ice_hw *hw, struct ice_switch_info *sw)
4393 enum ice_status status;
4396 /* Delete old entries from replay filter list head if there is any */
4397 ice_rm_sw_replay_rule_info(hw, sw);
4398 /* In start of replay, move entries into replay_rules list, it
4399 * will allow adding rules entries back to filt_rules list,
4400 * which is operational list.
4402 for (i = 0; i < ICE_MAX_NUM_RECIPES; i++)
4403 LIST_REPLACE_INIT(&sw->recp_list[i].filt_rules,
4404 &sw->recp_list[i].filt_replay_rules);
4405 ice_sched_replay_agg_vsi_preinit(hw);
4407 status = ice_sched_replay_root_node_bw(hw->port_info);
4411 return ice_sched_replay_tc_node_bw(hw->port_info);
4415 * ice_replay_vsi - replay VSI configuration
4416 * @hw: pointer to the HW struct
4417 * @vsi_handle: driver VSI handle
4419 * Restore all VSI configuration after reset. It is required to call this
4420 * function with main VSI first.
4422 enum ice_status ice_replay_vsi(struct ice_hw *hw, u16 vsi_handle)
4424 struct ice_switch_info *sw = hw->switch_info;
4425 struct ice_port_info *pi = hw->port_info;
4426 enum ice_status status;
4428 if (!ice_is_vsi_valid(hw, vsi_handle))
4429 return ICE_ERR_PARAM;
4431 /* Replay pre-initialization if there is any */
4432 if (ice_is_main_vsi(hw, vsi_handle)) {
4433 status = ice_replay_pre_init(hw, sw);
4437 /* Replay per VSI all RSS configurations */
4438 status = ice_replay_rss_cfg(hw, vsi_handle);
4441 /* Replay per VSI all filters */
4442 status = ice_replay_vsi_all_fltr(hw, pi, vsi_handle);
4444 status = ice_replay_vsi_agg(hw, vsi_handle);
4449 * ice_replay_post - post replay configuration cleanup
4450 * @hw: pointer to the HW struct
4452 * Post replay cleanup.
4454 void ice_replay_post(struct ice_hw *hw)
4456 /* Delete old entries from replay filter list head */
4457 ice_rm_all_sw_replay_rule_info(hw);
4458 ice_sched_replay_agg(hw);
4462 * ice_stat_update40 - read 40 bit stat from the chip and update stat values
4463 * @hw: ptr to the hardware info
4464 * @reg: offset of 64 bit HW register to read from
4465 * @prev_stat_loaded: bool to specify if previous stats are loaded
4466 * @prev_stat: ptr to previous loaded stat value
4467 * @cur_stat: ptr to current stat value
4470 ice_stat_update40(struct ice_hw *hw, u32 reg, bool prev_stat_loaded,
4471 u64 *prev_stat, u64 *cur_stat)
4473 u64 new_data = rd64(hw, reg) & (BIT_ULL(40) - 1);
4475 /* device stats are not reset at PFR, they likely will not be zeroed
4476 * when the driver starts. Thus, save the value from the first read
4477 * without adding to the statistic value so that we report stats which
4478 * count up from zero.
4480 if (!prev_stat_loaded) {
4481 *prev_stat = new_data;
4485 /* Calculate the difference between the new and old values, and then
4486 * add it to the software stat value.
4488 if (new_data >= *prev_stat)
4489 *cur_stat += new_data - *prev_stat;
4491 /* to manage the potential roll-over */
4492 *cur_stat += (new_data + BIT_ULL(40)) - *prev_stat;
4494 /* Update the previously stored value to prepare for next read */
4495 *prev_stat = new_data;
4499 * ice_stat_update32 - read 32 bit stat from the chip and update stat values
4500 * @hw: ptr to the hardware info
4501 * @reg: offset of HW register to read from
4502 * @prev_stat_loaded: bool to specify if previous stats are loaded
4503 * @prev_stat: ptr to previous loaded stat value
4504 * @cur_stat: ptr to current stat value
4507 ice_stat_update32(struct ice_hw *hw, u32 reg, bool prev_stat_loaded,
4508 u64 *prev_stat, u64 *cur_stat)
4512 new_data = rd32(hw, reg);
4514 /* device stats are not reset at PFR, they likely will not be zeroed
4515 * when the driver starts. Thus, save the value from the first read
4516 * without adding to the statistic value so that we report stats which
4517 * count up from zero.
4519 if (!prev_stat_loaded) {
4520 *prev_stat = new_data;
4524 /* Calculate the difference between the new and old values, and then
4525 * add it to the software stat value.
4527 if (new_data >= *prev_stat)
4528 *cur_stat += new_data - *prev_stat;
4530 /* to manage the potential roll-over */
4531 *cur_stat += (new_data + BIT_ULL(32)) - *prev_stat;
4533 /* Update the previously stored value to prepare for next read */
4534 *prev_stat = new_data;
4538 * ice_stat_update_repc - read GLV_REPC stats from chip and update stat values
4539 * @hw: ptr to the hardware info
4540 * @vsi_handle: VSI handle
4541 * @prev_stat_loaded: bool to specify if the previous stat values are loaded
4542 * @cur_stats: ptr to current stats structure
4544 * The GLV_REPC statistic register actually tracks two 16bit statistics, and
4545 * thus cannot be read using the normal ice_stat_update32 function.
4547 * Read the GLV_REPC register associated with the given VSI, and update the
4548 * rx_no_desc and rx_error values in the ice_eth_stats structure.
4550 * Because the statistics in GLV_REPC stick at 0xFFFF, the register must be
4551 * cleared each time it's read.
4553 * Note that the GLV_RDPC register also counts the causes that would trigger
4554 * GLV_REPC. However, it does not give the finer grained detail about why the
4555 * packets are being dropped. The GLV_REPC values can be used to distinguish
4556 * whether Rx packets are dropped due to errors or due to no available
4560 ice_stat_update_repc(struct ice_hw *hw, u16 vsi_handle, bool prev_stat_loaded,
4561 struct ice_eth_stats *cur_stats)
4563 u16 vsi_num, no_desc, error_cnt;
4566 if (!ice_is_vsi_valid(hw, vsi_handle))
4569 vsi_num = ice_get_hw_vsi_num(hw, vsi_handle);
4571 /* If we haven't loaded stats yet, just clear the current value */
4572 if (!prev_stat_loaded) {
4573 wr32(hw, GLV_REPC(vsi_num), 0);
4577 repc = rd32(hw, GLV_REPC(vsi_num));
4578 no_desc = (repc & GLV_REPC_NO_DESC_CNT_M) >> GLV_REPC_NO_DESC_CNT_S;
4579 error_cnt = (repc & GLV_REPC_ERROR_CNT_M) >> GLV_REPC_ERROR_CNT_S;
4581 /* Clear the count by writing to the stats register */
4582 wr32(hw, GLV_REPC(vsi_num), 0);
4584 cur_stats->rx_no_desc += no_desc;
4585 cur_stats->rx_errors += error_cnt;
4589 * ice_sched_query_elem - query element information from HW
4590 * @hw: pointer to the HW struct
4591 * @node_teid: node TEID to be queried
4592 * @buf: buffer to element information
4594 * This function queries HW element information
4597 ice_sched_query_elem(struct ice_hw *hw, u32 node_teid,
4598 struct ice_aqc_txsched_elem_data *buf)
4600 u16 buf_size, num_elem_ret = 0;
4601 enum ice_status status;
4603 buf_size = sizeof(*buf);
4604 ice_memset(buf, 0, buf_size, ICE_NONDMA_MEM);
4605 buf->node_teid = CPU_TO_LE32(node_teid);
4606 status = ice_aq_query_sched_elems(hw, 1, buf, buf_size, &num_elem_ret,
4608 if (status != ICE_SUCCESS || num_elem_ret != 1)
4609 ice_debug(hw, ICE_DBG_SCHED, "query element failed\n");
4614 * ice_get_fw_mode - returns FW mode
4615 * @hw: pointer to the HW struct
4617 enum ice_fw_modes ice_get_fw_mode(struct ice_hw *hw)
4619 #define ICE_FW_MODE_DBG_M BIT(0)
4620 #define ICE_FW_MODE_REC_M BIT(1)
4621 #define ICE_FW_MODE_ROLLBACK_M BIT(2)
4624 /* check the current FW mode */
4625 fw_mode = rd32(hw, GL_MNG_FWSM) & GL_MNG_FWSM_FW_MODES_M;
4627 if (fw_mode & ICE_FW_MODE_DBG_M)
4628 return ICE_FW_MODE_DBG;
4629 else if (fw_mode & ICE_FW_MODE_REC_M)
4630 return ICE_FW_MODE_REC;
4631 else if (fw_mode & ICE_FW_MODE_ROLLBACK_M)
4632 return ICE_FW_MODE_ROLLBACK;
4634 return ICE_FW_MODE_NORMAL;
4638 * ice_fw_supports_link_override
4639 * @hw: pointer to the hardware structure
4641 * Checks if the firmware supports link override
4643 bool ice_fw_supports_link_override(struct ice_hw *hw)
4645 if (hw->api_maj_ver == ICE_FW_API_LINK_OVERRIDE_MAJ) {
4646 if (hw->api_min_ver > ICE_FW_API_LINK_OVERRIDE_MIN)
4648 if (hw->api_min_ver == ICE_FW_API_LINK_OVERRIDE_MIN &&
4649 hw->api_patch >= ICE_FW_API_LINK_OVERRIDE_PATCH)
4651 } else if (hw->api_maj_ver > ICE_FW_API_LINK_OVERRIDE_MAJ) {
4659 * ice_get_link_default_override
4660 * @ldo: pointer to the link default override struct
4661 * @pi: pointer to the port info struct
4663 * Gets the link default override for a port
4666 ice_get_link_default_override(struct ice_link_default_override_tlv *ldo,
4667 struct ice_port_info *pi)
4669 u16 i, tlv, tlv_len, tlv_start, buf, offset;
4670 struct ice_hw *hw = pi->hw;
4671 enum ice_status status;
4673 status = ice_get_pfa_module_tlv(hw, &tlv, &tlv_len,
4674 ICE_SR_LINK_DEFAULT_OVERRIDE_PTR);
4676 ice_debug(hw, ICE_DBG_INIT, "Failed to read link override TLV.\n");
4680 /* Each port has its own config; calculate for our port */
4681 tlv_start = tlv + pi->lport * ICE_SR_PFA_LINK_OVERRIDE_WORDS +
4682 ICE_SR_PFA_LINK_OVERRIDE_OFFSET;
4684 /* link options first */
4685 status = ice_read_sr_word(hw, tlv_start, &buf);
4687 ice_debug(hw, ICE_DBG_INIT, "Failed to read override link options.\n");
4690 ldo->options = buf & ICE_LINK_OVERRIDE_OPT_M;
4691 ldo->phy_config = (buf & ICE_LINK_OVERRIDE_PHY_CFG_M) >>
4692 ICE_LINK_OVERRIDE_PHY_CFG_S;
4694 /* link PHY config */
4695 offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_FEC_OFFSET;
4696 status = ice_read_sr_word(hw, offset, &buf);
4698 ice_debug(hw, ICE_DBG_INIT, "Failed to read override phy config.\n");
4701 ldo->fec_options = buf & ICE_LINK_OVERRIDE_FEC_OPT_M;
4704 offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_PHY_OFFSET;
4705 for (i = 0; i < ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS; i++) {
4706 status = ice_read_sr_word(hw, (offset + i), &buf);
4708 ice_debug(hw, ICE_DBG_INIT, "Failed to read override link options.\n");
4711 /* shift 16 bits at a time to fill 64 bits */
4712 ldo->phy_type_low |= ((u64)buf << (i * 16));
4715 /* PHY types high */
4716 offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_PHY_OFFSET +
4717 ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS;
4718 for (i = 0; i < ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS; i++) {
4719 status = ice_read_sr_word(hw, (offset + i), &buf);
4721 ice_debug(hw, ICE_DBG_INIT, "Failed to read override link options.\n");
4724 /* shift 16 bits at a time to fill 64 bits */
4725 ldo->phy_type_high |= ((u64)buf << (i * 16));
4732 * ice_is_phy_caps_an_enabled - check if PHY capabilities autoneg is enabled
4733 * @caps: get PHY capability data
4735 bool ice_is_phy_caps_an_enabled(struct ice_aqc_get_phy_caps_data *caps)
4737 if (caps->caps & ICE_AQC_PHY_AN_MODE ||
4738 caps->low_power_ctrl_an & (ICE_AQC_PHY_AN_EN_CLAUSE28 |
4739 ICE_AQC_PHY_AN_EN_CLAUSE73 |
4740 ICE_AQC_PHY_AN_EN_CLAUSE37))
4747 * ice_aq_set_lldp_mib - Set the LLDP MIB
4748 * @hw: pointer to the HW struct
4749 * @mib_type: Local, Remote or both Local and Remote MIBs
4750 * @buf: pointer to the caller-supplied buffer to store the MIB block
4751 * @buf_size: size of the buffer (in bytes)
4752 * @cd: pointer to command details structure or NULL
4754 * Set the LLDP MIB. (0x0A08)
4757 ice_aq_set_lldp_mib(struct ice_hw *hw, u8 mib_type, void *buf, u16 buf_size,
4758 struct ice_sq_cd *cd)
4760 struct ice_aqc_lldp_set_local_mib *cmd;
4761 struct ice_aq_desc desc;
4763 cmd = &desc.params.lldp_set_mib;
4765 if (buf_size == 0 || !buf)
4766 return ICE_ERR_PARAM;
4768 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_lldp_set_local_mib);
4770 desc.flags |= CPU_TO_LE16((u16)ICE_AQ_FLAG_RD);
4771 desc.datalen = CPU_TO_LE16(buf_size);
4773 cmd->type = mib_type;
4774 cmd->length = CPU_TO_LE16(buf_size);
4776 return ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);
4780 * ice_fw_supports_lldp_fltr - check NVM version supports lldp_fltr_ctrl
4781 * @hw: pointer to HW struct
4783 bool ice_fw_supports_lldp_fltr_ctrl(struct ice_hw *hw)
4785 if (hw->mac_type != ICE_MAC_E810)
4788 if (hw->api_maj_ver == ICE_FW_API_LLDP_FLTR_MAJ) {
4789 if (hw->api_min_ver > ICE_FW_API_LLDP_FLTR_MIN)
4791 if (hw->api_min_ver == ICE_FW_API_LLDP_FLTR_MIN &&
4792 hw->api_patch >= ICE_FW_API_LLDP_FLTR_PATCH)
4794 } else if (hw->api_maj_ver > ICE_FW_API_LLDP_FLTR_MAJ) {
4801 * ice_lldp_fltr_add_remove - add or remove a LLDP Rx switch filter
4802 * @hw: pointer to HW struct
4803 * @vsi_num: absolute HW index for VSI
4804 * @add: boolean for if adding or removing a filter
4807 ice_lldp_fltr_add_remove(struct ice_hw *hw, u16 vsi_num, bool add)
4809 struct ice_aqc_lldp_filter_ctrl *cmd;
4810 struct ice_aq_desc desc;
4812 cmd = &desc.params.lldp_filter_ctrl;
4814 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_lldp_filter_ctrl);
4817 cmd->cmd_flags = ICE_AQC_LLDP_FILTER_ACTION_ADD;
4819 cmd->cmd_flags = ICE_AQC_LLDP_FILTER_ACTION_DELETE;
4821 cmd->vsi_num = CPU_TO_LE16(vsi_num);
4823 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);