1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2001-2020 Intel Corporation
5 #include "ice_common.h"
7 #include "ice_adminq_cmd.h"
10 #include "ice_switch.h"
12 #define ICE_PF_RESET_WAIT_COUNT 300
15 * ice_set_mac_type - Sets MAC type
16 * @hw: pointer to the HW structure
18 * This function sets the MAC type of the adapter based on the
19 * vendor ID and device ID stored in the HW structure.
21 static enum ice_status ice_set_mac_type(struct ice_hw *hw)
23 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
25 if (hw->vendor_id != ICE_INTEL_VENDOR_ID)
26 return ICE_ERR_DEVICE_NOT_SUPPORTED;
28 switch (hw->device_id) {
29 case ICE_DEV_ID_E810C_BACKPLANE:
30 case ICE_DEV_ID_E810C_QSFP:
31 case ICE_DEV_ID_E810C_SFP:
32 case ICE_DEV_ID_E810_XXV_BACKPLANE:
33 case ICE_DEV_ID_E810_XXV_QSFP:
34 case ICE_DEV_ID_E810_XXV_SFP:
35 hw->mac_type = ICE_MAC_E810;
37 case ICE_DEV_ID_E822C_10G_BASE_T:
38 case ICE_DEV_ID_E822C_BACKPLANE:
39 case ICE_DEV_ID_E822C_QSFP:
40 case ICE_DEV_ID_E822C_SFP:
41 case ICE_DEV_ID_E822C_SGMII:
42 case ICE_DEV_ID_E822L_10G_BASE_T:
43 case ICE_DEV_ID_E822L_BACKPLANE:
44 case ICE_DEV_ID_E822L_SFP:
45 case ICE_DEV_ID_E822L_SGMII:
46 hw->mac_type = ICE_MAC_GENERIC;
49 hw->mac_type = ICE_MAC_UNKNOWN;
53 ice_debug(hw, ICE_DBG_INIT, "mac_type: %d\n", hw->mac_type);
58 * ice_clear_pf_cfg - Clear PF configuration
59 * @hw: pointer to the hardware structure
61 * Clears any existing PF configuration (VSIs, VSI lists, switch rules, port
62 * configuration, flow director filters, etc.).
64 enum ice_status ice_clear_pf_cfg(struct ice_hw *hw)
66 struct ice_aq_desc desc;
68 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pf_cfg);
70 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
74 * ice_aq_manage_mac_read - manage MAC address read command
75 * @hw: pointer to the HW struct
76 * @buf: a virtual buffer to hold the manage MAC read response
77 * @buf_size: Size of the virtual buffer
78 * @cd: pointer to command details structure or NULL
80 * This function is used to return per PF station MAC address (0x0107).
81 * NOTE: Upon successful completion of this command, MAC address information
82 * is returned in user specified buffer. Please interpret user specified
83 * buffer as "manage_mac_read" response.
84 * Response such as various MAC addresses are stored in HW struct (port.mac)
85 * ice_aq_discover_caps is expected to be called before this function is called.
87 static enum ice_status
88 ice_aq_manage_mac_read(struct ice_hw *hw, void *buf, u16 buf_size,
91 struct ice_aqc_manage_mac_read_resp *resp;
92 struct ice_aqc_manage_mac_read *cmd;
93 struct ice_aq_desc desc;
94 enum ice_status status;
98 cmd = &desc.params.mac_read;
100 if (buf_size < sizeof(*resp))
101 return ICE_ERR_BUF_TOO_SHORT;
103 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_read);
105 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);
109 resp = (struct ice_aqc_manage_mac_read_resp *)buf;
110 flags = LE16_TO_CPU(cmd->flags) & ICE_AQC_MAN_MAC_READ_M;
112 if (!(flags & ICE_AQC_MAN_MAC_LAN_ADDR_VALID)) {
113 ice_debug(hw, ICE_DBG_LAN, "got invalid MAC address\n");
117 /* A single port can report up to two (LAN and WoL) addresses */
118 for (i = 0; i < cmd->num_addr; i++)
119 if (resp[i].addr_type == ICE_AQC_MAN_MAC_ADDR_TYPE_LAN) {
120 ice_memcpy(hw->port_info->mac.lan_addr,
121 resp[i].mac_addr, ETH_ALEN,
123 ice_memcpy(hw->port_info->mac.perm_addr,
125 ETH_ALEN, ICE_DMA_TO_NONDMA);
132 * ice_aq_get_phy_caps - returns PHY capabilities
133 * @pi: port information structure
134 * @qual_mods: report qualified modules
135 * @report_mode: report mode capabilities
136 * @pcaps: structure for PHY capabilities to be filled
137 * @cd: pointer to command details structure or NULL
139 * Returns the various PHY capabilities supported on the Port (0x0600)
142 ice_aq_get_phy_caps(struct ice_port_info *pi, bool qual_mods, u8 report_mode,
143 struct ice_aqc_get_phy_caps_data *pcaps,
144 struct ice_sq_cd *cd)
146 struct ice_aqc_get_phy_caps *cmd;
147 u16 pcaps_size = sizeof(*pcaps);
148 struct ice_aq_desc desc;
149 enum ice_status status;
152 cmd = &desc.params.get_phy;
154 if (!pcaps || (report_mode & ~ICE_AQC_REPORT_MODE_M) || !pi)
155 return ICE_ERR_PARAM;
158 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_phy_caps);
161 cmd->param0 |= CPU_TO_LE16(ICE_AQC_GET_PHY_RQM);
163 cmd->param0 |= CPU_TO_LE16(report_mode);
164 status = ice_aq_send_cmd(hw, &desc, pcaps, pcaps_size, cd);
166 ice_debug(hw, ICE_DBG_LINK, "get phy caps - report_mode = 0x%x\n",
168 ice_debug(hw, ICE_DBG_LINK, " phy_type_low = 0x%llx\n",
169 (unsigned long long)LE64_TO_CPU(pcaps->phy_type_low));
170 ice_debug(hw, ICE_DBG_LINK, " phy_type_high = 0x%llx\n",
171 (unsigned long long)LE64_TO_CPU(pcaps->phy_type_high));
172 ice_debug(hw, ICE_DBG_LINK, " caps = 0x%x\n", pcaps->caps);
173 ice_debug(hw, ICE_DBG_LINK, " low_power_ctrl_an = 0x%x\n",
174 pcaps->low_power_ctrl_an);
175 ice_debug(hw, ICE_DBG_LINK, " eee_cap = 0x%x\n", pcaps->eee_cap);
176 ice_debug(hw, ICE_DBG_LINK, " eeer_value = 0x%x\n",
178 ice_debug(hw, ICE_DBG_LINK, " link_fec_options = 0x%x\n",
179 pcaps->link_fec_options);
180 ice_debug(hw, ICE_DBG_LINK, " module_compliance_enforcement = 0x%x\n",
181 pcaps->module_compliance_enforcement);
182 ice_debug(hw, ICE_DBG_LINK, " extended_compliance_code = 0x%x\n",
183 pcaps->extended_compliance_code);
184 ice_debug(hw, ICE_DBG_LINK, " module_type[0] = 0x%x\n",
185 pcaps->module_type[0]);
186 ice_debug(hw, ICE_DBG_LINK, " module_type[1] = 0x%x\n",
187 pcaps->module_type[1]);
188 ice_debug(hw, ICE_DBG_LINK, " module_type[2] = 0x%x\n",
189 pcaps->module_type[2]);
192 if (status == ICE_SUCCESS && report_mode == ICE_AQC_REPORT_TOPO_CAP) {
193 pi->phy.phy_type_low = LE64_TO_CPU(pcaps->phy_type_low);
194 pi->phy.phy_type_high = LE64_TO_CPU(pcaps->phy_type_high);
201 * ice_aq_get_link_topo_handle - get link topology node return status
202 * @pi: port information structure
203 * @node_type: requested node type
204 * @cd: pointer to command details structure or NULL
206 * Get link topology node return status for specified node type (0x06E0)
208 * Node type cage can be used to determine if cage is present. If AQC
209 * returns error (ENOENT), then no cage present. If no cage present, then
210 * connection type is backplane or BASE-T.
212 static enum ice_status
213 ice_aq_get_link_topo_handle(struct ice_port_info *pi, u8 node_type,
214 struct ice_sq_cd *cd)
216 struct ice_aqc_get_link_topo *cmd;
217 struct ice_aq_desc desc;
219 cmd = &desc.params.get_link_topo;
221 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_topo);
223 cmd->addr.node_type_ctx = (ICE_AQC_LINK_TOPO_NODE_CTX_PORT <<
224 ICE_AQC_LINK_TOPO_NODE_CTX_S);
227 cmd->addr.node_type_ctx |= (ICE_AQC_LINK_TOPO_NODE_TYPE_M & node_type);
229 return ice_aq_send_cmd(pi->hw, &desc, NULL, 0, cd);
233 * ice_is_media_cage_present
234 * @pi: port information structure
236 * Returns true if media cage is present, else false. If no cage, then
237 * media type is backplane or BASE-T.
239 static bool ice_is_media_cage_present(struct ice_port_info *pi)
241 /* Node type cage can be used to determine if cage is present. If AQC
242 * returns error (ENOENT), then no cage present. If no cage present then
243 * connection type is backplane or BASE-T.
245 return !ice_aq_get_link_topo_handle(pi,
246 ICE_AQC_LINK_TOPO_NODE_TYPE_CAGE,
251 * ice_get_media_type - Gets media type
252 * @pi: port information structure
254 static enum ice_media_type ice_get_media_type(struct ice_port_info *pi)
256 struct ice_link_status *hw_link_info;
259 return ICE_MEDIA_UNKNOWN;
261 hw_link_info = &pi->phy.link_info;
262 if (hw_link_info->phy_type_low && hw_link_info->phy_type_high)
263 /* If more than one media type is selected, report unknown */
264 return ICE_MEDIA_UNKNOWN;
266 if (hw_link_info->phy_type_low) {
267 switch (hw_link_info->phy_type_low) {
268 case ICE_PHY_TYPE_LOW_1000BASE_SX:
269 case ICE_PHY_TYPE_LOW_1000BASE_LX:
270 case ICE_PHY_TYPE_LOW_10GBASE_SR:
271 case ICE_PHY_TYPE_LOW_10GBASE_LR:
272 case ICE_PHY_TYPE_LOW_10G_SFI_C2C:
273 case ICE_PHY_TYPE_LOW_25GBASE_SR:
274 case ICE_PHY_TYPE_LOW_25GBASE_LR:
275 case ICE_PHY_TYPE_LOW_40GBASE_SR4:
276 case ICE_PHY_TYPE_LOW_40GBASE_LR4:
277 case ICE_PHY_TYPE_LOW_50GBASE_SR2:
278 case ICE_PHY_TYPE_LOW_50GBASE_LR2:
279 case ICE_PHY_TYPE_LOW_50GBASE_SR:
280 case ICE_PHY_TYPE_LOW_50GBASE_FR:
281 case ICE_PHY_TYPE_LOW_50GBASE_LR:
282 case ICE_PHY_TYPE_LOW_100GBASE_SR4:
283 case ICE_PHY_TYPE_LOW_100GBASE_LR4:
284 case ICE_PHY_TYPE_LOW_100GBASE_SR2:
285 case ICE_PHY_TYPE_LOW_100GBASE_DR:
286 return ICE_MEDIA_FIBER;
287 case ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC:
288 case ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC:
289 case ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC:
290 case ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC:
291 case ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC:
292 case ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC:
293 case ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC:
294 case ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC:
295 return ICE_MEDIA_FIBER;
296 case ICE_PHY_TYPE_LOW_100BASE_TX:
297 case ICE_PHY_TYPE_LOW_1000BASE_T:
298 case ICE_PHY_TYPE_LOW_2500BASE_T:
299 case ICE_PHY_TYPE_LOW_5GBASE_T:
300 case ICE_PHY_TYPE_LOW_10GBASE_T:
301 case ICE_PHY_TYPE_LOW_25GBASE_T:
302 return ICE_MEDIA_BASET;
303 case ICE_PHY_TYPE_LOW_10G_SFI_DA:
304 case ICE_PHY_TYPE_LOW_25GBASE_CR:
305 case ICE_PHY_TYPE_LOW_25GBASE_CR_S:
306 case ICE_PHY_TYPE_LOW_25GBASE_CR1:
307 case ICE_PHY_TYPE_LOW_40GBASE_CR4:
308 case ICE_PHY_TYPE_LOW_50GBASE_CR2:
309 case ICE_PHY_TYPE_LOW_50GBASE_CP:
310 case ICE_PHY_TYPE_LOW_100GBASE_CR4:
311 case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4:
312 case ICE_PHY_TYPE_LOW_100GBASE_CP2:
314 case ICE_PHY_TYPE_LOW_25G_AUI_C2C:
315 case ICE_PHY_TYPE_LOW_40G_XLAUI:
316 case ICE_PHY_TYPE_LOW_50G_LAUI2:
317 case ICE_PHY_TYPE_LOW_50G_AUI2:
318 case ICE_PHY_TYPE_LOW_50G_AUI1:
319 case ICE_PHY_TYPE_LOW_100G_AUI4:
320 case ICE_PHY_TYPE_LOW_100G_CAUI4:
321 if (ice_is_media_cage_present(pi))
322 return ICE_MEDIA_AUI;
324 case ICE_PHY_TYPE_LOW_1000BASE_KX:
325 case ICE_PHY_TYPE_LOW_2500BASE_KX:
326 case ICE_PHY_TYPE_LOW_2500BASE_X:
327 case ICE_PHY_TYPE_LOW_5GBASE_KR:
328 case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1:
329 case ICE_PHY_TYPE_LOW_25GBASE_KR:
330 case ICE_PHY_TYPE_LOW_25GBASE_KR1:
331 case ICE_PHY_TYPE_LOW_25GBASE_KR_S:
332 case ICE_PHY_TYPE_LOW_40GBASE_KR4:
333 case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4:
334 case ICE_PHY_TYPE_LOW_50GBASE_KR2:
335 case ICE_PHY_TYPE_LOW_100GBASE_KR4:
336 case ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4:
337 return ICE_MEDIA_BACKPLANE;
340 switch (hw_link_info->phy_type_high) {
341 case ICE_PHY_TYPE_HIGH_100G_AUI2:
342 case ICE_PHY_TYPE_HIGH_100G_CAUI2:
343 if (ice_is_media_cage_present(pi))
344 return ICE_MEDIA_AUI;
346 case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4:
347 return ICE_MEDIA_BACKPLANE;
348 case ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC:
349 case ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC:
350 return ICE_MEDIA_FIBER;
353 return ICE_MEDIA_UNKNOWN;
357 * ice_aq_get_link_info
358 * @pi: port information structure
359 * @ena_lse: enable/disable LinkStatusEvent reporting
360 * @link: pointer to link status structure - optional
361 * @cd: pointer to command details structure or NULL
363 * Get Link Status (0x607). Returns the link status of the adapter.
366 ice_aq_get_link_info(struct ice_port_info *pi, bool ena_lse,
367 struct ice_link_status *link, struct ice_sq_cd *cd)
369 struct ice_aqc_get_link_status_data link_data = { 0 };
370 struct ice_aqc_get_link_status *resp;
371 struct ice_link_status *li_old, *li;
372 enum ice_media_type *hw_media_type;
373 struct ice_fc_info *hw_fc_info;
374 bool tx_pause, rx_pause;
375 struct ice_aq_desc desc;
376 enum ice_status status;
381 return ICE_ERR_PARAM;
383 li_old = &pi->phy.link_info_old;
384 hw_media_type = &pi->phy.media_type;
385 li = &pi->phy.link_info;
386 hw_fc_info = &pi->fc;
388 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_status);
389 cmd_flags = (ena_lse) ? ICE_AQ_LSE_ENA : ICE_AQ_LSE_DIS;
390 resp = &desc.params.get_link_status;
391 resp->cmd_flags = CPU_TO_LE16(cmd_flags);
392 resp->lport_num = pi->lport;
394 status = ice_aq_send_cmd(hw, &desc, &link_data, sizeof(link_data), cd);
396 if (status != ICE_SUCCESS)
399 /* save off old link status information */
402 /* update current link status information */
403 li->link_speed = LE16_TO_CPU(link_data.link_speed);
404 li->phy_type_low = LE64_TO_CPU(link_data.phy_type_low);
405 li->phy_type_high = LE64_TO_CPU(link_data.phy_type_high);
406 *hw_media_type = ice_get_media_type(pi);
407 li->link_info = link_data.link_info;
408 li->an_info = link_data.an_info;
409 li->ext_info = link_data.ext_info;
410 li->max_frame_size = LE16_TO_CPU(link_data.max_frame_size);
411 li->fec_info = link_data.cfg & ICE_AQ_FEC_MASK;
412 li->topo_media_conflict = link_data.topo_media_conflict;
413 li->pacing = link_data.cfg & (ICE_AQ_CFG_PACING_M |
414 ICE_AQ_CFG_PACING_TYPE_M);
417 tx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_TX);
418 rx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_RX);
419 if (tx_pause && rx_pause)
420 hw_fc_info->current_mode = ICE_FC_FULL;
422 hw_fc_info->current_mode = ICE_FC_TX_PAUSE;
424 hw_fc_info->current_mode = ICE_FC_RX_PAUSE;
426 hw_fc_info->current_mode = ICE_FC_NONE;
428 li->lse_ena = !!(resp->cmd_flags & CPU_TO_LE16(ICE_AQ_LSE_IS_ENABLED));
430 ice_debug(hw, ICE_DBG_LINK, "get link info\n");
431 ice_debug(hw, ICE_DBG_LINK, " link_speed = 0x%x\n", li->link_speed);
432 ice_debug(hw, ICE_DBG_LINK, " phy_type_low = 0x%llx\n",
433 (unsigned long long)li->phy_type_low);
434 ice_debug(hw, ICE_DBG_LINK, " phy_type_high = 0x%llx\n",
435 (unsigned long long)li->phy_type_high);
436 ice_debug(hw, ICE_DBG_LINK, " media_type = 0x%x\n", *hw_media_type);
437 ice_debug(hw, ICE_DBG_LINK, " link_info = 0x%x\n", li->link_info);
438 ice_debug(hw, ICE_DBG_LINK, " an_info = 0x%x\n", li->an_info);
439 ice_debug(hw, ICE_DBG_LINK, " ext_info = 0x%x\n", li->ext_info);
440 ice_debug(hw, ICE_DBG_LINK, " fec_info = 0x%x\n", li->fec_info);
441 ice_debug(hw, ICE_DBG_LINK, " lse_ena = 0x%x\n", li->lse_ena);
442 ice_debug(hw, ICE_DBG_LINK, " max_frame = 0x%x\n",
444 ice_debug(hw, ICE_DBG_LINK, " pacing = 0x%x\n", li->pacing);
446 /* save link status information */
450 /* flag cleared so calling functions don't call AQ again */
451 pi->phy.get_link_info = false;
457 * ice_fill_tx_timer_and_fc_thresh
458 * @hw: pointer to the HW struct
459 * @cmd: pointer to MAC cfg structure
461 * Add Tx timer and FC refresh threshold info to Set MAC Config AQ command
465 ice_fill_tx_timer_and_fc_thresh(struct ice_hw *hw,
466 struct ice_aqc_set_mac_cfg *cmd)
468 u16 fc_thres_val, tx_timer_val;
471 /* We read back the transmit timer and fc threshold value of
472 * LFC. Thus, we will use index =
473 * PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX.
475 * Also, because we are opearating on transmit timer and fc
476 * threshold of LFC, we don't turn on any bit in tx_tmr_priority
478 #define IDX_OF_LFC PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX
480 /* Retrieve the transmit timer */
481 val = rd32(hw, PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(IDX_OF_LFC));
483 PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_HSEC_CTL_TX_PAUSE_QUANTA_M;
484 cmd->tx_tmr_value = CPU_TO_LE16(tx_timer_val);
486 /* Retrieve the fc threshold */
487 val = rd32(hw, PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(IDX_OF_LFC));
488 fc_thres_val = val & PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_M;
490 cmd->fc_refresh_threshold = CPU_TO_LE16(fc_thres_val);
495 * @hw: pointer to the HW struct
496 * @max_frame_size: Maximum Frame Size to be supported
497 * @cd: pointer to command details structure or NULL
499 * Set MAC configuration (0x0603)
502 ice_aq_set_mac_cfg(struct ice_hw *hw, u16 max_frame_size, struct ice_sq_cd *cd)
504 struct ice_aqc_set_mac_cfg *cmd;
505 struct ice_aq_desc desc;
507 cmd = &desc.params.set_mac_cfg;
509 if (max_frame_size == 0)
510 return ICE_ERR_PARAM;
512 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_mac_cfg);
514 cmd->max_frame_size = CPU_TO_LE16(max_frame_size);
516 ice_fill_tx_timer_and_fc_thresh(hw, cmd);
518 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
522 * ice_init_fltr_mgmt_struct - initializes filter management list and locks
523 * @hw: pointer to the HW struct
525 enum ice_status ice_init_fltr_mgmt_struct(struct ice_hw *hw)
527 struct ice_switch_info *sw;
528 enum ice_status status;
530 hw->switch_info = (struct ice_switch_info *)
531 ice_malloc(hw, sizeof(*hw->switch_info));
533 sw = hw->switch_info;
536 return ICE_ERR_NO_MEMORY;
538 INIT_LIST_HEAD(&sw->vsi_list_map_head);
539 sw->prof_res_bm_init = 0;
541 status = ice_init_def_sw_recp(hw, &hw->switch_info->recp_list);
543 ice_free(hw, hw->switch_info);
550 * ice_cleanup_fltr_mgmt_single - clears single filter mngt struct
551 * @hw: pointer to the HW struct
552 * @sw: pointer to switch info struct for which function clears filters
555 ice_cleanup_fltr_mgmt_single(struct ice_hw *hw, struct ice_switch_info *sw)
557 struct ice_vsi_list_map_info *v_pos_map;
558 struct ice_vsi_list_map_info *v_tmp_map;
559 struct ice_sw_recipe *recps;
565 LIST_FOR_EACH_ENTRY_SAFE(v_pos_map, v_tmp_map, &sw->vsi_list_map_head,
566 ice_vsi_list_map_info, list_entry) {
567 LIST_DEL(&v_pos_map->list_entry);
568 ice_free(hw, v_pos_map);
570 recps = sw->recp_list;
571 for (i = 0; i < ICE_MAX_NUM_RECIPES; i++) {
572 struct ice_recp_grp_entry *rg_entry, *tmprg_entry;
574 recps[i].root_rid = i;
575 LIST_FOR_EACH_ENTRY_SAFE(rg_entry, tmprg_entry,
576 &recps[i].rg_list, ice_recp_grp_entry,
578 LIST_DEL(&rg_entry->l_entry);
579 ice_free(hw, rg_entry);
582 if (recps[i].adv_rule) {
583 struct ice_adv_fltr_mgmt_list_entry *tmp_entry;
584 struct ice_adv_fltr_mgmt_list_entry *lst_itr;
586 ice_destroy_lock(&recps[i].filt_rule_lock);
587 LIST_FOR_EACH_ENTRY_SAFE(lst_itr, tmp_entry,
588 &recps[i].filt_rules,
589 ice_adv_fltr_mgmt_list_entry,
591 LIST_DEL(&lst_itr->list_entry);
592 ice_free(hw, lst_itr->lkups);
593 ice_free(hw, lst_itr);
596 struct ice_fltr_mgmt_list_entry *lst_itr, *tmp_entry;
598 ice_destroy_lock(&recps[i].filt_rule_lock);
599 LIST_FOR_EACH_ENTRY_SAFE(lst_itr, tmp_entry,
600 &recps[i].filt_rules,
601 ice_fltr_mgmt_list_entry,
603 LIST_DEL(&lst_itr->list_entry);
604 ice_free(hw, lst_itr);
607 if (recps[i].root_buf)
608 ice_free(hw, recps[i].root_buf);
610 ice_rm_sw_replay_rule_info(hw, sw);
611 ice_free(hw, sw->recp_list);
616 * ice_cleanup_all_fltr_mgmt - cleanup filter management list and locks
617 * @hw: pointer to the HW struct
619 void ice_cleanup_fltr_mgmt_struct(struct ice_hw *hw)
621 ice_cleanup_fltr_mgmt_single(hw, hw->switch_info);
625 * ice_get_itr_intrl_gran
626 * @hw: pointer to the HW struct
628 * Determines the ITR/INTRL granularities based on the maximum aggregate
629 * bandwidth according to the device's configuration during power-on.
631 static void ice_get_itr_intrl_gran(struct ice_hw *hw)
633 u8 max_agg_bw = (rd32(hw, GL_PWR_MODE_CTL) &
634 GL_PWR_MODE_CTL_CAR_MAX_BW_M) >>
635 GL_PWR_MODE_CTL_CAR_MAX_BW_S;
637 switch (max_agg_bw) {
638 case ICE_MAX_AGG_BW_200G:
639 case ICE_MAX_AGG_BW_100G:
640 case ICE_MAX_AGG_BW_50G:
641 hw->itr_gran = ICE_ITR_GRAN_ABOVE_25;
642 hw->intrl_gran = ICE_INTRL_GRAN_ABOVE_25;
644 case ICE_MAX_AGG_BW_25G:
645 hw->itr_gran = ICE_ITR_GRAN_MAX_25;
646 hw->intrl_gran = ICE_INTRL_GRAN_MAX_25;
652 * ice_print_rollback_msg - print FW rollback message
653 * @hw: pointer to the hardware structure
655 void ice_print_rollback_msg(struct ice_hw *hw)
657 char nvm_str[ICE_NVM_VER_LEN] = { 0 };
658 struct ice_nvm_info *nvm = &hw->nvm;
659 struct ice_orom_info *orom;
663 SNPRINTF(nvm_str, sizeof(nvm_str), "%x.%02x 0x%x %d.%d.%d",
664 nvm->major_ver, nvm->minor_ver, nvm->eetrack, orom->major,
665 orom->build, orom->patch);
667 "Firmware rollback mode detected. Current version is NVM: %s, FW: %d.%d. Device may exhibit limited functionality. Refer to the Intel(R) Ethernet Adapters and Devices User Guide for details on firmware rollback mode\n",
668 nvm_str, hw->fw_maj_ver, hw->fw_min_ver);
672 * ice_init_hw - main hardware initialization routine
673 * @hw: pointer to the hardware structure
675 enum ice_status ice_init_hw(struct ice_hw *hw)
677 struct ice_aqc_get_phy_caps_data *pcaps;
678 enum ice_status status;
682 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
684 /* Set MAC type based on DeviceID */
685 status = ice_set_mac_type(hw);
689 hw->pf_id = (u8)(rd32(hw, PF_FUNC_RID) &
690 PF_FUNC_RID_FUNCTION_NUMBER_M) >>
691 PF_FUNC_RID_FUNCTION_NUMBER_S;
693 status = ice_reset(hw, ICE_RESET_PFR);
697 ice_get_itr_intrl_gran(hw);
699 status = ice_create_all_ctrlq(hw);
701 goto err_unroll_cqinit;
703 status = ice_init_nvm(hw);
705 goto err_unroll_cqinit;
707 if (ice_get_fw_mode(hw) == ICE_FW_MODE_ROLLBACK)
708 ice_print_rollback_msg(hw);
710 status = ice_clear_pf_cfg(hw);
712 goto err_unroll_cqinit;
714 /* Set bit to enable Flow Director filters */
715 wr32(hw, PFQF_FD_ENA, PFQF_FD_ENA_FD_ENA_M);
716 INIT_LIST_HEAD(&hw->fdir_list_head);
718 ice_clear_pxe_mode(hw);
720 status = ice_get_caps(hw);
722 goto err_unroll_cqinit;
724 hw->port_info = (struct ice_port_info *)
725 ice_malloc(hw, sizeof(*hw->port_info));
726 if (!hw->port_info) {
727 status = ICE_ERR_NO_MEMORY;
728 goto err_unroll_cqinit;
731 /* set the back pointer to HW */
732 hw->port_info->hw = hw;
734 /* Initialize port_info struct with switch configuration data */
735 status = ice_get_initial_sw_cfg(hw);
737 goto err_unroll_alloc;
740 /* Query the allocated resources for Tx scheduler */
741 status = ice_sched_query_res_alloc(hw);
743 ice_debug(hw, ICE_DBG_SCHED,
744 "Failed to get scheduler allocated resources\n");
745 goto err_unroll_alloc;
747 ice_sched_get_psm_clk_freq(hw);
749 /* Initialize port_info struct with scheduler data */
750 status = ice_sched_init_port(hw->port_info);
752 goto err_unroll_sched;
754 pcaps = (struct ice_aqc_get_phy_caps_data *)
755 ice_malloc(hw, sizeof(*pcaps));
757 status = ICE_ERR_NO_MEMORY;
758 goto err_unroll_sched;
761 /* Initialize port_info struct with PHY capabilities */
762 status = ice_aq_get_phy_caps(hw->port_info, false,
763 ICE_AQC_REPORT_TOPO_CAP, pcaps, NULL);
766 goto err_unroll_sched;
768 /* Initialize port_info struct with link information */
769 status = ice_aq_get_link_info(hw->port_info, false, NULL, NULL);
771 goto err_unroll_sched;
772 /* need a valid SW entry point to build a Tx tree */
773 if (!hw->sw_entry_point_layer) {
774 ice_debug(hw, ICE_DBG_SCHED, "invalid sw entry point\n");
775 status = ICE_ERR_CFG;
776 goto err_unroll_sched;
778 INIT_LIST_HEAD(&hw->agg_list);
779 /* Initialize max burst size */
780 if (!hw->max_burst_size)
781 ice_cfg_rl_burst_size(hw, ICE_SCHED_DFLT_BURST_SIZE);
782 status = ice_init_fltr_mgmt_struct(hw);
784 goto err_unroll_sched;
786 /* Get MAC information */
787 /* A single port can report up to two (LAN and WoL) addresses */
788 mac_buf = ice_calloc(hw, 2,
789 sizeof(struct ice_aqc_manage_mac_read_resp));
790 mac_buf_len = 2 * sizeof(struct ice_aqc_manage_mac_read_resp);
793 status = ICE_ERR_NO_MEMORY;
794 goto err_unroll_fltr_mgmt_struct;
797 status = ice_aq_manage_mac_read(hw, mac_buf, mac_buf_len, NULL);
798 ice_free(hw, mac_buf);
801 goto err_unroll_fltr_mgmt_struct;
802 /* enable jumbo frame support at MAC level */
803 status = ice_aq_set_mac_cfg(hw, ICE_AQ_SET_MAC_FRAME_SIZE_MAX, NULL);
805 goto err_unroll_fltr_mgmt_struct;
806 /* Obtain counter base index which would be used by flow director */
807 status = ice_alloc_fd_res_cntr(hw, &hw->fd_ctr_base);
809 goto err_unroll_fltr_mgmt_struct;
810 status = ice_init_hw_tbls(hw);
812 goto err_unroll_fltr_mgmt_struct;
813 ice_init_lock(&hw->tnl_lock);
816 err_unroll_fltr_mgmt_struct:
817 ice_cleanup_fltr_mgmt_struct(hw);
819 ice_sched_cleanup_all(hw);
821 ice_free(hw, hw->port_info);
822 hw->port_info = NULL;
824 ice_destroy_all_ctrlq(hw);
829 * ice_deinit_hw - unroll initialization operations done by ice_init_hw
830 * @hw: pointer to the hardware structure
832 * This should be called only during nominal operation, not as a result of
833 * ice_init_hw() failing since ice_init_hw() will take care of unrolling
834 * applicable initializations if it fails for any reason.
836 void ice_deinit_hw(struct ice_hw *hw)
838 ice_free_fd_res_cntr(hw, hw->fd_ctr_base);
839 ice_cleanup_fltr_mgmt_struct(hw);
841 ice_sched_cleanup_all(hw);
842 ice_sched_clear_agg(hw);
844 ice_free_hw_tbls(hw);
845 ice_destroy_lock(&hw->tnl_lock);
848 ice_free(hw, hw->port_info);
849 hw->port_info = NULL;
852 ice_destroy_all_ctrlq(hw);
854 /* Clear VSI contexts if not already cleared */
855 ice_clear_all_vsi_ctx(hw);
859 * ice_check_reset - Check to see if a global reset is complete
860 * @hw: pointer to the hardware structure
862 enum ice_status ice_check_reset(struct ice_hw *hw)
864 u32 cnt, reg = 0, grst_delay, uld_mask;
866 /* Poll for Device Active state in case a recent CORER, GLOBR,
867 * or EMPR has occurred. The grst delay value is in 100ms units.
868 * Add 1sec for outstanding AQ commands that can take a long time.
870 grst_delay = ((rd32(hw, GLGEN_RSTCTL) & GLGEN_RSTCTL_GRSTDEL_M) >>
871 GLGEN_RSTCTL_GRSTDEL_S) + 10;
873 for (cnt = 0; cnt < grst_delay; cnt++) {
874 ice_msec_delay(100, true);
875 reg = rd32(hw, GLGEN_RSTAT);
876 if (!(reg & GLGEN_RSTAT_DEVSTATE_M))
880 if (cnt == grst_delay) {
881 ice_debug(hw, ICE_DBG_INIT,
882 "Global reset polling failed to complete.\n");
883 return ICE_ERR_RESET_FAILED;
886 #define ICE_RESET_DONE_MASK (GLNVM_ULD_PCIER_DONE_M |\
887 GLNVM_ULD_PCIER_DONE_1_M |\
888 GLNVM_ULD_CORER_DONE_M |\
889 GLNVM_ULD_GLOBR_DONE_M |\
890 GLNVM_ULD_POR_DONE_M |\
891 GLNVM_ULD_POR_DONE_1_M |\
892 GLNVM_ULD_PCIER_DONE_2_M)
894 uld_mask = ICE_RESET_DONE_MASK;
896 /* Device is Active; check Global Reset processes are done */
897 for (cnt = 0; cnt < ICE_PF_RESET_WAIT_COUNT; cnt++) {
898 reg = rd32(hw, GLNVM_ULD) & uld_mask;
899 if (reg == uld_mask) {
900 ice_debug(hw, ICE_DBG_INIT,
901 "Global reset processes done. %d\n", cnt);
904 ice_msec_delay(10, true);
907 if (cnt == ICE_PF_RESET_WAIT_COUNT) {
908 ice_debug(hw, ICE_DBG_INIT,
909 "Wait for Reset Done timed out. GLNVM_ULD = 0x%x\n",
911 return ICE_ERR_RESET_FAILED;
918 * ice_pf_reset - Reset the PF
919 * @hw: pointer to the hardware structure
921 * If a global reset has been triggered, this function checks
922 * for its completion and then issues the PF reset
924 static enum ice_status ice_pf_reset(struct ice_hw *hw)
928 /* If at function entry a global reset was already in progress, i.e.
929 * state is not 'device active' or any of the reset done bits are not
930 * set in GLNVM_ULD, there is no need for a PF Reset; poll until the
931 * global reset is done.
933 if ((rd32(hw, GLGEN_RSTAT) & GLGEN_RSTAT_DEVSTATE_M) ||
934 (rd32(hw, GLNVM_ULD) & ICE_RESET_DONE_MASK) ^ ICE_RESET_DONE_MASK) {
935 /* poll on global reset currently in progress until done */
936 if (ice_check_reset(hw))
937 return ICE_ERR_RESET_FAILED;
943 reg = rd32(hw, PFGEN_CTRL);
945 wr32(hw, PFGEN_CTRL, (reg | PFGEN_CTRL_PFSWR_M));
947 /* Wait for the PFR to complete. The wait time is the global config lock
948 * timeout plus the PFR timeout which will account for a possible reset
949 * that is occurring during a download package operation.
951 for (cnt = 0; cnt < ICE_GLOBAL_CFG_LOCK_TIMEOUT +
952 ICE_PF_RESET_WAIT_COUNT; cnt++) {
953 reg = rd32(hw, PFGEN_CTRL);
954 if (!(reg & PFGEN_CTRL_PFSWR_M))
957 ice_msec_delay(1, true);
960 if (cnt == ICE_PF_RESET_WAIT_COUNT) {
961 ice_debug(hw, ICE_DBG_INIT,
962 "PF reset polling failed to complete.\n");
963 return ICE_ERR_RESET_FAILED;
970 * ice_reset - Perform different types of reset
971 * @hw: pointer to the hardware structure
972 * @req: reset request
974 * This function triggers a reset as specified by the req parameter.
977 * If anything other than a PF reset is triggered, PXE mode is restored.
978 * This has to be cleared using ice_clear_pxe_mode again, once the AQ
979 * interface has been restored in the rebuild flow.
981 enum ice_status ice_reset(struct ice_hw *hw, enum ice_reset_req req)
987 return ice_pf_reset(hw);
988 case ICE_RESET_CORER:
989 ice_debug(hw, ICE_DBG_INIT, "CoreR requested\n");
990 val = GLGEN_RTRIG_CORER_M;
992 case ICE_RESET_GLOBR:
993 ice_debug(hw, ICE_DBG_INIT, "GlobalR requested\n");
994 val = GLGEN_RTRIG_GLOBR_M;
997 return ICE_ERR_PARAM;
1000 val |= rd32(hw, GLGEN_RTRIG);
1001 wr32(hw, GLGEN_RTRIG, val);
1004 /* wait for the FW to be ready */
1005 return ice_check_reset(hw);
1009 * ice_copy_rxq_ctx_to_hw
1010 * @hw: pointer to the hardware structure
1011 * @ice_rxq_ctx: pointer to the rxq context
1012 * @rxq_index: the index of the Rx queue
1014 * Copies rxq context from dense structure to HW register space
1016 static enum ice_status
1017 ice_copy_rxq_ctx_to_hw(struct ice_hw *hw, u8 *ice_rxq_ctx, u32 rxq_index)
1022 return ICE_ERR_BAD_PTR;
1024 if (rxq_index > QRX_CTRL_MAX_INDEX)
1025 return ICE_ERR_PARAM;
1027 /* Copy each dword separately to HW */
1028 for (i = 0; i < ICE_RXQ_CTX_SIZE_DWORDS; i++) {
1029 wr32(hw, QRX_CONTEXT(i, rxq_index),
1030 *((u32 *)(ice_rxq_ctx + (i * sizeof(u32)))));
1032 ice_debug(hw, ICE_DBG_QCTX, "qrxdata[%d]: %08X\n", i,
1033 *((u32 *)(ice_rxq_ctx + (i * sizeof(u32)))));
1039 /* LAN Rx Queue Context */
1040 static const struct ice_ctx_ele ice_rlan_ctx_info[] = {
1041 /* Field Width LSB */
1042 ICE_CTX_STORE(ice_rlan_ctx, head, 13, 0),
1043 ICE_CTX_STORE(ice_rlan_ctx, cpuid, 8, 13),
1044 ICE_CTX_STORE(ice_rlan_ctx, base, 57, 32),
1045 ICE_CTX_STORE(ice_rlan_ctx, qlen, 13, 89),
1046 ICE_CTX_STORE(ice_rlan_ctx, dbuf, 7, 102),
1047 ICE_CTX_STORE(ice_rlan_ctx, hbuf, 5, 109),
1048 ICE_CTX_STORE(ice_rlan_ctx, dtype, 2, 114),
1049 ICE_CTX_STORE(ice_rlan_ctx, dsize, 1, 116),
1050 ICE_CTX_STORE(ice_rlan_ctx, crcstrip, 1, 117),
1051 ICE_CTX_STORE(ice_rlan_ctx, l2tsel, 1, 119),
1052 ICE_CTX_STORE(ice_rlan_ctx, hsplit_0, 4, 120),
1053 ICE_CTX_STORE(ice_rlan_ctx, hsplit_1, 2, 124),
1054 ICE_CTX_STORE(ice_rlan_ctx, showiv, 1, 127),
1055 ICE_CTX_STORE(ice_rlan_ctx, rxmax, 14, 174),
1056 ICE_CTX_STORE(ice_rlan_ctx, tphrdesc_ena, 1, 193),
1057 ICE_CTX_STORE(ice_rlan_ctx, tphwdesc_ena, 1, 194),
1058 ICE_CTX_STORE(ice_rlan_ctx, tphdata_ena, 1, 195),
1059 ICE_CTX_STORE(ice_rlan_ctx, tphhead_ena, 1, 196),
1060 ICE_CTX_STORE(ice_rlan_ctx, lrxqthresh, 3, 198),
1061 ICE_CTX_STORE(ice_rlan_ctx, prefena, 1, 201),
1067 * @hw: pointer to the hardware structure
1068 * @rlan_ctx: pointer to the rxq context
1069 * @rxq_index: the index of the Rx queue
1071 * Converts rxq context from sparse to dense structure and then writes
1072 * it to HW register space and enables the hardware to prefetch descriptors
1073 * instead of only fetching them on demand
1076 ice_write_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx,
1079 u8 ctx_buf[ICE_RXQ_CTX_SZ] = { 0 };
1082 return ICE_ERR_BAD_PTR;
1084 rlan_ctx->prefena = 1;
1086 ice_set_ctx(hw, (u8 *)rlan_ctx, ctx_buf, ice_rlan_ctx_info);
1087 return ice_copy_rxq_ctx_to_hw(hw, ctx_buf, rxq_index);
1092 * @hw: pointer to the hardware structure
1093 * @rxq_index: the index of the Rx queue to clear
1095 * Clears rxq context in HW register space
1097 enum ice_status ice_clear_rxq_ctx(struct ice_hw *hw, u32 rxq_index)
1101 if (rxq_index > QRX_CTRL_MAX_INDEX)
1102 return ICE_ERR_PARAM;
1104 /* Clear each dword register separately */
1105 for (i = 0; i < ICE_RXQ_CTX_SIZE_DWORDS; i++)
1106 wr32(hw, QRX_CONTEXT(i, rxq_index), 0);
1111 /* LAN Tx Queue Context */
1112 const struct ice_ctx_ele ice_tlan_ctx_info[] = {
1113 /* Field Width LSB */
1114 ICE_CTX_STORE(ice_tlan_ctx, base, 57, 0),
1115 ICE_CTX_STORE(ice_tlan_ctx, port_num, 3, 57),
1116 ICE_CTX_STORE(ice_tlan_ctx, cgd_num, 5, 60),
1117 ICE_CTX_STORE(ice_tlan_ctx, pf_num, 3, 65),
1118 ICE_CTX_STORE(ice_tlan_ctx, vmvf_num, 10, 68),
1119 ICE_CTX_STORE(ice_tlan_ctx, vmvf_type, 2, 78),
1120 ICE_CTX_STORE(ice_tlan_ctx, src_vsi, 10, 80),
1121 ICE_CTX_STORE(ice_tlan_ctx, tsyn_ena, 1, 90),
1122 ICE_CTX_STORE(ice_tlan_ctx, internal_usage_flag, 1, 91),
1123 ICE_CTX_STORE(ice_tlan_ctx, alt_vlan, 1, 92),
1124 ICE_CTX_STORE(ice_tlan_ctx, cpuid, 8, 93),
1125 ICE_CTX_STORE(ice_tlan_ctx, wb_mode, 1, 101),
1126 ICE_CTX_STORE(ice_tlan_ctx, tphrd_desc, 1, 102),
1127 ICE_CTX_STORE(ice_tlan_ctx, tphrd, 1, 103),
1128 ICE_CTX_STORE(ice_tlan_ctx, tphwr_desc, 1, 104),
1129 ICE_CTX_STORE(ice_tlan_ctx, cmpq_id, 9, 105),
1130 ICE_CTX_STORE(ice_tlan_ctx, qnum_in_func, 14, 114),
1131 ICE_CTX_STORE(ice_tlan_ctx, itr_notification_mode, 1, 128),
1132 ICE_CTX_STORE(ice_tlan_ctx, adjust_prof_id, 6, 129),
1133 ICE_CTX_STORE(ice_tlan_ctx, qlen, 13, 135),
1134 ICE_CTX_STORE(ice_tlan_ctx, quanta_prof_idx, 4, 148),
1135 ICE_CTX_STORE(ice_tlan_ctx, tso_ena, 1, 152),
1136 ICE_CTX_STORE(ice_tlan_ctx, tso_qnum, 11, 153),
1137 ICE_CTX_STORE(ice_tlan_ctx, legacy_int, 1, 164),
1138 ICE_CTX_STORE(ice_tlan_ctx, drop_ena, 1, 165),
1139 ICE_CTX_STORE(ice_tlan_ctx, cache_prof_idx, 2, 166),
1140 ICE_CTX_STORE(ice_tlan_ctx, pkt_shaper_prof_idx, 3, 168),
1141 ICE_CTX_STORE(ice_tlan_ctx, int_q_state, 122, 171),
1146 * ice_copy_tx_cmpltnq_ctx_to_hw
1147 * @hw: pointer to the hardware structure
1148 * @ice_tx_cmpltnq_ctx: pointer to the Tx completion queue context
1149 * @tx_cmpltnq_index: the index of the completion queue
1151 * Copies Tx completion queue context from dense structure to HW register space
1153 static enum ice_status
1154 ice_copy_tx_cmpltnq_ctx_to_hw(struct ice_hw *hw, u8 *ice_tx_cmpltnq_ctx,
1155 u32 tx_cmpltnq_index)
1159 if (!ice_tx_cmpltnq_ctx)
1160 return ICE_ERR_BAD_PTR;
1162 if (tx_cmpltnq_index > GLTCLAN_CQ_CNTX0_MAX_INDEX)
1163 return ICE_ERR_PARAM;
1165 /* Copy each dword separately to HW */
1166 for (i = 0; i < ICE_TX_CMPLTNQ_CTX_SIZE_DWORDS; i++) {
1167 wr32(hw, GLTCLAN_CQ_CNTX(i, tx_cmpltnq_index),
1168 *((u32 *)(ice_tx_cmpltnq_ctx + (i * sizeof(u32)))));
1170 ice_debug(hw, ICE_DBG_QCTX, "cmpltnqdata[%d]: %08X\n", i,
1171 *((u32 *)(ice_tx_cmpltnq_ctx + (i * sizeof(u32)))));
1177 /* LAN Tx Completion Queue Context */
1178 static const struct ice_ctx_ele ice_tx_cmpltnq_ctx_info[] = {
1179 /* Field Width LSB */
1180 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, base, 57, 0),
1181 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, q_len, 18, 64),
1182 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, generation, 1, 96),
1183 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, wrt_ptr, 22, 97),
1184 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, pf_num, 3, 128),
1185 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, vmvf_num, 10, 131),
1186 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, vmvf_type, 2, 141),
1187 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, tph_desc_wr, 1, 160),
1188 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, cpuid, 8, 161),
1189 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, cmpltn_cache, 512, 192),
1194 * ice_write_tx_cmpltnq_ctx
1195 * @hw: pointer to the hardware structure
1196 * @tx_cmpltnq_ctx: pointer to the completion queue context
1197 * @tx_cmpltnq_index: the index of the completion queue
1199 * Converts completion queue context from sparse to dense structure and then
1200 * writes it to HW register space
1203 ice_write_tx_cmpltnq_ctx(struct ice_hw *hw,
1204 struct ice_tx_cmpltnq_ctx *tx_cmpltnq_ctx,
1205 u32 tx_cmpltnq_index)
1207 u8 ctx_buf[ICE_TX_CMPLTNQ_CTX_SIZE_DWORDS * sizeof(u32)] = { 0 };
1209 ice_set_ctx(hw, (u8 *)tx_cmpltnq_ctx, ctx_buf, ice_tx_cmpltnq_ctx_info);
1210 return ice_copy_tx_cmpltnq_ctx_to_hw(hw, ctx_buf, tx_cmpltnq_index);
1214 * ice_clear_tx_cmpltnq_ctx
1215 * @hw: pointer to the hardware structure
1216 * @tx_cmpltnq_index: the index of the completion queue to clear
1218 * Clears Tx completion queue context in HW register space
1221 ice_clear_tx_cmpltnq_ctx(struct ice_hw *hw, u32 tx_cmpltnq_index)
1225 if (tx_cmpltnq_index > GLTCLAN_CQ_CNTX0_MAX_INDEX)
1226 return ICE_ERR_PARAM;
1228 /* Clear each dword register separately */
1229 for (i = 0; i < ICE_TX_CMPLTNQ_CTX_SIZE_DWORDS; i++)
1230 wr32(hw, GLTCLAN_CQ_CNTX(i, tx_cmpltnq_index), 0);
1236 * ice_copy_tx_drbell_q_ctx_to_hw
1237 * @hw: pointer to the hardware structure
1238 * @ice_tx_drbell_q_ctx: pointer to the doorbell queue context
1239 * @tx_drbell_q_index: the index of the doorbell queue
1241 * Copies doorbell queue context from dense structure to HW register space
1243 static enum ice_status
1244 ice_copy_tx_drbell_q_ctx_to_hw(struct ice_hw *hw, u8 *ice_tx_drbell_q_ctx,
1245 u32 tx_drbell_q_index)
1249 if (!ice_tx_drbell_q_ctx)
1250 return ICE_ERR_BAD_PTR;
1252 if (tx_drbell_q_index > QTX_COMM_DBLQ_DBELL_MAX_INDEX)
1253 return ICE_ERR_PARAM;
1255 /* Copy each dword separately to HW */
1256 for (i = 0; i < ICE_TX_DRBELL_Q_CTX_SIZE_DWORDS; i++) {
1257 wr32(hw, QTX_COMM_DBLQ_CNTX(i, tx_drbell_q_index),
1258 *((u32 *)(ice_tx_drbell_q_ctx + (i * sizeof(u32)))));
1260 ice_debug(hw, ICE_DBG_QCTX, "tx_drbell_qdata[%d]: %08X\n", i,
1261 *((u32 *)(ice_tx_drbell_q_ctx + (i * sizeof(u32)))));
1267 /* LAN Tx Doorbell Queue Context info */
1268 static const struct ice_ctx_ele ice_tx_drbell_q_ctx_info[] = {
1269 /* Field Width LSB */
1270 ICE_CTX_STORE(ice_tx_drbell_q_ctx, base, 57, 0),
1271 ICE_CTX_STORE(ice_tx_drbell_q_ctx, ring_len, 13, 64),
1272 ICE_CTX_STORE(ice_tx_drbell_q_ctx, pf_num, 3, 80),
1273 ICE_CTX_STORE(ice_tx_drbell_q_ctx, vf_num, 8, 84),
1274 ICE_CTX_STORE(ice_tx_drbell_q_ctx, vmvf_type, 2, 94),
1275 ICE_CTX_STORE(ice_tx_drbell_q_ctx, cpuid, 8, 96),
1276 ICE_CTX_STORE(ice_tx_drbell_q_ctx, tph_desc_rd, 1, 104),
1277 ICE_CTX_STORE(ice_tx_drbell_q_ctx, tph_desc_wr, 1, 108),
1278 ICE_CTX_STORE(ice_tx_drbell_q_ctx, db_q_en, 1, 112),
1279 ICE_CTX_STORE(ice_tx_drbell_q_ctx, rd_head, 13, 128),
1280 ICE_CTX_STORE(ice_tx_drbell_q_ctx, rd_tail, 13, 144),
1285 * ice_write_tx_drbell_q_ctx
1286 * @hw: pointer to the hardware structure
1287 * @tx_drbell_q_ctx: pointer to the doorbell queue context
1288 * @tx_drbell_q_index: the index of the doorbell queue
1290 * Converts doorbell queue context from sparse to dense structure and then
1291 * writes it to HW register space
1294 ice_write_tx_drbell_q_ctx(struct ice_hw *hw,
1295 struct ice_tx_drbell_q_ctx *tx_drbell_q_ctx,
1296 u32 tx_drbell_q_index)
1298 u8 ctx_buf[ICE_TX_DRBELL_Q_CTX_SIZE_DWORDS * sizeof(u32)] = { 0 };
1300 ice_set_ctx(hw, (u8 *)tx_drbell_q_ctx, ctx_buf,
1301 ice_tx_drbell_q_ctx_info);
1302 return ice_copy_tx_drbell_q_ctx_to_hw(hw, ctx_buf, tx_drbell_q_index);
1306 * ice_clear_tx_drbell_q_ctx
1307 * @hw: pointer to the hardware structure
1308 * @tx_drbell_q_index: the index of the doorbell queue to clear
1310 * Clears doorbell queue context in HW register space
1313 ice_clear_tx_drbell_q_ctx(struct ice_hw *hw, u32 tx_drbell_q_index)
1317 if (tx_drbell_q_index > QTX_COMM_DBLQ_DBELL_MAX_INDEX)
1318 return ICE_ERR_PARAM;
1320 /* Clear each dword register separately */
1321 for (i = 0; i < ICE_TX_DRBELL_Q_CTX_SIZE_DWORDS; i++)
1322 wr32(hw, QTX_COMM_DBLQ_CNTX(i, tx_drbell_q_index), 0);
1327 /* FW Admin Queue command wrappers */
1330 * ice_aq_send_cmd - send FW Admin Queue command to FW Admin Queue
1331 * @hw: pointer to the HW struct
1332 * @desc: descriptor describing the command
1333 * @buf: buffer to use for indirect commands (NULL for direct commands)
1334 * @buf_size: size of buffer for indirect commands (0 for direct commands)
1335 * @cd: pointer to command details structure
1337 * Helper function to send FW Admin Queue commands to the FW Admin Queue.
1340 ice_aq_send_cmd(struct ice_hw *hw, struct ice_aq_desc *desc, void *buf,
1341 u16 buf_size, struct ice_sq_cd *cd)
1343 if (hw->aq_send_cmd_fn) {
1344 enum ice_status status = ICE_ERR_NOT_READY;
1345 u16 retval = ICE_AQ_RC_OK;
1347 ice_acquire_lock(&hw->adminq.sq_lock);
1348 if (!hw->aq_send_cmd_fn(hw->aq_send_cmd_param, desc,
1350 retval = LE16_TO_CPU(desc->retval);
1351 /* strip off FW internal code */
1354 if (retval == ICE_AQ_RC_OK)
1355 status = ICE_SUCCESS;
1357 status = ICE_ERR_AQ_ERROR;
1360 hw->adminq.sq_last_status = (enum ice_aq_err)retval;
1361 ice_release_lock(&hw->adminq.sq_lock);
1365 return ice_sq_send_cmd(hw, &hw->adminq, desc, buf, buf_size, cd);
1370 * @hw: pointer to the HW struct
1371 * @cd: pointer to command details structure or NULL
1373 * Get the firmware version (0x0001) from the admin queue commands
1375 enum ice_status ice_aq_get_fw_ver(struct ice_hw *hw, struct ice_sq_cd *cd)
1377 struct ice_aqc_get_ver *resp;
1378 struct ice_aq_desc desc;
1379 enum ice_status status;
1381 resp = &desc.params.get_ver;
1383 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_ver);
1385 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
1388 hw->fw_branch = resp->fw_branch;
1389 hw->fw_maj_ver = resp->fw_major;
1390 hw->fw_min_ver = resp->fw_minor;
1391 hw->fw_patch = resp->fw_patch;
1392 hw->fw_build = LE32_TO_CPU(resp->fw_build);
1393 hw->api_branch = resp->api_branch;
1394 hw->api_maj_ver = resp->api_major;
1395 hw->api_min_ver = resp->api_minor;
1396 hw->api_patch = resp->api_patch;
1403 * ice_aq_send_driver_ver
1404 * @hw: pointer to the HW struct
1405 * @dv: driver's major, minor version
1406 * @cd: pointer to command details structure or NULL
1408 * Send the driver version (0x0002) to the firmware
1411 ice_aq_send_driver_ver(struct ice_hw *hw, struct ice_driver_ver *dv,
1412 struct ice_sq_cd *cd)
1414 struct ice_aqc_driver_ver *cmd;
1415 struct ice_aq_desc desc;
1418 cmd = &desc.params.driver_ver;
1421 return ICE_ERR_PARAM;
1423 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_driver_ver);
1425 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
1426 cmd->major_ver = dv->major_ver;
1427 cmd->minor_ver = dv->minor_ver;
1428 cmd->build_ver = dv->build_ver;
1429 cmd->subbuild_ver = dv->subbuild_ver;
1432 while (len < sizeof(dv->driver_string) &&
1433 IS_ASCII(dv->driver_string[len]) && dv->driver_string[len])
1436 return ice_aq_send_cmd(hw, &desc, dv->driver_string, len, cd);
1441 * @hw: pointer to the HW struct
1442 * @unloading: is the driver unloading itself
1444 * Tell the Firmware that we're shutting down the AdminQ and whether
1445 * or not the driver is unloading as well (0x0003).
1447 enum ice_status ice_aq_q_shutdown(struct ice_hw *hw, bool unloading)
1449 struct ice_aqc_q_shutdown *cmd;
1450 struct ice_aq_desc desc;
1452 cmd = &desc.params.q_shutdown;
1454 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_q_shutdown);
1457 cmd->driver_unloading = ICE_AQC_DRIVER_UNLOADING;
1459 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
1464 * @hw: pointer to the HW struct
1466 * @access: access type
1467 * @sdp_number: resource number
1468 * @timeout: the maximum time in ms that the driver may hold the resource
1469 * @cd: pointer to command details structure or NULL
1471 * Requests common resource using the admin queue commands (0x0008).
1472 * When attempting to acquire the Global Config Lock, the driver can
1473 * learn of three states:
1474 * 1) ICE_SUCCESS - acquired lock, and can perform download package
1475 * 2) ICE_ERR_AQ_ERROR - did not get lock, driver should fail to load
1476 * 3) ICE_ERR_AQ_NO_WORK - did not get lock, but another driver has
1477 * successfully downloaded the package; the driver does
1478 * not have to download the package and can continue
1481 * Note that if the caller is in an acquire lock, perform action, release lock
1482 * phase of operation, it is possible that the FW may detect a timeout and issue
1483 * a CORER. In this case, the driver will receive a CORER interrupt and will
1484 * have to determine its cause. The calling thread that is handling this flow
1485 * will likely get an error propagated back to it indicating the Download
1486 * Package, Update Package or the Release Resource AQ commands timed out.
1488 static enum ice_status
1489 ice_aq_req_res(struct ice_hw *hw, enum ice_aq_res_ids res,
1490 enum ice_aq_res_access_type access, u8 sdp_number, u32 *timeout,
1491 struct ice_sq_cd *cd)
1493 struct ice_aqc_req_res *cmd_resp;
1494 struct ice_aq_desc desc;
1495 enum ice_status status;
1497 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
1499 cmd_resp = &desc.params.res_owner;
1501 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_req_res);
1503 cmd_resp->res_id = CPU_TO_LE16(res);
1504 cmd_resp->access_type = CPU_TO_LE16(access);
1505 cmd_resp->res_number = CPU_TO_LE32(sdp_number);
1506 cmd_resp->timeout = CPU_TO_LE32(*timeout);
1509 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
1511 /* The completion specifies the maximum time in ms that the driver
1512 * may hold the resource in the Timeout field.
1515 /* Global config lock response utilizes an additional status field.
1517 * If the Global config lock resource is held by some other driver, the
1518 * command completes with ICE_AQ_RES_GLBL_IN_PROG in the status field
1519 * and the timeout field indicates the maximum time the current owner
1520 * of the resource has to free it.
1522 if (res == ICE_GLOBAL_CFG_LOCK_RES_ID) {
1523 if (LE16_TO_CPU(cmd_resp->status) == ICE_AQ_RES_GLBL_SUCCESS) {
1524 *timeout = LE32_TO_CPU(cmd_resp->timeout);
1526 } else if (LE16_TO_CPU(cmd_resp->status) ==
1527 ICE_AQ_RES_GLBL_IN_PROG) {
1528 *timeout = LE32_TO_CPU(cmd_resp->timeout);
1529 return ICE_ERR_AQ_ERROR;
1530 } else if (LE16_TO_CPU(cmd_resp->status) ==
1531 ICE_AQ_RES_GLBL_DONE) {
1532 return ICE_ERR_AQ_NO_WORK;
1535 /* invalid FW response, force a timeout immediately */
1537 return ICE_ERR_AQ_ERROR;
1540 /* If the resource is held by some other driver, the command completes
1541 * with a busy return value and the timeout field indicates the maximum
1542 * time the current owner of the resource has to free it.
1544 if (!status || hw->adminq.sq_last_status == ICE_AQ_RC_EBUSY)
1545 *timeout = LE32_TO_CPU(cmd_resp->timeout);
1551 * ice_aq_release_res
1552 * @hw: pointer to the HW struct
1554 * @sdp_number: resource number
1555 * @cd: pointer to command details structure or NULL
1557 * release common resource using the admin queue commands (0x0009)
1559 static enum ice_status
1560 ice_aq_release_res(struct ice_hw *hw, enum ice_aq_res_ids res, u8 sdp_number,
1561 struct ice_sq_cd *cd)
1563 struct ice_aqc_req_res *cmd;
1564 struct ice_aq_desc desc;
1566 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
1568 cmd = &desc.params.res_owner;
1570 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_release_res);
1572 cmd->res_id = CPU_TO_LE16(res);
1573 cmd->res_number = CPU_TO_LE32(sdp_number);
1575 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
1580 * @hw: pointer to the HW structure
1582 * @access: access type (read or write)
1583 * @timeout: timeout in milliseconds
1585 * This function will attempt to acquire the ownership of a resource.
1588 ice_acquire_res(struct ice_hw *hw, enum ice_aq_res_ids res,
1589 enum ice_aq_res_access_type access, u32 timeout)
1591 #define ICE_RES_POLLING_DELAY_MS 10
1592 u32 delay = ICE_RES_POLLING_DELAY_MS;
1593 u32 time_left = timeout;
1594 enum ice_status status;
1596 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
1598 status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL);
1600 /* A return code of ICE_ERR_AQ_NO_WORK means that another driver has
1601 * previously acquired the resource and performed any necessary updates;
1602 * in this case the caller does not obtain the resource and has no
1603 * further work to do.
1605 if (status == ICE_ERR_AQ_NO_WORK)
1606 goto ice_acquire_res_exit;
1609 ice_debug(hw, ICE_DBG_RES,
1610 "resource %d acquire type %d failed.\n", res, access);
1612 /* If necessary, poll until the current lock owner timeouts */
1613 timeout = time_left;
1614 while (status && timeout && time_left) {
1615 ice_msec_delay(delay, true);
1616 timeout = (timeout > delay) ? timeout - delay : 0;
1617 status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL);
1619 if (status == ICE_ERR_AQ_NO_WORK)
1620 /* lock free, but no work to do */
1627 if (status && status != ICE_ERR_AQ_NO_WORK)
1628 ice_debug(hw, ICE_DBG_RES, "resource acquire timed out.\n");
1630 ice_acquire_res_exit:
1631 if (status == ICE_ERR_AQ_NO_WORK) {
1632 if (access == ICE_RES_WRITE)
1633 ice_debug(hw, ICE_DBG_RES,
1634 "resource indicates no work to do.\n");
1636 ice_debug(hw, ICE_DBG_RES,
1637 "Warning: ICE_ERR_AQ_NO_WORK not expected\n");
1644 * @hw: pointer to the HW structure
1647 * This function will release a resource using the proper Admin Command.
1649 void ice_release_res(struct ice_hw *hw, enum ice_aq_res_ids res)
1651 enum ice_status status;
1652 u32 total_delay = 0;
1654 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
1656 status = ice_aq_release_res(hw, res, 0, NULL);
1658 /* there are some rare cases when trying to release the resource
1659 * results in an admin queue timeout, so handle them correctly
1661 while ((status == ICE_ERR_AQ_TIMEOUT) &&
1662 (total_delay < hw->adminq.sq_cmd_timeout)) {
1663 ice_msec_delay(1, true);
1664 status = ice_aq_release_res(hw, res, 0, NULL);
1670 * ice_aq_alloc_free_res - command to allocate/free resources
1671 * @hw: pointer to the HW struct
1672 * @num_entries: number of resource entries in buffer
1673 * @buf: Indirect buffer to hold data parameters and response
1674 * @buf_size: size of buffer for indirect commands
1675 * @opc: pass in the command opcode
1676 * @cd: pointer to command details structure or NULL
1678 * Helper function to allocate/free resources using the admin queue commands
1681 ice_aq_alloc_free_res(struct ice_hw *hw, u16 num_entries,
1682 struct ice_aqc_alloc_free_res_elem *buf, u16 buf_size,
1683 enum ice_adminq_opc opc, struct ice_sq_cd *cd)
1685 struct ice_aqc_alloc_free_res_cmd *cmd;
1686 struct ice_aq_desc desc;
1688 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
1690 cmd = &desc.params.sw_res_ctrl;
1693 return ICE_ERR_PARAM;
1695 if (buf_size < (num_entries * sizeof(buf->elem[0])))
1696 return ICE_ERR_PARAM;
1698 ice_fill_dflt_direct_cmd_desc(&desc, opc);
1700 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
1702 cmd->num_entries = CPU_TO_LE16(num_entries);
1704 return ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);
1708 * ice_alloc_hw_res - allocate resource
1709 * @hw: pointer to the HW struct
1710 * @type: type of resource
1711 * @num: number of resources to allocate
1712 * @btm: allocate from bottom
1713 * @res: pointer to array that will receive the resources
1716 ice_alloc_hw_res(struct ice_hw *hw, u16 type, u16 num, bool btm, u16 *res)
1718 struct ice_aqc_alloc_free_res_elem *buf;
1719 enum ice_status status;
1722 buf_len = ice_struct_size(buf, elem, num - 1);
1723 buf = (struct ice_aqc_alloc_free_res_elem *)
1724 ice_malloc(hw, buf_len);
1726 return ICE_ERR_NO_MEMORY;
1728 /* Prepare buffer to allocate resource. */
1729 buf->num_elems = CPU_TO_LE16(num);
1730 buf->res_type = CPU_TO_LE16(type | ICE_AQC_RES_TYPE_FLAG_DEDICATED |
1731 ICE_AQC_RES_TYPE_FLAG_IGNORE_INDEX);
1733 buf->res_type |= CPU_TO_LE16(ICE_AQC_RES_TYPE_FLAG_SCAN_BOTTOM);
1735 status = ice_aq_alloc_free_res(hw, 1, buf, buf_len,
1736 ice_aqc_opc_alloc_res, NULL);
1738 goto ice_alloc_res_exit;
1740 ice_memcpy(res, buf->elem, sizeof(buf->elem) * num,
1741 ICE_NONDMA_TO_NONDMA);
1749 * ice_free_hw_res - free allocated HW resource
1750 * @hw: pointer to the HW struct
1751 * @type: type of resource to free
1752 * @num: number of resources
1753 * @res: pointer to array that contains the resources to free
1755 enum ice_status ice_free_hw_res(struct ice_hw *hw, u16 type, u16 num, u16 *res)
1757 struct ice_aqc_alloc_free_res_elem *buf;
1758 enum ice_status status;
1761 buf_len = ice_struct_size(buf, elem, num - 1);
1762 buf = (struct ice_aqc_alloc_free_res_elem *)ice_malloc(hw, buf_len);
1764 return ICE_ERR_NO_MEMORY;
1766 /* Prepare buffer to free resource. */
1767 buf->num_elems = CPU_TO_LE16(num);
1768 buf->res_type = CPU_TO_LE16(type);
1769 ice_memcpy(buf->elem, res, sizeof(buf->elem) * num,
1770 ICE_NONDMA_TO_NONDMA);
1772 status = ice_aq_alloc_free_res(hw, num, buf, buf_len,
1773 ice_aqc_opc_free_res, NULL);
1775 ice_debug(hw, ICE_DBG_SW, "CQ CMD Buffer:\n");
1782 * ice_get_num_per_func - determine number of resources per PF
1783 * @hw: pointer to the HW structure
1784 * @max: value to be evenly split between each PF
1786 * Determine the number of valid functions by going through the bitmap returned
1787 * from parsing capabilities and use this to calculate the number of resources
1788 * per PF based on the max value passed in.
1790 static u32 ice_get_num_per_func(struct ice_hw *hw, u32 max)
1794 #define ICE_CAPS_VALID_FUNCS_M 0xFF
1795 funcs = ice_hweight8(hw->dev_caps.common_cap.valid_functions &
1796 ICE_CAPS_VALID_FUNCS_M);
1805 * ice_parse_caps - parse function/device capabilities
1806 * @hw: pointer to the HW struct
1807 * @buf: pointer to a buffer containing function/device capability records
1808 * @cap_count: number of capability records in the list
1809 * @opc: type of capabilities list to parse
1811 * Helper function to parse function(0x000a)/device(0x000b) capabilities list.
1814 ice_parse_caps(struct ice_hw *hw, void *buf, u32 cap_count,
1815 enum ice_adminq_opc opc)
1817 struct ice_aqc_list_caps_elem *cap_resp;
1818 struct ice_hw_func_caps *func_p = NULL;
1819 struct ice_hw_dev_caps *dev_p = NULL;
1820 struct ice_hw_common_caps *caps;
1827 cap_resp = (struct ice_aqc_list_caps_elem *)buf;
1829 if (opc == ice_aqc_opc_list_dev_caps) {
1830 dev_p = &hw->dev_caps;
1831 caps = &dev_p->common_cap;
1833 ice_memset(dev_p, 0, sizeof(*dev_p), ICE_NONDMA_MEM);
1836 } else if (opc == ice_aqc_opc_list_func_caps) {
1837 func_p = &hw->func_caps;
1838 caps = &func_p->common_cap;
1840 ice_memset(func_p, 0, sizeof(*func_p), ICE_NONDMA_MEM);
1842 prefix = "func cap";
1844 ice_debug(hw, ICE_DBG_INIT, "wrong opcode\n");
1848 for (i = 0; caps && i < cap_count; i++, cap_resp++) {
1849 u32 logical_id = LE32_TO_CPU(cap_resp->logical_id);
1850 u32 phys_id = LE32_TO_CPU(cap_resp->phys_id);
1851 u32 number = LE32_TO_CPU(cap_resp->number);
1852 u16 cap = LE16_TO_CPU(cap_resp->cap);
1855 case ICE_AQC_CAPS_VALID_FUNCTIONS:
1856 caps->valid_functions = number;
1857 ice_debug(hw, ICE_DBG_INIT,
1858 "%s: valid_functions (bitmap) = %d\n", prefix,
1859 caps->valid_functions);
1861 /* store func count for resource management purposes */
1863 dev_p->num_funcs = ice_hweight32(number);
1865 case ICE_AQC_CAPS_VSI:
1867 dev_p->num_vsi_allocd_to_host = number;
1868 ice_debug(hw, ICE_DBG_INIT,
1869 "%s: num_vsi_allocd_to_host = %d\n",
1871 dev_p->num_vsi_allocd_to_host);
1872 } else if (func_p) {
1873 func_p->guar_num_vsi =
1874 ice_get_num_per_func(hw, ICE_MAX_VSI);
1875 ice_debug(hw, ICE_DBG_INIT,
1876 "%s: guar_num_vsi (fw) = %d\n",
1878 ice_debug(hw, ICE_DBG_INIT,
1879 "%s: guar_num_vsi = %d\n",
1880 prefix, func_p->guar_num_vsi);
1883 case ICE_AQC_CAPS_DCB:
1884 caps->dcb = (number == 1);
1885 caps->active_tc_bitmap = logical_id;
1886 caps->maxtc = phys_id;
1887 ice_debug(hw, ICE_DBG_INIT,
1888 "%s: dcb = %d\n", prefix, caps->dcb);
1889 ice_debug(hw, ICE_DBG_INIT,
1890 "%s: active_tc_bitmap = %d\n", prefix,
1891 caps->active_tc_bitmap);
1892 ice_debug(hw, ICE_DBG_INIT,
1893 "%s: maxtc = %d\n", prefix, caps->maxtc);
1895 case ICE_AQC_CAPS_RSS:
1896 caps->rss_table_size = number;
1897 caps->rss_table_entry_width = logical_id;
1898 ice_debug(hw, ICE_DBG_INIT,
1899 "%s: rss_table_size = %d\n", prefix,
1900 caps->rss_table_size);
1901 ice_debug(hw, ICE_DBG_INIT,
1902 "%s: rss_table_entry_width = %d\n", prefix,
1903 caps->rss_table_entry_width);
1905 case ICE_AQC_CAPS_RXQS:
1906 caps->num_rxq = number;
1907 caps->rxq_first_id = phys_id;
1908 ice_debug(hw, ICE_DBG_INIT,
1909 "%s: num_rxq = %d\n", prefix,
1911 ice_debug(hw, ICE_DBG_INIT,
1912 "%s: rxq_first_id = %d\n", prefix,
1913 caps->rxq_first_id);
1915 case ICE_AQC_CAPS_TXQS:
1916 caps->num_txq = number;
1917 caps->txq_first_id = phys_id;
1918 ice_debug(hw, ICE_DBG_INIT,
1919 "%s: num_txq = %d\n", prefix,
1921 ice_debug(hw, ICE_DBG_INIT,
1922 "%s: txq_first_id = %d\n", prefix,
1923 caps->txq_first_id);
1925 case ICE_AQC_CAPS_MSIX:
1926 caps->num_msix_vectors = number;
1927 caps->msix_vector_first_id = phys_id;
1928 ice_debug(hw, ICE_DBG_INIT,
1929 "%s: num_msix_vectors = %d\n", prefix,
1930 caps->num_msix_vectors);
1931 ice_debug(hw, ICE_DBG_INIT,
1932 "%s: msix_vector_first_id = %d\n", prefix,
1933 caps->msix_vector_first_id);
1935 case ICE_AQC_CAPS_FD:
1937 dev_p->num_flow_director_fltr = number;
1938 ice_debug(hw, ICE_DBG_INIT,
1939 "%s: num_flow_director_fltr = %d\n",
1941 dev_p->num_flow_director_fltr);
1946 if (hw->dcf_enabled)
1948 reg_val = rd32(hw, GLQF_FD_SIZE);
1949 val = (reg_val & GLQF_FD_SIZE_FD_GSIZE_M) >>
1950 GLQF_FD_SIZE_FD_GSIZE_S;
1951 func_p->fd_fltr_guar =
1952 ice_get_num_per_func(hw, val);
1953 val = (reg_val & GLQF_FD_SIZE_FD_BSIZE_M) >>
1954 GLQF_FD_SIZE_FD_BSIZE_S;
1955 func_p->fd_fltr_best_effort = val;
1956 ice_debug(hw, ICE_DBG_INIT,
1957 "%s: fd_fltr_guar = %d\n",
1958 prefix, func_p->fd_fltr_guar);
1959 ice_debug(hw, ICE_DBG_INIT,
1960 "%s: fd_fltr_best_effort = %d\n",
1961 prefix, func_p->fd_fltr_best_effort);
1964 case ICE_AQC_CAPS_MAX_MTU:
1965 caps->max_mtu = number;
1966 ice_debug(hw, ICE_DBG_INIT, "%s: max_mtu = %d\n",
1967 prefix, caps->max_mtu);
1970 ice_debug(hw, ICE_DBG_INIT,
1971 "%s: unknown capability[%d]: 0x%x\n", prefix,
1977 /* Re-calculate capabilities that are dependent on the number of
1978 * physical ports; i.e. some features are not supported or function
1979 * differently on devices with more than 4 ports.
1981 if (hw->dev_caps.num_funcs > 4) {
1982 /* Max 4 TCs per port */
1984 ice_debug(hw, ICE_DBG_INIT,
1985 "%s: maxtc = %d (based on #ports)\n", prefix,
1991 * ice_aq_discover_caps - query function/device capabilities
1992 * @hw: pointer to the HW struct
1993 * @buf: a virtual buffer to hold the capabilities
1994 * @buf_size: Size of the virtual buffer
1995 * @cap_count: cap count needed if AQ err==ENOMEM
1996 * @opc: capabilities type to discover - pass in the command opcode
1997 * @cd: pointer to command details structure or NULL
1999 * Get the function(0x000a)/device(0x000b) capabilities description from
2002 static enum ice_status
2003 ice_aq_discover_caps(struct ice_hw *hw, void *buf, u16 buf_size, u32 *cap_count,
2004 enum ice_adminq_opc opc, struct ice_sq_cd *cd)
2006 struct ice_aqc_list_caps *cmd;
2007 struct ice_aq_desc desc;
2008 enum ice_status status;
2010 cmd = &desc.params.get_cap;
2012 if (opc != ice_aqc_opc_list_func_caps &&
2013 opc != ice_aqc_opc_list_dev_caps)
2014 return ICE_ERR_PARAM;
2016 ice_fill_dflt_direct_cmd_desc(&desc, opc);
2018 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);
2020 ice_parse_caps(hw, buf, LE32_TO_CPU(cmd->count), opc);
2021 else if (hw->adminq.sq_last_status == ICE_AQ_RC_ENOMEM)
2022 *cap_count = LE32_TO_CPU(cmd->count);
2027 * ice_discover_caps - get info about the HW
2028 * @hw: pointer to the hardware structure
2029 * @opc: capabilities type to discover - pass in the command opcode
2031 static enum ice_status
2032 ice_discover_caps(struct ice_hw *hw, enum ice_adminq_opc opc)
2034 enum ice_status status;
2039 /* The driver doesn't know how many capabilities the device will return
2040 * so the buffer size required isn't known ahead of time. The driver
2041 * starts with cbuf_len and if this turns out to be insufficient, the
2042 * device returns ICE_AQ_RC_ENOMEM and also the cap_count it needs.
2043 * The driver then allocates the buffer based on the count and retries
2044 * the operation. So it follows that the retry count is 2.
2046 #define ICE_GET_CAP_BUF_COUNT 40
2047 #define ICE_GET_CAP_RETRY_COUNT 2
2049 cap_count = ICE_GET_CAP_BUF_COUNT;
2050 retries = ICE_GET_CAP_RETRY_COUNT;
2055 cbuf_len = (u16)(cap_count *
2056 sizeof(struct ice_aqc_list_caps_elem));
2057 cbuf = ice_malloc(hw, cbuf_len);
2059 return ICE_ERR_NO_MEMORY;
2061 status = ice_aq_discover_caps(hw, cbuf, cbuf_len, &cap_count,
2065 if (!status || hw->adminq.sq_last_status != ICE_AQ_RC_ENOMEM)
2068 /* If ENOMEM is returned, try again with bigger buffer */
2069 } while (--retries);
2075 * ice_set_safe_mode_caps - Override dev/func capabilities when in safe mode
2076 * @hw: pointer to the hardware structure
2078 void ice_set_safe_mode_caps(struct ice_hw *hw)
2080 struct ice_hw_func_caps *func_caps = &hw->func_caps;
2081 struct ice_hw_dev_caps *dev_caps = &hw->dev_caps;
2082 u32 valid_func, rxq_first_id, txq_first_id;
2083 u32 msix_vector_first_id, max_mtu;
2086 /* cache some func_caps values that should be restored after memset */
2087 valid_func = func_caps->common_cap.valid_functions;
2088 txq_first_id = func_caps->common_cap.txq_first_id;
2089 rxq_first_id = func_caps->common_cap.rxq_first_id;
2090 msix_vector_first_id = func_caps->common_cap.msix_vector_first_id;
2091 max_mtu = func_caps->common_cap.max_mtu;
2093 /* unset func capabilities */
2094 memset(func_caps, 0, sizeof(*func_caps));
2096 /* restore cached values */
2097 func_caps->common_cap.valid_functions = valid_func;
2098 func_caps->common_cap.txq_first_id = txq_first_id;
2099 func_caps->common_cap.rxq_first_id = rxq_first_id;
2100 func_caps->common_cap.msix_vector_first_id = msix_vector_first_id;
2101 func_caps->common_cap.max_mtu = max_mtu;
2103 /* one Tx and one Rx queue in safe mode */
2104 func_caps->common_cap.num_rxq = 1;
2105 func_caps->common_cap.num_txq = 1;
2107 /* two MSIX vectors, one for traffic and one for misc causes */
2108 func_caps->common_cap.num_msix_vectors = 2;
2109 func_caps->guar_num_vsi = 1;
2111 /* cache some dev_caps values that should be restored after memset */
2112 valid_func = dev_caps->common_cap.valid_functions;
2113 txq_first_id = dev_caps->common_cap.txq_first_id;
2114 rxq_first_id = dev_caps->common_cap.rxq_first_id;
2115 msix_vector_first_id = dev_caps->common_cap.msix_vector_first_id;
2116 max_mtu = dev_caps->common_cap.max_mtu;
2117 num_funcs = dev_caps->num_funcs;
2119 /* unset dev capabilities */
2120 memset(dev_caps, 0, sizeof(*dev_caps));
2122 /* restore cached values */
2123 dev_caps->common_cap.valid_functions = valid_func;
2124 dev_caps->common_cap.txq_first_id = txq_first_id;
2125 dev_caps->common_cap.rxq_first_id = rxq_first_id;
2126 dev_caps->common_cap.msix_vector_first_id = msix_vector_first_id;
2127 dev_caps->common_cap.max_mtu = max_mtu;
2128 dev_caps->num_funcs = num_funcs;
2130 /* one Tx and one Rx queue per function in safe mode */
2131 dev_caps->common_cap.num_rxq = num_funcs;
2132 dev_caps->common_cap.num_txq = num_funcs;
2134 /* two MSIX vectors per function */
2135 dev_caps->common_cap.num_msix_vectors = 2 * num_funcs;
2139 * ice_get_caps - get info about the HW
2140 * @hw: pointer to the hardware structure
2142 enum ice_status ice_get_caps(struct ice_hw *hw)
2144 enum ice_status status;
2146 status = ice_discover_caps(hw, ice_aqc_opc_list_dev_caps);
2148 status = ice_discover_caps(hw, ice_aqc_opc_list_func_caps);
2154 * ice_aq_manage_mac_write - manage MAC address write command
2155 * @hw: pointer to the HW struct
2156 * @mac_addr: MAC address to be written as LAA/LAA+WoL/Port address
2157 * @flags: flags to control write behavior
2158 * @cd: pointer to command details structure or NULL
2160 * This function is used to write MAC address to the NVM (0x0108).
2163 ice_aq_manage_mac_write(struct ice_hw *hw, const u8 *mac_addr, u8 flags,
2164 struct ice_sq_cd *cd)
2166 struct ice_aqc_manage_mac_write *cmd;
2167 struct ice_aq_desc desc;
2169 cmd = &desc.params.mac_write;
2170 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_write);
2173 ice_memcpy(cmd->mac_addr, mac_addr, ETH_ALEN, ICE_NONDMA_TO_DMA);
2175 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
2179 * ice_aq_clear_pxe_mode
2180 * @hw: pointer to the HW struct
2182 * Tell the firmware that the driver is taking over from PXE (0x0110).
2184 static enum ice_status ice_aq_clear_pxe_mode(struct ice_hw *hw)
2186 struct ice_aq_desc desc;
2188 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pxe_mode);
2189 desc.params.clear_pxe.rx_cnt = ICE_AQC_CLEAR_PXE_RX_CNT;
2191 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
2195 * ice_clear_pxe_mode - clear pxe operations mode
2196 * @hw: pointer to the HW struct
2198 * Make sure all PXE mode settings are cleared, including things
2199 * like descriptor fetch/write-back mode.
2201 void ice_clear_pxe_mode(struct ice_hw *hw)
2203 if (ice_check_sq_alive(hw, &hw->adminq))
2204 ice_aq_clear_pxe_mode(hw);
2208 * ice_get_link_speed_based_on_phy_type - returns link speed
2209 * @phy_type_low: lower part of phy_type
2210 * @phy_type_high: higher part of phy_type
2212 * This helper function will convert an entry in PHY type structure
2213 * [phy_type_low, phy_type_high] to its corresponding link speed.
2214 * Note: In the structure of [phy_type_low, phy_type_high], there should
2215 * be one bit set, as this function will convert one PHY type to its
2217 * If no bit gets set, ICE_LINK_SPEED_UNKNOWN will be returned
2218 * If more than one bit gets set, ICE_LINK_SPEED_UNKNOWN will be returned
2221 ice_get_link_speed_based_on_phy_type(u64 phy_type_low, u64 phy_type_high)
2223 u16 speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN;
2224 u16 speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN;
2226 switch (phy_type_low) {
2227 case ICE_PHY_TYPE_LOW_100BASE_TX:
2228 case ICE_PHY_TYPE_LOW_100M_SGMII:
2229 speed_phy_type_low = ICE_AQ_LINK_SPEED_100MB;
2231 case ICE_PHY_TYPE_LOW_1000BASE_T:
2232 case ICE_PHY_TYPE_LOW_1000BASE_SX:
2233 case ICE_PHY_TYPE_LOW_1000BASE_LX:
2234 case ICE_PHY_TYPE_LOW_1000BASE_KX:
2235 case ICE_PHY_TYPE_LOW_1G_SGMII:
2236 speed_phy_type_low = ICE_AQ_LINK_SPEED_1000MB;
2238 case ICE_PHY_TYPE_LOW_2500BASE_T:
2239 case ICE_PHY_TYPE_LOW_2500BASE_X:
2240 case ICE_PHY_TYPE_LOW_2500BASE_KX:
2241 speed_phy_type_low = ICE_AQ_LINK_SPEED_2500MB;
2243 case ICE_PHY_TYPE_LOW_5GBASE_T:
2244 case ICE_PHY_TYPE_LOW_5GBASE_KR:
2245 speed_phy_type_low = ICE_AQ_LINK_SPEED_5GB;
2247 case ICE_PHY_TYPE_LOW_10GBASE_T:
2248 case ICE_PHY_TYPE_LOW_10G_SFI_DA:
2249 case ICE_PHY_TYPE_LOW_10GBASE_SR:
2250 case ICE_PHY_TYPE_LOW_10GBASE_LR:
2251 case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1:
2252 case ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC:
2253 case ICE_PHY_TYPE_LOW_10G_SFI_C2C:
2254 speed_phy_type_low = ICE_AQ_LINK_SPEED_10GB;
2256 case ICE_PHY_TYPE_LOW_25GBASE_T:
2257 case ICE_PHY_TYPE_LOW_25GBASE_CR:
2258 case ICE_PHY_TYPE_LOW_25GBASE_CR_S:
2259 case ICE_PHY_TYPE_LOW_25GBASE_CR1:
2260 case ICE_PHY_TYPE_LOW_25GBASE_SR:
2261 case ICE_PHY_TYPE_LOW_25GBASE_LR:
2262 case ICE_PHY_TYPE_LOW_25GBASE_KR:
2263 case ICE_PHY_TYPE_LOW_25GBASE_KR_S:
2264 case ICE_PHY_TYPE_LOW_25GBASE_KR1:
2265 case ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC:
2266 case ICE_PHY_TYPE_LOW_25G_AUI_C2C:
2267 speed_phy_type_low = ICE_AQ_LINK_SPEED_25GB;
2269 case ICE_PHY_TYPE_LOW_40GBASE_CR4:
2270 case ICE_PHY_TYPE_LOW_40GBASE_SR4:
2271 case ICE_PHY_TYPE_LOW_40GBASE_LR4:
2272 case ICE_PHY_TYPE_LOW_40GBASE_KR4:
2273 case ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC:
2274 case ICE_PHY_TYPE_LOW_40G_XLAUI:
2275 speed_phy_type_low = ICE_AQ_LINK_SPEED_40GB;
2277 case ICE_PHY_TYPE_LOW_50GBASE_CR2:
2278 case ICE_PHY_TYPE_LOW_50GBASE_SR2:
2279 case ICE_PHY_TYPE_LOW_50GBASE_LR2:
2280 case ICE_PHY_TYPE_LOW_50GBASE_KR2:
2281 case ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC:
2282 case ICE_PHY_TYPE_LOW_50G_LAUI2:
2283 case ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC:
2284 case ICE_PHY_TYPE_LOW_50G_AUI2:
2285 case ICE_PHY_TYPE_LOW_50GBASE_CP:
2286 case ICE_PHY_TYPE_LOW_50GBASE_SR:
2287 case ICE_PHY_TYPE_LOW_50GBASE_FR:
2288 case ICE_PHY_TYPE_LOW_50GBASE_LR:
2289 case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4:
2290 case ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC:
2291 case ICE_PHY_TYPE_LOW_50G_AUI1:
2292 speed_phy_type_low = ICE_AQ_LINK_SPEED_50GB;
2294 case ICE_PHY_TYPE_LOW_100GBASE_CR4:
2295 case ICE_PHY_TYPE_LOW_100GBASE_SR4:
2296 case ICE_PHY_TYPE_LOW_100GBASE_LR4:
2297 case ICE_PHY_TYPE_LOW_100GBASE_KR4:
2298 case ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC:
2299 case ICE_PHY_TYPE_LOW_100G_CAUI4:
2300 case ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC:
2301 case ICE_PHY_TYPE_LOW_100G_AUI4:
2302 case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4:
2303 case ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4:
2304 case ICE_PHY_TYPE_LOW_100GBASE_CP2:
2305 case ICE_PHY_TYPE_LOW_100GBASE_SR2:
2306 case ICE_PHY_TYPE_LOW_100GBASE_DR:
2307 speed_phy_type_low = ICE_AQ_LINK_SPEED_100GB;
2310 speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN;
2314 switch (phy_type_high) {
2315 case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4:
2316 case ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC:
2317 case ICE_PHY_TYPE_HIGH_100G_CAUI2:
2318 case ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC:
2319 case ICE_PHY_TYPE_HIGH_100G_AUI2:
2320 speed_phy_type_high = ICE_AQ_LINK_SPEED_100GB;
2323 speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN;
2327 if (speed_phy_type_low == ICE_AQ_LINK_SPEED_UNKNOWN &&
2328 speed_phy_type_high == ICE_AQ_LINK_SPEED_UNKNOWN)
2329 return ICE_AQ_LINK_SPEED_UNKNOWN;
2330 else if (speed_phy_type_low != ICE_AQ_LINK_SPEED_UNKNOWN &&
2331 speed_phy_type_high != ICE_AQ_LINK_SPEED_UNKNOWN)
2332 return ICE_AQ_LINK_SPEED_UNKNOWN;
2333 else if (speed_phy_type_low != ICE_AQ_LINK_SPEED_UNKNOWN &&
2334 speed_phy_type_high == ICE_AQ_LINK_SPEED_UNKNOWN)
2335 return speed_phy_type_low;
2337 return speed_phy_type_high;
2341 * ice_update_phy_type
2342 * @phy_type_low: pointer to the lower part of phy_type
2343 * @phy_type_high: pointer to the higher part of phy_type
2344 * @link_speeds_bitmap: targeted link speeds bitmap
2346 * Note: For the link_speeds_bitmap structure, you can check it at
2347 * [ice_aqc_get_link_status->link_speed]. Caller can pass in
2348 * link_speeds_bitmap include multiple speeds.
2350 * Each entry in this [phy_type_low, phy_type_high] structure will
2351 * present a certain link speed. This helper function will turn on bits
2352 * in [phy_type_low, phy_type_high] structure based on the value of
2353 * link_speeds_bitmap input parameter.
2356 ice_update_phy_type(u64 *phy_type_low, u64 *phy_type_high,
2357 u16 link_speeds_bitmap)
2364 /* We first check with low part of phy_type */
2365 for (index = 0; index <= ICE_PHY_TYPE_LOW_MAX_INDEX; index++) {
2366 pt_low = BIT_ULL(index);
2367 speed = ice_get_link_speed_based_on_phy_type(pt_low, 0);
2369 if (link_speeds_bitmap & speed)
2370 *phy_type_low |= BIT_ULL(index);
2373 /* We then check with high part of phy_type */
2374 for (index = 0; index <= ICE_PHY_TYPE_HIGH_MAX_INDEX; index++) {
2375 pt_high = BIT_ULL(index);
2376 speed = ice_get_link_speed_based_on_phy_type(0, pt_high);
2378 if (link_speeds_bitmap & speed)
2379 *phy_type_high |= BIT_ULL(index);
2384 * ice_aq_set_phy_cfg
2385 * @hw: pointer to the HW struct
2386 * @pi: port info structure of the interested logical port
2387 * @cfg: structure with PHY configuration data to be set
2388 * @cd: pointer to command details structure or NULL
2390 * Set the various PHY configuration parameters supported on the Port.
2391 * One or more of the Set PHY config parameters may be ignored in an MFP
2392 * mode as the PF may not have the privilege to set some of the PHY Config
2393 * parameters. This status will be indicated by the command response (0x0601).
2396 ice_aq_set_phy_cfg(struct ice_hw *hw, struct ice_port_info *pi,
2397 struct ice_aqc_set_phy_cfg_data *cfg, struct ice_sq_cd *cd)
2399 struct ice_aq_desc desc;
2400 enum ice_status status;
2403 return ICE_ERR_PARAM;
2405 /* Ensure that only valid bits of cfg->caps can be turned on. */
2406 if (cfg->caps & ~ICE_AQ_PHY_ENA_VALID_MASK) {
2407 ice_debug(hw, ICE_DBG_PHY,
2408 "Invalid bit is set in ice_aqc_set_phy_cfg_data->caps : 0x%x\n",
2411 cfg->caps &= ICE_AQ_PHY_ENA_VALID_MASK;
2414 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_phy_cfg);
2415 desc.params.set_phy.lport_num = pi->lport;
2416 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
2418 ice_debug(hw, ICE_DBG_LINK, "set phy cfg\n");
2419 ice_debug(hw, ICE_DBG_LINK, " phy_type_low = 0x%llx\n",
2420 (unsigned long long)LE64_TO_CPU(cfg->phy_type_low));
2421 ice_debug(hw, ICE_DBG_LINK, " phy_type_high = 0x%llx\n",
2422 (unsigned long long)LE64_TO_CPU(cfg->phy_type_high));
2423 ice_debug(hw, ICE_DBG_LINK, " caps = 0x%x\n", cfg->caps);
2424 ice_debug(hw, ICE_DBG_LINK, " low_power_ctrl_an = 0x%x\n",
2425 cfg->low_power_ctrl_an);
2426 ice_debug(hw, ICE_DBG_LINK, " eee_cap = 0x%x\n", cfg->eee_cap);
2427 ice_debug(hw, ICE_DBG_LINK, " eeer_value = 0x%x\n", cfg->eeer_value);
2428 ice_debug(hw, ICE_DBG_LINK, " link_fec_opt = 0x%x\n",
2431 status = ice_aq_send_cmd(hw, &desc, cfg, sizeof(*cfg), cd);
2433 if (hw->adminq.sq_last_status == ICE_AQ_RC_EMODE)
2434 status = ICE_SUCCESS;
2437 pi->phy.curr_user_phy_cfg = *cfg;
2443 * ice_update_link_info - update status of the HW network link
2444 * @pi: port info structure of the interested logical port
2446 enum ice_status ice_update_link_info(struct ice_port_info *pi)
2448 struct ice_link_status *li;
2449 enum ice_status status;
2452 return ICE_ERR_PARAM;
2454 li = &pi->phy.link_info;
2456 status = ice_aq_get_link_info(pi, true, NULL, NULL);
2460 if (li->link_info & ICE_AQ_MEDIA_AVAILABLE) {
2461 struct ice_aqc_get_phy_caps_data *pcaps;
2465 pcaps = (struct ice_aqc_get_phy_caps_data *)
2466 ice_malloc(hw, sizeof(*pcaps));
2468 return ICE_ERR_NO_MEMORY;
2470 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_TOPO_CAP,
2472 if (status == ICE_SUCCESS)
2473 ice_memcpy(li->module_type, &pcaps->module_type,
2474 sizeof(li->module_type),
2475 ICE_NONDMA_TO_NONDMA);
2477 ice_free(hw, pcaps);
2484 * ice_cache_phy_user_req
2485 * @pi: port information structure
2486 * @cache_data: PHY logging data
2487 * @cache_mode: PHY logging mode
2489 * Log the user request on (FC, FEC, SPEED) for later user.
2492 ice_cache_phy_user_req(struct ice_port_info *pi,
2493 struct ice_phy_cache_mode_data cache_data,
2494 enum ice_phy_cache_mode cache_mode)
2499 switch (cache_mode) {
2501 pi->phy.curr_user_fc_req = cache_data.data.curr_user_fc_req;
2503 case ICE_SPEED_MODE:
2504 pi->phy.curr_user_speed_req =
2505 cache_data.data.curr_user_speed_req;
2508 pi->phy.curr_user_fec_req = cache_data.data.curr_user_fec_req;
2516 * ice_caps_to_fc_mode
2517 * @caps: PHY capabilities
2519 * Convert PHY FC capabilities to ice FC mode
2521 enum ice_fc_mode ice_caps_to_fc_mode(u8 caps)
2523 if (caps & ICE_AQC_PHY_EN_TX_LINK_PAUSE &&
2524 caps & ICE_AQC_PHY_EN_RX_LINK_PAUSE)
2527 if (caps & ICE_AQC_PHY_EN_TX_LINK_PAUSE)
2528 return ICE_FC_TX_PAUSE;
2530 if (caps & ICE_AQC_PHY_EN_RX_LINK_PAUSE)
2531 return ICE_FC_RX_PAUSE;
2537 * ice_caps_to_fec_mode
2538 * @caps: PHY capabilities
2539 * @fec_options: Link FEC options
2541 * Convert PHY FEC capabilities to ice FEC mode
2543 enum ice_fec_mode ice_caps_to_fec_mode(u8 caps, u8 fec_options)
2545 if (caps & ICE_AQC_PHY_EN_AUTO_FEC)
2546 return ICE_FEC_AUTO;
2548 if (fec_options & (ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN |
2549 ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ |
2550 ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN |
2551 ICE_AQC_PHY_FEC_25G_KR_REQ))
2552 return ICE_FEC_BASER;
2554 if (fec_options & (ICE_AQC_PHY_FEC_25G_RS_528_REQ |
2555 ICE_AQC_PHY_FEC_25G_RS_544_REQ |
2556 ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN))
2559 return ICE_FEC_NONE;
2562 static enum ice_status
2563 ice_cfg_phy_fc(struct ice_port_info *pi, struct ice_aqc_set_phy_cfg_data *cfg,
2564 enum ice_fc_mode req_mode)
2566 struct ice_aqc_get_phy_caps_data *pcaps = NULL;
2567 struct ice_phy_cache_mode_data cache_data;
2568 enum ice_status status = ICE_SUCCESS;
2569 u8 pause_mask = 0x0;
2572 return ICE_ERR_BAD_PTR;
2574 pcaps = (struct ice_aqc_get_phy_caps_data *)
2575 ice_malloc(pi->hw, sizeof(*pcaps));
2577 return ICE_ERR_NO_MEMORY;
2579 /* Cache user FC request */
2580 cache_data.data.curr_user_fc_req = req_mode;
2581 ice_cache_phy_user_req(pi, cache_data, ICE_FC_MODE);
2585 /* Query the value of FC that both the NIC and attached media
2588 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_TOPO_CAP,
2593 pause_mask |= pcaps->caps & ICE_AQC_PHY_EN_TX_LINK_PAUSE;
2594 pause_mask |= pcaps->caps & ICE_AQC_PHY_EN_RX_LINK_PAUSE;
2597 pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE;
2598 pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE;
2600 case ICE_FC_RX_PAUSE:
2601 pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE;
2603 case ICE_FC_TX_PAUSE:
2604 pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE;
2610 /* clear the old pause settings */
2611 cfg->caps &= ~(ICE_AQC_PHY_EN_TX_LINK_PAUSE |
2612 ICE_AQC_PHY_EN_RX_LINK_PAUSE);
2614 /* set the new capabilities */
2615 cfg->caps |= pause_mask;
2618 ice_free(pi->hw, pcaps);
2624 * @pi: port information structure
2625 * @aq_failures: pointer to status code, specific to ice_set_fc routine
2626 * @ena_auto_link_update: enable automatic link update
2628 * Set the requested flow control mode.
2631 ice_set_fc(struct ice_port_info *pi, u8 *aq_failures, bool ena_auto_link_update)
2633 struct ice_aqc_set_phy_cfg_data cfg = { 0 };
2634 struct ice_aqc_get_phy_caps_data *pcaps;
2635 enum ice_status status;
2638 if (!pi || !aq_failures)
2639 return ICE_ERR_BAD_PTR;
2644 pcaps = (struct ice_aqc_get_phy_caps_data *)
2645 ice_malloc(hw, sizeof(*pcaps));
2647 return ICE_ERR_NO_MEMORY;
2649 /* Get the current PHY config */
2650 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_SW_CFG, pcaps,
2653 *aq_failures = ICE_SET_FC_AQ_FAIL_GET;
2657 ice_copy_phy_caps_to_cfg(pi, pcaps, &cfg);
2659 /* Configure the set PHY data */
2660 status = ice_cfg_phy_fc(pi, &cfg, pi->fc.req_mode);
2662 if (status != ICE_ERR_BAD_PTR)
2663 *aq_failures = ICE_SET_FC_AQ_FAIL_GET;
2668 /* If the capabilities have changed, then set the new config */
2669 if (cfg.caps != pcaps->caps) {
2670 int retry_count, retry_max = 10;
2672 /* Auto restart link so settings take effect */
2673 if (ena_auto_link_update)
2674 cfg.caps |= ICE_AQ_PHY_ENA_AUTO_LINK_UPDT;
2676 status = ice_aq_set_phy_cfg(hw, pi, &cfg, NULL);
2678 *aq_failures = ICE_SET_FC_AQ_FAIL_SET;
2682 /* Update the link info
2683 * It sometimes takes a really long time for link to
2684 * come back from the atomic reset. Thus, we wait a
2687 for (retry_count = 0; retry_count < retry_max; retry_count++) {
2688 status = ice_update_link_info(pi);
2690 if (status == ICE_SUCCESS)
2693 ice_msec_delay(100, true);
2697 *aq_failures = ICE_SET_FC_AQ_FAIL_UPDATE;
2701 ice_free(hw, pcaps);
2706 * ice_phy_caps_equals_cfg
2707 * @phy_caps: PHY capabilities
2708 * @phy_cfg: PHY configuration
2710 * Helper function to determine if PHY capabilities matches PHY
2714 ice_phy_caps_equals_cfg(struct ice_aqc_get_phy_caps_data *phy_caps,
2715 struct ice_aqc_set_phy_cfg_data *phy_cfg)
2717 u8 caps_mask, cfg_mask;
2719 if (!phy_caps || !phy_cfg)
2722 /* These bits are not common between capabilities and configuration.
2723 * Do not use them to determine equality.
2725 caps_mask = ICE_AQC_PHY_CAPS_MASK & ~(ICE_AQC_PHY_AN_MODE |
2726 ICE_AQC_PHY_EN_MOD_QUAL);
2727 cfg_mask = ICE_AQ_PHY_ENA_VALID_MASK & ~ICE_AQ_PHY_ENA_AUTO_LINK_UPDT;
2729 if (phy_caps->phy_type_low != phy_cfg->phy_type_low ||
2730 phy_caps->phy_type_high != phy_cfg->phy_type_high ||
2731 ((phy_caps->caps & caps_mask) != (phy_cfg->caps & cfg_mask)) ||
2732 phy_caps->low_power_ctrl_an != phy_cfg->low_power_ctrl_an ||
2733 phy_caps->eee_cap != phy_cfg->eee_cap ||
2734 phy_caps->eeer_value != phy_cfg->eeer_value ||
2735 phy_caps->link_fec_options != phy_cfg->link_fec_opt)
2742 * ice_copy_phy_caps_to_cfg - Copy PHY ability data to configuration data
2743 * @pi: port information structure
2744 * @caps: PHY ability structure to copy date from
2745 * @cfg: PHY configuration structure to copy data to
2747 * Helper function to copy AQC PHY get ability data to PHY set configuration
2751 ice_copy_phy_caps_to_cfg(struct ice_port_info *pi,
2752 struct ice_aqc_get_phy_caps_data *caps,
2753 struct ice_aqc_set_phy_cfg_data *cfg)
2755 if (!pi || !caps || !cfg)
2758 ice_memset(cfg, 0, sizeof(*cfg), ICE_NONDMA_MEM);
2759 cfg->phy_type_low = caps->phy_type_low;
2760 cfg->phy_type_high = caps->phy_type_high;
2761 cfg->caps = caps->caps;
2762 cfg->low_power_ctrl_an = caps->low_power_ctrl_an;
2763 cfg->eee_cap = caps->eee_cap;
2764 cfg->eeer_value = caps->eeer_value;
2765 cfg->link_fec_opt = caps->link_fec_options;
2766 cfg->module_compliance_enforcement =
2767 caps->module_compliance_enforcement;
2769 if (ice_fw_supports_link_override(pi->hw)) {
2770 struct ice_link_default_override_tlv tlv;
2772 if (ice_get_link_default_override(&tlv, pi))
2775 if (tlv.options & ICE_LINK_OVERRIDE_STRICT_MODE)
2776 cfg->module_compliance_enforcement |=
2777 ICE_LINK_OVERRIDE_STRICT_MODE;
2782 * ice_cfg_phy_fec - Configure PHY FEC data based on FEC mode
2783 * @pi: port information structure
2784 * @cfg: PHY configuration data to set FEC mode
2785 * @fec: FEC mode to configure
2788 ice_cfg_phy_fec(struct ice_port_info *pi, struct ice_aqc_set_phy_cfg_data *cfg,
2789 enum ice_fec_mode fec)
2791 struct ice_aqc_get_phy_caps_data *pcaps;
2792 enum ice_status status = ICE_SUCCESS;
2796 return ICE_ERR_BAD_PTR;
2800 pcaps = (struct ice_aqc_get_phy_caps_data *)
2801 ice_malloc(hw, sizeof(*pcaps));
2803 return ICE_ERR_NO_MEMORY;
2805 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_TOPO_CAP, pcaps,
2810 cfg->caps |= (pcaps->caps & ICE_AQC_PHY_EN_AUTO_FEC);
2811 cfg->link_fec_opt = pcaps->link_fec_options;
2815 /* Clear RS bits, and AND BASE-R ability
2816 * bits and OR request bits.
2818 cfg->link_fec_opt &= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN |
2819 ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN;
2820 cfg->link_fec_opt |= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ |
2821 ICE_AQC_PHY_FEC_25G_KR_REQ;
2824 /* Clear BASE-R bits, and AND RS ability
2825 * bits and OR request bits.
2827 cfg->link_fec_opt &= ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN;
2828 cfg->link_fec_opt |= ICE_AQC_PHY_FEC_25G_RS_528_REQ |
2829 ICE_AQC_PHY_FEC_25G_RS_544_REQ;
2832 /* Clear all FEC option bits. */
2833 cfg->link_fec_opt &= ~ICE_AQC_PHY_FEC_MASK;
2836 /* AND auto FEC bit, and all caps bits. */
2837 cfg->caps &= ICE_AQC_PHY_CAPS_MASK;
2838 cfg->link_fec_opt |= pcaps->link_fec_options;
2841 status = ICE_ERR_PARAM;
2845 if (fec == ICE_FEC_AUTO && ice_fw_supports_link_override(pi->hw)) {
2846 struct ice_link_default_override_tlv tlv;
2848 if (ice_get_link_default_override(&tlv, pi))
2851 if (!(tlv.options & ICE_LINK_OVERRIDE_STRICT_MODE) &&
2852 (tlv.options & ICE_LINK_OVERRIDE_EN))
2853 cfg->link_fec_opt = tlv.fec_options;
2857 ice_free(hw, pcaps);
2863 * ice_get_link_status - get status of the HW network link
2864 * @pi: port information structure
2865 * @link_up: pointer to bool (true/false = linkup/linkdown)
2867 * Variable link_up is true if link is up, false if link is down.
2868 * The variable link_up is invalid if status is non zero. As a
2869 * result of this call, link status reporting becomes enabled
2871 enum ice_status ice_get_link_status(struct ice_port_info *pi, bool *link_up)
2873 struct ice_phy_info *phy_info;
2874 enum ice_status status = ICE_SUCCESS;
2876 if (!pi || !link_up)
2877 return ICE_ERR_PARAM;
2879 phy_info = &pi->phy;
2881 if (phy_info->get_link_info) {
2882 status = ice_update_link_info(pi);
2885 ice_debug(pi->hw, ICE_DBG_LINK,
2886 "get link status error, status = %d\n",
2890 *link_up = phy_info->link_info.link_info & ICE_AQ_LINK_UP;
2896 * ice_aq_set_link_restart_an
2897 * @pi: pointer to the port information structure
2898 * @ena_link: if true: enable link, if false: disable link
2899 * @cd: pointer to command details structure or NULL
2901 * Sets up the link and restarts the Auto-Negotiation over the link.
2904 ice_aq_set_link_restart_an(struct ice_port_info *pi, bool ena_link,
2905 struct ice_sq_cd *cd)
2907 struct ice_aqc_restart_an *cmd;
2908 struct ice_aq_desc desc;
2910 cmd = &desc.params.restart_an;
2912 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_restart_an);
2914 cmd->cmd_flags = ICE_AQC_RESTART_AN_LINK_RESTART;
2915 cmd->lport_num = pi->lport;
2917 cmd->cmd_flags |= ICE_AQC_RESTART_AN_LINK_ENABLE;
2919 cmd->cmd_flags &= ~ICE_AQC_RESTART_AN_LINK_ENABLE;
2921 return ice_aq_send_cmd(pi->hw, &desc, NULL, 0, cd);
2925 * ice_aq_set_event_mask
2926 * @hw: pointer to the HW struct
2927 * @port_num: port number of the physical function
2928 * @mask: event mask to be set
2929 * @cd: pointer to command details structure or NULL
2931 * Set event mask (0x0613)
2934 ice_aq_set_event_mask(struct ice_hw *hw, u8 port_num, u16 mask,
2935 struct ice_sq_cd *cd)
2937 struct ice_aqc_set_event_mask *cmd;
2938 struct ice_aq_desc desc;
2940 cmd = &desc.params.set_event_mask;
2942 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_event_mask);
2944 cmd->lport_num = port_num;
2946 cmd->event_mask = CPU_TO_LE16(mask);
2947 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
2951 * ice_aq_set_mac_loopback
2952 * @hw: pointer to the HW struct
2953 * @ena_lpbk: Enable or Disable loopback
2954 * @cd: pointer to command details structure or NULL
2956 * Enable/disable loopback on a given port
2959 ice_aq_set_mac_loopback(struct ice_hw *hw, bool ena_lpbk, struct ice_sq_cd *cd)
2961 struct ice_aqc_set_mac_lb *cmd;
2962 struct ice_aq_desc desc;
2964 cmd = &desc.params.set_mac_lb;
2966 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_mac_lb);
2968 cmd->lb_mode = ICE_AQ_MAC_LB_EN;
2970 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
2974 * ice_aq_set_port_id_led
2975 * @pi: pointer to the port information
2976 * @is_orig_mode: is this LED set to original mode (by the net-list)
2977 * @cd: pointer to command details structure or NULL
2979 * Set LED value for the given port (0x06e9)
2982 ice_aq_set_port_id_led(struct ice_port_info *pi, bool is_orig_mode,
2983 struct ice_sq_cd *cd)
2985 struct ice_aqc_set_port_id_led *cmd;
2986 struct ice_hw *hw = pi->hw;
2987 struct ice_aq_desc desc;
2989 cmd = &desc.params.set_port_id_led;
2991 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_port_id_led);
2994 cmd->ident_mode = ICE_AQC_PORT_IDENT_LED_ORIG;
2996 cmd->ident_mode = ICE_AQC_PORT_IDENT_LED_BLINK;
2998 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
3003 * @hw: pointer to the HW struct
3004 * @lport: bits [7:0] = logical port, bit [8] = logical port valid
3005 * @bus_addr: I2C bus address of the eeprom (typically 0xA0, 0=topo default)
3006 * @mem_addr: I2C offset. lower 8 bits for address, 8 upper bits zero padding.
3008 * @set_page: set or ignore the page
3009 * @data: pointer to data buffer to be read/written to the I2C device.
3010 * @length: 1-16 for read, 1 for write.
3011 * @write: 0 read, 1 for write.
3012 * @cd: pointer to command details structure or NULL
3014 * Read/Write SFF EEPROM (0x06EE)
3017 ice_aq_sff_eeprom(struct ice_hw *hw, u16 lport, u8 bus_addr,
3018 u16 mem_addr, u8 page, u8 set_page, u8 *data, u8 length,
3019 bool write, struct ice_sq_cd *cd)
3021 struct ice_aqc_sff_eeprom *cmd;
3022 struct ice_aq_desc desc;
3023 enum ice_status status;
3025 if (!data || (mem_addr & 0xff00))
3026 return ICE_ERR_PARAM;
3028 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_sff_eeprom);
3029 cmd = &desc.params.read_write_sff_param;
3030 desc.flags = CPU_TO_LE16(ICE_AQ_FLAG_RD | ICE_AQ_FLAG_BUF);
3031 cmd->lport_num = (u8)(lport & 0xff);
3032 cmd->lport_num_valid = (u8)((lport >> 8) & 0x01);
3033 cmd->i2c_bus_addr = CPU_TO_LE16(((bus_addr >> 1) &
3034 ICE_AQC_SFF_I2CBUS_7BIT_M) |
3036 ICE_AQC_SFF_SET_EEPROM_PAGE_S) &
3037 ICE_AQC_SFF_SET_EEPROM_PAGE_M));
3038 cmd->i2c_mem_addr = CPU_TO_LE16(mem_addr & 0xff);
3039 cmd->eeprom_page = CPU_TO_LE16((u16)page << ICE_AQC_SFF_EEPROM_PAGE_S);
3041 cmd->i2c_bus_addr |= CPU_TO_LE16(ICE_AQC_SFF_IS_WRITE);
3043 status = ice_aq_send_cmd(hw, &desc, data, length, cd);
3048 * __ice_aq_get_set_rss_lut
3049 * @hw: pointer to the hardware structure
3050 * @vsi_id: VSI FW index
3051 * @lut_type: LUT table type
3052 * @lut: pointer to the LUT buffer provided by the caller
3053 * @lut_size: size of the LUT buffer
3054 * @glob_lut_idx: global LUT index
3055 * @set: set true to set the table, false to get the table
3057 * Internal function to get (0x0B05) or set (0x0B03) RSS look up table
3059 static enum ice_status
3060 __ice_aq_get_set_rss_lut(struct ice_hw *hw, u16 vsi_id, u8 lut_type, u8 *lut,
3061 u16 lut_size, u8 glob_lut_idx, bool set)
3063 struct ice_aqc_get_set_rss_lut *cmd_resp;
3064 struct ice_aq_desc desc;
3065 enum ice_status status;
3068 cmd_resp = &desc.params.get_set_rss_lut;
3071 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_rss_lut);
3072 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
3074 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_rss_lut);
3077 cmd_resp->vsi_id = CPU_TO_LE16(((vsi_id <<
3078 ICE_AQC_GSET_RSS_LUT_VSI_ID_S) &
3079 ICE_AQC_GSET_RSS_LUT_VSI_ID_M) |
3080 ICE_AQC_GSET_RSS_LUT_VSI_VALID);
3083 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_VSI:
3084 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF:
3085 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL:
3086 flags |= ((lut_type << ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S) &
3087 ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_M);
3090 status = ICE_ERR_PARAM;
3091 goto ice_aq_get_set_rss_lut_exit;
3094 if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL) {
3095 flags |= ((glob_lut_idx << ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S) &
3096 ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_M);
3099 goto ice_aq_get_set_rss_lut_send;
3100 } else if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF) {
3102 goto ice_aq_get_set_rss_lut_send;
3104 goto ice_aq_get_set_rss_lut_send;
3107 /* LUT size is only valid for Global and PF table types */
3109 case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128:
3110 flags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128_FLAG <<
3111 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) &
3112 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M;
3114 case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512:
3115 flags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512_FLAG <<
3116 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) &
3117 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M;
3119 case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K:
3120 if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF) {
3121 flags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K_FLAG <<
3122 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) &
3123 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M;
3128 status = ICE_ERR_PARAM;
3129 goto ice_aq_get_set_rss_lut_exit;
3132 ice_aq_get_set_rss_lut_send:
3133 cmd_resp->flags = CPU_TO_LE16(flags);
3134 status = ice_aq_send_cmd(hw, &desc, lut, lut_size, NULL);
3136 ice_aq_get_set_rss_lut_exit:
3141 * ice_aq_get_rss_lut
3142 * @hw: pointer to the hardware structure
3143 * @vsi_handle: software VSI handle
3144 * @lut_type: LUT table type
3145 * @lut: pointer to the LUT buffer provided by the caller
3146 * @lut_size: size of the LUT buffer
3148 * get the RSS lookup table, PF or VSI type
3151 ice_aq_get_rss_lut(struct ice_hw *hw, u16 vsi_handle, u8 lut_type,
3152 u8 *lut, u16 lut_size)
3154 if (!ice_is_vsi_valid(hw, vsi_handle) || !lut)
3155 return ICE_ERR_PARAM;
3157 return __ice_aq_get_set_rss_lut(hw, ice_get_hw_vsi_num(hw, vsi_handle),
3158 lut_type, lut, lut_size, 0, false);
3162 * ice_aq_set_rss_lut
3163 * @hw: pointer to the hardware structure
3164 * @vsi_handle: software VSI handle
3165 * @lut_type: LUT table type
3166 * @lut: pointer to the LUT buffer provided by the caller
3167 * @lut_size: size of the LUT buffer
3169 * set the RSS lookup table, PF or VSI type
3172 ice_aq_set_rss_lut(struct ice_hw *hw, u16 vsi_handle, u8 lut_type,
3173 u8 *lut, u16 lut_size)
3175 if (!ice_is_vsi_valid(hw, vsi_handle) || !lut)
3176 return ICE_ERR_PARAM;
3178 return __ice_aq_get_set_rss_lut(hw, ice_get_hw_vsi_num(hw, vsi_handle),
3179 lut_type, lut, lut_size, 0, true);
3183 * __ice_aq_get_set_rss_key
3184 * @hw: pointer to the HW struct
3185 * @vsi_id: VSI FW index
3186 * @key: pointer to key info struct
3187 * @set: set true to set the key, false to get the key
3189 * get (0x0B04) or set (0x0B02) the RSS key per VSI
3192 ice_status __ice_aq_get_set_rss_key(struct ice_hw *hw, u16 vsi_id,
3193 struct ice_aqc_get_set_rss_keys *key,
3196 struct ice_aqc_get_set_rss_key *cmd_resp;
3197 u16 key_size = sizeof(*key);
3198 struct ice_aq_desc desc;
3200 cmd_resp = &desc.params.get_set_rss_key;
3203 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_rss_key);
3204 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
3206 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_rss_key);
3209 cmd_resp->vsi_id = CPU_TO_LE16(((vsi_id <<
3210 ICE_AQC_GSET_RSS_KEY_VSI_ID_S) &
3211 ICE_AQC_GSET_RSS_KEY_VSI_ID_M) |
3212 ICE_AQC_GSET_RSS_KEY_VSI_VALID);
3214 return ice_aq_send_cmd(hw, &desc, key, key_size, NULL);
3218 * ice_aq_get_rss_key
3219 * @hw: pointer to the HW struct
3220 * @vsi_handle: software VSI handle
3221 * @key: pointer to key info struct
3223 * get the RSS key per VSI
3226 ice_aq_get_rss_key(struct ice_hw *hw, u16 vsi_handle,
3227 struct ice_aqc_get_set_rss_keys *key)
3229 if (!ice_is_vsi_valid(hw, vsi_handle) || !key)
3230 return ICE_ERR_PARAM;
3232 return __ice_aq_get_set_rss_key(hw, ice_get_hw_vsi_num(hw, vsi_handle),
3237 * ice_aq_set_rss_key
3238 * @hw: pointer to the HW struct
3239 * @vsi_handle: software VSI handle
3240 * @keys: pointer to key info struct
3242 * set the RSS key per VSI
3245 ice_aq_set_rss_key(struct ice_hw *hw, u16 vsi_handle,
3246 struct ice_aqc_get_set_rss_keys *keys)
3248 if (!ice_is_vsi_valid(hw, vsi_handle) || !keys)
3249 return ICE_ERR_PARAM;
3251 return __ice_aq_get_set_rss_key(hw, ice_get_hw_vsi_num(hw, vsi_handle),
3256 * ice_aq_add_lan_txq
3257 * @hw: pointer to the hardware structure
3258 * @num_qgrps: Number of added queue groups
3259 * @qg_list: list of queue groups to be added
3260 * @buf_size: size of buffer for indirect command
3261 * @cd: pointer to command details structure or NULL
3263 * Add Tx LAN queue (0x0C30)
3266 * Prior to calling add Tx LAN queue:
3267 * Initialize the following as part of the Tx queue context:
3268 * Completion queue ID if the queue uses Completion queue, Quanta profile,
3269 * Cache profile and Packet shaper profile.
3271 * After add Tx LAN queue AQ command is completed:
3272 * Interrupts should be associated with specific queues,
3273 * Association of Tx queue to Doorbell queue is not part of Add LAN Tx queue
3277 ice_aq_add_lan_txq(struct ice_hw *hw, u8 num_qgrps,
3278 struct ice_aqc_add_tx_qgrp *qg_list, u16 buf_size,
3279 struct ice_sq_cd *cd)
3281 u16 i, sum_header_size, sum_q_size = 0;
3282 struct ice_aqc_add_tx_qgrp *list;
3283 struct ice_aqc_add_txqs *cmd;
3284 struct ice_aq_desc desc;
3286 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
3288 cmd = &desc.params.add_txqs;
3290 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_add_txqs);
3293 return ICE_ERR_PARAM;
3295 if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS)
3296 return ICE_ERR_PARAM;
3298 sum_header_size = num_qgrps *
3299 (sizeof(*qg_list) - sizeof(*qg_list->txqs));
3302 for (i = 0; i < num_qgrps; i++) {
3303 struct ice_aqc_add_txqs_perq *q = list->txqs;
3305 sum_q_size += list->num_txqs * sizeof(*q);
3306 list = (struct ice_aqc_add_tx_qgrp *)(q + list->num_txqs);
3309 if (buf_size != (sum_header_size + sum_q_size))
3310 return ICE_ERR_PARAM;
3312 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
3314 cmd->num_qgrps = num_qgrps;
3316 return ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd);
3320 * ice_aq_dis_lan_txq
3321 * @hw: pointer to the hardware structure
3322 * @num_qgrps: number of groups in the list
3323 * @qg_list: the list of groups to disable
3324 * @buf_size: the total size of the qg_list buffer in bytes
3325 * @rst_src: if called due to reset, specifies the reset source
3326 * @vmvf_num: the relative VM or VF number that is undergoing the reset
3327 * @cd: pointer to command details structure or NULL
3329 * Disable LAN Tx queue (0x0C31)
3331 static enum ice_status
3332 ice_aq_dis_lan_txq(struct ice_hw *hw, u8 num_qgrps,
3333 struct ice_aqc_dis_txq_item *qg_list, u16 buf_size,
3334 enum ice_disq_rst_src rst_src, u16 vmvf_num,
3335 struct ice_sq_cd *cd)
3337 struct ice_aqc_dis_txqs *cmd;
3338 struct ice_aq_desc desc;
3339 enum ice_status status;
3342 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
3343 cmd = &desc.params.dis_txqs;
3344 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_dis_txqs);
3346 /* qg_list can be NULL only in VM/VF reset flow */
3347 if (!qg_list && !rst_src)
3348 return ICE_ERR_PARAM;
3350 if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS)
3351 return ICE_ERR_PARAM;
3353 cmd->num_entries = num_qgrps;
3355 cmd->vmvf_and_timeout = CPU_TO_LE16((5 << ICE_AQC_Q_DIS_TIMEOUT_S) &
3356 ICE_AQC_Q_DIS_TIMEOUT_M);
3360 cmd->cmd_type = ICE_AQC_Q_DIS_CMD_VM_RESET;
3361 cmd->vmvf_and_timeout |=
3362 CPU_TO_LE16(vmvf_num & ICE_AQC_Q_DIS_VMVF_NUM_M);
3369 /* flush pipe on time out */
3370 cmd->cmd_type |= ICE_AQC_Q_DIS_CMD_FLUSH_PIPE;
3371 /* If no queue group info, we are in a reset flow. Issue the AQ */
3375 /* set RD bit to indicate that command buffer is provided by the driver
3376 * and it needs to be read by the firmware
3378 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
3380 for (i = 0; i < num_qgrps; ++i) {
3381 /* Calculate the size taken up by the queue IDs in this group */
3382 sz += qg_list[i].num_qs * sizeof(qg_list[i].q_id);
3384 /* Add the size of the group header */
3385 sz += sizeof(qg_list[i]) - sizeof(qg_list[i].q_id);
3387 /* If the num of queues is even, add 2 bytes of padding */
3388 if ((qg_list[i].num_qs % 2) == 0)
3393 return ICE_ERR_PARAM;
3396 status = ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd);
3399 ice_debug(hw, ICE_DBG_SCHED, "VM%d disable failed %d\n",
3400 vmvf_num, hw->adminq.sq_last_status);
3402 ice_debug(hw, ICE_DBG_SCHED, "disable queue %d failed %d\n",
3403 LE16_TO_CPU(qg_list[0].q_id[0]),
3404 hw->adminq.sq_last_status);
3410 * ice_aq_move_recfg_lan_txq
3411 * @hw: pointer to the hardware structure
3412 * @num_qs: number of queues to move/reconfigure
3413 * @is_move: true if this operation involves node movement
3414 * @is_tc_change: true if this operation involves a TC change
3415 * @subseq_call: true if this operation is a subsequent call
3416 * @flush_pipe: on timeout, true to flush pipe, false to return EAGAIN
3417 * @timeout: timeout in units of 100 usec (valid values 0-50)
3418 * @blocked_cgds: out param, bitmap of CGDs that timed out if returning EAGAIN
3419 * @buf: struct containing src/dest TEID and per-queue info
3420 * @buf_size: size of buffer for indirect command
3421 * @txqs_moved: out param, number of queues successfully moved
3422 * @cd: pointer to command details structure or NULL
3424 * Move / Reconfigure Tx LAN queues (0x0C32)
3427 ice_aq_move_recfg_lan_txq(struct ice_hw *hw, u8 num_qs, bool is_move,
3428 bool is_tc_change, bool subseq_call, bool flush_pipe,
3429 u8 timeout, u32 *blocked_cgds,
3430 struct ice_aqc_move_txqs_data *buf, u16 buf_size,
3431 u8 *txqs_moved, struct ice_sq_cd *cd)
3433 struct ice_aqc_move_txqs *cmd;
3434 struct ice_aq_desc desc;
3435 enum ice_status status;
3437 cmd = &desc.params.move_txqs;
3438 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_move_recfg_txqs);
3440 #define ICE_LAN_TXQ_MOVE_TIMEOUT_MAX 50
3441 if (timeout > ICE_LAN_TXQ_MOVE_TIMEOUT_MAX)
3442 return ICE_ERR_PARAM;
3444 if (is_tc_change && !flush_pipe && !blocked_cgds)
3445 return ICE_ERR_PARAM;
3447 if (!is_move && !is_tc_change)
3448 return ICE_ERR_PARAM;
3450 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
3453 cmd->cmd_type |= ICE_AQC_Q_CMD_TYPE_MOVE;
3456 cmd->cmd_type |= ICE_AQC_Q_CMD_TYPE_TC_CHANGE;
3459 cmd->cmd_type |= ICE_AQC_Q_CMD_SUBSEQ_CALL;
3462 cmd->cmd_type |= ICE_AQC_Q_CMD_FLUSH_PIPE;
3464 cmd->num_qs = num_qs;
3465 cmd->timeout = ((timeout << ICE_AQC_Q_CMD_TIMEOUT_S) &
3466 ICE_AQC_Q_CMD_TIMEOUT_M);
3468 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);
3470 if (!status && txqs_moved)
3471 *txqs_moved = cmd->num_qs;
3473 if (hw->adminq.sq_last_status == ICE_AQ_RC_EAGAIN &&
3474 is_tc_change && !flush_pipe)
3475 *blocked_cgds = LE32_TO_CPU(cmd->blocked_cgds);
3480 /* End of FW Admin Queue command wrappers */
3483 * ice_write_byte - write a byte to a packed context structure
3484 * @src_ctx: the context structure to read from
3485 * @dest_ctx: the context to be written to
3486 * @ce_info: a description of the struct to be filled
3489 ice_write_byte(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)
3491 u8 src_byte, dest_byte, mask;
3495 /* copy from the next struct field */
3496 from = src_ctx + ce_info->offset;
3498 /* prepare the bits and mask */
3499 shift_width = ce_info->lsb % 8;
3500 mask = (u8)(BIT(ce_info->width) - 1);
3505 /* shift to correct alignment */
3506 mask <<= shift_width;
3507 src_byte <<= shift_width;
3509 /* get the current bits from the target bit string */
3510 dest = dest_ctx + (ce_info->lsb / 8);
3512 ice_memcpy(&dest_byte, dest, sizeof(dest_byte), ICE_DMA_TO_NONDMA);
3514 dest_byte &= ~mask; /* get the bits not changing */
3515 dest_byte |= src_byte; /* add in the new bits */
3517 /* put it all back */
3518 ice_memcpy(dest, &dest_byte, sizeof(dest_byte), ICE_NONDMA_TO_DMA);
3522 * ice_write_word - write a word to a packed context structure
3523 * @src_ctx: the context structure to read from
3524 * @dest_ctx: the context to be written to
3525 * @ce_info: a description of the struct to be filled
3528 ice_write_word(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)
3535 /* copy from the next struct field */
3536 from = src_ctx + ce_info->offset;
3538 /* prepare the bits and mask */
3539 shift_width = ce_info->lsb % 8;
3540 mask = BIT(ce_info->width) - 1;
3542 /* don't swizzle the bits until after the mask because the mask bits
3543 * will be in a different bit position on big endian machines
3545 src_word = *(u16 *)from;
3548 /* shift to correct alignment */
3549 mask <<= shift_width;
3550 src_word <<= shift_width;
3552 /* get the current bits from the target bit string */
3553 dest = dest_ctx + (ce_info->lsb / 8);
3555 ice_memcpy(&dest_word, dest, sizeof(dest_word), ICE_DMA_TO_NONDMA);
3557 dest_word &= ~(CPU_TO_LE16(mask)); /* get the bits not changing */
3558 dest_word |= CPU_TO_LE16(src_word); /* add in the new bits */
3560 /* put it all back */
3561 ice_memcpy(dest, &dest_word, sizeof(dest_word), ICE_NONDMA_TO_DMA);
3565 * ice_write_dword - write a dword to a packed context structure
3566 * @src_ctx: the context structure to read from
3567 * @dest_ctx: the context to be written to
3568 * @ce_info: a description of the struct to be filled
3571 ice_write_dword(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)
3573 u32 src_dword, mask;
3578 /* copy from the next struct field */
3579 from = src_ctx + ce_info->offset;
3581 /* prepare the bits and mask */
3582 shift_width = ce_info->lsb % 8;
3584 /* if the field width is exactly 32 on an x86 machine, then the shift
3585 * operation will not work because the SHL instructions count is masked
3586 * to 5 bits so the shift will do nothing
3588 if (ce_info->width < 32)
3589 mask = BIT(ce_info->width) - 1;
3593 /* don't swizzle the bits until after the mask because the mask bits
3594 * will be in a different bit position on big endian machines
3596 src_dword = *(u32 *)from;
3599 /* shift to correct alignment */
3600 mask <<= shift_width;
3601 src_dword <<= shift_width;
3603 /* get the current bits from the target bit string */
3604 dest = dest_ctx + (ce_info->lsb / 8);
3606 ice_memcpy(&dest_dword, dest, sizeof(dest_dword), ICE_DMA_TO_NONDMA);
3608 dest_dword &= ~(CPU_TO_LE32(mask)); /* get the bits not changing */
3609 dest_dword |= CPU_TO_LE32(src_dword); /* add in the new bits */
3611 /* put it all back */
3612 ice_memcpy(dest, &dest_dword, sizeof(dest_dword), ICE_NONDMA_TO_DMA);
3616 * ice_write_qword - write a qword to a packed context structure
3617 * @src_ctx: the context structure to read from
3618 * @dest_ctx: the context to be written to
3619 * @ce_info: a description of the struct to be filled
3622 ice_write_qword(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)
3624 u64 src_qword, mask;
3629 /* copy from the next struct field */
3630 from = src_ctx + ce_info->offset;
3632 /* prepare the bits and mask */
3633 shift_width = ce_info->lsb % 8;
3635 /* if the field width is exactly 64 on an x86 machine, then the shift
3636 * operation will not work because the SHL instructions count is masked
3637 * to 6 bits so the shift will do nothing
3639 if (ce_info->width < 64)
3640 mask = BIT_ULL(ce_info->width) - 1;
3644 /* don't swizzle the bits until after the mask because the mask bits
3645 * will be in a different bit position on big endian machines
3647 src_qword = *(u64 *)from;
3650 /* shift to correct alignment */
3651 mask <<= shift_width;
3652 src_qword <<= shift_width;
3654 /* get the current bits from the target bit string */
3655 dest = dest_ctx + (ce_info->lsb / 8);
3657 ice_memcpy(&dest_qword, dest, sizeof(dest_qword), ICE_DMA_TO_NONDMA);
3659 dest_qword &= ~(CPU_TO_LE64(mask)); /* get the bits not changing */
3660 dest_qword |= CPU_TO_LE64(src_qword); /* add in the new bits */
3662 /* put it all back */
3663 ice_memcpy(dest, &dest_qword, sizeof(dest_qword), ICE_NONDMA_TO_DMA);
3667 * ice_set_ctx - set context bits in packed structure
3668 * @hw: pointer to the hardware structure
3669 * @src_ctx: pointer to a generic non-packed context structure
3670 * @dest_ctx: pointer to memory for the packed structure
3671 * @ce_info: a description of the structure to be transformed
3674 ice_set_ctx(struct ice_hw *hw, u8 *src_ctx, u8 *dest_ctx,
3675 const struct ice_ctx_ele *ce_info)
3679 for (f = 0; ce_info[f].width; f++) {
3680 /* We have to deal with each element of the FW response
3681 * using the correct size so that we are correct regardless
3682 * of the endianness of the machine.
3684 if (ce_info[f].width > (ce_info[f].size_of * BITS_PER_BYTE)) {
3685 ice_debug(hw, ICE_DBG_QCTX,
3686 "Field %d width of %d bits larger than size of %d byte(s) ... skipping write\n",
3687 f, ce_info[f].width, ce_info[f].size_of);
3690 switch (ce_info[f].size_of) {
3692 ice_write_byte(src_ctx, dest_ctx, &ce_info[f]);
3695 ice_write_word(src_ctx, dest_ctx, &ce_info[f]);
3698 ice_write_dword(src_ctx, dest_ctx, &ce_info[f]);
3701 ice_write_qword(src_ctx, dest_ctx, &ce_info[f]);
3704 return ICE_ERR_INVAL_SIZE;
3712 * ice_read_byte - read context byte into struct
3713 * @src_ctx: the context structure to read from
3714 * @dest_ctx: the context to be written to
3715 * @ce_info: a description of the struct to be filled
3718 ice_read_byte(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info)
3724 /* prepare the bits and mask */
3725 shift_width = ce_info->lsb % 8;
3726 mask = (u8)(BIT(ce_info->width) - 1);
3728 /* shift to correct alignment */
3729 mask <<= shift_width;
3731 /* get the current bits from the src bit string */
3732 src = src_ctx + (ce_info->lsb / 8);
3734 ice_memcpy(&dest_byte, src, sizeof(dest_byte), ICE_DMA_TO_NONDMA);
3736 dest_byte &= ~(mask);
3738 dest_byte >>= shift_width;
3740 /* get the address from the struct field */
3741 target = dest_ctx + ce_info->offset;
3743 /* put it back in the struct */
3744 ice_memcpy(target, &dest_byte, sizeof(dest_byte), ICE_NONDMA_TO_DMA);
3748 * ice_read_word - read context word into struct
3749 * @src_ctx: the context structure to read from
3750 * @dest_ctx: the context to be written to
3751 * @ce_info: a description of the struct to be filled
3754 ice_read_word(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info)
3756 u16 dest_word, mask;
3761 /* prepare the bits and mask */
3762 shift_width = ce_info->lsb % 8;
3763 mask = BIT(ce_info->width) - 1;
3765 /* shift to correct alignment */
3766 mask <<= shift_width;
3768 /* get the current bits from the src bit string */
3769 src = src_ctx + (ce_info->lsb / 8);
3771 ice_memcpy(&src_word, src, sizeof(src_word), ICE_DMA_TO_NONDMA);
3773 /* the data in the memory is stored as little endian so mask it
3776 src_word &= ~(CPU_TO_LE16(mask));
3778 /* get the data back into host order before shifting */
3779 dest_word = LE16_TO_CPU(src_word);
3781 dest_word >>= shift_width;
3783 /* get the address from the struct field */
3784 target = dest_ctx + ce_info->offset;
3786 /* put it back in the struct */
3787 ice_memcpy(target, &dest_word, sizeof(dest_word), ICE_NONDMA_TO_DMA);
3791 * ice_read_dword - read context dword into struct
3792 * @src_ctx: the context structure to read from
3793 * @dest_ctx: the context to be written to
3794 * @ce_info: a description of the struct to be filled
3797 ice_read_dword(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info)
3799 u32 dest_dword, mask;
3804 /* prepare the bits and mask */
3805 shift_width = ce_info->lsb % 8;
3807 /* if the field width is exactly 32 on an x86 machine, then the shift
3808 * operation will not work because the SHL instructions count is masked
3809 * to 5 bits so the shift will do nothing
3811 if (ce_info->width < 32)
3812 mask = BIT(ce_info->width) - 1;
3816 /* shift to correct alignment */
3817 mask <<= shift_width;
3819 /* get the current bits from the src bit string */
3820 src = src_ctx + (ce_info->lsb / 8);
3822 ice_memcpy(&src_dword, src, sizeof(src_dword), ICE_DMA_TO_NONDMA);
3824 /* the data in the memory is stored as little endian so mask it
3827 src_dword &= ~(CPU_TO_LE32(mask));
3829 /* get the data back into host order before shifting */
3830 dest_dword = LE32_TO_CPU(src_dword);
3832 dest_dword >>= shift_width;
3834 /* get the address from the struct field */
3835 target = dest_ctx + ce_info->offset;
3837 /* put it back in the struct */
3838 ice_memcpy(target, &dest_dword, sizeof(dest_dword), ICE_NONDMA_TO_DMA);
3842 * ice_read_qword - read context qword into struct
3843 * @src_ctx: the context structure to read from
3844 * @dest_ctx: the context to be written to
3845 * @ce_info: a description of the struct to be filled
3848 ice_read_qword(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info)
3850 u64 dest_qword, mask;
3855 /* prepare the bits and mask */
3856 shift_width = ce_info->lsb % 8;
3858 /* if the field width is exactly 64 on an x86 machine, then the shift
3859 * operation will not work because the SHL instructions count is masked
3860 * to 6 bits so the shift will do nothing
3862 if (ce_info->width < 64)
3863 mask = BIT_ULL(ce_info->width) - 1;
3867 /* shift to correct alignment */
3868 mask <<= shift_width;
3870 /* get the current bits from the src bit string */
3871 src = src_ctx + (ce_info->lsb / 8);
3873 ice_memcpy(&src_qword, src, sizeof(src_qword), ICE_DMA_TO_NONDMA);
3875 /* the data in the memory is stored as little endian so mask it
3878 src_qword &= ~(CPU_TO_LE64(mask));
3880 /* get the data back into host order before shifting */
3881 dest_qword = LE64_TO_CPU(src_qword);
3883 dest_qword >>= shift_width;
3885 /* get the address from the struct field */
3886 target = dest_ctx + ce_info->offset;
3888 /* put it back in the struct */
3889 ice_memcpy(target, &dest_qword, sizeof(dest_qword), ICE_NONDMA_TO_DMA);
3893 * ice_get_ctx - extract context bits from a packed structure
3894 * @src_ctx: pointer to a generic packed context structure
3895 * @dest_ctx: pointer to a generic non-packed context structure
3896 * @ce_info: a description of the structure to be read from
3899 ice_get_ctx(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info)
3903 for (f = 0; ce_info[f].width; f++) {
3904 switch (ce_info[f].size_of) {
3906 ice_read_byte(src_ctx, dest_ctx, &ce_info[f]);
3909 ice_read_word(src_ctx, dest_ctx, &ce_info[f]);
3912 ice_read_dword(src_ctx, dest_ctx, &ce_info[f]);
3915 ice_read_qword(src_ctx, dest_ctx, &ce_info[f]);
3918 /* nothing to do, just keep going */
3927 * ice_get_lan_q_ctx - get the LAN queue context for the given VSI and TC
3928 * @hw: pointer to the HW struct
3929 * @vsi_handle: software VSI handle
3931 * @q_handle: software queue handle
3934 ice_get_lan_q_ctx(struct ice_hw *hw, u16 vsi_handle, u8 tc, u16 q_handle)
3936 struct ice_vsi_ctx *vsi;
3937 struct ice_q_ctx *q_ctx;
3939 vsi = ice_get_vsi_ctx(hw, vsi_handle);
3942 if (q_handle >= vsi->num_lan_q_entries[tc])
3944 if (!vsi->lan_q_ctx[tc])
3946 q_ctx = vsi->lan_q_ctx[tc];
3947 return &q_ctx[q_handle];
3952 * @pi: port information structure
3953 * @vsi_handle: software VSI handle
3955 * @q_handle: software queue handle
3956 * @num_qgrps: Number of added queue groups
3957 * @buf: list of queue groups to be added
3958 * @buf_size: size of buffer for indirect command
3959 * @cd: pointer to command details structure or NULL
3961 * This function adds one LAN queue
3964 ice_ena_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u16 q_handle,
3965 u8 num_qgrps, struct ice_aqc_add_tx_qgrp *buf, u16 buf_size,
3966 struct ice_sq_cd *cd)
3968 struct ice_aqc_txsched_elem_data node = { 0 };
3969 struct ice_sched_node *parent;
3970 struct ice_q_ctx *q_ctx;
3971 enum ice_status status;
3974 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY)
3977 if (num_qgrps > 1 || buf->num_txqs > 1)
3978 return ICE_ERR_MAX_LIMIT;
3982 if (!ice_is_vsi_valid(hw, vsi_handle))
3983 return ICE_ERR_PARAM;
3985 ice_acquire_lock(&pi->sched_lock);
3987 q_ctx = ice_get_lan_q_ctx(hw, vsi_handle, tc, q_handle);
3989 ice_debug(hw, ICE_DBG_SCHED, "Enaq: invalid queue handle %d\n",
3991 status = ICE_ERR_PARAM;
3995 /* find a parent node */
3996 parent = ice_sched_get_free_qparent(pi, vsi_handle, tc,
3997 ICE_SCHED_NODE_OWNER_LAN);
3999 status = ICE_ERR_PARAM;
4003 buf->parent_teid = parent->info.node_teid;
4004 node.parent_teid = parent->info.node_teid;
4005 /* Mark that the values in the "generic" section as valid. The default
4006 * value in the "generic" section is zero. This means that :
4007 * - Scheduling mode is Bytes Per Second (BPS), indicated by Bit 0.
4008 * - 0 priority among siblings, indicated by Bit 1-3.
4009 * - WFQ, indicated by Bit 4.
4010 * - 0 Adjustment value is used in PSM credit update flow, indicated by
4012 * - Bit 7 is reserved.
4013 * Without setting the generic section as valid in valid_sections, the
4014 * Admin queue command will fail with error code ICE_AQ_RC_EINVAL.
4016 buf->txqs[0].info.valid_sections =
4017 ICE_AQC_ELEM_VALID_GENERIC | ICE_AQC_ELEM_VALID_CIR |
4018 ICE_AQC_ELEM_VALID_EIR;
4019 buf->txqs[0].info.generic = 0;
4020 buf->txqs[0].info.cir_bw.bw_profile_idx =
4021 CPU_TO_LE16(ICE_SCHED_DFLT_RL_PROF_ID);
4022 buf->txqs[0].info.cir_bw.bw_alloc =
4023 CPU_TO_LE16(ICE_SCHED_DFLT_BW_WT);
4024 buf->txqs[0].info.eir_bw.bw_profile_idx =
4025 CPU_TO_LE16(ICE_SCHED_DFLT_RL_PROF_ID);
4026 buf->txqs[0].info.eir_bw.bw_alloc =
4027 CPU_TO_LE16(ICE_SCHED_DFLT_BW_WT);
4029 /* add the LAN queue */
4030 status = ice_aq_add_lan_txq(hw, num_qgrps, buf, buf_size, cd);
4031 if (status != ICE_SUCCESS) {
4032 ice_debug(hw, ICE_DBG_SCHED, "enable queue %d failed %d\n",
4033 LE16_TO_CPU(buf->txqs[0].txq_id),
4034 hw->adminq.sq_last_status);
4038 node.node_teid = buf->txqs[0].q_teid;
4039 node.data.elem_type = ICE_AQC_ELEM_TYPE_LEAF;
4040 q_ctx->q_handle = q_handle;
4041 q_ctx->q_teid = LE32_TO_CPU(node.node_teid);
4043 /* add a leaf node into scheduler tree queue layer */
4044 status = ice_sched_add_node(pi, hw->num_tx_sched_layers - 1, &node);
4046 status = ice_sched_replay_q_bw(pi, q_ctx);
4049 ice_release_lock(&pi->sched_lock);
4055 * @pi: port information structure
4056 * @vsi_handle: software VSI handle
4058 * @num_queues: number of queues
4059 * @q_handles: pointer to software queue handle array
4060 * @q_ids: pointer to the q_id array
4061 * @q_teids: pointer to queue node teids
4062 * @rst_src: if called due to reset, specifies the reset source
4063 * @vmvf_num: the relative VM or VF number that is undergoing the reset
4064 * @cd: pointer to command details structure or NULL
4066 * This function removes queues and their corresponding nodes in SW DB
4069 ice_dis_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u8 num_queues,
4070 u16 *q_handles, u16 *q_ids, u32 *q_teids,
4071 enum ice_disq_rst_src rst_src, u16 vmvf_num,
4072 struct ice_sq_cd *cd)
4074 enum ice_status status = ICE_ERR_DOES_NOT_EXIST;
4075 struct ice_aqc_dis_txq_item qg_list;
4076 struct ice_q_ctx *q_ctx;
4079 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY)
4083 /* if queue is disabled already yet the disable queue command
4084 * has to be sent to complete the VF reset, then call
4085 * ice_aq_dis_lan_txq without any queue information
4088 return ice_aq_dis_lan_txq(pi->hw, 0, NULL, 0, rst_src,
4093 ice_acquire_lock(&pi->sched_lock);
4095 for (i = 0; i < num_queues; i++) {
4096 struct ice_sched_node *node;
4098 node = ice_sched_find_node_by_teid(pi->root, q_teids[i]);
4101 q_ctx = ice_get_lan_q_ctx(pi->hw, vsi_handle, tc, q_handles[i]);
4103 ice_debug(pi->hw, ICE_DBG_SCHED, "invalid queue handle%d\n",
4107 if (q_ctx->q_handle != q_handles[i]) {
4108 ice_debug(pi->hw, ICE_DBG_SCHED, "Err:handles %d %d\n",
4109 q_ctx->q_handle, q_handles[i]);
4112 qg_list.parent_teid = node->info.parent_teid;
4114 qg_list.q_id[0] = CPU_TO_LE16(q_ids[i]);
4115 status = ice_aq_dis_lan_txq(pi->hw, 1, &qg_list,
4116 sizeof(qg_list), rst_src, vmvf_num,
4119 if (status != ICE_SUCCESS)
4121 ice_free_sched_node(pi, node);
4122 q_ctx->q_handle = ICE_INVAL_Q_HANDLE;
4124 ice_release_lock(&pi->sched_lock);
4129 * ice_cfg_vsi_qs - configure the new/existing VSI queues
4130 * @pi: port information structure
4131 * @vsi_handle: software VSI handle
4132 * @tc_bitmap: TC bitmap
4133 * @maxqs: max queues array per TC
4134 * @owner: LAN or RDMA
4136 * This function adds/updates the VSI queues per TC.
4138 static enum ice_status
4139 ice_cfg_vsi_qs(struct ice_port_info *pi, u16 vsi_handle, u16 tc_bitmap,
4140 u16 *maxqs, u8 owner)
4142 enum ice_status status = ICE_SUCCESS;
4145 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY)
4148 if (!ice_is_vsi_valid(pi->hw, vsi_handle))
4149 return ICE_ERR_PARAM;
4151 ice_acquire_lock(&pi->sched_lock);
4153 ice_for_each_traffic_class(i) {
4154 /* configuration is possible only if TC node is present */
4155 if (!ice_sched_get_tc_node(pi, i))
4158 status = ice_sched_cfg_vsi(pi, vsi_handle, i, maxqs[i], owner,
4159 ice_is_tc_ena(tc_bitmap, i));
4164 ice_release_lock(&pi->sched_lock);
4169 * ice_cfg_vsi_lan - configure VSI LAN queues
4170 * @pi: port information structure
4171 * @vsi_handle: software VSI handle
4172 * @tc_bitmap: TC bitmap
4173 * @max_lanqs: max LAN queues array per TC
4175 * This function adds/updates the VSI LAN queues per TC.
4178 ice_cfg_vsi_lan(struct ice_port_info *pi, u16 vsi_handle, u16 tc_bitmap,
4181 return ice_cfg_vsi_qs(pi, vsi_handle, tc_bitmap, max_lanqs,
4182 ICE_SCHED_NODE_OWNER_LAN);
4186 * ice_is_main_vsi - checks whether the VSI is main VSI
4187 * @hw: pointer to the HW struct
4188 * @vsi_handle: VSI handle
4190 * Checks whether the VSI is the main VSI (the first PF VSI created on
4193 static bool ice_is_main_vsi(struct ice_hw *hw, u16 vsi_handle)
4195 return vsi_handle == ICE_MAIN_VSI_HANDLE && hw->vsi_ctx[vsi_handle];
4199 * ice_replay_pre_init - replay pre initialization
4200 * @hw: pointer to the HW struct
4201 * @sw: pointer to switch info struct for which function initializes filters
4203 * Initializes required config data for VSI, FD, ACL, and RSS before replay.
4205 static enum ice_status
4206 ice_replay_pre_init(struct ice_hw *hw, struct ice_switch_info *sw)
4210 /* Delete old entries from replay filter list head if there is any */
4211 ice_rm_sw_replay_rule_info(hw, sw);
4212 /* In start of replay, move entries into replay_rules list, it
4213 * will allow adding rules entries back to filt_rules list,
4214 * which is operational list.
4216 for (i = 0; i < ICE_MAX_NUM_RECIPES; i++)
4217 LIST_REPLACE_INIT(&sw->recp_list[i].filt_rules,
4218 &sw->recp_list[i].filt_replay_rules);
4219 ice_sched_replay_agg_vsi_preinit(hw);
4221 return ice_sched_replay_tc_node_bw(hw->port_info);
4225 * ice_replay_vsi - replay VSI configuration
4226 * @hw: pointer to the HW struct
4227 * @vsi_handle: driver VSI handle
4229 * Restore all VSI configuration after reset. It is required to call this
4230 * function with main VSI first.
4232 enum ice_status ice_replay_vsi(struct ice_hw *hw, u16 vsi_handle)
4234 struct ice_switch_info *sw = hw->switch_info;
4235 struct ice_port_info *pi = hw->port_info;
4236 enum ice_status status;
4238 if (!ice_is_vsi_valid(hw, vsi_handle))
4239 return ICE_ERR_PARAM;
4241 /* Replay pre-initialization if there is any */
4242 if (ice_is_main_vsi(hw, vsi_handle)) {
4243 status = ice_replay_pre_init(hw, sw);
4247 /* Replay per VSI all RSS configurations */
4248 status = ice_replay_rss_cfg(hw, vsi_handle);
4251 /* Replay per VSI all filters */
4252 status = ice_replay_vsi_all_fltr(hw, pi, vsi_handle);
4254 status = ice_replay_vsi_agg(hw, vsi_handle);
4259 * ice_replay_post - post replay configuration cleanup
4260 * @hw: pointer to the HW struct
4262 * Post replay cleanup.
4264 void ice_replay_post(struct ice_hw *hw)
4266 /* Delete old entries from replay filter list head */
4267 ice_rm_all_sw_replay_rule_info(hw);
4268 ice_sched_replay_agg(hw);
4272 * ice_stat_update40 - read 40 bit stat from the chip and update stat values
4273 * @hw: ptr to the hardware info
4274 * @reg: offset of 64 bit HW register to read from
4275 * @prev_stat_loaded: bool to specify if previous stats are loaded
4276 * @prev_stat: ptr to previous loaded stat value
4277 * @cur_stat: ptr to current stat value
4280 ice_stat_update40(struct ice_hw *hw, u32 reg, bool prev_stat_loaded,
4281 u64 *prev_stat, u64 *cur_stat)
4283 u64 new_data = rd64(hw, reg) & (BIT_ULL(40) - 1);
4285 /* device stats are not reset at PFR, they likely will not be zeroed
4286 * when the driver starts. Thus, save the value from the first read
4287 * without adding to the statistic value so that we report stats which
4288 * count up from zero.
4290 if (!prev_stat_loaded) {
4291 *prev_stat = new_data;
4295 /* Calculate the difference between the new and old values, and then
4296 * add it to the software stat value.
4298 if (new_data >= *prev_stat)
4299 *cur_stat += new_data - *prev_stat;
4301 /* to manage the potential roll-over */
4302 *cur_stat += (new_data + BIT_ULL(40)) - *prev_stat;
4304 /* Update the previously stored value to prepare for next read */
4305 *prev_stat = new_data;
4309 * ice_stat_update32 - read 32 bit stat from the chip and update stat values
4310 * @hw: ptr to the hardware info
4311 * @reg: offset of HW register to read from
4312 * @prev_stat_loaded: bool to specify if previous stats are loaded
4313 * @prev_stat: ptr to previous loaded stat value
4314 * @cur_stat: ptr to current stat value
4317 ice_stat_update32(struct ice_hw *hw, u32 reg, bool prev_stat_loaded,
4318 u64 *prev_stat, u64 *cur_stat)
4322 new_data = rd32(hw, reg);
4324 /* device stats are not reset at PFR, they likely will not be zeroed
4325 * when the driver starts. Thus, save the value from the first read
4326 * without adding to the statistic value so that we report stats which
4327 * count up from zero.
4329 if (!prev_stat_loaded) {
4330 *prev_stat = new_data;
4334 /* Calculate the difference between the new and old values, and then
4335 * add it to the software stat value.
4337 if (new_data >= *prev_stat)
4338 *cur_stat += new_data - *prev_stat;
4340 /* to manage the potential roll-over */
4341 *cur_stat += (new_data + BIT_ULL(32)) - *prev_stat;
4343 /* Update the previously stored value to prepare for next read */
4344 *prev_stat = new_data;
4348 * ice_stat_update_repc - read GLV_REPC stats from chip and update stat values
4349 * @hw: ptr to the hardware info
4350 * @vsi_handle: VSI handle
4351 * @prev_stat_loaded: bool to specify if the previous stat values are loaded
4352 * @cur_stats: ptr to current stats structure
4354 * The GLV_REPC statistic register actually tracks two 16bit statistics, and
4355 * thus cannot be read using the normal ice_stat_update32 function.
4357 * Read the GLV_REPC register associated with the given VSI, and update the
4358 * rx_no_desc and rx_error values in the ice_eth_stats structure.
4360 * Because the statistics in GLV_REPC stick at 0xFFFF, the register must be
4361 * cleared each time it's read.
4363 * Note that the GLV_RDPC register also counts the causes that would trigger
4364 * GLV_REPC. However, it does not give the finer grained detail about why the
4365 * packets are being dropped. The GLV_REPC values can be used to distinguish
4366 * whether Rx packets are dropped due to errors or due to no available
4370 ice_stat_update_repc(struct ice_hw *hw, u16 vsi_handle, bool prev_stat_loaded,
4371 struct ice_eth_stats *cur_stats)
4373 u16 vsi_num, no_desc, error_cnt;
4376 if (!ice_is_vsi_valid(hw, vsi_handle))
4379 vsi_num = ice_get_hw_vsi_num(hw, vsi_handle);
4381 /* If we haven't loaded stats yet, just clear the current value */
4382 if (!prev_stat_loaded) {
4383 wr32(hw, GLV_REPC(vsi_num), 0);
4387 repc = rd32(hw, GLV_REPC(vsi_num));
4388 no_desc = (repc & GLV_REPC_NO_DESC_CNT_M) >> GLV_REPC_NO_DESC_CNT_S;
4389 error_cnt = (repc & GLV_REPC_ERROR_CNT_M) >> GLV_REPC_ERROR_CNT_S;
4391 /* Clear the count by writing to the stats register */
4392 wr32(hw, GLV_REPC(vsi_num), 0);
4394 cur_stats->rx_no_desc += no_desc;
4395 cur_stats->rx_errors += error_cnt;
4399 * ice_sched_query_elem - query element information from HW
4400 * @hw: pointer to the HW struct
4401 * @node_teid: node TEID to be queried
4402 * @buf: buffer to element information
4404 * This function queries HW element information
4407 ice_sched_query_elem(struct ice_hw *hw, u32 node_teid,
4408 struct ice_aqc_get_elem *buf)
4410 u16 buf_size, num_elem_ret = 0;
4411 enum ice_status status;
4413 buf_size = sizeof(*buf);
4414 ice_memset(buf, 0, buf_size, ICE_NONDMA_MEM);
4415 buf->generic[0].node_teid = CPU_TO_LE32(node_teid);
4416 status = ice_aq_query_sched_elems(hw, 1, buf, buf_size, &num_elem_ret,
4418 if (status != ICE_SUCCESS || num_elem_ret != 1)
4419 ice_debug(hw, ICE_DBG_SCHED, "query element failed\n");
4424 * ice_get_fw_mode - returns FW mode
4425 * @hw: pointer to the HW struct
4427 enum ice_fw_modes ice_get_fw_mode(struct ice_hw *hw)
4429 #define ICE_FW_MODE_DBG_M BIT(0)
4430 #define ICE_FW_MODE_REC_M BIT(1)
4431 #define ICE_FW_MODE_ROLLBACK_M BIT(2)
4434 /* check the current FW mode */
4435 fw_mode = rd32(hw, GL_MNG_FWSM) & GL_MNG_FWSM_FW_MODES_M;
4437 if (fw_mode & ICE_FW_MODE_DBG_M)
4438 return ICE_FW_MODE_DBG;
4439 else if (fw_mode & ICE_FW_MODE_REC_M)
4440 return ICE_FW_MODE_REC;
4441 else if (fw_mode & ICE_FW_MODE_ROLLBACK_M)
4442 return ICE_FW_MODE_ROLLBACK;
4444 return ICE_FW_MODE_NORMAL;
4448 * ice_fw_supports_link_override
4449 * @hw: pointer to the hardware structure
4451 * Checks if the firmware supports link override
4453 bool ice_fw_supports_link_override(struct ice_hw *hw)
4455 /* Currently, only supported for E810 devices */
4456 if (hw->mac_type != ICE_MAC_E810)
4459 if (hw->api_maj_ver == ICE_FW_API_LINK_OVERRIDE_MAJ) {
4460 if (hw->api_min_ver > ICE_FW_API_LINK_OVERRIDE_MIN)
4462 if (hw->api_min_ver == ICE_FW_API_LINK_OVERRIDE_MIN &&
4463 hw->api_patch >= ICE_FW_API_LINK_OVERRIDE_PATCH)
4465 } else if (hw->api_maj_ver > ICE_FW_API_LINK_OVERRIDE_MAJ) {
4473 * ice_get_link_default_override
4474 * @ldo: pointer to the link default override struct
4475 * @pi: pointer to the port info struct
4477 * Gets the link default override for a port
4480 ice_get_link_default_override(struct ice_link_default_override_tlv *ldo,
4481 struct ice_port_info *pi)
4483 u16 i, tlv, tlv_len, tlv_start, buf, offset;
4484 struct ice_hw *hw = pi->hw;
4485 enum ice_status status;
4487 status = ice_get_pfa_module_tlv(hw, &tlv, &tlv_len,
4488 ICE_SR_LINK_DEFAULT_OVERRIDE_PTR);
4490 ice_debug(hw, ICE_DBG_INIT,
4491 "Failed to read link override TLV.\n");
4495 /* Each port has its own config; calculate for our port */
4496 tlv_start = tlv + pi->lport * ICE_SR_PFA_LINK_OVERRIDE_WORDS +
4497 ICE_SR_PFA_LINK_OVERRIDE_OFFSET;
4499 /* link options first */
4500 status = ice_read_sr_word(hw, tlv_start, &buf);
4502 ice_debug(hw, ICE_DBG_INIT,
4503 "Failed to read override link options.\n");
4506 ldo->options = buf & ICE_LINK_OVERRIDE_OPT_M;
4507 ldo->phy_config = (buf & ICE_LINK_OVERRIDE_PHY_CFG_M) >>
4508 ICE_LINK_OVERRIDE_PHY_CFG_S;
4510 /* link PHY config */
4511 offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_FEC_OFFSET;
4512 status = ice_read_sr_word(hw, offset, &buf);
4514 ice_debug(hw, ICE_DBG_INIT,
4515 "Failed to read override phy config.\n");
4518 ldo->fec_options = buf & ICE_LINK_OVERRIDE_FEC_OPT_M;
4521 offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_PHY_OFFSET;
4522 for (i = 0; i < ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS; i++) {
4523 status = ice_read_sr_word(hw, (offset + i), &buf);
4525 ice_debug(hw, ICE_DBG_INIT,
4526 "Failed to read override link options.\n");
4529 /* shift 16 bits at a time to fill 64 bits */
4530 ldo->phy_type_low |= ((u64)buf << (i * 16));
4533 /* PHY types high */
4534 offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_PHY_OFFSET +
4535 ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS;
4536 for (i = 0; i < ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS; i++) {
4537 status = ice_read_sr_word(hw, (offset + i), &buf);
4539 ice_debug(hw, ICE_DBG_INIT,
4540 "Failed to read override link options.\n");
4543 /* shift 16 bits at a time to fill 64 bits */
4544 ldo->phy_type_high |= ((u64)buf << (i * 16));
4551 * ice_is_phy_caps_an_enabled - check if PHY capabilities autoneg is enabled
4552 * @caps: get PHY capability data
4554 bool ice_is_phy_caps_an_enabled(struct ice_aqc_get_phy_caps_data *caps)
4556 if (caps->caps & ICE_AQC_PHY_AN_MODE ||
4557 caps->low_power_ctrl_an & (ICE_AQC_PHY_AN_EN_CLAUSE28 |
4558 ICE_AQC_PHY_AN_EN_CLAUSE73 |
4559 ICE_AQC_PHY_AN_EN_CLAUSE37))