1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2001-2021 Intel Corporation
5 #include "ice_common.h"
7 #include "ice_adminq_cmd.h"
10 #include "ice_switch.h"
12 #define ICE_PF_RESET_WAIT_COUNT 300
15 * ice_set_mac_type - Sets MAC type
16 * @hw: pointer to the HW structure
18 * This function sets the MAC type of the adapter based on the
19 * vendor ID and device ID stored in the HW structure.
21 static enum ice_status ice_set_mac_type(struct ice_hw *hw)
23 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
25 if (hw->vendor_id != ICE_INTEL_VENDOR_ID)
26 return ICE_ERR_DEVICE_NOT_SUPPORTED;
28 switch (hw->device_id) {
29 case ICE_DEV_ID_E810C_BACKPLANE:
30 case ICE_DEV_ID_E810C_QSFP:
31 case ICE_DEV_ID_E810C_SFP:
32 case ICE_DEV_ID_E810_XXV_BACKPLANE:
33 case ICE_DEV_ID_E810_XXV_QSFP:
34 case ICE_DEV_ID_E810_XXV_SFP:
35 hw->mac_type = ICE_MAC_E810;
37 case ICE_DEV_ID_E822C_10G_BASE_T:
38 case ICE_DEV_ID_E822C_BACKPLANE:
39 case ICE_DEV_ID_E822C_QSFP:
40 case ICE_DEV_ID_E822C_SFP:
41 case ICE_DEV_ID_E822C_SGMII:
42 case ICE_DEV_ID_E822L_10G_BASE_T:
43 case ICE_DEV_ID_E822L_BACKPLANE:
44 case ICE_DEV_ID_E822L_SFP:
45 case ICE_DEV_ID_E822L_SGMII:
46 case ICE_DEV_ID_E823L_10G_BASE_T:
47 case ICE_DEV_ID_E823L_1GBE:
48 case ICE_DEV_ID_E823L_BACKPLANE:
49 case ICE_DEV_ID_E823L_QSFP:
50 case ICE_DEV_ID_E823L_SFP:
51 hw->mac_type = ICE_MAC_GENERIC;
54 hw->mac_type = ICE_MAC_UNKNOWN;
58 ice_debug(hw, ICE_DBG_INIT, "mac_type: %d\n", hw->mac_type);
63 * ice_clear_pf_cfg - Clear PF configuration
64 * @hw: pointer to the hardware structure
66 * Clears any existing PF configuration (VSIs, VSI lists, switch rules, port
67 * configuration, flow director filters, etc.).
69 enum ice_status ice_clear_pf_cfg(struct ice_hw *hw)
71 struct ice_aq_desc desc;
73 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pf_cfg);
75 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
79 * ice_aq_manage_mac_read - manage MAC address read command
80 * @hw: pointer to the HW struct
81 * @buf: a virtual buffer to hold the manage MAC read response
82 * @buf_size: Size of the virtual buffer
83 * @cd: pointer to command details structure or NULL
85 * This function is used to return per PF station MAC address (0x0107).
86 * NOTE: Upon successful completion of this command, MAC address information
87 * is returned in user specified buffer. Please interpret user specified
88 * buffer as "manage_mac_read" response.
89 * Response such as various MAC addresses are stored in HW struct (port.mac)
90 * ice_discover_dev_caps is expected to be called before this function is
93 static enum ice_status
94 ice_aq_manage_mac_read(struct ice_hw *hw, void *buf, u16 buf_size,
97 struct ice_aqc_manage_mac_read_resp *resp;
98 struct ice_aqc_manage_mac_read *cmd;
99 struct ice_aq_desc desc;
100 enum ice_status status;
104 cmd = &desc.params.mac_read;
106 if (buf_size < sizeof(*resp))
107 return ICE_ERR_BUF_TOO_SHORT;
109 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_read);
111 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);
115 resp = (struct ice_aqc_manage_mac_read_resp *)buf;
116 flags = LE16_TO_CPU(cmd->flags) & ICE_AQC_MAN_MAC_READ_M;
118 if (!(flags & ICE_AQC_MAN_MAC_LAN_ADDR_VALID)) {
119 ice_debug(hw, ICE_DBG_LAN, "got invalid MAC address\n");
123 /* A single port can report up to two (LAN and WoL) addresses */
124 for (i = 0; i < cmd->num_addr; i++)
125 if (resp[i].addr_type == ICE_AQC_MAN_MAC_ADDR_TYPE_LAN) {
126 ice_memcpy(hw->port_info->mac.lan_addr,
127 resp[i].mac_addr, ETH_ALEN,
129 ice_memcpy(hw->port_info->mac.perm_addr,
131 ETH_ALEN, ICE_DMA_TO_NONDMA);
138 * ice_aq_get_phy_caps - returns PHY capabilities
139 * @pi: port information structure
140 * @qual_mods: report qualified modules
141 * @report_mode: report mode capabilities
142 * @pcaps: structure for PHY capabilities to be filled
143 * @cd: pointer to command details structure or NULL
145 * Returns the various PHY capabilities supported on the Port (0x0600)
148 ice_aq_get_phy_caps(struct ice_port_info *pi, bool qual_mods, u8 report_mode,
149 struct ice_aqc_get_phy_caps_data *pcaps,
150 struct ice_sq_cd *cd)
152 struct ice_aqc_get_phy_caps *cmd;
153 u16 pcaps_size = sizeof(*pcaps);
154 struct ice_aq_desc desc;
155 enum ice_status status;
158 cmd = &desc.params.get_phy;
160 if (!pcaps || (report_mode & ~ICE_AQC_REPORT_MODE_M) || !pi)
161 return ICE_ERR_PARAM;
164 if (report_mode == ICE_AQC_REPORT_DFLT_CFG &&
165 !ice_fw_supports_report_dflt_cfg(hw))
166 return ICE_ERR_PARAM;
168 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_phy_caps);
171 cmd->param0 |= CPU_TO_LE16(ICE_AQC_GET_PHY_RQM);
173 cmd->param0 |= CPU_TO_LE16(report_mode);
174 status = ice_aq_send_cmd(hw, &desc, pcaps, pcaps_size, cd);
176 ice_debug(hw, ICE_DBG_LINK, "get phy caps - report_mode = 0x%x\n",
178 ice_debug(hw, ICE_DBG_LINK, " phy_type_low = 0x%llx\n",
179 (unsigned long long)LE64_TO_CPU(pcaps->phy_type_low));
180 ice_debug(hw, ICE_DBG_LINK, " phy_type_high = 0x%llx\n",
181 (unsigned long long)LE64_TO_CPU(pcaps->phy_type_high));
182 ice_debug(hw, ICE_DBG_LINK, " caps = 0x%x\n", pcaps->caps);
183 ice_debug(hw, ICE_DBG_LINK, " low_power_ctrl_an = 0x%x\n",
184 pcaps->low_power_ctrl_an);
185 ice_debug(hw, ICE_DBG_LINK, " eee_cap = 0x%x\n", pcaps->eee_cap);
186 ice_debug(hw, ICE_DBG_LINK, " eeer_value = 0x%x\n",
188 ice_debug(hw, ICE_DBG_LINK, " link_fec_options = 0x%x\n",
189 pcaps->link_fec_options);
190 ice_debug(hw, ICE_DBG_LINK, " module_compliance_enforcement = 0x%x\n",
191 pcaps->module_compliance_enforcement);
192 ice_debug(hw, ICE_DBG_LINK, " extended_compliance_code = 0x%x\n",
193 pcaps->extended_compliance_code);
194 ice_debug(hw, ICE_DBG_LINK, " module_type[0] = 0x%x\n",
195 pcaps->module_type[0]);
196 ice_debug(hw, ICE_DBG_LINK, " module_type[1] = 0x%x\n",
197 pcaps->module_type[1]);
198 ice_debug(hw, ICE_DBG_LINK, " module_type[2] = 0x%x\n",
199 pcaps->module_type[2]);
201 if (status == ICE_SUCCESS && report_mode == ICE_AQC_REPORT_TOPO_CAP_MEDIA) {
202 pi->phy.phy_type_low = LE64_TO_CPU(pcaps->phy_type_low);
203 pi->phy.phy_type_high = LE64_TO_CPU(pcaps->phy_type_high);
204 ice_memcpy(pi->phy.link_info.module_type, &pcaps->module_type,
205 sizeof(pi->phy.link_info.module_type),
206 ICE_NONDMA_TO_NONDMA);
213 * ice_aq_get_link_topo_handle - get link topology node return status
214 * @pi: port information structure
215 * @node_type: requested node type
216 * @cd: pointer to command details structure or NULL
218 * Get link topology node return status for specified node type (0x06E0)
220 * Node type cage can be used to determine if cage is present. If AQC
221 * returns error (ENOENT), then no cage present. If no cage present, then
222 * connection type is backplane or BASE-T.
224 static enum ice_status
225 ice_aq_get_link_topo_handle(struct ice_port_info *pi, u8 node_type,
226 struct ice_sq_cd *cd)
228 struct ice_aqc_get_link_topo *cmd;
229 struct ice_aq_desc desc;
231 cmd = &desc.params.get_link_topo;
233 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_topo);
235 cmd->addr.node_type_ctx = (ICE_AQC_LINK_TOPO_NODE_CTX_PORT <<
236 ICE_AQC_LINK_TOPO_NODE_CTX_S);
239 cmd->addr.node_type_ctx |= (ICE_AQC_LINK_TOPO_NODE_TYPE_M & node_type);
241 return ice_aq_send_cmd(pi->hw, &desc, NULL, 0, cd);
245 * ice_is_media_cage_present
246 * @pi: port information structure
248 * Returns true if media cage is present, else false. If no cage, then
249 * media type is backplane or BASE-T.
251 static bool ice_is_media_cage_present(struct ice_port_info *pi)
253 /* Node type cage can be used to determine if cage is present. If AQC
254 * returns error (ENOENT), then no cage present. If no cage present then
255 * connection type is backplane or BASE-T.
257 return !ice_aq_get_link_topo_handle(pi,
258 ICE_AQC_LINK_TOPO_NODE_TYPE_CAGE,
263 * ice_get_media_type - Gets media type
264 * @pi: port information structure
266 static enum ice_media_type ice_get_media_type(struct ice_port_info *pi)
268 struct ice_link_status *hw_link_info;
271 return ICE_MEDIA_UNKNOWN;
273 hw_link_info = &pi->phy.link_info;
274 if (hw_link_info->phy_type_low && hw_link_info->phy_type_high)
275 /* If more than one media type is selected, report unknown */
276 return ICE_MEDIA_UNKNOWN;
278 if (hw_link_info->phy_type_low) {
279 /* 1G SGMII is a special case where some DA cable PHYs
280 * may show this as an option when it really shouldn't
281 * be since SGMII is meant to be between a MAC and a PHY
282 * in a backplane. Try to detect this case and handle it
284 if (hw_link_info->phy_type_low == ICE_PHY_TYPE_LOW_1G_SGMII &&
285 (hw_link_info->module_type[ICE_AQC_MOD_TYPE_IDENT] ==
286 ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_ACTIVE ||
287 hw_link_info->module_type[ICE_AQC_MOD_TYPE_IDENT] ==
288 ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_PASSIVE))
291 switch (hw_link_info->phy_type_low) {
292 case ICE_PHY_TYPE_LOW_1000BASE_SX:
293 case ICE_PHY_TYPE_LOW_1000BASE_LX:
294 case ICE_PHY_TYPE_LOW_10GBASE_SR:
295 case ICE_PHY_TYPE_LOW_10GBASE_LR:
296 case ICE_PHY_TYPE_LOW_10G_SFI_C2C:
297 case ICE_PHY_TYPE_LOW_25GBASE_SR:
298 case ICE_PHY_TYPE_LOW_25GBASE_LR:
299 case ICE_PHY_TYPE_LOW_40GBASE_SR4:
300 case ICE_PHY_TYPE_LOW_40GBASE_LR4:
301 case ICE_PHY_TYPE_LOW_50GBASE_SR2:
302 case ICE_PHY_TYPE_LOW_50GBASE_LR2:
303 case ICE_PHY_TYPE_LOW_50GBASE_SR:
304 case ICE_PHY_TYPE_LOW_50GBASE_FR:
305 case ICE_PHY_TYPE_LOW_50GBASE_LR:
306 case ICE_PHY_TYPE_LOW_100GBASE_SR4:
307 case ICE_PHY_TYPE_LOW_100GBASE_LR4:
308 case ICE_PHY_TYPE_LOW_100GBASE_SR2:
309 case ICE_PHY_TYPE_LOW_100GBASE_DR:
310 return ICE_MEDIA_FIBER;
311 case ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC:
312 case ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC:
313 case ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC:
314 case ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC:
315 case ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC:
316 case ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC:
317 case ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC:
318 case ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC:
319 return ICE_MEDIA_FIBER;
320 case ICE_PHY_TYPE_LOW_100BASE_TX:
321 case ICE_PHY_TYPE_LOW_1000BASE_T:
322 case ICE_PHY_TYPE_LOW_2500BASE_T:
323 case ICE_PHY_TYPE_LOW_5GBASE_T:
324 case ICE_PHY_TYPE_LOW_10GBASE_T:
325 case ICE_PHY_TYPE_LOW_25GBASE_T:
326 return ICE_MEDIA_BASET;
327 case ICE_PHY_TYPE_LOW_10G_SFI_DA:
328 case ICE_PHY_TYPE_LOW_25GBASE_CR:
329 case ICE_PHY_TYPE_LOW_25GBASE_CR_S:
330 case ICE_PHY_TYPE_LOW_25GBASE_CR1:
331 case ICE_PHY_TYPE_LOW_40GBASE_CR4:
332 case ICE_PHY_TYPE_LOW_50GBASE_CR2:
333 case ICE_PHY_TYPE_LOW_50GBASE_CP:
334 case ICE_PHY_TYPE_LOW_100GBASE_CR4:
335 case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4:
336 case ICE_PHY_TYPE_LOW_100GBASE_CP2:
338 case ICE_PHY_TYPE_LOW_25G_AUI_C2C:
339 case ICE_PHY_TYPE_LOW_40G_XLAUI:
340 case ICE_PHY_TYPE_LOW_50G_LAUI2:
341 case ICE_PHY_TYPE_LOW_50G_AUI2:
342 case ICE_PHY_TYPE_LOW_50G_AUI1:
343 case ICE_PHY_TYPE_LOW_100G_AUI4:
344 case ICE_PHY_TYPE_LOW_100G_CAUI4:
345 if (ice_is_media_cage_present(pi))
346 return ICE_MEDIA_AUI;
348 case ICE_PHY_TYPE_LOW_1000BASE_KX:
349 case ICE_PHY_TYPE_LOW_2500BASE_KX:
350 case ICE_PHY_TYPE_LOW_2500BASE_X:
351 case ICE_PHY_TYPE_LOW_5GBASE_KR:
352 case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1:
353 case ICE_PHY_TYPE_LOW_25GBASE_KR:
354 case ICE_PHY_TYPE_LOW_25GBASE_KR1:
355 case ICE_PHY_TYPE_LOW_25GBASE_KR_S:
356 case ICE_PHY_TYPE_LOW_40GBASE_KR4:
357 case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4:
358 case ICE_PHY_TYPE_LOW_50GBASE_KR2:
359 case ICE_PHY_TYPE_LOW_100GBASE_KR4:
360 case ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4:
361 return ICE_MEDIA_BACKPLANE;
364 switch (hw_link_info->phy_type_high) {
365 case ICE_PHY_TYPE_HIGH_100G_AUI2:
366 case ICE_PHY_TYPE_HIGH_100G_CAUI2:
367 if (ice_is_media_cage_present(pi))
368 return ICE_MEDIA_AUI;
370 case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4:
371 return ICE_MEDIA_BACKPLANE;
372 case ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC:
373 case ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC:
374 return ICE_MEDIA_FIBER;
377 return ICE_MEDIA_UNKNOWN;
381 * ice_aq_get_link_info
382 * @pi: port information structure
383 * @ena_lse: enable/disable LinkStatusEvent reporting
384 * @link: pointer to link status structure - optional
385 * @cd: pointer to command details structure or NULL
387 * Get Link Status (0x607). Returns the link status of the adapter.
390 ice_aq_get_link_info(struct ice_port_info *pi, bool ena_lse,
391 struct ice_link_status *link, struct ice_sq_cd *cd)
393 struct ice_aqc_get_link_status_data link_data = { 0 };
394 struct ice_aqc_get_link_status *resp;
395 struct ice_link_status *li_old, *li;
396 enum ice_media_type *hw_media_type;
397 struct ice_fc_info *hw_fc_info;
398 bool tx_pause, rx_pause;
399 struct ice_aq_desc desc;
400 enum ice_status status;
405 return ICE_ERR_PARAM;
407 li_old = &pi->phy.link_info_old;
408 hw_media_type = &pi->phy.media_type;
409 li = &pi->phy.link_info;
410 hw_fc_info = &pi->fc;
412 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_status);
413 cmd_flags = (ena_lse) ? ICE_AQ_LSE_ENA : ICE_AQ_LSE_DIS;
414 resp = &desc.params.get_link_status;
415 resp->cmd_flags = CPU_TO_LE16(cmd_flags);
416 resp->lport_num = pi->lport;
418 status = ice_aq_send_cmd(hw, &desc, &link_data, sizeof(link_data), cd);
420 if (status != ICE_SUCCESS)
423 /* save off old link status information */
426 /* update current link status information */
427 li->link_speed = LE16_TO_CPU(link_data.link_speed);
428 li->phy_type_low = LE64_TO_CPU(link_data.phy_type_low);
429 li->phy_type_high = LE64_TO_CPU(link_data.phy_type_high);
430 *hw_media_type = ice_get_media_type(pi);
431 li->link_info = link_data.link_info;
432 li->an_info = link_data.an_info;
433 li->ext_info = link_data.ext_info;
434 li->max_frame_size = LE16_TO_CPU(link_data.max_frame_size);
435 li->fec_info = link_data.cfg & ICE_AQ_FEC_MASK;
436 li->topo_media_conflict = link_data.topo_media_conflict;
437 li->pacing = link_data.cfg & (ICE_AQ_CFG_PACING_M |
438 ICE_AQ_CFG_PACING_TYPE_M);
441 tx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_TX);
442 rx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_RX);
443 if (tx_pause && rx_pause)
444 hw_fc_info->current_mode = ICE_FC_FULL;
446 hw_fc_info->current_mode = ICE_FC_TX_PAUSE;
448 hw_fc_info->current_mode = ICE_FC_RX_PAUSE;
450 hw_fc_info->current_mode = ICE_FC_NONE;
452 li->lse_ena = !!(resp->cmd_flags & CPU_TO_LE16(ICE_AQ_LSE_IS_ENABLED));
454 ice_debug(hw, ICE_DBG_LINK, "get link info\n");
455 ice_debug(hw, ICE_DBG_LINK, " link_speed = 0x%x\n", li->link_speed);
456 ice_debug(hw, ICE_DBG_LINK, " phy_type_low = 0x%llx\n",
457 (unsigned long long)li->phy_type_low);
458 ice_debug(hw, ICE_DBG_LINK, " phy_type_high = 0x%llx\n",
459 (unsigned long long)li->phy_type_high);
460 ice_debug(hw, ICE_DBG_LINK, " media_type = 0x%x\n", *hw_media_type);
461 ice_debug(hw, ICE_DBG_LINK, " link_info = 0x%x\n", li->link_info);
462 ice_debug(hw, ICE_DBG_LINK, " an_info = 0x%x\n", li->an_info);
463 ice_debug(hw, ICE_DBG_LINK, " ext_info = 0x%x\n", li->ext_info);
464 ice_debug(hw, ICE_DBG_LINK, " fec_info = 0x%x\n", li->fec_info);
465 ice_debug(hw, ICE_DBG_LINK, " lse_ena = 0x%x\n", li->lse_ena);
466 ice_debug(hw, ICE_DBG_LINK, " max_frame = 0x%x\n",
468 ice_debug(hw, ICE_DBG_LINK, " pacing = 0x%x\n", li->pacing);
470 /* save link status information */
474 /* flag cleared so calling functions don't call AQ again */
475 pi->phy.get_link_info = false;
481 * ice_fill_tx_timer_and_fc_thresh
482 * @hw: pointer to the HW struct
483 * @cmd: pointer to MAC cfg structure
485 * Add Tx timer and FC refresh threshold info to Set MAC Config AQ command
489 ice_fill_tx_timer_and_fc_thresh(struct ice_hw *hw,
490 struct ice_aqc_set_mac_cfg *cmd)
492 u16 fc_thres_val, tx_timer_val;
495 /* We read back the transmit timer and fc threshold value of
496 * LFC. Thus, we will use index =
497 * PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX.
499 * Also, because we are opearating on transmit timer and fc
500 * threshold of LFC, we don't turn on any bit in tx_tmr_priority
502 #define IDX_OF_LFC PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX
504 /* Retrieve the transmit timer */
505 val = rd32(hw, PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(IDX_OF_LFC));
507 PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_HSEC_CTL_TX_PAUSE_QUANTA_M;
508 cmd->tx_tmr_value = CPU_TO_LE16(tx_timer_val);
510 /* Retrieve the fc threshold */
511 val = rd32(hw, PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(IDX_OF_LFC));
512 fc_thres_val = val & PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_M;
514 cmd->fc_refresh_threshold = CPU_TO_LE16(fc_thres_val);
519 * @hw: pointer to the HW struct
520 * @max_frame_size: Maximum Frame Size to be supported
521 * @cd: pointer to command details structure or NULL
523 * Set MAC configuration (0x0603)
526 ice_aq_set_mac_cfg(struct ice_hw *hw, u16 max_frame_size, struct ice_sq_cd *cd)
528 struct ice_aqc_set_mac_cfg *cmd;
529 struct ice_aq_desc desc;
531 cmd = &desc.params.set_mac_cfg;
533 if (max_frame_size == 0)
534 return ICE_ERR_PARAM;
536 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_mac_cfg);
538 cmd->max_frame_size = CPU_TO_LE16(max_frame_size);
540 ice_fill_tx_timer_and_fc_thresh(hw, cmd);
542 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
546 * ice_init_fltr_mgmt_struct - initializes filter management list and locks
547 * @hw: pointer to the HW struct
549 enum ice_status ice_init_fltr_mgmt_struct(struct ice_hw *hw)
551 struct ice_switch_info *sw;
552 enum ice_status status;
554 hw->switch_info = (struct ice_switch_info *)
555 ice_malloc(hw, sizeof(*hw->switch_info));
557 sw = hw->switch_info;
560 return ICE_ERR_NO_MEMORY;
562 INIT_LIST_HEAD(&sw->vsi_list_map_head);
563 sw->prof_res_bm_init = 0;
565 status = ice_init_def_sw_recp(hw, &hw->switch_info->recp_list);
567 ice_free(hw, hw->switch_info);
574 * ice_cleanup_fltr_mgmt_single - clears single filter mngt struct
575 * @hw: pointer to the HW struct
576 * @sw: pointer to switch info struct for which function clears filters
579 ice_cleanup_fltr_mgmt_single(struct ice_hw *hw, struct ice_switch_info *sw)
581 struct ice_vsi_list_map_info *v_pos_map;
582 struct ice_vsi_list_map_info *v_tmp_map;
583 struct ice_sw_recipe *recps;
589 LIST_FOR_EACH_ENTRY_SAFE(v_pos_map, v_tmp_map, &sw->vsi_list_map_head,
590 ice_vsi_list_map_info, list_entry) {
591 LIST_DEL(&v_pos_map->list_entry);
592 ice_free(hw, v_pos_map);
594 recps = sw->recp_list;
595 for (i = 0; i < ICE_MAX_NUM_RECIPES; i++) {
596 struct ice_recp_grp_entry *rg_entry, *tmprg_entry;
598 recps[i].root_rid = i;
599 LIST_FOR_EACH_ENTRY_SAFE(rg_entry, tmprg_entry,
600 &recps[i].rg_list, ice_recp_grp_entry,
602 LIST_DEL(&rg_entry->l_entry);
603 ice_free(hw, rg_entry);
606 if (recps[i].adv_rule) {
607 struct ice_adv_fltr_mgmt_list_entry *tmp_entry;
608 struct ice_adv_fltr_mgmt_list_entry *lst_itr;
610 ice_destroy_lock(&recps[i].filt_rule_lock);
611 LIST_FOR_EACH_ENTRY_SAFE(lst_itr, tmp_entry,
612 &recps[i].filt_rules,
613 ice_adv_fltr_mgmt_list_entry,
615 LIST_DEL(&lst_itr->list_entry);
616 ice_free(hw, lst_itr->lkups);
617 ice_free(hw, lst_itr);
620 struct ice_fltr_mgmt_list_entry *lst_itr, *tmp_entry;
622 ice_destroy_lock(&recps[i].filt_rule_lock);
623 LIST_FOR_EACH_ENTRY_SAFE(lst_itr, tmp_entry,
624 &recps[i].filt_rules,
625 ice_fltr_mgmt_list_entry,
627 LIST_DEL(&lst_itr->list_entry);
628 ice_free(hw, lst_itr);
631 if (recps[i].root_buf)
632 ice_free(hw, recps[i].root_buf);
634 ice_rm_sw_replay_rule_info(hw, sw);
635 ice_free(hw, sw->recp_list);
640 * ice_cleanup_all_fltr_mgmt - cleanup filter management list and locks
641 * @hw: pointer to the HW struct
643 void ice_cleanup_fltr_mgmt_struct(struct ice_hw *hw)
645 ice_cleanup_fltr_mgmt_single(hw, hw->switch_info);
649 * ice_get_itr_intrl_gran
650 * @hw: pointer to the HW struct
652 * Determines the ITR/INTRL granularities based on the maximum aggregate
653 * bandwidth according to the device's configuration during power-on.
655 static void ice_get_itr_intrl_gran(struct ice_hw *hw)
657 u8 max_agg_bw = (rd32(hw, GL_PWR_MODE_CTL) &
658 GL_PWR_MODE_CTL_CAR_MAX_BW_M) >>
659 GL_PWR_MODE_CTL_CAR_MAX_BW_S;
661 switch (max_agg_bw) {
662 case ICE_MAX_AGG_BW_200G:
663 case ICE_MAX_AGG_BW_100G:
664 case ICE_MAX_AGG_BW_50G:
665 hw->itr_gran = ICE_ITR_GRAN_ABOVE_25;
666 hw->intrl_gran = ICE_INTRL_GRAN_ABOVE_25;
668 case ICE_MAX_AGG_BW_25G:
669 hw->itr_gran = ICE_ITR_GRAN_MAX_25;
670 hw->intrl_gran = ICE_INTRL_GRAN_MAX_25;
676 * ice_print_rollback_msg - print FW rollback message
677 * @hw: pointer to the hardware structure
679 void ice_print_rollback_msg(struct ice_hw *hw)
681 char nvm_str[ICE_NVM_VER_LEN] = { 0 };
682 struct ice_orom_info *orom;
683 struct ice_nvm_info *nvm;
685 orom = &hw->flash.orom;
686 nvm = &hw->flash.nvm;
688 SNPRINTF(nvm_str, sizeof(nvm_str), "%x.%02x 0x%x %d.%d.%d",
689 nvm->major, nvm->minor, nvm->eetrack, orom->major,
690 orom->build, orom->patch);
692 "Firmware rollback mode detected. Current version is NVM: %s, FW: %d.%d. Device may exhibit limited functionality. Refer to the Intel(R) Ethernet Adapters and Devices User Guide for details on firmware rollback mode\n",
693 nvm_str, hw->fw_maj_ver, hw->fw_min_ver);
697 * ice_init_hw - main hardware initialization routine
698 * @hw: pointer to the hardware structure
700 enum ice_status ice_init_hw(struct ice_hw *hw)
702 struct ice_aqc_get_phy_caps_data *pcaps;
703 enum ice_status status;
707 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
709 /* Set MAC type based on DeviceID */
710 status = ice_set_mac_type(hw);
714 hw->pf_id = (u8)(rd32(hw, PF_FUNC_RID) &
715 PF_FUNC_RID_FUNCTION_NUMBER_M) >>
716 PF_FUNC_RID_FUNCTION_NUMBER_S;
718 status = ice_reset(hw, ICE_RESET_PFR);
722 ice_get_itr_intrl_gran(hw);
724 status = ice_create_all_ctrlq(hw);
726 goto err_unroll_cqinit;
728 status = ice_init_nvm(hw);
730 goto err_unroll_cqinit;
732 if (ice_get_fw_mode(hw) == ICE_FW_MODE_ROLLBACK)
733 ice_print_rollback_msg(hw);
735 status = ice_clear_pf_cfg(hw);
737 goto err_unroll_cqinit;
739 /* Set bit to enable Flow Director filters */
740 wr32(hw, PFQF_FD_ENA, PFQF_FD_ENA_FD_ENA_M);
741 INIT_LIST_HEAD(&hw->fdir_list_head);
743 ice_clear_pxe_mode(hw);
745 status = ice_get_caps(hw);
747 goto err_unroll_cqinit;
749 hw->port_info = (struct ice_port_info *)
750 ice_malloc(hw, sizeof(*hw->port_info));
751 if (!hw->port_info) {
752 status = ICE_ERR_NO_MEMORY;
753 goto err_unroll_cqinit;
756 /* set the back pointer to HW */
757 hw->port_info->hw = hw;
759 /* Initialize port_info struct with switch configuration data */
760 status = ice_get_initial_sw_cfg(hw);
762 goto err_unroll_alloc;
765 /* Query the allocated resources for Tx scheduler */
766 status = ice_sched_query_res_alloc(hw);
768 ice_debug(hw, ICE_DBG_SCHED, "Failed to get scheduler allocated resources\n");
769 goto err_unroll_alloc;
771 ice_sched_get_psm_clk_freq(hw);
773 /* Initialize port_info struct with scheduler data */
774 status = ice_sched_init_port(hw->port_info);
776 goto err_unroll_sched;
777 pcaps = (struct ice_aqc_get_phy_caps_data *)
778 ice_malloc(hw, sizeof(*pcaps));
780 status = ICE_ERR_NO_MEMORY;
781 goto err_unroll_sched;
784 /* Initialize port_info struct with PHY capabilities */
785 status = ice_aq_get_phy_caps(hw->port_info, false,
786 ICE_AQC_REPORT_TOPO_CAP_MEDIA, pcaps, NULL);
789 ice_warn(hw, "Get PHY capabilities failed status = %d, continuing anyway\n",
792 /* Initialize port_info struct with link information */
793 status = ice_aq_get_link_info(hw->port_info, false, NULL, NULL);
795 goto err_unroll_sched;
796 /* need a valid SW entry point to build a Tx tree */
797 if (!hw->sw_entry_point_layer) {
798 ice_debug(hw, ICE_DBG_SCHED, "invalid sw entry point\n");
799 status = ICE_ERR_CFG;
800 goto err_unroll_sched;
802 INIT_LIST_HEAD(&hw->agg_list);
803 /* Initialize max burst size */
804 if (!hw->max_burst_size)
805 ice_cfg_rl_burst_size(hw, ICE_SCHED_DFLT_BURST_SIZE);
806 status = ice_init_fltr_mgmt_struct(hw);
808 goto err_unroll_sched;
810 /* Get MAC information */
811 /* A single port can report up to two (LAN and WoL) addresses */
812 mac_buf = ice_calloc(hw, 2,
813 sizeof(struct ice_aqc_manage_mac_read_resp));
814 mac_buf_len = 2 * sizeof(struct ice_aqc_manage_mac_read_resp);
817 status = ICE_ERR_NO_MEMORY;
818 goto err_unroll_fltr_mgmt_struct;
821 status = ice_aq_manage_mac_read(hw, mac_buf, mac_buf_len, NULL);
822 ice_free(hw, mac_buf);
825 goto err_unroll_fltr_mgmt_struct;
826 /* enable jumbo frame support at MAC level */
827 status = ice_aq_set_mac_cfg(hw, ICE_AQ_SET_MAC_FRAME_SIZE_MAX, NULL);
829 goto err_unroll_fltr_mgmt_struct;
830 /* Obtain counter base index which would be used by flow director */
831 status = ice_alloc_fd_res_cntr(hw, &hw->fd_ctr_base);
833 goto err_unroll_fltr_mgmt_struct;
834 status = ice_init_hw_tbls(hw);
836 goto err_unroll_fltr_mgmt_struct;
837 ice_init_lock(&hw->tnl_lock);
841 err_unroll_fltr_mgmt_struct:
842 ice_cleanup_fltr_mgmt_struct(hw);
844 ice_sched_cleanup_all(hw);
846 ice_free(hw, hw->port_info);
847 hw->port_info = NULL;
849 ice_destroy_all_ctrlq(hw);
854 * ice_deinit_hw - unroll initialization operations done by ice_init_hw
855 * @hw: pointer to the hardware structure
857 * This should be called only during nominal operation, not as a result of
858 * ice_init_hw() failing since ice_init_hw() will take care of unrolling
859 * applicable initializations if it fails for any reason.
861 void ice_deinit_hw(struct ice_hw *hw)
863 ice_free_fd_res_cntr(hw, hw->fd_ctr_base);
864 ice_cleanup_fltr_mgmt_struct(hw);
866 ice_sched_cleanup_all(hw);
867 ice_sched_clear_agg(hw);
869 ice_free_hw_tbls(hw);
870 ice_destroy_lock(&hw->tnl_lock);
873 ice_free(hw, hw->port_info);
874 hw->port_info = NULL;
877 ice_destroy_all_ctrlq(hw);
879 /* Clear VSI contexts if not already cleared */
880 ice_clear_all_vsi_ctx(hw);
884 * ice_check_reset - Check to see if a global reset is complete
885 * @hw: pointer to the hardware structure
887 enum ice_status ice_check_reset(struct ice_hw *hw)
889 u32 cnt, reg = 0, grst_timeout, uld_mask;
891 /* Poll for Device Active state in case a recent CORER, GLOBR,
892 * or EMPR has occurred. The grst delay value is in 100ms units.
893 * Add 1sec for outstanding AQ commands that can take a long time.
895 grst_timeout = ((rd32(hw, GLGEN_RSTCTL) & GLGEN_RSTCTL_GRSTDEL_M) >>
896 GLGEN_RSTCTL_GRSTDEL_S) + 10;
898 for (cnt = 0; cnt < grst_timeout; cnt++) {
899 ice_msec_delay(100, true);
900 reg = rd32(hw, GLGEN_RSTAT);
901 if (!(reg & GLGEN_RSTAT_DEVSTATE_M))
905 if (cnt == grst_timeout) {
906 ice_debug(hw, ICE_DBG_INIT, "Global reset polling failed to complete.\n");
907 return ICE_ERR_RESET_FAILED;
910 #define ICE_RESET_DONE_MASK (GLNVM_ULD_PCIER_DONE_M |\
911 GLNVM_ULD_PCIER_DONE_1_M |\
912 GLNVM_ULD_CORER_DONE_M |\
913 GLNVM_ULD_GLOBR_DONE_M |\
914 GLNVM_ULD_POR_DONE_M |\
915 GLNVM_ULD_POR_DONE_1_M |\
916 GLNVM_ULD_PCIER_DONE_2_M)
918 uld_mask = ICE_RESET_DONE_MASK;
920 /* Device is Active; check Global Reset processes are done */
921 for (cnt = 0; cnt < ICE_PF_RESET_WAIT_COUNT; cnt++) {
922 reg = rd32(hw, GLNVM_ULD) & uld_mask;
923 if (reg == uld_mask) {
924 ice_debug(hw, ICE_DBG_INIT, "Global reset processes done. %d\n", cnt);
927 ice_msec_delay(10, true);
930 if (cnt == ICE_PF_RESET_WAIT_COUNT) {
931 ice_debug(hw, ICE_DBG_INIT, "Wait for Reset Done timed out. GLNVM_ULD = 0x%x\n",
933 return ICE_ERR_RESET_FAILED;
940 * ice_pf_reset - Reset the PF
941 * @hw: pointer to the hardware structure
943 * If a global reset has been triggered, this function checks
944 * for its completion and then issues the PF reset
946 static enum ice_status ice_pf_reset(struct ice_hw *hw)
950 /* If at function entry a global reset was already in progress, i.e.
951 * state is not 'device active' or any of the reset done bits are not
952 * set in GLNVM_ULD, there is no need for a PF Reset; poll until the
953 * global reset is done.
955 if ((rd32(hw, GLGEN_RSTAT) & GLGEN_RSTAT_DEVSTATE_M) ||
956 (rd32(hw, GLNVM_ULD) & ICE_RESET_DONE_MASK) ^ ICE_RESET_DONE_MASK) {
957 /* poll on global reset currently in progress until done */
958 if (ice_check_reset(hw))
959 return ICE_ERR_RESET_FAILED;
965 reg = rd32(hw, PFGEN_CTRL);
967 wr32(hw, PFGEN_CTRL, (reg | PFGEN_CTRL_PFSWR_M));
969 /* Wait for the PFR to complete. The wait time is the global config lock
970 * timeout plus the PFR timeout which will account for a possible reset
971 * that is occurring during a download package operation.
973 for (cnt = 0; cnt < ICE_GLOBAL_CFG_LOCK_TIMEOUT +
974 ICE_PF_RESET_WAIT_COUNT; cnt++) {
975 reg = rd32(hw, PFGEN_CTRL);
976 if (!(reg & PFGEN_CTRL_PFSWR_M))
979 ice_msec_delay(1, true);
982 if (cnt == ICE_PF_RESET_WAIT_COUNT) {
983 ice_debug(hw, ICE_DBG_INIT, "PF reset polling failed to complete.\n");
984 return ICE_ERR_RESET_FAILED;
991 * ice_reset - Perform different types of reset
992 * @hw: pointer to the hardware structure
993 * @req: reset request
995 * This function triggers a reset as specified by the req parameter.
998 * If anything other than a PF reset is triggered, PXE mode is restored.
999 * This has to be cleared using ice_clear_pxe_mode again, once the AQ
1000 * interface has been restored in the rebuild flow.
1002 enum ice_status ice_reset(struct ice_hw *hw, enum ice_reset_req req)
1008 return ice_pf_reset(hw);
1009 case ICE_RESET_CORER:
1010 ice_debug(hw, ICE_DBG_INIT, "CoreR requested\n");
1011 val = GLGEN_RTRIG_CORER_M;
1013 case ICE_RESET_GLOBR:
1014 ice_debug(hw, ICE_DBG_INIT, "GlobalR requested\n");
1015 val = GLGEN_RTRIG_GLOBR_M;
1018 return ICE_ERR_PARAM;
1021 val |= rd32(hw, GLGEN_RTRIG);
1022 wr32(hw, GLGEN_RTRIG, val);
1025 /* wait for the FW to be ready */
1026 return ice_check_reset(hw);
1030 * ice_copy_rxq_ctx_to_hw
1031 * @hw: pointer to the hardware structure
1032 * @ice_rxq_ctx: pointer to the rxq context
1033 * @rxq_index: the index of the Rx queue
1035 * Copies rxq context from dense structure to HW register space
1037 static enum ice_status
1038 ice_copy_rxq_ctx_to_hw(struct ice_hw *hw, u8 *ice_rxq_ctx, u32 rxq_index)
1043 return ICE_ERR_BAD_PTR;
1045 if (rxq_index > QRX_CTRL_MAX_INDEX)
1046 return ICE_ERR_PARAM;
1048 /* Copy each dword separately to HW */
1049 for (i = 0; i < ICE_RXQ_CTX_SIZE_DWORDS; i++) {
1050 wr32(hw, QRX_CONTEXT(i, rxq_index),
1051 *((u32 *)(ice_rxq_ctx + (i * sizeof(u32)))));
1053 ice_debug(hw, ICE_DBG_QCTX, "qrxdata[%d]: %08X\n", i,
1054 *((u32 *)(ice_rxq_ctx + (i * sizeof(u32)))));
1060 /* LAN Rx Queue Context */
1061 static const struct ice_ctx_ele ice_rlan_ctx_info[] = {
1062 /* Field Width LSB */
1063 ICE_CTX_STORE(ice_rlan_ctx, head, 13, 0),
1064 ICE_CTX_STORE(ice_rlan_ctx, cpuid, 8, 13),
1065 ICE_CTX_STORE(ice_rlan_ctx, base, 57, 32),
1066 ICE_CTX_STORE(ice_rlan_ctx, qlen, 13, 89),
1067 ICE_CTX_STORE(ice_rlan_ctx, dbuf, 7, 102),
1068 ICE_CTX_STORE(ice_rlan_ctx, hbuf, 5, 109),
1069 ICE_CTX_STORE(ice_rlan_ctx, dtype, 2, 114),
1070 ICE_CTX_STORE(ice_rlan_ctx, dsize, 1, 116),
1071 ICE_CTX_STORE(ice_rlan_ctx, crcstrip, 1, 117),
1072 ICE_CTX_STORE(ice_rlan_ctx, l2tsel, 1, 119),
1073 ICE_CTX_STORE(ice_rlan_ctx, hsplit_0, 4, 120),
1074 ICE_CTX_STORE(ice_rlan_ctx, hsplit_1, 2, 124),
1075 ICE_CTX_STORE(ice_rlan_ctx, showiv, 1, 127),
1076 ICE_CTX_STORE(ice_rlan_ctx, rxmax, 14, 174),
1077 ICE_CTX_STORE(ice_rlan_ctx, tphrdesc_ena, 1, 193),
1078 ICE_CTX_STORE(ice_rlan_ctx, tphwdesc_ena, 1, 194),
1079 ICE_CTX_STORE(ice_rlan_ctx, tphdata_ena, 1, 195),
1080 ICE_CTX_STORE(ice_rlan_ctx, tphhead_ena, 1, 196),
1081 ICE_CTX_STORE(ice_rlan_ctx, lrxqthresh, 3, 198),
1082 ICE_CTX_STORE(ice_rlan_ctx, prefena, 1, 201),
1088 * @hw: pointer to the hardware structure
1089 * @rlan_ctx: pointer to the rxq context
1090 * @rxq_index: the index of the Rx queue
1092 * Converts rxq context from sparse to dense structure and then writes
1093 * it to HW register space and enables the hardware to prefetch descriptors
1094 * instead of only fetching them on demand
1097 ice_write_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx,
1100 u8 ctx_buf[ICE_RXQ_CTX_SZ] = { 0 };
1103 return ICE_ERR_BAD_PTR;
1105 rlan_ctx->prefena = 1;
1107 ice_set_ctx(hw, (u8 *)rlan_ctx, ctx_buf, ice_rlan_ctx_info);
1108 return ice_copy_rxq_ctx_to_hw(hw, ctx_buf, rxq_index);
1113 * @hw: pointer to the hardware structure
1114 * @rxq_index: the index of the Rx queue to clear
1116 * Clears rxq context in HW register space
1118 enum ice_status ice_clear_rxq_ctx(struct ice_hw *hw, u32 rxq_index)
1122 if (rxq_index > QRX_CTRL_MAX_INDEX)
1123 return ICE_ERR_PARAM;
1125 /* Clear each dword register separately */
1126 for (i = 0; i < ICE_RXQ_CTX_SIZE_DWORDS; i++)
1127 wr32(hw, QRX_CONTEXT(i, rxq_index), 0);
1132 /* LAN Tx Queue Context */
1133 const struct ice_ctx_ele ice_tlan_ctx_info[] = {
1134 /* Field Width LSB */
1135 ICE_CTX_STORE(ice_tlan_ctx, base, 57, 0),
1136 ICE_CTX_STORE(ice_tlan_ctx, port_num, 3, 57),
1137 ICE_CTX_STORE(ice_tlan_ctx, cgd_num, 5, 60),
1138 ICE_CTX_STORE(ice_tlan_ctx, pf_num, 3, 65),
1139 ICE_CTX_STORE(ice_tlan_ctx, vmvf_num, 10, 68),
1140 ICE_CTX_STORE(ice_tlan_ctx, vmvf_type, 2, 78),
1141 ICE_CTX_STORE(ice_tlan_ctx, src_vsi, 10, 80),
1142 ICE_CTX_STORE(ice_tlan_ctx, tsyn_ena, 1, 90),
1143 ICE_CTX_STORE(ice_tlan_ctx, internal_usage_flag, 1, 91),
1144 ICE_CTX_STORE(ice_tlan_ctx, alt_vlan, 1, 92),
1145 ICE_CTX_STORE(ice_tlan_ctx, cpuid, 8, 93),
1146 ICE_CTX_STORE(ice_tlan_ctx, wb_mode, 1, 101),
1147 ICE_CTX_STORE(ice_tlan_ctx, tphrd_desc, 1, 102),
1148 ICE_CTX_STORE(ice_tlan_ctx, tphrd, 1, 103),
1149 ICE_CTX_STORE(ice_tlan_ctx, tphwr_desc, 1, 104),
1150 ICE_CTX_STORE(ice_tlan_ctx, cmpq_id, 9, 105),
1151 ICE_CTX_STORE(ice_tlan_ctx, qnum_in_func, 14, 114),
1152 ICE_CTX_STORE(ice_tlan_ctx, itr_notification_mode, 1, 128),
1153 ICE_CTX_STORE(ice_tlan_ctx, adjust_prof_id, 6, 129),
1154 ICE_CTX_STORE(ice_tlan_ctx, qlen, 13, 135),
1155 ICE_CTX_STORE(ice_tlan_ctx, quanta_prof_idx, 4, 148),
1156 ICE_CTX_STORE(ice_tlan_ctx, tso_ena, 1, 152),
1157 ICE_CTX_STORE(ice_tlan_ctx, tso_qnum, 11, 153),
1158 ICE_CTX_STORE(ice_tlan_ctx, legacy_int, 1, 164),
1159 ICE_CTX_STORE(ice_tlan_ctx, drop_ena, 1, 165),
1160 ICE_CTX_STORE(ice_tlan_ctx, cache_prof_idx, 2, 166),
1161 ICE_CTX_STORE(ice_tlan_ctx, pkt_shaper_prof_idx, 3, 168),
1162 ICE_CTX_STORE(ice_tlan_ctx, int_q_state, 122, 171),
1167 * ice_copy_tx_cmpltnq_ctx_to_hw
1168 * @hw: pointer to the hardware structure
1169 * @ice_tx_cmpltnq_ctx: pointer to the Tx completion queue context
1170 * @tx_cmpltnq_index: the index of the completion queue
1172 * Copies Tx completion queue context from dense structure to HW register space
1174 static enum ice_status
1175 ice_copy_tx_cmpltnq_ctx_to_hw(struct ice_hw *hw, u8 *ice_tx_cmpltnq_ctx,
1176 u32 tx_cmpltnq_index)
1180 if (!ice_tx_cmpltnq_ctx)
1181 return ICE_ERR_BAD_PTR;
1183 if (tx_cmpltnq_index > GLTCLAN_CQ_CNTX0_MAX_INDEX)
1184 return ICE_ERR_PARAM;
1186 /* Copy each dword separately to HW */
1187 for (i = 0; i < ICE_TX_CMPLTNQ_CTX_SIZE_DWORDS; i++) {
1188 wr32(hw, GLTCLAN_CQ_CNTX(i, tx_cmpltnq_index),
1189 *((u32 *)(ice_tx_cmpltnq_ctx + (i * sizeof(u32)))));
1191 ice_debug(hw, ICE_DBG_QCTX, "cmpltnqdata[%d]: %08X\n", i,
1192 *((u32 *)(ice_tx_cmpltnq_ctx + (i * sizeof(u32)))));
1198 /* LAN Tx Completion Queue Context */
1199 static const struct ice_ctx_ele ice_tx_cmpltnq_ctx_info[] = {
1200 /* Field Width LSB */
1201 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, base, 57, 0),
1202 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, q_len, 18, 64),
1203 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, generation, 1, 96),
1204 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, wrt_ptr, 22, 97),
1205 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, pf_num, 3, 128),
1206 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, vmvf_num, 10, 131),
1207 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, vmvf_type, 2, 141),
1208 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, tph_desc_wr, 1, 160),
1209 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, cpuid, 8, 161),
1210 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, cmpltn_cache, 512, 192),
1215 * ice_write_tx_cmpltnq_ctx
1216 * @hw: pointer to the hardware structure
1217 * @tx_cmpltnq_ctx: pointer to the completion queue context
1218 * @tx_cmpltnq_index: the index of the completion queue
1220 * Converts completion queue context from sparse to dense structure and then
1221 * writes it to HW register space
1224 ice_write_tx_cmpltnq_ctx(struct ice_hw *hw,
1225 struct ice_tx_cmpltnq_ctx *tx_cmpltnq_ctx,
1226 u32 tx_cmpltnq_index)
1228 u8 ctx_buf[ICE_TX_CMPLTNQ_CTX_SIZE_DWORDS * sizeof(u32)] = { 0 };
1230 ice_set_ctx(hw, (u8 *)tx_cmpltnq_ctx, ctx_buf, ice_tx_cmpltnq_ctx_info);
1231 return ice_copy_tx_cmpltnq_ctx_to_hw(hw, ctx_buf, tx_cmpltnq_index);
1235 * ice_clear_tx_cmpltnq_ctx
1236 * @hw: pointer to the hardware structure
1237 * @tx_cmpltnq_index: the index of the completion queue to clear
1239 * Clears Tx completion queue context in HW register space
1242 ice_clear_tx_cmpltnq_ctx(struct ice_hw *hw, u32 tx_cmpltnq_index)
1246 if (tx_cmpltnq_index > GLTCLAN_CQ_CNTX0_MAX_INDEX)
1247 return ICE_ERR_PARAM;
1249 /* Clear each dword register separately */
1250 for (i = 0; i < ICE_TX_CMPLTNQ_CTX_SIZE_DWORDS; i++)
1251 wr32(hw, GLTCLAN_CQ_CNTX(i, tx_cmpltnq_index), 0);
1257 * ice_copy_tx_drbell_q_ctx_to_hw
1258 * @hw: pointer to the hardware structure
1259 * @ice_tx_drbell_q_ctx: pointer to the doorbell queue context
1260 * @tx_drbell_q_index: the index of the doorbell queue
1262 * Copies doorbell queue context from dense structure to HW register space
1264 static enum ice_status
1265 ice_copy_tx_drbell_q_ctx_to_hw(struct ice_hw *hw, u8 *ice_tx_drbell_q_ctx,
1266 u32 tx_drbell_q_index)
1270 if (!ice_tx_drbell_q_ctx)
1271 return ICE_ERR_BAD_PTR;
1273 if (tx_drbell_q_index > QTX_COMM_DBLQ_DBELL_MAX_INDEX)
1274 return ICE_ERR_PARAM;
1276 /* Copy each dword separately to HW */
1277 for (i = 0; i < ICE_TX_DRBELL_Q_CTX_SIZE_DWORDS; i++) {
1278 wr32(hw, QTX_COMM_DBLQ_CNTX(i, tx_drbell_q_index),
1279 *((u32 *)(ice_tx_drbell_q_ctx + (i * sizeof(u32)))));
1281 ice_debug(hw, ICE_DBG_QCTX, "tx_drbell_qdata[%d]: %08X\n", i,
1282 *((u32 *)(ice_tx_drbell_q_ctx + (i * sizeof(u32)))));
1288 /* LAN Tx Doorbell Queue Context info */
1289 static const struct ice_ctx_ele ice_tx_drbell_q_ctx_info[] = {
1290 /* Field Width LSB */
1291 ICE_CTX_STORE(ice_tx_drbell_q_ctx, base, 57, 0),
1292 ICE_CTX_STORE(ice_tx_drbell_q_ctx, ring_len, 13, 64),
1293 ICE_CTX_STORE(ice_tx_drbell_q_ctx, pf_num, 3, 80),
1294 ICE_CTX_STORE(ice_tx_drbell_q_ctx, vf_num, 8, 84),
1295 ICE_CTX_STORE(ice_tx_drbell_q_ctx, vmvf_type, 2, 94),
1296 ICE_CTX_STORE(ice_tx_drbell_q_ctx, cpuid, 8, 96),
1297 ICE_CTX_STORE(ice_tx_drbell_q_ctx, tph_desc_rd, 1, 104),
1298 ICE_CTX_STORE(ice_tx_drbell_q_ctx, tph_desc_wr, 1, 108),
1299 ICE_CTX_STORE(ice_tx_drbell_q_ctx, db_q_en, 1, 112),
1300 ICE_CTX_STORE(ice_tx_drbell_q_ctx, rd_head, 13, 128),
1301 ICE_CTX_STORE(ice_tx_drbell_q_ctx, rd_tail, 13, 144),
1306 * ice_write_tx_drbell_q_ctx
1307 * @hw: pointer to the hardware structure
1308 * @tx_drbell_q_ctx: pointer to the doorbell queue context
1309 * @tx_drbell_q_index: the index of the doorbell queue
1311 * Converts doorbell queue context from sparse to dense structure and then
1312 * writes it to HW register space
1315 ice_write_tx_drbell_q_ctx(struct ice_hw *hw,
1316 struct ice_tx_drbell_q_ctx *tx_drbell_q_ctx,
1317 u32 tx_drbell_q_index)
1319 u8 ctx_buf[ICE_TX_DRBELL_Q_CTX_SIZE_DWORDS * sizeof(u32)] = { 0 };
1321 ice_set_ctx(hw, (u8 *)tx_drbell_q_ctx, ctx_buf,
1322 ice_tx_drbell_q_ctx_info);
1323 return ice_copy_tx_drbell_q_ctx_to_hw(hw, ctx_buf, tx_drbell_q_index);
1327 * ice_clear_tx_drbell_q_ctx
1328 * @hw: pointer to the hardware structure
1329 * @tx_drbell_q_index: the index of the doorbell queue to clear
1331 * Clears doorbell queue context in HW register space
1334 ice_clear_tx_drbell_q_ctx(struct ice_hw *hw, u32 tx_drbell_q_index)
1338 if (tx_drbell_q_index > QTX_COMM_DBLQ_DBELL_MAX_INDEX)
1339 return ICE_ERR_PARAM;
1341 /* Clear each dword register separately */
1342 for (i = 0; i < ICE_TX_DRBELL_Q_CTX_SIZE_DWORDS; i++)
1343 wr32(hw, QTX_COMM_DBLQ_CNTX(i, tx_drbell_q_index), 0);
1348 /* FW Admin Queue command wrappers */
1351 * ice_should_retry_sq_send_cmd
1352 * @opcode: AQ opcode
1354 * Decide if we should retry the send command routine for the ATQ, depending
1357 static bool ice_should_retry_sq_send_cmd(u16 opcode)
1360 case ice_aqc_opc_get_link_topo:
1361 case ice_aqc_opc_lldp_stop:
1362 case ice_aqc_opc_lldp_start:
1363 case ice_aqc_opc_lldp_filter_ctrl:
1371 * ice_sq_send_cmd_retry - send command to Control Queue (ATQ)
1372 * @hw: pointer to the HW struct
1373 * @cq: pointer to the specific Control queue
1374 * @desc: prefilled descriptor describing the command
1375 * @buf: buffer to use for indirect commands (or NULL for direct commands)
1376 * @buf_size: size of buffer for indirect commands (or 0 for direct commands)
1377 * @cd: pointer to command details structure
1379 * Retry sending the FW Admin Queue command, multiple times, to the FW Admin
1380 * Queue if the EBUSY AQ error is returned.
1382 static enum ice_status
1383 ice_sq_send_cmd_retry(struct ice_hw *hw, struct ice_ctl_q_info *cq,
1384 struct ice_aq_desc *desc, void *buf, u16 buf_size,
1385 struct ice_sq_cd *cd)
1387 struct ice_aq_desc desc_cpy;
1388 enum ice_status status;
1389 bool is_cmd_for_retry;
1394 opcode = LE16_TO_CPU(desc->opcode);
1395 is_cmd_for_retry = ice_should_retry_sq_send_cmd(opcode);
1396 ice_memset(&desc_cpy, 0, sizeof(desc_cpy), ICE_NONDMA_MEM);
1398 if (is_cmd_for_retry) {
1400 buf_cpy = (u8 *)ice_malloc(hw, buf_size);
1402 return ICE_ERR_NO_MEMORY;
1405 ice_memcpy(&desc_cpy, desc, sizeof(desc_cpy),
1406 ICE_NONDMA_TO_NONDMA);
1410 status = ice_sq_send_cmd(hw, cq, desc, buf, buf_size, cd);
1412 if (!is_cmd_for_retry || status == ICE_SUCCESS ||
1413 hw->adminq.sq_last_status != ICE_AQ_RC_EBUSY)
1417 ice_memcpy(buf, buf_cpy, buf_size,
1418 ICE_NONDMA_TO_NONDMA);
1420 ice_memcpy(desc, &desc_cpy, sizeof(desc_cpy),
1421 ICE_NONDMA_TO_NONDMA);
1423 ice_msec_delay(ICE_SQ_SEND_DELAY_TIME_MS, false);
1425 } while (++idx < ICE_SQ_SEND_MAX_EXECUTE);
1428 ice_free(hw, buf_cpy);
1434 * ice_aq_send_cmd - send FW Admin Queue command to FW Admin Queue
1435 * @hw: pointer to the HW struct
1436 * @desc: descriptor describing the command
1437 * @buf: buffer to use for indirect commands (NULL for direct commands)
1438 * @buf_size: size of buffer for indirect commands (0 for direct commands)
1439 * @cd: pointer to command details structure
1441 * Helper function to send FW Admin Queue commands to the FW Admin Queue.
1444 ice_aq_send_cmd(struct ice_hw *hw, struct ice_aq_desc *desc, void *buf,
1445 u16 buf_size, struct ice_sq_cd *cd)
1447 if (hw->aq_send_cmd_fn) {
1448 enum ice_status status = ICE_ERR_NOT_READY;
1449 u16 retval = ICE_AQ_RC_OK;
1451 ice_acquire_lock(&hw->adminq.sq_lock);
1452 if (!hw->aq_send_cmd_fn(hw->aq_send_cmd_param, desc,
1454 retval = LE16_TO_CPU(desc->retval);
1455 /* strip off FW internal code */
1458 if (retval == ICE_AQ_RC_OK)
1459 status = ICE_SUCCESS;
1461 status = ICE_ERR_AQ_ERROR;
1464 hw->adminq.sq_last_status = (enum ice_aq_err)retval;
1465 ice_release_lock(&hw->adminq.sq_lock);
1469 return ice_sq_send_cmd_retry(hw, &hw->adminq, desc, buf, buf_size, cd);
1474 * @hw: pointer to the HW struct
1475 * @cd: pointer to command details structure or NULL
1477 * Get the firmware version (0x0001) from the admin queue commands
1479 enum ice_status ice_aq_get_fw_ver(struct ice_hw *hw, struct ice_sq_cd *cd)
1481 struct ice_aqc_get_ver *resp;
1482 struct ice_aq_desc desc;
1483 enum ice_status status;
1485 resp = &desc.params.get_ver;
1487 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_ver);
1489 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
1492 hw->fw_branch = resp->fw_branch;
1493 hw->fw_maj_ver = resp->fw_major;
1494 hw->fw_min_ver = resp->fw_minor;
1495 hw->fw_patch = resp->fw_patch;
1496 hw->fw_build = LE32_TO_CPU(resp->fw_build);
1497 hw->api_branch = resp->api_branch;
1498 hw->api_maj_ver = resp->api_major;
1499 hw->api_min_ver = resp->api_minor;
1500 hw->api_patch = resp->api_patch;
1507 * ice_aq_send_driver_ver
1508 * @hw: pointer to the HW struct
1509 * @dv: driver's major, minor version
1510 * @cd: pointer to command details structure or NULL
1512 * Send the driver version (0x0002) to the firmware
1515 ice_aq_send_driver_ver(struct ice_hw *hw, struct ice_driver_ver *dv,
1516 struct ice_sq_cd *cd)
1518 struct ice_aqc_driver_ver *cmd;
1519 struct ice_aq_desc desc;
1522 cmd = &desc.params.driver_ver;
1525 return ICE_ERR_PARAM;
1527 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_driver_ver);
1529 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
1530 cmd->major_ver = dv->major_ver;
1531 cmd->minor_ver = dv->minor_ver;
1532 cmd->build_ver = dv->build_ver;
1533 cmd->subbuild_ver = dv->subbuild_ver;
1536 while (len < sizeof(dv->driver_string) &&
1537 IS_ASCII(dv->driver_string[len]) && dv->driver_string[len])
1540 return ice_aq_send_cmd(hw, &desc, dv->driver_string, len, cd);
1545 * @hw: pointer to the HW struct
1546 * @unloading: is the driver unloading itself
1548 * Tell the Firmware that we're shutting down the AdminQ and whether
1549 * or not the driver is unloading as well (0x0003).
1551 enum ice_status ice_aq_q_shutdown(struct ice_hw *hw, bool unloading)
1553 struct ice_aqc_q_shutdown *cmd;
1554 struct ice_aq_desc desc;
1556 cmd = &desc.params.q_shutdown;
1558 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_q_shutdown);
1561 cmd->driver_unloading = ICE_AQC_DRIVER_UNLOADING;
1563 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
1568 * @hw: pointer to the HW struct
1570 * @access: access type
1571 * @sdp_number: resource number
1572 * @timeout: the maximum time in ms that the driver may hold the resource
1573 * @cd: pointer to command details structure or NULL
1575 * Requests common resource using the admin queue commands (0x0008).
1576 * When attempting to acquire the Global Config Lock, the driver can
1577 * learn of three states:
1578 * 1) ICE_SUCCESS - acquired lock, and can perform download package
1579 * 2) ICE_ERR_AQ_ERROR - did not get lock, driver should fail to load
1580 * 3) ICE_ERR_AQ_NO_WORK - did not get lock, but another driver has
1581 * successfully downloaded the package; the driver does
1582 * not have to download the package and can continue
1585 * Note that if the caller is in an acquire lock, perform action, release lock
1586 * phase of operation, it is possible that the FW may detect a timeout and issue
1587 * a CORER. In this case, the driver will receive a CORER interrupt and will
1588 * have to determine its cause. The calling thread that is handling this flow
1589 * will likely get an error propagated back to it indicating the Download
1590 * Package, Update Package or the Release Resource AQ commands timed out.
1592 static enum ice_status
1593 ice_aq_req_res(struct ice_hw *hw, enum ice_aq_res_ids res,
1594 enum ice_aq_res_access_type access, u8 sdp_number, u32 *timeout,
1595 struct ice_sq_cd *cd)
1597 struct ice_aqc_req_res *cmd_resp;
1598 struct ice_aq_desc desc;
1599 enum ice_status status;
1601 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
1603 cmd_resp = &desc.params.res_owner;
1605 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_req_res);
1607 cmd_resp->res_id = CPU_TO_LE16(res);
1608 cmd_resp->access_type = CPU_TO_LE16(access);
1609 cmd_resp->res_number = CPU_TO_LE32(sdp_number);
1610 cmd_resp->timeout = CPU_TO_LE32(*timeout);
1613 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
1615 /* The completion specifies the maximum time in ms that the driver
1616 * may hold the resource in the Timeout field.
1619 /* Global config lock response utilizes an additional status field.
1621 * If the Global config lock resource is held by some other driver, the
1622 * command completes with ICE_AQ_RES_GLBL_IN_PROG in the status field
1623 * and the timeout field indicates the maximum time the current owner
1624 * of the resource has to free it.
1626 if (res == ICE_GLOBAL_CFG_LOCK_RES_ID) {
1627 if (LE16_TO_CPU(cmd_resp->status) == ICE_AQ_RES_GLBL_SUCCESS) {
1628 *timeout = LE32_TO_CPU(cmd_resp->timeout);
1630 } else if (LE16_TO_CPU(cmd_resp->status) ==
1631 ICE_AQ_RES_GLBL_IN_PROG) {
1632 *timeout = LE32_TO_CPU(cmd_resp->timeout);
1633 return ICE_ERR_AQ_ERROR;
1634 } else if (LE16_TO_CPU(cmd_resp->status) ==
1635 ICE_AQ_RES_GLBL_DONE) {
1636 return ICE_ERR_AQ_NO_WORK;
1639 /* invalid FW response, force a timeout immediately */
1641 return ICE_ERR_AQ_ERROR;
1644 /* If the resource is held by some other driver, the command completes
1645 * with a busy return value and the timeout field indicates the maximum
1646 * time the current owner of the resource has to free it.
1648 if (!status || hw->adminq.sq_last_status == ICE_AQ_RC_EBUSY)
1649 *timeout = LE32_TO_CPU(cmd_resp->timeout);
1655 * ice_aq_release_res
1656 * @hw: pointer to the HW struct
1658 * @sdp_number: resource number
1659 * @cd: pointer to command details structure or NULL
1661 * release common resource using the admin queue commands (0x0009)
1663 static enum ice_status
1664 ice_aq_release_res(struct ice_hw *hw, enum ice_aq_res_ids res, u8 sdp_number,
1665 struct ice_sq_cd *cd)
1667 struct ice_aqc_req_res *cmd;
1668 struct ice_aq_desc desc;
1670 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
1672 cmd = &desc.params.res_owner;
1674 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_release_res);
1676 cmd->res_id = CPU_TO_LE16(res);
1677 cmd->res_number = CPU_TO_LE32(sdp_number);
1679 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
1684 * @hw: pointer to the HW structure
1686 * @access: access type (read or write)
1687 * @timeout: timeout in milliseconds
1689 * This function will attempt to acquire the ownership of a resource.
1692 ice_acquire_res(struct ice_hw *hw, enum ice_aq_res_ids res,
1693 enum ice_aq_res_access_type access, u32 timeout)
1695 #define ICE_RES_POLLING_DELAY_MS 10
1696 u32 delay = ICE_RES_POLLING_DELAY_MS;
1697 u32 time_left = timeout;
1698 enum ice_status status;
1700 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
1702 status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL);
1704 /* A return code of ICE_ERR_AQ_NO_WORK means that another driver has
1705 * previously acquired the resource and performed any necessary updates;
1706 * in this case the caller does not obtain the resource and has no
1707 * further work to do.
1709 if (status == ICE_ERR_AQ_NO_WORK)
1710 goto ice_acquire_res_exit;
1713 ice_debug(hw, ICE_DBG_RES, "resource %d acquire type %d failed.\n", res, access);
1715 /* If necessary, poll until the current lock owner timeouts */
1716 timeout = time_left;
1717 while (status && timeout && time_left) {
1718 ice_msec_delay(delay, true);
1719 timeout = (timeout > delay) ? timeout - delay : 0;
1720 status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL);
1722 if (status == ICE_ERR_AQ_NO_WORK)
1723 /* lock free, but no work to do */
1730 if (status && status != ICE_ERR_AQ_NO_WORK)
1731 ice_debug(hw, ICE_DBG_RES, "resource acquire timed out.\n");
1733 ice_acquire_res_exit:
1734 if (status == ICE_ERR_AQ_NO_WORK) {
1735 if (access == ICE_RES_WRITE)
1736 ice_debug(hw, ICE_DBG_RES, "resource indicates no work to do.\n");
1738 ice_debug(hw, ICE_DBG_RES, "Warning: ICE_ERR_AQ_NO_WORK not expected\n");
1745 * @hw: pointer to the HW structure
1748 * This function will release a resource using the proper Admin Command.
1750 void ice_release_res(struct ice_hw *hw, enum ice_aq_res_ids res)
1752 enum ice_status status;
1753 u32 total_delay = 0;
1755 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
1757 status = ice_aq_release_res(hw, res, 0, NULL);
1759 /* there are some rare cases when trying to release the resource
1760 * results in an admin queue timeout, so handle them correctly
1762 while ((status == ICE_ERR_AQ_TIMEOUT) &&
1763 (total_delay < hw->adminq.sq_cmd_timeout)) {
1764 ice_msec_delay(1, true);
1765 status = ice_aq_release_res(hw, res, 0, NULL);
1771 * ice_aq_alloc_free_res - command to allocate/free resources
1772 * @hw: pointer to the HW struct
1773 * @num_entries: number of resource entries in buffer
1774 * @buf: Indirect buffer to hold data parameters and response
1775 * @buf_size: size of buffer for indirect commands
1776 * @opc: pass in the command opcode
1777 * @cd: pointer to command details structure or NULL
1779 * Helper function to allocate/free resources using the admin queue commands
1782 ice_aq_alloc_free_res(struct ice_hw *hw, u16 num_entries,
1783 struct ice_aqc_alloc_free_res_elem *buf, u16 buf_size,
1784 enum ice_adminq_opc opc, struct ice_sq_cd *cd)
1786 struct ice_aqc_alloc_free_res_cmd *cmd;
1787 struct ice_aq_desc desc;
1789 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
1791 cmd = &desc.params.sw_res_ctrl;
1794 return ICE_ERR_PARAM;
1796 if (buf_size < FLEX_ARRAY_SIZE(buf, elem, num_entries))
1797 return ICE_ERR_PARAM;
1799 ice_fill_dflt_direct_cmd_desc(&desc, opc);
1801 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
1803 cmd->num_entries = CPU_TO_LE16(num_entries);
1805 return ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);
1809 * ice_alloc_hw_res - allocate resource
1810 * @hw: pointer to the HW struct
1811 * @type: type of resource
1812 * @num: number of resources to allocate
1813 * @btm: allocate from bottom
1814 * @res: pointer to array that will receive the resources
1817 ice_alloc_hw_res(struct ice_hw *hw, u16 type, u16 num, bool btm, u16 *res)
1819 struct ice_aqc_alloc_free_res_elem *buf;
1820 enum ice_status status;
1823 buf_len = ice_struct_size(buf, elem, num);
1824 buf = (struct ice_aqc_alloc_free_res_elem *)ice_malloc(hw, buf_len);
1826 return ICE_ERR_NO_MEMORY;
1828 /* Prepare buffer to allocate resource. */
1829 buf->num_elems = CPU_TO_LE16(num);
1830 buf->res_type = CPU_TO_LE16(type | ICE_AQC_RES_TYPE_FLAG_DEDICATED |
1831 ICE_AQC_RES_TYPE_FLAG_IGNORE_INDEX);
1833 buf->res_type |= CPU_TO_LE16(ICE_AQC_RES_TYPE_FLAG_SCAN_BOTTOM);
1835 status = ice_aq_alloc_free_res(hw, 1, buf, buf_len,
1836 ice_aqc_opc_alloc_res, NULL);
1838 goto ice_alloc_res_exit;
1840 ice_memcpy(res, buf->elem, sizeof(*buf->elem) * num,
1841 ICE_NONDMA_TO_NONDMA);
1849 * ice_free_hw_res - free allocated HW resource
1850 * @hw: pointer to the HW struct
1851 * @type: type of resource to free
1852 * @num: number of resources
1853 * @res: pointer to array that contains the resources to free
1855 enum ice_status ice_free_hw_res(struct ice_hw *hw, u16 type, u16 num, u16 *res)
1857 struct ice_aqc_alloc_free_res_elem *buf;
1858 enum ice_status status;
1861 buf_len = ice_struct_size(buf, elem, num);
1862 buf = (struct ice_aqc_alloc_free_res_elem *)ice_malloc(hw, buf_len);
1864 return ICE_ERR_NO_MEMORY;
1866 /* Prepare buffer to free resource. */
1867 buf->num_elems = CPU_TO_LE16(num);
1868 buf->res_type = CPU_TO_LE16(type);
1869 ice_memcpy(buf->elem, res, sizeof(*buf->elem) * num,
1870 ICE_NONDMA_TO_NONDMA);
1872 status = ice_aq_alloc_free_res(hw, num, buf, buf_len,
1873 ice_aqc_opc_free_res, NULL);
1875 ice_debug(hw, ICE_DBG_SW, "CQ CMD Buffer:\n");
1882 * ice_get_num_per_func - determine number of resources per PF
1883 * @hw: pointer to the HW structure
1884 * @max: value to be evenly split between each PF
1886 * Determine the number of valid functions by going through the bitmap returned
1887 * from parsing capabilities and use this to calculate the number of resources
1888 * per PF based on the max value passed in.
1890 static u32 ice_get_num_per_func(struct ice_hw *hw, u32 max)
1894 #define ICE_CAPS_VALID_FUNCS_M 0xFF
1895 funcs = ice_hweight8(hw->dev_caps.common_cap.valid_functions &
1896 ICE_CAPS_VALID_FUNCS_M);
1905 * ice_parse_common_caps - parse common device/function capabilities
1906 * @hw: pointer to the HW struct
1907 * @caps: pointer to common capabilities structure
1908 * @elem: the capability element to parse
1909 * @prefix: message prefix for tracing capabilities
1911 * Given a capability element, extract relevant details into the common
1912 * capability structure.
1914 * Returns: true if the capability matches one of the common capability ids,
1918 ice_parse_common_caps(struct ice_hw *hw, struct ice_hw_common_caps *caps,
1919 struct ice_aqc_list_caps_elem *elem, const char *prefix)
1921 u32 logical_id = LE32_TO_CPU(elem->logical_id);
1922 u32 phys_id = LE32_TO_CPU(elem->phys_id);
1923 u32 number = LE32_TO_CPU(elem->number);
1924 u16 cap = LE16_TO_CPU(elem->cap);
1928 case ICE_AQC_CAPS_VALID_FUNCTIONS:
1929 caps->valid_functions = number;
1930 ice_debug(hw, ICE_DBG_INIT, "%s: valid_functions (bitmap) = %d\n", prefix,
1931 caps->valid_functions);
1933 case ICE_AQC_CAPS_DCB:
1934 caps->dcb = (number == 1);
1935 caps->active_tc_bitmap = logical_id;
1936 caps->maxtc = phys_id;
1937 ice_debug(hw, ICE_DBG_INIT, "%s: dcb = %d\n", prefix, caps->dcb);
1938 ice_debug(hw, ICE_DBG_INIT, "%s: active_tc_bitmap = %d\n", prefix,
1939 caps->active_tc_bitmap);
1940 ice_debug(hw, ICE_DBG_INIT, "%s: maxtc = %d\n", prefix, caps->maxtc);
1942 case ICE_AQC_CAPS_RSS:
1943 caps->rss_table_size = number;
1944 caps->rss_table_entry_width = logical_id;
1945 ice_debug(hw, ICE_DBG_INIT, "%s: rss_table_size = %d\n", prefix,
1946 caps->rss_table_size);
1947 ice_debug(hw, ICE_DBG_INIT, "%s: rss_table_entry_width = %d\n", prefix,
1948 caps->rss_table_entry_width);
1950 case ICE_AQC_CAPS_RXQS:
1951 caps->num_rxq = number;
1952 caps->rxq_first_id = phys_id;
1953 ice_debug(hw, ICE_DBG_INIT, "%s: num_rxq = %d\n", prefix,
1955 ice_debug(hw, ICE_DBG_INIT, "%s: rxq_first_id = %d\n", prefix,
1956 caps->rxq_first_id);
1958 case ICE_AQC_CAPS_TXQS:
1959 caps->num_txq = number;
1960 caps->txq_first_id = phys_id;
1961 ice_debug(hw, ICE_DBG_INIT, "%s: num_txq = %d\n", prefix,
1963 ice_debug(hw, ICE_DBG_INIT, "%s: txq_first_id = %d\n", prefix,
1964 caps->txq_first_id);
1966 case ICE_AQC_CAPS_MSIX:
1967 caps->num_msix_vectors = number;
1968 caps->msix_vector_first_id = phys_id;
1969 ice_debug(hw, ICE_DBG_INIT, "%s: num_msix_vectors = %d\n", prefix,
1970 caps->num_msix_vectors);
1971 ice_debug(hw, ICE_DBG_INIT, "%s: msix_vector_first_id = %d\n", prefix,
1972 caps->msix_vector_first_id);
1974 case ICE_AQC_CAPS_NVM_MGMT:
1975 caps->sec_rev_disabled =
1976 (number & ICE_NVM_MGMT_SEC_REV_DISABLED) ?
1978 ice_debug(hw, ICE_DBG_INIT, "%s: sec_rev_disabled = %d\n", prefix,
1979 caps->sec_rev_disabled);
1980 caps->update_disabled =
1981 (number & ICE_NVM_MGMT_UPDATE_DISABLED) ?
1983 ice_debug(hw, ICE_DBG_INIT, "%s: update_disabled = %d\n", prefix,
1984 caps->update_disabled);
1985 caps->nvm_unified_update =
1986 (number & ICE_NVM_MGMT_UNIFIED_UPD_SUPPORT) ?
1988 ice_debug(hw, ICE_DBG_INIT, "%s: nvm_unified_update = %d\n", prefix,
1989 caps->nvm_unified_update);
1991 case ICE_AQC_CAPS_MAX_MTU:
1992 caps->max_mtu = number;
1993 ice_debug(hw, ICE_DBG_INIT, "%s: max_mtu = %d\n",
1994 prefix, caps->max_mtu);
1997 /* Not one of the recognized common capabilities */
2005 * ice_recalc_port_limited_caps - Recalculate port limited capabilities
2006 * @hw: pointer to the HW structure
2007 * @caps: pointer to capabilities structure to fix
2009 * Re-calculate the capabilities that are dependent on the number of physical
2010 * ports; i.e. some features are not supported or function differently on
2011 * devices with more than 4 ports.
2014 ice_recalc_port_limited_caps(struct ice_hw *hw, struct ice_hw_common_caps *caps)
2016 /* This assumes device capabilities are always scanned before function
2017 * capabilities during the initialization flow.
2019 if (hw->dev_caps.num_funcs > 4) {
2020 /* Max 4 TCs per port */
2022 ice_debug(hw, ICE_DBG_INIT, "reducing maxtc to %d (based on #ports)\n",
2028 * ice_parse_vsi_func_caps - Parse ICE_AQC_CAPS_VSI function caps
2029 * @hw: pointer to the HW struct
2030 * @func_p: pointer to function capabilities structure
2031 * @cap: pointer to the capability element to parse
2033 * Extract function capabilities for ICE_AQC_CAPS_VSI.
2036 ice_parse_vsi_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p,
2037 struct ice_aqc_list_caps_elem *cap)
2039 func_p->guar_num_vsi = ice_get_num_per_func(hw, ICE_MAX_VSI);
2040 ice_debug(hw, ICE_DBG_INIT, "func caps: guar_num_vsi (fw) = %d\n",
2041 LE32_TO_CPU(cap->number));
2042 ice_debug(hw, ICE_DBG_INIT, "func caps: guar_num_vsi = %d\n",
2043 func_p->guar_num_vsi);
2047 * ice_parse_fdir_func_caps - Parse ICE_AQC_CAPS_FD function caps
2048 * @hw: pointer to the HW struct
2049 * @func_p: pointer to function capabilities structure
2051 * Extract function capabilities for ICE_AQC_CAPS_FD.
2054 ice_parse_fdir_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p)
2058 if (hw->dcf_enabled)
2060 reg_val = rd32(hw, GLQF_FD_SIZE);
2061 val = (reg_val & GLQF_FD_SIZE_FD_GSIZE_M) >>
2062 GLQF_FD_SIZE_FD_GSIZE_S;
2063 func_p->fd_fltr_guar =
2064 ice_get_num_per_func(hw, val);
2065 val = (reg_val & GLQF_FD_SIZE_FD_BSIZE_M) >>
2066 GLQF_FD_SIZE_FD_BSIZE_S;
2067 func_p->fd_fltr_best_effort = val;
2069 ice_debug(hw, ICE_DBG_INIT, "func caps: fd_fltr_guar = %d\n",
2070 func_p->fd_fltr_guar);
2071 ice_debug(hw, ICE_DBG_INIT, "func caps: fd_fltr_best_effort = %d\n",
2072 func_p->fd_fltr_best_effort);
2076 * ice_parse_func_caps - Parse function capabilities
2077 * @hw: pointer to the HW struct
2078 * @func_p: pointer to function capabilities structure
2079 * @buf: buffer containing the function capability records
2080 * @cap_count: the number of capabilities
2082 * Helper function to parse function (0x000A) capabilities list. For
2083 * capabilities shared between device and function, this relies on
2084 * ice_parse_common_caps.
2086 * Loop through the list of provided capabilities and extract the relevant
2087 * data into the function capabilities structured.
2090 ice_parse_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p,
2091 void *buf, u32 cap_count)
2093 struct ice_aqc_list_caps_elem *cap_resp;
2096 cap_resp = (struct ice_aqc_list_caps_elem *)buf;
2098 ice_memset(func_p, 0, sizeof(*func_p), ICE_NONDMA_MEM);
2100 for (i = 0; i < cap_count; i++) {
2101 u16 cap = LE16_TO_CPU(cap_resp[i].cap);
2104 found = ice_parse_common_caps(hw, &func_p->common_cap,
2105 &cap_resp[i], "func caps");
2108 case ICE_AQC_CAPS_VSI:
2109 ice_parse_vsi_func_caps(hw, func_p, &cap_resp[i]);
2111 case ICE_AQC_CAPS_FD:
2112 ice_parse_fdir_func_caps(hw, func_p);
2115 /* Don't list common capabilities as unknown */
2117 ice_debug(hw, ICE_DBG_INIT, "func caps: unknown capability[%d]: 0x%x\n",
2123 ice_recalc_port_limited_caps(hw, &func_p->common_cap);
2127 * ice_parse_valid_functions_cap - Parse ICE_AQC_CAPS_VALID_FUNCTIONS caps
2128 * @hw: pointer to the HW struct
2129 * @dev_p: pointer to device capabilities structure
2130 * @cap: capability element to parse
2132 * Parse ICE_AQC_CAPS_VALID_FUNCTIONS for device capabilities.
2135 ice_parse_valid_functions_cap(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p,
2136 struct ice_aqc_list_caps_elem *cap)
2138 u32 number = LE32_TO_CPU(cap->number);
2140 dev_p->num_funcs = ice_hweight32(number);
2141 ice_debug(hw, ICE_DBG_INIT, "dev caps: num_funcs = %d\n",
2146 * ice_parse_vsi_dev_caps - Parse ICE_AQC_CAPS_VSI device caps
2147 * @hw: pointer to the HW struct
2148 * @dev_p: pointer to device capabilities structure
2149 * @cap: capability element to parse
2151 * Parse ICE_AQC_CAPS_VSI for device capabilities.
2154 ice_parse_vsi_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p,
2155 struct ice_aqc_list_caps_elem *cap)
2157 u32 number = LE32_TO_CPU(cap->number);
2159 dev_p->num_vsi_allocd_to_host = number;
2160 ice_debug(hw, ICE_DBG_INIT, "dev caps: num_vsi_allocd_to_host = %d\n",
2161 dev_p->num_vsi_allocd_to_host);
2165 * ice_parse_fdir_dev_caps - Parse ICE_AQC_CAPS_FD device caps
2166 * @hw: pointer to the HW struct
2167 * @dev_p: pointer to device capabilities structure
2168 * @cap: capability element to parse
2170 * Parse ICE_AQC_CAPS_FD for device capabilities.
2173 ice_parse_fdir_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p,
2174 struct ice_aqc_list_caps_elem *cap)
2176 u32 number = LE32_TO_CPU(cap->number);
2178 dev_p->num_flow_director_fltr = number;
2179 ice_debug(hw, ICE_DBG_INIT, "dev caps: num_flow_director_fltr = %d\n",
2180 dev_p->num_flow_director_fltr);
2184 * ice_parse_dev_caps - Parse device capabilities
2185 * @hw: pointer to the HW struct
2186 * @dev_p: pointer to device capabilities structure
2187 * @buf: buffer containing the device capability records
2188 * @cap_count: the number of capabilities
2190 * Helper device to parse device (0x000B) capabilities list. For
2191 * capabilities shared between device and function, this relies on
2192 * ice_parse_common_caps.
2194 * Loop through the list of provided capabilities and extract the relevant
2195 * data into the device capabilities structured.
2198 ice_parse_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p,
2199 void *buf, u32 cap_count)
2201 struct ice_aqc_list_caps_elem *cap_resp;
2204 cap_resp = (struct ice_aqc_list_caps_elem *)buf;
2206 ice_memset(dev_p, 0, sizeof(*dev_p), ICE_NONDMA_MEM);
2208 for (i = 0; i < cap_count; i++) {
2209 u16 cap = LE16_TO_CPU(cap_resp[i].cap);
2212 found = ice_parse_common_caps(hw, &dev_p->common_cap,
2213 &cap_resp[i], "dev caps");
2216 case ICE_AQC_CAPS_VALID_FUNCTIONS:
2217 ice_parse_valid_functions_cap(hw, dev_p, &cap_resp[i]);
2219 case ICE_AQC_CAPS_VSI:
2220 ice_parse_vsi_dev_caps(hw, dev_p, &cap_resp[i]);
2222 case ICE_AQC_CAPS_FD:
2223 ice_parse_fdir_dev_caps(hw, dev_p, &cap_resp[i]);
2226 /* Don't list common capabilities as unknown */
2228 ice_debug(hw, ICE_DBG_INIT, "dev caps: unknown capability[%d]: 0x%x\n",
2234 ice_recalc_port_limited_caps(hw, &dev_p->common_cap);
2238 * ice_aq_list_caps - query function/device capabilities
2239 * @hw: pointer to the HW struct
2240 * @buf: a buffer to hold the capabilities
2241 * @buf_size: size of the buffer
2242 * @cap_count: if not NULL, set to the number of capabilities reported
2243 * @opc: capabilities type to discover, device or function
2244 * @cd: pointer to command details structure or NULL
2246 * Get the function (0x000A) or device (0x000B) capabilities description from
2247 * firmware and store it in the buffer.
2249 * If the cap_count pointer is not NULL, then it is set to the number of
2250 * capabilities firmware will report. Note that if the buffer size is too
2251 * small, it is possible the command will return ICE_AQ_ERR_ENOMEM. The
2252 * cap_count will still be updated in this case. It is recommended that the
2253 * buffer size be set to ICE_AQ_MAX_BUF_LEN (the largest possible buffer that
2254 * firmware could return) to avoid this.
2256 static enum ice_status
2257 ice_aq_list_caps(struct ice_hw *hw, void *buf, u16 buf_size, u32 *cap_count,
2258 enum ice_adminq_opc opc, struct ice_sq_cd *cd)
2260 struct ice_aqc_list_caps *cmd;
2261 struct ice_aq_desc desc;
2262 enum ice_status status;
2264 cmd = &desc.params.get_cap;
2266 if (opc != ice_aqc_opc_list_func_caps &&
2267 opc != ice_aqc_opc_list_dev_caps)
2268 return ICE_ERR_PARAM;
2270 ice_fill_dflt_direct_cmd_desc(&desc, opc);
2271 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);
2274 *cap_count = LE32_TO_CPU(cmd->count);
2280 * ice_discover_dev_caps - Read and extract device capabilities
2281 * @hw: pointer to the hardware structure
2282 * @dev_caps: pointer to device capabilities structure
2284 * Read the device capabilities and extract them into the dev_caps structure
2287 static enum ice_status
2288 ice_discover_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_caps)
2290 enum ice_status status;
2294 cbuf = ice_malloc(hw, ICE_AQ_MAX_BUF_LEN);
2296 return ICE_ERR_NO_MEMORY;
2298 /* Although the driver doesn't know the number of capabilities the
2299 * device will return, we can simply send a 4KB buffer, the maximum
2300 * possible size that firmware can return.
2302 cap_count = ICE_AQ_MAX_BUF_LEN / sizeof(struct ice_aqc_list_caps_elem);
2304 status = ice_aq_list_caps(hw, cbuf, ICE_AQ_MAX_BUF_LEN, &cap_count,
2305 ice_aqc_opc_list_dev_caps, NULL);
2307 ice_parse_dev_caps(hw, dev_caps, cbuf, cap_count);
2314 * ice_discover_func_caps - Read and extract function capabilities
2315 * @hw: pointer to the hardware structure
2316 * @func_caps: pointer to function capabilities structure
2318 * Read the function capabilities and extract them into the func_caps structure
2321 static enum ice_status
2322 ice_discover_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_caps)
2324 enum ice_status status;
2328 cbuf = ice_malloc(hw, ICE_AQ_MAX_BUF_LEN);
2330 return ICE_ERR_NO_MEMORY;
2332 /* Although the driver doesn't know the number of capabilities the
2333 * device will return, we can simply send a 4KB buffer, the maximum
2334 * possible size that firmware can return.
2336 cap_count = ICE_AQ_MAX_BUF_LEN / sizeof(struct ice_aqc_list_caps_elem);
2338 status = ice_aq_list_caps(hw, cbuf, ICE_AQ_MAX_BUF_LEN, &cap_count,
2339 ice_aqc_opc_list_func_caps, NULL);
2341 ice_parse_func_caps(hw, func_caps, cbuf, cap_count);
2348 * ice_set_safe_mode_caps - Override dev/func capabilities when in safe mode
2349 * @hw: pointer to the hardware structure
2351 void ice_set_safe_mode_caps(struct ice_hw *hw)
2353 struct ice_hw_func_caps *func_caps = &hw->func_caps;
2354 struct ice_hw_dev_caps *dev_caps = &hw->dev_caps;
2355 struct ice_hw_common_caps cached_caps;
2358 /* cache some func_caps values that should be restored after memset */
2359 cached_caps = func_caps->common_cap;
2361 /* unset func capabilities */
2362 memset(func_caps, 0, sizeof(*func_caps));
2364 #define ICE_RESTORE_FUNC_CAP(name) \
2365 func_caps->common_cap.name = cached_caps.name
2367 /* restore cached values */
2368 ICE_RESTORE_FUNC_CAP(valid_functions);
2369 ICE_RESTORE_FUNC_CAP(txq_first_id);
2370 ICE_RESTORE_FUNC_CAP(rxq_first_id);
2371 ICE_RESTORE_FUNC_CAP(msix_vector_first_id);
2372 ICE_RESTORE_FUNC_CAP(max_mtu);
2373 ICE_RESTORE_FUNC_CAP(nvm_unified_update);
2375 /* one Tx and one Rx queue in safe mode */
2376 func_caps->common_cap.num_rxq = 1;
2377 func_caps->common_cap.num_txq = 1;
2379 /* two MSIX vectors, one for traffic and one for misc causes */
2380 func_caps->common_cap.num_msix_vectors = 2;
2381 func_caps->guar_num_vsi = 1;
2383 /* cache some dev_caps values that should be restored after memset */
2384 cached_caps = dev_caps->common_cap;
2385 num_funcs = dev_caps->num_funcs;
2387 /* unset dev capabilities */
2388 memset(dev_caps, 0, sizeof(*dev_caps));
2390 #define ICE_RESTORE_DEV_CAP(name) \
2391 dev_caps->common_cap.name = cached_caps.name
2393 /* restore cached values */
2394 ICE_RESTORE_DEV_CAP(valid_functions);
2395 ICE_RESTORE_DEV_CAP(txq_first_id);
2396 ICE_RESTORE_DEV_CAP(rxq_first_id);
2397 ICE_RESTORE_DEV_CAP(msix_vector_first_id);
2398 ICE_RESTORE_DEV_CAP(max_mtu);
2399 ICE_RESTORE_DEV_CAP(nvm_unified_update);
2400 dev_caps->num_funcs = num_funcs;
2402 /* one Tx and one Rx queue per function in safe mode */
2403 dev_caps->common_cap.num_rxq = num_funcs;
2404 dev_caps->common_cap.num_txq = num_funcs;
2406 /* two MSIX vectors per function */
2407 dev_caps->common_cap.num_msix_vectors = 2 * num_funcs;
2411 * ice_get_caps - get info about the HW
2412 * @hw: pointer to the hardware structure
2414 enum ice_status ice_get_caps(struct ice_hw *hw)
2416 enum ice_status status;
2418 status = ice_discover_dev_caps(hw, &hw->dev_caps);
2422 return ice_discover_func_caps(hw, &hw->func_caps);
2426 * ice_aq_manage_mac_write - manage MAC address write command
2427 * @hw: pointer to the HW struct
2428 * @mac_addr: MAC address to be written as LAA/LAA+WoL/Port address
2429 * @flags: flags to control write behavior
2430 * @cd: pointer to command details structure or NULL
2432 * This function is used to write MAC address to the NVM (0x0108).
2435 ice_aq_manage_mac_write(struct ice_hw *hw, const u8 *mac_addr, u8 flags,
2436 struct ice_sq_cd *cd)
2438 struct ice_aqc_manage_mac_write *cmd;
2439 struct ice_aq_desc desc;
2441 cmd = &desc.params.mac_write;
2442 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_write);
2445 ice_memcpy(cmd->mac_addr, mac_addr, ETH_ALEN, ICE_NONDMA_TO_NONDMA);
2447 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
2451 * ice_aq_clear_pxe_mode
2452 * @hw: pointer to the HW struct
2454 * Tell the firmware that the driver is taking over from PXE (0x0110).
2456 static enum ice_status ice_aq_clear_pxe_mode(struct ice_hw *hw)
2458 struct ice_aq_desc desc;
2460 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pxe_mode);
2461 desc.params.clear_pxe.rx_cnt = ICE_AQC_CLEAR_PXE_RX_CNT;
2463 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
2467 * ice_clear_pxe_mode - clear pxe operations mode
2468 * @hw: pointer to the HW struct
2470 * Make sure all PXE mode settings are cleared, including things
2471 * like descriptor fetch/write-back mode.
2473 void ice_clear_pxe_mode(struct ice_hw *hw)
2475 if (ice_check_sq_alive(hw, &hw->adminq))
2476 ice_aq_clear_pxe_mode(hw);
2480 * ice_aq_set_port_params - set physical port parameters.
2481 * @pi: pointer to the port info struct
2482 * @bad_frame_vsi: defines the VSI to which bad frames are forwarded
2483 * @save_bad_pac: if set packets with errors are forwarded to the bad frames VSI
2484 * @pad_short_pac: if set transmit packets smaller than 60 bytes are padded
2485 * @double_vlan: if set double VLAN is enabled
2486 * @cd: pointer to command details structure or NULL
2488 * Set Physical port parameters (0x0203)
2491 ice_aq_set_port_params(struct ice_port_info *pi, u16 bad_frame_vsi,
2492 bool save_bad_pac, bool pad_short_pac, bool double_vlan,
2493 struct ice_sq_cd *cd)
2496 struct ice_aqc_set_port_params *cmd;
2497 struct ice_hw *hw = pi->hw;
2498 struct ice_aq_desc desc;
2501 cmd = &desc.params.set_port_params;
2503 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_port_params);
2504 cmd->bad_frame_vsi = CPU_TO_LE16(bad_frame_vsi);
2506 cmd_flags |= ICE_AQC_SET_P_PARAMS_SAVE_BAD_PACKETS;
2508 cmd_flags |= ICE_AQC_SET_P_PARAMS_PAD_SHORT_PACKETS;
2510 cmd_flags |= ICE_AQC_SET_P_PARAMS_DOUBLE_VLAN_ENA;
2511 cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
2513 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
2517 * ice_get_link_speed_based_on_phy_type - returns link speed
2518 * @phy_type_low: lower part of phy_type
2519 * @phy_type_high: higher part of phy_type
2521 * This helper function will convert an entry in PHY type structure
2522 * [phy_type_low, phy_type_high] to its corresponding link speed.
2523 * Note: In the structure of [phy_type_low, phy_type_high], there should
2524 * be one bit set, as this function will convert one PHY type to its
2526 * If no bit gets set, ICE_LINK_SPEED_UNKNOWN will be returned
2527 * If more than one bit gets set, ICE_LINK_SPEED_UNKNOWN will be returned
2530 ice_get_link_speed_based_on_phy_type(u64 phy_type_low, u64 phy_type_high)
2532 u16 speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN;
2533 u16 speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN;
2535 switch (phy_type_low) {
2536 case ICE_PHY_TYPE_LOW_100BASE_TX:
2537 case ICE_PHY_TYPE_LOW_100M_SGMII:
2538 speed_phy_type_low = ICE_AQ_LINK_SPEED_100MB;
2540 case ICE_PHY_TYPE_LOW_1000BASE_T:
2541 case ICE_PHY_TYPE_LOW_1000BASE_SX:
2542 case ICE_PHY_TYPE_LOW_1000BASE_LX:
2543 case ICE_PHY_TYPE_LOW_1000BASE_KX:
2544 case ICE_PHY_TYPE_LOW_1G_SGMII:
2545 speed_phy_type_low = ICE_AQ_LINK_SPEED_1000MB;
2547 case ICE_PHY_TYPE_LOW_2500BASE_T:
2548 case ICE_PHY_TYPE_LOW_2500BASE_X:
2549 case ICE_PHY_TYPE_LOW_2500BASE_KX:
2550 speed_phy_type_low = ICE_AQ_LINK_SPEED_2500MB;
2552 case ICE_PHY_TYPE_LOW_5GBASE_T:
2553 case ICE_PHY_TYPE_LOW_5GBASE_KR:
2554 speed_phy_type_low = ICE_AQ_LINK_SPEED_5GB;
2556 case ICE_PHY_TYPE_LOW_10GBASE_T:
2557 case ICE_PHY_TYPE_LOW_10G_SFI_DA:
2558 case ICE_PHY_TYPE_LOW_10GBASE_SR:
2559 case ICE_PHY_TYPE_LOW_10GBASE_LR:
2560 case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1:
2561 case ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC:
2562 case ICE_PHY_TYPE_LOW_10G_SFI_C2C:
2563 speed_phy_type_low = ICE_AQ_LINK_SPEED_10GB;
2565 case ICE_PHY_TYPE_LOW_25GBASE_T:
2566 case ICE_PHY_TYPE_LOW_25GBASE_CR:
2567 case ICE_PHY_TYPE_LOW_25GBASE_CR_S:
2568 case ICE_PHY_TYPE_LOW_25GBASE_CR1:
2569 case ICE_PHY_TYPE_LOW_25GBASE_SR:
2570 case ICE_PHY_TYPE_LOW_25GBASE_LR:
2571 case ICE_PHY_TYPE_LOW_25GBASE_KR:
2572 case ICE_PHY_TYPE_LOW_25GBASE_KR_S:
2573 case ICE_PHY_TYPE_LOW_25GBASE_KR1:
2574 case ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC:
2575 case ICE_PHY_TYPE_LOW_25G_AUI_C2C:
2576 speed_phy_type_low = ICE_AQ_LINK_SPEED_25GB;
2578 case ICE_PHY_TYPE_LOW_40GBASE_CR4:
2579 case ICE_PHY_TYPE_LOW_40GBASE_SR4:
2580 case ICE_PHY_TYPE_LOW_40GBASE_LR4:
2581 case ICE_PHY_TYPE_LOW_40GBASE_KR4:
2582 case ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC:
2583 case ICE_PHY_TYPE_LOW_40G_XLAUI:
2584 speed_phy_type_low = ICE_AQ_LINK_SPEED_40GB;
2586 case ICE_PHY_TYPE_LOW_50GBASE_CR2:
2587 case ICE_PHY_TYPE_LOW_50GBASE_SR2:
2588 case ICE_PHY_TYPE_LOW_50GBASE_LR2:
2589 case ICE_PHY_TYPE_LOW_50GBASE_KR2:
2590 case ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC:
2591 case ICE_PHY_TYPE_LOW_50G_LAUI2:
2592 case ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC:
2593 case ICE_PHY_TYPE_LOW_50G_AUI2:
2594 case ICE_PHY_TYPE_LOW_50GBASE_CP:
2595 case ICE_PHY_TYPE_LOW_50GBASE_SR:
2596 case ICE_PHY_TYPE_LOW_50GBASE_FR:
2597 case ICE_PHY_TYPE_LOW_50GBASE_LR:
2598 case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4:
2599 case ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC:
2600 case ICE_PHY_TYPE_LOW_50G_AUI1:
2601 speed_phy_type_low = ICE_AQ_LINK_SPEED_50GB;
2603 case ICE_PHY_TYPE_LOW_100GBASE_CR4:
2604 case ICE_PHY_TYPE_LOW_100GBASE_SR4:
2605 case ICE_PHY_TYPE_LOW_100GBASE_LR4:
2606 case ICE_PHY_TYPE_LOW_100GBASE_KR4:
2607 case ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC:
2608 case ICE_PHY_TYPE_LOW_100G_CAUI4:
2609 case ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC:
2610 case ICE_PHY_TYPE_LOW_100G_AUI4:
2611 case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4:
2612 case ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4:
2613 case ICE_PHY_TYPE_LOW_100GBASE_CP2:
2614 case ICE_PHY_TYPE_LOW_100GBASE_SR2:
2615 case ICE_PHY_TYPE_LOW_100GBASE_DR:
2616 speed_phy_type_low = ICE_AQ_LINK_SPEED_100GB;
2619 speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN;
2623 switch (phy_type_high) {
2624 case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4:
2625 case ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC:
2626 case ICE_PHY_TYPE_HIGH_100G_CAUI2:
2627 case ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC:
2628 case ICE_PHY_TYPE_HIGH_100G_AUI2:
2629 speed_phy_type_high = ICE_AQ_LINK_SPEED_100GB;
2632 speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN;
2636 if (speed_phy_type_low == ICE_AQ_LINK_SPEED_UNKNOWN &&
2637 speed_phy_type_high == ICE_AQ_LINK_SPEED_UNKNOWN)
2638 return ICE_AQ_LINK_SPEED_UNKNOWN;
2639 else if (speed_phy_type_low != ICE_AQ_LINK_SPEED_UNKNOWN &&
2640 speed_phy_type_high != ICE_AQ_LINK_SPEED_UNKNOWN)
2641 return ICE_AQ_LINK_SPEED_UNKNOWN;
2642 else if (speed_phy_type_low != ICE_AQ_LINK_SPEED_UNKNOWN &&
2643 speed_phy_type_high == ICE_AQ_LINK_SPEED_UNKNOWN)
2644 return speed_phy_type_low;
2646 return speed_phy_type_high;
2650 * ice_update_phy_type
2651 * @phy_type_low: pointer to the lower part of phy_type
2652 * @phy_type_high: pointer to the higher part of phy_type
2653 * @link_speeds_bitmap: targeted link speeds bitmap
2655 * Note: For the link_speeds_bitmap structure, you can check it at
2656 * [ice_aqc_get_link_status->link_speed]. Caller can pass in
2657 * link_speeds_bitmap include multiple speeds.
2659 * Each entry in this [phy_type_low, phy_type_high] structure will
2660 * present a certain link speed. This helper function will turn on bits
2661 * in [phy_type_low, phy_type_high] structure based on the value of
2662 * link_speeds_bitmap input parameter.
2665 ice_update_phy_type(u64 *phy_type_low, u64 *phy_type_high,
2666 u16 link_speeds_bitmap)
2673 /* We first check with low part of phy_type */
2674 for (index = 0; index <= ICE_PHY_TYPE_LOW_MAX_INDEX; index++) {
2675 pt_low = BIT_ULL(index);
2676 speed = ice_get_link_speed_based_on_phy_type(pt_low, 0);
2678 if (link_speeds_bitmap & speed)
2679 *phy_type_low |= BIT_ULL(index);
2682 /* We then check with high part of phy_type */
2683 for (index = 0; index <= ICE_PHY_TYPE_HIGH_MAX_INDEX; index++) {
2684 pt_high = BIT_ULL(index);
2685 speed = ice_get_link_speed_based_on_phy_type(0, pt_high);
2687 if (link_speeds_bitmap & speed)
2688 *phy_type_high |= BIT_ULL(index);
2693 * ice_aq_set_phy_cfg
2694 * @hw: pointer to the HW struct
2695 * @pi: port info structure of the interested logical port
2696 * @cfg: structure with PHY configuration data to be set
2697 * @cd: pointer to command details structure or NULL
2699 * Set the various PHY configuration parameters supported on the Port.
2700 * One or more of the Set PHY config parameters may be ignored in an MFP
2701 * mode as the PF may not have the privilege to set some of the PHY Config
2702 * parameters. This status will be indicated by the command response (0x0601).
2705 ice_aq_set_phy_cfg(struct ice_hw *hw, struct ice_port_info *pi,
2706 struct ice_aqc_set_phy_cfg_data *cfg, struct ice_sq_cd *cd)
2708 struct ice_aq_desc desc;
2709 enum ice_status status;
2712 return ICE_ERR_PARAM;
2714 /* Ensure that only valid bits of cfg->caps can be turned on. */
2715 if (cfg->caps & ~ICE_AQ_PHY_ENA_VALID_MASK) {
2716 ice_debug(hw, ICE_DBG_PHY, "Invalid bit is set in ice_aqc_set_phy_cfg_data->caps : 0x%x\n",
2719 cfg->caps &= ICE_AQ_PHY_ENA_VALID_MASK;
2722 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_phy_cfg);
2723 desc.params.set_phy.lport_num = pi->lport;
2724 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
2726 ice_debug(hw, ICE_DBG_LINK, "set phy cfg\n");
2727 ice_debug(hw, ICE_DBG_LINK, " phy_type_low = 0x%llx\n",
2728 (unsigned long long)LE64_TO_CPU(cfg->phy_type_low));
2729 ice_debug(hw, ICE_DBG_LINK, " phy_type_high = 0x%llx\n",
2730 (unsigned long long)LE64_TO_CPU(cfg->phy_type_high));
2731 ice_debug(hw, ICE_DBG_LINK, " caps = 0x%x\n", cfg->caps);
2732 ice_debug(hw, ICE_DBG_LINK, " low_power_ctrl_an = 0x%x\n",
2733 cfg->low_power_ctrl_an);
2734 ice_debug(hw, ICE_DBG_LINK, " eee_cap = 0x%x\n", cfg->eee_cap);
2735 ice_debug(hw, ICE_DBG_LINK, " eeer_value = 0x%x\n", cfg->eeer_value);
2736 ice_debug(hw, ICE_DBG_LINK, " link_fec_opt = 0x%x\n",
2739 status = ice_aq_send_cmd(hw, &desc, cfg, sizeof(*cfg), cd);
2741 if (hw->adminq.sq_last_status == ICE_AQ_RC_EMODE)
2742 status = ICE_SUCCESS;
2745 pi->phy.curr_user_phy_cfg = *cfg;
2751 * ice_update_link_info - update status of the HW network link
2752 * @pi: port info structure of the interested logical port
2754 enum ice_status ice_update_link_info(struct ice_port_info *pi)
2756 struct ice_link_status *li;
2757 enum ice_status status;
2760 return ICE_ERR_PARAM;
2762 li = &pi->phy.link_info;
2764 status = ice_aq_get_link_info(pi, true, NULL, NULL);
2768 if (li->link_info & ICE_AQ_MEDIA_AVAILABLE) {
2769 struct ice_aqc_get_phy_caps_data *pcaps;
2773 pcaps = (struct ice_aqc_get_phy_caps_data *)
2774 ice_malloc(hw, sizeof(*pcaps));
2776 return ICE_ERR_NO_MEMORY;
2778 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_TOPO_CAP_MEDIA,
2781 if (status == ICE_SUCCESS)
2782 ice_memcpy(li->module_type, &pcaps->module_type,
2783 sizeof(li->module_type),
2784 ICE_NONDMA_TO_NONDMA);
2786 ice_free(hw, pcaps);
2793 * ice_cache_phy_user_req
2794 * @pi: port information structure
2795 * @cache_data: PHY logging data
2796 * @cache_mode: PHY logging mode
2798 * Log the user request on (FC, FEC, SPEED) for later user.
2801 ice_cache_phy_user_req(struct ice_port_info *pi,
2802 struct ice_phy_cache_mode_data cache_data,
2803 enum ice_phy_cache_mode cache_mode)
2808 switch (cache_mode) {
2810 pi->phy.curr_user_fc_req = cache_data.data.curr_user_fc_req;
2812 case ICE_SPEED_MODE:
2813 pi->phy.curr_user_speed_req =
2814 cache_data.data.curr_user_speed_req;
2817 pi->phy.curr_user_fec_req = cache_data.data.curr_user_fec_req;
2825 * ice_caps_to_fc_mode
2826 * @caps: PHY capabilities
2828 * Convert PHY FC capabilities to ice FC mode
2830 enum ice_fc_mode ice_caps_to_fc_mode(u8 caps)
2832 if (caps & ICE_AQC_PHY_EN_TX_LINK_PAUSE &&
2833 caps & ICE_AQC_PHY_EN_RX_LINK_PAUSE)
2836 if (caps & ICE_AQC_PHY_EN_TX_LINK_PAUSE)
2837 return ICE_FC_TX_PAUSE;
2839 if (caps & ICE_AQC_PHY_EN_RX_LINK_PAUSE)
2840 return ICE_FC_RX_PAUSE;
2846 * ice_caps_to_fec_mode
2847 * @caps: PHY capabilities
2848 * @fec_options: Link FEC options
2850 * Convert PHY FEC capabilities to ice FEC mode
2852 enum ice_fec_mode ice_caps_to_fec_mode(u8 caps, u8 fec_options)
2854 if (caps & ICE_AQC_PHY_EN_AUTO_FEC)
2855 return ICE_FEC_AUTO;
2857 if (fec_options & (ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN |
2858 ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ |
2859 ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN |
2860 ICE_AQC_PHY_FEC_25G_KR_REQ))
2861 return ICE_FEC_BASER;
2863 if (fec_options & (ICE_AQC_PHY_FEC_25G_RS_528_REQ |
2864 ICE_AQC_PHY_FEC_25G_RS_544_REQ |
2865 ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN))
2868 return ICE_FEC_NONE;
2872 * ice_cfg_phy_fc - Configure PHY FC data based on FC mode
2873 * @pi: port information structure
2874 * @cfg: PHY configuration data to set FC mode
2875 * @req_mode: FC mode to configure
2877 static enum ice_status
2878 ice_cfg_phy_fc(struct ice_port_info *pi, struct ice_aqc_set_phy_cfg_data *cfg,
2879 enum ice_fc_mode req_mode)
2881 struct ice_phy_cache_mode_data cache_data;
2882 u8 pause_mask = 0x0;
2885 return ICE_ERR_BAD_PTR;
2890 struct ice_aqc_get_phy_caps_data *pcaps;
2891 enum ice_status status;
2893 pcaps = (struct ice_aqc_get_phy_caps_data *)
2894 ice_malloc(pi->hw, sizeof(*pcaps));
2896 return ICE_ERR_NO_MEMORY;
2898 /* Query the value of FC that both the NIC and attached media
2901 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_TOPO_CAP_MEDIA,
2904 ice_free(pi->hw, pcaps);
2908 pause_mask |= pcaps->caps & ICE_AQC_PHY_EN_TX_LINK_PAUSE;
2909 pause_mask |= pcaps->caps & ICE_AQC_PHY_EN_RX_LINK_PAUSE;
2911 ice_free(pi->hw, pcaps);
2915 pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE;
2916 pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE;
2918 case ICE_FC_RX_PAUSE:
2919 pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE;
2921 case ICE_FC_TX_PAUSE:
2922 pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE;
2928 /* clear the old pause settings */
2929 cfg->caps &= ~(ICE_AQC_PHY_EN_TX_LINK_PAUSE |
2930 ICE_AQC_PHY_EN_RX_LINK_PAUSE);
2932 /* set the new capabilities */
2933 cfg->caps |= pause_mask;
2935 /* Cache user FC request */
2936 cache_data.data.curr_user_fc_req = req_mode;
2937 ice_cache_phy_user_req(pi, cache_data, ICE_FC_MODE);
2944 * @pi: port information structure
2945 * @aq_failures: pointer to status code, specific to ice_set_fc routine
2946 * @ena_auto_link_update: enable automatic link update
2948 * Set the requested flow control mode.
2951 ice_set_fc(struct ice_port_info *pi, u8 *aq_failures, bool ena_auto_link_update)
2953 struct ice_aqc_set_phy_cfg_data cfg = { 0 };
2954 struct ice_aqc_get_phy_caps_data *pcaps;
2955 enum ice_status status;
2958 if (!pi || !aq_failures)
2959 return ICE_ERR_BAD_PTR;
2964 pcaps = (struct ice_aqc_get_phy_caps_data *)
2965 ice_malloc(hw, sizeof(*pcaps));
2967 return ICE_ERR_NO_MEMORY;
2969 /* Get the current PHY config */
2970 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_ACTIVE_CFG,
2974 *aq_failures = ICE_SET_FC_AQ_FAIL_GET;
2978 ice_copy_phy_caps_to_cfg(pi, pcaps, &cfg);
2980 /* Configure the set PHY data */
2981 status = ice_cfg_phy_fc(pi, &cfg, pi->fc.req_mode);
2983 if (status != ICE_ERR_BAD_PTR)
2984 *aq_failures = ICE_SET_FC_AQ_FAIL_GET;
2989 /* If the capabilities have changed, then set the new config */
2990 if (cfg.caps != pcaps->caps) {
2991 int retry_count, retry_max = 10;
2993 /* Auto restart link so settings take effect */
2994 if (ena_auto_link_update)
2995 cfg.caps |= ICE_AQ_PHY_ENA_AUTO_LINK_UPDT;
2997 status = ice_aq_set_phy_cfg(hw, pi, &cfg, NULL);
2999 *aq_failures = ICE_SET_FC_AQ_FAIL_SET;
3003 /* Update the link info
3004 * It sometimes takes a really long time for link to
3005 * come back from the atomic reset. Thus, we wait a
3008 for (retry_count = 0; retry_count < retry_max; retry_count++) {
3009 status = ice_update_link_info(pi);
3011 if (status == ICE_SUCCESS)
3014 ice_msec_delay(100, true);
3018 *aq_failures = ICE_SET_FC_AQ_FAIL_UPDATE;
3022 ice_free(hw, pcaps);
3027 * ice_phy_caps_equals_cfg
3028 * @phy_caps: PHY capabilities
3029 * @phy_cfg: PHY configuration
3031 * Helper function to determine if PHY capabilities matches PHY
3035 ice_phy_caps_equals_cfg(struct ice_aqc_get_phy_caps_data *phy_caps,
3036 struct ice_aqc_set_phy_cfg_data *phy_cfg)
3038 u8 caps_mask, cfg_mask;
3040 if (!phy_caps || !phy_cfg)
3043 /* These bits are not common between capabilities and configuration.
3044 * Do not use them to determine equality.
3046 caps_mask = ICE_AQC_PHY_CAPS_MASK & ~(ICE_AQC_PHY_AN_MODE |
3047 ICE_AQC_PHY_EN_MOD_QUAL);
3048 cfg_mask = ICE_AQ_PHY_ENA_VALID_MASK & ~ICE_AQ_PHY_ENA_AUTO_LINK_UPDT;
3050 if (phy_caps->phy_type_low != phy_cfg->phy_type_low ||
3051 phy_caps->phy_type_high != phy_cfg->phy_type_high ||
3052 ((phy_caps->caps & caps_mask) != (phy_cfg->caps & cfg_mask)) ||
3053 phy_caps->low_power_ctrl_an != phy_cfg->low_power_ctrl_an ||
3054 phy_caps->eee_cap != phy_cfg->eee_cap ||
3055 phy_caps->eeer_value != phy_cfg->eeer_value ||
3056 phy_caps->link_fec_options != phy_cfg->link_fec_opt)
3063 * ice_copy_phy_caps_to_cfg - Copy PHY ability data to configuration data
3064 * @pi: port information structure
3065 * @caps: PHY ability structure to copy date from
3066 * @cfg: PHY configuration structure to copy data to
3068 * Helper function to copy AQC PHY get ability data to PHY set configuration
3072 ice_copy_phy_caps_to_cfg(struct ice_port_info *pi,
3073 struct ice_aqc_get_phy_caps_data *caps,
3074 struct ice_aqc_set_phy_cfg_data *cfg)
3076 if (!pi || !caps || !cfg)
3079 ice_memset(cfg, 0, sizeof(*cfg), ICE_NONDMA_MEM);
3080 cfg->phy_type_low = caps->phy_type_low;
3081 cfg->phy_type_high = caps->phy_type_high;
3082 cfg->caps = caps->caps;
3083 cfg->low_power_ctrl_an = caps->low_power_ctrl_an;
3084 cfg->eee_cap = caps->eee_cap;
3085 cfg->eeer_value = caps->eeer_value;
3086 cfg->link_fec_opt = caps->link_fec_options;
3087 cfg->module_compliance_enforcement =
3088 caps->module_compliance_enforcement;
3092 * ice_cfg_phy_fec - Configure PHY FEC data based on FEC mode
3093 * @pi: port information structure
3094 * @cfg: PHY configuration data to set FEC mode
3095 * @fec: FEC mode to configure
3098 ice_cfg_phy_fec(struct ice_port_info *pi, struct ice_aqc_set_phy_cfg_data *cfg,
3099 enum ice_fec_mode fec)
3101 struct ice_aqc_get_phy_caps_data *pcaps;
3102 enum ice_status status = ICE_SUCCESS;
3106 return ICE_ERR_BAD_PTR;
3110 pcaps = (struct ice_aqc_get_phy_caps_data *)
3111 ice_malloc(hw, sizeof(*pcaps));
3113 return ICE_ERR_NO_MEMORY;
3115 status = ice_aq_get_phy_caps(pi, false,
3116 (ice_fw_supports_report_dflt_cfg(hw) ?
3117 ICE_AQC_REPORT_DFLT_CFG :
3118 ICE_AQC_REPORT_TOPO_CAP_MEDIA), pcaps, NULL);
3123 cfg->caps |= (pcaps->caps & ICE_AQC_PHY_EN_AUTO_FEC);
3124 cfg->link_fec_opt = pcaps->link_fec_options;
3128 /* Clear RS bits, and AND BASE-R ability
3129 * bits and OR request bits.
3131 cfg->link_fec_opt &= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN |
3132 ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN;
3133 cfg->link_fec_opt |= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ |
3134 ICE_AQC_PHY_FEC_25G_KR_REQ;
3137 /* Clear BASE-R bits, and AND RS ability
3138 * bits and OR request bits.
3140 cfg->link_fec_opt &= ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN;
3141 cfg->link_fec_opt |= ICE_AQC_PHY_FEC_25G_RS_528_REQ |
3142 ICE_AQC_PHY_FEC_25G_RS_544_REQ;
3145 /* Clear all FEC option bits. */
3146 cfg->link_fec_opt &= ~ICE_AQC_PHY_FEC_MASK;
3149 /* AND auto FEC bit, and all caps bits. */
3150 cfg->caps &= ICE_AQC_PHY_CAPS_MASK;
3151 cfg->link_fec_opt |= pcaps->link_fec_options;
3154 status = ICE_ERR_PARAM;
3158 if (fec == ICE_FEC_AUTO && ice_fw_supports_link_override(pi->hw) &&
3159 !ice_fw_supports_report_dflt_cfg(pi->hw)) {
3160 struct ice_link_default_override_tlv tlv;
3162 if (ice_get_link_default_override(&tlv, pi))
3165 if (!(tlv.options & ICE_LINK_OVERRIDE_STRICT_MODE) &&
3166 (tlv.options & ICE_LINK_OVERRIDE_EN))
3167 cfg->link_fec_opt = tlv.fec_options;
3171 ice_free(hw, pcaps);
3177 * ice_get_link_status - get status of the HW network link
3178 * @pi: port information structure
3179 * @link_up: pointer to bool (true/false = linkup/linkdown)
3181 * Variable link_up is true if link is up, false if link is down.
3182 * The variable link_up is invalid if status is non zero. As a
3183 * result of this call, link status reporting becomes enabled
3185 enum ice_status ice_get_link_status(struct ice_port_info *pi, bool *link_up)
3187 struct ice_phy_info *phy_info;
3188 enum ice_status status = ICE_SUCCESS;
3190 if (!pi || !link_up)
3191 return ICE_ERR_PARAM;
3193 phy_info = &pi->phy;
3195 if (phy_info->get_link_info) {
3196 status = ice_update_link_info(pi);
3199 ice_debug(pi->hw, ICE_DBG_LINK, "get link status error, status = %d\n",
3203 *link_up = phy_info->link_info.link_info & ICE_AQ_LINK_UP;
3209 * ice_aq_set_link_restart_an
3210 * @pi: pointer to the port information structure
3211 * @ena_link: if true: enable link, if false: disable link
3212 * @cd: pointer to command details structure or NULL
3214 * Sets up the link and restarts the Auto-Negotiation over the link.
3217 ice_aq_set_link_restart_an(struct ice_port_info *pi, bool ena_link,
3218 struct ice_sq_cd *cd)
3220 struct ice_aqc_restart_an *cmd;
3221 struct ice_aq_desc desc;
3223 cmd = &desc.params.restart_an;
3225 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_restart_an);
3227 cmd->cmd_flags = ICE_AQC_RESTART_AN_LINK_RESTART;
3228 cmd->lport_num = pi->lport;
3230 cmd->cmd_flags |= ICE_AQC_RESTART_AN_LINK_ENABLE;
3232 cmd->cmd_flags &= ~ICE_AQC_RESTART_AN_LINK_ENABLE;
3234 return ice_aq_send_cmd(pi->hw, &desc, NULL, 0, cd);
3238 * ice_aq_set_event_mask
3239 * @hw: pointer to the HW struct
3240 * @port_num: port number of the physical function
3241 * @mask: event mask to be set
3242 * @cd: pointer to command details structure or NULL
3244 * Set event mask (0x0613)
3247 ice_aq_set_event_mask(struct ice_hw *hw, u8 port_num, u16 mask,
3248 struct ice_sq_cd *cd)
3250 struct ice_aqc_set_event_mask *cmd;
3251 struct ice_aq_desc desc;
3253 cmd = &desc.params.set_event_mask;
3255 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_event_mask);
3257 cmd->lport_num = port_num;
3259 cmd->event_mask = CPU_TO_LE16(mask);
3260 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
3264 * ice_aq_set_mac_loopback
3265 * @hw: pointer to the HW struct
3266 * @ena_lpbk: Enable or Disable loopback
3267 * @cd: pointer to command details structure or NULL
3269 * Enable/disable loopback on a given port
3272 ice_aq_set_mac_loopback(struct ice_hw *hw, bool ena_lpbk, struct ice_sq_cd *cd)
3274 struct ice_aqc_set_mac_lb *cmd;
3275 struct ice_aq_desc desc;
3277 cmd = &desc.params.set_mac_lb;
3279 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_mac_lb);
3281 cmd->lb_mode = ICE_AQ_MAC_LB_EN;
3283 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
3287 * ice_aq_set_port_id_led
3288 * @pi: pointer to the port information
3289 * @is_orig_mode: is this LED set to original mode (by the net-list)
3290 * @cd: pointer to command details structure or NULL
3292 * Set LED value for the given port (0x06e9)
3295 ice_aq_set_port_id_led(struct ice_port_info *pi, bool is_orig_mode,
3296 struct ice_sq_cd *cd)
3298 struct ice_aqc_set_port_id_led *cmd;
3299 struct ice_hw *hw = pi->hw;
3300 struct ice_aq_desc desc;
3302 cmd = &desc.params.set_port_id_led;
3304 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_port_id_led);
3307 cmd->ident_mode = ICE_AQC_PORT_IDENT_LED_ORIG;
3309 cmd->ident_mode = ICE_AQC_PORT_IDENT_LED_BLINK;
3311 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
3316 * @hw: pointer to the HW struct
3317 * @lport: bits [7:0] = logical port, bit [8] = logical port valid
3318 * @bus_addr: I2C bus address of the eeprom (typically 0xA0, 0=topo default)
3319 * @mem_addr: I2C offset. lower 8 bits for address, 8 upper bits zero padding.
3321 * @set_page: set or ignore the page
3322 * @data: pointer to data buffer to be read/written to the I2C device.
3323 * @length: 1-16 for read, 1 for write.
3324 * @write: 0 read, 1 for write.
3325 * @cd: pointer to command details structure or NULL
3327 * Read/Write SFF EEPROM (0x06EE)
3330 ice_aq_sff_eeprom(struct ice_hw *hw, u16 lport, u8 bus_addr,
3331 u16 mem_addr, u8 page, u8 set_page, u8 *data, u8 length,
3332 bool write, struct ice_sq_cd *cd)
3334 struct ice_aqc_sff_eeprom *cmd;
3335 struct ice_aq_desc desc;
3336 enum ice_status status;
3338 if (!data || (mem_addr & 0xff00))
3339 return ICE_ERR_PARAM;
3341 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_sff_eeprom);
3342 cmd = &desc.params.read_write_sff_param;
3343 desc.flags = CPU_TO_LE16(ICE_AQ_FLAG_RD);
3344 cmd->lport_num = (u8)(lport & 0xff);
3345 cmd->lport_num_valid = (u8)((lport >> 8) & 0x01);
3346 cmd->i2c_bus_addr = CPU_TO_LE16(((bus_addr >> 1) &
3347 ICE_AQC_SFF_I2CBUS_7BIT_M) |
3349 ICE_AQC_SFF_SET_EEPROM_PAGE_S) &
3350 ICE_AQC_SFF_SET_EEPROM_PAGE_M));
3351 cmd->i2c_mem_addr = CPU_TO_LE16(mem_addr & 0xff);
3352 cmd->eeprom_page = CPU_TO_LE16((u16)page << ICE_AQC_SFF_EEPROM_PAGE_S);
3354 cmd->i2c_bus_addr |= CPU_TO_LE16(ICE_AQC_SFF_IS_WRITE);
3356 status = ice_aq_send_cmd(hw, &desc, data, length, cd);
3361 * __ice_aq_get_set_rss_lut
3362 * @hw: pointer to the hardware structure
3363 * @params: RSS LUT parameters
3364 * @set: set true to set the table, false to get the table
3366 * Internal function to get (0x0B05) or set (0x0B03) RSS look up table
3368 static enum ice_status
3369 __ice_aq_get_set_rss_lut(struct ice_hw *hw, struct ice_aq_get_set_rss_lut_params *params, bool set)
3371 u16 flags = 0, vsi_id, lut_type, lut_size, glob_lut_idx, vsi_handle;
3372 struct ice_aqc_get_set_rss_lut *cmd_resp;
3373 struct ice_aq_desc desc;
3374 enum ice_status status;
3378 return ICE_ERR_PARAM;
3380 vsi_handle = params->vsi_handle;
3383 if (!ice_is_vsi_valid(hw, vsi_handle) || !lut)
3384 return ICE_ERR_PARAM;
3386 lut_size = params->lut_size;
3387 lut_type = params->lut_type;
3388 glob_lut_idx = params->global_lut_id;
3389 vsi_id = ice_get_hw_vsi_num(hw, vsi_handle);
3391 cmd_resp = &desc.params.get_set_rss_lut;
3394 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_rss_lut);
3395 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
3397 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_rss_lut);
3400 cmd_resp->vsi_id = CPU_TO_LE16(((vsi_id <<
3401 ICE_AQC_GSET_RSS_LUT_VSI_ID_S) &
3402 ICE_AQC_GSET_RSS_LUT_VSI_ID_M) |
3403 ICE_AQC_GSET_RSS_LUT_VSI_VALID);
3406 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_VSI:
3407 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF:
3408 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL:
3409 flags |= ((lut_type << ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S) &
3410 ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_M);
3413 status = ICE_ERR_PARAM;
3414 goto ice_aq_get_set_rss_lut_exit;
3417 if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL) {
3418 flags |= ((glob_lut_idx << ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S) &
3419 ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_M);
3422 goto ice_aq_get_set_rss_lut_send;
3423 } else if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF) {
3425 goto ice_aq_get_set_rss_lut_send;
3427 goto ice_aq_get_set_rss_lut_send;
3430 /* LUT size is only valid for Global and PF table types */
3432 case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128:
3433 flags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128_FLAG <<
3434 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) &
3435 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M;
3437 case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512:
3438 flags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512_FLAG <<
3439 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) &
3440 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M;
3442 case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K:
3443 if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF) {
3444 flags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K_FLAG <<
3445 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) &
3446 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M;
3451 status = ICE_ERR_PARAM;
3452 goto ice_aq_get_set_rss_lut_exit;
3455 ice_aq_get_set_rss_lut_send:
3456 cmd_resp->flags = CPU_TO_LE16(flags);
3457 status = ice_aq_send_cmd(hw, &desc, lut, lut_size, NULL);
3459 ice_aq_get_set_rss_lut_exit:
3464 * ice_aq_get_rss_lut
3465 * @hw: pointer to the hardware structure
3466 * @get_params: RSS LUT parameters used to specify which RSS LUT to get
3468 * get the RSS lookup table, PF or VSI type
3471 ice_aq_get_rss_lut(struct ice_hw *hw, struct ice_aq_get_set_rss_lut_params *get_params)
3473 return __ice_aq_get_set_rss_lut(hw, get_params, false);
3477 * ice_aq_set_rss_lut
3478 * @hw: pointer to the hardware structure
3479 * @set_params: RSS LUT parameters used to specify how to set the RSS LUT
3481 * set the RSS lookup table, PF or VSI type
3484 ice_aq_set_rss_lut(struct ice_hw *hw, struct ice_aq_get_set_rss_lut_params *set_params)
3486 return __ice_aq_get_set_rss_lut(hw, set_params, true);
3490 * __ice_aq_get_set_rss_key
3491 * @hw: pointer to the HW struct
3492 * @vsi_id: VSI FW index
3493 * @key: pointer to key info struct
3494 * @set: set true to set the key, false to get the key
3496 * get (0x0B04) or set (0x0B02) the RSS key per VSI
3499 ice_status __ice_aq_get_set_rss_key(struct ice_hw *hw, u16 vsi_id,
3500 struct ice_aqc_get_set_rss_keys *key,
3503 struct ice_aqc_get_set_rss_key *cmd_resp;
3504 u16 key_size = sizeof(*key);
3505 struct ice_aq_desc desc;
3507 cmd_resp = &desc.params.get_set_rss_key;
3510 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_rss_key);
3511 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
3513 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_rss_key);
3516 cmd_resp->vsi_id = CPU_TO_LE16(((vsi_id <<
3517 ICE_AQC_GSET_RSS_KEY_VSI_ID_S) &
3518 ICE_AQC_GSET_RSS_KEY_VSI_ID_M) |
3519 ICE_AQC_GSET_RSS_KEY_VSI_VALID);
3521 return ice_aq_send_cmd(hw, &desc, key, key_size, NULL);
3525 * ice_aq_get_rss_key
3526 * @hw: pointer to the HW struct
3527 * @vsi_handle: software VSI handle
3528 * @key: pointer to key info struct
3530 * get the RSS key per VSI
3533 ice_aq_get_rss_key(struct ice_hw *hw, u16 vsi_handle,
3534 struct ice_aqc_get_set_rss_keys *key)
3536 if (!ice_is_vsi_valid(hw, vsi_handle) || !key)
3537 return ICE_ERR_PARAM;
3539 return __ice_aq_get_set_rss_key(hw, ice_get_hw_vsi_num(hw, vsi_handle),
3544 * ice_aq_set_rss_key
3545 * @hw: pointer to the HW struct
3546 * @vsi_handle: software VSI handle
3547 * @keys: pointer to key info struct
3549 * set the RSS key per VSI
3552 ice_aq_set_rss_key(struct ice_hw *hw, u16 vsi_handle,
3553 struct ice_aqc_get_set_rss_keys *keys)
3555 if (!ice_is_vsi_valid(hw, vsi_handle) || !keys)
3556 return ICE_ERR_PARAM;
3558 return __ice_aq_get_set_rss_key(hw, ice_get_hw_vsi_num(hw, vsi_handle),
3563 * ice_aq_add_lan_txq
3564 * @hw: pointer to the hardware structure
3565 * @num_qgrps: Number of added queue groups
3566 * @qg_list: list of queue groups to be added
3567 * @buf_size: size of buffer for indirect command
3568 * @cd: pointer to command details structure or NULL
3570 * Add Tx LAN queue (0x0C30)
3573 * Prior to calling add Tx LAN queue:
3574 * Initialize the following as part of the Tx queue context:
3575 * Completion queue ID if the queue uses Completion queue, Quanta profile,
3576 * Cache profile and Packet shaper profile.
3578 * After add Tx LAN queue AQ command is completed:
3579 * Interrupts should be associated with specific queues,
3580 * Association of Tx queue to Doorbell queue is not part of Add LAN Tx queue
3584 ice_aq_add_lan_txq(struct ice_hw *hw, u8 num_qgrps,
3585 struct ice_aqc_add_tx_qgrp *qg_list, u16 buf_size,
3586 struct ice_sq_cd *cd)
3588 struct ice_aqc_add_tx_qgrp *list;
3589 struct ice_aqc_add_txqs *cmd;
3590 struct ice_aq_desc desc;
3591 u16 i, sum_size = 0;
3593 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
3595 cmd = &desc.params.add_txqs;
3597 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_add_txqs);
3600 return ICE_ERR_PARAM;
3602 if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS)
3603 return ICE_ERR_PARAM;
3605 for (i = 0, list = qg_list; i < num_qgrps; i++) {
3606 sum_size += ice_struct_size(list, txqs, list->num_txqs);
3607 list = (struct ice_aqc_add_tx_qgrp *)(list->txqs +
3611 if (buf_size != sum_size)
3612 return ICE_ERR_PARAM;
3614 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
3616 cmd->num_qgrps = num_qgrps;
3618 return ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd);
3622 * ice_aq_dis_lan_txq
3623 * @hw: pointer to the hardware structure
3624 * @num_qgrps: number of groups in the list
3625 * @qg_list: the list of groups to disable
3626 * @buf_size: the total size of the qg_list buffer in bytes
3627 * @rst_src: if called due to reset, specifies the reset source
3628 * @vmvf_num: the relative VM or VF number that is undergoing the reset
3629 * @cd: pointer to command details structure or NULL
3631 * Disable LAN Tx queue (0x0C31)
3633 static enum ice_status
3634 ice_aq_dis_lan_txq(struct ice_hw *hw, u8 num_qgrps,
3635 struct ice_aqc_dis_txq_item *qg_list, u16 buf_size,
3636 enum ice_disq_rst_src rst_src, u16 vmvf_num,
3637 struct ice_sq_cd *cd)
3639 struct ice_aqc_dis_txq_item *item;
3640 struct ice_aqc_dis_txqs *cmd;
3641 struct ice_aq_desc desc;
3642 enum ice_status status;
3645 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
3646 cmd = &desc.params.dis_txqs;
3647 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_dis_txqs);
3649 /* qg_list can be NULL only in VM/VF reset flow */
3650 if (!qg_list && !rst_src)
3651 return ICE_ERR_PARAM;
3653 if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS)
3654 return ICE_ERR_PARAM;
3656 cmd->num_entries = num_qgrps;
3658 cmd->vmvf_and_timeout = CPU_TO_LE16((5 << ICE_AQC_Q_DIS_TIMEOUT_S) &
3659 ICE_AQC_Q_DIS_TIMEOUT_M);
3663 cmd->cmd_type = ICE_AQC_Q_DIS_CMD_VM_RESET;
3664 cmd->vmvf_and_timeout |=
3665 CPU_TO_LE16(vmvf_num & ICE_AQC_Q_DIS_VMVF_NUM_M);
3672 /* flush pipe on time out */
3673 cmd->cmd_type |= ICE_AQC_Q_DIS_CMD_FLUSH_PIPE;
3674 /* If no queue group info, we are in a reset flow. Issue the AQ */
3678 /* set RD bit to indicate that command buffer is provided by the driver
3679 * and it needs to be read by the firmware
3681 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
3683 for (i = 0, item = qg_list; i < num_qgrps; i++) {
3684 u16 item_size = ice_struct_size(item, q_id, item->num_qs);
3686 /* If the num of queues is even, add 2 bytes of padding */
3687 if ((item->num_qs % 2) == 0)
3692 item = (struct ice_aqc_dis_txq_item *)((u8 *)item + item_size);
3696 return ICE_ERR_PARAM;
3699 status = ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd);
3702 ice_debug(hw, ICE_DBG_SCHED, "VM%d disable failed %d\n",
3703 vmvf_num, hw->adminq.sq_last_status);
3705 ice_debug(hw, ICE_DBG_SCHED, "disable queue %d failed %d\n",
3706 LE16_TO_CPU(qg_list[0].q_id[0]),
3707 hw->adminq.sq_last_status);
3713 * ice_aq_move_recfg_lan_txq
3714 * @hw: pointer to the hardware structure
3715 * @num_qs: number of queues to move/reconfigure
3716 * @is_move: true if this operation involves node movement
3717 * @is_tc_change: true if this operation involves a TC change
3718 * @subseq_call: true if this operation is a subsequent call
3719 * @flush_pipe: on timeout, true to flush pipe, false to return EAGAIN
3720 * @timeout: timeout in units of 100 usec (valid values 0-50)
3721 * @blocked_cgds: out param, bitmap of CGDs that timed out if returning EAGAIN
3722 * @buf: struct containing src/dest TEID and per-queue info
3723 * @buf_size: size of buffer for indirect command
3724 * @txqs_moved: out param, number of queues successfully moved
3725 * @cd: pointer to command details structure or NULL
3727 * Move / Reconfigure Tx LAN queues (0x0C32)
3730 ice_aq_move_recfg_lan_txq(struct ice_hw *hw, u8 num_qs, bool is_move,
3731 bool is_tc_change, bool subseq_call, bool flush_pipe,
3732 u8 timeout, u32 *blocked_cgds,
3733 struct ice_aqc_move_txqs_data *buf, u16 buf_size,
3734 u8 *txqs_moved, struct ice_sq_cd *cd)
3736 struct ice_aqc_move_txqs *cmd;
3737 struct ice_aq_desc desc;
3738 enum ice_status status;
3740 cmd = &desc.params.move_txqs;
3741 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_move_recfg_txqs);
3743 #define ICE_LAN_TXQ_MOVE_TIMEOUT_MAX 50
3744 if (timeout > ICE_LAN_TXQ_MOVE_TIMEOUT_MAX)
3745 return ICE_ERR_PARAM;
3747 if (is_tc_change && !flush_pipe && !blocked_cgds)
3748 return ICE_ERR_PARAM;
3750 if (!is_move && !is_tc_change)
3751 return ICE_ERR_PARAM;
3753 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
3756 cmd->cmd_type |= ICE_AQC_Q_CMD_TYPE_MOVE;
3759 cmd->cmd_type |= ICE_AQC_Q_CMD_TYPE_TC_CHANGE;
3762 cmd->cmd_type |= ICE_AQC_Q_CMD_SUBSEQ_CALL;
3765 cmd->cmd_type |= ICE_AQC_Q_CMD_FLUSH_PIPE;
3767 cmd->num_qs = num_qs;
3768 cmd->timeout = ((timeout << ICE_AQC_Q_CMD_TIMEOUT_S) &
3769 ICE_AQC_Q_CMD_TIMEOUT_M);
3771 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);
3773 if (!status && txqs_moved)
3774 *txqs_moved = cmd->num_qs;
3776 if (hw->adminq.sq_last_status == ICE_AQ_RC_EAGAIN &&
3777 is_tc_change && !flush_pipe)
3778 *blocked_cgds = LE32_TO_CPU(cmd->blocked_cgds);
3783 /* End of FW Admin Queue command wrappers */
3786 * ice_write_byte - write a byte to a packed context structure
3787 * @src_ctx: the context structure to read from
3788 * @dest_ctx: the context to be written to
3789 * @ce_info: a description of the struct to be filled
3792 ice_write_byte(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)
3794 u8 src_byte, dest_byte, mask;
3798 /* copy from the next struct field */
3799 from = src_ctx + ce_info->offset;
3801 /* prepare the bits and mask */
3802 shift_width = ce_info->lsb % 8;
3803 mask = (u8)(BIT(ce_info->width) - 1);
3808 /* shift to correct alignment */
3809 mask <<= shift_width;
3810 src_byte <<= shift_width;
3812 /* get the current bits from the target bit string */
3813 dest = dest_ctx + (ce_info->lsb / 8);
3815 ice_memcpy(&dest_byte, dest, sizeof(dest_byte), ICE_DMA_TO_NONDMA);
3817 dest_byte &= ~mask; /* get the bits not changing */
3818 dest_byte |= src_byte; /* add in the new bits */
3820 /* put it all back */
3821 ice_memcpy(dest, &dest_byte, sizeof(dest_byte), ICE_NONDMA_TO_DMA);
3825 * ice_write_word - write a word to a packed context structure
3826 * @src_ctx: the context structure to read from
3827 * @dest_ctx: the context to be written to
3828 * @ce_info: a description of the struct to be filled
3831 ice_write_word(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)
3838 /* copy from the next struct field */
3839 from = src_ctx + ce_info->offset;
3841 /* prepare the bits and mask */
3842 shift_width = ce_info->lsb % 8;
3843 mask = BIT(ce_info->width) - 1;
3845 /* don't swizzle the bits until after the mask because the mask bits
3846 * will be in a different bit position on big endian machines
3848 src_word = *(u16 *)from;
3851 /* shift to correct alignment */
3852 mask <<= shift_width;
3853 src_word <<= shift_width;
3855 /* get the current bits from the target bit string */
3856 dest = dest_ctx + (ce_info->lsb / 8);
3858 ice_memcpy(&dest_word, dest, sizeof(dest_word), ICE_DMA_TO_NONDMA);
3860 dest_word &= ~(CPU_TO_LE16(mask)); /* get the bits not changing */
3861 dest_word |= CPU_TO_LE16(src_word); /* add in the new bits */
3863 /* put it all back */
3864 ice_memcpy(dest, &dest_word, sizeof(dest_word), ICE_NONDMA_TO_DMA);
3868 * ice_write_dword - write a dword to a packed context structure
3869 * @src_ctx: the context structure to read from
3870 * @dest_ctx: the context to be written to
3871 * @ce_info: a description of the struct to be filled
3874 ice_write_dword(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)
3876 u32 src_dword, mask;
3881 /* copy from the next struct field */
3882 from = src_ctx + ce_info->offset;
3884 /* prepare the bits and mask */
3885 shift_width = ce_info->lsb % 8;
3887 /* if the field width is exactly 32 on an x86 machine, then the shift
3888 * operation will not work because the SHL instructions count is masked
3889 * to 5 bits so the shift will do nothing
3891 if (ce_info->width < 32)
3892 mask = BIT(ce_info->width) - 1;
3896 /* don't swizzle the bits until after the mask because the mask bits
3897 * will be in a different bit position on big endian machines
3899 src_dword = *(u32 *)from;
3902 /* shift to correct alignment */
3903 mask <<= shift_width;
3904 src_dword <<= shift_width;
3906 /* get the current bits from the target bit string */
3907 dest = dest_ctx + (ce_info->lsb / 8);
3909 ice_memcpy(&dest_dword, dest, sizeof(dest_dword), ICE_DMA_TO_NONDMA);
3911 dest_dword &= ~(CPU_TO_LE32(mask)); /* get the bits not changing */
3912 dest_dword |= CPU_TO_LE32(src_dword); /* add in the new bits */
3914 /* put it all back */
3915 ice_memcpy(dest, &dest_dword, sizeof(dest_dword), ICE_NONDMA_TO_DMA);
3919 * ice_write_qword - write a qword to a packed context structure
3920 * @src_ctx: the context structure to read from
3921 * @dest_ctx: the context to be written to
3922 * @ce_info: a description of the struct to be filled
3925 ice_write_qword(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)
3927 u64 src_qword, mask;
3932 /* copy from the next struct field */
3933 from = src_ctx + ce_info->offset;
3935 /* prepare the bits and mask */
3936 shift_width = ce_info->lsb % 8;
3938 /* if the field width is exactly 64 on an x86 machine, then the shift
3939 * operation will not work because the SHL instructions count is masked
3940 * to 6 bits so the shift will do nothing
3942 if (ce_info->width < 64)
3943 mask = BIT_ULL(ce_info->width) - 1;
3947 /* don't swizzle the bits until after the mask because the mask bits
3948 * will be in a different bit position on big endian machines
3950 src_qword = *(u64 *)from;
3953 /* shift to correct alignment */
3954 mask <<= shift_width;
3955 src_qword <<= shift_width;
3957 /* get the current bits from the target bit string */
3958 dest = dest_ctx + (ce_info->lsb / 8);
3960 ice_memcpy(&dest_qword, dest, sizeof(dest_qword), ICE_DMA_TO_NONDMA);
3962 dest_qword &= ~(CPU_TO_LE64(mask)); /* get the bits not changing */
3963 dest_qword |= CPU_TO_LE64(src_qword); /* add in the new bits */
3965 /* put it all back */
3966 ice_memcpy(dest, &dest_qword, sizeof(dest_qword), ICE_NONDMA_TO_DMA);
3970 * ice_set_ctx - set context bits in packed structure
3971 * @hw: pointer to the hardware structure
3972 * @src_ctx: pointer to a generic non-packed context structure
3973 * @dest_ctx: pointer to memory for the packed structure
3974 * @ce_info: a description of the structure to be transformed
3977 ice_set_ctx(struct ice_hw *hw, u8 *src_ctx, u8 *dest_ctx,
3978 const struct ice_ctx_ele *ce_info)
3982 for (f = 0; ce_info[f].width; f++) {
3983 /* We have to deal with each element of the FW response
3984 * using the correct size so that we are correct regardless
3985 * of the endianness of the machine.
3987 if (ce_info[f].width > (ce_info[f].size_of * BITS_PER_BYTE)) {
3988 ice_debug(hw, ICE_DBG_QCTX, "Field %d width of %d bits larger than size of %d byte(s) ... skipping write\n",
3989 f, ce_info[f].width, ce_info[f].size_of);
3992 switch (ce_info[f].size_of) {
3994 ice_write_byte(src_ctx, dest_ctx, &ce_info[f]);
3997 ice_write_word(src_ctx, dest_ctx, &ce_info[f]);
4000 ice_write_dword(src_ctx, dest_ctx, &ce_info[f]);
4003 ice_write_qword(src_ctx, dest_ctx, &ce_info[f]);
4006 return ICE_ERR_INVAL_SIZE;
4014 * ice_read_byte - read context byte into struct
4015 * @src_ctx: the context structure to read from
4016 * @dest_ctx: the context to be written to
4017 * @ce_info: a description of the struct to be filled
4020 ice_read_byte(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info)
4026 /* prepare the bits and mask */
4027 shift_width = ce_info->lsb % 8;
4028 mask = (u8)(BIT(ce_info->width) - 1);
4030 /* shift to correct alignment */
4031 mask <<= shift_width;
4033 /* get the current bits from the src bit string */
4034 src = src_ctx + (ce_info->lsb / 8);
4036 ice_memcpy(&dest_byte, src, sizeof(dest_byte), ICE_DMA_TO_NONDMA);
4038 dest_byte &= ~(mask);
4040 dest_byte >>= shift_width;
4042 /* get the address from the struct field */
4043 target = dest_ctx + ce_info->offset;
4045 /* put it back in the struct */
4046 ice_memcpy(target, &dest_byte, sizeof(dest_byte), ICE_NONDMA_TO_DMA);
4050 * ice_read_word - read context word into struct
4051 * @src_ctx: the context structure to read from
4052 * @dest_ctx: the context to be written to
4053 * @ce_info: a description of the struct to be filled
4056 ice_read_word(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info)
4058 u16 dest_word, mask;
4063 /* prepare the bits and mask */
4064 shift_width = ce_info->lsb % 8;
4065 mask = BIT(ce_info->width) - 1;
4067 /* shift to correct alignment */
4068 mask <<= shift_width;
4070 /* get the current bits from the src bit string */
4071 src = src_ctx + (ce_info->lsb / 8);
4073 ice_memcpy(&src_word, src, sizeof(src_word), ICE_DMA_TO_NONDMA);
4075 /* the data in the memory is stored as little endian so mask it
4078 src_word &= ~(CPU_TO_LE16(mask));
4080 /* get the data back into host order before shifting */
4081 dest_word = LE16_TO_CPU(src_word);
4083 dest_word >>= shift_width;
4085 /* get the address from the struct field */
4086 target = dest_ctx + ce_info->offset;
4088 /* put it back in the struct */
4089 ice_memcpy(target, &dest_word, sizeof(dest_word), ICE_NONDMA_TO_DMA);
4093 * ice_read_dword - read context dword into struct
4094 * @src_ctx: the context structure to read from
4095 * @dest_ctx: the context to be written to
4096 * @ce_info: a description of the struct to be filled
4099 ice_read_dword(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info)
4101 u32 dest_dword, mask;
4106 /* prepare the bits and mask */
4107 shift_width = ce_info->lsb % 8;
4109 /* if the field width is exactly 32 on an x86 machine, then the shift
4110 * operation will not work because the SHL instructions count is masked
4111 * to 5 bits so the shift will do nothing
4113 if (ce_info->width < 32)
4114 mask = BIT(ce_info->width) - 1;
4118 /* shift to correct alignment */
4119 mask <<= shift_width;
4121 /* get the current bits from the src bit string */
4122 src = src_ctx + (ce_info->lsb / 8);
4124 ice_memcpy(&src_dword, src, sizeof(src_dword), ICE_DMA_TO_NONDMA);
4126 /* the data in the memory is stored as little endian so mask it
4129 src_dword &= ~(CPU_TO_LE32(mask));
4131 /* get the data back into host order before shifting */
4132 dest_dword = LE32_TO_CPU(src_dword);
4134 dest_dword >>= shift_width;
4136 /* get the address from the struct field */
4137 target = dest_ctx + ce_info->offset;
4139 /* put it back in the struct */
4140 ice_memcpy(target, &dest_dword, sizeof(dest_dword), ICE_NONDMA_TO_DMA);
4144 * ice_read_qword - read context qword into struct
4145 * @src_ctx: the context structure to read from
4146 * @dest_ctx: the context to be written to
4147 * @ce_info: a description of the struct to be filled
4150 ice_read_qword(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info)
4152 u64 dest_qword, mask;
4157 /* prepare the bits and mask */
4158 shift_width = ce_info->lsb % 8;
4160 /* if the field width is exactly 64 on an x86 machine, then the shift
4161 * operation will not work because the SHL instructions count is masked
4162 * to 6 bits so the shift will do nothing
4164 if (ce_info->width < 64)
4165 mask = BIT_ULL(ce_info->width) - 1;
4169 /* shift to correct alignment */
4170 mask <<= shift_width;
4172 /* get the current bits from the src bit string */
4173 src = src_ctx + (ce_info->lsb / 8);
4175 ice_memcpy(&src_qword, src, sizeof(src_qword), ICE_DMA_TO_NONDMA);
4177 /* the data in the memory is stored as little endian so mask it
4180 src_qword &= ~(CPU_TO_LE64(mask));
4182 /* get the data back into host order before shifting */
4183 dest_qword = LE64_TO_CPU(src_qword);
4185 dest_qword >>= shift_width;
4187 /* get the address from the struct field */
4188 target = dest_ctx + ce_info->offset;
4190 /* put it back in the struct */
4191 ice_memcpy(target, &dest_qword, sizeof(dest_qword), ICE_NONDMA_TO_DMA);
4195 * ice_get_ctx - extract context bits from a packed structure
4196 * @src_ctx: pointer to a generic packed context structure
4197 * @dest_ctx: pointer to a generic non-packed context structure
4198 * @ce_info: a description of the structure to be read from
4201 ice_get_ctx(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info)
4205 for (f = 0; ce_info[f].width; f++) {
4206 switch (ce_info[f].size_of) {
4208 ice_read_byte(src_ctx, dest_ctx, &ce_info[f]);
4211 ice_read_word(src_ctx, dest_ctx, &ce_info[f]);
4214 ice_read_dword(src_ctx, dest_ctx, &ce_info[f]);
4217 ice_read_qword(src_ctx, dest_ctx, &ce_info[f]);
4220 /* nothing to do, just keep going */
4229 * ice_get_lan_q_ctx - get the LAN queue context for the given VSI and TC
4230 * @hw: pointer to the HW struct
4231 * @vsi_handle: software VSI handle
4233 * @q_handle: software queue handle
4236 ice_get_lan_q_ctx(struct ice_hw *hw, u16 vsi_handle, u8 tc, u16 q_handle)
4238 struct ice_vsi_ctx *vsi;
4239 struct ice_q_ctx *q_ctx;
4241 vsi = ice_get_vsi_ctx(hw, vsi_handle);
4244 if (q_handle >= vsi->num_lan_q_entries[tc])
4246 if (!vsi->lan_q_ctx[tc])
4248 q_ctx = vsi->lan_q_ctx[tc];
4249 return &q_ctx[q_handle];
4254 * @pi: port information structure
4255 * @vsi_handle: software VSI handle
4257 * @q_handle: software queue handle
4258 * @num_qgrps: Number of added queue groups
4259 * @buf: list of queue groups to be added
4260 * @buf_size: size of buffer for indirect command
4261 * @cd: pointer to command details structure or NULL
4263 * This function adds one LAN queue
4266 ice_ena_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u16 q_handle,
4267 u8 num_qgrps, struct ice_aqc_add_tx_qgrp *buf, u16 buf_size,
4268 struct ice_sq_cd *cd)
4270 struct ice_aqc_txsched_elem_data node = { 0 };
4271 struct ice_sched_node *parent;
4272 struct ice_q_ctx *q_ctx;
4273 enum ice_status status;
4276 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY)
4279 if (num_qgrps > 1 || buf->num_txqs > 1)
4280 return ICE_ERR_MAX_LIMIT;
4284 if (!ice_is_vsi_valid(hw, vsi_handle))
4285 return ICE_ERR_PARAM;
4287 ice_acquire_lock(&pi->sched_lock);
4289 q_ctx = ice_get_lan_q_ctx(hw, vsi_handle, tc, q_handle);
4291 ice_debug(hw, ICE_DBG_SCHED, "Enaq: invalid queue handle %d\n",
4293 status = ICE_ERR_PARAM;
4297 /* find a parent node */
4298 parent = ice_sched_get_free_qparent(pi, vsi_handle, tc,
4299 ICE_SCHED_NODE_OWNER_LAN);
4301 status = ICE_ERR_PARAM;
4305 buf->parent_teid = parent->info.node_teid;
4306 node.parent_teid = parent->info.node_teid;
4307 /* Mark that the values in the "generic" section as valid. The default
4308 * value in the "generic" section is zero. This means that :
4309 * - Scheduling mode is Bytes Per Second (BPS), indicated by Bit 0.
4310 * - 0 priority among siblings, indicated by Bit 1-3.
4311 * - WFQ, indicated by Bit 4.
4312 * - 0 Adjustment value is used in PSM credit update flow, indicated by
4314 * - Bit 7 is reserved.
4315 * Without setting the generic section as valid in valid_sections, the
4316 * Admin queue command will fail with error code ICE_AQ_RC_EINVAL.
4318 buf->txqs[0].info.valid_sections =
4319 ICE_AQC_ELEM_VALID_GENERIC | ICE_AQC_ELEM_VALID_CIR |
4320 ICE_AQC_ELEM_VALID_EIR;
4321 buf->txqs[0].info.generic = 0;
4322 buf->txqs[0].info.cir_bw.bw_profile_idx =
4323 CPU_TO_LE16(ICE_SCHED_DFLT_RL_PROF_ID);
4324 buf->txqs[0].info.cir_bw.bw_alloc =
4325 CPU_TO_LE16(ICE_SCHED_DFLT_BW_WT);
4326 buf->txqs[0].info.eir_bw.bw_profile_idx =
4327 CPU_TO_LE16(ICE_SCHED_DFLT_RL_PROF_ID);
4328 buf->txqs[0].info.eir_bw.bw_alloc =
4329 CPU_TO_LE16(ICE_SCHED_DFLT_BW_WT);
4331 /* add the LAN queue */
4332 status = ice_aq_add_lan_txq(hw, num_qgrps, buf, buf_size, cd);
4333 if (status != ICE_SUCCESS) {
4334 ice_debug(hw, ICE_DBG_SCHED, "enable queue %d failed %d\n",
4335 LE16_TO_CPU(buf->txqs[0].txq_id),
4336 hw->adminq.sq_last_status);
4340 node.node_teid = buf->txqs[0].q_teid;
4341 node.data.elem_type = ICE_AQC_ELEM_TYPE_LEAF;
4342 q_ctx->q_handle = q_handle;
4343 q_ctx->q_teid = LE32_TO_CPU(node.node_teid);
4345 /* add a leaf node into scheduler tree queue layer */
4346 status = ice_sched_add_node(pi, hw->num_tx_sched_layers - 1, &node);
4348 status = ice_sched_replay_q_bw(pi, q_ctx);
4351 ice_release_lock(&pi->sched_lock);
4357 * @pi: port information structure
4358 * @vsi_handle: software VSI handle
4360 * @num_queues: number of queues
4361 * @q_handles: pointer to software queue handle array
4362 * @q_ids: pointer to the q_id array
4363 * @q_teids: pointer to queue node teids
4364 * @rst_src: if called due to reset, specifies the reset source
4365 * @vmvf_num: the relative VM or VF number that is undergoing the reset
4366 * @cd: pointer to command details structure or NULL
4368 * This function removes queues and their corresponding nodes in SW DB
4371 ice_dis_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u8 num_queues,
4372 u16 *q_handles, u16 *q_ids, u32 *q_teids,
4373 enum ice_disq_rst_src rst_src, u16 vmvf_num,
4374 struct ice_sq_cd *cd)
4376 enum ice_status status = ICE_ERR_DOES_NOT_EXIST;
4377 struct ice_aqc_dis_txq_item *qg_list;
4378 struct ice_q_ctx *q_ctx;
4382 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY)
4388 /* if queue is disabled already yet the disable queue command
4389 * has to be sent to complete the VF reset, then call
4390 * ice_aq_dis_lan_txq without any queue information
4393 return ice_aq_dis_lan_txq(hw, 0, NULL, 0, rst_src,
4398 buf_size = ice_struct_size(qg_list, q_id, 1);
4399 qg_list = (struct ice_aqc_dis_txq_item *)ice_malloc(hw, buf_size);
4401 return ICE_ERR_NO_MEMORY;
4403 ice_acquire_lock(&pi->sched_lock);
4405 for (i = 0; i < num_queues; i++) {
4406 struct ice_sched_node *node;
4408 node = ice_sched_find_node_by_teid(pi->root, q_teids[i]);
4411 q_ctx = ice_get_lan_q_ctx(hw, vsi_handle, tc, q_handles[i]);
4413 ice_debug(hw, ICE_DBG_SCHED, "invalid queue handle%d\n",
4417 if (q_ctx->q_handle != q_handles[i]) {
4418 ice_debug(hw, ICE_DBG_SCHED, "Err:handles %d %d\n",
4419 q_ctx->q_handle, q_handles[i]);
4422 qg_list->parent_teid = node->info.parent_teid;
4423 qg_list->num_qs = 1;
4424 qg_list->q_id[0] = CPU_TO_LE16(q_ids[i]);
4425 status = ice_aq_dis_lan_txq(hw, 1, qg_list, buf_size, rst_src,
4428 if (status != ICE_SUCCESS)
4430 ice_free_sched_node(pi, node);
4431 q_ctx->q_handle = ICE_INVAL_Q_HANDLE;
4433 ice_release_lock(&pi->sched_lock);
4434 ice_free(hw, qg_list);
4439 * ice_cfg_vsi_qs - configure the new/existing VSI queues
4440 * @pi: port information structure
4441 * @vsi_handle: software VSI handle
4442 * @tc_bitmap: TC bitmap
4443 * @maxqs: max queues array per TC
4444 * @owner: LAN or RDMA
4446 * This function adds/updates the VSI queues per TC.
4448 static enum ice_status
4449 ice_cfg_vsi_qs(struct ice_port_info *pi, u16 vsi_handle, u16 tc_bitmap,
4450 u16 *maxqs, u8 owner)
4452 enum ice_status status = ICE_SUCCESS;
4455 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY)
4458 if (!ice_is_vsi_valid(pi->hw, vsi_handle))
4459 return ICE_ERR_PARAM;
4461 ice_acquire_lock(&pi->sched_lock);
4463 ice_for_each_traffic_class(i) {
4464 /* configuration is possible only if TC node is present */
4465 if (!ice_sched_get_tc_node(pi, i))
4468 status = ice_sched_cfg_vsi(pi, vsi_handle, i, maxqs[i], owner,
4469 ice_is_tc_ena(tc_bitmap, i));
4474 ice_release_lock(&pi->sched_lock);
4479 * ice_cfg_vsi_lan - configure VSI LAN queues
4480 * @pi: port information structure
4481 * @vsi_handle: software VSI handle
4482 * @tc_bitmap: TC bitmap
4483 * @max_lanqs: max LAN queues array per TC
4485 * This function adds/updates the VSI LAN queues per TC.
4488 ice_cfg_vsi_lan(struct ice_port_info *pi, u16 vsi_handle, u16 tc_bitmap,
4491 return ice_cfg_vsi_qs(pi, vsi_handle, tc_bitmap, max_lanqs,
4492 ICE_SCHED_NODE_OWNER_LAN);
4496 * ice_is_main_vsi - checks whether the VSI is main VSI
4497 * @hw: pointer to the HW struct
4498 * @vsi_handle: VSI handle
4500 * Checks whether the VSI is the main VSI (the first PF VSI created on
4503 static bool ice_is_main_vsi(struct ice_hw *hw, u16 vsi_handle)
4505 return vsi_handle == ICE_MAIN_VSI_HANDLE && hw->vsi_ctx[vsi_handle];
4509 * ice_replay_pre_init - replay pre initialization
4510 * @hw: pointer to the HW struct
4511 * @sw: pointer to switch info struct for which function initializes filters
4513 * Initializes required config data for VSI, FD, ACL, and RSS before replay.
4515 static enum ice_status
4516 ice_replay_pre_init(struct ice_hw *hw, struct ice_switch_info *sw)
4518 enum ice_status status;
4521 /* Delete old entries from replay filter list head if there is any */
4522 ice_rm_sw_replay_rule_info(hw, sw);
4523 /* In start of replay, move entries into replay_rules list, it
4524 * will allow adding rules entries back to filt_rules list,
4525 * which is operational list.
4527 for (i = 0; i < ICE_MAX_NUM_RECIPES; i++)
4528 LIST_REPLACE_INIT(&sw->recp_list[i].filt_rules,
4529 &sw->recp_list[i].filt_replay_rules);
4530 ice_sched_replay_agg_vsi_preinit(hw);
4532 status = ice_sched_replay_root_node_bw(hw->port_info);
4536 return ice_sched_replay_tc_node_bw(hw->port_info);
4540 * ice_replay_vsi - replay VSI configuration
4541 * @hw: pointer to the HW struct
4542 * @vsi_handle: driver VSI handle
4544 * Restore all VSI configuration after reset. It is required to call this
4545 * function with main VSI first.
4547 enum ice_status ice_replay_vsi(struct ice_hw *hw, u16 vsi_handle)
4549 struct ice_switch_info *sw = hw->switch_info;
4550 struct ice_port_info *pi = hw->port_info;
4551 enum ice_status status;
4553 if (!ice_is_vsi_valid(hw, vsi_handle))
4554 return ICE_ERR_PARAM;
4556 /* Replay pre-initialization if there is any */
4557 if (ice_is_main_vsi(hw, vsi_handle)) {
4558 status = ice_replay_pre_init(hw, sw);
4562 /* Replay per VSI all RSS configurations */
4563 status = ice_replay_rss_cfg(hw, vsi_handle);
4566 /* Replay per VSI all filters */
4567 status = ice_replay_vsi_all_fltr(hw, pi, vsi_handle);
4569 status = ice_replay_vsi_agg(hw, vsi_handle);
4574 * ice_replay_post - post replay configuration cleanup
4575 * @hw: pointer to the HW struct
4577 * Post replay cleanup.
4579 void ice_replay_post(struct ice_hw *hw)
4581 /* Delete old entries from replay filter list head */
4582 ice_rm_all_sw_replay_rule_info(hw);
4583 ice_sched_replay_agg(hw);
4587 * ice_stat_update40 - read 40 bit stat from the chip and update stat values
4588 * @hw: ptr to the hardware info
4589 * @reg: offset of 64 bit HW register to read from
4590 * @prev_stat_loaded: bool to specify if previous stats are loaded
4591 * @prev_stat: ptr to previous loaded stat value
4592 * @cur_stat: ptr to current stat value
4595 ice_stat_update40(struct ice_hw *hw, u32 reg, bool prev_stat_loaded,
4596 u64 *prev_stat, u64 *cur_stat)
4598 u64 new_data = rd64(hw, reg) & (BIT_ULL(40) - 1);
4600 /* device stats are not reset at PFR, they likely will not be zeroed
4601 * when the driver starts. Thus, save the value from the first read
4602 * without adding to the statistic value so that we report stats which
4603 * count up from zero.
4605 if (!prev_stat_loaded) {
4606 *prev_stat = new_data;
4610 /* Calculate the difference between the new and old values, and then
4611 * add it to the software stat value.
4613 if (new_data >= *prev_stat)
4614 *cur_stat += new_data - *prev_stat;
4616 /* to manage the potential roll-over */
4617 *cur_stat += (new_data + BIT_ULL(40)) - *prev_stat;
4619 /* Update the previously stored value to prepare for next read */
4620 *prev_stat = new_data;
4624 * ice_stat_update32 - read 32 bit stat from the chip and update stat values
4625 * @hw: ptr to the hardware info
4626 * @reg: offset of HW register to read from
4627 * @prev_stat_loaded: bool to specify if previous stats are loaded
4628 * @prev_stat: ptr to previous loaded stat value
4629 * @cur_stat: ptr to current stat value
4632 ice_stat_update32(struct ice_hw *hw, u32 reg, bool prev_stat_loaded,
4633 u64 *prev_stat, u64 *cur_stat)
4637 new_data = rd32(hw, reg);
4639 /* device stats are not reset at PFR, they likely will not be zeroed
4640 * when the driver starts. Thus, save the value from the first read
4641 * without adding to the statistic value so that we report stats which
4642 * count up from zero.
4644 if (!prev_stat_loaded) {
4645 *prev_stat = new_data;
4649 /* Calculate the difference between the new and old values, and then
4650 * add it to the software stat value.
4652 if (new_data >= *prev_stat)
4653 *cur_stat += new_data - *prev_stat;
4655 /* to manage the potential roll-over */
4656 *cur_stat += (new_data + BIT_ULL(32)) - *prev_stat;
4658 /* Update the previously stored value to prepare for next read */
4659 *prev_stat = new_data;
4663 * ice_stat_update_repc - read GLV_REPC stats from chip and update stat values
4664 * @hw: ptr to the hardware info
4665 * @vsi_handle: VSI handle
4666 * @prev_stat_loaded: bool to specify if the previous stat values are loaded
4667 * @cur_stats: ptr to current stats structure
4669 * The GLV_REPC statistic register actually tracks two 16bit statistics, and
4670 * thus cannot be read using the normal ice_stat_update32 function.
4672 * Read the GLV_REPC register associated with the given VSI, and update the
4673 * rx_no_desc and rx_error values in the ice_eth_stats structure.
4675 * Because the statistics in GLV_REPC stick at 0xFFFF, the register must be
4676 * cleared each time it's read.
4678 * Note that the GLV_RDPC register also counts the causes that would trigger
4679 * GLV_REPC. However, it does not give the finer grained detail about why the
4680 * packets are being dropped. The GLV_REPC values can be used to distinguish
4681 * whether Rx packets are dropped due to errors or due to no available
4685 ice_stat_update_repc(struct ice_hw *hw, u16 vsi_handle, bool prev_stat_loaded,
4686 struct ice_eth_stats *cur_stats)
4688 u16 vsi_num, no_desc, error_cnt;
4691 if (!ice_is_vsi_valid(hw, vsi_handle))
4694 vsi_num = ice_get_hw_vsi_num(hw, vsi_handle);
4696 /* If we haven't loaded stats yet, just clear the current value */
4697 if (!prev_stat_loaded) {
4698 wr32(hw, GLV_REPC(vsi_num), 0);
4702 repc = rd32(hw, GLV_REPC(vsi_num));
4703 no_desc = (repc & GLV_REPC_NO_DESC_CNT_M) >> GLV_REPC_NO_DESC_CNT_S;
4704 error_cnt = (repc & GLV_REPC_ERROR_CNT_M) >> GLV_REPC_ERROR_CNT_S;
4706 /* Clear the count by writing to the stats register */
4707 wr32(hw, GLV_REPC(vsi_num), 0);
4709 cur_stats->rx_no_desc += no_desc;
4710 cur_stats->rx_errors += error_cnt;
4714 * ice_sched_query_elem - query element information from HW
4715 * @hw: pointer to the HW struct
4716 * @node_teid: node TEID to be queried
4717 * @buf: buffer to element information
4719 * This function queries HW element information
4722 ice_sched_query_elem(struct ice_hw *hw, u32 node_teid,
4723 struct ice_aqc_txsched_elem_data *buf)
4725 u16 buf_size, num_elem_ret = 0;
4726 enum ice_status status;
4728 buf_size = sizeof(*buf);
4729 ice_memset(buf, 0, buf_size, ICE_NONDMA_MEM);
4730 buf->node_teid = CPU_TO_LE32(node_teid);
4731 status = ice_aq_query_sched_elems(hw, 1, buf, buf_size, &num_elem_ret,
4733 if (status != ICE_SUCCESS || num_elem_ret != 1)
4734 ice_debug(hw, ICE_DBG_SCHED, "query element failed\n");
4739 * ice_get_fw_mode - returns FW mode
4740 * @hw: pointer to the HW struct
4742 enum ice_fw_modes ice_get_fw_mode(struct ice_hw *hw)
4744 #define ICE_FW_MODE_DBG_M BIT(0)
4745 #define ICE_FW_MODE_REC_M BIT(1)
4746 #define ICE_FW_MODE_ROLLBACK_M BIT(2)
4749 /* check the current FW mode */
4750 fw_mode = rd32(hw, GL_MNG_FWSM) & GL_MNG_FWSM_FW_MODES_M;
4752 if (fw_mode & ICE_FW_MODE_DBG_M)
4753 return ICE_FW_MODE_DBG;
4754 else if (fw_mode & ICE_FW_MODE_REC_M)
4755 return ICE_FW_MODE_REC;
4756 else if (fw_mode & ICE_FW_MODE_ROLLBACK_M)
4757 return ICE_FW_MODE_ROLLBACK;
4759 return ICE_FW_MODE_NORMAL;
4763 * ice_fw_supports_link_override
4764 * @hw: pointer to the hardware structure
4766 * Checks if the firmware supports link override
4768 bool ice_fw_supports_link_override(struct ice_hw *hw)
4770 if (hw->api_maj_ver == ICE_FW_API_LINK_OVERRIDE_MAJ) {
4771 if (hw->api_min_ver > ICE_FW_API_LINK_OVERRIDE_MIN)
4773 if (hw->api_min_ver == ICE_FW_API_LINK_OVERRIDE_MIN &&
4774 hw->api_patch >= ICE_FW_API_LINK_OVERRIDE_PATCH)
4776 } else if (hw->api_maj_ver > ICE_FW_API_LINK_OVERRIDE_MAJ) {
4784 * ice_get_link_default_override
4785 * @ldo: pointer to the link default override struct
4786 * @pi: pointer to the port info struct
4788 * Gets the link default override for a port
4791 ice_get_link_default_override(struct ice_link_default_override_tlv *ldo,
4792 struct ice_port_info *pi)
4794 u16 i, tlv, tlv_len, tlv_start, buf, offset;
4795 struct ice_hw *hw = pi->hw;
4796 enum ice_status status;
4798 status = ice_get_pfa_module_tlv(hw, &tlv, &tlv_len,
4799 ICE_SR_LINK_DEFAULT_OVERRIDE_PTR);
4801 ice_debug(hw, ICE_DBG_INIT, "Failed to read link override TLV.\n");
4805 /* Each port has its own config; calculate for our port */
4806 tlv_start = tlv + pi->lport * ICE_SR_PFA_LINK_OVERRIDE_WORDS +
4807 ICE_SR_PFA_LINK_OVERRIDE_OFFSET;
4809 /* link options first */
4810 status = ice_read_sr_word(hw, tlv_start, &buf);
4812 ice_debug(hw, ICE_DBG_INIT, "Failed to read override link options.\n");
4815 ldo->options = buf & ICE_LINK_OVERRIDE_OPT_M;
4816 ldo->phy_config = (buf & ICE_LINK_OVERRIDE_PHY_CFG_M) >>
4817 ICE_LINK_OVERRIDE_PHY_CFG_S;
4819 /* link PHY config */
4820 offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_FEC_OFFSET;
4821 status = ice_read_sr_word(hw, offset, &buf);
4823 ice_debug(hw, ICE_DBG_INIT, "Failed to read override phy config.\n");
4826 ldo->fec_options = buf & ICE_LINK_OVERRIDE_FEC_OPT_M;
4829 offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_PHY_OFFSET;
4830 for (i = 0; i < ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS; i++) {
4831 status = ice_read_sr_word(hw, (offset + i), &buf);
4833 ice_debug(hw, ICE_DBG_INIT, "Failed to read override link options.\n");
4836 /* shift 16 bits at a time to fill 64 bits */
4837 ldo->phy_type_low |= ((u64)buf << (i * 16));
4840 /* PHY types high */
4841 offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_PHY_OFFSET +
4842 ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS;
4843 for (i = 0; i < ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS; i++) {
4844 status = ice_read_sr_word(hw, (offset + i), &buf);
4846 ice_debug(hw, ICE_DBG_INIT, "Failed to read override link options.\n");
4849 /* shift 16 bits at a time to fill 64 bits */
4850 ldo->phy_type_high |= ((u64)buf << (i * 16));
4857 * ice_is_phy_caps_an_enabled - check if PHY capabilities autoneg is enabled
4858 * @caps: get PHY capability data
4860 bool ice_is_phy_caps_an_enabled(struct ice_aqc_get_phy_caps_data *caps)
4862 if (caps->caps & ICE_AQC_PHY_AN_MODE ||
4863 caps->low_power_ctrl_an & (ICE_AQC_PHY_AN_EN_CLAUSE28 |
4864 ICE_AQC_PHY_AN_EN_CLAUSE73 |
4865 ICE_AQC_PHY_AN_EN_CLAUSE37))
4872 * ice_aq_set_lldp_mib - Set the LLDP MIB
4873 * @hw: pointer to the HW struct
4874 * @mib_type: Local, Remote or both Local and Remote MIBs
4875 * @buf: pointer to the caller-supplied buffer to store the MIB block
4876 * @buf_size: size of the buffer (in bytes)
4877 * @cd: pointer to command details structure or NULL
4879 * Set the LLDP MIB. (0x0A08)
4882 ice_aq_set_lldp_mib(struct ice_hw *hw, u8 mib_type, void *buf, u16 buf_size,
4883 struct ice_sq_cd *cd)
4885 struct ice_aqc_lldp_set_local_mib *cmd;
4886 struct ice_aq_desc desc;
4888 cmd = &desc.params.lldp_set_mib;
4890 if (buf_size == 0 || !buf)
4891 return ICE_ERR_PARAM;
4893 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_lldp_set_local_mib);
4895 desc.flags |= CPU_TO_LE16((u16)ICE_AQ_FLAG_RD);
4896 desc.datalen = CPU_TO_LE16(buf_size);
4898 cmd->type = mib_type;
4899 cmd->length = CPU_TO_LE16(buf_size);
4901 return ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);
4905 * ice_fw_supports_lldp_fltr - check NVM version supports lldp_fltr_ctrl
4906 * @hw: pointer to HW struct
4908 bool ice_fw_supports_lldp_fltr_ctrl(struct ice_hw *hw)
4910 if (hw->mac_type != ICE_MAC_E810)
4913 if (hw->api_maj_ver == ICE_FW_API_LLDP_FLTR_MAJ) {
4914 if (hw->api_min_ver > ICE_FW_API_LLDP_FLTR_MIN)
4916 if (hw->api_min_ver == ICE_FW_API_LLDP_FLTR_MIN &&
4917 hw->api_patch >= ICE_FW_API_LLDP_FLTR_PATCH)
4919 } else if (hw->api_maj_ver > ICE_FW_API_LLDP_FLTR_MAJ) {
4926 * ice_lldp_fltr_add_remove - add or remove a LLDP Rx switch filter
4927 * @hw: pointer to HW struct
4928 * @vsi_num: absolute HW index for VSI
4929 * @add: boolean for if adding or removing a filter
4932 ice_lldp_fltr_add_remove(struct ice_hw *hw, u16 vsi_num, bool add)
4934 struct ice_aqc_lldp_filter_ctrl *cmd;
4935 struct ice_aq_desc desc;
4937 cmd = &desc.params.lldp_filter_ctrl;
4939 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_lldp_filter_ctrl);
4942 cmd->cmd_flags = ICE_AQC_LLDP_FILTER_ACTION_ADD;
4944 cmd->cmd_flags = ICE_AQC_LLDP_FILTER_ACTION_DELETE;
4946 cmd->vsi_num = CPU_TO_LE16(vsi_num);
4948 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
4952 * ice_fw_supports_report_dflt_cfg
4953 * @hw: pointer to the hardware structure
4955 * Checks if the firmware supports report default configuration
4957 bool ice_fw_supports_report_dflt_cfg(struct ice_hw *hw)
4959 if (hw->api_maj_ver == ICE_FW_API_REPORT_DFLT_CFG_MAJ) {
4960 if (hw->api_min_ver > ICE_FW_API_REPORT_DFLT_CFG_MIN)
4962 if (hw->api_min_ver == ICE_FW_API_REPORT_DFLT_CFG_MIN &&
4963 hw->api_patch >= ICE_FW_API_REPORT_DFLT_CFG_PATCH)
4965 } else if (hw->api_maj_ver > ICE_FW_API_REPORT_DFLT_CFG_MAJ) {