1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2001-2020 Intel Corporation
5 #include "ice_common.h"
7 #include "ice_adminq_cmd.h"
10 #include "ice_switch.h"
12 #define ICE_PF_RESET_WAIT_COUNT 300
15 * ice_set_mac_type - Sets MAC type
16 * @hw: pointer to the HW structure
18 * This function sets the MAC type of the adapter based on the
19 * vendor ID and device ID stored in the HW structure.
21 static enum ice_status ice_set_mac_type(struct ice_hw *hw)
23 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
25 if (hw->vendor_id != ICE_INTEL_VENDOR_ID)
26 return ICE_ERR_DEVICE_NOT_SUPPORTED;
28 switch (hw->device_id) {
29 case ICE_DEV_ID_E810C_BACKPLANE:
30 case ICE_DEV_ID_E810C_QSFP:
31 case ICE_DEV_ID_E810C_SFP:
32 case ICE_DEV_ID_E810_XXV_BACKPLANE:
33 case ICE_DEV_ID_E810_XXV_QSFP:
34 case ICE_DEV_ID_E810_XXV_SFP:
35 hw->mac_type = ICE_MAC_E810;
37 case ICE_DEV_ID_E822C_10G_BASE_T:
38 case ICE_DEV_ID_E822C_BACKPLANE:
39 case ICE_DEV_ID_E822C_QSFP:
40 case ICE_DEV_ID_E822C_SFP:
41 case ICE_DEV_ID_E822C_SGMII:
42 case ICE_DEV_ID_E822L_10G_BASE_T:
43 case ICE_DEV_ID_E822L_BACKPLANE:
44 case ICE_DEV_ID_E822L_SFP:
45 case ICE_DEV_ID_E822L_SGMII:
46 hw->mac_type = ICE_MAC_GENERIC;
49 hw->mac_type = ICE_MAC_UNKNOWN;
53 ice_debug(hw, ICE_DBG_INIT, "mac_type: %d\n", hw->mac_type);
58 * ice_clear_pf_cfg - Clear PF configuration
59 * @hw: pointer to the hardware structure
61 * Clears any existing PF configuration (VSIs, VSI lists, switch rules, port
62 * configuration, flow director filters, etc.).
64 enum ice_status ice_clear_pf_cfg(struct ice_hw *hw)
66 struct ice_aq_desc desc;
68 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pf_cfg);
70 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
74 * ice_aq_manage_mac_read - manage MAC address read command
75 * @hw: pointer to the HW struct
76 * @buf: a virtual buffer to hold the manage MAC read response
77 * @buf_size: Size of the virtual buffer
78 * @cd: pointer to command details structure or NULL
80 * This function is used to return per PF station MAC address (0x0107).
81 * NOTE: Upon successful completion of this command, MAC address information
82 * is returned in user specified buffer. Please interpret user specified
83 * buffer as "manage_mac_read" response.
84 * Response such as various MAC addresses are stored in HW struct (port.mac)
85 * ice_aq_discover_caps is expected to be called before this function is called.
87 static enum ice_status
88 ice_aq_manage_mac_read(struct ice_hw *hw, void *buf, u16 buf_size,
91 struct ice_aqc_manage_mac_read_resp *resp;
92 struct ice_aqc_manage_mac_read *cmd;
93 struct ice_aq_desc desc;
94 enum ice_status status;
98 cmd = &desc.params.mac_read;
100 if (buf_size < sizeof(*resp))
101 return ICE_ERR_BUF_TOO_SHORT;
103 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_read);
105 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);
109 resp = (struct ice_aqc_manage_mac_read_resp *)buf;
110 flags = LE16_TO_CPU(cmd->flags) & ICE_AQC_MAN_MAC_READ_M;
112 if (!(flags & ICE_AQC_MAN_MAC_LAN_ADDR_VALID)) {
113 ice_debug(hw, ICE_DBG_LAN, "got invalid MAC address\n");
117 /* A single port can report up to two (LAN and WoL) addresses */
118 for (i = 0; i < cmd->num_addr; i++)
119 if (resp[i].addr_type == ICE_AQC_MAN_MAC_ADDR_TYPE_LAN) {
120 ice_memcpy(hw->port_info->mac.lan_addr,
121 resp[i].mac_addr, ETH_ALEN,
123 ice_memcpy(hw->port_info->mac.perm_addr,
125 ETH_ALEN, ICE_DMA_TO_NONDMA);
132 * ice_aq_get_phy_caps - returns PHY capabilities
133 * @pi: port information structure
134 * @qual_mods: report qualified modules
135 * @report_mode: report mode capabilities
136 * @pcaps: structure for PHY capabilities to be filled
137 * @cd: pointer to command details structure or NULL
139 * Returns the various PHY capabilities supported on the Port (0x0600)
142 ice_aq_get_phy_caps(struct ice_port_info *pi, bool qual_mods, u8 report_mode,
143 struct ice_aqc_get_phy_caps_data *pcaps,
144 struct ice_sq_cd *cd)
146 struct ice_aqc_get_phy_caps *cmd;
147 u16 pcaps_size = sizeof(*pcaps);
148 struct ice_aq_desc desc;
149 enum ice_status status;
152 cmd = &desc.params.get_phy;
154 if (!pcaps || (report_mode & ~ICE_AQC_REPORT_MODE_M) || !pi)
155 return ICE_ERR_PARAM;
158 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_phy_caps);
161 cmd->param0 |= CPU_TO_LE16(ICE_AQC_GET_PHY_RQM);
163 cmd->param0 |= CPU_TO_LE16(report_mode);
164 status = ice_aq_send_cmd(hw, &desc, pcaps, pcaps_size, cd);
166 ice_debug(hw, ICE_DBG_LINK, "get phy caps - report_mode = 0x%x\n",
168 ice_debug(hw, ICE_DBG_LINK, " phy_type_low = 0x%llx\n",
169 (unsigned long long)LE64_TO_CPU(pcaps->phy_type_low));
170 ice_debug(hw, ICE_DBG_LINK, " phy_type_high = 0x%llx\n",
171 (unsigned long long)LE64_TO_CPU(pcaps->phy_type_high));
172 ice_debug(hw, ICE_DBG_LINK, " caps = 0x%x\n", pcaps->caps);
173 ice_debug(hw, ICE_DBG_LINK, " low_power_ctrl_an = 0x%x\n",
174 pcaps->low_power_ctrl_an);
175 ice_debug(hw, ICE_DBG_LINK, " eee_cap = 0x%x\n", pcaps->eee_cap);
176 ice_debug(hw, ICE_DBG_LINK, " eeer_value = 0x%x\n",
178 ice_debug(hw, ICE_DBG_LINK, " link_fec_options = 0x%x\n",
179 pcaps->link_fec_options);
180 ice_debug(hw, ICE_DBG_LINK, " module_compliance_enforcement = 0x%x\n",
181 pcaps->module_compliance_enforcement);
182 ice_debug(hw, ICE_DBG_LINK, " extended_compliance_code = 0x%x\n",
183 pcaps->extended_compliance_code);
184 ice_debug(hw, ICE_DBG_LINK, " module_type[0] = 0x%x\n",
185 pcaps->module_type[0]);
186 ice_debug(hw, ICE_DBG_LINK, " module_type[1] = 0x%x\n",
187 pcaps->module_type[1]);
188 ice_debug(hw, ICE_DBG_LINK, " module_type[2] = 0x%x\n",
189 pcaps->module_type[2]);
192 if (status == ICE_SUCCESS && report_mode == ICE_AQC_REPORT_TOPO_CAP) {
193 pi->phy.phy_type_low = LE64_TO_CPU(pcaps->phy_type_low);
194 pi->phy.phy_type_high = LE64_TO_CPU(pcaps->phy_type_high);
201 * ice_aq_get_link_topo_handle - get link topology node return status
202 * @pi: port information structure
203 * @node_type: requested node type
204 * @cd: pointer to command details structure or NULL
206 * Get link topology node return status for specified node type (0x06E0)
208 * Node type cage can be used to determine if cage is present. If AQC
209 * returns error (ENOENT), then no cage present. If no cage present, then
210 * connection type is backplane or BASE-T.
212 static enum ice_status
213 ice_aq_get_link_topo_handle(struct ice_port_info *pi, u8 node_type,
214 struct ice_sq_cd *cd)
216 struct ice_aqc_get_link_topo *cmd;
217 struct ice_aq_desc desc;
219 cmd = &desc.params.get_link_topo;
221 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_topo);
223 cmd->addr.node_type_ctx = (ICE_AQC_LINK_TOPO_NODE_CTX_PORT <<
224 ICE_AQC_LINK_TOPO_NODE_CTX_S);
227 cmd->addr.node_type_ctx |= (ICE_AQC_LINK_TOPO_NODE_TYPE_M & node_type);
229 return ice_aq_send_cmd(pi->hw, &desc, NULL, 0, cd);
233 * ice_is_media_cage_present
234 * @pi: port information structure
236 * Returns true if media cage is present, else false. If no cage, then
237 * media type is backplane or BASE-T.
239 static bool ice_is_media_cage_present(struct ice_port_info *pi)
241 /* Node type cage can be used to determine if cage is present. If AQC
242 * returns error (ENOENT), then no cage present. If no cage present then
243 * connection type is backplane or BASE-T.
245 return !ice_aq_get_link_topo_handle(pi,
246 ICE_AQC_LINK_TOPO_NODE_TYPE_CAGE,
251 * ice_get_media_type - Gets media type
252 * @pi: port information structure
254 static enum ice_media_type ice_get_media_type(struct ice_port_info *pi)
256 struct ice_link_status *hw_link_info;
259 return ICE_MEDIA_UNKNOWN;
261 hw_link_info = &pi->phy.link_info;
262 if (hw_link_info->phy_type_low && hw_link_info->phy_type_high)
263 /* If more than one media type is selected, report unknown */
264 return ICE_MEDIA_UNKNOWN;
266 if (hw_link_info->phy_type_low) {
267 switch (hw_link_info->phy_type_low) {
268 case ICE_PHY_TYPE_LOW_1000BASE_SX:
269 case ICE_PHY_TYPE_LOW_1000BASE_LX:
270 case ICE_PHY_TYPE_LOW_10GBASE_SR:
271 case ICE_PHY_TYPE_LOW_10GBASE_LR:
272 case ICE_PHY_TYPE_LOW_10G_SFI_C2C:
273 case ICE_PHY_TYPE_LOW_25GBASE_SR:
274 case ICE_PHY_TYPE_LOW_25GBASE_LR:
275 case ICE_PHY_TYPE_LOW_40GBASE_SR4:
276 case ICE_PHY_TYPE_LOW_40GBASE_LR4:
277 case ICE_PHY_TYPE_LOW_50GBASE_SR2:
278 case ICE_PHY_TYPE_LOW_50GBASE_LR2:
279 case ICE_PHY_TYPE_LOW_50GBASE_SR:
280 case ICE_PHY_TYPE_LOW_50GBASE_FR:
281 case ICE_PHY_TYPE_LOW_50GBASE_LR:
282 case ICE_PHY_TYPE_LOW_100GBASE_SR4:
283 case ICE_PHY_TYPE_LOW_100GBASE_LR4:
284 case ICE_PHY_TYPE_LOW_100GBASE_SR2:
285 case ICE_PHY_TYPE_LOW_100GBASE_DR:
286 return ICE_MEDIA_FIBER;
287 case ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC:
288 case ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC:
289 case ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC:
290 case ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC:
291 case ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC:
292 case ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC:
293 case ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC:
294 case ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC:
295 return ICE_MEDIA_FIBER;
296 case ICE_PHY_TYPE_LOW_100BASE_TX:
297 case ICE_PHY_TYPE_LOW_1000BASE_T:
298 case ICE_PHY_TYPE_LOW_2500BASE_T:
299 case ICE_PHY_TYPE_LOW_5GBASE_T:
300 case ICE_PHY_TYPE_LOW_10GBASE_T:
301 case ICE_PHY_TYPE_LOW_25GBASE_T:
302 return ICE_MEDIA_BASET;
303 case ICE_PHY_TYPE_LOW_10G_SFI_DA:
304 case ICE_PHY_TYPE_LOW_25GBASE_CR:
305 case ICE_PHY_TYPE_LOW_25GBASE_CR_S:
306 case ICE_PHY_TYPE_LOW_25GBASE_CR1:
307 case ICE_PHY_TYPE_LOW_40GBASE_CR4:
308 case ICE_PHY_TYPE_LOW_50GBASE_CR2:
309 case ICE_PHY_TYPE_LOW_50GBASE_CP:
310 case ICE_PHY_TYPE_LOW_100GBASE_CR4:
311 case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4:
312 case ICE_PHY_TYPE_LOW_100GBASE_CP2:
314 case ICE_PHY_TYPE_LOW_25G_AUI_C2C:
315 case ICE_PHY_TYPE_LOW_40G_XLAUI:
316 case ICE_PHY_TYPE_LOW_50G_LAUI2:
317 case ICE_PHY_TYPE_LOW_50G_AUI2:
318 case ICE_PHY_TYPE_LOW_50G_AUI1:
319 case ICE_PHY_TYPE_LOW_100G_AUI4:
320 case ICE_PHY_TYPE_LOW_100G_CAUI4:
321 if (ice_is_media_cage_present(pi))
322 return ICE_MEDIA_AUI;
324 case ICE_PHY_TYPE_LOW_1000BASE_KX:
325 case ICE_PHY_TYPE_LOW_2500BASE_KX:
326 case ICE_PHY_TYPE_LOW_2500BASE_X:
327 case ICE_PHY_TYPE_LOW_5GBASE_KR:
328 case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1:
329 case ICE_PHY_TYPE_LOW_25GBASE_KR:
330 case ICE_PHY_TYPE_LOW_25GBASE_KR1:
331 case ICE_PHY_TYPE_LOW_25GBASE_KR_S:
332 case ICE_PHY_TYPE_LOW_40GBASE_KR4:
333 case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4:
334 case ICE_PHY_TYPE_LOW_50GBASE_KR2:
335 case ICE_PHY_TYPE_LOW_100GBASE_KR4:
336 case ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4:
337 return ICE_MEDIA_BACKPLANE;
340 switch (hw_link_info->phy_type_high) {
341 case ICE_PHY_TYPE_HIGH_100G_AUI2:
342 case ICE_PHY_TYPE_HIGH_100G_CAUI2:
343 if (ice_is_media_cage_present(pi))
344 return ICE_MEDIA_AUI;
346 case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4:
347 return ICE_MEDIA_BACKPLANE;
348 case ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC:
349 case ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC:
350 return ICE_MEDIA_FIBER;
353 return ICE_MEDIA_UNKNOWN;
357 * ice_aq_get_link_info
358 * @pi: port information structure
359 * @ena_lse: enable/disable LinkStatusEvent reporting
360 * @link: pointer to link status structure - optional
361 * @cd: pointer to command details structure or NULL
363 * Get Link Status (0x607). Returns the link status of the adapter.
366 ice_aq_get_link_info(struct ice_port_info *pi, bool ena_lse,
367 struct ice_link_status *link, struct ice_sq_cd *cd)
369 struct ice_aqc_get_link_status_data link_data = { 0 };
370 struct ice_aqc_get_link_status *resp;
371 struct ice_link_status *li_old, *li;
372 enum ice_media_type *hw_media_type;
373 struct ice_fc_info *hw_fc_info;
374 bool tx_pause, rx_pause;
375 struct ice_aq_desc desc;
376 enum ice_status status;
381 return ICE_ERR_PARAM;
383 li_old = &pi->phy.link_info_old;
384 hw_media_type = &pi->phy.media_type;
385 li = &pi->phy.link_info;
386 hw_fc_info = &pi->fc;
388 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_status);
389 cmd_flags = (ena_lse) ? ICE_AQ_LSE_ENA : ICE_AQ_LSE_DIS;
390 resp = &desc.params.get_link_status;
391 resp->cmd_flags = CPU_TO_LE16(cmd_flags);
392 resp->lport_num = pi->lport;
394 status = ice_aq_send_cmd(hw, &desc, &link_data, sizeof(link_data), cd);
396 if (status != ICE_SUCCESS)
399 /* save off old link status information */
402 /* update current link status information */
403 li->link_speed = LE16_TO_CPU(link_data.link_speed);
404 li->phy_type_low = LE64_TO_CPU(link_data.phy_type_low);
405 li->phy_type_high = LE64_TO_CPU(link_data.phy_type_high);
406 *hw_media_type = ice_get_media_type(pi);
407 li->link_info = link_data.link_info;
408 li->an_info = link_data.an_info;
409 li->ext_info = link_data.ext_info;
410 li->max_frame_size = LE16_TO_CPU(link_data.max_frame_size);
411 li->fec_info = link_data.cfg & ICE_AQ_FEC_MASK;
412 li->topo_media_conflict = link_data.topo_media_conflict;
413 li->pacing = link_data.cfg & (ICE_AQ_CFG_PACING_M |
414 ICE_AQ_CFG_PACING_TYPE_M);
417 tx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_TX);
418 rx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_RX);
419 if (tx_pause && rx_pause)
420 hw_fc_info->current_mode = ICE_FC_FULL;
422 hw_fc_info->current_mode = ICE_FC_TX_PAUSE;
424 hw_fc_info->current_mode = ICE_FC_RX_PAUSE;
426 hw_fc_info->current_mode = ICE_FC_NONE;
428 li->lse_ena = !!(resp->cmd_flags & CPU_TO_LE16(ICE_AQ_LSE_IS_ENABLED));
430 ice_debug(hw, ICE_DBG_LINK, "get link info\n");
431 ice_debug(hw, ICE_DBG_LINK, " link_speed = 0x%x\n", li->link_speed);
432 ice_debug(hw, ICE_DBG_LINK, " phy_type_low = 0x%llx\n",
433 (unsigned long long)li->phy_type_low);
434 ice_debug(hw, ICE_DBG_LINK, " phy_type_high = 0x%llx\n",
435 (unsigned long long)li->phy_type_high);
436 ice_debug(hw, ICE_DBG_LINK, " media_type = 0x%x\n", *hw_media_type);
437 ice_debug(hw, ICE_DBG_LINK, " link_info = 0x%x\n", li->link_info);
438 ice_debug(hw, ICE_DBG_LINK, " an_info = 0x%x\n", li->an_info);
439 ice_debug(hw, ICE_DBG_LINK, " ext_info = 0x%x\n", li->ext_info);
440 ice_debug(hw, ICE_DBG_LINK, " fec_info = 0x%x\n", li->fec_info);
441 ice_debug(hw, ICE_DBG_LINK, " lse_ena = 0x%x\n", li->lse_ena);
442 ice_debug(hw, ICE_DBG_LINK, " max_frame = 0x%x\n",
444 ice_debug(hw, ICE_DBG_LINK, " pacing = 0x%x\n", li->pacing);
446 /* save link status information */
450 /* flag cleared so calling functions don't call AQ again */
451 pi->phy.get_link_info = false;
457 * ice_fill_tx_timer_and_fc_thresh
458 * @hw: pointer to the HW struct
459 * @cmd: pointer to MAC cfg structure
461 * Add Tx timer and FC refresh threshold info to Set MAC Config AQ command
465 ice_fill_tx_timer_and_fc_thresh(struct ice_hw *hw,
466 struct ice_aqc_set_mac_cfg *cmd)
468 u16 fc_thres_val, tx_timer_val;
471 /* We read back the transmit timer and fc threshold value of
472 * LFC. Thus, we will use index =
473 * PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX.
475 * Also, because we are opearating on transmit timer and fc
476 * threshold of LFC, we don't turn on any bit in tx_tmr_priority
478 #define IDX_OF_LFC PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX
480 /* Retrieve the transmit timer */
481 val = rd32(hw, PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(IDX_OF_LFC));
483 PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_HSEC_CTL_TX_PAUSE_QUANTA_M;
484 cmd->tx_tmr_value = CPU_TO_LE16(tx_timer_val);
486 /* Retrieve the fc threshold */
487 val = rd32(hw, PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(IDX_OF_LFC));
488 fc_thres_val = val & PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_M;
490 cmd->fc_refresh_threshold = CPU_TO_LE16(fc_thres_val);
495 * @hw: pointer to the HW struct
496 * @max_frame_size: Maximum Frame Size to be supported
497 * @cd: pointer to command details structure or NULL
499 * Set MAC configuration (0x0603)
502 ice_aq_set_mac_cfg(struct ice_hw *hw, u16 max_frame_size, struct ice_sq_cd *cd)
504 struct ice_aqc_set_mac_cfg *cmd;
505 struct ice_aq_desc desc;
507 cmd = &desc.params.set_mac_cfg;
509 if (max_frame_size == 0)
510 return ICE_ERR_PARAM;
512 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_mac_cfg);
514 cmd->max_frame_size = CPU_TO_LE16(max_frame_size);
516 ice_fill_tx_timer_and_fc_thresh(hw, cmd);
518 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
522 * ice_init_fltr_mgmt_struct - initializes filter management list and locks
523 * @hw: pointer to the HW struct
525 enum ice_status ice_init_fltr_mgmt_struct(struct ice_hw *hw)
527 struct ice_switch_info *sw;
528 enum ice_status status;
530 hw->switch_info = (struct ice_switch_info *)
531 ice_malloc(hw, sizeof(*hw->switch_info));
533 sw = hw->switch_info;
536 return ICE_ERR_NO_MEMORY;
538 INIT_LIST_HEAD(&sw->vsi_list_map_head);
540 status = ice_init_def_sw_recp(hw, &hw->switch_info->recp_list);
542 ice_free(hw, hw->switch_info);
549 * ice_cleanup_fltr_mgmt_single - clears single filter mngt struct
550 * @hw: pointer to the HW struct
551 * @sw: pointer to switch info struct for which function clears filters
554 ice_cleanup_fltr_mgmt_single(struct ice_hw *hw, struct ice_switch_info *sw)
556 struct ice_vsi_list_map_info *v_pos_map;
557 struct ice_vsi_list_map_info *v_tmp_map;
558 struct ice_sw_recipe *recps;
564 LIST_FOR_EACH_ENTRY_SAFE(v_pos_map, v_tmp_map, &sw->vsi_list_map_head,
565 ice_vsi_list_map_info, list_entry) {
566 LIST_DEL(&v_pos_map->list_entry);
567 ice_free(hw, v_pos_map);
569 recps = sw->recp_list;
570 for (i = 0; i < ICE_MAX_NUM_RECIPES; i++) {
571 struct ice_recp_grp_entry *rg_entry, *tmprg_entry;
573 recps[i].root_rid = i;
574 LIST_FOR_EACH_ENTRY_SAFE(rg_entry, tmprg_entry,
575 &recps[i].rg_list, ice_recp_grp_entry,
577 LIST_DEL(&rg_entry->l_entry);
578 ice_free(hw, rg_entry);
581 if (recps[i].adv_rule) {
582 struct ice_adv_fltr_mgmt_list_entry *tmp_entry;
583 struct ice_adv_fltr_mgmt_list_entry *lst_itr;
585 ice_destroy_lock(&recps[i].filt_rule_lock);
586 LIST_FOR_EACH_ENTRY_SAFE(lst_itr, tmp_entry,
587 &recps[i].filt_rules,
588 ice_adv_fltr_mgmt_list_entry,
590 LIST_DEL(&lst_itr->list_entry);
591 ice_free(hw, lst_itr->lkups);
592 ice_free(hw, lst_itr);
595 struct ice_fltr_mgmt_list_entry *lst_itr, *tmp_entry;
597 ice_destroy_lock(&recps[i].filt_rule_lock);
598 LIST_FOR_EACH_ENTRY_SAFE(lst_itr, tmp_entry,
599 &recps[i].filt_rules,
600 ice_fltr_mgmt_list_entry,
602 LIST_DEL(&lst_itr->list_entry);
603 ice_free(hw, lst_itr);
606 if (recps[i].root_buf)
607 ice_free(hw, recps[i].root_buf);
609 ice_rm_sw_replay_rule_info(hw, sw);
610 ice_free(hw, sw->recp_list);
615 * ice_cleanup_all_fltr_mgmt - cleanup filter management list and locks
616 * @hw: pointer to the HW struct
618 void ice_cleanup_fltr_mgmt_struct(struct ice_hw *hw)
620 ice_cleanup_fltr_mgmt_single(hw, hw->switch_info);
624 * ice_get_itr_intrl_gran
625 * @hw: pointer to the HW struct
627 * Determines the ITR/INTRL granularities based on the maximum aggregate
628 * bandwidth according to the device's configuration during power-on.
630 static void ice_get_itr_intrl_gran(struct ice_hw *hw)
632 u8 max_agg_bw = (rd32(hw, GL_PWR_MODE_CTL) &
633 GL_PWR_MODE_CTL_CAR_MAX_BW_M) >>
634 GL_PWR_MODE_CTL_CAR_MAX_BW_S;
636 switch (max_agg_bw) {
637 case ICE_MAX_AGG_BW_200G:
638 case ICE_MAX_AGG_BW_100G:
639 case ICE_MAX_AGG_BW_50G:
640 hw->itr_gran = ICE_ITR_GRAN_ABOVE_25;
641 hw->intrl_gran = ICE_INTRL_GRAN_ABOVE_25;
643 case ICE_MAX_AGG_BW_25G:
644 hw->itr_gran = ICE_ITR_GRAN_MAX_25;
645 hw->intrl_gran = ICE_INTRL_GRAN_MAX_25;
651 * ice_print_rollback_msg - print FW rollback message
652 * @hw: pointer to the hardware structure
654 void ice_print_rollback_msg(struct ice_hw *hw)
656 char nvm_str[ICE_NVM_VER_LEN] = { 0 };
657 struct ice_nvm_info *nvm = &hw->nvm;
658 struct ice_orom_info *orom;
662 SNPRINTF(nvm_str, sizeof(nvm_str), "%x.%02x 0x%x %d.%d.%d",
663 nvm->major_ver, nvm->minor_ver, nvm->eetrack, orom->major,
664 orom->build, orom->patch);
666 "Firmware rollback mode detected. Current version is NVM: %s, FW: %d.%d. Device may exhibit limited functionality. Refer to the Intel(R) Ethernet Adapters and Devices User Guide for details on firmware rollback mode\n",
667 nvm_str, hw->fw_maj_ver, hw->fw_min_ver);
671 * ice_init_hw - main hardware initialization routine
672 * @hw: pointer to the hardware structure
674 enum ice_status ice_init_hw(struct ice_hw *hw)
676 struct ice_aqc_get_phy_caps_data *pcaps;
677 enum ice_status status;
681 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
683 /* Set MAC type based on DeviceID */
684 status = ice_set_mac_type(hw);
688 hw->pf_id = (u8)(rd32(hw, PF_FUNC_RID) &
689 PF_FUNC_RID_FUNCTION_NUMBER_M) >>
690 PF_FUNC_RID_FUNCTION_NUMBER_S;
692 status = ice_reset(hw, ICE_RESET_PFR);
696 ice_get_itr_intrl_gran(hw);
698 status = ice_create_all_ctrlq(hw);
700 goto err_unroll_cqinit;
702 status = ice_init_nvm(hw);
704 goto err_unroll_cqinit;
706 if (ice_get_fw_mode(hw) == ICE_FW_MODE_ROLLBACK)
707 ice_print_rollback_msg(hw);
709 status = ice_clear_pf_cfg(hw);
711 goto err_unroll_cqinit;
713 /* Set bit to enable Flow Director filters */
714 wr32(hw, PFQF_FD_ENA, PFQF_FD_ENA_FD_ENA_M);
715 INIT_LIST_HEAD(&hw->fdir_list_head);
717 ice_clear_pxe_mode(hw);
719 status = ice_get_caps(hw);
721 goto err_unroll_cqinit;
723 hw->port_info = (struct ice_port_info *)
724 ice_malloc(hw, sizeof(*hw->port_info));
725 if (!hw->port_info) {
726 status = ICE_ERR_NO_MEMORY;
727 goto err_unroll_cqinit;
730 /* set the back pointer to HW */
731 hw->port_info->hw = hw;
733 /* Initialize port_info struct with switch configuration data */
734 status = ice_get_initial_sw_cfg(hw);
736 goto err_unroll_alloc;
739 /* Query the allocated resources for Tx scheduler */
740 status = ice_sched_query_res_alloc(hw);
742 ice_debug(hw, ICE_DBG_SCHED,
743 "Failed to get scheduler allocated resources\n");
744 goto err_unroll_alloc;
746 ice_sched_get_psm_clk_freq(hw);
748 /* Initialize port_info struct with scheduler data */
749 status = ice_sched_init_port(hw->port_info);
751 goto err_unroll_sched;
753 pcaps = (struct ice_aqc_get_phy_caps_data *)
754 ice_malloc(hw, sizeof(*pcaps));
756 status = ICE_ERR_NO_MEMORY;
757 goto err_unroll_sched;
760 /* Initialize port_info struct with PHY capabilities */
761 status = ice_aq_get_phy_caps(hw->port_info, false,
762 ICE_AQC_REPORT_TOPO_CAP, pcaps, NULL);
765 goto err_unroll_sched;
767 /* Initialize port_info struct with link information */
768 status = ice_aq_get_link_info(hw->port_info, false, NULL, NULL);
770 goto err_unroll_sched;
771 /* need a valid SW entry point to build a Tx tree */
772 if (!hw->sw_entry_point_layer) {
773 ice_debug(hw, ICE_DBG_SCHED, "invalid sw entry point\n");
774 status = ICE_ERR_CFG;
775 goto err_unroll_sched;
777 INIT_LIST_HEAD(&hw->agg_list);
778 /* Initialize max burst size */
779 if (!hw->max_burst_size)
780 ice_cfg_rl_burst_size(hw, ICE_SCHED_DFLT_BURST_SIZE);
781 status = ice_init_fltr_mgmt_struct(hw);
783 goto err_unroll_sched;
785 /* Get MAC information */
786 /* A single port can report up to two (LAN and WoL) addresses */
787 mac_buf = ice_calloc(hw, 2,
788 sizeof(struct ice_aqc_manage_mac_read_resp));
789 mac_buf_len = 2 * sizeof(struct ice_aqc_manage_mac_read_resp);
792 status = ICE_ERR_NO_MEMORY;
793 goto err_unroll_fltr_mgmt_struct;
796 status = ice_aq_manage_mac_read(hw, mac_buf, mac_buf_len, NULL);
797 ice_free(hw, mac_buf);
800 goto err_unroll_fltr_mgmt_struct;
801 /* enable jumbo frame support at MAC level */
802 status = ice_aq_set_mac_cfg(hw, ICE_AQ_SET_MAC_FRAME_SIZE_MAX, NULL);
804 goto err_unroll_fltr_mgmt_struct;
805 /* Obtain counter base index which would be used by flow director */
806 status = ice_alloc_fd_res_cntr(hw, &hw->fd_ctr_base);
808 goto err_unroll_fltr_mgmt_struct;
809 status = ice_init_hw_tbls(hw);
811 goto err_unroll_fltr_mgmt_struct;
812 ice_init_lock(&hw->tnl_lock);
815 err_unroll_fltr_mgmt_struct:
816 ice_cleanup_fltr_mgmt_struct(hw);
818 ice_sched_cleanup_all(hw);
820 ice_free(hw, hw->port_info);
821 hw->port_info = NULL;
823 ice_destroy_all_ctrlq(hw);
828 * ice_deinit_hw - unroll initialization operations done by ice_init_hw
829 * @hw: pointer to the hardware structure
831 * This should be called only during nominal operation, not as a result of
832 * ice_init_hw() failing since ice_init_hw() will take care of unrolling
833 * applicable initializations if it fails for any reason.
835 void ice_deinit_hw(struct ice_hw *hw)
837 ice_free_fd_res_cntr(hw, hw->fd_ctr_base);
838 ice_cleanup_fltr_mgmt_struct(hw);
840 ice_sched_cleanup_all(hw);
841 ice_sched_clear_agg(hw);
843 ice_free_hw_tbls(hw);
844 ice_destroy_lock(&hw->tnl_lock);
847 ice_free(hw, hw->port_info);
848 hw->port_info = NULL;
851 ice_destroy_all_ctrlq(hw);
853 /* Clear VSI contexts if not already cleared */
854 ice_clear_all_vsi_ctx(hw);
858 * ice_check_reset - Check to see if a global reset is complete
859 * @hw: pointer to the hardware structure
861 enum ice_status ice_check_reset(struct ice_hw *hw)
863 u32 cnt, reg = 0, grst_delay, uld_mask;
865 /* Poll for Device Active state in case a recent CORER, GLOBR,
866 * or EMPR has occurred. The grst delay value is in 100ms units.
867 * Add 1sec for outstanding AQ commands that can take a long time.
869 grst_delay = ((rd32(hw, GLGEN_RSTCTL) & GLGEN_RSTCTL_GRSTDEL_M) >>
870 GLGEN_RSTCTL_GRSTDEL_S) + 10;
872 for (cnt = 0; cnt < grst_delay; cnt++) {
873 ice_msec_delay(100, true);
874 reg = rd32(hw, GLGEN_RSTAT);
875 if (!(reg & GLGEN_RSTAT_DEVSTATE_M))
879 if (cnt == grst_delay) {
880 ice_debug(hw, ICE_DBG_INIT,
881 "Global reset polling failed to complete.\n");
882 return ICE_ERR_RESET_FAILED;
885 #define ICE_RESET_DONE_MASK (GLNVM_ULD_PCIER_DONE_M |\
886 GLNVM_ULD_PCIER_DONE_1_M |\
887 GLNVM_ULD_CORER_DONE_M |\
888 GLNVM_ULD_GLOBR_DONE_M |\
889 GLNVM_ULD_POR_DONE_M |\
890 GLNVM_ULD_POR_DONE_1_M |\
891 GLNVM_ULD_PCIER_DONE_2_M)
893 uld_mask = ICE_RESET_DONE_MASK;
895 /* Device is Active; check Global Reset processes are done */
896 for (cnt = 0; cnt < ICE_PF_RESET_WAIT_COUNT; cnt++) {
897 reg = rd32(hw, GLNVM_ULD) & uld_mask;
898 if (reg == uld_mask) {
899 ice_debug(hw, ICE_DBG_INIT,
900 "Global reset processes done. %d\n", cnt);
903 ice_msec_delay(10, true);
906 if (cnt == ICE_PF_RESET_WAIT_COUNT) {
907 ice_debug(hw, ICE_DBG_INIT,
908 "Wait for Reset Done timed out. GLNVM_ULD = 0x%x\n",
910 return ICE_ERR_RESET_FAILED;
917 * ice_pf_reset - Reset the PF
918 * @hw: pointer to the hardware structure
920 * If a global reset has been triggered, this function checks
921 * for its completion and then issues the PF reset
923 static enum ice_status ice_pf_reset(struct ice_hw *hw)
927 /* If at function entry a global reset was already in progress, i.e.
928 * state is not 'device active' or any of the reset done bits are not
929 * set in GLNVM_ULD, there is no need for a PF Reset; poll until the
930 * global reset is done.
932 if ((rd32(hw, GLGEN_RSTAT) & GLGEN_RSTAT_DEVSTATE_M) ||
933 (rd32(hw, GLNVM_ULD) & ICE_RESET_DONE_MASK) ^ ICE_RESET_DONE_MASK) {
934 /* poll on global reset currently in progress until done */
935 if (ice_check_reset(hw))
936 return ICE_ERR_RESET_FAILED;
942 reg = rd32(hw, PFGEN_CTRL);
944 wr32(hw, PFGEN_CTRL, (reg | PFGEN_CTRL_PFSWR_M));
946 /* Wait for the PFR to complete. The wait time is the global config lock
947 * timeout plus the PFR timeout which will account for a possible reset
948 * that is occurring during a download package operation.
950 for (cnt = 0; cnt < ICE_GLOBAL_CFG_LOCK_TIMEOUT +
951 ICE_PF_RESET_WAIT_COUNT; cnt++) {
952 reg = rd32(hw, PFGEN_CTRL);
953 if (!(reg & PFGEN_CTRL_PFSWR_M))
956 ice_msec_delay(1, true);
959 if (cnt == ICE_PF_RESET_WAIT_COUNT) {
960 ice_debug(hw, ICE_DBG_INIT,
961 "PF reset polling failed to complete.\n");
962 return ICE_ERR_RESET_FAILED;
969 * ice_reset - Perform different types of reset
970 * @hw: pointer to the hardware structure
971 * @req: reset request
973 * This function triggers a reset as specified by the req parameter.
976 * If anything other than a PF reset is triggered, PXE mode is restored.
977 * This has to be cleared using ice_clear_pxe_mode again, once the AQ
978 * interface has been restored in the rebuild flow.
980 enum ice_status ice_reset(struct ice_hw *hw, enum ice_reset_req req)
986 return ice_pf_reset(hw);
987 case ICE_RESET_CORER:
988 ice_debug(hw, ICE_DBG_INIT, "CoreR requested\n");
989 val = GLGEN_RTRIG_CORER_M;
991 case ICE_RESET_GLOBR:
992 ice_debug(hw, ICE_DBG_INIT, "GlobalR requested\n");
993 val = GLGEN_RTRIG_GLOBR_M;
996 return ICE_ERR_PARAM;
999 val |= rd32(hw, GLGEN_RTRIG);
1000 wr32(hw, GLGEN_RTRIG, val);
1003 /* wait for the FW to be ready */
1004 return ice_check_reset(hw);
1008 * ice_copy_rxq_ctx_to_hw
1009 * @hw: pointer to the hardware structure
1010 * @ice_rxq_ctx: pointer to the rxq context
1011 * @rxq_index: the index of the Rx queue
1013 * Copies rxq context from dense structure to HW register space
1015 static enum ice_status
1016 ice_copy_rxq_ctx_to_hw(struct ice_hw *hw, u8 *ice_rxq_ctx, u32 rxq_index)
1021 return ICE_ERR_BAD_PTR;
1023 if (rxq_index > QRX_CTRL_MAX_INDEX)
1024 return ICE_ERR_PARAM;
1026 /* Copy each dword separately to HW */
1027 for (i = 0; i < ICE_RXQ_CTX_SIZE_DWORDS; i++) {
1028 wr32(hw, QRX_CONTEXT(i, rxq_index),
1029 *((u32 *)(ice_rxq_ctx + (i * sizeof(u32)))));
1031 ice_debug(hw, ICE_DBG_QCTX, "qrxdata[%d]: %08X\n", i,
1032 *((u32 *)(ice_rxq_ctx + (i * sizeof(u32)))));
1038 /* LAN Rx Queue Context */
1039 static const struct ice_ctx_ele ice_rlan_ctx_info[] = {
1040 /* Field Width LSB */
1041 ICE_CTX_STORE(ice_rlan_ctx, head, 13, 0),
1042 ICE_CTX_STORE(ice_rlan_ctx, cpuid, 8, 13),
1043 ICE_CTX_STORE(ice_rlan_ctx, base, 57, 32),
1044 ICE_CTX_STORE(ice_rlan_ctx, qlen, 13, 89),
1045 ICE_CTX_STORE(ice_rlan_ctx, dbuf, 7, 102),
1046 ICE_CTX_STORE(ice_rlan_ctx, hbuf, 5, 109),
1047 ICE_CTX_STORE(ice_rlan_ctx, dtype, 2, 114),
1048 ICE_CTX_STORE(ice_rlan_ctx, dsize, 1, 116),
1049 ICE_CTX_STORE(ice_rlan_ctx, crcstrip, 1, 117),
1050 ICE_CTX_STORE(ice_rlan_ctx, l2tsel, 1, 119),
1051 ICE_CTX_STORE(ice_rlan_ctx, hsplit_0, 4, 120),
1052 ICE_CTX_STORE(ice_rlan_ctx, hsplit_1, 2, 124),
1053 ICE_CTX_STORE(ice_rlan_ctx, showiv, 1, 127),
1054 ICE_CTX_STORE(ice_rlan_ctx, rxmax, 14, 174),
1055 ICE_CTX_STORE(ice_rlan_ctx, tphrdesc_ena, 1, 193),
1056 ICE_CTX_STORE(ice_rlan_ctx, tphwdesc_ena, 1, 194),
1057 ICE_CTX_STORE(ice_rlan_ctx, tphdata_ena, 1, 195),
1058 ICE_CTX_STORE(ice_rlan_ctx, tphhead_ena, 1, 196),
1059 ICE_CTX_STORE(ice_rlan_ctx, lrxqthresh, 3, 198),
1060 ICE_CTX_STORE(ice_rlan_ctx, prefena, 1, 201),
1066 * @hw: pointer to the hardware structure
1067 * @rlan_ctx: pointer to the rxq context
1068 * @rxq_index: the index of the Rx queue
1070 * Converts rxq context from sparse to dense structure and then writes
1071 * it to HW register space and enables the hardware to prefetch descriptors
1072 * instead of only fetching them on demand
1075 ice_write_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx,
1078 u8 ctx_buf[ICE_RXQ_CTX_SZ] = { 0 };
1081 return ICE_ERR_BAD_PTR;
1083 rlan_ctx->prefena = 1;
1085 ice_set_ctx(hw, (u8 *)rlan_ctx, ctx_buf, ice_rlan_ctx_info);
1086 return ice_copy_rxq_ctx_to_hw(hw, ctx_buf, rxq_index);
1091 * @hw: pointer to the hardware structure
1092 * @rxq_index: the index of the Rx queue to clear
1094 * Clears rxq context in HW register space
1096 enum ice_status ice_clear_rxq_ctx(struct ice_hw *hw, u32 rxq_index)
1100 if (rxq_index > QRX_CTRL_MAX_INDEX)
1101 return ICE_ERR_PARAM;
1103 /* Clear each dword register separately */
1104 for (i = 0; i < ICE_RXQ_CTX_SIZE_DWORDS; i++)
1105 wr32(hw, QRX_CONTEXT(i, rxq_index), 0);
1110 /* LAN Tx Queue Context */
1111 const struct ice_ctx_ele ice_tlan_ctx_info[] = {
1112 /* Field Width LSB */
1113 ICE_CTX_STORE(ice_tlan_ctx, base, 57, 0),
1114 ICE_CTX_STORE(ice_tlan_ctx, port_num, 3, 57),
1115 ICE_CTX_STORE(ice_tlan_ctx, cgd_num, 5, 60),
1116 ICE_CTX_STORE(ice_tlan_ctx, pf_num, 3, 65),
1117 ICE_CTX_STORE(ice_tlan_ctx, vmvf_num, 10, 68),
1118 ICE_CTX_STORE(ice_tlan_ctx, vmvf_type, 2, 78),
1119 ICE_CTX_STORE(ice_tlan_ctx, src_vsi, 10, 80),
1120 ICE_CTX_STORE(ice_tlan_ctx, tsyn_ena, 1, 90),
1121 ICE_CTX_STORE(ice_tlan_ctx, internal_usage_flag, 1, 91),
1122 ICE_CTX_STORE(ice_tlan_ctx, alt_vlan, 1, 92),
1123 ICE_CTX_STORE(ice_tlan_ctx, cpuid, 8, 93),
1124 ICE_CTX_STORE(ice_tlan_ctx, wb_mode, 1, 101),
1125 ICE_CTX_STORE(ice_tlan_ctx, tphrd_desc, 1, 102),
1126 ICE_CTX_STORE(ice_tlan_ctx, tphrd, 1, 103),
1127 ICE_CTX_STORE(ice_tlan_ctx, tphwr_desc, 1, 104),
1128 ICE_CTX_STORE(ice_tlan_ctx, cmpq_id, 9, 105),
1129 ICE_CTX_STORE(ice_tlan_ctx, qnum_in_func, 14, 114),
1130 ICE_CTX_STORE(ice_tlan_ctx, itr_notification_mode, 1, 128),
1131 ICE_CTX_STORE(ice_tlan_ctx, adjust_prof_id, 6, 129),
1132 ICE_CTX_STORE(ice_tlan_ctx, qlen, 13, 135),
1133 ICE_CTX_STORE(ice_tlan_ctx, quanta_prof_idx, 4, 148),
1134 ICE_CTX_STORE(ice_tlan_ctx, tso_ena, 1, 152),
1135 ICE_CTX_STORE(ice_tlan_ctx, tso_qnum, 11, 153),
1136 ICE_CTX_STORE(ice_tlan_ctx, legacy_int, 1, 164),
1137 ICE_CTX_STORE(ice_tlan_ctx, drop_ena, 1, 165),
1138 ICE_CTX_STORE(ice_tlan_ctx, cache_prof_idx, 2, 166),
1139 ICE_CTX_STORE(ice_tlan_ctx, pkt_shaper_prof_idx, 3, 168),
1140 ICE_CTX_STORE(ice_tlan_ctx, int_q_state, 122, 171),
1145 * ice_copy_tx_cmpltnq_ctx_to_hw
1146 * @hw: pointer to the hardware structure
1147 * @ice_tx_cmpltnq_ctx: pointer to the Tx completion queue context
1148 * @tx_cmpltnq_index: the index of the completion queue
1150 * Copies Tx completion queue context from dense structure to HW register space
1152 static enum ice_status
1153 ice_copy_tx_cmpltnq_ctx_to_hw(struct ice_hw *hw, u8 *ice_tx_cmpltnq_ctx,
1154 u32 tx_cmpltnq_index)
1158 if (!ice_tx_cmpltnq_ctx)
1159 return ICE_ERR_BAD_PTR;
1161 if (tx_cmpltnq_index > GLTCLAN_CQ_CNTX0_MAX_INDEX)
1162 return ICE_ERR_PARAM;
1164 /* Copy each dword separately to HW */
1165 for (i = 0; i < ICE_TX_CMPLTNQ_CTX_SIZE_DWORDS; i++) {
1166 wr32(hw, GLTCLAN_CQ_CNTX(i, tx_cmpltnq_index),
1167 *((u32 *)(ice_tx_cmpltnq_ctx + (i * sizeof(u32)))));
1169 ice_debug(hw, ICE_DBG_QCTX, "cmpltnqdata[%d]: %08X\n", i,
1170 *((u32 *)(ice_tx_cmpltnq_ctx + (i * sizeof(u32)))));
1176 /* LAN Tx Completion Queue Context */
1177 static const struct ice_ctx_ele ice_tx_cmpltnq_ctx_info[] = {
1178 /* Field Width LSB */
1179 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, base, 57, 0),
1180 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, q_len, 18, 64),
1181 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, generation, 1, 96),
1182 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, wrt_ptr, 22, 97),
1183 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, pf_num, 3, 128),
1184 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, vmvf_num, 10, 131),
1185 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, vmvf_type, 2, 141),
1186 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, tph_desc_wr, 1, 160),
1187 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, cpuid, 8, 161),
1188 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, cmpltn_cache, 512, 192),
1193 * ice_write_tx_cmpltnq_ctx
1194 * @hw: pointer to the hardware structure
1195 * @tx_cmpltnq_ctx: pointer to the completion queue context
1196 * @tx_cmpltnq_index: the index of the completion queue
1198 * Converts completion queue context from sparse to dense structure and then
1199 * writes it to HW register space
1202 ice_write_tx_cmpltnq_ctx(struct ice_hw *hw,
1203 struct ice_tx_cmpltnq_ctx *tx_cmpltnq_ctx,
1204 u32 tx_cmpltnq_index)
1206 u8 ctx_buf[ICE_TX_CMPLTNQ_CTX_SIZE_DWORDS * sizeof(u32)] = { 0 };
1208 ice_set_ctx(hw, (u8 *)tx_cmpltnq_ctx, ctx_buf, ice_tx_cmpltnq_ctx_info);
1209 return ice_copy_tx_cmpltnq_ctx_to_hw(hw, ctx_buf, tx_cmpltnq_index);
1213 * ice_clear_tx_cmpltnq_ctx
1214 * @hw: pointer to the hardware structure
1215 * @tx_cmpltnq_index: the index of the completion queue to clear
1217 * Clears Tx completion queue context in HW register space
1220 ice_clear_tx_cmpltnq_ctx(struct ice_hw *hw, u32 tx_cmpltnq_index)
1224 if (tx_cmpltnq_index > GLTCLAN_CQ_CNTX0_MAX_INDEX)
1225 return ICE_ERR_PARAM;
1227 /* Clear each dword register separately */
1228 for (i = 0; i < ICE_TX_CMPLTNQ_CTX_SIZE_DWORDS; i++)
1229 wr32(hw, GLTCLAN_CQ_CNTX(i, tx_cmpltnq_index), 0);
1235 * ice_copy_tx_drbell_q_ctx_to_hw
1236 * @hw: pointer to the hardware structure
1237 * @ice_tx_drbell_q_ctx: pointer to the doorbell queue context
1238 * @tx_drbell_q_index: the index of the doorbell queue
1240 * Copies doorbell queue context from dense structure to HW register space
1242 static enum ice_status
1243 ice_copy_tx_drbell_q_ctx_to_hw(struct ice_hw *hw, u8 *ice_tx_drbell_q_ctx,
1244 u32 tx_drbell_q_index)
1248 if (!ice_tx_drbell_q_ctx)
1249 return ICE_ERR_BAD_PTR;
1251 if (tx_drbell_q_index > QTX_COMM_DBLQ_DBELL_MAX_INDEX)
1252 return ICE_ERR_PARAM;
1254 /* Copy each dword separately to HW */
1255 for (i = 0; i < ICE_TX_DRBELL_Q_CTX_SIZE_DWORDS; i++) {
1256 wr32(hw, QTX_COMM_DBLQ_CNTX(i, tx_drbell_q_index),
1257 *((u32 *)(ice_tx_drbell_q_ctx + (i * sizeof(u32)))));
1259 ice_debug(hw, ICE_DBG_QCTX, "tx_drbell_qdata[%d]: %08X\n", i,
1260 *((u32 *)(ice_tx_drbell_q_ctx + (i * sizeof(u32)))));
1266 /* LAN Tx Doorbell Queue Context info */
1267 static const struct ice_ctx_ele ice_tx_drbell_q_ctx_info[] = {
1268 /* Field Width LSB */
1269 ICE_CTX_STORE(ice_tx_drbell_q_ctx, base, 57, 0),
1270 ICE_CTX_STORE(ice_tx_drbell_q_ctx, ring_len, 13, 64),
1271 ICE_CTX_STORE(ice_tx_drbell_q_ctx, pf_num, 3, 80),
1272 ICE_CTX_STORE(ice_tx_drbell_q_ctx, vf_num, 8, 84),
1273 ICE_CTX_STORE(ice_tx_drbell_q_ctx, vmvf_type, 2, 94),
1274 ICE_CTX_STORE(ice_tx_drbell_q_ctx, cpuid, 8, 96),
1275 ICE_CTX_STORE(ice_tx_drbell_q_ctx, tph_desc_rd, 1, 104),
1276 ICE_CTX_STORE(ice_tx_drbell_q_ctx, tph_desc_wr, 1, 108),
1277 ICE_CTX_STORE(ice_tx_drbell_q_ctx, db_q_en, 1, 112),
1278 ICE_CTX_STORE(ice_tx_drbell_q_ctx, rd_head, 13, 128),
1279 ICE_CTX_STORE(ice_tx_drbell_q_ctx, rd_tail, 13, 144),
1284 * ice_write_tx_drbell_q_ctx
1285 * @hw: pointer to the hardware structure
1286 * @tx_drbell_q_ctx: pointer to the doorbell queue context
1287 * @tx_drbell_q_index: the index of the doorbell queue
1289 * Converts doorbell queue context from sparse to dense structure and then
1290 * writes it to HW register space
1293 ice_write_tx_drbell_q_ctx(struct ice_hw *hw,
1294 struct ice_tx_drbell_q_ctx *tx_drbell_q_ctx,
1295 u32 tx_drbell_q_index)
1297 u8 ctx_buf[ICE_TX_DRBELL_Q_CTX_SIZE_DWORDS * sizeof(u32)] = { 0 };
1299 ice_set_ctx(hw, (u8 *)tx_drbell_q_ctx, ctx_buf,
1300 ice_tx_drbell_q_ctx_info);
1301 return ice_copy_tx_drbell_q_ctx_to_hw(hw, ctx_buf, tx_drbell_q_index);
1305 * ice_clear_tx_drbell_q_ctx
1306 * @hw: pointer to the hardware structure
1307 * @tx_drbell_q_index: the index of the doorbell queue to clear
1309 * Clears doorbell queue context in HW register space
1312 ice_clear_tx_drbell_q_ctx(struct ice_hw *hw, u32 tx_drbell_q_index)
1316 if (tx_drbell_q_index > QTX_COMM_DBLQ_DBELL_MAX_INDEX)
1317 return ICE_ERR_PARAM;
1319 /* Clear each dword register separately */
1320 for (i = 0; i < ICE_TX_DRBELL_Q_CTX_SIZE_DWORDS; i++)
1321 wr32(hw, QTX_COMM_DBLQ_CNTX(i, tx_drbell_q_index), 0);
1326 /* FW Admin Queue command wrappers */
1329 * ice_aq_send_cmd - send FW Admin Queue command to FW Admin Queue
1330 * @hw: pointer to the HW struct
1331 * @desc: descriptor describing the command
1332 * @buf: buffer to use for indirect commands (NULL for direct commands)
1333 * @buf_size: size of buffer for indirect commands (0 for direct commands)
1334 * @cd: pointer to command details structure
1336 * Helper function to send FW Admin Queue commands to the FW Admin Queue.
1339 ice_aq_send_cmd(struct ice_hw *hw, struct ice_aq_desc *desc, void *buf,
1340 u16 buf_size, struct ice_sq_cd *cd)
1342 if (hw->aq_send_cmd_fn) {
1343 enum ice_status status = ICE_ERR_NOT_READY;
1344 u16 retval = ICE_AQ_RC_OK;
1346 ice_acquire_lock(&hw->adminq.sq_lock);
1347 if (!hw->aq_send_cmd_fn(hw->aq_send_cmd_param, desc,
1349 retval = LE16_TO_CPU(desc->retval);
1350 /* strip off FW internal code */
1353 if (retval == ICE_AQ_RC_OK)
1354 status = ICE_SUCCESS;
1356 status = ICE_ERR_AQ_ERROR;
1359 hw->adminq.sq_last_status = (enum ice_aq_err)retval;
1360 ice_release_lock(&hw->adminq.sq_lock);
1364 return ice_sq_send_cmd(hw, &hw->adminq, desc, buf, buf_size, cd);
1369 * @hw: pointer to the HW struct
1370 * @cd: pointer to command details structure or NULL
1372 * Get the firmware version (0x0001) from the admin queue commands
1374 enum ice_status ice_aq_get_fw_ver(struct ice_hw *hw, struct ice_sq_cd *cd)
1376 struct ice_aqc_get_ver *resp;
1377 struct ice_aq_desc desc;
1378 enum ice_status status;
1380 resp = &desc.params.get_ver;
1382 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_ver);
1384 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
1387 hw->fw_branch = resp->fw_branch;
1388 hw->fw_maj_ver = resp->fw_major;
1389 hw->fw_min_ver = resp->fw_minor;
1390 hw->fw_patch = resp->fw_patch;
1391 hw->fw_build = LE32_TO_CPU(resp->fw_build);
1392 hw->api_branch = resp->api_branch;
1393 hw->api_maj_ver = resp->api_major;
1394 hw->api_min_ver = resp->api_minor;
1395 hw->api_patch = resp->api_patch;
1402 * ice_aq_send_driver_ver
1403 * @hw: pointer to the HW struct
1404 * @dv: driver's major, minor version
1405 * @cd: pointer to command details structure or NULL
1407 * Send the driver version (0x0002) to the firmware
1410 ice_aq_send_driver_ver(struct ice_hw *hw, struct ice_driver_ver *dv,
1411 struct ice_sq_cd *cd)
1413 struct ice_aqc_driver_ver *cmd;
1414 struct ice_aq_desc desc;
1417 cmd = &desc.params.driver_ver;
1420 return ICE_ERR_PARAM;
1422 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_driver_ver);
1424 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
1425 cmd->major_ver = dv->major_ver;
1426 cmd->minor_ver = dv->minor_ver;
1427 cmd->build_ver = dv->build_ver;
1428 cmd->subbuild_ver = dv->subbuild_ver;
1431 while (len < sizeof(dv->driver_string) &&
1432 IS_ASCII(dv->driver_string[len]) && dv->driver_string[len])
1435 return ice_aq_send_cmd(hw, &desc, dv->driver_string, len, cd);
1440 * @hw: pointer to the HW struct
1441 * @unloading: is the driver unloading itself
1443 * Tell the Firmware that we're shutting down the AdminQ and whether
1444 * or not the driver is unloading as well (0x0003).
1446 enum ice_status ice_aq_q_shutdown(struct ice_hw *hw, bool unloading)
1448 struct ice_aqc_q_shutdown *cmd;
1449 struct ice_aq_desc desc;
1451 cmd = &desc.params.q_shutdown;
1453 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_q_shutdown);
1456 cmd->driver_unloading = ICE_AQC_DRIVER_UNLOADING;
1458 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
1463 * @hw: pointer to the HW struct
1465 * @access: access type
1466 * @sdp_number: resource number
1467 * @timeout: the maximum time in ms that the driver may hold the resource
1468 * @cd: pointer to command details structure or NULL
1470 * Requests common resource using the admin queue commands (0x0008).
1471 * When attempting to acquire the Global Config Lock, the driver can
1472 * learn of three states:
1473 * 1) ICE_SUCCESS - acquired lock, and can perform download package
1474 * 2) ICE_ERR_AQ_ERROR - did not get lock, driver should fail to load
1475 * 3) ICE_ERR_AQ_NO_WORK - did not get lock, but another driver has
1476 * successfully downloaded the package; the driver does
1477 * not have to download the package and can continue
1480 * Note that if the caller is in an acquire lock, perform action, release lock
1481 * phase of operation, it is possible that the FW may detect a timeout and issue
1482 * a CORER. In this case, the driver will receive a CORER interrupt and will
1483 * have to determine its cause. The calling thread that is handling this flow
1484 * will likely get an error propagated back to it indicating the Download
1485 * Package, Update Package or the Release Resource AQ commands timed out.
1487 static enum ice_status
1488 ice_aq_req_res(struct ice_hw *hw, enum ice_aq_res_ids res,
1489 enum ice_aq_res_access_type access, u8 sdp_number, u32 *timeout,
1490 struct ice_sq_cd *cd)
1492 struct ice_aqc_req_res *cmd_resp;
1493 struct ice_aq_desc desc;
1494 enum ice_status status;
1496 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
1498 cmd_resp = &desc.params.res_owner;
1500 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_req_res);
1502 cmd_resp->res_id = CPU_TO_LE16(res);
1503 cmd_resp->access_type = CPU_TO_LE16(access);
1504 cmd_resp->res_number = CPU_TO_LE32(sdp_number);
1505 cmd_resp->timeout = CPU_TO_LE32(*timeout);
1508 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
1510 /* The completion specifies the maximum time in ms that the driver
1511 * may hold the resource in the Timeout field.
1514 /* Global config lock response utilizes an additional status field.
1516 * If the Global config lock resource is held by some other driver, the
1517 * command completes with ICE_AQ_RES_GLBL_IN_PROG in the status field
1518 * and the timeout field indicates the maximum time the current owner
1519 * of the resource has to free it.
1521 if (res == ICE_GLOBAL_CFG_LOCK_RES_ID) {
1522 if (LE16_TO_CPU(cmd_resp->status) == ICE_AQ_RES_GLBL_SUCCESS) {
1523 *timeout = LE32_TO_CPU(cmd_resp->timeout);
1525 } else if (LE16_TO_CPU(cmd_resp->status) ==
1526 ICE_AQ_RES_GLBL_IN_PROG) {
1527 *timeout = LE32_TO_CPU(cmd_resp->timeout);
1528 return ICE_ERR_AQ_ERROR;
1529 } else if (LE16_TO_CPU(cmd_resp->status) ==
1530 ICE_AQ_RES_GLBL_DONE) {
1531 return ICE_ERR_AQ_NO_WORK;
1534 /* invalid FW response, force a timeout immediately */
1536 return ICE_ERR_AQ_ERROR;
1539 /* If the resource is held by some other driver, the command completes
1540 * with a busy return value and the timeout field indicates the maximum
1541 * time the current owner of the resource has to free it.
1543 if (!status || hw->adminq.sq_last_status == ICE_AQ_RC_EBUSY)
1544 *timeout = LE32_TO_CPU(cmd_resp->timeout);
1550 * ice_aq_release_res
1551 * @hw: pointer to the HW struct
1553 * @sdp_number: resource number
1554 * @cd: pointer to command details structure or NULL
1556 * release common resource using the admin queue commands (0x0009)
1558 static enum ice_status
1559 ice_aq_release_res(struct ice_hw *hw, enum ice_aq_res_ids res, u8 sdp_number,
1560 struct ice_sq_cd *cd)
1562 struct ice_aqc_req_res *cmd;
1563 struct ice_aq_desc desc;
1565 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
1567 cmd = &desc.params.res_owner;
1569 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_release_res);
1571 cmd->res_id = CPU_TO_LE16(res);
1572 cmd->res_number = CPU_TO_LE32(sdp_number);
1574 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
1579 * @hw: pointer to the HW structure
1581 * @access: access type (read or write)
1582 * @timeout: timeout in milliseconds
1584 * This function will attempt to acquire the ownership of a resource.
1587 ice_acquire_res(struct ice_hw *hw, enum ice_aq_res_ids res,
1588 enum ice_aq_res_access_type access, u32 timeout)
1590 #define ICE_RES_POLLING_DELAY_MS 10
1591 u32 delay = ICE_RES_POLLING_DELAY_MS;
1592 u32 time_left = timeout;
1593 enum ice_status status;
1595 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
1597 status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL);
1599 /* A return code of ICE_ERR_AQ_NO_WORK means that another driver has
1600 * previously acquired the resource and performed any necessary updates;
1601 * in this case the caller does not obtain the resource and has no
1602 * further work to do.
1604 if (status == ICE_ERR_AQ_NO_WORK)
1605 goto ice_acquire_res_exit;
1608 ice_debug(hw, ICE_DBG_RES,
1609 "resource %d acquire type %d failed.\n", res, access);
1611 /* If necessary, poll until the current lock owner timeouts */
1612 timeout = time_left;
1613 while (status && timeout && time_left) {
1614 ice_msec_delay(delay, true);
1615 timeout = (timeout > delay) ? timeout - delay : 0;
1616 status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL);
1618 if (status == ICE_ERR_AQ_NO_WORK)
1619 /* lock free, but no work to do */
1626 if (status && status != ICE_ERR_AQ_NO_WORK)
1627 ice_debug(hw, ICE_DBG_RES, "resource acquire timed out.\n");
1629 ice_acquire_res_exit:
1630 if (status == ICE_ERR_AQ_NO_WORK) {
1631 if (access == ICE_RES_WRITE)
1632 ice_debug(hw, ICE_DBG_RES,
1633 "resource indicates no work to do.\n");
1635 ice_debug(hw, ICE_DBG_RES,
1636 "Warning: ICE_ERR_AQ_NO_WORK not expected\n");
1643 * @hw: pointer to the HW structure
1646 * This function will release a resource using the proper Admin Command.
1648 void ice_release_res(struct ice_hw *hw, enum ice_aq_res_ids res)
1650 enum ice_status status;
1651 u32 total_delay = 0;
1653 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
1655 status = ice_aq_release_res(hw, res, 0, NULL);
1657 /* there are some rare cases when trying to release the resource
1658 * results in an admin queue timeout, so handle them correctly
1660 while ((status == ICE_ERR_AQ_TIMEOUT) &&
1661 (total_delay < hw->adminq.sq_cmd_timeout)) {
1662 ice_msec_delay(1, true);
1663 status = ice_aq_release_res(hw, res, 0, NULL);
1669 * ice_aq_alloc_free_res - command to allocate/free resources
1670 * @hw: pointer to the HW struct
1671 * @num_entries: number of resource entries in buffer
1672 * @buf: Indirect buffer to hold data parameters and response
1673 * @buf_size: size of buffer for indirect commands
1674 * @opc: pass in the command opcode
1675 * @cd: pointer to command details structure or NULL
1677 * Helper function to allocate/free resources using the admin queue commands
1680 ice_aq_alloc_free_res(struct ice_hw *hw, u16 num_entries,
1681 struct ice_aqc_alloc_free_res_elem *buf, u16 buf_size,
1682 enum ice_adminq_opc opc, struct ice_sq_cd *cd)
1684 struct ice_aqc_alloc_free_res_cmd *cmd;
1685 struct ice_aq_desc desc;
1687 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
1689 cmd = &desc.params.sw_res_ctrl;
1692 return ICE_ERR_PARAM;
1694 if (buf_size < (num_entries * sizeof(buf->elem[0])))
1695 return ICE_ERR_PARAM;
1697 ice_fill_dflt_direct_cmd_desc(&desc, opc);
1699 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
1701 cmd->num_entries = CPU_TO_LE16(num_entries);
1703 return ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);
1707 * ice_alloc_hw_res - allocate resource
1708 * @hw: pointer to the HW struct
1709 * @type: type of resource
1710 * @num: number of resources to allocate
1711 * @btm: allocate from bottom
1712 * @res: pointer to array that will receive the resources
1715 ice_alloc_hw_res(struct ice_hw *hw, u16 type, u16 num, bool btm, u16 *res)
1717 struct ice_aqc_alloc_free_res_elem *buf;
1718 enum ice_status status;
1721 buf_len = ice_struct_size(buf, elem, num - 1);
1722 buf = (struct ice_aqc_alloc_free_res_elem *)
1723 ice_malloc(hw, buf_len);
1725 return ICE_ERR_NO_MEMORY;
1727 /* Prepare buffer to allocate resource. */
1728 buf->num_elems = CPU_TO_LE16(num);
1729 buf->res_type = CPU_TO_LE16(type | ICE_AQC_RES_TYPE_FLAG_DEDICATED |
1730 ICE_AQC_RES_TYPE_FLAG_IGNORE_INDEX);
1732 buf->res_type |= CPU_TO_LE16(ICE_AQC_RES_TYPE_FLAG_SCAN_BOTTOM);
1734 status = ice_aq_alloc_free_res(hw, 1, buf, buf_len,
1735 ice_aqc_opc_alloc_res, NULL);
1737 goto ice_alloc_res_exit;
1739 ice_memcpy(res, buf->elem, sizeof(buf->elem) * num,
1740 ICE_NONDMA_TO_NONDMA);
1748 * ice_free_hw_res - free allocated HW resource
1749 * @hw: pointer to the HW struct
1750 * @type: type of resource to free
1751 * @num: number of resources
1752 * @res: pointer to array that contains the resources to free
1754 enum ice_status ice_free_hw_res(struct ice_hw *hw, u16 type, u16 num, u16 *res)
1756 struct ice_aqc_alloc_free_res_elem *buf;
1757 enum ice_status status;
1760 buf_len = ice_struct_size(buf, elem, num - 1);
1761 buf = (struct ice_aqc_alloc_free_res_elem *)ice_malloc(hw, buf_len);
1763 return ICE_ERR_NO_MEMORY;
1765 /* Prepare buffer to free resource. */
1766 buf->num_elems = CPU_TO_LE16(num);
1767 buf->res_type = CPU_TO_LE16(type);
1768 ice_memcpy(buf->elem, res, sizeof(buf->elem) * num,
1769 ICE_NONDMA_TO_NONDMA);
1771 status = ice_aq_alloc_free_res(hw, num, buf, buf_len,
1772 ice_aqc_opc_free_res, NULL);
1774 ice_debug(hw, ICE_DBG_SW, "CQ CMD Buffer:\n");
1781 * ice_get_num_per_func - determine number of resources per PF
1782 * @hw: pointer to the HW structure
1783 * @max: value to be evenly split between each PF
1785 * Determine the number of valid functions by going through the bitmap returned
1786 * from parsing capabilities and use this to calculate the number of resources
1787 * per PF based on the max value passed in.
1789 static u32 ice_get_num_per_func(struct ice_hw *hw, u32 max)
1793 #define ICE_CAPS_VALID_FUNCS_M 0xFF
1794 funcs = ice_hweight8(hw->dev_caps.common_cap.valid_functions &
1795 ICE_CAPS_VALID_FUNCS_M);
1804 * ice_parse_caps - parse function/device capabilities
1805 * @hw: pointer to the HW struct
1806 * @buf: pointer to a buffer containing function/device capability records
1807 * @cap_count: number of capability records in the list
1808 * @opc: type of capabilities list to parse
1810 * Helper function to parse function(0x000a)/device(0x000b) capabilities list.
1813 ice_parse_caps(struct ice_hw *hw, void *buf, u32 cap_count,
1814 enum ice_adminq_opc opc)
1816 struct ice_aqc_list_caps_elem *cap_resp;
1817 struct ice_hw_func_caps *func_p = NULL;
1818 struct ice_hw_dev_caps *dev_p = NULL;
1819 struct ice_hw_common_caps *caps;
1826 cap_resp = (struct ice_aqc_list_caps_elem *)buf;
1828 if (opc == ice_aqc_opc_list_dev_caps) {
1829 dev_p = &hw->dev_caps;
1830 caps = &dev_p->common_cap;
1832 } else if (opc == ice_aqc_opc_list_func_caps) {
1833 func_p = &hw->func_caps;
1834 caps = &func_p->common_cap;
1835 prefix = "func cap";
1837 ice_debug(hw, ICE_DBG_INIT, "wrong opcode\n");
1841 for (i = 0; caps && i < cap_count; i++, cap_resp++) {
1842 u32 logical_id = LE32_TO_CPU(cap_resp->logical_id);
1843 u32 phys_id = LE32_TO_CPU(cap_resp->phys_id);
1844 u32 number = LE32_TO_CPU(cap_resp->number);
1845 u16 cap = LE16_TO_CPU(cap_resp->cap);
1848 case ICE_AQC_CAPS_VALID_FUNCTIONS:
1849 caps->valid_functions = number;
1850 ice_debug(hw, ICE_DBG_INIT,
1851 "%s: valid_functions (bitmap) = %d\n", prefix,
1852 caps->valid_functions);
1854 /* store func count for resource management purposes */
1856 dev_p->num_funcs = ice_hweight32(number);
1858 case ICE_AQC_CAPS_VSI:
1860 dev_p->num_vsi_allocd_to_host = number;
1861 ice_debug(hw, ICE_DBG_INIT,
1862 "%s: num_vsi_allocd_to_host = %d\n",
1864 dev_p->num_vsi_allocd_to_host);
1865 } else if (func_p) {
1866 func_p->guar_num_vsi =
1867 ice_get_num_per_func(hw, ICE_MAX_VSI);
1868 ice_debug(hw, ICE_DBG_INIT,
1869 "%s: guar_num_vsi (fw) = %d\n",
1871 ice_debug(hw, ICE_DBG_INIT,
1872 "%s: guar_num_vsi = %d\n",
1873 prefix, func_p->guar_num_vsi);
1876 case ICE_AQC_CAPS_DCB:
1877 caps->dcb = (number == 1);
1878 caps->active_tc_bitmap = logical_id;
1879 caps->maxtc = phys_id;
1880 ice_debug(hw, ICE_DBG_INIT,
1881 "%s: dcb = %d\n", prefix, caps->dcb);
1882 ice_debug(hw, ICE_DBG_INIT,
1883 "%s: active_tc_bitmap = %d\n", prefix,
1884 caps->active_tc_bitmap);
1885 ice_debug(hw, ICE_DBG_INIT,
1886 "%s: maxtc = %d\n", prefix, caps->maxtc);
1888 case ICE_AQC_CAPS_RSS:
1889 caps->rss_table_size = number;
1890 caps->rss_table_entry_width = logical_id;
1891 ice_debug(hw, ICE_DBG_INIT,
1892 "%s: rss_table_size = %d\n", prefix,
1893 caps->rss_table_size);
1894 ice_debug(hw, ICE_DBG_INIT,
1895 "%s: rss_table_entry_width = %d\n", prefix,
1896 caps->rss_table_entry_width);
1898 case ICE_AQC_CAPS_RXQS:
1899 caps->num_rxq = number;
1900 caps->rxq_first_id = phys_id;
1901 ice_debug(hw, ICE_DBG_INIT,
1902 "%s: num_rxq = %d\n", prefix,
1904 ice_debug(hw, ICE_DBG_INIT,
1905 "%s: rxq_first_id = %d\n", prefix,
1906 caps->rxq_first_id);
1908 case ICE_AQC_CAPS_TXQS:
1909 caps->num_txq = number;
1910 caps->txq_first_id = phys_id;
1911 ice_debug(hw, ICE_DBG_INIT,
1912 "%s: num_txq = %d\n", prefix,
1914 ice_debug(hw, ICE_DBG_INIT,
1915 "%s: txq_first_id = %d\n", prefix,
1916 caps->txq_first_id);
1918 case ICE_AQC_CAPS_MSIX:
1919 caps->num_msix_vectors = number;
1920 caps->msix_vector_first_id = phys_id;
1921 ice_debug(hw, ICE_DBG_INIT,
1922 "%s: num_msix_vectors = %d\n", prefix,
1923 caps->num_msix_vectors);
1924 ice_debug(hw, ICE_DBG_INIT,
1925 "%s: msix_vector_first_id = %d\n", prefix,
1926 caps->msix_vector_first_id);
1928 case ICE_AQC_CAPS_FD:
1930 dev_p->num_flow_director_fltr = number;
1931 ice_debug(hw, ICE_DBG_INIT,
1932 "%s: num_flow_director_fltr = %d\n",
1934 dev_p->num_flow_director_fltr);
1939 if (hw->dcf_enabled)
1941 reg_val = rd32(hw, GLQF_FD_SIZE);
1942 val = (reg_val & GLQF_FD_SIZE_FD_GSIZE_M) >>
1943 GLQF_FD_SIZE_FD_GSIZE_S;
1944 func_p->fd_fltr_guar =
1945 ice_get_num_per_func(hw, val);
1946 val = (reg_val & GLQF_FD_SIZE_FD_BSIZE_M) >>
1947 GLQF_FD_SIZE_FD_BSIZE_S;
1948 func_p->fd_fltr_best_effort = val;
1949 ice_debug(hw, ICE_DBG_INIT,
1950 "%s: fd_fltr_guar = %d\n",
1951 prefix, func_p->fd_fltr_guar);
1952 ice_debug(hw, ICE_DBG_INIT,
1953 "%s: fd_fltr_best_effort = %d\n",
1954 prefix, func_p->fd_fltr_best_effort);
1957 case ICE_AQC_CAPS_MAX_MTU:
1958 caps->max_mtu = number;
1959 ice_debug(hw, ICE_DBG_INIT, "%s: max_mtu = %d\n",
1960 prefix, caps->max_mtu);
1963 ice_debug(hw, ICE_DBG_INIT,
1964 "%s: unknown capability[%d]: 0x%x\n", prefix,
1970 /* Re-calculate capabilities that are dependent on the number of
1971 * physical ports; i.e. some features are not supported or function
1972 * differently on devices with more than 4 ports.
1974 if (hw->dev_caps.num_funcs > 4) {
1975 /* Max 4 TCs per port */
1977 ice_debug(hw, ICE_DBG_INIT,
1978 "%s: maxtc = %d (based on #ports)\n", prefix,
1984 * ice_aq_discover_caps - query function/device capabilities
1985 * @hw: pointer to the HW struct
1986 * @buf: a virtual buffer to hold the capabilities
1987 * @buf_size: Size of the virtual buffer
1988 * @cap_count: cap count needed if AQ err==ENOMEM
1989 * @opc: capabilities type to discover - pass in the command opcode
1990 * @cd: pointer to command details structure or NULL
1992 * Get the function(0x000a)/device(0x000b) capabilities description from
1995 static enum ice_status
1996 ice_aq_discover_caps(struct ice_hw *hw, void *buf, u16 buf_size, u32 *cap_count,
1997 enum ice_adminq_opc opc, struct ice_sq_cd *cd)
1999 struct ice_aqc_list_caps *cmd;
2000 struct ice_aq_desc desc;
2001 enum ice_status status;
2003 cmd = &desc.params.get_cap;
2005 if (opc != ice_aqc_opc_list_func_caps &&
2006 opc != ice_aqc_opc_list_dev_caps)
2007 return ICE_ERR_PARAM;
2009 ice_fill_dflt_direct_cmd_desc(&desc, opc);
2011 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);
2013 ice_parse_caps(hw, buf, LE32_TO_CPU(cmd->count), opc);
2014 else if (hw->adminq.sq_last_status == ICE_AQ_RC_ENOMEM)
2015 *cap_count = LE32_TO_CPU(cmd->count);
2020 * ice_discover_caps - get info about the HW
2021 * @hw: pointer to the hardware structure
2022 * @opc: capabilities type to discover - pass in the command opcode
2024 static enum ice_status
2025 ice_discover_caps(struct ice_hw *hw, enum ice_adminq_opc opc)
2027 enum ice_status status;
2032 /* The driver doesn't know how many capabilities the device will return
2033 * so the buffer size required isn't known ahead of time. The driver
2034 * starts with cbuf_len and if this turns out to be insufficient, the
2035 * device returns ICE_AQ_RC_ENOMEM and also the cap_count it needs.
2036 * The driver then allocates the buffer based on the count and retries
2037 * the operation. So it follows that the retry count is 2.
2039 #define ICE_GET_CAP_BUF_COUNT 40
2040 #define ICE_GET_CAP_RETRY_COUNT 2
2042 cap_count = ICE_GET_CAP_BUF_COUNT;
2043 retries = ICE_GET_CAP_RETRY_COUNT;
2048 cbuf_len = (u16)(cap_count *
2049 sizeof(struct ice_aqc_list_caps_elem));
2050 cbuf = ice_malloc(hw, cbuf_len);
2052 return ICE_ERR_NO_MEMORY;
2054 status = ice_aq_discover_caps(hw, cbuf, cbuf_len, &cap_count,
2058 if (!status || hw->adminq.sq_last_status != ICE_AQ_RC_ENOMEM)
2061 /* If ENOMEM is returned, try again with bigger buffer */
2062 } while (--retries);
2068 * ice_set_safe_mode_caps - Override dev/func capabilities when in safe mode
2069 * @hw: pointer to the hardware structure
2071 void ice_set_safe_mode_caps(struct ice_hw *hw)
2073 struct ice_hw_func_caps *func_caps = &hw->func_caps;
2074 struct ice_hw_dev_caps *dev_caps = &hw->dev_caps;
2075 u32 valid_func, rxq_first_id, txq_first_id;
2076 u32 msix_vector_first_id, max_mtu;
2079 /* cache some func_caps values that should be restored after memset */
2080 valid_func = func_caps->common_cap.valid_functions;
2081 txq_first_id = func_caps->common_cap.txq_first_id;
2082 rxq_first_id = func_caps->common_cap.rxq_first_id;
2083 msix_vector_first_id = func_caps->common_cap.msix_vector_first_id;
2084 max_mtu = func_caps->common_cap.max_mtu;
2086 /* unset func capabilities */
2087 memset(func_caps, 0, sizeof(*func_caps));
2089 /* restore cached values */
2090 func_caps->common_cap.valid_functions = valid_func;
2091 func_caps->common_cap.txq_first_id = txq_first_id;
2092 func_caps->common_cap.rxq_first_id = rxq_first_id;
2093 func_caps->common_cap.msix_vector_first_id = msix_vector_first_id;
2094 func_caps->common_cap.max_mtu = max_mtu;
2096 /* one Tx and one Rx queue in safe mode */
2097 func_caps->common_cap.num_rxq = 1;
2098 func_caps->common_cap.num_txq = 1;
2100 /* two MSIX vectors, one for traffic and one for misc causes */
2101 func_caps->common_cap.num_msix_vectors = 2;
2102 func_caps->guar_num_vsi = 1;
2104 /* cache some dev_caps values that should be restored after memset */
2105 valid_func = dev_caps->common_cap.valid_functions;
2106 txq_first_id = dev_caps->common_cap.txq_first_id;
2107 rxq_first_id = dev_caps->common_cap.rxq_first_id;
2108 msix_vector_first_id = dev_caps->common_cap.msix_vector_first_id;
2109 max_mtu = dev_caps->common_cap.max_mtu;
2110 num_funcs = dev_caps->num_funcs;
2112 /* unset dev capabilities */
2113 memset(dev_caps, 0, sizeof(*dev_caps));
2115 /* restore cached values */
2116 dev_caps->common_cap.valid_functions = valid_func;
2117 dev_caps->common_cap.txq_first_id = txq_first_id;
2118 dev_caps->common_cap.rxq_first_id = rxq_first_id;
2119 dev_caps->common_cap.msix_vector_first_id = msix_vector_first_id;
2120 dev_caps->common_cap.max_mtu = max_mtu;
2121 dev_caps->num_funcs = num_funcs;
2123 /* one Tx and one Rx queue per function in safe mode */
2124 dev_caps->common_cap.num_rxq = num_funcs;
2125 dev_caps->common_cap.num_txq = num_funcs;
2127 /* two MSIX vectors per function */
2128 dev_caps->common_cap.num_msix_vectors = 2 * num_funcs;
2132 * ice_get_caps - get info about the HW
2133 * @hw: pointer to the hardware structure
2135 enum ice_status ice_get_caps(struct ice_hw *hw)
2137 enum ice_status status;
2139 status = ice_discover_caps(hw, ice_aqc_opc_list_dev_caps);
2141 status = ice_discover_caps(hw, ice_aqc_opc_list_func_caps);
2147 * ice_aq_manage_mac_write - manage MAC address write command
2148 * @hw: pointer to the HW struct
2149 * @mac_addr: MAC address to be written as LAA/LAA+WoL/Port address
2150 * @flags: flags to control write behavior
2151 * @cd: pointer to command details structure or NULL
2153 * This function is used to write MAC address to the NVM (0x0108).
2156 ice_aq_manage_mac_write(struct ice_hw *hw, const u8 *mac_addr, u8 flags,
2157 struct ice_sq_cd *cd)
2159 struct ice_aqc_manage_mac_write *cmd;
2160 struct ice_aq_desc desc;
2162 cmd = &desc.params.mac_write;
2163 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_write);
2166 ice_memcpy(cmd->mac_addr, mac_addr, ETH_ALEN, ICE_NONDMA_TO_DMA);
2168 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
2172 * ice_aq_clear_pxe_mode
2173 * @hw: pointer to the HW struct
2175 * Tell the firmware that the driver is taking over from PXE (0x0110).
2177 static enum ice_status ice_aq_clear_pxe_mode(struct ice_hw *hw)
2179 struct ice_aq_desc desc;
2181 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pxe_mode);
2182 desc.params.clear_pxe.rx_cnt = ICE_AQC_CLEAR_PXE_RX_CNT;
2184 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
2188 * ice_clear_pxe_mode - clear pxe operations mode
2189 * @hw: pointer to the HW struct
2191 * Make sure all PXE mode settings are cleared, including things
2192 * like descriptor fetch/write-back mode.
2194 void ice_clear_pxe_mode(struct ice_hw *hw)
2196 if (ice_check_sq_alive(hw, &hw->adminq))
2197 ice_aq_clear_pxe_mode(hw);
2201 * ice_get_link_speed_based_on_phy_type - returns link speed
2202 * @phy_type_low: lower part of phy_type
2203 * @phy_type_high: higher part of phy_type
2205 * This helper function will convert an entry in PHY type structure
2206 * [phy_type_low, phy_type_high] to its corresponding link speed.
2207 * Note: In the structure of [phy_type_low, phy_type_high], there should
2208 * be one bit set, as this function will convert one PHY type to its
2210 * If no bit gets set, ICE_LINK_SPEED_UNKNOWN will be returned
2211 * If more than one bit gets set, ICE_LINK_SPEED_UNKNOWN will be returned
2214 ice_get_link_speed_based_on_phy_type(u64 phy_type_low, u64 phy_type_high)
2216 u16 speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN;
2217 u16 speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN;
2219 switch (phy_type_low) {
2220 case ICE_PHY_TYPE_LOW_100BASE_TX:
2221 case ICE_PHY_TYPE_LOW_100M_SGMII:
2222 speed_phy_type_low = ICE_AQ_LINK_SPEED_100MB;
2224 case ICE_PHY_TYPE_LOW_1000BASE_T:
2225 case ICE_PHY_TYPE_LOW_1000BASE_SX:
2226 case ICE_PHY_TYPE_LOW_1000BASE_LX:
2227 case ICE_PHY_TYPE_LOW_1000BASE_KX:
2228 case ICE_PHY_TYPE_LOW_1G_SGMII:
2229 speed_phy_type_low = ICE_AQ_LINK_SPEED_1000MB;
2231 case ICE_PHY_TYPE_LOW_2500BASE_T:
2232 case ICE_PHY_TYPE_LOW_2500BASE_X:
2233 case ICE_PHY_TYPE_LOW_2500BASE_KX:
2234 speed_phy_type_low = ICE_AQ_LINK_SPEED_2500MB;
2236 case ICE_PHY_TYPE_LOW_5GBASE_T:
2237 case ICE_PHY_TYPE_LOW_5GBASE_KR:
2238 speed_phy_type_low = ICE_AQ_LINK_SPEED_5GB;
2240 case ICE_PHY_TYPE_LOW_10GBASE_T:
2241 case ICE_PHY_TYPE_LOW_10G_SFI_DA:
2242 case ICE_PHY_TYPE_LOW_10GBASE_SR:
2243 case ICE_PHY_TYPE_LOW_10GBASE_LR:
2244 case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1:
2245 case ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC:
2246 case ICE_PHY_TYPE_LOW_10G_SFI_C2C:
2247 speed_phy_type_low = ICE_AQ_LINK_SPEED_10GB;
2249 case ICE_PHY_TYPE_LOW_25GBASE_T:
2250 case ICE_PHY_TYPE_LOW_25GBASE_CR:
2251 case ICE_PHY_TYPE_LOW_25GBASE_CR_S:
2252 case ICE_PHY_TYPE_LOW_25GBASE_CR1:
2253 case ICE_PHY_TYPE_LOW_25GBASE_SR:
2254 case ICE_PHY_TYPE_LOW_25GBASE_LR:
2255 case ICE_PHY_TYPE_LOW_25GBASE_KR:
2256 case ICE_PHY_TYPE_LOW_25GBASE_KR_S:
2257 case ICE_PHY_TYPE_LOW_25GBASE_KR1:
2258 case ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC:
2259 case ICE_PHY_TYPE_LOW_25G_AUI_C2C:
2260 speed_phy_type_low = ICE_AQ_LINK_SPEED_25GB;
2262 case ICE_PHY_TYPE_LOW_40GBASE_CR4:
2263 case ICE_PHY_TYPE_LOW_40GBASE_SR4:
2264 case ICE_PHY_TYPE_LOW_40GBASE_LR4:
2265 case ICE_PHY_TYPE_LOW_40GBASE_KR4:
2266 case ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC:
2267 case ICE_PHY_TYPE_LOW_40G_XLAUI:
2268 speed_phy_type_low = ICE_AQ_LINK_SPEED_40GB;
2270 case ICE_PHY_TYPE_LOW_50GBASE_CR2:
2271 case ICE_PHY_TYPE_LOW_50GBASE_SR2:
2272 case ICE_PHY_TYPE_LOW_50GBASE_LR2:
2273 case ICE_PHY_TYPE_LOW_50GBASE_KR2:
2274 case ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC:
2275 case ICE_PHY_TYPE_LOW_50G_LAUI2:
2276 case ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC:
2277 case ICE_PHY_TYPE_LOW_50G_AUI2:
2278 case ICE_PHY_TYPE_LOW_50GBASE_CP:
2279 case ICE_PHY_TYPE_LOW_50GBASE_SR:
2280 case ICE_PHY_TYPE_LOW_50GBASE_FR:
2281 case ICE_PHY_TYPE_LOW_50GBASE_LR:
2282 case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4:
2283 case ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC:
2284 case ICE_PHY_TYPE_LOW_50G_AUI1:
2285 speed_phy_type_low = ICE_AQ_LINK_SPEED_50GB;
2287 case ICE_PHY_TYPE_LOW_100GBASE_CR4:
2288 case ICE_PHY_TYPE_LOW_100GBASE_SR4:
2289 case ICE_PHY_TYPE_LOW_100GBASE_LR4:
2290 case ICE_PHY_TYPE_LOW_100GBASE_KR4:
2291 case ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC:
2292 case ICE_PHY_TYPE_LOW_100G_CAUI4:
2293 case ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC:
2294 case ICE_PHY_TYPE_LOW_100G_AUI4:
2295 case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4:
2296 case ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4:
2297 case ICE_PHY_TYPE_LOW_100GBASE_CP2:
2298 case ICE_PHY_TYPE_LOW_100GBASE_SR2:
2299 case ICE_PHY_TYPE_LOW_100GBASE_DR:
2300 speed_phy_type_low = ICE_AQ_LINK_SPEED_100GB;
2303 speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN;
2307 switch (phy_type_high) {
2308 case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4:
2309 case ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC:
2310 case ICE_PHY_TYPE_HIGH_100G_CAUI2:
2311 case ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC:
2312 case ICE_PHY_TYPE_HIGH_100G_AUI2:
2313 speed_phy_type_high = ICE_AQ_LINK_SPEED_100GB;
2316 speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN;
2320 if (speed_phy_type_low == ICE_AQ_LINK_SPEED_UNKNOWN &&
2321 speed_phy_type_high == ICE_AQ_LINK_SPEED_UNKNOWN)
2322 return ICE_AQ_LINK_SPEED_UNKNOWN;
2323 else if (speed_phy_type_low != ICE_AQ_LINK_SPEED_UNKNOWN &&
2324 speed_phy_type_high != ICE_AQ_LINK_SPEED_UNKNOWN)
2325 return ICE_AQ_LINK_SPEED_UNKNOWN;
2326 else if (speed_phy_type_low != ICE_AQ_LINK_SPEED_UNKNOWN &&
2327 speed_phy_type_high == ICE_AQ_LINK_SPEED_UNKNOWN)
2328 return speed_phy_type_low;
2330 return speed_phy_type_high;
2334 * ice_update_phy_type
2335 * @phy_type_low: pointer to the lower part of phy_type
2336 * @phy_type_high: pointer to the higher part of phy_type
2337 * @link_speeds_bitmap: targeted link speeds bitmap
2339 * Note: For the link_speeds_bitmap structure, you can check it at
2340 * [ice_aqc_get_link_status->link_speed]. Caller can pass in
2341 * link_speeds_bitmap include multiple speeds.
2343 * Each entry in this [phy_type_low, phy_type_high] structure will
2344 * present a certain link speed. This helper function will turn on bits
2345 * in [phy_type_low, phy_type_high] structure based on the value of
2346 * link_speeds_bitmap input parameter.
2349 ice_update_phy_type(u64 *phy_type_low, u64 *phy_type_high,
2350 u16 link_speeds_bitmap)
2357 /* We first check with low part of phy_type */
2358 for (index = 0; index <= ICE_PHY_TYPE_LOW_MAX_INDEX; index++) {
2359 pt_low = BIT_ULL(index);
2360 speed = ice_get_link_speed_based_on_phy_type(pt_low, 0);
2362 if (link_speeds_bitmap & speed)
2363 *phy_type_low |= BIT_ULL(index);
2366 /* We then check with high part of phy_type */
2367 for (index = 0; index <= ICE_PHY_TYPE_HIGH_MAX_INDEX; index++) {
2368 pt_high = BIT_ULL(index);
2369 speed = ice_get_link_speed_based_on_phy_type(0, pt_high);
2371 if (link_speeds_bitmap & speed)
2372 *phy_type_high |= BIT_ULL(index);
2377 * ice_aq_set_phy_cfg
2378 * @hw: pointer to the HW struct
2379 * @pi: port info structure of the interested logical port
2380 * @cfg: structure with PHY configuration data to be set
2381 * @cd: pointer to command details structure or NULL
2383 * Set the various PHY configuration parameters supported on the Port.
2384 * One or more of the Set PHY config parameters may be ignored in an MFP
2385 * mode as the PF may not have the privilege to set some of the PHY Config
2386 * parameters. This status will be indicated by the command response (0x0601).
2389 ice_aq_set_phy_cfg(struct ice_hw *hw, struct ice_port_info *pi,
2390 struct ice_aqc_set_phy_cfg_data *cfg, struct ice_sq_cd *cd)
2392 struct ice_aq_desc desc;
2393 enum ice_status status;
2396 return ICE_ERR_PARAM;
2398 /* Ensure that only valid bits of cfg->caps can be turned on. */
2399 if (cfg->caps & ~ICE_AQ_PHY_ENA_VALID_MASK) {
2400 ice_debug(hw, ICE_DBG_PHY,
2401 "Invalid bit is set in ice_aqc_set_phy_cfg_data->caps : 0x%x\n",
2404 cfg->caps &= ICE_AQ_PHY_ENA_VALID_MASK;
2407 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_phy_cfg);
2408 desc.params.set_phy.lport_num = pi->lport;
2409 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
2411 ice_debug(hw, ICE_DBG_LINK, "set phy cfg\n");
2412 ice_debug(hw, ICE_DBG_LINK, " phy_type_low = 0x%llx\n",
2413 (unsigned long long)LE64_TO_CPU(cfg->phy_type_low));
2414 ice_debug(hw, ICE_DBG_LINK, " phy_type_high = 0x%llx\n",
2415 (unsigned long long)LE64_TO_CPU(cfg->phy_type_high));
2416 ice_debug(hw, ICE_DBG_LINK, " caps = 0x%x\n", cfg->caps);
2417 ice_debug(hw, ICE_DBG_LINK, " low_power_ctrl_an = 0x%x\n",
2418 cfg->low_power_ctrl_an);
2419 ice_debug(hw, ICE_DBG_LINK, " eee_cap = 0x%x\n", cfg->eee_cap);
2420 ice_debug(hw, ICE_DBG_LINK, " eeer_value = 0x%x\n", cfg->eeer_value);
2421 ice_debug(hw, ICE_DBG_LINK, " link_fec_opt = 0x%x\n",
2424 status = ice_aq_send_cmd(hw, &desc, cfg, sizeof(*cfg), cd);
2426 if (hw->adminq.sq_last_status == ICE_AQ_RC_EMODE)
2427 status = ICE_SUCCESS;
2430 pi->phy.curr_user_phy_cfg = *cfg;
2436 * ice_update_link_info - update status of the HW network link
2437 * @pi: port info structure of the interested logical port
2439 enum ice_status ice_update_link_info(struct ice_port_info *pi)
2441 struct ice_link_status *li;
2442 enum ice_status status;
2445 return ICE_ERR_PARAM;
2447 li = &pi->phy.link_info;
2449 status = ice_aq_get_link_info(pi, true, NULL, NULL);
2453 if (li->link_info & ICE_AQ_MEDIA_AVAILABLE) {
2454 struct ice_aqc_get_phy_caps_data *pcaps;
2458 pcaps = (struct ice_aqc_get_phy_caps_data *)
2459 ice_malloc(hw, sizeof(*pcaps));
2461 return ICE_ERR_NO_MEMORY;
2463 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_TOPO_CAP,
2465 if (status == ICE_SUCCESS)
2466 ice_memcpy(li->module_type, &pcaps->module_type,
2467 sizeof(li->module_type),
2468 ICE_NONDMA_TO_NONDMA);
2470 ice_free(hw, pcaps);
2477 * ice_cache_phy_user_req
2478 * @pi: port information structure
2479 * @cache_data: PHY logging data
2480 * @cache_mode: PHY logging mode
2482 * Log the user request on (FC, FEC, SPEED) for later user.
2485 ice_cache_phy_user_req(struct ice_port_info *pi,
2486 struct ice_phy_cache_mode_data cache_data,
2487 enum ice_phy_cache_mode cache_mode)
2492 switch (cache_mode) {
2494 pi->phy.curr_user_fc_req = cache_data.data.curr_user_fc_req;
2496 case ICE_SPEED_MODE:
2497 pi->phy.curr_user_speed_req =
2498 cache_data.data.curr_user_speed_req;
2501 pi->phy.curr_user_fec_req = cache_data.data.curr_user_fec_req;
2509 * ice_caps_to_fc_mode
2510 * @caps: PHY capabilities
2512 * Convert PHY FC capabilities to ice FC mode
2514 enum ice_fc_mode ice_caps_to_fc_mode(u8 caps)
2516 if (caps & ICE_AQC_PHY_EN_TX_LINK_PAUSE &&
2517 caps & ICE_AQC_PHY_EN_RX_LINK_PAUSE)
2520 if (caps & ICE_AQC_PHY_EN_TX_LINK_PAUSE)
2521 return ICE_FC_TX_PAUSE;
2523 if (caps & ICE_AQC_PHY_EN_RX_LINK_PAUSE)
2524 return ICE_FC_RX_PAUSE;
2530 * ice_caps_to_fec_mode
2531 * @caps: PHY capabilities
2532 * @fec_options: Link FEC options
2534 * Convert PHY FEC capabilities to ice FEC mode
2536 enum ice_fec_mode ice_caps_to_fec_mode(u8 caps, u8 fec_options)
2538 if (caps & ICE_AQC_PHY_EN_AUTO_FEC)
2539 return ICE_FEC_AUTO;
2541 if (fec_options & (ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN |
2542 ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ |
2543 ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN |
2544 ICE_AQC_PHY_FEC_25G_KR_REQ))
2545 return ICE_FEC_BASER;
2547 if (fec_options & (ICE_AQC_PHY_FEC_25G_RS_528_REQ |
2548 ICE_AQC_PHY_FEC_25G_RS_544_REQ |
2549 ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN))
2552 return ICE_FEC_NONE;
2555 static enum ice_status
2556 ice_cfg_phy_fc(struct ice_port_info *pi, struct ice_aqc_set_phy_cfg_data *cfg,
2557 enum ice_fc_mode req_mode)
2559 struct ice_aqc_get_phy_caps_data *pcaps = NULL;
2560 struct ice_phy_cache_mode_data cache_data;
2561 enum ice_status status = ICE_SUCCESS;
2562 u8 pause_mask = 0x0;
2565 return ICE_ERR_BAD_PTR;
2567 pcaps = (struct ice_aqc_get_phy_caps_data *)
2568 ice_malloc(pi->hw, sizeof(*pcaps));
2570 return ICE_ERR_NO_MEMORY;
2572 /* Cache user FC request */
2573 cache_data.data.curr_user_fc_req = req_mode;
2574 ice_cache_phy_user_req(pi, cache_data, ICE_FC_MODE);
2578 /* Query the value of FC that both the NIC and attached media
2581 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_TOPO_CAP,
2586 pause_mask |= pcaps->caps & ICE_AQC_PHY_EN_TX_LINK_PAUSE;
2587 pause_mask |= pcaps->caps & ICE_AQC_PHY_EN_RX_LINK_PAUSE;
2590 pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE;
2591 pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE;
2593 case ICE_FC_RX_PAUSE:
2594 pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE;
2596 case ICE_FC_TX_PAUSE:
2597 pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE;
2603 /* clear the old pause settings */
2604 cfg->caps &= ~(ICE_AQC_PHY_EN_TX_LINK_PAUSE |
2605 ICE_AQC_PHY_EN_RX_LINK_PAUSE);
2607 /* set the new capabilities */
2608 cfg->caps |= pause_mask;
2611 ice_free(pi->hw, pcaps);
2617 * @pi: port information structure
2618 * @aq_failures: pointer to status code, specific to ice_set_fc routine
2619 * @ena_auto_link_update: enable automatic link update
2621 * Set the requested flow control mode.
2624 ice_set_fc(struct ice_port_info *pi, u8 *aq_failures, bool ena_auto_link_update)
2626 struct ice_aqc_set_phy_cfg_data cfg = { 0 };
2627 struct ice_aqc_get_phy_caps_data *pcaps;
2628 enum ice_status status;
2631 if (!pi || !aq_failures)
2632 return ICE_ERR_BAD_PTR;
2636 pcaps = (struct ice_aqc_get_phy_caps_data *)
2637 ice_malloc(hw, sizeof(*pcaps));
2639 return ICE_ERR_NO_MEMORY;
2641 /* Get the current PHY config */
2642 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_SW_CFG, pcaps,
2645 *aq_failures = ICE_SET_FC_AQ_FAIL_GET;
2649 ice_copy_phy_caps_to_cfg(pi, pcaps, &cfg);
2651 /* Configure the set PHY data */
2652 status = ice_cfg_phy_fc(pi, &cfg, pi->fc.req_mode);
2654 if (status != ICE_ERR_BAD_PTR)
2655 *aq_failures = ICE_SET_FC_AQ_FAIL_GET;
2660 /* If the capabilities have changed, then set the new config */
2661 if (cfg.caps != pcaps->caps) {
2662 int retry_count, retry_max = 10;
2664 /* Auto restart link so settings take effect */
2665 if (ena_auto_link_update)
2666 cfg.caps |= ICE_AQ_PHY_ENA_AUTO_LINK_UPDT;
2668 status = ice_aq_set_phy_cfg(hw, pi, &cfg, NULL);
2670 *aq_failures = ICE_SET_FC_AQ_FAIL_SET;
2674 /* Update the link info
2675 * It sometimes takes a really long time for link to
2676 * come back from the atomic reset. Thus, we wait a
2679 for (retry_count = 0; retry_count < retry_max; retry_count++) {
2680 status = ice_update_link_info(pi);
2682 if (status == ICE_SUCCESS)
2685 ice_msec_delay(100, true);
2689 *aq_failures = ICE_SET_FC_AQ_FAIL_UPDATE;
2693 ice_free(hw, pcaps);
2698 * ice_phy_caps_equals_cfg
2699 * @phy_caps: PHY capabilities
2700 * @phy_cfg: PHY configuration
2702 * Helper function to determine if PHY capabilities matches PHY
2706 ice_phy_caps_equals_cfg(struct ice_aqc_get_phy_caps_data *phy_caps,
2707 struct ice_aqc_set_phy_cfg_data *phy_cfg)
2709 u8 caps_mask, cfg_mask;
2711 if (!phy_caps || !phy_cfg)
2714 /* These bits are not common between capabilities and configuration.
2715 * Do not use them to determine equality.
2717 caps_mask = ICE_AQC_PHY_CAPS_MASK & ~(ICE_AQC_PHY_AN_MODE |
2718 ICE_AQC_PHY_EN_MOD_QUAL);
2719 cfg_mask = ICE_AQ_PHY_ENA_VALID_MASK & ~ICE_AQ_PHY_ENA_AUTO_LINK_UPDT;
2721 if (phy_caps->phy_type_low != phy_cfg->phy_type_low ||
2722 phy_caps->phy_type_high != phy_cfg->phy_type_high ||
2723 ((phy_caps->caps & caps_mask) != (phy_cfg->caps & cfg_mask)) ||
2724 phy_caps->low_power_ctrl_an != phy_cfg->low_power_ctrl_an ||
2725 phy_caps->eee_cap != phy_cfg->eee_cap ||
2726 phy_caps->eeer_value != phy_cfg->eeer_value ||
2727 phy_caps->link_fec_options != phy_cfg->link_fec_opt)
2734 * ice_copy_phy_caps_to_cfg - Copy PHY ability data to configuration data
2735 * @pi: port information structure
2736 * @caps: PHY ability structure to copy date from
2737 * @cfg: PHY configuration structure to copy data to
2739 * Helper function to copy AQC PHY get ability data to PHY set configuration
2743 ice_copy_phy_caps_to_cfg(struct ice_port_info *pi,
2744 struct ice_aqc_get_phy_caps_data *caps,
2745 struct ice_aqc_set_phy_cfg_data *cfg)
2747 if (!pi || !caps || !cfg)
2750 ice_memset(cfg, 0, sizeof(*cfg), ICE_NONDMA_MEM);
2751 cfg->phy_type_low = caps->phy_type_low;
2752 cfg->phy_type_high = caps->phy_type_high;
2753 cfg->caps = caps->caps;
2754 cfg->low_power_ctrl_an = caps->low_power_ctrl_an;
2755 cfg->eee_cap = caps->eee_cap;
2756 cfg->eeer_value = caps->eeer_value;
2757 cfg->link_fec_opt = caps->link_fec_options;
2758 cfg->module_compliance_enforcement =
2759 caps->module_compliance_enforcement;
2761 if (ice_fw_supports_link_override(pi->hw)) {
2762 struct ice_link_default_override_tlv tlv;
2764 if (ice_get_link_default_override(&tlv, pi))
2767 if (tlv.options & ICE_LINK_OVERRIDE_STRICT_MODE)
2768 cfg->module_compliance_enforcement |=
2769 ICE_LINK_OVERRIDE_STRICT_MODE;
2774 * ice_cfg_phy_fec - Configure PHY FEC data based on FEC mode
2775 * @pi: port information structure
2776 * @cfg: PHY configuration data to set FEC mode
2777 * @fec: FEC mode to configure
2780 ice_cfg_phy_fec(struct ice_port_info *pi, struct ice_aqc_set_phy_cfg_data *cfg,
2781 enum ice_fec_mode fec)
2783 struct ice_aqc_get_phy_caps_data *pcaps;
2784 enum ice_status status = ICE_SUCCESS;
2788 return ICE_ERR_BAD_PTR;
2792 pcaps = (struct ice_aqc_get_phy_caps_data *)
2793 ice_malloc(hw, sizeof(*pcaps));
2795 return ICE_ERR_NO_MEMORY;
2797 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_TOPO_CAP, pcaps,
2802 cfg->caps |= (pcaps->caps & ICE_AQC_PHY_EN_AUTO_FEC);
2803 cfg->link_fec_opt = pcaps->link_fec_options;
2807 /* Clear RS bits, and AND BASE-R ability
2808 * bits and OR request bits.
2810 cfg->link_fec_opt &= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN |
2811 ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN;
2812 cfg->link_fec_opt |= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ |
2813 ICE_AQC_PHY_FEC_25G_KR_REQ;
2816 /* Clear BASE-R bits, and AND RS ability
2817 * bits and OR request bits.
2819 cfg->link_fec_opt &= ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN;
2820 cfg->link_fec_opt |= ICE_AQC_PHY_FEC_25G_RS_528_REQ |
2821 ICE_AQC_PHY_FEC_25G_RS_544_REQ;
2824 /* Clear all FEC option bits. */
2825 cfg->link_fec_opt &= ~ICE_AQC_PHY_FEC_MASK;
2828 /* AND auto FEC bit, and all caps bits. */
2829 cfg->caps &= ICE_AQC_PHY_CAPS_MASK;
2830 cfg->link_fec_opt |= pcaps->link_fec_options;
2833 status = ICE_ERR_PARAM;
2837 if (fec == ICE_FEC_AUTO && ice_fw_supports_link_override(pi->hw)) {
2838 struct ice_link_default_override_tlv tlv;
2840 if (ice_get_link_default_override(&tlv, pi))
2843 if (!(tlv.options & ICE_LINK_OVERRIDE_STRICT_MODE) &&
2844 (tlv.options & ICE_LINK_OVERRIDE_EN))
2845 cfg->link_fec_opt = tlv.fec_options;
2849 ice_free(hw, pcaps);
2855 * ice_get_link_status - get status of the HW network link
2856 * @pi: port information structure
2857 * @link_up: pointer to bool (true/false = linkup/linkdown)
2859 * Variable link_up is true if link is up, false if link is down.
2860 * The variable link_up is invalid if status is non zero. As a
2861 * result of this call, link status reporting becomes enabled
2863 enum ice_status ice_get_link_status(struct ice_port_info *pi, bool *link_up)
2865 struct ice_phy_info *phy_info;
2866 enum ice_status status = ICE_SUCCESS;
2868 if (!pi || !link_up)
2869 return ICE_ERR_PARAM;
2871 phy_info = &pi->phy;
2873 if (phy_info->get_link_info) {
2874 status = ice_update_link_info(pi);
2877 ice_debug(pi->hw, ICE_DBG_LINK,
2878 "get link status error, status = %d\n",
2882 *link_up = phy_info->link_info.link_info & ICE_AQ_LINK_UP;
2888 * ice_aq_set_link_restart_an
2889 * @pi: pointer to the port information structure
2890 * @ena_link: if true: enable link, if false: disable link
2891 * @cd: pointer to command details structure or NULL
2893 * Sets up the link and restarts the Auto-Negotiation over the link.
2896 ice_aq_set_link_restart_an(struct ice_port_info *pi, bool ena_link,
2897 struct ice_sq_cd *cd)
2899 struct ice_aqc_restart_an *cmd;
2900 struct ice_aq_desc desc;
2902 cmd = &desc.params.restart_an;
2904 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_restart_an);
2906 cmd->cmd_flags = ICE_AQC_RESTART_AN_LINK_RESTART;
2907 cmd->lport_num = pi->lport;
2909 cmd->cmd_flags |= ICE_AQC_RESTART_AN_LINK_ENABLE;
2911 cmd->cmd_flags &= ~ICE_AQC_RESTART_AN_LINK_ENABLE;
2913 return ice_aq_send_cmd(pi->hw, &desc, NULL, 0, cd);
2917 * ice_aq_set_event_mask
2918 * @hw: pointer to the HW struct
2919 * @port_num: port number of the physical function
2920 * @mask: event mask to be set
2921 * @cd: pointer to command details structure or NULL
2923 * Set event mask (0x0613)
2926 ice_aq_set_event_mask(struct ice_hw *hw, u8 port_num, u16 mask,
2927 struct ice_sq_cd *cd)
2929 struct ice_aqc_set_event_mask *cmd;
2930 struct ice_aq_desc desc;
2932 cmd = &desc.params.set_event_mask;
2934 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_event_mask);
2936 cmd->lport_num = port_num;
2938 cmd->event_mask = CPU_TO_LE16(mask);
2939 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
2943 * ice_aq_set_mac_loopback
2944 * @hw: pointer to the HW struct
2945 * @ena_lpbk: Enable or Disable loopback
2946 * @cd: pointer to command details structure or NULL
2948 * Enable/disable loopback on a given port
2951 ice_aq_set_mac_loopback(struct ice_hw *hw, bool ena_lpbk, struct ice_sq_cd *cd)
2953 struct ice_aqc_set_mac_lb *cmd;
2954 struct ice_aq_desc desc;
2956 cmd = &desc.params.set_mac_lb;
2958 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_mac_lb);
2960 cmd->lb_mode = ICE_AQ_MAC_LB_EN;
2962 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
2966 * ice_aq_set_port_id_led
2967 * @pi: pointer to the port information
2968 * @is_orig_mode: is this LED set to original mode (by the net-list)
2969 * @cd: pointer to command details structure or NULL
2971 * Set LED value for the given port (0x06e9)
2974 ice_aq_set_port_id_led(struct ice_port_info *pi, bool is_orig_mode,
2975 struct ice_sq_cd *cd)
2977 struct ice_aqc_set_port_id_led *cmd;
2978 struct ice_hw *hw = pi->hw;
2979 struct ice_aq_desc desc;
2981 cmd = &desc.params.set_port_id_led;
2983 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_port_id_led);
2986 cmd->ident_mode = ICE_AQC_PORT_IDENT_LED_ORIG;
2988 cmd->ident_mode = ICE_AQC_PORT_IDENT_LED_BLINK;
2990 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
2995 * @hw: pointer to the HW struct
2996 * @lport: bits [7:0] = logical port, bit [8] = logical port valid
2997 * @bus_addr: I2C bus address of the eeprom (typically 0xA0, 0=topo default)
2998 * @mem_addr: I2C offset. lower 8 bits for address, 8 upper bits zero padding.
3000 * @set_page: set or ignore the page
3001 * @data: pointer to data buffer to be read/written to the I2C device.
3002 * @length: 1-16 for read, 1 for write.
3003 * @write: 0 read, 1 for write.
3004 * @cd: pointer to command details structure or NULL
3006 * Read/Write SFF EEPROM (0x06EE)
3009 ice_aq_sff_eeprom(struct ice_hw *hw, u16 lport, u8 bus_addr,
3010 u16 mem_addr, u8 page, u8 set_page, u8 *data, u8 length,
3011 bool write, struct ice_sq_cd *cd)
3013 struct ice_aqc_sff_eeprom *cmd;
3014 struct ice_aq_desc desc;
3015 enum ice_status status;
3017 if (!data || (mem_addr & 0xff00))
3018 return ICE_ERR_PARAM;
3020 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_sff_eeprom);
3021 cmd = &desc.params.read_write_sff_param;
3022 desc.flags = CPU_TO_LE16(ICE_AQ_FLAG_RD | ICE_AQ_FLAG_BUF);
3023 cmd->lport_num = (u8)(lport & 0xff);
3024 cmd->lport_num_valid = (u8)((lport >> 8) & 0x01);
3025 cmd->i2c_bus_addr = CPU_TO_LE16(((bus_addr >> 1) &
3026 ICE_AQC_SFF_I2CBUS_7BIT_M) |
3028 ICE_AQC_SFF_SET_EEPROM_PAGE_S) &
3029 ICE_AQC_SFF_SET_EEPROM_PAGE_M));
3030 cmd->i2c_mem_addr = CPU_TO_LE16(mem_addr & 0xff);
3031 cmd->eeprom_page = CPU_TO_LE16((u16)page << ICE_AQC_SFF_EEPROM_PAGE_S);
3033 cmd->i2c_bus_addr |= CPU_TO_LE16(ICE_AQC_SFF_IS_WRITE);
3035 status = ice_aq_send_cmd(hw, &desc, data, length, cd);
3040 * __ice_aq_get_set_rss_lut
3041 * @hw: pointer to the hardware structure
3042 * @vsi_id: VSI FW index
3043 * @lut_type: LUT table type
3044 * @lut: pointer to the LUT buffer provided by the caller
3045 * @lut_size: size of the LUT buffer
3046 * @glob_lut_idx: global LUT index
3047 * @set: set true to set the table, false to get the table
3049 * Internal function to get (0x0B05) or set (0x0B03) RSS look up table
3051 static enum ice_status
3052 __ice_aq_get_set_rss_lut(struct ice_hw *hw, u16 vsi_id, u8 lut_type, u8 *lut,
3053 u16 lut_size, u8 glob_lut_idx, bool set)
3055 struct ice_aqc_get_set_rss_lut *cmd_resp;
3056 struct ice_aq_desc desc;
3057 enum ice_status status;
3060 cmd_resp = &desc.params.get_set_rss_lut;
3063 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_rss_lut);
3064 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
3066 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_rss_lut);
3069 cmd_resp->vsi_id = CPU_TO_LE16(((vsi_id <<
3070 ICE_AQC_GSET_RSS_LUT_VSI_ID_S) &
3071 ICE_AQC_GSET_RSS_LUT_VSI_ID_M) |
3072 ICE_AQC_GSET_RSS_LUT_VSI_VALID);
3075 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_VSI:
3076 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF:
3077 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL:
3078 flags |= ((lut_type << ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S) &
3079 ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_M);
3082 status = ICE_ERR_PARAM;
3083 goto ice_aq_get_set_rss_lut_exit;
3086 if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL) {
3087 flags |= ((glob_lut_idx << ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S) &
3088 ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_M);
3091 goto ice_aq_get_set_rss_lut_send;
3092 } else if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF) {
3094 goto ice_aq_get_set_rss_lut_send;
3096 goto ice_aq_get_set_rss_lut_send;
3099 /* LUT size is only valid for Global and PF table types */
3101 case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128:
3102 flags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128_FLAG <<
3103 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) &
3104 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M;
3106 case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512:
3107 flags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512_FLAG <<
3108 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) &
3109 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M;
3111 case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K:
3112 if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF) {
3113 flags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K_FLAG <<
3114 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) &
3115 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M;
3120 status = ICE_ERR_PARAM;
3121 goto ice_aq_get_set_rss_lut_exit;
3124 ice_aq_get_set_rss_lut_send:
3125 cmd_resp->flags = CPU_TO_LE16(flags);
3126 status = ice_aq_send_cmd(hw, &desc, lut, lut_size, NULL);
3128 ice_aq_get_set_rss_lut_exit:
3133 * ice_aq_get_rss_lut
3134 * @hw: pointer to the hardware structure
3135 * @vsi_handle: software VSI handle
3136 * @lut_type: LUT table type
3137 * @lut: pointer to the LUT buffer provided by the caller
3138 * @lut_size: size of the LUT buffer
3140 * get the RSS lookup table, PF or VSI type
3143 ice_aq_get_rss_lut(struct ice_hw *hw, u16 vsi_handle, u8 lut_type,
3144 u8 *lut, u16 lut_size)
3146 if (!ice_is_vsi_valid(hw, vsi_handle) || !lut)
3147 return ICE_ERR_PARAM;
3149 return __ice_aq_get_set_rss_lut(hw, ice_get_hw_vsi_num(hw, vsi_handle),
3150 lut_type, lut, lut_size, 0, false);
3154 * ice_aq_set_rss_lut
3155 * @hw: pointer to the hardware structure
3156 * @vsi_handle: software VSI handle
3157 * @lut_type: LUT table type
3158 * @lut: pointer to the LUT buffer provided by the caller
3159 * @lut_size: size of the LUT buffer
3161 * set the RSS lookup table, PF or VSI type
3164 ice_aq_set_rss_lut(struct ice_hw *hw, u16 vsi_handle, u8 lut_type,
3165 u8 *lut, u16 lut_size)
3167 if (!ice_is_vsi_valid(hw, vsi_handle) || !lut)
3168 return ICE_ERR_PARAM;
3170 return __ice_aq_get_set_rss_lut(hw, ice_get_hw_vsi_num(hw, vsi_handle),
3171 lut_type, lut, lut_size, 0, true);
3175 * __ice_aq_get_set_rss_key
3176 * @hw: pointer to the HW struct
3177 * @vsi_id: VSI FW index
3178 * @key: pointer to key info struct
3179 * @set: set true to set the key, false to get the key
3181 * get (0x0B04) or set (0x0B02) the RSS key per VSI
3184 ice_status __ice_aq_get_set_rss_key(struct ice_hw *hw, u16 vsi_id,
3185 struct ice_aqc_get_set_rss_keys *key,
3188 struct ice_aqc_get_set_rss_key *cmd_resp;
3189 u16 key_size = sizeof(*key);
3190 struct ice_aq_desc desc;
3192 cmd_resp = &desc.params.get_set_rss_key;
3195 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_rss_key);
3196 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
3198 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_rss_key);
3201 cmd_resp->vsi_id = CPU_TO_LE16(((vsi_id <<
3202 ICE_AQC_GSET_RSS_KEY_VSI_ID_S) &
3203 ICE_AQC_GSET_RSS_KEY_VSI_ID_M) |
3204 ICE_AQC_GSET_RSS_KEY_VSI_VALID);
3206 return ice_aq_send_cmd(hw, &desc, key, key_size, NULL);
3210 * ice_aq_get_rss_key
3211 * @hw: pointer to the HW struct
3212 * @vsi_handle: software VSI handle
3213 * @key: pointer to key info struct
3215 * get the RSS key per VSI
3218 ice_aq_get_rss_key(struct ice_hw *hw, u16 vsi_handle,
3219 struct ice_aqc_get_set_rss_keys *key)
3221 if (!ice_is_vsi_valid(hw, vsi_handle) || !key)
3222 return ICE_ERR_PARAM;
3224 return __ice_aq_get_set_rss_key(hw, ice_get_hw_vsi_num(hw, vsi_handle),
3229 * ice_aq_set_rss_key
3230 * @hw: pointer to the HW struct
3231 * @vsi_handle: software VSI handle
3232 * @keys: pointer to key info struct
3234 * set the RSS key per VSI
3237 ice_aq_set_rss_key(struct ice_hw *hw, u16 vsi_handle,
3238 struct ice_aqc_get_set_rss_keys *keys)
3240 if (!ice_is_vsi_valid(hw, vsi_handle) || !keys)
3241 return ICE_ERR_PARAM;
3243 return __ice_aq_get_set_rss_key(hw, ice_get_hw_vsi_num(hw, vsi_handle),
3248 * ice_aq_add_lan_txq
3249 * @hw: pointer to the hardware structure
3250 * @num_qgrps: Number of added queue groups
3251 * @qg_list: list of queue groups to be added
3252 * @buf_size: size of buffer for indirect command
3253 * @cd: pointer to command details structure or NULL
3255 * Add Tx LAN queue (0x0C30)
3258 * Prior to calling add Tx LAN queue:
3259 * Initialize the following as part of the Tx queue context:
3260 * Completion queue ID if the queue uses Completion queue, Quanta profile,
3261 * Cache profile and Packet shaper profile.
3263 * After add Tx LAN queue AQ command is completed:
3264 * Interrupts should be associated with specific queues,
3265 * Association of Tx queue to Doorbell queue is not part of Add LAN Tx queue
3269 ice_aq_add_lan_txq(struct ice_hw *hw, u8 num_qgrps,
3270 struct ice_aqc_add_tx_qgrp *qg_list, u16 buf_size,
3271 struct ice_sq_cd *cd)
3273 u16 i, sum_header_size, sum_q_size = 0;
3274 struct ice_aqc_add_tx_qgrp *list;
3275 struct ice_aqc_add_txqs *cmd;
3276 struct ice_aq_desc desc;
3278 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
3280 cmd = &desc.params.add_txqs;
3282 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_add_txqs);
3285 return ICE_ERR_PARAM;
3287 if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS)
3288 return ICE_ERR_PARAM;
3290 sum_header_size = num_qgrps *
3291 (sizeof(*qg_list) - sizeof(*qg_list->txqs));
3294 for (i = 0; i < num_qgrps; i++) {
3295 struct ice_aqc_add_txqs_perq *q = list->txqs;
3297 sum_q_size += list->num_txqs * sizeof(*q);
3298 list = (struct ice_aqc_add_tx_qgrp *)(q + list->num_txqs);
3301 if (buf_size != (sum_header_size + sum_q_size))
3302 return ICE_ERR_PARAM;
3304 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
3306 cmd->num_qgrps = num_qgrps;
3308 return ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd);
3312 * ice_aq_dis_lan_txq
3313 * @hw: pointer to the hardware structure
3314 * @num_qgrps: number of groups in the list
3315 * @qg_list: the list of groups to disable
3316 * @buf_size: the total size of the qg_list buffer in bytes
3317 * @rst_src: if called due to reset, specifies the reset source
3318 * @vmvf_num: the relative VM or VF number that is undergoing the reset
3319 * @cd: pointer to command details structure or NULL
3321 * Disable LAN Tx queue (0x0C31)
3323 static enum ice_status
3324 ice_aq_dis_lan_txq(struct ice_hw *hw, u8 num_qgrps,
3325 struct ice_aqc_dis_txq_item *qg_list, u16 buf_size,
3326 enum ice_disq_rst_src rst_src, u16 vmvf_num,
3327 struct ice_sq_cd *cd)
3329 struct ice_aqc_dis_txqs *cmd;
3330 struct ice_aq_desc desc;
3331 enum ice_status status;
3334 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
3335 cmd = &desc.params.dis_txqs;
3336 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_dis_txqs);
3338 /* qg_list can be NULL only in VM/VF reset flow */
3339 if (!qg_list && !rst_src)
3340 return ICE_ERR_PARAM;
3342 if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS)
3343 return ICE_ERR_PARAM;
3345 cmd->num_entries = num_qgrps;
3347 cmd->vmvf_and_timeout = CPU_TO_LE16((5 << ICE_AQC_Q_DIS_TIMEOUT_S) &
3348 ICE_AQC_Q_DIS_TIMEOUT_M);
3352 cmd->cmd_type = ICE_AQC_Q_DIS_CMD_VM_RESET;
3353 cmd->vmvf_and_timeout |=
3354 CPU_TO_LE16(vmvf_num & ICE_AQC_Q_DIS_VMVF_NUM_M);
3361 /* flush pipe on time out */
3362 cmd->cmd_type |= ICE_AQC_Q_DIS_CMD_FLUSH_PIPE;
3363 /* If no queue group info, we are in a reset flow. Issue the AQ */
3367 /* set RD bit to indicate that command buffer is provided by the driver
3368 * and it needs to be read by the firmware
3370 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
3372 for (i = 0; i < num_qgrps; ++i) {
3373 /* Calculate the size taken up by the queue IDs in this group */
3374 sz += qg_list[i].num_qs * sizeof(qg_list[i].q_id);
3376 /* Add the size of the group header */
3377 sz += sizeof(qg_list[i]) - sizeof(qg_list[i].q_id);
3379 /* If the num of queues is even, add 2 bytes of padding */
3380 if ((qg_list[i].num_qs % 2) == 0)
3385 return ICE_ERR_PARAM;
3388 status = ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd);
3391 ice_debug(hw, ICE_DBG_SCHED, "VM%d disable failed %d\n",
3392 vmvf_num, hw->adminq.sq_last_status);
3394 ice_debug(hw, ICE_DBG_SCHED, "disable queue %d failed %d\n",
3395 LE16_TO_CPU(qg_list[0].q_id[0]),
3396 hw->adminq.sq_last_status);
3402 * ice_aq_move_recfg_lan_txq
3403 * @hw: pointer to the hardware structure
3404 * @num_qs: number of queues to move/reconfigure
3405 * @is_move: true if this operation involves node movement
3406 * @is_tc_change: true if this operation involves a TC change
3407 * @subseq_call: true if this operation is a subsequent call
3408 * @flush_pipe: on timeout, true to flush pipe, false to return EAGAIN
3409 * @timeout: timeout in units of 100 usec (valid values 0-50)
3410 * @blocked_cgds: out param, bitmap of CGDs that timed out if returning EAGAIN
3411 * @buf: struct containing src/dest TEID and per-queue info
3412 * @buf_size: size of buffer for indirect command
3413 * @txqs_moved: out param, number of queues successfully moved
3414 * @cd: pointer to command details structure or NULL
3416 * Move / Reconfigure Tx LAN queues (0x0C32)
3419 ice_aq_move_recfg_lan_txq(struct ice_hw *hw, u8 num_qs, bool is_move,
3420 bool is_tc_change, bool subseq_call, bool flush_pipe,
3421 u8 timeout, u32 *blocked_cgds,
3422 struct ice_aqc_move_txqs_data *buf, u16 buf_size,
3423 u8 *txqs_moved, struct ice_sq_cd *cd)
3425 struct ice_aqc_move_txqs *cmd;
3426 struct ice_aq_desc desc;
3427 enum ice_status status;
3429 cmd = &desc.params.move_txqs;
3430 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_move_recfg_txqs);
3432 #define ICE_LAN_TXQ_MOVE_TIMEOUT_MAX 50
3433 if (timeout > ICE_LAN_TXQ_MOVE_TIMEOUT_MAX)
3434 return ICE_ERR_PARAM;
3436 if (is_tc_change && !flush_pipe && !blocked_cgds)
3437 return ICE_ERR_PARAM;
3439 if (!is_move && !is_tc_change)
3440 return ICE_ERR_PARAM;
3442 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
3445 cmd->cmd_type |= ICE_AQC_Q_CMD_TYPE_MOVE;
3448 cmd->cmd_type |= ICE_AQC_Q_CMD_TYPE_TC_CHANGE;
3451 cmd->cmd_type |= ICE_AQC_Q_CMD_SUBSEQ_CALL;
3454 cmd->cmd_type |= ICE_AQC_Q_CMD_FLUSH_PIPE;
3456 cmd->num_qs = num_qs;
3457 cmd->timeout = ((timeout << ICE_AQC_Q_CMD_TIMEOUT_S) &
3458 ICE_AQC_Q_CMD_TIMEOUT_M);
3460 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);
3462 if (!status && txqs_moved)
3463 *txqs_moved = cmd->num_qs;
3465 if (hw->adminq.sq_last_status == ICE_AQ_RC_EAGAIN &&
3466 is_tc_change && !flush_pipe)
3467 *blocked_cgds = LE32_TO_CPU(cmd->blocked_cgds);
3472 /* End of FW Admin Queue command wrappers */
3475 * ice_write_byte - write a byte to a packed context structure
3476 * @src_ctx: the context structure to read from
3477 * @dest_ctx: the context to be written to
3478 * @ce_info: a description of the struct to be filled
3481 ice_write_byte(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)
3483 u8 src_byte, dest_byte, mask;
3487 /* copy from the next struct field */
3488 from = src_ctx + ce_info->offset;
3490 /* prepare the bits and mask */
3491 shift_width = ce_info->lsb % 8;
3492 mask = (u8)(BIT(ce_info->width) - 1);
3497 /* shift to correct alignment */
3498 mask <<= shift_width;
3499 src_byte <<= shift_width;
3501 /* get the current bits from the target bit string */
3502 dest = dest_ctx + (ce_info->lsb / 8);
3504 ice_memcpy(&dest_byte, dest, sizeof(dest_byte), ICE_DMA_TO_NONDMA);
3506 dest_byte &= ~mask; /* get the bits not changing */
3507 dest_byte |= src_byte; /* add in the new bits */
3509 /* put it all back */
3510 ice_memcpy(dest, &dest_byte, sizeof(dest_byte), ICE_NONDMA_TO_DMA);
3514 * ice_write_word - write a word to a packed context structure
3515 * @src_ctx: the context structure to read from
3516 * @dest_ctx: the context to be written to
3517 * @ce_info: a description of the struct to be filled
3520 ice_write_word(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)
3527 /* copy from the next struct field */
3528 from = src_ctx + ce_info->offset;
3530 /* prepare the bits and mask */
3531 shift_width = ce_info->lsb % 8;
3532 mask = BIT(ce_info->width) - 1;
3534 /* don't swizzle the bits until after the mask because the mask bits
3535 * will be in a different bit position on big endian machines
3537 src_word = *(u16 *)from;
3540 /* shift to correct alignment */
3541 mask <<= shift_width;
3542 src_word <<= shift_width;
3544 /* get the current bits from the target bit string */
3545 dest = dest_ctx + (ce_info->lsb / 8);
3547 ice_memcpy(&dest_word, dest, sizeof(dest_word), ICE_DMA_TO_NONDMA);
3549 dest_word &= ~(CPU_TO_LE16(mask)); /* get the bits not changing */
3550 dest_word |= CPU_TO_LE16(src_word); /* add in the new bits */
3552 /* put it all back */
3553 ice_memcpy(dest, &dest_word, sizeof(dest_word), ICE_NONDMA_TO_DMA);
3557 * ice_write_dword - write a dword to a packed context structure
3558 * @src_ctx: the context structure to read from
3559 * @dest_ctx: the context to be written to
3560 * @ce_info: a description of the struct to be filled
3563 ice_write_dword(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)
3565 u32 src_dword, mask;
3570 /* copy from the next struct field */
3571 from = src_ctx + ce_info->offset;
3573 /* prepare the bits and mask */
3574 shift_width = ce_info->lsb % 8;
3576 /* if the field width is exactly 32 on an x86 machine, then the shift
3577 * operation will not work because the SHL instructions count is masked
3578 * to 5 bits so the shift will do nothing
3580 if (ce_info->width < 32)
3581 mask = BIT(ce_info->width) - 1;
3585 /* don't swizzle the bits until after the mask because the mask bits
3586 * will be in a different bit position on big endian machines
3588 src_dword = *(u32 *)from;
3591 /* shift to correct alignment */
3592 mask <<= shift_width;
3593 src_dword <<= shift_width;
3595 /* get the current bits from the target bit string */
3596 dest = dest_ctx + (ce_info->lsb / 8);
3598 ice_memcpy(&dest_dword, dest, sizeof(dest_dword), ICE_DMA_TO_NONDMA);
3600 dest_dword &= ~(CPU_TO_LE32(mask)); /* get the bits not changing */
3601 dest_dword |= CPU_TO_LE32(src_dword); /* add in the new bits */
3603 /* put it all back */
3604 ice_memcpy(dest, &dest_dword, sizeof(dest_dword), ICE_NONDMA_TO_DMA);
3608 * ice_write_qword - write a qword to a packed context structure
3609 * @src_ctx: the context structure to read from
3610 * @dest_ctx: the context to be written to
3611 * @ce_info: a description of the struct to be filled
3614 ice_write_qword(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)
3616 u64 src_qword, mask;
3621 /* copy from the next struct field */
3622 from = src_ctx + ce_info->offset;
3624 /* prepare the bits and mask */
3625 shift_width = ce_info->lsb % 8;
3627 /* if the field width is exactly 64 on an x86 machine, then the shift
3628 * operation will not work because the SHL instructions count is masked
3629 * to 6 bits so the shift will do nothing
3631 if (ce_info->width < 64)
3632 mask = BIT_ULL(ce_info->width) - 1;
3636 /* don't swizzle the bits until after the mask because the mask bits
3637 * will be in a different bit position on big endian machines
3639 src_qword = *(u64 *)from;
3642 /* shift to correct alignment */
3643 mask <<= shift_width;
3644 src_qword <<= shift_width;
3646 /* get the current bits from the target bit string */
3647 dest = dest_ctx + (ce_info->lsb / 8);
3649 ice_memcpy(&dest_qword, dest, sizeof(dest_qword), ICE_DMA_TO_NONDMA);
3651 dest_qword &= ~(CPU_TO_LE64(mask)); /* get the bits not changing */
3652 dest_qword |= CPU_TO_LE64(src_qword); /* add in the new bits */
3654 /* put it all back */
3655 ice_memcpy(dest, &dest_qword, sizeof(dest_qword), ICE_NONDMA_TO_DMA);
3659 * ice_set_ctx - set context bits in packed structure
3660 * @hw: pointer to the hardware structure
3661 * @src_ctx: pointer to a generic non-packed context structure
3662 * @dest_ctx: pointer to memory for the packed structure
3663 * @ce_info: a description of the structure to be transformed
3666 ice_set_ctx(struct ice_hw *hw, u8 *src_ctx, u8 *dest_ctx,
3667 const struct ice_ctx_ele *ce_info)
3671 for (f = 0; ce_info[f].width; f++) {
3672 /* We have to deal with each element of the FW response
3673 * using the correct size so that we are correct regardless
3674 * of the endianness of the machine.
3676 if (ce_info[f].width > (ce_info[f].size_of * BITS_PER_BYTE)) {
3677 ice_debug(hw, ICE_DBG_QCTX,
3678 "Field %d width of %d bits larger than size of %d byte(s) ... skipping write\n",
3679 f, ce_info[f].width, ce_info[f].size_of);
3682 switch (ce_info[f].size_of) {
3684 ice_write_byte(src_ctx, dest_ctx, &ce_info[f]);
3687 ice_write_word(src_ctx, dest_ctx, &ce_info[f]);
3690 ice_write_dword(src_ctx, dest_ctx, &ce_info[f]);
3693 ice_write_qword(src_ctx, dest_ctx, &ce_info[f]);
3696 return ICE_ERR_INVAL_SIZE;
3704 * ice_read_byte - read context byte into struct
3705 * @src_ctx: the context structure to read from
3706 * @dest_ctx: the context to be written to
3707 * @ce_info: a description of the struct to be filled
3710 ice_read_byte(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info)
3716 /* prepare the bits and mask */
3717 shift_width = ce_info->lsb % 8;
3718 mask = (u8)(BIT(ce_info->width) - 1);
3720 /* shift to correct alignment */
3721 mask <<= shift_width;
3723 /* get the current bits from the src bit string */
3724 src = src_ctx + (ce_info->lsb / 8);
3726 ice_memcpy(&dest_byte, src, sizeof(dest_byte), ICE_DMA_TO_NONDMA);
3728 dest_byte &= ~(mask);
3730 dest_byte >>= shift_width;
3732 /* get the address from the struct field */
3733 target = dest_ctx + ce_info->offset;
3735 /* put it back in the struct */
3736 ice_memcpy(target, &dest_byte, sizeof(dest_byte), ICE_NONDMA_TO_DMA);
3740 * ice_read_word - read context word into struct
3741 * @src_ctx: the context structure to read from
3742 * @dest_ctx: the context to be written to
3743 * @ce_info: a description of the struct to be filled
3746 ice_read_word(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info)
3748 u16 dest_word, mask;
3753 /* prepare the bits and mask */
3754 shift_width = ce_info->lsb % 8;
3755 mask = BIT(ce_info->width) - 1;
3757 /* shift to correct alignment */
3758 mask <<= shift_width;
3760 /* get the current bits from the src bit string */
3761 src = src_ctx + (ce_info->lsb / 8);
3763 ice_memcpy(&src_word, src, sizeof(src_word), ICE_DMA_TO_NONDMA);
3765 /* the data in the memory is stored as little endian so mask it
3768 src_word &= ~(CPU_TO_LE16(mask));
3770 /* get the data back into host order before shifting */
3771 dest_word = LE16_TO_CPU(src_word);
3773 dest_word >>= shift_width;
3775 /* get the address from the struct field */
3776 target = dest_ctx + ce_info->offset;
3778 /* put it back in the struct */
3779 ice_memcpy(target, &dest_word, sizeof(dest_word), ICE_NONDMA_TO_DMA);
3783 * ice_read_dword - read context dword into struct
3784 * @src_ctx: the context structure to read from
3785 * @dest_ctx: the context to be written to
3786 * @ce_info: a description of the struct to be filled
3789 ice_read_dword(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info)
3791 u32 dest_dword, mask;
3796 /* prepare the bits and mask */
3797 shift_width = ce_info->lsb % 8;
3799 /* if the field width is exactly 32 on an x86 machine, then the shift
3800 * operation will not work because the SHL instructions count is masked
3801 * to 5 bits so the shift will do nothing
3803 if (ce_info->width < 32)
3804 mask = BIT(ce_info->width) - 1;
3808 /* shift to correct alignment */
3809 mask <<= shift_width;
3811 /* get the current bits from the src bit string */
3812 src = src_ctx + (ce_info->lsb / 8);
3814 ice_memcpy(&src_dword, src, sizeof(src_dword), ICE_DMA_TO_NONDMA);
3816 /* the data in the memory is stored as little endian so mask it
3819 src_dword &= ~(CPU_TO_LE32(mask));
3821 /* get the data back into host order before shifting */
3822 dest_dword = LE32_TO_CPU(src_dword);
3824 dest_dword >>= shift_width;
3826 /* get the address from the struct field */
3827 target = dest_ctx + ce_info->offset;
3829 /* put it back in the struct */
3830 ice_memcpy(target, &dest_dword, sizeof(dest_dword), ICE_NONDMA_TO_DMA);
3834 * ice_read_qword - read context qword into struct
3835 * @src_ctx: the context structure to read from
3836 * @dest_ctx: the context to be written to
3837 * @ce_info: a description of the struct to be filled
3840 ice_read_qword(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info)
3842 u64 dest_qword, mask;
3847 /* prepare the bits and mask */
3848 shift_width = ce_info->lsb % 8;
3850 /* if the field width is exactly 64 on an x86 machine, then the shift
3851 * operation will not work because the SHL instructions count is masked
3852 * to 6 bits so the shift will do nothing
3854 if (ce_info->width < 64)
3855 mask = BIT_ULL(ce_info->width) - 1;
3859 /* shift to correct alignment */
3860 mask <<= shift_width;
3862 /* get the current bits from the src bit string */
3863 src = src_ctx + (ce_info->lsb / 8);
3865 ice_memcpy(&src_qword, src, sizeof(src_qword), ICE_DMA_TO_NONDMA);
3867 /* the data in the memory is stored as little endian so mask it
3870 src_qword &= ~(CPU_TO_LE64(mask));
3872 /* get the data back into host order before shifting */
3873 dest_qword = LE64_TO_CPU(src_qword);
3875 dest_qword >>= shift_width;
3877 /* get the address from the struct field */
3878 target = dest_ctx + ce_info->offset;
3880 /* put it back in the struct */
3881 ice_memcpy(target, &dest_qword, sizeof(dest_qword), ICE_NONDMA_TO_DMA);
3885 * ice_get_ctx - extract context bits from a packed structure
3886 * @src_ctx: pointer to a generic packed context structure
3887 * @dest_ctx: pointer to a generic non-packed context structure
3888 * @ce_info: a description of the structure to be read from
3891 ice_get_ctx(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info)
3895 for (f = 0; ce_info[f].width; f++) {
3896 switch (ce_info[f].size_of) {
3898 ice_read_byte(src_ctx, dest_ctx, &ce_info[f]);
3901 ice_read_word(src_ctx, dest_ctx, &ce_info[f]);
3904 ice_read_dword(src_ctx, dest_ctx, &ce_info[f]);
3907 ice_read_qword(src_ctx, dest_ctx, &ce_info[f]);
3910 /* nothing to do, just keep going */
3919 * ice_get_lan_q_ctx - get the LAN queue context for the given VSI and TC
3920 * @hw: pointer to the HW struct
3921 * @vsi_handle: software VSI handle
3923 * @q_handle: software queue handle
3926 ice_get_lan_q_ctx(struct ice_hw *hw, u16 vsi_handle, u8 tc, u16 q_handle)
3928 struct ice_vsi_ctx *vsi;
3929 struct ice_q_ctx *q_ctx;
3931 vsi = ice_get_vsi_ctx(hw, vsi_handle);
3934 if (q_handle >= vsi->num_lan_q_entries[tc])
3936 if (!vsi->lan_q_ctx[tc])
3938 q_ctx = vsi->lan_q_ctx[tc];
3939 return &q_ctx[q_handle];
3944 * @pi: port information structure
3945 * @vsi_handle: software VSI handle
3947 * @q_handle: software queue handle
3948 * @num_qgrps: Number of added queue groups
3949 * @buf: list of queue groups to be added
3950 * @buf_size: size of buffer for indirect command
3951 * @cd: pointer to command details structure or NULL
3953 * This function adds one LAN queue
3956 ice_ena_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u16 q_handle,
3957 u8 num_qgrps, struct ice_aqc_add_tx_qgrp *buf, u16 buf_size,
3958 struct ice_sq_cd *cd)
3960 struct ice_aqc_txsched_elem_data node = { 0 };
3961 struct ice_sched_node *parent;
3962 struct ice_q_ctx *q_ctx;
3963 enum ice_status status;
3966 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY)
3969 if (num_qgrps > 1 || buf->num_txqs > 1)
3970 return ICE_ERR_MAX_LIMIT;
3974 if (!ice_is_vsi_valid(hw, vsi_handle))
3975 return ICE_ERR_PARAM;
3977 ice_acquire_lock(&pi->sched_lock);
3979 q_ctx = ice_get_lan_q_ctx(hw, vsi_handle, tc, q_handle);
3981 ice_debug(hw, ICE_DBG_SCHED, "Enaq: invalid queue handle %d\n",
3983 status = ICE_ERR_PARAM;
3987 /* find a parent node */
3988 parent = ice_sched_get_free_qparent(pi, vsi_handle, tc,
3989 ICE_SCHED_NODE_OWNER_LAN);
3991 status = ICE_ERR_PARAM;
3995 buf->parent_teid = parent->info.node_teid;
3996 node.parent_teid = parent->info.node_teid;
3997 /* Mark that the values in the "generic" section as valid. The default
3998 * value in the "generic" section is zero. This means that :
3999 * - Scheduling mode is Bytes Per Second (BPS), indicated by Bit 0.
4000 * - 0 priority among siblings, indicated by Bit 1-3.
4001 * - WFQ, indicated by Bit 4.
4002 * - 0 Adjustment value is used in PSM credit update flow, indicated by
4004 * - Bit 7 is reserved.
4005 * Without setting the generic section as valid in valid_sections, the
4006 * Admin queue command will fail with error code ICE_AQ_RC_EINVAL.
4008 buf->txqs[0].info.valid_sections = ICE_AQC_ELEM_VALID_GENERIC;
4010 /* add the LAN queue */
4011 status = ice_aq_add_lan_txq(hw, num_qgrps, buf, buf_size, cd);
4012 if (status != ICE_SUCCESS) {
4013 ice_debug(hw, ICE_DBG_SCHED, "enable queue %d failed %d\n",
4014 LE16_TO_CPU(buf->txqs[0].txq_id),
4015 hw->adminq.sq_last_status);
4019 node.node_teid = buf->txqs[0].q_teid;
4020 node.data.elem_type = ICE_AQC_ELEM_TYPE_LEAF;
4021 q_ctx->q_handle = q_handle;
4022 q_ctx->q_teid = LE32_TO_CPU(node.node_teid);
4024 /* add a leaf node into scheduler tree queue layer */
4025 status = ice_sched_add_node(pi, hw->num_tx_sched_layers - 1, &node);
4027 status = ice_sched_replay_q_bw(pi, q_ctx);
4030 ice_release_lock(&pi->sched_lock);
4036 * @pi: port information structure
4037 * @vsi_handle: software VSI handle
4039 * @num_queues: number of queues
4040 * @q_handles: pointer to software queue handle array
4041 * @q_ids: pointer to the q_id array
4042 * @q_teids: pointer to queue node teids
4043 * @rst_src: if called due to reset, specifies the reset source
4044 * @vmvf_num: the relative VM or VF number that is undergoing the reset
4045 * @cd: pointer to command details structure or NULL
4047 * This function removes queues and their corresponding nodes in SW DB
4050 ice_dis_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u8 num_queues,
4051 u16 *q_handles, u16 *q_ids, u32 *q_teids,
4052 enum ice_disq_rst_src rst_src, u16 vmvf_num,
4053 struct ice_sq_cd *cd)
4055 enum ice_status status = ICE_ERR_DOES_NOT_EXIST;
4056 struct ice_aqc_dis_txq_item qg_list;
4057 struct ice_q_ctx *q_ctx;
4060 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY)
4064 /* if queue is disabled already yet the disable queue command
4065 * has to be sent to complete the VF reset, then call
4066 * ice_aq_dis_lan_txq without any queue information
4069 return ice_aq_dis_lan_txq(pi->hw, 0, NULL, 0, rst_src,
4074 ice_acquire_lock(&pi->sched_lock);
4076 for (i = 0; i < num_queues; i++) {
4077 struct ice_sched_node *node;
4079 node = ice_sched_find_node_by_teid(pi->root, q_teids[i]);
4082 q_ctx = ice_get_lan_q_ctx(pi->hw, vsi_handle, tc, q_handles[i]);
4084 ice_debug(pi->hw, ICE_DBG_SCHED, "invalid queue handle%d\n",
4088 if (q_ctx->q_handle != q_handles[i]) {
4089 ice_debug(pi->hw, ICE_DBG_SCHED, "Err:handles %d %d\n",
4090 q_ctx->q_handle, q_handles[i]);
4093 qg_list.parent_teid = node->info.parent_teid;
4095 qg_list.q_id[0] = CPU_TO_LE16(q_ids[i]);
4096 status = ice_aq_dis_lan_txq(pi->hw, 1, &qg_list,
4097 sizeof(qg_list), rst_src, vmvf_num,
4100 if (status != ICE_SUCCESS)
4102 ice_free_sched_node(pi, node);
4103 q_ctx->q_handle = ICE_INVAL_Q_HANDLE;
4105 ice_release_lock(&pi->sched_lock);
4110 * ice_cfg_vsi_qs - configure the new/existing VSI queues
4111 * @pi: port information structure
4112 * @vsi_handle: software VSI handle
4113 * @tc_bitmap: TC bitmap
4114 * @maxqs: max queues array per TC
4115 * @owner: LAN or RDMA
4117 * This function adds/updates the VSI queues per TC.
4119 static enum ice_status
4120 ice_cfg_vsi_qs(struct ice_port_info *pi, u16 vsi_handle, u16 tc_bitmap,
4121 u16 *maxqs, u8 owner)
4123 enum ice_status status = ICE_SUCCESS;
4126 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY)
4129 if (!ice_is_vsi_valid(pi->hw, vsi_handle))
4130 return ICE_ERR_PARAM;
4132 ice_acquire_lock(&pi->sched_lock);
4134 ice_for_each_traffic_class(i) {
4135 /* configuration is possible only if TC node is present */
4136 if (!ice_sched_get_tc_node(pi, i))
4139 status = ice_sched_cfg_vsi(pi, vsi_handle, i, maxqs[i], owner,
4140 ice_is_tc_ena(tc_bitmap, i));
4145 ice_release_lock(&pi->sched_lock);
4150 * ice_cfg_vsi_lan - configure VSI LAN queues
4151 * @pi: port information structure
4152 * @vsi_handle: software VSI handle
4153 * @tc_bitmap: TC bitmap
4154 * @max_lanqs: max LAN queues array per TC
4156 * This function adds/updates the VSI LAN queues per TC.
4159 ice_cfg_vsi_lan(struct ice_port_info *pi, u16 vsi_handle, u16 tc_bitmap,
4162 return ice_cfg_vsi_qs(pi, vsi_handle, tc_bitmap, max_lanqs,
4163 ICE_SCHED_NODE_OWNER_LAN);
4167 * ice_is_main_vsi - checks whether the VSI is main VSI
4168 * @hw: pointer to the HW struct
4169 * @vsi_handle: VSI handle
4171 * Checks whether the VSI is the main VSI (the first PF VSI created on
4174 static bool ice_is_main_vsi(struct ice_hw *hw, u16 vsi_handle)
4176 return vsi_handle == ICE_MAIN_VSI_HANDLE && hw->vsi_ctx[vsi_handle];
4180 * ice_replay_pre_init - replay pre initialization
4181 * @hw: pointer to the HW struct
4182 * @sw: pointer to switch info struct for which function initializes filters
4184 * Initializes required config data for VSI, FD, ACL, and RSS before replay.
4186 static enum ice_status
4187 ice_replay_pre_init(struct ice_hw *hw, struct ice_switch_info *sw)
4191 /* Delete old entries from replay filter list head if there is any */
4192 ice_rm_sw_replay_rule_info(hw, sw);
4193 /* In start of replay, move entries into replay_rules list, it
4194 * will allow adding rules entries back to filt_rules list,
4195 * which is operational list.
4197 for (i = 0; i < ICE_MAX_NUM_RECIPES; i++)
4198 LIST_REPLACE_INIT(&sw->recp_list[i].filt_rules,
4199 &sw->recp_list[i].filt_replay_rules);
4200 ice_sched_replay_agg_vsi_preinit(hw);
4202 return ice_sched_replay_tc_node_bw(hw->port_info);
4206 * ice_replay_vsi - replay VSI configuration
4207 * @hw: pointer to the HW struct
4208 * @vsi_handle: driver VSI handle
4210 * Restore all VSI configuration after reset. It is required to call this
4211 * function with main VSI first.
4213 enum ice_status ice_replay_vsi(struct ice_hw *hw, u16 vsi_handle)
4215 struct ice_switch_info *sw = hw->switch_info;
4216 struct ice_port_info *pi = hw->port_info;
4217 enum ice_status status;
4219 if (!ice_is_vsi_valid(hw, vsi_handle))
4220 return ICE_ERR_PARAM;
4222 /* Replay pre-initialization if there is any */
4223 if (ice_is_main_vsi(hw, vsi_handle)) {
4224 status = ice_replay_pre_init(hw, sw);
4228 /* Replay per VSI all RSS configurations */
4229 status = ice_replay_rss_cfg(hw, vsi_handle);
4232 /* Replay per VSI all filters */
4233 status = ice_replay_vsi_all_fltr(hw, pi, vsi_handle);
4235 status = ice_replay_vsi_agg(hw, vsi_handle);
4240 * ice_replay_post - post replay configuration cleanup
4241 * @hw: pointer to the HW struct
4243 * Post replay cleanup.
4245 void ice_replay_post(struct ice_hw *hw)
4247 /* Delete old entries from replay filter list head */
4248 ice_rm_all_sw_replay_rule_info(hw);
4249 ice_sched_replay_agg(hw);
4253 * ice_stat_update40 - read 40 bit stat from the chip and update stat values
4254 * @hw: ptr to the hardware info
4255 * @reg: offset of 64 bit HW register to read from
4256 * @prev_stat_loaded: bool to specify if previous stats are loaded
4257 * @prev_stat: ptr to previous loaded stat value
4258 * @cur_stat: ptr to current stat value
4261 ice_stat_update40(struct ice_hw *hw, u32 reg, bool prev_stat_loaded,
4262 u64 *prev_stat, u64 *cur_stat)
4264 u64 new_data = rd64(hw, reg) & (BIT_ULL(40) - 1);
4266 /* device stats are not reset at PFR, they likely will not be zeroed
4267 * when the driver starts. Thus, save the value from the first read
4268 * without adding to the statistic value so that we report stats which
4269 * count up from zero.
4271 if (!prev_stat_loaded) {
4272 *prev_stat = new_data;
4276 /* Calculate the difference between the new and old values, and then
4277 * add it to the software stat value.
4279 if (new_data >= *prev_stat)
4280 *cur_stat += new_data - *prev_stat;
4282 /* to manage the potential roll-over */
4283 *cur_stat += (new_data + BIT_ULL(40)) - *prev_stat;
4285 /* Update the previously stored value to prepare for next read */
4286 *prev_stat = new_data;
4290 * ice_stat_update32 - read 32 bit stat from the chip and update stat values
4291 * @hw: ptr to the hardware info
4292 * @reg: offset of HW register to read from
4293 * @prev_stat_loaded: bool to specify if previous stats are loaded
4294 * @prev_stat: ptr to previous loaded stat value
4295 * @cur_stat: ptr to current stat value
4298 ice_stat_update32(struct ice_hw *hw, u32 reg, bool prev_stat_loaded,
4299 u64 *prev_stat, u64 *cur_stat)
4303 new_data = rd32(hw, reg);
4305 /* device stats are not reset at PFR, they likely will not be zeroed
4306 * when the driver starts. Thus, save the value from the first read
4307 * without adding to the statistic value so that we report stats which
4308 * count up from zero.
4310 if (!prev_stat_loaded) {
4311 *prev_stat = new_data;
4315 /* Calculate the difference between the new and old values, and then
4316 * add it to the software stat value.
4318 if (new_data >= *prev_stat)
4319 *cur_stat += new_data - *prev_stat;
4321 /* to manage the potential roll-over */
4322 *cur_stat += (new_data + BIT_ULL(32)) - *prev_stat;
4324 /* Update the previously stored value to prepare for next read */
4325 *prev_stat = new_data;
4329 * ice_stat_update_repc - read GLV_REPC stats from chip and update stat values
4330 * @hw: ptr to the hardware info
4331 * @vsi_handle: VSI handle
4332 * @prev_stat_loaded: bool to specify if the previous stat values are loaded
4333 * @cur_stats: ptr to current stats structure
4335 * The GLV_REPC statistic register actually tracks two 16bit statistics, and
4336 * thus cannot be read using the normal ice_stat_update32 function.
4338 * Read the GLV_REPC register associated with the given VSI, and update the
4339 * rx_no_desc and rx_error values in the ice_eth_stats structure.
4341 * Because the statistics in GLV_REPC stick at 0xFFFF, the register must be
4342 * cleared each time it's read.
4344 * Note that the GLV_RDPC register also counts the causes that would trigger
4345 * GLV_REPC. However, it does not give the finer grained detail about why the
4346 * packets are being dropped. The GLV_REPC values can be used to distinguish
4347 * whether Rx packets are dropped due to errors or due to no available
4351 ice_stat_update_repc(struct ice_hw *hw, u16 vsi_handle, bool prev_stat_loaded,
4352 struct ice_eth_stats *cur_stats)
4354 u16 vsi_num, no_desc, error_cnt;
4357 if (!ice_is_vsi_valid(hw, vsi_handle))
4360 vsi_num = ice_get_hw_vsi_num(hw, vsi_handle);
4362 /* If we haven't loaded stats yet, just clear the current value */
4363 if (!prev_stat_loaded) {
4364 wr32(hw, GLV_REPC(vsi_num), 0);
4368 repc = rd32(hw, GLV_REPC(vsi_num));
4369 no_desc = (repc & GLV_REPC_NO_DESC_CNT_M) >> GLV_REPC_NO_DESC_CNT_S;
4370 error_cnt = (repc & GLV_REPC_ERROR_CNT_M) >> GLV_REPC_ERROR_CNT_S;
4372 /* Clear the count by writing to the stats register */
4373 wr32(hw, GLV_REPC(vsi_num), 0);
4375 cur_stats->rx_no_desc += no_desc;
4376 cur_stats->rx_errors += error_cnt;
4380 * ice_sched_query_elem - query element information from HW
4381 * @hw: pointer to the HW struct
4382 * @node_teid: node TEID to be queried
4383 * @buf: buffer to element information
4385 * This function queries HW element information
4388 ice_sched_query_elem(struct ice_hw *hw, u32 node_teid,
4389 struct ice_aqc_get_elem *buf)
4391 u16 buf_size, num_elem_ret = 0;
4392 enum ice_status status;
4394 buf_size = sizeof(*buf);
4395 ice_memset(buf, 0, buf_size, ICE_NONDMA_MEM);
4396 buf->generic[0].node_teid = CPU_TO_LE32(node_teid);
4397 status = ice_aq_query_sched_elems(hw, 1, buf, buf_size, &num_elem_ret,
4399 if (status != ICE_SUCCESS || num_elem_ret != 1)
4400 ice_debug(hw, ICE_DBG_SCHED, "query element failed\n");
4405 * ice_get_fw_mode - returns FW mode
4406 * @hw: pointer to the HW struct
4408 enum ice_fw_modes ice_get_fw_mode(struct ice_hw *hw)
4410 #define ICE_FW_MODE_DBG_M BIT(0)
4411 #define ICE_FW_MODE_REC_M BIT(1)
4412 #define ICE_FW_MODE_ROLLBACK_M BIT(2)
4415 /* check the current FW mode */
4416 fw_mode = rd32(hw, GL_MNG_FWSM) & GL_MNG_FWSM_FW_MODES_M;
4418 if (fw_mode & ICE_FW_MODE_DBG_M)
4419 return ICE_FW_MODE_DBG;
4420 else if (fw_mode & ICE_FW_MODE_REC_M)
4421 return ICE_FW_MODE_REC;
4422 else if (fw_mode & ICE_FW_MODE_ROLLBACK_M)
4423 return ICE_FW_MODE_ROLLBACK;
4425 return ICE_FW_MODE_NORMAL;
4429 * ice_fw_supports_link_override
4430 * @hw: pointer to the hardware structure
4432 * Checks if the firmware supports link override
4434 bool ice_fw_supports_link_override(struct ice_hw *hw)
4436 /* Currently, only supported for E810 devices */
4437 if (hw->mac_type != ICE_MAC_E810)
4440 if (hw->api_maj_ver == ICE_FW_API_LINK_OVERRIDE_MAJ) {
4441 if (hw->api_min_ver > ICE_FW_API_LINK_OVERRIDE_MIN)
4443 if (hw->api_min_ver == ICE_FW_API_LINK_OVERRIDE_MIN &&
4444 hw->api_patch >= ICE_FW_API_LINK_OVERRIDE_PATCH)
4446 } else if (hw->api_maj_ver > ICE_FW_API_LINK_OVERRIDE_MAJ) {
4454 * ice_get_link_default_override
4455 * @ldo: pointer to the link default override struct
4456 * @pi: pointer to the port info struct
4458 * Gets the link default override for a port
4461 ice_get_link_default_override(struct ice_link_default_override_tlv *ldo,
4462 struct ice_port_info *pi)
4464 u16 i, tlv, tlv_len, tlv_start, buf, offset;
4465 struct ice_hw *hw = pi->hw;
4466 enum ice_status status;
4468 status = ice_get_pfa_module_tlv(hw, &tlv, &tlv_len,
4469 ICE_SR_LINK_DEFAULT_OVERRIDE_PTR);
4471 ice_debug(hw, ICE_DBG_INIT,
4472 "Failed to read link override TLV.\n");
4476 /* Each port has its own config; calculate for our port */
4477 tlv_start = tlv + pi->lport * ICE_SR_PFA_LINK_OVERRIDE_WORDS +
4478 ICE_SR_PFA_LINK_OVERRIDE_OFFSET;
4480 /* link options first */
4481 status = ice_read_sr_word(hw, tlv_start, &buf);
4483 ice_debug(hw, ICE_DBG_INIT,
4484 "Failed to read override link options.\n");
4487 ldo->options = buf & ICE_LINK_OVERRIDE_OPT_M;
4488 ldo->phy_config = (buf & ICE_LINK_OVERRIDE_PHY_CFG_M) >>
4489 ICE_LINK_OVERRIDE_PHY_CFG_S;
4491 /* link PHY config */
4492 offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_FEC_OFFSET;
4493 status = ice_read_sr_word(hw, offset, &buf);
4495 ice_debug(hw, ICE_DBG_INIT,
4496 "Failed to read override phy config.\n");
4499 ldo->fec_options = buf & ICE_LINK_OVERRIDE_FEC_OPT_M;
4502 offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_PHY_OFFSET;
4503 for (i = 0; i < ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS; i++) {
4504 status = ice_read_sr_word(hw, (offset + i), &buf);
4506 ice_debug(hw, ICE_DBG_INIT,
4507 "Failed to read override link options.\n");
4510 /* shift 16 bits at a time to fill 64 bits */
4511 ldo->phy_type_low |= ((u64)buf << (i * 16));
4514 /* PHY types high */
4515 offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_PHY_OFFSET +
4516 ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS;
4517 for (i = 0; i < ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS; i++) {
4518 status = ice_read_sr_word(hw, (offset + i), &buf);
4520 ice_debug(hw, ICE_DBG_INIT,
4521 "Failed to read override link options.\n");
4524 /* shift 16 bits at a time to fill 64 bits */
4525 ldo->phy_type_high |= ((u64)buf << (i * 16));