1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2001-2021 Intel Corporation
5 #include "ice_common.h"
7 #include "ice_adminq_cmd.h"
10 #include "ice_switch.h"
12 #define ICE_PF_RESET_WAIT_COUNT 300
15 * dump_phy_type - helper function that prints PHY type strings
16 * @hw: pointer to the HW structure
17 * @phy: 64 bit PHY type to decipher
18 * @i: bit index within phy
19 * @phy_string: string corresponding to bit i in phy
20 * @prefix: prefix string to differentiate multiple dumps
23 dump_phy_type(struct ice_hw *hw, u64 phy, u8 i, const char *phy_string,
27 ice_debug(hw, ICE_DBG_PHY, "%s: bit(%d): %s\n", prefix, i,
32 * ice_dump_phy_type_low - helper function to dump phy_type_low
33 * @hw: pointer to the HW structure
34 * @low: 64 bit value for phy_type_low
35 * @prefix: prefix string to differentiate multiple dumps
38 ice_dump_phy_type_low(struct ice_hw *hw, u64 low, const char *prefix)
40 ice_debug(hw, ICE_DBG_PHY, "%s: phy_type_low: 0x%016llx\n", prefix,
41 (unsigned long long)low);
43 dump_phy_type(hw, low, 0, "100BASE_TX", prefix);
44 dump_phy_type(hw, low, 1, "100M_SGMII", prefix);
45 dump_phy_type(hw, low, 2, "1000BASE_T", prefix);
46 dump_phy_type(hw, low, 3, "1000BASE_SX", prefix);
47 dump_phy_type(hw, low, 4, "1000BASE_LX", prefix);
48 dump_phy_type(hw, low, 5, "1000BASE_KX", prefix);
49 dump_phy_type(hw, low, 6, "1G_SGMII", prefix);
50 dump_phy_type(hw, low, 7, "2500BASE_T", prefix);
51 dump_phy_type(hw, low, 8, "2500BASE_X", prefix);
52 dump_phy_type(hw, low, 9, "2500BASE_KX", prefix);
53 dump_phy_type(hw, low, 10, "5GBASE_T", prefix);
54 dump_phy_type(hw, low, 11, "5GBASE_KR", prefix);
55 dump_phy_type(hw, low, 12, "10GBASE_T", prefix);
56 dump_phy_type(hw, low, 13, "10G_SFI_DA", prefix);
57 dump_phy_type(hw, low, 14, "10GBASE_SR", prefix);
58 dump_phy_type(hw, low, 15, "10GBASE_LR", prefix);
59 dump_phy_type(hw, low, 16, "10GBASE_KR_CR1", prefix);
60 dump_phy_type(hw, low, 17, "10G_SFI_AOC_ACC", prefix);
61 dump_phy_type(hw, low, 18, "10G_SFI_C2C", prefix);
62 dump_phy_type(hw, low, 19, "25GBASE_T", prefix);
63 dump_phy_type(hw, low, 20, "25GBASE_CR", prefix);
64 dump_phy_type(hw, low, 21, "25GBASE_CR_S", prefix);
65 dump_phy_type(hw, low, 22, "25GBASE_CR1", prefix);
66 dump_phy_type(hw, low, 23, "25GBASE_SR", prefix);
67 dump_phy_type(hw, low, 24, "25GBASE_LR", prefix);
68 dump_phy_type(hw, low, 25, "25GBASE_KR", prefix);
69 dump_phy_type(hw, low, 26, "25GBASE_KR_S", prefix);
70 dump_phy_type(hw, low, 27, "25GBASE_KR1", prefix);
71 dump_phy_type(hw, low, 28, "25G_AUI_AOC_ACC", prefix);
72 dump_phy_type(hw, low, 29, "25G_AUI_C2C", prefix);
73 dump_phy_type(hw, low, 30, "40GBASE_CR4", prefix);
74 dump_phy_type(hw, low, 31, "40GBASE_SR4", prefix);
75 dump_phy_type(hw, low, 32, "40GBASE_LR4", prefix);
76 dump_phy_type(hw, low, 33, "40GBASE_KR4", prefix);
77 dump_phy_type(hw, low, 34, "40G_XLAUI_AOC_ACC", prefix);
78 dump_phy_type(hw, low, 35, "40G_XLAUI", prefix);
79 dump_phy_type(hw, low, 36, "50GBASE_CR2", prefix);
80 dump_phy_type(hw, low, 37, "50GBASE_SR2", prefix);
81 dump_phy_type(hw, low, 38, "50GBASE_LR2", prefix);
82 dump_phy_type(hw, low, 39, "50GBASE_KR2", prefix);
83 dump_phy_type(hw, low, 40, "50G_LAUI2_AOC_ACC", prefix);
84 dump_phy_type(hw, low, 41, "50G_LAUI2", prefix);
85 dump_phy_type(hw, low, 42, "50G_AUI2_AOC_ACC", prefix);
86 dump_phy_type(hw, low, 43, "50G_AUI2", prefix);
87 dump_phy_type(hw, low, 44, "50GBASE_CP", prefix);
88 dump_phy_type(hw, low, 45, "50GBASE_SR", prefix);
89 dump_phy_type(hw, low, 46, "50GBASE_FR", prefix);
90 dump_phy_type(hw, low, 47, "50GBASE_LR", prefix);
91 dump_phy_type(hw, low, 48, "50GBASE_KR_PAM4", prefix);
92 dump_phy_type(hw, low, 49, "50G_AUI1_AOC_ACC", prefix);
93 dump_phy_type(hw, low, 50, "50G_AUI1", prefix);
94 dump_phy_type(hw, low, 51, "100GBASE_CR4", prefix);
95 dump_phy_type(hw, low, 52, "100GBASE_SR4", prefix);
96 dump_phy_type(hw, low, 53, "100GBASE_LR4", prefix);
97 dump_phy_type(hw, low, 54, "100GBASE_KR4", prefix);
98 dump_phy_type(hw, low, 55, "100G_CAUI4_AOC_ACC", prefix);
99 dump_phy_type(hw, low, 56, "100G_CAUI4", prefix);
100 dump_phy_type(hw, low, 57, "100G_AUI4_AOC_ACC", prefix);
101 dump_phy_type(hw, low, 58, "100G_AUI4", prefix);
102 dump_phy_type(hw, low, 59, "100GBASE_CR_PAM4", prefix);
103 dump_phy_type(hw, low, 60, "100GBASE_KR_PAM4", prefix);
104 dump_phy_type(hw, low, 61, "100GBASE_CP2", prefix);
105 dump_phy_type(hw, low, 62, "100GBASE_SR2", prefix);
106 dump_phy_type(hw, low, 63, "100GBASE_DR", prefix);
110 * ice_dump_phy_type_high - helper function to dump phy_type_high
111 * @hw: pointer to the HW structure
112 * @high: 64 bit value for phy_type_high
113 * @prefix: prefix string to differentiate multiple dumps
116 ice_dump_phy_type_high(struct ice_hw *hw, u64 high, const char *prefix)
118 ice_debug(hw, ICE_DBG_PHY, "%s: phy_type_high: 0x%016llx\n", prefix,
119 (unsigned long long)high);
121 dump_phy_type(hw, high, 0, "100GBASE_KR2_PAM4", prefix);
122 dump_phy_type(hw, high, 1, "100G_CAUI2_AOC_ACC", prefix);
123 dump_phy_type(hw, high, 2, "100G_CAUI2", prefix);
124 dump_phy_type(hw, high, 3, "100G_AUI2_AOC_ACC", prefix);
125 dump_phy_type(hw, high, 4, "100G_AUI2", prefix);
129 * ice_set_mac_type - Sets MAC type
130 * @hw: pointer to the HW structure
132 * This function sets the MAC type of the adapter based on the
133 * vendor ID and device ID stored in the HW structure.
135 static enum ice_status ice_set_mac_type(struct ice_hw *hw)
137 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
139 if (hw->vendor_id != ICE_INTEL_VENDOR_ID)
140 return ICE_ERR_DEVICE_NOT_SUPPORTED;
142 switch (hw->device_id) {
143 case ICE_DEV_ID_E810C_BACKPLANE:
144 case ICE_DEV_ID_E810C_QSFP:
145 case ICE_DEV_ID_E810C_SFP:
146 case ICE_DEV_ID_E810_XXV_BACKPLANE:
147 case ICE_DEV_ID_E810_XXV_QSFP:
148 case ICE_DEV_ID_E810_XXV_SFP:
149 hw->mac_type = ICE_MAC_E810;
151 case ICE_DEV_ID_E822C_10G_BASE_T:
152 case ICE_DEV_ID_E822C_BACKPLANE:
153 case ICE_DEV_ID_E822C_QSFP:
154 case ICE_DEV_ID_E822C_SFP:
155 case ICE_DEV_ID_E822C_SGMII:
156 case ICE_DEV_ID_E822L_10G_BASE_T:
157 case ICE_DEV_ID_E822L_BACKPLANE:
158 case ICE_DEV_ID_E822L_SFP:
159 case ICE_DEV_ID_E822L_SGMII:
160 case ICE_DEV_ID_E823L_10G_BASE_T:
161 case ICE_DEV_ID_E823L_1GBE:
162 case ICE_DEV_ID_E823L_BACKPLANE:
163 case ICE_DEV_ID_E823L_QSFP:
164 case ICE_DEV_ID_E823L_SFP:
165 case ICE_DEV_ID_E823C_10G_BASE_T:
166 case ICE_DEV_ID_E823C_BACKPLANE:
167 case ICE_DEV_ID_E823C_QSFP:
168 case ICE_DEV_ID_E823C_SFP:
169 case ICE_DEV_ID_E823C_SGMII:
170 hw->mac_type = ICE_MAC_GENERIC;
173 hw->mac_type = ICE_MAC_UNKNOWN;
177 ice_debug(hw, ICE_DBG_INIT, "mac_type: %d\n", hw->mac_type);
183 * @hw: pointer to the hardware structure
185 * returns true if mac_type is ICE_MAC_GENERIC, false if not
187 bool ice_is_generic_mac(struct ice_hw *hw)
189 return hw->mac_type == ICE_MAC_GENERIC;
194 * @hw: pointer to the hardware structure
196 * returns true if the device is E810 based, false if not.
198 bool ice_is_e810(struct ice_hw *hw)
200 return hw->mac_type == ICE_MAC_E810;
205 * @hw: pointer to the hardware structure
207 * returns true if the device is E810T based, false if not.
209 bool ice_is_e810t(struct ice_hw *hw)
211 return (hw->device_id == ICE_DEV_ID_E810C_SFP &&
212 hw->subsystem_device_id == ICE_SUBDEV_ID_E810T);
216 * ice_clear_pf_cfg - Clear PF configuration
217 * @hw: pointer to the hardware structure
219 * Clears any existing PF configuration (VSIs, VSI lists, switch rules, port
220 * configuration, flow director filters, etc.).
222 enum ice_status ice_clear_pf_cfg(struct ice_hw *hw)
224 struct ice_aq_desc desc;
226 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pf_cfg);
228 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
232 * ice_aq_manage_mac_read - manage MAC address read command
233 * @hw: pointer to the HW struct
234 * @buf: a virtual buffer to hold the manage MAC read response
235 * @buf_size: Size of the virtual buffer
236 * @cd: pointer to command details structure or NULL
238 * This function is used to return per PF station MAC address (0x0107).
239 * NOTE: Upon successful completion of this command, MAC address information
240 * is returned in user specified buffer. Please interpret user specified
241 * buffer as "manage_mac_read" response.
242 * Response such as various MAC addresses are stored in HW struct (port.mac)
243 * ice_discover_dev_caps is expected to be called before this function is
246 static enum ice_status
247 ice_aq_manage_mac_read(struct ice_hw *hw, void *buf, u16 buf_size,
248 struct ice_sq_cd *cd)
250 struct ice_aqc_manage_mac_read_resp *resp;
251 struct ice_aqc_manage_mac_read *cmd;
252 struct ice_aq_desc desc;
253 enum ice_status status;
257 cmd = &desc.params.mac_read;
259 if (buf_size < sizeof(*resp))
260 return ICE_ERR_BUF_TOO_SHORT;
262 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_read);
264 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);
268 resp = (struct ice_aqc_manage_mac_read_resp *)buf;
269 flags = LE16_TO_CPU(cmd->flags) & ICE_AQC_MAN_MAC_READ_M;
271 if (!(flags & ICE_AQC_MAN_MAC_LAN_ADDR_VALID)) {
272 ice_debug(hw, ICE_DBG_LAN, "got invalid MAC address\n");
276 /* A single port can report up to two (LAN and WoL) addresses */
277 for (i = 0; i < cmd->num_addr; i++)
278 if (resp[i].addr_type == ICE_AQC_MAN_MAC_ADDR_TYPE_LAN) {
279 ice_memcpy(hw->port_info->mac.lan_addr,
280 resp[i].mac_addr, ETH_ALEN,
282 ice_memcpy(hw->port_info->mac.perm_addr,
284 ETH_ALEN, ICE_DMA_TO_NONDMA);
291 * ice_aq_get_phy_caps - returns PHY capabilities
292 * @pi: port information structure
293 * @qual_mods: report qualified modules
294 * @report_mode: report mode capabilities
295 * @pcaps: structure for PHY capabilities to be filled
296 * @cd: pointer to command details structure or NULL
298 * Returns the various PHY capabilities supported on the Port (0x0600)
301 ice_aq_get_phy_caps(struct ice_port_info *pi, bool qual_mods, u8 report_mode,
302 struct ice_aqc_get_phy_caps_data *pcaps,
303 struct ice_sq_cd *cd)
305 struct ice_aqc_get_phy_caps *cmd;
306 u16 pcaps_size = sizeof(*pcaps);
307 struct ice_aq_desc desc;
308 enum ice_status status;
312 cmd = &desc.params.get_phy;
314 if (!pcaps || (report_mode & ~ICE_AQC_REPORT_MODE_M) || !pi)
315 return ICE_ERR_PARAM;
318 if (report_mode == ICE_AQC_REPORT_DFLT_CFG &&
319 !ice_fw_supports_report_dflt_cfg(hw))
320 return ICE_ERR_PARAM;
322 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_phy_caps);
325 cmd->param0 |= CPU_TO_LE16(ICE_AQC_GET_PHY_RQM);
327 cmd->param0 |= CPU_TO_LE16(report_mode);
328 status = ice_aq_send_cmd(hw, &desc, pcaps, pcaps_size, cd);
330 ice_debug(hw, ICE_DBG_LINK, "get phy caps dump\n");
332 if (report_mode == ICE_AQC_REPORT_TOPO_CAP_MEDIA)
333 prefix = "phy_caps_media";
334 else if (report_mode == ICE_AQC_REPORT_TOPO_CAP_NO_MEDIA)
335 prefix = "phy_caps_no_media";
336 else if (report_mode == ICE_AQC_REPORT_ACTIVE_CFG)
337 prefix = "phy_caps_active";
338 else if (report_mode == ICE_AQC_REPORT_DFLT_CFG)
339 prefix = "phy_caps_default";
341 prefix = "phy_caps_invalid";
343 ice_dump_phy_type_low(hw, LE64_TO_CPU(pcaps->phy_type_low), prefix);
344 ice_dump_phy_type_high(hw, LE64_TO_CPU(pcaps->phy_type_high), prefix);
346 ice_debug(hw, ICE_DBG_LINK, "%s: report_mode = 0x%x\n",
347 prefix, report_mode);
348 ice_debug(hw, ICE_DBG_LINK, "%s: caps = 0x%x\n", prefix, pcaps->caps);
349 ice_debug(hw, ICE_DBG_LINK, "%s: low_power_ctrl_an = 0x%x\n", prefix,
350 pcaps->low_power_ctrl_an);
351 ice_debug(hw, ICE_DBG_LINK, "%s: eee_cap = 0x%x\n", prefix,
353 ice_debug(hw, ICE_DBG_LINK, "%s: eeer_value = 0x%x\n", prefix,
355 ice_debug(hw, ICE_DBG_LINK, "%s: link_fec_options = 0x%x\n", prefix,
356 pcaps->link_fec_options);
357 ice_debug(hw, ICE_DBG_LINK, "%s: module_compliance_enforcement = 0x%x\n",
358 prefix, pcaps->module_compliance_enforcement);
359 ice_debug(hw, ICE_DBG_LINK, "%s: extended_compliance_code = 0x%x\n",
360 prefix, pcaps->extended_compliance_code);
361 ice_debug(hw, ICE_DBG_LINK, "%s: module_type[0] = 0x%x\n", prefix,
362 pcaps->module_type[0]);
363 ice_debug(hw, ICE_DBG_LINK, "%s: module_type[1] = 0x%x\n", prefix,
364 pcaps->module_type[1]);
365 ice_debug(hw, ICE_DBG_LINK, "%s: module_type[2] = 0x%x\n", prefix,
366 pcaps->module_type[2]);
368 if (status == ICE_SUCCESS && report_mode == ICE_AQC_REPORT_TOPO_CAP_MEDIA) {
369 pi->phy.phy_type_low = LE64_TO_CPU(pcaps->phy_type_low);
370 pi->phy.phy_type_high = LE64_TO_CPU(pcaps->phy_type_high);
371 ice_memcpy(pi->phy.link_info.module_type, &pcaps->module_type,
372 sizeof(pi->phy.link_info.module_type),
373 ICE_NONDMA_TO_NONDMA);
380 * ice_aq_get_link_topo_handle - get link topology node return status
381 * @pi: port information structure
382 * @node_type: requested node type
383 * @cd: pointer to command details structure or NULL
385 * Get link topology node return status for specified node type (0x06E0)
387 * Node type cage can be used to determine if cage is present. If AQC
388 * returns error (ENOENT), then no cage present. If no cage present, then
389 * connection type is backplane or BASE-T.
391 static enum ice_status
392 ice_aq_get_link_topo_handle(struct ice_port_info *pi, u8 node_type,
393 struct ice_sq_cd *cd)
395 struct ice_aqc_get_link_topo *cmd;
396 struct ice_aq_desc desc;
398 cmd = &desc.params.get_link_topo;
400 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_topo);
402 cmd->addr.topo_params.node_type_ctx =
403 (ICE_AQC_LINK_TOPO_NODE_CTX_PORT <<
404 ICE_AQC_LINK_TOPO_NODE_CTX_S);
407 cmd->addr.topo_params.node_type_ctx |=
408 (ICE_AQC_LINK_TOPO_NODE_TYPE_M & node_type);
410 return ice_aq_send_cmd(pi->hw, &desc, NULL, 0, cd);
414 * ice_is_media_cage_present
415 * @pi: port information structure
417 * Returns true if media cage is present, else false. If no cage, then
418 * media type is backplane or BASE-T.
420 static bool ice_is_media_cage_present(struct ice_port_info *pi)
422 /* Node type cage can be used to determine if cage is present. If AQC
423 * returns error (ENOENT), then no cage present. If no cage present then
424 * connection type is backplane or BASE-T.
426 return !ice_aq_get_link_topo_handle(pi,
427 ICE_AQC_LINK_TOPO_NODE_TYPE_CAGE,
432 * ice_get_media_type - Gets media type
433 * @pi: port information structure
435 static enum ice_media_type ice_get_media_type(struct ice_port_info *pi)
437 struct ice_link_status *hw_link_info;
440 return ICE_MEDIA_UNKNOWN;
442 hw_link_info = &pi->phy.link_info;
443 if (hw_link_info->phy_type_low && hw_link_info->phy_type_high)
444 /* If more than one media type is selected, report unknown */
445 return ICE_MEDIA_UNKNOWN;
447 if (hw_link_info->phy_type_low) {
448 /* 1G SGMII is a special case where some DA cable PHYs
449 * may show this as an option when it really shouldn't
450 * be since SGMII is meant to be between a MAC and a PHY
451 * in a backplane. Try to detect this case and handle it
453 if (hw_link_info->phy_type_low == ICE_PHY_TYPE_LOW_1G_SGMII &&
454 (hw_link_info->module_type[ICE_AQC_MOD_TYPE_IDENT] ==
455 ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_ACTIVE ||
456 hw_link_info->module_type[ICE_AQC_MOD_TYPE_IDENT] ==
457 ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_PASSIVE))
460 switch (hw_link_info->phy_type_low) {
461 case ICE_PHY_TYPE_LOW_1000BASE_SX:
462 case ICE_PHY_TYPE_LOW_1000BASE_LX:
463 case ICE_PHY_TYPE_LOW_10GBASE_SR:
464 case ICE_PHY_TYPE_LOW_10GBASE_LR:
465 case ICE_PHY_TYPE_LOW_10G_SFI_C2C:
466 case ICE_PHY_TYPE_LOW_25GBASE_SR:
467 case ICE_PHY_TYPE_LOW_25GBASE_LR:
468 case ICE_PHY_TYPE_LOW_40GBASE_SR4:
469 case ICE_PHY_TYPE_LOW_40GBASE_LR4:
470 case ICE_PHY_TYPE_LOW_50GBASE_SR2:
471 case ICE_PHY_TYPE_LOW_50GBASE_LR2:
472 case ICE_PHY_TYPE_LOW_50GBASE_SR:
473 case ICE_PHY_TYPE_LOW_50GBASE_FR:
474 case ICE_PHY_TYPE_LOW_50GBASE_LR:
475 case ICE_PHY_TYPE_LOW_100GBASE_SR4:
476 case ICE_PHY_TYPE_LOW_100GBASE_LR4:
477 case ICE_PHY_TYPE_LOW_100GBASE_SR2:
478 case ICE_PHY_TYPE_LOW_100GBASE_DR:
479 return ICE_MEDIA_FIBER;
480 case ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC:
481 case ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC:
482 case ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC:
483 case ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC:
484 case ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC:
485 case ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC:
486 case ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC:
487 case ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC:
488 return ICE_MEDIA_FIBER;
489 case ICE_PHY_TYPE_LOW_100BASE_TX:
490 case ICE_PHY_TYPE_LOW_1000BASE_T:
491 case ICE_PHY_TYPE_LOW_2500BASE_T:
492 case ICE_PHY_TYPE_LOW_5GBASE_T:
493 case ICE_PHY_TYPE_LOW_10GBASE_T:
494 case ICE_PHY_TYPE_LOW_25GBASE_T:
495 return ICE_MEDIA_BASET;
496 case ICE_PHY_TYPE_LOW_10G_SFI_DA:
497 case ICE_PHY_TYPE_LOW_25GBASE_CR:
498 case ICE_PHY_TYPE_LOW_25GBASE_CR_S:
499 case ICE_PHY_TYPE_LOW_25GBASE_CR1:
500 case ICE_PHY_TYPE_LOW_40GBASE_CR4:
501 case ICE_PHY_TYPE_LOW_50GBASE_CR2:
502 case ICE_PHY_TYPE_LOW_50GBASE_CP:
503 case ICE_PHY_TYPE_LOW_100GBASE_CR4:
504 case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4:
505 case ICE_PHY_TYPE_LOW_100GBASE_CP2:
507 case ICE_PHY_TYPE_LOW_25G_AUI_C2C:
508 case ICE_PHY_TYPE_LOW_40G_XLAUI:
509 case ICE_PHY_TYPE_LOW_50G_LAUI2:
510 case ICE_PHY_TYPE_LOW_50G_AUI2:
511 case ICE_PHY_TYPE_LOW_50G_AUI1:
512 case ICE_PHY_TYPE_LOW_100G_AUI4:
513 case ICE_PHY_TYPE_LOW_100G_CAUI4:
514 if (ice_is_media_cage_present(pi))
515 return ICE_MEDIA_AUI;
517 case ICE_PHY_TYPE_LOW_1000BASE_KX:
518 case ICE_PHY_TYPE_LOW_2500BASE_KX:
519 case ICE_PHY_TYPE_LOW_2500BASE_X:
520 case ICE_PHY_TYPE_LOW_5GBASE_KR:
521 case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1:
522 case ICE_PHY_TYPE_LOW_25GBASE_KR:
523 case ICE_PHY_TYPE_LOW_25GBASE_KR1:
524 case ICE_PHY_TYPE_LOW_25GBASE_KR_S:
525 case ICE_PHY_TYPE_LOW_40GBASE_KR4:
526 case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4:
527 case ICE_PHY_TYPE_LOW_50GBASE_KR2:
528 case ICE_PHY_TYPE_LOW_100GBASE_KR4:
529 case ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4:
530 return ICE_MEDIA_BACKPLANE;
533 switch (hw_link_info->phy_type_high) {
534 case ICE_PHY_TYPE_HIGH_100G_AUI2:
535 case ICE_PHY_TYPE_HIGH_100G_CAUI2:
536 if (ice_is_media_cage_present(pi))
537 return ICE_MEDIA_AUI;
539 case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4:
540 return ICE_MEDIA_BACKPLANE;
541 case ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC:
542 case ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC:
543 return ICE_MEDIA_FIBER;
546 return ICE_MEDIA_UNKNOWN;
550 * ice_aq_get_link_info
551 * @pi: port information structure
552 * @ena_lse: enable/disable LinkStatusEvent reporting
553 * @link: pointer to link status structure - optional
554 * @cd: pointer to command details structure or NULL
556 * Get Link Status (0x607). Returns the link status of the adapter.
559 ice_aq_get_link_info(struct ice_port_info *pi, bool ena_lse,
560 struct ice_link_status *link, struct ice_sq_cd *cd)
562 struct ice_aqc_get_link_status_data link_data = { 0 };
563 struct ice_aqc_get_link_status *resp;
564 struct ice_link_status *li_old, *li;
565 enum ice_media_type *hw_media_type;
566 struct ice_fc_info *hw_fc_info;
567 bool tx_pause, rx_pause;
568 struct ice_aq_desc desc;
569 enum ice_status status;
574 return ICE_ERR_PARAM;
576 li_old = &pi->phy.link_info_old;
577 hw_media_type = &pi->phy.media_type;
578 li = &pi->phy.link_info;
579 hw_fc_info = &pi->fc;
581 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_status);
582 cmd_flags = (ena_lse) ? ICE_AQ_LSE_ENA : ICE_AQ_LSE_DIS;
583 resp = &desc.params.get_link_status;
584 resp->cmd_flags = CPU_TO_LE16(cmd_flags);
585 resp->lport_num = pi->lport;
587 status = ice_aq_send_cmd(hw, &desc, &link_data, sizeof(link_data), cd);
589 if (status != ICE_SUCCESS)
592 /* save off old link status information */
595 /* update current link status information */
596 li->link_speed = LE16_TO_CPU(link_data.link_speed);
597 li->phy_type_low = LE64_TO_CPU(link_data.phy_type_low);
598 li->phy_type_high = LE64_TO_CPU(link_data.phy_type_high);
599 *hw_media_type = ice_get_media_type(pi);
600 li->link_info = link_data.link_info;
601 li->link_cfg_err = link_data.link_cfg_err;
602 li->an_info = link_data.an_info;
603 li->ext_info = link_data.ext_info;
604 li->max_frame_size = LE16_TO_CPU(link_data.max_frame_size);
605 li->fec_info = link_data.cfg & ICE_AQ_FEC_MASK;
606 li->topo_media_conflict = link_data.topo_media_conflict;
607 li->pacing = link_data.cfg & (ICE_AQ_CFG_PACING_M |
608 ICE_AQ_CFG_PACING_TYPE_M);
611 tx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_TX);
612 rx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_RX);
613 if (tx_pause && rx_pause)
614 hw_fc_info->current_mode = ICE_FC_FULL;
616 hw_fc_info->current_mode = ICE_FC_TX_PAUSE;
618 hw_fc_info->current_mode = ICE_FC_RX_PAUSE;
620 hw_fc_info->current_mode = ICE_FC_NONE;
622 li->lse_ena = !!(resp->cmd_flags & CPU_TO_LE16(ICE_AQ_LSE_IS_ENABLED));
624 ice_debug(hw, ICE_DBG_LINK, "get link info\n");
625 ice_debug(hw, ICE_DBG_LINK, " link_speed = 0x%x\n", li->link_speed);
626 ice_debug(hw, ICE_DBG_LINK, " phy_type_low = 0x%llx\n",
627 (unsigned long long)li->phy_type_low);
628 ice_debug(hw, ICE_DBG_LINK, " phy_type_high = 0x%llx\n",
629 (unsigned long long)li->phy_type_high);
630 ice_debug(hw, ICE_DBG_LINK, " media_type = 0x%x\n", *hw_media_type);
631 ice_debug(hw, ICE_DBG_LINK, " link_info = 0x%x\n", li->link_info);
632 ice_debug(hw, ICE_DBG_LINK, " link_cfg_err = 0x%x\n", li->link_cfg_err);
633 ice_debug(hw, ICE_DBG_LINK, " an_info = 0x%x\n", li->an_info);
634 ice_debug(hw, ICE_DBG_LINK, " ext_info = 0x%x\n", li->ext_info);
635 ice_debug(hw, ICE_DBG_LINK, " fec_info = 0x%x\n", li->fec_info);
636 ice_debug(hw, ICE_DBG_LINK, " lse_ena = 0x%x\n", li->lse_ena);
637 ice_debug(hw, ICE_DBG_LINK, " max_frame = 0x%x\n",
639 ice_debug(hw, ICE_DBG_LINK, " pacing = 0x%x\n", li->pacing);
641 /* save link status information */
645 /* flag cleared so calling functions don't call AQ again */
646 pi->phy.get_link_info = false;
652 * ice_fill_tx_timer_and_fc_thresh
653 * @hw: pointer to the HW struct
654 * @cmd: pointer to MAC cfg structure
656 * Add Tx timer and FC refresh threshold info to Set MAC Config AQ command
660 ice_fill_tx_timer_and_fc_thresh(struct ice_hw *hw,
661 struct ice_aqc_set_mac_cfg *cmd)
663 u16 fc_thres_val, tx_timer_val;
666 /* We read back the transmit timer and fc threshold value of
667 * LFC. Thus, we will use index =
668 * PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX.
670 * Also, because we are opearating on transmit timer and fc
671 * threshold of LFC, we don't turn on any bit in tx_tmr_priority
673 #define IDX_OF_LFC PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX
675 /* Retrieve the transmit timer */
676 val = rd32(hw, PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(IDX_OF_LFC));
678 PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_HSEC_CTL_TX_PAUSE_QUANTA_M;
679 cmd->tx_tmr_value = CPU_TO_LE16(tx_timer_val);
681 /* Retrieve the fc threshold */
682 val = rd32(hw, PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(IDX_OF_LFC));
683 fc_thres_val = val & PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_M;
685 cmd->fc_refresh_threshold = CPU_TO_LE16(fc_thres_val);
690 * @hw: pointer to the HW struct
691 * @max_frame_size: Maximum Frame Size to be supported
692 * @cd: pointer to command details structure or NULL
694 * Set MAC configuration (0x0603)
697 ice_aq_set_mac_cfg(struct ice_hw *hw, u16 max_frame_size, struct ice_sq_cd *cd)
699 struct ice_aqc_set_mac_cfg *cmd;
700 struct ice_aq_desc desc;
702 cmd = &desc.params.set_mac_cfg;
704 if (max_frame_size == 0)
705 return ICE_ERR_PARAM;
707 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_mac_cfg);
709 cmd->max_frame_size = CPU_TO_LE16(max_frame_size);
711 ice_fill_tx_timer_and_fc_thresh(hw, cmd);
713 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
717 * ice_init_fltr_mgmt_struct - initializes filter management list and locks
718 * @hw: pointer to the HW struct
720 enum ice_status ice_init_fltr_mgmt_struct(struct ice_hw *hw)
722 struct ice_switch_info *sw;
723 enum ice_status status;
725 hw->switch_info = (struct ice_switch_info *)
726 ice_malloc(hw, sizeof(*hw->switch_info));
728 sw = hw->switch_info;
731 return ICE_ERR_NO_MEMORY;
733 INIT_LIST_HEAD(&sw->vsi_list_map_head);
734 sw->prof_res_bm_init = 0;
736 status = ice_init_def_sw_recp(hw, &hw->switch_info->recp_list);
738 ice_free(hw, hw->switch_info);
745 * ice_cleanup_fltr_mgmt_single - clears single filter mngt struct
746 * @hw: pointer to the HW struct
747 * @sw: pointer to switch info struct for which function clears filters
750 ice_cleanup_fltr_mgmt_single(struct ice_hw *hw, struct ice_switch_info *sw)
752 struct ice_vsi_list_map_info *v_pos_map;
753 struct ice_vsi_list_map_info *v_tmp_map;
754 struct ice_sw_recipe *recps;
760 LIST_FOR_EACH_ENTRY_SAFE(v_pos_map, v_tmp_map, &sw->vsi_list_map_head,
761 ice_vsi_list_map_info, list_entry) {
762 LIST_DEL(&v_pos_map->list_entry);
763 ice_free(hw, v_pos_map);
765 recps = sw->recp_list;
766 for (i = 0; i < ICE_MAX_NUM_RECIPES; i++) {
767 struct ice_recp_grp_entry *rg_entry, *tmprg_entry;
769 recps[i].root_rid = i;
770 LIST_FOR_EACH_ENTRY_SAFE(rg_entry, tmprg_entry,
771 &recps[i].rg_list, ice_recp_grp_entry,
773 LIST_DEL(&rg_entry->l_entry);
774 ice_free(hw, rg_entry);
777 if (recps[i].adv_rule) {
778 struct ice_adv_fltr_mgmt_list_entry *tmp_entry;
779 struct ice_adv_fltr_mgmt_list_entry *lst_itr;
781 ice_destroy_lock(&recps[i].filt_rule_lock);
782 LIST_FOR_EACH_ENTRY_SAFE(lst_itr, tmp_entry,
783 &recps[i].filt_rules,
784 ice_adv_fltr_mgmt_list_entry,
786 LIST_DEL(&lst_itr->list_entry);
787 ice_free(hw, lst_itr->lkups);
788 ice_free(hw, lst_itr);
791 struct ice_fltr_mgmt_list_entry *lst_itr, *tmp_entry;
793 ice_destroy_lock(&recps[i].filt_rule_lock);
794 LIST_FOR_EACH_ENTRY_SAFE(lst_itr, tmp_entry,
795 &recps[i].filt_rules,
796 ice_fltr_mgmt_list_entry,
798 LIST_DEL(&lst_itr->list_entry);
799 ice_free(hw, lst_itr);
802 if (recps[i].root_buf)
803 ice_free(hw, recps[i].root_buf);
805 ice_rm_sw_replay_rule_info(hw, sw);
806 ice_free(hw, sw->recp_list);
811 * ice_cleanup_fltr_mgmt_struct - cleanup filter management list and locks
812 * @hw: pointer to the HW struct
814 void ice_cleanup_fltr_mgmt_struct(struct ice_hw *hw)
816 ice_cleanup_fltr_mgmt_single(hw, hw->switch_info);
820 * ice_get_itr_intrl_gran
821 * @hw: pointer to the HW struct
823 * Determines the ITR/INTRL granularities based on the maximum aggregate
824 * bandwidth according to the device's configuration during power-on.
826 static void ice_get_itr_intrl_gran(struct ice_hw *hw)
828 u8 max_agg_bw = (rd32(hw, GL_PWR_MODE_CTL) &
829 GL_PWR_MODE_CTL_CAR_MAX_BW_M) >>
830 GL_PWR_MODE_CTL_CAR_MAX_BW_S;
832 switch (max_agg_bw) {
833 case ICE_MAX_AGG_BW_200G:
834 case ICE_MAX_AGG_BW_100G:
835 case ICE_MAX_AGG_BW_50G:
836 hw->itr_gran = ICE_ITR_GRAN_ABOVE_25;
837 hw->intrl_gran = ICE_INTRL_GRAN_ABOVE_25;
839 case ICE_MAX_AGG_BW_25G:
840 hw->itr_gran = ICE_ITR_GRAN_MAX_25;
841 hw->intrl_gran = ICE_INTRL_GRAN_MAX_25;
847 * ice_print_rollback_msg - print FW rollback message
848 * @hw: pointer to the hardware structure
850 void ice_print_rollback_msg(struct ice_hw *hw)
852 char nvm_str[ICE_NVM_VER_LEN] = { 0 };
853 struct ice_orom_info *orom;
854 struct ice_nvm_info *nvm;
856 orom = &hw->flash.orom;
857 nvm = &hw->flash.nvm;
859 SNPRINTF(nvm_str, sizeof(nvm_str), "%x.%02x 0x%x %d.%d.%d",
860 nvm->major, nvm->minor, nvm->eetrack, orom->major,
861 orom->build, orom->patch);
863 "Firmware rollback mode detected. Current version is NVM: %s, FW: %d.%d. Device may exhibit limited functionality. Refer to the Intel(R) Ethernet Adapters and Devices User Guide for details on firmware rollback mode\n",
864 nvm_str, hw->fw_maj_ver, hw->fw_min_ver);
868 * ice_init_hw - main hardware initialization routine
869 * @hw: pointer to the hardware structure
871 enum ice_status ice_init_hw(struct ice_hw *hw)
873 struct ice_aqc_get_phy_caps_data *pcaps;
874 enum ice_status status;
878 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
880 /* Set MAC type based on DeviceID */
881 status = ice_set_mac_type(hw);
885 hw->pf_id = (u8)(rd32(hw, PF_FUNC_RID) &
886 PF_FUNC_RID_FUNCTION_NUMBER_M) >>
887 PF_FUNC_RID_FUNCTION_NUMBER_S;
889 status = ice_reset(hw, ICE_RESET_PFR);
893 ice_get_itr_intrl_gran(hw);
895 status = ice_create_all_ctrlq(hw);
897 goto err_unroll_cqinit;
899 status = ice_init_nvm(hw);
901 goto err_unroll_cqinit;
903 if (ice_get_fw_mode(hw) == ICE_FW_MODE_ROLLBACK)
904 ice_print_rollback_msg(hw);
906 status = ice_clear_pf_cfg(hw);
908 goto err_unroll_cqinit;
910 /* Set bit to enable Flow Director filters */
911 wr32(hw, PFQF_FD_ENA, PFQF_FD_ENA_FD_ENA_M);
912 INIT_LIST_HEAD(&hw->fdir_list_head);
914 ice_clear_pxe_mode(hw);
916 status = ice_get_caps(hw);
918 goto err_unroll_cqinit;
920 hw->port_info = (struct ice_port_info *)
921 ice_malloc(hw, sizeof(*hw->port_info));
922 if (!hw->port_info) {
923 status = ICE_ERR_NO_MEMORY;
924 goto err_unroll_cqinit;
927 /* set the back pointer to HW */
928 hw->port_info->hw = hw;
930 /* Initialize port_info struct with switch configuration data */
931 status = ice_get_initial_sw_cfg(hw);
933 goto err_unroll_alloc;
936 /* Query the allocated resources for Tx scheduler */
937 status = ice_sched_query_res_alloc(hw);
939 ice_debug(hw, ICE_DBG_SCHED, "Failed to get scheduler allocated resources\n");
940 goto err_unroll_alloc;
942 ice_sched_get_psm_clk_freq(hw);
944 /* Initialize port_info struct with scheduler data */
945 status = ice_sched_init_port(hw->port_info);
947 goto err_unroll_sched;
948 pcaps = (struct ice_aqc_get_phy_caps_data *)
949 ice_malloc(hw, sizeof(*pcaps));
951 status = ICE_ERR_NO_MEMORY;
952 goto err_unroll_sched;
955 /* Initialize port_info struct with PHY capabilities */
956 status = ice_aq_get_phy_caps(hw->port_info, false,
957 ICE_AQC_REPORT_TOPO_CAP_MEDIA, pcaps, NULL);
960 ice_warn(hw, "Get PHY capabilities failed status = %d, continuing anyway\n",
963 /* Initialize port_info struct with link information */
964 status = ice_aq_get_link_info(hw->port_info, false, NULL, NULL);
966 goto err_unroll_sched;
967 /* need a valid SW entry point to build a Tx tree */
968 if (!hw->sw_entry_point_layer) {
969 ice_debug(hw, ICE_DBG_SCHED, "invalid sw entry point\n");
970 status = ICE_ERR_CFG;
971 goto err_unroll_sched;
973 INIT_LIST_HEAD(&hw->agg_list);
974 /* Initialize max burst size */
975 if (!hw->max_burst_size)
976 ice_cfg_rl_burst_size(hw, ICE_SCHED_DFLT_BURST_SIZE);
977 status = ice_init_fltr_mgmt_struct(hw);
979 goto err_unroll_sched;
981 /* Get MAC information */
982 /* A single port can report up to two (LAN and WoL) addresses */
983 mac_buf = ice_calloc(hw, 2,
984 sizeof(struct ice_aqc_manage_mac_read_resp));
985 mac_buf_len = 2 * sizeof(struct ice_aqc_manage_mac_read_resp);
988 status = ICE_ERR_NO_MEMORY;
989 goto err_unroll_fltr_mgmt_struct;
992 status = ice_aq_manage_mac_read(hw, mac_buf, mac_buf_len, NULL);
993 ice_free(hw, mac_buf);
996 goto err_unroll_fltr_mgmt_struct;
997 /* Obtain counter base index which would be used by flow director */
998 status = ice_alloc_fd_res_cntr(hw, &hw->fd_ctr_base);
1000 goto err_unroll_fltr_mgmt_struct;
1001 status = ice_init_hw_tbls(hw);
1003 goto err_unroll_fltr_mgmt_struct;
1004 ice_init_lock(&hw->tnl_lock);
1008 err_unroll_fltr_mgmt_struct:
1009 ice_cleanup_fltr_mgmt_struct(hw);
1011 ice_sched_cleanup_all(hw);
1013 ice_free(hw, hw->port_info);
1014 hw->port_info = NULL;
1016 ice_destroy_all_ctrlq(hw);
1021 * ice_deinit_hw - unroll initialization operations done by ice_init_hw
1022 * @hw: pointer to the hardware structure
1024 * This should be called only during nominal operation, not as a result of
1025 * ice_init_hw() failing since ice_init_hw() will take care of unrolling
1026 * applicable initializations if it fails for any reason.
1028 void ice_deinit_hw(struct ice_hw *hw)
1030 ice_free_fd_res_cntr(hw, hw->fd_ctr_base);
1031 ice_cleanup_fltr_mgmt_struct(hw);
1033 ice_sched_cleanup_all(hw);
1034 ice_sched_clear_agg(hw);
1036 ice_free_hw_tbls(hw);
1037 ice_destroy_lock(&hw->tnl_lock);
1039 if (hw->port_info) {
1040 ice_free(hw, hw->port_info);
1041 hw->port_info = NULL;
1044 ice_destroy_all_ctrlq(hw);
1046 /* Clear VSI contexts if not already cleared */
1047 ice_clear_all_vsi_ctx(hw);
1051 * ice_check_reset - Check to see if a global reset is complete
1052 * @hw: pointer to the hardware structure
1054 enum ice_status ice_check_reset(struct ice_hw *hw)
1056 u32 cnt, reg = 0, grst_timeout, uld_mask;
1058 /* Poll for Device Active state in case a recent CORER, GLOBR,
1059 * or EMPR has occurred. The grst delay value is in 100ms units.
1060 * Add 1sec for outstanding AQ commands that can take a long time.
1062 grst_timeout = ((rd32(hw, GLGEN_RSTCTL) & GLGEN_RSTCTL_GRSTDEL_M) >>
1063 GLGEN_RSTCTL_GRSTDEL_S) + 10;
1065 for (cnt = 0; cnt < grst_timeout; cnt++) {
1066 ice_msec_delay(100, true);
1067 reg = rd32(hw, GLGEN_RSTAT);
1068 if (!(reg & GLGEN_RSTAT_DEVSTATE_M))
1072 if (cnt == grst_timeout) {
1073 ice_debug(hw, ICE_DBG_INIT, "Global reset polling failed to complete.\n");
1074 return ICE_ERR_RESET_FAILED;
1077 #define ICE_RESET_DONE_MASK (GLNVM_ULD_PCIER_DONE_M |\
1078 GLNVM_ULD_PCIER_DONE_1_M |\
1079 GLNVM_ULD_CORER_DONE_M |\
1080 GLNVM_ULD_GLOBR_DONE_M |\
1081 GLNVM_ULD_POR_DONE_M |\
1082 GLNVM_ULD_POR_DONE_1_M |\
1083 GLNVM_ULD_PCIER_DONE_2_M)
1085 uld_mask = ICE_RESET_DONE_MASK;
1087 /* Device is Active; check Global Reset processes are done */
1088 for (cnt = 0; cnt < ICE_PF_RESET_WAIT_COUNT; cnt++) {
1089 reg = rd32(hw, GLNVM_ULD) & uld_mask;
1090 if (reg == uld_mask) {
1091 ice_debug(hw, ICE_DBG_INIT, "Global reset processes done. %d\n", cnt);
1094 ice_msec_delay(10, true);
1097 if (cnt == ICE_PF_RESET_WAIT_COUNT) {
1098 ice_debug(hw, ICE_DBG_INIT, "Wait for Reset Done timed out. GLNVM_ULD = 0x%x\n",
1100 return ICE_ERR_RESET_FAILED;
1107 * ice_pf_reset - Reset the PF
1108 * @hw: pointer to the hardware structure
1110 * If a global reset has been triggered, this function checks
1111 * for its completion and then issues the PF reset
1113 static enum ice_status ice_pf_reset(struct ice_hw *hw)
1117 /* If at function entry a global reset was already in progress, i.e.
1118 * state is not 'device active' or any of the reset done bits are not
1119 * set in GLNVM_ULD, there is no need for a PF Reset; poll until the
1120 * global reset is done.
1122 if ((rd32(hw, GLGEN_RSTAT) & GLGEN_RSTAT_DEVSTATE_M) ||
1123 (rd32(hw, GLNVM_ULD) & ICE_RESET_DONE_MASK) ^ ICE_RESET_DONE_MASK) {
1124 /* poll on global reset currently in progress until done */
1125 if (ice_check_reset(hw))
1126 return ICE_ERR_RESET_FAILED;
1132 reg = rd32(hw, PFGEN_CTRL);
1134 wr32(hw, PFGEN_CTRL, (reg | PFGEN_CTRL_PFSWR_M));
1136 /* Wait for the PFR to complete. The wait time is the global config lock
1137 * timeout plus the PFR timeout which will account for a possible reset
1138 * that is occurring during a download package operation.
1140 for (cnt = 0; cnt < ICE_GLOBAL_CFG_LOCK_TIMEOUT +
1141 ICE_PF_RESET_WAIT_COUNT; cnt++) {
1142 reg = rd32(hw, PFGEN_CTRL);
1143 if (!(reg & PFGEN_CTRL_PFSWR_M))
1146 ice_msec_delay(1, true);
1149 if (cnt == ICE_PF_RESET_WAIT_COUNT) {
1150 ice_debug(hw, ICE_DBG_INIT, "PF reset polling failed to complete.\n");
1151 return ICE_ERR_RESET_FAILED;
1158 * ice_reset - Perform different types of reset
1159 * @hw: pointer to the hardware structure
1160 * @req: reset request
1162 * This function triggers a reset as specified by the req parameter.
1165 * If anything other than a PF reset is triggered, PXE mode is restored.
1166 * This has to be cleared using ice_clear_pxe_mode again, once the AQ
1167 * interface has been restored in the rebuild flow.
1169 enum ice_status ice_reset(struct ice_hw *hw, enum ice_reset_req req)
1175 return ice_pf_reset(hw);
1176 case ICE_RESET_CORER:
1177 ice_debug(hw, ICE_DBG_INIT, "CoreR requested\n");
1178 val = GLGEN_RTRIG_CORER_M;
1180 case ICE_RESET_GLOBR:
1181 ice_debug(hw, ICE_DBG_INIT, "GlobalR requested\n");
1182 val = GLGEN_RTRIG_GLOBR_M;
1185 return ICE_ERR_PARAM;
1188 val |= rd32(hw, GLGEN_RTRIG);
1189 wr32(hw, GLGEN_RTRIG, val);
1192 /* wait for the FW to be ready */
1193 return ice_check_reset(hw);
1197 * ice_copy_rxq_ctx_to_hw
1198 * @hw: pointer to the hardware structure
1199 * @ice_rxq_ctx: pointer to the rxq context
1200 * @rxq_index: the index of the Rx queue
1202 * Copies rxq context from dense structure to HW register space
1204 static enum ice_status
1205 ice_copy_rxq_ctx_to_hw(struct ice_hw *hw, u8 *ice_rxq_ctx, u32 rxq_index)
1210 return ICE_ERR_BAD_PTR;
1212 if (rxq_index > QRX_CTRL_MAX_INDEX)
1213 return ICE_ERR_PARAM;
1215 /* Copy each dword separately to HW */
1216 for (i = 0; i < ICE_RXQ_CTX_SIZE_DWORDS; i++) {
1217 wr32(hw, QRX_CONTEXT(i, rxq_index),
1218 *((u32 *)(ice_rxq_ctx + (i * sizeof(u32)))));
1220 ice_debug(hw, ICE_DBG_QCTX, "qrxdata[%d]: %08X\n", i,
1221 *((u32 *)(ice_rxq_ctx + (i * sizeof(u32)))));
1227 /* LAN Rx Queue Context */
1228 static const struct ice_ctx_ele ice_rlan_ctx_info[] = {
1229 /* Field Width LSB */
1230 ICE_CTX_STORE(ice_rlan_ctx, head, 13, 0),
1231 ICE_CTX_STORE(ice_rlan_ctx, cpuid, 8, 13),
1232 ICE_CTX_STORE(ice_rlan_ctx, base, 57, 32),
1233 ICE_CTX_STORE(ice_rlan_ctx, qlen, 13, 89),
1234 ICE_CTX_STORE(ice_rlan_ctx, dbuf, 7, 102),
1235 ICE_CTX_STORE(ice_rlan_ctx, hbuf, 5, 109),
1236 ICE_CTX_STORE(ice_rlan_ctx, dtype, 2, 114),
1237 ICE_CTX_STORE(ice_rlan_ctx, dsize, 1, 116),
1238 ICE_CTX_STORE(ice_rlan_ctx, crcstrip, 1, 117),
1239 ICE_CTX_STORE(ice_rlan_ctx, l2tsel, 1, 119),
1240 ICE_CTX_STORE(ice_rlan_ctx, hsplit_0, 4, 120),
1241 ICE_CTX_STORE(ice_rlan_ctx, hsplit_1, 2, 124),
1242 ICE_CTX_STORE(ice_rlan_ctx, showiv, 1, 127),
1243 ICE_CTX_STORE(ice_rlan_ctx, rxmax, 14, 174),
1244 ICE_CTX_STORE(ice_rlan_ctx, tphrdesc_ena, 1, 193),
1245 ICE_CTX_STORE(ice_rlan_ctx, tphwdesc_ena, 1, 194),
1246 ICE_CTX_STORE(ice_rlan_ctx, tphdata_ena, 1, 195),
1247 ICE_CTX_STORE(ice_rlan_ctx, tphhead_ena, 1, 196),
1248 ICE_CTX_STORE(ice_rlan_ctx, lrxqthresh, 3, 198),
1249 ICE_CTX_STORE(ice_rlan_ctx, prefena, 1, 201),
1255 * @hw: pointer to the hardware structure
1256 * @rlan_ctx: pointer to the rxq context
1257 * @rxq_index: the index of the Rx queue
1259 * Converts rxq context from sparse to dense structure and then writes
1260 * it to HW register space and enables the hardware to prefetch descriptors
1261 * instead of only fetching them on demand
1264 ice_write_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx,
1267 u8 ctx_buf[ICE_RXQ_CTX_SZ] = { 0 };
1270 return ICE_ERR_BAD_PTR;
1272 rlan_ctx->prefena = 1;
1274 ice_set_ctx(hw, (u8 *)rlan_ctx, ctx_buf, ice_rlan_ctx_info);
1275 return ice_copy_rxq_ctx_to_hw(hw, ctx_buf, rxq_index);
1280 * @hw: pointer to the hardware structure
1281 * @rxq_index: the index of the Rx queue to clear
1283 * Clears rxq context in HW register space
1285 enum ice_status ice_clear_rxq_ctx(struct ice_hw *hw, u32 rxq_index)
1289 if (rxq_index > QRX_CTRL_MAX_INDEX)
1290 return ICE_ERR_PARAM;
1292 /* Clear each dword register separately */
1293 for (i = 0; i < ICE_RXQ_CTX_SIZE_DWORDS; i++)
1294 wr32(hw, QRX_CONTEXT(i, rxq_index), 0);
1299 /* LAN Tx Queue Context */
1300 const struct ice_ctx_ele ice_tlan_ctx_info[] = {
1301 /* Field Width LSB */
1302 ICE_CTX_STORE(ice_tlan_ctx, base, 57, 0),
1303 ICE_CTX_STORE(ice_tlan_ctx, port_num, 3, 57),
1304 ICE_CTX_STORE(ice_tlan_ctx, cgd_num, 5, 60),
1305 ICE_CTX_STORE(ice_tlan_ctx, pf_num, 3, 65),
1306 ICE_CTX_STORE(ice_tlan_ctx, vmvf_num, 10, 68),
1307 ICE_CTX_STORE(ice_tlan_ctx, vmvf_type, 2, 78),
1308 ICE_CTX_STORE(ice_tlan_ctx, src_vsi, 10, 80),
1309 ICE_CTX_STORE(ice_tlan_ctx, tsyn_ena, 1, 90),
1310 ICE_CTX_STORE(ice_tlan_ctx, internal_usage_flag, 1, 91),
1311 ICE_CTX_STORE(ice_tlan_ctx, alt_vlan, 1, 92),
1312 ICE_CTX_STORE(ice_tlan_ctx, cpuid, 8, 93),
1313 ICE_CTX_STORE(ice_tlan_ctx, wb_mode, 1, 101),
1314 ICE_CTX_STORE(ice_tlan_ctx, tphrd_desc, 1, 102),
1315 ICE_CTX_STORE(ice_tlan_ctx, tphrd, 1, 103),
1316 ICE_CTX_STORE(ice_tlan_ctx, tphwr_desc, 1, 104),
1317 ICE_CTX_STORE(ice_tlan_ctx, cmpq_id, 9, 105),
1318 ICE_CTX_STORE(ice_tlan_ctx, qnum_in_func, 14, 114),
1319 ICE_CTX_STORE(ice_tlan_ctx, itr_notification_mode, 1, 128),
1320 ICE_CTX_STORE(ice_tlan_ctx, adjust_prof_id, 6, 129),
1321 ICE_CTX_STORE(ice_tlan_ctx, qlen, 13, 135),
1322 ICE_CTX_STORE(ice_tlan_ctx, quanta_prof_idx, 4, 148),
1323 ICE_CTX_STORE(ice_tlan_ctx, tso_ena, 1, 152),
1324 ICE_CTX_STORE(ice_tlan_ctx, tso_qnum, 11, 153),
1325 ICE_CTX_STORE(ice_tlan_ctx, legacy_int, 1, 164),
1326 ICE_CTX_STORE(ice_tlan_ctx, drop_ena, 1, 165),
1327 ICE_CTX_STORE(ice_tlan_ctx, cache_prof_idx, 2, 166),
1328 ICE_CTX_STORE(ice_tlan_ctx, pkt_shaper_prof_idx, 3, 168),
1329 ICE_CTX_STORE(ice_tlan_ctx, int_q_state, 122, 171),
1334 * ice_copy_tx_cmpltnq_ctx_to_hw
1335 * @hw: pointer to the hardware structure
1336 * @ice_tx_cmpltnq_ctx: pointer to the Tx completion queue context
1337 * @tx_cmpltnq_index: the index of the completion queue
1339 * Copies Tx completion queue context from dense structure to HW register space
1341 static enum ice_status
1342 ice_copy_tx_cmpltnq_ctx_to_hw(struct ice_hw *hw, u8 *ice_tx_cmpltnq_ctx,
1343 u32 tx_cmpltnq_index)
1347 if (!ice_tx_cmpltnq_ctx)
1348 return ICE_ERR_BAD_PTR;
1350 if (tx_cmpltnq_index > GLTCLAN_CQ_CNTX0_MAX_INDEX)
1351 return ICE_ERR_PARAM;
1353 /* Copy each dword separately to HW */
1354 for (i = 0; i < ICE_TX_CMPLTNQ_CTX_SIZE_DWORDS; i++) {
1355 wr32(hw, GLTCLAN_CQ_CNTX(i, tx_cmpltnq_index),
1356 *((u32 *)(ice_tx_cmpltnq_ctx + (i * sizeof(u32)))));
1358 ice_debug(hw, ICE_DBG_QCTX, "cmpltnqdata[%d]: %08X\n", i,
1359 *((u32 *)(ice_tx_cmpltnq_ctx + (i * sizeof(u32)))));
1365 /* LAN Tx Completion Queue Context */
1366 static const struct ice_ctx_ele ice_tx_cmpltnq_ctx_info[] = {
1367 /* Field Width LSB */
1368 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, base, 57, 0),
1369 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, q_len, 18, 64),
1370 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, generation, 1, 96),
1371 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, wrt_ptr, 22, 97),
1372 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, pf_num, 3, 128),
1373 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, vmvf_num, 10, 131),
1374 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, vmvf_type, 2, 141),
1375 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, tph_desc_wr, 1, 160),
1376 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, cpuid, 8, 161),
1377 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, cmpltn_cache, 512, 192),
1382 * ice_write_tx_cmpltnq_ctx
1383 * @hw: pointer to the hardware structure
1384 * @tx_cmpltnq_ctx: pointer to the completion queue context
1385 * @tx_cmpltnq_index: the index of the completion queue
1387 * Converts completion queue context from sparse to dense structure and then
1388 * writes it to HW register space
1391 ice_write_tx_cmpltnq_ctx(struct ice_hw *hw,
1392 struct ice_tx_cmpltnq_ctx *tx_cmpltnq_ctx,
1393 u32 tx_cmpltnq_index)
1395 u8 ctx_buf[ICE_TX_CMPLTNQ_CTX_SIZE_DWORDS * sizeof(u32)] = { 0 };
1397 ice_set_ctx(hw, (u8 *)tx_cmpltnq_ctx, ctx_buf, ice_tx_cmpltnq_ctx_info);
1398 return ice_copy_tx_cmpltnq_ctx_to_hw(hw, ctx_buf, tx_cmpltnq_index);
1402 * ice_clear_tx_cmpltnq_ctx
1403 * @hw: pointer to the hardware structure
1404 * @tx_cmpltnq_index: the index of the completion queue to clear
1406 * Clears Tx completion queue context in HW register space
1409 ice_clear_tx_cmpltnq_ctx(struct ice_hw *hw, u32 tx_cmpltnq_index)
1413 if (tx_cmpltnq_index > GLTCLAN_CQ_CNTX0_MAX_INDEX)
1414 return ICE_ERR_PARAM;
1416 /* Clear each dword register separately */
1417 for (i = 0; i < ICE_TX_CMPLTNQ_CTX_SIZE_DWORDS; i++)
1418 wr32(hw, GLTCLAN_CQ_CNTX(i, tx_cmpltnq_index), 0);
1424 * ice_copy_tx_drbell_q_ctx_to_hw
1425 * @hw: pointer to the hardware structure
1426 * @ice_tx_drbell_q_ctx: pointer to the doorbell queue context
1427 * @tx_drbell_q_index: the index of the doorbell queue
1429 * Copies doorbell queue context from dense structure to HW register space
1431 static enum ice_status
1432 ice_copy_tx_drbell_q_ctx_to_hw(struct ice_hw *hw, u8 *ice_tx_drbell_q_ctx,
1433 u32 tx_drbell_q_index)
1437 if (!ice_tx_drbell_q_ctx)
1438 return ICE_ERR_BAD_PTR;
1440 if (tx_drbell_q_index > QTX_COMM_DBLQ_DBELL_MAX_INDEX)
1441 return ICE_ERR_PARAM;
1443 /* Copy each dword separately to HW */
1444 for (i = 0; i < ICE_TX_DRBELL_Q_CTX_SIZE_DWORDS; i++) {
1445 wr32(hw, QTX_COMM_DBLQ_CNTX(i, tx_drbell_q_index),
1446 *((u32 *)(ice_tx_drbell_q_ctx + (i * sizeof(u32)))));
1448 ice_debug(hw, ICE_DBG_QCTX, "tx_drbell_qdata[%d]: %08X\n", i,
1449 *((u32 *)(ice_tx_drbell_q_ctx + (i * sizeof(u32)))));
1455 /* LAN Tx Doorbell Queue Context info */
1456 static const struct ice_ctx_ele ice_tx_drbell_q_ctx_info[] = {
1457 /* Field Width LSB */
1458 ICE_CTX_STORE(ice_tx_drbell_q_ctx, base, 57, 0),
1459 ICE_CTX_STORE(ice_tx_drbell_q_ctx, ring_len, 13, 64),
1460 ICE_CTX_STORE(ice_tx_drbell_q_ctx, pf_num, 3, 80),
1461 ICE_CTX_STORE(ice_tx_drbell_q_ctx, vf_num, 8, 84),
1462 ICE_CTX_STORE(ice_tx_drbell_q_ctx, vmvf_type, 2, 94),
1463 ICE_CTX_STORE(ice_tx_drbell_q_ctx, cpuid, 8, 96),
1464 ICE_CTX_STORE(ice_tx_drbell_q_ctx, tph_desc_rd, 1, 104),
1465 ICE_CTX_STORE(ice_tx_drbell_q_ctx, tph_desc_wr, 1, 108),
1466 ICE_CTX_STORE(ice_tx_drbell_q_ctx, db_q_en, 1, 112),
1467 ICE_CTX_STORE(ice_tx_drbell_q_ctx, rd_head, 13, 128),
1468 ICE_CTX_STORE(ice_tx_drbell_q_ctx, rd_tail, 13, 144),
1473 * ice_write_tx_drbell_q_ctx
1474 * @hw: pointer to the hardware structure
1475 * @tx_drbell_q_ctx: pointer to the doorbell queue context
1476 * @tx_drbell_q_index: the index of the doorbell queue
1478 * Converts doorbell queue context from sparse to dense structure and then
1479 * writes it to HW register space
1482 ice_write_tx_drbell_q_ctx(struct ice_hw *hw,
1483 struct ice_tx_drbell_q_ctx *tx_drbell_q_ctx,
1484 u32 tx_drbell_q_index)
1486 u8 ctx_buf[ICE_TX_DRBELL_Q_CTX_SIZE_DWORDS * sizeof(u32)] = { 0 };
1488 ice_set_ctx(hw, (u8 *)tx_drbell_q_ctx, ctx_buf,
1489 ice_tx_drbell_q_ctx_info);
1490 return ice_copy_tx_drbell_q_ctx_to_hw(hw, ctx_buf, tx_drbell_q_index);
1494 * ice_clear_tx_drbell_q_ctx
1495 * @hw: pointer to the hardware structure
1496 * @tx_drbell_q_index: the index of the doorbell queue to clear
1498 * Clears doorbell queue context in HW register space
1501 ice_clear_tx_drbell_q_ctx(struct ice_hw *hw, u32 tx_drbell_q_index)
1505 if (tx_drbell_q_index > QTX_COMM_DBLQ_DBELL_MAX_INDEX)
1506 return ICE_ERR_PARAM;
1508 /* Clear each dword register separately */
1509 for (i = 0; i < ICE_TX_DRBELL_Q_CTX_SIZE_DWORDS; i++)
1510 wr32(hw, QTX_COMM_DBLQ_CNTX(i, tx_drbell_q_index), 0);
1515 /* Sideband Queue command wrappers */
1518 * ice_get_sbq - returns the right control queue to use for sideband
1519 * @hw: pointer to the hardware structure
1521 static struct ice_ctl_q_info *ice_get_sbq(struct ice_hw *hw)
1523 if (!ice_is_generic_mac(hw))
1529 * ice_sbq_send_cmd - send Sideband Queue command to Sideband Queue
1530 * @hw: pointer to the HW struct
1531 * @desc: descriptor describing the command
1532 * @buf: buffer to use for indirect commands (NULL for direct commands)
1533 * @buf_size: size of buffer for indirect commands (0 for direct commands)
1534 * @cd: pointer to command details structure
1536 static enum ice_status
1537 ice_sbq_send_cmd(struct ice_hw *hw, struct ice_sbq_cmd_desc *desc,
1538 void *buf, u16 buf_size, struct ice_sq_cd *cd)
1540 return ice_sq_send_cmd(hw, ice_get_sbq(hw), (struct ice_aq_desc *)desc,
1545 * ice_sbq_send_cmd_nolock - send Sideband Queue command to Sideband Queue
1546 * but do not lock sq_lock
1547 * @hw: pointer to the HW struct
1548 * @desc: descriptor describing the command
1549 * @buf: buffer to use for indirect commands (NULL for direct commands)
1550 * @buf_size: size of buffer for indirect commands (0 for direct commands)
1551 * @cd: pointer to command details structure
1553 static enum ice_status
1554 ice_sbq_send_cmd_nolock(struct ice_hw *hw, struct ice_sbq_cmd_desc *desc,
1555 void *buf, u16 buf_size, struct ice_sq_cd *cd)
1557 return ice_sq_send_cmd_nolock(hw, ice_get_sbq(hw),
1558 (struct ice_aq_desc *)desc, buf,
1563 * ice_sbq_rw_reg_lp - Fill Sideband Queue command, with lock parameter
1564 * @hw: pointer to the HW struct
1565 * @in: message info to be filled in descriptor
1566 * @lock: true to lock the sq_lock (the usual case); false if the sq_lock has
1567 * already been locked at a higher level
1569 enum ice_status ice_sbq_rw_reg_lp(struct ice_hw *hw,
1570 struct ice_sbq_msg_input *in, bool lock)
1572 struct ice_sbq_cmd_desc desc = {0};
1573 struct ice_sbq_msg_req msg = {0};
1574 enum ice_status status;
1577 msg_len = sizeof(msg);
1579 msg.dest_dev = in->dest_dev;
1580 msg.opcode = in->opcode;
1581 msg.flags = ICE_SBQ_MSG_FLAGS;
1582 msg.sbe_fbe = ICE_SBQ_MSG_SBE_FBE;
1583 msg.msg_addr_low = CPU_TO_LE16(in->msg_addr_low);
1584 msg.msg_addr_high = CPU_TO_LE32(in->msg_addr_high);
1587 msg.data = CPU_TO_LE32(in->data);
1589 /* data read comes back in completion, so shorten the struct by
1592 msg_len -= sizeof(msg.data);
1594 desc.flags = CPU_TO_LE16(ICE_AQ_FLAG_RD);
1595 desc.opcode = CPU_TO_LE16(ice_sbq_opc_neigh_dev_req);
1596 desc.param0.cmd_len = CPU_TO_LE16(msg_len);
1598 status = ice_sbq_send_cmd(hw, &desc, &msg, msg_len, NULL);
1600 status = ice_sbq_send_cmd_nolock(hw, &desc, &msg, msg_len,
1602 if (!status && !in->opcode)
1603 in->data = LE32_TO_CPU
1604 (((struct ice_sbq_msg_cmpl *)&msg)->data);
1609 * ice_sbq_rw_reg - Fill Sideband Queue command
1610 * @hw: pointer to the HW struct
1611 * @in: message info to be filled in descriptor
1613 enum ice_status ice_sbq_rw_reg(struct ice_hw *hw, struct ice_sbq_msg_input *in)
1615 return ice_sbq_rw_reg_lp(hw, in, true);
1619 * ice_sbq_lock - Lock the sideband queue's sq_lock
1620 * @hw: pointer to the HW struct
1622 void ice_sbq_lock(struct ice_hw *hw)
1624 ice_acquire_lock(&ice_get_sbq(hw)->sq_lock);
1628 * ice_sbq_unlock - Unlock the sideband queue's sq_lock
1629 * @hw: pointer to the HW struct
1631 void ice_sbq_unlock(struct ice_hw *hw)
1633 ice_release_lock(&ice_get_sbq(hw)->sq_lock);
1636 /* FW Admin Queue command wrappers */
1639 * ice_should_retry_sq_send_cmd
1640 * @opcode: AQ opcode
1642 * Decide if we should retry the send command routine for the ATQ, depending
1645 static bool ice_should_retry_sq_send_cmd(u16 opcode)
1648 case ice_aqc_opc_get_link_topo:
1649 case ice_aqc_opc_lldp_stop:
1650 case ice_aqc_opc_lldp_start:
1651 case ice_aqc_opc_lldp_filter_ctrl:
1659 * ice_sq_send_cmd_retry - send command to Control Queue (ATQ)
1660 * @hw: pointer to the HW struct
1661 * @cq: pointer to the specific Control queue
1662 * @desc: prefilled descriptor describing the command
1663 * @buf: buffer to use for indirect commands (or NULL for direct commands)
1664 * @buf_size: size of buffer for indirect commands (or 0 for direct commands)
1665 * @cd: pointer to command details structure
1667 * Retry sending the FW Admin Queue command, multiple times, to the FW Admin
1668 * Queue if the EBUSY AQ error is returned.
1670 static enum ice_status
1671 ice_sq_send_cmd_retry(struct ice_hw *hw, struct ice_ctl_q_info *cq,
1672 struct ice_aq_desc *desc, void *buf, u16 buf_size,
1673 struct ice_sq_cd *cd)
1675 struct ice_aq_desc desc_cpy;
1676 enum ice_status status;
1677 bool is_cmd_for_retry;
1682 opcode = LE16_TO_CPU(desc->opcode);
1683 is_cmd_for_retry = ice_should_retry_sq_send_cmd(opcode);
1684 ice_memset(&desc_cpy, 0, sizeof(desc_cpy), ICE_NONDMA_MEM);
1686 if (is_cmd_for_retry) {
1688 buf_cpy = (u8 *)ice_malloc(hw, buf_size);
1690 return ICE_ERR_NO_MEMORY;
1693 ice_memcpy(&desc_cpy, desc, sizeof(desc_cpy),
1694 ICE_NONDMA_TO_NONDMA);
1698 status = ice_sq_send_cmd(hw, cq, desc, buf, buf_size, cd);
1700 if (!is_cmd_for_retry || status == ICE_SUCCESS ||
1701 hw->adminq.sq_last_status != ICE_AQ_RC_EBUSY)
1705 ice_memcpy(buf, buf_cpy, buf_size,
1706 ICE_NONDMA_TO_NONDMA);
1708 ice_memcpy(desc, &desc_cpy, sizeof(desc_cpy),
1709 ICE_NONDMA_TO_NONDMA);
1711 ice_msec_delay(ICE_SQ_SEND_DELAY_TIME_MS, false);
1713 } while (++idx < ICE_SQ_SEND_MAX_EXECUTE);
1716 ice_free(hw, buf_cpy);
1722 * ice_aq_send_cmd - send FW Admin Queue command to FW Admin Queue
1723 * @hw: pointer to the HW struct
1724 * @desc: descriptor describing the command
1725 * @buf: buffer to use for indirect commands (NULL for direct commands)
1726 * @buf_size: size of buffer for indirect commands (0 for direct commands)
1727 * @cd: pointer to command details structure
1729 * Helper function to send FW Admin Queue commands to the FW Admin Queue.
1732 ice_aq_send_cmd(struct ice_hw *hw, struct ice_aq_desc *desc, void *buf,
1733 u16 buf_size, struct ice_sq_cd *cd)
1735 if (hw->aq_send_cmd_fn) {
1736 enum ice_status status = ICE_ERR_NOT_READY;
1737 u16 retval = ICE_AQ_RC_OK;
1739 ice_acquire_lock(&hw->adminq.sq_lock);
1740 if (!hw->aq_send_cmd_fn(hw->aq_send_cmd_param, desc,
1742 retval = LE16_TO_CPU(desc->retval);
1743 /* strip off FW internal code */
1746 if (retval == ICE_AQ_RC_OK)
1747 status = ICE_SUCCESS;
1749 status = ICE_ERR_AQ_ERROR;
1752 hw->adminq.sq_last_status = (enum ice_aq_err)retval;
1753 ice_release_lock(&hw->adminq.sq_lock);
1757 return ice_sq_send_cmd_retry(hw, &hw->adminq, desc, buf, buf_size, cd);
1762 * @hw: pointer to the HW struct
1763 * @cd: pointer to command details structure or NULL
1765 * Get the firmware version (0x0001) from the admin queue commands
1767 enum ice_status ice_aq_get_fw_ver(struct ice_hw *hw, struct ice_sq_cd *cd)
1769 struct ice_aqc_get_ver *resp;
1770 struct ice_aq_desc desc;
1771 enum ice_status status;
1773 resp = &desc.params.get_ver;
1775 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_ver);
1777 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
1780 hw->fw_branch = resp->fw_branch;
1781 hw->fw_maj_ver = resp->fw_major;
1782 hw->fw_min_ver = resp->fw_minor;
1783 hw->fw_patch = resp->fw_patch;
1784 hw->fw_build = LE32_TO_CPU(resp->fw_build);
1785 hw->api_branch = resp->api_branch;
1786 hw->api_maj_ver = resp->api_major;
1787 hw->api_min_ver = resp->api_minor;
1788 hw->api_patch = resp->api_patch;
1795 * ice_aq_send_driver_ver
1796 * @hw: pointer to the HW struct
1797 * @dv: driver's major, minor version
1798 * @cd: pointer to command details structure or NULL
1800 * Send the driver version (0x0002) to the firmware
1803 ice_aq_send_driver_ver(struct ice_hw *hw, struct ice_driver_ver *dv,
1804 struct ice_sq_cd *cd)
1806 struct ice_aqc_driver_ver *cmd;
1807 struct ice_aq_desc desc;
1810 cmd = &desc.params.driver_ver;
1813 return ICE_ERR_PARAM;
1815 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_driver_ver);
1817 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
1818 cmd->major_ver = dv->major_ver;
1819 cmd->minor_ver = dv->minor_ver;
1820 cmd->build_ver = dv->build_ver;
1821 cmd->subbuild_ver = dv->subbuild_ver;
1824 while (len < sizeof(dv->driver_string) &&
1825 IS_ASCII(dv->driver_string[len]) && dv->driver_string[len])
1828 return ice_aq_send_cmd(hw, &desc, dv->driver_string, len, cd);
1833 * @hw: pointer to the HW struct
1834 * @unloading: is the driver unloading itself
1836 * Tell the Firmware that we're shutting down the AdminQ and whether
1837 * or not the driver is unloading as well (0x0003).
1839 enum ice_status ice_aq_q_shutdown(struct ice_hw *hw, bool unloading)
1841 struct ice_aqc_q_shutdown *cmd;
1842 struct ice_aq_desc desc;
1844 cmd = &desc.params.q_shutdown;
1846 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_q_shutdown);
1849 cmd->driver_unloading = ICE_AQC_DRIVER_UNLOADING;
1851 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
1856 * @hw: pointer to the HW struct
1858 * @access: access type
1859 * @sdp_number: resource number
1860 * @timeout: the maximum time in ms that the driver may hold the resource
1861 * @cd: pointer to command details structure or NULL
1863 * Requests common resource using the admin queue commands (0x0008).
1864 * When attempting to acquire the Global Config Lock, the driver can
1865 * learn of three states:
1866 * 1) ICE_SUCCESS - acquired lock, and can perform download package
1867 * 2) ICE_ERR_AQ_ERROR - did not get lock, driver should fail to load
1868 * 3) ICE_ERR_AQ_NO_WORK - did not get lock, but another driver has
1869 * successfully downloaded the package; the driver does
1870 * not have to download the package and can continue
1873 * Note that if the caller is in an acquire lock, perform action, release lock
1874 * phase of operation, it is possible that the FW may detect a timeout and issue
1875 * a CORER. In this case, the driver will receive a CORER interrupt and will
1876 * have to determine its cause. The calling thread that is handling this flow
1877 * will likely get an error propagated back to it indicating the Download
1878 * Package, Update Package or the Release Resource AQ commands timed out.
1880 static enum ice_status
1881 ice_aq_req_res(struct ice_hw *hw, enum ice_aq_res_ids res,
1882 enum ice_aq_res_access_type access, u8 sdp_number, u32 *timeout,
1883 struct ice_sq_cd *cd)
1885 struct ice_aqc_req_res *cmd_resp;
1886 struct ice_aq_desc desc;
1887 enum ice_status status;
1889 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
1891 cmd_resp = &desc.params.res_owner;
1893 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_req_res);
1895 cmd_resp->res_id = CPU_TO_LE16(res);
1896 cmd_resp->access_type = CPU_TO_LE16(access);
1897 cmd_resp->res_number = CPU_TO_LE32(sdp_number);
1898 cmd_resp->timeout = CPU_TO_LE32(*timeout);
1901 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
1903 /* The completion specifies the maximum time in ms that the driver
1904 * may hold the resource in the Timeout field.
1907 /* Global config lock response utilizes an additional status field.
1909 * If the Global config lock resource is held by some other driver, the
1910 * command completes with ICE_AQ_RES_GLBL_IN_PROG in the status field
1911 * and the timeout field indicates the maximum time the current owner
1912 * of the resource has to free it.
1914 if (res == ICE_GLOBAL_CFG_LOCK_RES_ID) {
1915 if (LE16_TO_CPU(cmd_resp->status) == ICE_AQ_RES_GLBL_SUCCESS) {
1916 *timeout = LE32_TO_CPU(cmd_resp->timeout);
1918 } else if (LE16_TO_CPU(cmd_resp->status) ==
1919 ICE_AQ_RES_GLBL_IN_PROG) {
1920 *timeout = LE32_TO_CPU(cmd_resp->timeout);
1921 return ICE_ERR_AQ_ERROR;
1922 } else if (LE16_TO_CPU(cmd_resp->status) ==
1923 ICE_AQ_RES_GLBL_DONE) {
1924 return ICE_ERR_AQ_NO_WORK;
1927 /* invalid FW response, force a timeout immediately */
1929 return ICE_ERR_AQ_ERROR;
1932 /* If the resource is held by some other driver, the command completes
1933 * with a busy return value and the timeout field indicates the maximum
1934 * time the current owner of the resource has to free it.
1936 if (!status || hw->adminq.sq_last_status == ICE_AQ_RC_EBUSY)
1937 *timeout = LE32_TO_CPU(cmd_resp->timeout);
1943 * ice_aq_release_res
1944 * @hw: pointer to the HW struct
1946 * @sdp_number: resource number
1947 * @cd: pointer to command details structure or NULL
1949 * release common resource using the admin queue commands (0x0009)
1951 static enum ice_status
1952 ice_aq_release_res(struct ice_hw *hw, enum ice_aq_res_ids res, u8 sdp_number,
1953 struct ice_sq_cd *cd)
1955 struct ice_aqc_req_res *cmd;
1956 struct ice_aq_desc desc;
1958 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
1960 cmd = &desc.params.res_owner;
1962 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_release_res);
1964 cmd->res_id = CPU_TO_LE16(res);
1965 cmd->res_number = CPU_TO_LE32(sdp_number);
1967 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
1972 * @hw: pointer to the HW structure
1974 * @access: access type (read or write)
1975 * @timeout: timeout in milliseconds
1977 * This function will attempt to acquire the ownership of a resource.
1980 ice_acquire_res(struct ice_hw *hw, enum ice_aq_res_ids res,
1981 enum ice_aq_res_access_type access, u32 timeout)
1983 #define ICE_RES_POLLING_DELAY_MS 10
1984 u32 delay = ICE_RES_POLLING_DELAY_MS;
1985 u32 time_left = timeout;
1986 enum ice_status status;
1988 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
1990 status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL);
1992 /* A return code of ICE_ERR_AQ_NO_WORK means that another driver has
1993 * previously acquired the resource and performed any necessary updates;
1994 * in this case the caller does not obtain the resource and has no
1995 * further work to do.
1997 if (status == ICE_ERR_AQ_NO_WORK)
1998 goto ice_acquire_res_exit;
2001 ice_debug(hw, ICE_DBG_RES, "resource %d acquire type %d failed.\n", res, access);
2003 /* If necessary, poll until the current lock owner timeouts */
2004 timeout = time_left;
2005 while (status && timeout && time_left) {
2006 ice_msec_delay(delay, true);
2007 timeout = (timeout > delay) ? timeout - delay : 0;
2008 status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL);
2010 if (status == ICE_ERR_AQ_NO_WORK)
2011 /* lock free, but no work to do */
2018 if (status && status != ICE_ERR_AQ_NO_WORK)
2019 ice_debug(hw, ICE_DBG_RES, "resource acquire timed out.\n");
2021 ice_acquire_res_exit:
2022 if (status == ICE_ERR_AQ_NO_WORK) {
2023 if (access == ICE_RES_WRITE)
2024 ice_debug(hw, ICE_DBG_RES, "resource indicates no work to do.\n");
2026 ice_debug(hw, ICE_DBG_RES, "Warning: ICE_ERR_AQ_NO_WORK not expected\n");
2033 * @hw: pointer to the HW structure
2036 * This function will release a resource using the proper Admin Command.
2038 void ice_release_res(struct ice_hw *hw, enum ice_aq_res_ids res)
2040 enum ice_status status;
2041 u32 total_delay = 0;
2043 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
2045 status = ice_aq_release_res(hw, res, 0, NULL);
2047 /* there are some rare cases when trying to release the resource
2048 * results in an admin queue timeout, so handle them correctly
2050 while ((status == ICE_ERR_AQ_TIMEOUT) &&
2051 (total_delay < hw->adminq.sq_cmd_timeout)) {
2052 ice_msec_delay(1, true);
2053 status = ice_aq_release_res(hw, res, 0, NULL);
2059 * ice_aq_alloc_free_res - command to allocate/free resources
2060 * @hw: pointer to the HW struct
2061 * @num_entries: number of resource entries in buffer
2062 * @buf: Indirect buffer to hold data parameters and response
2063 * @buf_size: size of buffer for indirect commands
2064 * @opc: pass in the command opcode
2065 * @cd: pointer to command details structure or NULL
2067 * Helper function to allocate/free resources using the admin queue commands
2070 ice_aq_alloc_free_res(struct ice_hw *hw, u16 num_entries,
2071 struct ice_aqc_alloc_free_res_elem *buf, u16 buf_size,
2072 enum ice_adminq_opc opc, struct ice_sq_cd *cd)
2074 struct ice_aqc_alloc_free_res_cmd *cmd;
2075 struct ice_aq_desc desc;
2077 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
2079 cmd = &desc.params.sw_res_ctrl;
2082 return ICE_ERR_PARAM;
2084 if (buf_size < FLEX_ARRAY_SIZE(buf, elem, num_entries))
2085 return ICE_ERR_PARAM;
2087 ice_fill_dflt_direct_cmd_desc(&desc, opc);
2089 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
2091 cmd->num_entries = CPU_TO_LE16(num_entries);
2093 return ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);
2097 * ice_alloc_hw_res - allocate resource
2098 * @hw: pointer to the HW struct
2099 * @type: type of resource
2100 * @num: number of resources to allocate
2101 * @btm: allocate from bottom
2102 * @res: pointer to array that will receive the resources
2105 ice_alloc_hw_res(struct ice_hw *hw, u16 type, u16 num, bool btm, u16 *res)
2107 struct ice_aqc_alloc_free_res_elem *buf;
2108 enum ice_status status;
2111 buf_len = ice_struct_size(buf, elem, num);
2112 buf = (struct ice_aqc_alloc_free_res_elem *)ice_malloc(hw, buf_len);
2114 return ICE_ERR_NO_MEMORY;
2116 /* Prepare buffer to allocate resource. */
2117 buf->num_elems = CPU_TO_LE16(num);
2118 buf->res_type = CPU_TO_LE16(type | ICE_AQC_RES_TYPE_FLAG_DEDICATED |
2119 ICE_AQC_RES_TYPE_FLAG_IGNORE_INDEX);
2121 buf->res_type |= CPU_TO_LE16(ICE_AQC_RES_TYPE_FLAG_SCAN_BOTTOM);
2123 status = ice_aq_alloc_free_res(hw, 1, buf, buf_len,
2124 ice_aqc_opc_alloc_res, NULL);
2126 goto ice_alloc_res_exit;
2128 ice_memcpy(res, buf->elem, sizeof(*buf->elem) * num,
2129 ICE_NONDMA_TO_NONDMA);
2137 * ice_free_hw_res - free allocated HW resource
2138 * @hw: pointer to the HW struct
2139 * @type: type of resource to free
2140 * @num: number of resources
2141 * @res: pointer to array that contains the resources to free
2143 enum ice_status ice_free_hw_res(struct ice_hw *hw, u16 type, u16 num, u16 *res)
2145 struct ice_aqc_alloc_free_res_elem *buf;
2146 enum ice_status status;
2149 buf_len = ice_struct_size(buf, elem, num);
2150 buf = (struct ice_aqc_alloc_free_res_elem *)ice_malloc(hw, buf_len);
2152 return ICE_ERR_NO_MEMORY;
2154 /* Prepare buffer to free resource. */
2155 buf->num_elems = CPU_TO_LE16(num);
2156 buf->res_type = CPU_TO_LE16(type);
2157 ice_memcpy(buf->elem, res, sizeof(*buf->elem) * num,
2158 ICE_NONDMA_TO_NONDMA);
2160 status = ice_aq_alloc_free_res(hw, num, buf, buf_len,
2161 ice_aqc_opc_free_res, NULL);
2163 ice_debug(hw, ICE_DBG_SW, "CQ CMD Buffer:\n");
2170 * ice_get_num_per_func - determine number of resources per PF
2171 * @hw: pointer to the HW structure
2172 * @max: value to be evenly split between each PF
2174 * Determine the number of valid functions by going through the bitmap returned
2175 * from parsing capabilities and use this to calculate the number of resources
2176 * per PF based on the max value passed in.
2178 static u32 ice_get_num_per_func(struct ice_hw *hw, u32 max)
2182 #define ICE_CAPS_VALID_FUNCS_M 0xFF
2183 funcs = ice_hweight8(hw->dev_caps.common_cap.valid_functions &
2184 ICE_CAPS_VALID_FUNCS_M);
2193 * ice_parse_common_caps - parse common device/function capabilities
2194 * @hw: pointer to the HW struct
2195 * @caps: pointer to common capabilities structure
2196 * @elem: the capability element to parse
2197 * @prefix: message prefix for tracing capabilities
2199 * Given a capability element, extract relevant details into the common
2200 * capability structure.
2202 * Returns: true if the capability matches one of the common capability ids,
2206 ice_parse_common_caps(struct ice_hw *hw, struct ice_hw_common_caps *caps,
2207 struct ice_aqc_list_caps_elem *elem, const char *prefix)
2209 u32 logical_id = LE32_TO_CPU(elem->logical_id);
2210 u32 phys_id = LE32_TO_CPU(elem->phys_id);
2211 u32 number = LE32_TO_CPU(elem->number);
2212 u16 cap = LE16_TO_CPU(elem->cap);
2216 case ICE_AQC_CAPS_VALID_FUNCTIONS:
2217 caps->valid_functions = number;
2218 ice_debug(hw, ICE_DBG_INIT, "%s: valid_functions (bitmap) = %d\n", prefix,
2219 caps->valid_functions);
2221 case ICE_AQC_CAPS_DCB:
2222 caps->dcb = (number == 1);
2223 caps->active_tc_bitmap = logical_id;
2224 caps->maxtc = phys_id;
2225 ice_debug(hw, ICE_DBG_INIT, "%s: dcb = %d\n", prefix, caps->dcb);
2226 ice_debug(hw, ICE_DBG_INIT, "%s: active_tc_bitmap = %d\n", prefix,
2227 caps->active_tc_bitmap);
2228 ice_debug(hw, ICE_DBG_INIT, "%s: maxtc = %d\n", prefix, caps->maxtc);
2230 case ICE_AQC_CAPS_RSS:
2231 caps->rss_table_size = number;
2232 caps->rss_table_entry_width = logical_id;
2233 ice_debug(hw, ICE_DBG_INIT, "%s: rss_table_size = %d\n", prefix,
2234 caps->rss_table_size);
2235 ice_debug(hw, ICE_DBG_INIT, "%s: rss_table_entry_width = %d\n", prefix,
2236 caps->rss_table_entry_width);
2238 case ICE_AQC_CAPS_RXQS:
2239 caps->num_rxq = number;
2240 caps->rxq_first_id = phys_id;
2241 ice_debug(hw, ICE_DBG_INIT, "%s: num_rxq = %d\n", prefix,
2243 ice_debug(hw, ICE_DBG_INIT, "%s: rxq_first_id = %d\n", prefix,
2244 caps->rxq_first_id);
2246 case ICE_AQC_CAPS_TXQS:
2247 caps->num_txq = number;
2248 caps->txq_first_id = phys_id;
2249 ice_debug(hw, ICE_DBG_INIT, "%s: num_txq = %d\n", prefix,
2251 ice_debug(hw, ICE_DBG_INIT, "%s: txq_first_id = %d\n", prefix,
2252 caps->txq_first_id);
2254 case ICE_AQC_CAPS_MSIX:
2255 caps->num_msix_vectors = number;
2256 caps->msix_vector_first_id = phys_id;
2257 ice_debug(hw, ICE_DBG_INIT, "%s: num_msix_vectors = %d\n", prefix,
2258 caps->num_msix_vectors);
2259 ice_debug(hw, ICE_DBG_INIT, "%s: msix_vector_first_id = %d\n", prefix,
2260 caps->msix_vector_first_id);
2262 case ICE_AQC_CAPS_NVM_MGMT:
2263 caps->sec_rev_disabled =
2264 (number & ICE_NVM_MGMT_SEC_REV_DISABLED) ?
2266 ice_debug(hw, ICE_DBG_INIT, "%s: sec_rev_disabled = %d\n", prefix,
2267 caps->sec_rev_disabled);
2268 caps->update_disabled =
2269 (number & ICE_NVM_MGMT_UPDATE_DISABLED) ?
2271 ice_debug(hw, ICE_DBG_INIT, "%s: update_disabled = %d\n", prefix,
2272 caps->update_disabled);
2273 caps->nvm_unified_update =
2274 (number & ICE_NVM_MGMT_UNIFIED_UPD_SUPPORT) ?
2276 ice_debug(hw, ICE_DBG_INIT, "%s: nvm_unified_update = %d\n", prefix,
2277 caps->nvm_unified_update);
2279 case ICE_AQC_CAPS_MAX_MTU:
2280 caps->max_mtu = number;
2281 ice_debug(hw, ICE_DBG_INIT, "%s: max_mtu = %d\n",
2282 prefix, caps->max_mtu);
2284 case ICE_AQC_CAPS_EXT_TOPO_DEV_IMG0:
2285 case ICE_AQC_CAPS_EXT_TOPO_DEV_IMG1:
2286 case ICE_AQC_CAPS_EXT_TOPO_DEV_IMG2:
2287 case ICE_AQC_CAPS_EXT_TOPO_DEV_IMG3:
2289 u8 index = cap - ICE_AQC_CAPS_EXT_TOPO_DEV_IMG0;
2291 caps->ext_topo_dev_img_ver_high[index] = number;
2292 caps->ext_topo_dev_img_ver_low[index] = logical_id;
2293 caps->ext_topo_dev_img_part_num[index] =
2294 (phys_id & ICE_EXT_TOPO_DEV_IMG_PART_NUM_M) >>
2295 ICE_EXT_TOPO_DEV_IMG_PART_NUM_S;
2296 caps->ext_topo_dev_img_load_en[index] =
2297 (phys_id & ICE_EXT_TOPO_DEV_IMG_LOAD_EN) != 0;
2298 caps->ext_topo_dev_img_prog_en[index] =
2299 (phys_id & ICE_EXT_TOPO_DEV_IMG_PROG_EN) != 0;
2300 ice_debug(hw, ICE_DBG_INIT,
2301 "%s: ext_topo_dev_img_ver_high[%d] = %d\n",
2303 caps->ext_topo_dev_img_ver_high[index]);
2304 ice_debug(hw, ICE_DBG_INIT,
2305 "%s: ext_topo_dev_img_ver_low[%d] = %d\n",
2307 caps->ext_topo_dev_img_ver_low[index]);
2308 ice_debug(hw, ICE_DBG_INIT,
2309 "%s: ext_topo_dev_img_part_num[%d] = %d\n",
2311 caps->ext_topo_dev_img_part_num[index]);
2312 ice_debug(hw, ICE_DBG_INIT,
2313 "%s: ext_topo_dev_img_load_en[%d] = %d\n",
2315 caps->ext_topo_dev_img_load_en[index]);
2316 ice_debug(hw, ICE_DBG_INIT,
2317 "%s: ext_topo_dev_img_prog_en[%d] = %d\n",
2319 caps->ext_topo_dev_img_prog_en[index]);
2323 /* Not one of the recognized common capabilities */
2331 * ice_recalc_port_limited_caps - Recalculate port limited capabilities
2332 * @hw: pointer to the HW structure
2333 * @caps: pointer to capabilities structure to fix
2335 * Re-calculate the capabilities that are dependent on the number of physical
2336 * ports; i.e. some features are not supported or function differently on
2337 * devices with more than 4 ports.
2340 ice_recalc_port_limited_caps(struct ice_hw *hw, struct ice_hw_common_caps *caps)
2342 /* This assumes device capabilities are always scanned before function
2343 * capabilities during the initialization flow.
2345 if (hw->dev_caps.num_funcs > 4) {
2346 /* Max 4 TCs per port */
2348 ice_debug(hw, ICE_DBG_INIT, "reducing maxtc to %d (based on #ports)\n",
2354 * ice_parse_vsi_func_caps - Parse ICE_AQC_CAPS_VSI function caps
2355 * @hw: pointer to the HW struct
2356 * @func_p: pointer to function capabilities structure
2357 * @cap: pointer to the capability element to parse
2359 * Extract function capabilities for ICE_AQC_CAPS_VSI.
2362 ice_parse_vsi_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p,
2363 struct ice_aqc_list_caps_elem *cap)
2365 func_p->guar_num_vsi = ice_get_num_per_func(hw, ICE_MAX_VSI);
2366 ice_debug(hw, ICE_DBG_INIT, "func caps: guar_num_vsi (fw) = %d\n",
2367 LE32_TO_CPU(cap->number));
2368 ice_debug(hw, ICE_DBG_INIT, "func caps: guar_num_vsi = %d\n",
2369 func_p->guar_num_vsi);
2373 * ice_parse_1588_func_caps - Parse ICE_AQC_CAPS_1588 function caps
2374 * @hw: pointer to the HW struct
2375 * @func_p: pointer to function capabilities structure
2376 * @cap: pointer to the capability element to parse
2378 * Extract function capabilities for ICE_AQC_CAPS_1588.
2381 ice_parse_1588_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p,
2382 struct ice_aqc_list_caps_elem *cap)
2384 struct ice_ts_func_info *info = &func_p->ts_func_info;
2385 u32 number = LE32_TO_CPU(cap->number);
2387 info->ena = ((number & ICE_TS_FUNC_ENA_M) != 0);
2388 func_p->common_cap.ieee_1588 = info->ena;
2390 info->src_tmr_owned = ((number & ICE_TS_SRC_TMR_OWND_M) != 0);
2391 info->tmr_ena = ((number & ICE_TS_TMR_ENA_M) != 0);
2392 info->tmr_index_owned = ((number & ICE_TS_TMR_IDX_OWND_M) != 0);
2393 info->tmr_index_assoc = ((number & ICE_TS_TMR_IDX_ASSOC_M) != 0);
2395 info->clk_freq = (number & ICE_TS_CLK_FREQ_M) >> ICE_TS_CLK_FREQ_S;
2396 info->clk_src = ((number & ICE_TS_CLK_SRC_M) != 0);
2398 if (info->clk_freq < NUM_ICE_TIME_REF_FREQ) {
2399 info->time_ref = (enum ice_time_ref_freq)info->clk_freq;
2401 /* Unknown clock frequency, so assume a (probably incorrect)
2402 * default to avoid out-of-bounds look ups of frequency
2403 * related information.
2405 ice_debug(hw, ICE_DBG_INIT, "1588 func caps: unknown clock frequency %u\n",
2407 info->time_ref = ICE_TIME_REF_FREQ_25_000;
2410 ice_debug(hw, ICE_DBG_INIT, "func caps: ieee_1588 = %u\n",
2411 func_p->common_cap.ieee_1588);
2412 ice_debug(hw, ICE_DBG_INIT, "func caps: src_tmr_owned = %u\n",
2413 info->src_tmr_owned);
2414 ice_debug(hw, ICE_DBG_INIT, "func caps: tmr_ena = %u\n",
2416 ice_debug(hw, ICE_DBG_INIT, "func caps: tmr_index_owned = %u\n",
2417 info->tmr_index_owned);
2418 ice_debug(hw, ICE_DBG_INIT, "func caps: tmr_index_assoc = %u\n",
2419 info->tmr_index_assoc);
2420 ice_debug(hw, ICE_DBG_INIT, "func caps: clk_freq = %u\n",
2422 ice_debug(hw, ICE_DBG_INIT, "func caps: clk_src = %u\n",
2427 * ice_parse_fdir_func_caps - Parse ICE_AQC_CAPS_FD function caps
2428 * @hw: pointer to the HW struct
2429 * @func_p: pointer to function capabilities structure
2431 * Extract function capabilities for ICE_AQC_CAPS_FD.
2434 ice_parse_fdir_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p)
2438 if (hw->dcf_enabled)
2440 reg_val = rd32(hw, GLQF_FD_SIZE);
2441 val = (reg_val & GLQF_FD_SIZE_FD_GSIZE_M) >>
2442 GLQF_FD_SIZE_FD_GSIZE_S;
2443 func_p->fd_fltr_guar =
2444 ice_get_num_per_func(hw, val);
2445 val = (reg_val & GLQF_FD_SIZE_FD_BSIZE_M) >>
2446 GLQF_FD_SIZE_FD_BSIZE_S;
2447 func_p->fd_fltr_best_effort = val;
2449 ice_debug(hw, ICE_DBG_INIT, "func caps: fd_fltr_guar = %d\n",
2450 func_p->fd_fltr_guar);
2451 ice_debug(hw, ICE_DBG_INIT, "func caps: fd_fltr_best_effort = %d\n",
2452 func_p->fd_fltr_best_effort);
2456 * ice_parse_func_caps - Parse function capabilities
2457 * @hw: pointer to the HW struct
2458 * @func_p: pointer to function capabilities structure
2459 * @buf: buffer containing the function capability records
2460 * @cap_count: the number of capabilities
2462 * Helper function to parse function (0x000A) capabilities list. For
2463 * capabilities shared between device and function, this relies on
2464 * ice_parse_common_caps.
2466 * Loop through the list of provided capabilities and extract the relevant
2467 * data into the function capabilities structured.
2470 ice_parse_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p,
2471 void *buf, u32 cap_count)
2473 struct ice_aqc_list_caps_elem *cap_resp;
2476 cap_resp = (struct ice_aqc_list_caps_elem *)buf;
2478 ice_memset(func_p, 0, sizeof(*func_p), ICE_NONDMA_MEM);
2480 for (i = 0; i < cap_count; i++) {
2481 u16 cap = LE16_TO_CPU(cap_resp[i].cap);
2484 found = ice_parse_common_caps(hw, &func_p->common_cap,
2485 &cap_resp[i], "func caps");
2488 case ICE_AQC_CAPS_VSI:
2489 ice_parse_vsi_func_caps(hw, func_p, &cap_resp[i]);
2491 case ICE_AQC_CAPS_1588:
2492 ice_parse_1588_func_caps(hw, func_p, &cap_resp[i]);
2494 case ICE_AQC_CAPS_FD:
2495 ice_parse_fdir_func_caps(hw, func_p);
2498 /* Don't list common capabilities as unknown */
2500 ice_debug(hw, ICE_DBG_INIT, "func caps: unknown capability[%d]: 0x%x\n",
2506 ice_recalc_port_limited_caps(hw, &func_p->common_cap);
2510 * ice_parse_valid_functions_cap - Parse ICE_AQC_CAPS_VALID_FUNCTIONS caps
2511 * @hw: pointer to the HW struct
2512 * @dev_p: pointer to device capabilities structure
2513 * @cap: capability element to parse
2515 * Parse ICE_AQC_CAPS_VALID_FUNCTIONS for device capabilities.
2518 ice_parse_valid_functions_cap(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p,
2519 struct ice_aqc_list_caps_elem *cap)
2521 u32 number = LE32_TO_CPU(cap->number);
2523 dev_p->num_funcs = ice_hweight32(number);
2524 ice_debug(hw, ICE_DBG_INIT, "dev caps: num_funcs = %d\n",
2529 * ice_parse_vsi_dev_caps - Parse ICE_AQC_CAPS_VSI device caps
2530 * @hw: pointer to the HW struct
2531 * @dev_p: pointer to device capabilities structure
2532 * @cap: capability element to parse
2534 * Parse ICE_AQC_CAPS_VSI for device capabilities.
2537 ice_parse_vsi_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p,
2538 struct ice_aqc_list_caps_elem *cap)
2540 u32 number = LE32_TO_CPU(cap->number);
2542 dev_p->num_vsi_allocd_to_host = number;
2543 ice_debug(hw, ICE_DBG_INIT, "dev caps: num_vsi_allocd_to_host = %d\n",
2544 dev_p->num_vsi_allocd_to_host);
2548 * ice_parse_1588_dev_caps - Parse ICE_AQC_CAPS_1588 device caps
2549 * @hw: pointer to the HW struct
2550 * @dev_p: pointer to device capabilities structure
2551 * @cap: capability element to parse
2553 * Parse ICE_AQC_CAPS_1588 for device capabilities.
2556 ice_parse_1588_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p,
2557 struct ice_aqc_list_caps_elem *cap)
2559 struct ice_ts_dev_info *info = &dev_p->ts_dev_info;
2560 u32 logical_id = LE32_TO_CPU(cap->logical_id);
2561 u32 phys_id = LE32_TO_CPU(cap->phys_id);
2562 u32 number = LE32_TO_CPU(cap->number);
2564 info->ena = ((number & ICE_TS_DEV_ENA_M) != 0);
2565 dev_p->common_cap.ieee_1588 = info->ena;
2567 info->tmr0_owner = number & ICE_TS_TMR0_OWNR_M;
2568 info->tmr0_owned = ((number & ICE_TS_TMR0_OWND_M) != 0);
2569 info->tmr0_ena = ((number & ICE_TS_TMR0_ENA_M) != 0);
2571 info->tmr1_owner = (number & ICE_TS_TMR1_OWNR_M) >> ICE_TS_TMR1_OWNR_S;
2572 info->tmr1_owned = ((number & ICE_TS_TMR1_OWND_M) != 0);
2573 info->tmr1_ena = ((number & ICE_TS_TMR1_ENA_M) != 0);
2575 info->ena_ports = logical_id;
2576 info->tmr_own_map = phys_id;
2578 ice_debug(hw, ICE_DBG_INIT, "dev caps: ieee_1588 = %u\n",
2579 dev_p->common_cap.ieee_1588);
2580 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr0_owner = %u\n",
2582 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr0_owned = %u\n",
2584 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr0_ena = %u\n",
2586 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr1_owner = %u\n",
2588 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr1_owned = %u\n",
2590 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr1_ena = %u\n",
2592 ice_debug(hw, ICE_DBG_INIT, "dev caps: ieee_1588 ena_ports = %u\n",
2594 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr_own_map = %u\n",
2599 * ice_parse_fdir_dev_caps - Parse ICE_AQC_CAPS_FD device caps
2600 * @hw: pointer to the HW struct
2601 * @dev_p: pointer to device capabilities structure
2602 * @cap: capability element to parse
2604 * Parse ICE_AQC_CAPS_FD for device capabilities.
2607 ice_parse_fdir_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p,
2608 struct ice_aqc_list_caps_elem *cap)
2610 u32 number = LE32_TO_CPU(cap->number);
2612 dev_p->num_flow_director_fltr = number;
2613 ice_debug(hw, ICE_DBG_INIT, "dev caps: num_flow_director_fltr = %d\n",
2614 dev_p->num_flow_director_fltr);
2618 * ice_parse_dev_caps - Parse device capabilities
2619 * @hw: pointer to the HW struct
2620 * @dev_p: pointer to device capabilities structure
2621 * @buf: buffer containing the device capability records
2622 * @cap_count: the number of capabilities
2624 * Helper device to parse device (0x000B) capabilities list. For
2625 * capabilities shared between device and function, this relies on
2626 * ice_parse_common_caps.
2628 * Loop through the list of provided capabilities and extract the relevant
2629 * data into the device capabilities structured.
2632 ice_parse_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p,
2633 void *buf, u32 cap_count)
2635 struct ice_aqc_list_caps_elem *cap_resp;
2638 cap_resp = (struct ice_aqc_list_caps_elem *)buf;
2640 ice_memset(dev_p, 0, sizeof(*dev_p), ICE_NONDMA_MEM);
2642 for (i = 0; i < cap_count; i++) {
2643 u16 cap = LE16_TO_CPU(cap_resp[i].cap);
2646 found = ice_parse_common_caps(hw, &dev_p->common_cap,
2647 &cap_resp[i], "dev caps");
2650 case ICE_AQC_CAPS_VALID_FUNCTIONS:
2651 ice_parse_valid_functions_cap(hw, dev_p, &cap_resp[i]);
2653 case ICE_AQC_CAPS_VSI:
2654 ice_parse_vsi_dev_caps(hw, dev_p, &cap_resp[i]);
2656 case ICE_AQC_CAPS_1588:
2657 ice_parse_1588_dev_caps(hw, dev_p, &cap_resp[i]);
2659 case ICE_AQC_CAPS_FD:
2660 ice_parse_fdir_dev_caps(hw, dev_p, &cap_resp[i]);
2663 /* Don't list common capabilities as unknown */
2665 ice_debug(hw, ICE_DBG_INIT, "dev caps: unknown capability[%d]: 0x%x\n",
2671 ice_recalc_port_limited_caps(hw, &dev_p->common_cap);
2675 * ice_aq_list_caps - query function/device capabilities
2676 * @hw: pointer to the HW struct
2677 * @buf: a buffer to hold the capabilities
2678 * @buf_size: size of the buffer
2679 * @cap_count: if not NULL, set to the number of capabilities reported
2680 * @opc: capabilities type to discover, device or function
2681 * @cd: pointer to command details structure or NULL
2683 * Get the function (0x000A) or device (0x000B) capabilities description from
2684 * firmware and store it in the buffer.
2686 * If the cap_count pointer is not NULL, then it is set to the number of
2687 * capabilities firmware will report. Note that if the buffer size is too
2688 * small, it is possible the command will return ICE_AQ_ERR_ENOMEM. The
2689 * cap_count will still be updated in this case. It is recommended that the
2690 * buffer size be set to ICE_AQ_MAX_BUF_LEN (the largest possible buffer that
2691 * firmware could return) to avoid this.
2693 static enum ice_status
2694 ice_aq_list_caps(struct ice_hw *hw, void *buf, u16 buf_size, u32 *cap_count,
2695 enum ice_adminq_opc opc, struct ice_sq_cd *cd)
2697 struct ice_aqc_list_caps *cmd;
2698 struct ice_aq_desc desc;
2699 enum ice_status status;
2701 cmd = &desc.params.get_cap;
2703 if (opc != ice_aqc_opc_list_func_caps &&
2704 opc != ice_aqc_opc_list_dev_caps)
2705 return ICE_ERR_PARAM;
2707 ice_fill_dflt_direct_cmd_desc(&desc, opc);
2708 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);
2711 *cap_count = LE32_TO_CPU(cmd->count);
2717 * ice_discover_dev_caps - Read and extract device capabilities
2718 * @hw: pointer to the hardware structure
2719 * @dev_caps: pointer to device capabilities structure
2721 * Read the device capabilities and extract them into the dev_caps structure
2724 static enum ice_status
2725 ice_discover_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_caps)
2727 enum ice_status status;
2731 cbuf = ice_malloc(hw, ICE_AQ_MAX_BUF_LEN);
2733 return ICE_ERR_NO_MEMORY;
2735 /* Although the driver doesn't know the number of capabilities the
2736 * device will return, we can simply send a 4KB buffer, the maximum
2737 * possible size that firmware can return.
2739 cap_count = ICE_AQ_MAX_BUF_LEN / sizeof(struct ice_aqc_list_caps_elem);
2741 status = ice_aq_list_caps(hw, cbuf, ICE_AQ_MAX_BUF_LEN, &cap_count,
2742 ice_aqc_opc_list_dev_caps, NULL);
2744 ice_parse_dev_caps(hw, dev_caps, cbuf, cap_count);
2751 * ice_discover_func_caps - Read and extract function capabilities
2752 * @hw: pointer to the hardware structure
2753 * @func_caps: pointer to function capabilities structure
2755 * Read the function capabilities and extract them into the func_caps structure
2758 static enum ice_status
2759 ice_discover_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_caps)
2761 enum ice_status status;
2765 cbuf = ice_malloc(hw, ICE_AQ_MAX_BUF_LEN);
2767 return ICE_ERR_NO_MEMORY;
2769 /* Although the driver doesn't know the number of capabilities the
2770 * device will return, we can simply send a 4KB buffer, the maximum
2771 * possible size that firmware can return.
2773 cap_count = ICE_AQ_MAX_BUF_LEN / sizeof(struct ice_aqc_list_caps_elem);
2775 status = ice_aq_list_caps(hw, cbuf, ICE_AQ_MAX_BUF_LEN, &cap_count,
2776 ice_aqc_opc_list_func_caps, NULL);
2778 ice_parse_func_caps(hw, func_caps, cbuf, cap_count);
2785 * ice_set_safe_mode_caps - Override dev/func capabilities when in safe mode
2786 * @hw: pointer to the hardware structure
2788 void ice_set_safe_mode_caps(struct ice_hw *hw)
2790 struct ice_hw_func_caps *func_caps = &hw->func_caps;
2791 struct ice_hw_dev_caps *dev_caps = &hw->dev_caps;
2792 struct ice_hw_common_caps cached_caps;
2795 /* cache some func_caps values that should be restored after memset */
2796 cached_caps = func_caps->common_cap;
2798 /* unset func capabilities */
2799 memset(func_caps, 0, sizeof(*func_caps));
2801 #define ICE_RESTORE_FUNC_CAP(name) \
2802 func_caps->common_cap.name = cached_caps.name
2804 /* restore cached values */
2805 ICE_RESTORE_FUNC_CAP(valid_functions);
2806 ICE_RESTORE_FUNC_CAP(txq_first_id);
2807 ICE_RESTORE_FUNC_CAP(rxq_first_id);
2808 ICE_RESTORE_FUNC_CAP(msix_vector_first_id);
2809 ICE_RESTORE_FUNC_CAP(max_mtu);
2810 ICE_RESTORE_FUNC_CAP(nvm_unified_update);
2812 /* one Tx and one Rx queue in safe mode */
2813 func_caps->common_cap.num_rxq = 1;
2814 func_caps->common_cap.num_txq = 1;
2816 /* two MSIX vectors, one for traffic and one for misc causes */
2817 func_caps->common_cap.num_msix_vectors = 2;
2818 func_caps->guar_num_vsi = 1;
2820 /* cache some dev_caps values that should be restored after memset */
2821 cached_caps = dev_caps->common_cap;
2822 num_funcs = dev_caps->num_funcs;
2824 /* unset dev capabilities */
2825 memset(dev_caps, 0, sizeof(*dev_caps));
2827 #define ICE_RESTORE_DEV_CAP(name) \
2828 dev_caps->common_cap.name = cached_caps.name
2830 /* restore cached values */
2831 ICE_RESTORE_DEV_CAP(valid_functions);
2832 ICE_RESTORE_DEV_CAP(txq_first_id);
2833 ICE_RESTORE_DEV_CAP(rxq_first_id);
2834 ICE_RESTORE_DEV_CAP(msix_vector_first_id);
2835 ICE_RESTORE_DEV_CAP(max_mtu);
2836 ICE_RESTORE_DEV_CAP(nvm_unified_update);
2837 dev_caps->num_funcs = num_funcs;
2839 /* one Tx and one Rx queue per function in safe mode */
2840 dev_caps->common_cap.num_rxq = num_funcs;
2841 dev_caps->common_cap.num_txq = num_funcs;
2843 /* two MSIX vectors per function */
2844 dev_caps->common_cap.num_msix_vectors = 2 * num_funcs;
2848 * ice_get_caps - get info about the HW
2849 * @hw: pointer to the hardware structure
2851 enum ice_status ice_get_caps(struct ice_hw *hw)
2853 enum ice_status status;
2855 status = ice_discover_dev_caps(hw, &hw->dev_caps);
2859 return ice_discover_func_caps(hw, &hw->func_caps);
2863 * ice_aq_manage_mac_write - manage MAC address write command
2864 * @hw: pointer to the HW struct
2865 * @mac_addr: MAC address to be written as LAA/LAA+WoL/Port address
2866 * @flags: flags to control write behavior
2867 * @cd: pointer to command details structure or NULL
2869 * This function is used to write MAC address to the NVM (0x0108).
2872 ice_aq_manage_mac_write(struct ice_hw *hw, const u8 *mac_addr, u8 flags,
2873 struct ice_sq_cd *cd)
2875 struct ice_aqc_manage_mac_write *cmd;
2876 struct ice_aq_desc desc;
2878 cmd = &desc.params.mac_write;
2879 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_write);
2882 ice_memcpy(cmd->mac_addr, mac_addr, ETH_ALEN, ICE_NONDMA_TO_NONDMA);
2884 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
2888 * ice_aq_clear_pxe_mode
2889 * @hw: pointer to the HW struct
2891 * Tell the firmware that the driver is taking over from PXE (0x0110).
2893 static enum ice_status ice_aq_clear_pxe_mode(struct ice_hw *hw)
2895 struct ice_aq_desc desc;
2897 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pxe_mode);
2898 desc.params.clear_pxe.rx_cnt = ICE_AQC_CLEAR_PXE_RX_CNT;
2900 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
2904 * ice_clear_pxe_mode - clear pxe operations mode
2905 * @hw: pointer to the HW struct
2907 * Make sure all PXE mode settings are cleared, including things
2908 * like descriptor fetch/write-back mode.
2910 void ice_clear_pxe_mode(struct ice_hw *hw)
2912 if (ice_check_sq_alive(hw, &hw->adminq))
2913 ice_aq_clear_pxe_mode(hw);
2917 * ice_aq_set_port_params - set physical port parameters.
2918 * @pi: pointer to the port info struct
2919 * @bad_frame_vsi: defines the VSI to which bad frames are forwarded
2920 * @save_bad_pac: if set packets with errors are forwarded to the bad frames VSI
2921 * @pad_short_pac: if set transmit packets smaller than 60 bytes are padded
2922 * @double_vlan: if set double VLAN is enabled
2923 * @cd: pointer to command details structure or NULL
2925 * Set Physical port parameters (0x0203)
2928 ice_aq_set_port_params(struct ice_port_info *pi, u16 bad_frame_vsi,
2929 bool save_bad_pac, bool pad_short_pac, bool double_vlan,
2930 struct ice_sq_cd *cd)
2933 struct ice_aqc_set_port_params *cmd;
2934 struct ice_hw *hw = pi->hw;
2935 struct ice_aq_desc desc;
2938 cmd = &desc.params.set_port_params;
2940 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_port_params);
2941 cmd->bad_frame_vsi = CPU_TO_LE16(bad_frame_vsi);
2943 cmd_flags |= ICE_AQC_SET_P_PARAMS_SAVE_BAD_PACKETS;
2945 cmd_flags |= ICE_AQC_SET_P_PARAMS_PAD_SHORT_PACKETS;
2947 cmd_flags |= ICE_AQC_SET_P_PARAMS_DOUBLE_VLAN_ENA;
2948 cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
2950 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
2954 * ice_get_link_speed_based_on_phy_type - returns link speed
2955 * @phy_type_low: lower part of phy_type
2956 * @phy_type_high: higher part of phy_type
2958 * This helper function will convert an entry in PHY type structure
2959 * [phy_type_low, phy_type_high] to its corresponding link speed.
2960 * Note: In the structure of [phy_type_low, phy_type_high], there should
2961 * be one bit set, as this function will convert one PHY type to its
2963 * If no bit gets set, ICE_LINK_SPEED_UNKNOWN will be returned
2964 * If more than one bit gets set, ICE_LINK_SPEED_UNKNOWN will be returned
2967 ice_get_link_speed_based_on_phy_type(u64 phy_type_low, u64 phy_type_high)
2969 u16 speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN;
2970 u16 speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN;
2972 switch (phy_type_low) {
2973 case ICE_PHY_TYPE_LOW_100BASE_TX:
2974 case ICE_PHY_TYPE_LOW_100M_SGMII:
2975 speed_phy_type_low = ICE_AQ_LINK_SPEED_100MB;
2977 case ICE_PHY_TYPE_LOW_1000BASE_T:
2978 case ICE_PHY_TYPE_LOW_1000BASE_SX:
2979 case ICE_PHY_TYPE_LOW_1000BASE_LX:
2980 case ICE_PHY_TYPE_LOW_1000BASE_KX:
2981 case ICE_PHY_TYPE_LOW_1G_SGMII:
2982 speed_phy_type_low = ICE_AQ_LINK_SPEED_1000MB;
2984 case ICE_PHY_TYPE_LOW_2500BASE_T:
2985 case ICE_PHY_TYPE_LOW_2500BASE_X:
2986 case ICE_PHY_TYPE_LOW_2500BASE_KX:
2987 speed_phy_type_low = ICE_AQ_LINK_SPEED_2500MB;
2989 case ICE_PHY_TYPE_LOW_5GBASE_T:
2990 case ICE_PHY_TYPE_LOW_5GBASE_KR:
2991 speed_phy_type_low = ICE_AQ_LINK_SPEED_5GB;
2993 case ICE_PHY_TYPE_LOW_10GBASE_T:
2994 case ICE_PHY_TYPE_LOW_10G_SFI_DA:
2995 case ICE_PHY_TYPE_LOW_10GBASE_SR:
2996 case ICE_PHY_TYPE_LOW_10GBASE_LR:
2997 case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1:
2998 case ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC:
2999 case ICE_PHY_TYPE_LOW_10G_SFI_C2C:
3000 speed_phy_type_low = ICE_AQ_LINK_SPEED_10GB;
3002 case ICE_PHY_TYPE_LOW_25GBASE_T:
3003 case ICE_PHY_TYPE_LOW_25GBASE_CR:
3004 case ICE_PHY_TYPE_LOW_25GBASE_CR_S:
3005 case ICE_PHY_TYPE_LOW_25GBASE_CR1:
3006 case ICE_PHY_TYPE_LOW_25GBASE_SR:
3007 case ICE_PHY_TYPE_LOW_25GBASE_LR:
3008 case ICE_PHY_TYPE_LOW_25GBASE_KR:
3009 case ICE_PHY_TYPE_LOW_25GBASE_KR_S:
3010 case ICE_PHY_TYPE_LOW_25GBASE_KR1:
3011 case ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC:
3012 case ICE_PHY_TYPE_LOW_25G_AUI_C2C:
3013 speed_phy_type_low = ICE_AQ_LINK_SPEED_25GB;
3015 case ICE_PHY_TYPE_LOW_40GBASE_CR4:
3016 case ICE_PHY_TYPE_LOW_40GBASE_SR4:
3017 case ICE_PHY_TYPE_LOW_40GBASE_LR4:
3018 case ICE_PHY_TYPE_LOW_40GBASE_KR4:
3019 case ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC:
3020 case ICE_PHY_TYPE_LOW_40G_XLAUI:
3021 speed_phy_type_low = ICE_AQ_LINK_SPEED_40GB;
3023 case ICE_PHY_TYPE_LOW_50GBASE_CR2:
3024 case ICE_PHY_TYPE_LOW_50GBASE_SR2:
3025 case ICE_PHY_TYPE_LOW_50GBASE_LR2:
3026 case ICE_PHY_TYPE_LOW_50GBASE_KR2:
3027 case ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC:
3028 case ICE_PHY_TYPE_LOW_50G_LAUI2:
3029 case ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC:
3030 case ICE_PHY_TYPE_LOW_50G_AUI2:
3031 case ICE_PHY_TYPE_LOW_50GBASE_CP:
3032 case ICE_PHY_TYPE_LOW_50GBASE_SR:
3033 case ICE_PHY_TYPE_LOW_50GBASE_FR:
3034 case ICE_PHY_TYPE_LOW_50GBASE_LR:
3035 case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4:
3036 case ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC:
3037 case ICE_PHY_TYPE_LOW_50G_AUI1:
3038 speed_phy_type_low = ICE_AQ_LINK_SPEED_50GB;
3040 case ICE_PHY_TYPE_LOW_100GBASE_CR4:
3041 case ICE_PHY_TYPE_LOW_100GBASE_SR4:
3042 case ICE_PHY_TYPE_LOW_100GBASE_LR4:
3043 case ICE_PHY_TYPE_LOW_100GBASE_KR4:
3044 case ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC:
3045 case ICE_PHY_TYPE_LOW_100G_CAUI4:
3046 case ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC:
3047 case ICE_PHY_TYPE_LOW_100G_AUI4:
3048 case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4:
3049 case ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4:
3050 case ICE_PHY_TYPE_LOW_100GBASE_CP2:
3051 case ICE_PHY_TYPE_LOW_100GBASE_SR2:
3052 case ICE_PHY_TYPE_LOW_100GBASE_DR:
3053 speed_phy_type_low = ICE_AQ_LINK_SPEED_100GB;
3056 speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN;
3060 switch (phy_type_high) {
3061 case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4:
3062 case ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC:
3063 case ICE_PHY_TYPE_HIGH_100G_CAUI2:
3064 case ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC:
3065 case ICE_PHY_TYPE_HIGH_100G_AUI2:
3066 speed_phy_type_high = ICE_AQ_LINK_SPEED_100GB;
3069 speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN;
3073 if (speed_phy_type_low == ICE_AQ_LINK_SPEED_UNKNOWN &&
3074 speed_phy_type_high == ICE_AQ_LINK_SPEED_UNKNOWN)
3075 return ICE_AQ_LINK_SPEED_UNKNOWN;
3076 else if (speed_phy_type_low != ICE_AQ_LINK_SPEED_UNKNOWN &&
3077 speed_phy_type_high != ICE_AQ_LINK_SPEED_UNKNOWN)
3078 return ICE_AQ_LINK_SPEED_UNKNOWN;
3079 else if (speed_phy_type_low != ICE_AQ_LINK_SPEED_UNKNOWN &&
3080 speed_phy_type_high == ICE_AQ_LINK_SPEED_UNKNOWN)
3081 return speed_phy_type_low;
3083 return speed_phy_type_high;
3087 * ice_update_phy_type
3088 * @phy_type_low: pointer to the lower part of phy_type
3089 * @phy_type_high: pointer to the higher part of phy_type
3090 * @link_speeds_bitmap: targeted link speeds bitmap
3092 * Note: For the link_speeds_bitmap structure, you can check it at
3093 * [ice_aqc_get_link_status->link_speed]. Caller can pass in
3094 * link_speeds_bitmap include multiple speeds.
3096 * Each entry in this [phy_type_low, phy_type_high] structure will
3097 * present a certain link speed. This helper function will turn on bits
3098 * in [phy_type_low, phy_type_high] structure based on the value of
3099 * link_speeds_bitmap input parameter.
3102 ice_update_phy_type(u64 *phy_type_low, u64 *phy_type_high,
3103 u16 link_speeds_bitmap)
3110 /* We first check with low part of phy_type */
3111 for (index = 0; index <= ICE_PHY_TYPE_LOW_MAX_INDEX; index++) {
3112 pt_low = BIT_ULL(index);
3113 speed = ice_get_link_speed_based_on_phy_type(pt_low, 0);
3115 if (link_speeds_bitmap & speed)
3116 *phy_type_low |= BIT_ULL(index);
3119 /* We then check with high part of phy_type */
3120 for (index = 0; index <= ICE_PHY_TYPE_HIGH_MAX_INDEX; index++) {
3121 pt_high = BIT_ULL(index);
3122 speed = ice_get_link_speed_based_on_phy_type(0, pt_high);
3124 if (link_speeds_bitmap & speed)
3125 *phy_type_high |= BIT_ULL(index);
3130 * ice_aq_set_phy_cfg
3131 * @hw: pointer to the HW struct
3132 * @pi: port info structure of the interested logical port
3133 * @cfg: structure with PHY configuration data to be set
3134 * @cd: pointer to command details structure or NULL
3136 * Set the various PHY configuration parameters supported on the Port.
3137 * One or more of the Set PHY config parameters may be ignored in an MFP
3138 * mode as the PF may not have the privilege to set some of the PHY Config
3139 * parameters. This status will be indicated by the command response (0x0601).
3142 ice_aq_set_phy_cfg(struct ice_hw *hw, struct ice_port_info *pi,
3143 struct ice_aqc_set_phy_cfg_data *cfg, struct ice_sq_cd *cd)
3145 struct ice_aq_desc desc;
3146 enum ice_status status;
3149 return ICE_ERR_PARAM;
3151 /* Ensure that only valid bits of cfg->caps can be turned on. */
3152 if (cfg->caps & ~ICE_AQ_PHY_ENA_VALID_MASK) {
3153 ice_debug(hw, ICE_DBG_PHY, "Invalid bit is set in ice_aqc_set_phy_cfg_data->caps : 0x%x\n",
3156 cfg->caps &= ICE_AQ_PHY_ENA_VALID_MASK;
3159 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_phy_cfg);
3160 desc.params.set_phy.lport_num = pi->lport;
3161 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
3163 ice_debug(hw, ICE_DBG_LINK, "set phy cfg\n");
3164 ice_debug(hw, ICE_DBG_LINK, " phy_type_low = 0x%llx\n",
3165 (unsigned long long)LE64_TO_CPU(cfg->phy_type_low));
3166 ice_debug(hw, ICE_DBG_LINK, " phy_type_high = 0x%llx\n",
3167 (unsigned long long)LE64_TO_CPU(cfg->phy_type_high));
3168 ice_debug(hw, ICE_DBG_LINK, " caps = 0x%x\n", cfg->caps);
3169 ice_debug(hw, ICE_DBG_LINK, " low_power_ctrl_an = 0x%x\n",
3170 cfg->low_power_ctrl_an);
3171 ice_debug(hw, ICE_DBG_LINK, " eee_cap = 0x%x\n", cfg->eee_cap);
3172 ice_debug(hw, ICE_DBG_LINK, " eeer_value = 0x%x\n", cfg->eeer_value);
3173 ice_debug(hw, ICE_DBG_LINK, " link_fec_opt = 0x%x\n",
3176 status = ice_aq_send_cmd(hw, &desc, cfg, sizeof(*cfg), cd);
3178 if (hw->adminq.sq_last_status == ICE_AQ_RC_EMODE)
3179 status = ICE_SUCCESS;
3182 pi->phy.curr_user_phy_cfg = *cfg;
3188 * ice_update_link_info - update status of the HW network link
3189 * @pi: port info structure of the interested logical port
3191 enum ice_status ice_update_link_info(struct ice_port_info *pi)
3193 struct ice_link_status *li;
3194 enum ice_status status;
3197 return ICE_ERR_PARAM;
3199 li = &pi->phy.link_info;
3201 status = ice_aq_get_link_info(pi, true, NULL, NULL);
3205 if (li->link_info & ICE_AQ_MEDIA_AVAILABLE) {
3206 struct ice_aqc_get_phy_caps_data *pcaps;
3210 pcaps = (struct ice_aqc_get_phy_caps_data *)
3211 ice_malloc(hw, sizeof(*pcaps));
3213 return ICE_ERR_NO_MEMORY;
3215 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_TOPO_CAP_MEDIA,
3218 if (status == ICE_SUCCESS)
3219 ice_memcpy(li->module_type, &pcaps->module_type,
3220 sizeof(li->module_type),
3221 ICE_NONDMA_TO_NONDMA);
3223 ice_free(hw, pcaps);
3230 * ice_cache_phy_user_req
3231 * @pi: port information structure
3232 * @cache_data: PHY logging data
3233 * @cache_mode: PHY logging mode
3235 * Log the user request on (FC, FEC, SPEED) for later user.
3238 ice_cache_phy_user_req(struct ice_port_info *pi,
3239 struct ice_phy_cache_mode_data cache_data,
3240 enum ice_phy_cache_mode cache_mode)
3245 switch (cache_mode) {
3247 pi->phy.curr_user_fc_req = cache_data.data.curr_user_fc_req;
3249 case ICE_SPEED_MODE:
3250 pi->phy.curr_user_speed_req =
3251 cache_data.data.curr_user_speed_req;
3254 pi->phy.curr_user_fec_req = cache_data.data.curr_user_fec_req;
3262 * ice_caps_to_fc_mode
3263 * @caps: PHY capabilities
3265 * Convert PHY FC capabilities to ice FC mode
3267 enum ice_fc_mode ice_caps_to_fc_mode(u8 caps)
3269 if (caps & ICE_AQC_PHY_EN_TX_LINK_PAUSE &&
3270 caps & ICE_AQC_PHY_EN_RX_LINK_PAUSE)
3273 if (caps & ICE_AQC_PHY_EN_TX_LINK_PAUSE)
3274 return ICE_FC_TX_PAUSE;
3276 if (caps & ICE_AQC_PHY_EN_RX_LINK_PAUSE)
3277 return ICE_FC_RX_PAUSE;
3283 * ice_caps_to_fec_mode
3284 * @caps: PHY capabilities
3285 * @fec_options: Link FEC options
3287 * Convert PHY FEC capabilities to ice FEC mode
3289 enum ice_fec_mode ice_caps_to_fec_mode(u8 caps, u8 fec_options)
3291 if (caps & ICE_AQC_PHY_EN_AUTO_FEC)
3292 return ICE_FEC_AUTO;
3294 if (fec_options & (ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN |
3295 ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ |
3296 ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN |
3297 ICE_AQC_PHY_FEC_25G_KR_REQ))
3298 return ICE_FEC_BASER;
3300 if (fec_options & (ICE_AQC_PHY_FEC_25G_RS_528_REQ |
3301 ICE_AQC_PHY_FEC_25G_RS_544_REQ |
3302 ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN))
3305 return ICE_FEC_NONE;
3309 * ice_cfg_phy_fc - Configure PHY FC data based on FC mode
3310 * @pi: port information structure
3311 * @cfg: PHY configuration data to set FC mode
3312 * @req_mode: FC mode to configure
3314 static enum ice_status
3315 ice_cfg_phy_fc(struct ice_port_info *pi, struct ice_aqc_set_phy_cfg_data *cfg,
3316 enum ice_fc_mode req_mode)
3318 struct ice_phy_cache_mode_data cache_data;
3319 u8 pause_mask = 0x0;
3322 return ICE_ERR_BAD_PTR;
3327 struct ice_aqc_get_phy_caps_data *pcaps;
3328 enum ice_status status;
3330 pcaps = (struct ice_aqc_get_phy_caps_data *)
3331 ice_malloc(pi->hw, sizeof(*pcaps));
3333 return ICE_ERR_NO_MEMORY;
3335 /* Query the value of FC that both the NIC and attached media
3338 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_TOPO_CAP_MEDIA,
3341 ice_free(pi->hw, pcaps);
3345 pause_mask |= pcaps->caps & ICE_AQC_PHY_EN_TX_LINK_PAUSE;
3346 pause_mask |= pcaps->caps & ICE_AQC_PHY_EN_RX_LINK_PAUSE;
3348 ice_free(pi->hw, pcaps);
3352 pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE;
3353 pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE;
3355 case ICE_FC_RX_PAUSE:
3356 pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE;
3358 case ICE_FC_TX_PAUSE:
3359 pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE;
3365 /* clear the old pause settings */
3366 cfg->caps &= ~(ICE_AQC_PHY_EN_TX_LINK_PAUSE |
3367 ICE_AQC_PHY_EN_RX_LINK_PAUSE);
3369 /* set the new capabilities */
3370 cfg->caps |= pause_mask;
3372 /* Cache user FC request */
3373 cache_data.data.curr_user_fc_req = req_mode;
3374 ice_cache_phy_user_req(pi, cache_data, ICE_FC_MODE);
3381 * @pi: port information structure
3382 * @aq_failures: pointer to status code, specific to ice_set_fc routine
3383 * @ena_auto_link_update: enable automatic link update
3385 * Set the requested flow control mode.
3388 ice_set_fc(struct ice_port_info *pi, u8 *aq_failures, bool ena_auto_link_update)
3390 struct ice_aqc_set_phy_cfg_data cfg = { 0 };
3391 struct ice_aqc_get_phy_caps_data *pcaps;
3392 enum ice_status status;
3395 if (!pi || !aq_failures)
3396 return ICE_ERR_BAD_PTR;
3401 pcaps = (struct ice_aqc_get_phy_caps_data *)
3402 ice_malloc(hw, sizeof(*pcaps));
3404 return ICE_ERR_NO_MEMORY;
3406 /* Get the current PHY config */
3407 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_ACTIVE_CFG,
3411 *aq_failures = ICE_SET_FC_AQ_FAIL_GET;
3415 ice_copy_phy_caps_to_cfg(pi, pcaps, &cfg);
3417 /* Configure the set PHY data */
3418 status = ice_cfg_phy_fc(pi, &cfg, pi->fc.req_mode);
3420 if (status != ICE_ERR_BAD_PTR)
3421 *aq_failures = ICE_SET_FC_AQ_FAIL_GET;
3426 /* If the capabilities have changed, then set the new config */
3427 if (cfg.caps != pcaps->caps) {
3428 int retry_count, retry_max = 10;
3430 /* Auto restart link so settings take effect */
3431 if (ena_auto_link_update)
3432 cfg.caps |= ICE_AQ_PHY_ENA_AUTO_LINK_UPDT;
3434 status = ice_aq_set_phy_cfg(hw, pi, &cfg, NULL);
3436 *aq_failures = ICE_SET_FC_AQ_FAIL_SET;
3440 /* Update the link info
3441 * It sometimes takes a really long time for link to
3442 * come back from the atomic reset. Thus, we wait a
3445 for (retry_count = 0; retry_count < retry_max; retry_count++) {
3446 status = ice_update_link_info(pi);
3448 if (status == ICE_SUCCESS)
3451 ice_msec_delay(100, true);
3455 *aq_failures = ICE_SET_FC_AQ_FAIL_UPDATE;
3459 ice_free(hw, pcaps);
3464 * ice_phy_caps_equals_cfg
3465 * @phy_caps: PHY capabilities
3466 * @phy_cfg: PHY configuration
3468 * Helper function to determine if PHY capabilities matches PHY
3472 ice_phy_caps_equals_cfg(struct ice_aqc_get_phy_caps_data *phy_caps,
3473 struct ice_aqc_set_phy_cfg_data *phy_cfg)
3475 u8 caps_mask, cfg_mask;
3477 if (!phy_caps || !phy_cfg)
3480 /* These bits are not common between capabilities and configuration.
3481 * Do not use them to determine equality.
3483 caps_mask = ICE_AQC_PHY_CAPS_MASK & ~(ICE_AQC_PHY_AN_MODE |
3484 ICE_AQC_PHY_EN_MOD_QUAL);
3485 cfg_mask = ICE_AQ_PHY_ENA_VALID_MASK & ~ICE_AQ_PHY_ENA_AUTO_LINK_UPDT;
3487 if (phy_caps->phy_type_low != phy_cfg->phy_type_low ||
3488 phy_caps->phy_type_high != phy_cfg->phy_type_high ||
3489 ((phy_caps->caps & caps_mask) != (phy_cfg->caps & cfg_mask)) ||
3490 phy_caps->low_power_ctrl_an != phy_cfg->low_power_ctrl_an ||
3491 phy_caps->eee_cap != phy_cfg->eee_cap ||
3492 phy_caps->eeer_value != phy_cfg->eeer_value ||
3493 phy_caps->link_fec_options != phy_cfg->link_fec_opt)
3500 * ice_copy_phy_caps_to_cfg - Copy PHY ability data to configuration data
3501 * @pi: port information structure
3502 * @caps: PHY ability structure to copy date from
3503 * @cfg: PHY configuration structure to copy data to
3505 * Helper function to copy AQC PHY get ability data to PHY set configuration
3509 ice_copy_phy_caps_to_cfg(struct ice_port_info *pi,
3510 struct ice_aqc_get_phy_caps_data *caps,
3511 struct ice_aqc_set_phy_cfg_data *cfg)
3513 if (!pi || !caps || !cfg)
3516 ice_memset(cfg, 0, sizeof(*cfg), ICE_NONDMA_MEM);
3517 cfg->phy_type_low = caps->phy_type_low;
3518 cfg->phy_type_high = caps->phy_type_high;
3519 cfg->caps = caps->caps;
3520 cfg->low_power_ctrl_an = caps->low_power_ctrl_an;
3521 cfg->eee_cap = caps->eee_cap;
3522 cfg->eeer_value = caps->eeer_value;
3523 cfg->link_fec_opt = caps->link_fec_options;
3524 cfg->module_compliance_enforcement =
3525 caps->module_compliance_enforcement;
3529 * ice_cfg_phy_fec - Configure PHY FEC data based on FEC mode
3530 * @pi: port information structure
3531 * @cfg: PHY configuration data to set FEC mode
3532 * @fec: FEC mode to configure
3535 ice_cfg_phy_fec(struct ice_port_info *pi, struct ice_aqc_set_phy_cfg_data *cfg,
3536 enum ice_fec_mode fec)
3538 struct ice_aqc_get_phy_caps_data *pcaps;
3539 enum ice_status status = ICE_SUCCESS;
3543 return ICE_ERR_BAD_PTR;
3547 pcaps = (struct ice_aqc_get_phy_caps_data *)
3548 ice_malloc(hw, sizeof(*pcaps));
3550 return ICE_ERR_NO_MEMORY;
3552 status = ice_aq_get_phy_caps(pi, false,
3553 (ice_fw_supports_report_dflt_cfg(hw) ?
3554 ICE_AQC_REPORT_DFLT_CFG :
3555 ICE_AQC_REPORT_TOPO_CAP_MEDIA), pcaps, NULL);
3560 cfg->caps |= (pcaps->caps & ICE_AQC_PHY_EN_AUTO_FEC);
3561 cfg->link_fec_opt = pcaps->link_fec_options;
3565 /* Clear RS bits, and AND BASE-R ability
3566 * bits and OR request bits.
3568 cfg->link_fec_opt &= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN |
3569 ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN;
3570 cfg->link_fec_opt |= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ |
3571 ICE_AQC_PHY_FEC_25G_KR_REQ;
3574 /* Clear BASE-R bits, and AND RS ability
3575 * bits and OR request bits.
3577 cfg->link_fec_opt &= ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN;
3578 cfg->link_fec_opt |= ICE_AQC_PHY_FEC_25G_RS_528_REQ |
3579 ICE_AQC_PHY_FEC_25G_RS_544_REQ;
3582 /* Clear all FEC option bits. */
3583 cfg->link_fec_opt &= ~ICE_AQC_PHY_FEC_MASK;
3586 /* AND auto FEC bit, and all caps bits. */
3587 cfg->caps &= ICE_AQC_PHY_CAPS_MASK;
3588 cfg->link_fec_opt |= pcaps->link_fec_options;
3591 status = ICE_ERR_PARAM;
3595 if (fec == ICE_FEC_AUTO && ice_fw_supports_link_override(pi->hw) &&
3596 !ice_fw_supports_report_dflt_cfg(pi->hw)) {
3597 struct ice_link_default_override_tlv tlv;
3599 if (ice_get_link_default_override(&tlv, pi))
3602 if (!(tlv.options & ICE_LINK_OVERRIDE_STRICT_MODE) &&
3603 (tlv.options & ICE_LINK_OVERRIDE_EN))
3604 cfg->link_fec_opt = tlv.fec_options;
3608 ice_free(hw, pcaps);
3614 * ice_get_link_status - get status of the HW network link
3615 * @pi: port information structure
3616 * @link_up: pointer to bool (true/false = linkup/linkdown)
3618 * Variable link_up is true if link is up, false if link is down.
3619 * The variable link_up is invalid if status is non zero. As a
3620 * result of this call, link status reporting becomes enabled
3622 enum ice_status ice_get_link_status(struct ice_port_info *pi, bool *link_up)
3624 struct ice_phy_info *phy_info;
3625 enum ice_status status = ICE_SUCCESS;
3627 if (!pi || !link_up)
3628 return ICE_ERR_PARAM;
3630 phy_info = &pi->phy;
3632 if (phy_info->get_link_info) {
3633 status = ice_update_link_info(pi);
3636 ice_debug(pi->hw, ICE_DBG_LINK, "get link status error, status = %d\n",
3640 *link_up = phy_info->link_info.link_info & ICE_AQ_LINK_UP;
3646 * ice_aq_set_link_restart_an
3647 * @pi: pointer to the port information structure
3648 * @ena_link: if true: enable link, if false: disable link
3649 * @cd: pointer to command details structure or NULL
3651 * Sets up the link and restarts the Auto-Negotiation over the link.
3654 ice_aq_set_link_restart_an(struct ice_port_info *pi, bool ena_link,
3655 struct ice_sq_cd *cd)
3657 struct ice_aqc_restart_an *cmd;
3658 struct ice_aq_desc desc;
3660 cmd = &desc.params.restart_an;
3662 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_restart_an);
3664 cmd->cmd_flags = ICE_AQC_RESTART_AN_LINK_RESTART;
3665 cmd->lport_num = pi->lport;
3667 cmd->cmd_flags |= ICE_AQC_RESTART_AN_LINK_ENABLE;
3669 cmd->cmd_flags &= ~ICE_AQC_RESTART_AN_LINK_ENABLE;
3671 return ice_aq_send_cmd(pi->hw, &desc, NULL, 0, cd);
3675 * ice_aq_set_event_mask
3676 * @hw: pointer to the HW struct
3677 * @port_num: port number of the physical function
3678 * @mask: event mask to be set
3679 * @cd: pointer to command details structure or NULL
3681 * Set event mask (0x0613)
3684 ice_aq_set_event_mask(struct ice_hw *hw, u8 port_num, u16 mask,
3685 struct ice_sq_cd *cd)
3687 struct ice_aqc_set_event_mask *cmd;
3688 struct ice_aq_desc desc;
3690 cmd = &desc.params.set_event_mask;
3692 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_event_mask);
3694 cmd->lport_num = port_num;
3696 cmd->event_mask = CPU_TO_LE16(mask);
3697 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
3701 * ice_aq_set_mac_loopback
3702 * @hw: pointer to the HW struct
3703 * @ena_lpbk: Enable or Disable loopback
3704 * @cd: pointer to command details structure or NULL
3706 * Enable/disable loopback on a given port
3709 ice_aq_set_mac_loopback(struct ice_hw *hw, bool ena_lpbk, struct ice_sq_cd *cd)
3711 struct ice_aqc_set_mac_lb *cmd;
3712 struct ice_aq_desc desc;
3714 cmd = &desc.params.set_mac_lb;
3716 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_mac_lb);
3718 cmd->lb_mode = ICE_AQ_MAC_LB_EN;
3720 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
3724 * ice_aq_set_port_id_led
3725 * @pi: pointer to the port information
3726 * @is_orig_mode: is this LED set to original mode (by the net-list)
3727 * @cd: pointer to command details structure or NULL
3729 * Set LED value for the given port (0x06e9)
3732 ice_aq_set_port_id_led(struct ice_port_info *pi, bool is_orig_mode,
3733 struct ice_sq_cd *cd)
3735 struct ice_aqc_set_port_id_led *cmd;
3736 struct ice_hw *hw = pi->hw;
3737 struct ice_aq_desc desc;
3739 cmd = &desc.params.set_port_id_led;
3741 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_port_id_led);
3744 cmd->ident_mode = ICE_AQC_PORT_IDENT_LED_ORIG;
3746 cmd->ident_mode = ICE_AQC_PORT_IDENT_LED_BLINK;
3748 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
3753 * @hw: pointer to the HW struct
3754 * @lport: bits [7:0] = logical port, bit [8] = logical port valid
3755 * @bus_addr: I2C bus address of the eeprom (typically 0xA0, 0=topo default)
3756 * @mem_addr: I2C offset. lower 8 bits for address, 8 upper bits zero padding.
3758 * @set_page: set or ignore the page
3759 * @data: pointer to data buffer to be read/written to the I2C device.
3760 * @length: 1-16 for read, 1 for write.
3761 * @write: 0 read, 1 for write.
3762 * @cd: pointer to command details structure or NULL
3764 * Read/Write SFF EEPROM (0x06EE)
3767 ice_aq_sff_eeprom(struct ice_hw *hw, u16 lport, u8 bus_addr,
3768 u16 mem_addr, u8 page, u8 set_page, u8 *data, u8 length,
3769 bool write, struct ice_sq_cd *cd)
3771 struct ice_aqc_sff_eeprom *cmd;
3772 struct ice_aq_desc desc;
3773 enum ice_status status;
3775 if (!data || (mem_addr & 0xff00))
3776 return ICE_ERR_PARAM;
3778 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_sff_eeprom);
3779 cmd = &desc.params.read_write_sff_param;
3780 desc.flags = CPU_TO_LE16(ICE_AQ_FLAG_RD);
3781 cmd->lport_num = (u8)(lport & 0xff);
3782 cmd->lport_num_valid = (u8)((lport >> 8) & 0x01);
3783 cmd->i2c_bus_addr = CPU_TO_LE16(((bus_addr >> 1) &
3784 ICE_AQC_SFF_I2CBUS_7BIT_M) |
3786 ICE_AQC_SFF_SET_EEPROM_PAGE_S) &
3787 ICE_AQC_SFF_SET_EEPROM_PAGE_M));
3788 cmd->i2c_mem_addr = CPU_TO_LE16(mem_addr & 0xff);
3789 cmd->eeprom_page = CPU_TO_LE16((u16)page << ICE_AQC_SFF_EEPROM_PAGE_S);
3791 cmd->i2c_bus_addr |= CPU_TO_LE16(ICE_AQC_SFF_IS_WRITE);
3793 status = ice_aq_send_cmd(hw, &desc, data, length, cd);
3798 * ice_aq_prog_topo_dev_nvm
3799 * @hw: pointer to the hardware structure
3800 * @topo_params: pointer to structure storing topology parameters for a device
3801 * @cd: pointer to command details structure or NULL
3803 * Program Topology Device NVM (0x06F2)
3807 ice_aq_prog_topo_dev_nvm(struct ice_hw *hw,
3808 struct ice_aqc_link_topo_params *topo_params,
3809 struct ice_sq_cd *cd)
3811 struct ice_aqc_prog_topo_dev_nvm *cmd;
3812 struct ice_aq_desc desc;
3814 cmd = &desc.params.prog_topo_dev_nvm;
3816 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_prog_topo_dev_nvm);
3818 ice_memcpy(&cmd->topo_params, topo_params, sizeof(*topo_params),
3819 ICE_NONDMA_TO_NONDMA);
3821 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
3825 * ice_aq_read_topo_dev_nvm
3826 * @hw: pointer to the hardware structure
3827 * @topo_params: pointer to structure storing topology parameters for a device
3828 * @start_address: byte offset in the topology device NVM
3829 * @data: pointer to data buffer
3830 * @data_size: number of bytes to be read from the topology device NVM
3831 * @cd: pointer to command details structure or NULL
3832 * Read Topology Device NVM (0x06F3)
3836 ice_aq_read_topo_dev_nvm(struct ice_hw *hw,
3837 struct ice_aqc_link_topo_params *topo_params,
3838 u32 start_address, u8 *data, u8 data_size,
3839 struct ice_sq_cd *cd)
3841 struct ice_aqc_read_topo_dev_nvm *cmd;
3842 struct ice_aq_desc desc;
3843 enum ice_status status;
3845 if (!data || data_size == 0 ||
3846 data_size > ICE_AQC_READ_TOPO_DEV_NVM_DATA_READ_SIZE)
3847 return ICE_ERR_PARAM;
3849 cmd = &desc.params.read_topo_dev_nvm;
3851 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_read_topo_dev_nvm);
3853 desc.datalen = data_size;
3854 ice_memcpy(&cmd->topo_params, topo_params, sizeof(*topo_params),
3855 ICE_NONDMA_TO_NONDMA);
3856 cmd->start_address = CPU_TO_LE32(start_address);
3858 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
3862 ice_memcpy(data, cmd->data_read, data_size, ICE_NONDMA_TO_NONDMA);
3868 * __ice_aq_get_set_rss_lut
3869 * @hw: pointer to the hardware structure
3870 * @params: RSS LUT parameters
3871 * @set: set true to set the table, false to get the table
3873 * Internal function to get (0x0B05) or set (0x0B03) RSS look up table
3875 static enum ice_status
3876 __ice_aq_get_set_rss_lut(struct ice_hw *hw, struct ice_aq_get_set_rss_lut_params *params, bool set)
3878 u16 flags = 0, vsi_id, lut_type, lut_size, glob_lut_idx, vsi_handle;
3879 struct ice_aqc_get_set_rss_lut *cmd_resp;
3880 struct ice_aq_desc desc;
3881 enum ice_status status;
3885 return ICE_ERR_PARAM;
3887 vsi_handle = params->vsi_handle;
3890 if (!ice_is_vsi_valid(hw, vsi_handle) || !lut)
3891 return ICE_ERR_PARAM;
3893 lut_size = params->lut_size;
3894 lut_type = params->lut_type;
3895 glob_lut_idx = params->global_lut_id;
3896 vsi_id = ice_get_hw_vsi_num(hw, vsi_handle);
3898 cmd_resp = &desc.params.get_set_rss_lut;
3901 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_rss_lut);
3902 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
3904 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_rss_lut);
3907 cmd_resp->vsi_id = CPU_TO_LE16(((vsi_id <<
3908 ICE_AQC_GSET_RSS_LUT_VSI_ID_S) &
3909 ICE_AQC_GSET_RSS_LUT_VSI_ID_M) |
3910 ICE_AQC_GSET_RSS_LUT_VSI_VALID);
3913 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_VSI:
3914 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF:
3915 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL:
3916 flags |= ((lut_type << ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S) &
3917 ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_M);
3920 status = ICE_ERR_PARAM;
3921 goto ice_aq_get_set_rss_lut_exit;
3924 if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL) {
3925 flags |= ((glob_lut_idx << ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S) &
3926 ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_M);
3929 goto ice_aq_get_set_rss_lut_send;
3930 } else if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF) {
3932 goto ice_aq_get_set_rss_lut_send;
3934 goto ice_aq_get_set_rss_lut_send;
3937 /* LUT size is only valid for Global and PF table types */
3939 case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128:
3940 flags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128_FLAG <<
3941 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) &
3942 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M;
3944 case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512:
3945 flags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512_FLAG <<
3946 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) &
3947 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M;
3949 case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K:
3950 if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF) {
3951 flags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K_FLAG <<
3952 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) &
3953 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M;
3958 status = ICE_ERR_PARAM;
3959 goto ice_aq_get_set_rss_lut_exit;
3962 ice_aq_get_set_rss_lut_send:
3963 cmd_resp->flags = CPU_TO_LE16(flags);
3964 status = ice_aq_send_cmd(hw, &desc, lut, lut_size, NULL);
3966 ice_aq_get_set_rss_lut_exit:
3971 * ice_aq_get_rss_lut
3972 * @hw: pointer to the hardware structure
3973 * @get_params: RSS LUT parameters used to specify which RSS LUT to get
3975 * get the RSS lookup table, PF or VSI type
3978 ice_aq_get_rss_lut(struct ice_hw *hw, struct ice_aq_get_set_rss_lut_params *get_params)
3980 return __ice_aq_get_set_rss_lut(hw, get_params, false);
3984 * ice_aq_set_rss_lut
3985 * @hw: pointer to the hardware structure
3986 * @set_params: RSS LUT parameters used to specify how to set the RSS LUT
3988 * set the RSS lookup table, PF or VSI type
3991 ice_aq_set_rss_lut(struct ice_hw *hw, struct ice_aq_get_set_rss_lut_params *set_params)
3993 return __ice_aq_get_set_rss_lut(hw, set_params, true);
3997 * __ice_aq_get_set_rss_key
3998 * @hw: pointer to the HW struct
3999 * @vsi_id: VSI FW index
4000 * @key: pointer to key info struct
4001 * @set: set true to set the key, false to get the key
4003 * get (0x0B04) or set (0x0B02) the RSS key per VSI
4006 ice_status __ice_aq_get_set_rss_key(struct ice_hw *hw, u16 vsi_id,
4007 struct ice_aqc_get_set_rss_keys *key,
4010 struct ice_aqc_get_set_rss_key *cmd_resp;
4011 u16 key_size = sizeof(*key);
4012 struct ice_aq_desc desc;
4014 cmd_resp = &desc.params.get_set_rss_key;
4017 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_rss_key);
4018 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
4020 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_rss_key);
4023 cmd_resp->vsi_id = CPU_TO_LE16(((vsi_id <<
4024 ICE_AQC_GSET_RSS_KEY_VSI_ID_S) &
4025 ICE_AQC_GSET_RSS_KEY_VSI_ID_M) |
4026 ICE_AQC_GSET_RSS_KEY_VSI_VALID);
4028 return ice_aq_send_cmd(hw, &desc, key, key_size, NULL);
4032 * ice_aq_get_rss_key
4033 * @hw: pointer to the HW struct
4034 * @vsi_handle: software VSI handle
4035 * @key: pointer to key info struct
4037 * get the RSS key per VSI
4040 ice_aq_get_rss_key(struct ice_hw *hw, u16 vsi_handle,
4041 struct ice_aqc_get_set_rss_keys *key)
4043 if (!ice_is_vsi_valid(hw, vsi_handle) || !key)
4044 return ICE_ERR_PARAM;
4046 return __ice_aq_get_set_rss_key(hw, ice_get_hw_vsi_num(hw, vsi_handle),
4051 * ice_aq_set_rss_key
4052 * @hw: pointer to the HW struct
4053 * @vsi_handle: software VSI handle
4054 * @keys: pointer to key info struct
4056 * set the RSS key per VSI
4059 ice_aq_set_rss_key(struct ice_hw *hw, u16 vsi_handle,
4060 struct ice_aqc_get_set_rss_keys *keys)
4062 if (!ice_is_vsi_valid(hw, vsi_handle) || !keys)
4063 return ICE_ERR_PARAM;
4065 return __ice_aq_get_set_rss_key(hw, ice_get_hw_vsi_num(hw, vsi_handle),
4070 * ice_aq_add_lan_txq
4071 * @hw: pointer to the hardware structure
4072 * @num_qgrps: Number of added queue groups
4073 * @qg_list: list of queue groups to be added
4074 * @buf_size: size of buffer for indirect command
4075 * @cd: pointer to command details structure or NULL
4077 * Add Tx LAN queue (0x0C30)
4080 * Prior to calling add Tx LAN queue:
4081 * Initialize the following as part of the Tx queue context:
4082 * Completion queue ID if the queue uses Completion queue, Quanta profile,
4083 * Cache profile and Packet shaper profile.
4085 * After add Tx LAN queue AQ command is completed:
4086 * Interrupts should be associated with specific queues,
4087 * Association of Tx queue to Doorbell queue is not part of Add LAN Tx queue
4091 ice_aq_add_lan_txq(struct ice_hw *hw, u8 num_qgrps,
4092 struct ice_aqc_add_tx_qgrp *qg_list, u16 buf_size,
4093 struct ice_sq_cd *cd)
4095 struct ice_aqc_add_tx_qgrp *list;
4096 struct ice_aqc_add_txqs *cmd;
4097 struct ice_aq_desc desc;
4098 u16 i, sum_size = 0;
4100 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
4102 cmd = &desc.params.add_txqs;
4104 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_add_txqs);
4107 return ICE_ERR_PARAM;
4109 if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS)
4110 return ICE_ERR_PARAM;
4112 for (i = 0, list = qg_list; i < num_qgrps; i++) {
4113 sum_size += ice_struct_size(list, txqs, list->num_txqs);
4114 list = (struct ice_aqc_add_tx_qgrp *)(list->txqs +
4118 if (buf_size != sum_size)
4119 return ICE_ERR_PARAM;
4121 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
4123 cmd->num_qgrps = num_qgrps;
4125 return ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd);
4129 * ice_aq_dis_lan_txq
4130 * @hw: pointer to the hardware structure
4131 * @num_qgrps: number of groups in the list
4132 * @qg_list: the list of groups to disable
4133 * @buf_size: the total size of the qg_list buffer in bytes
4134 * @rst_src: if called due to reset, specifies the reset source
4135 * @vmvf_num: the relative VM or VF number that is undergoing the reset
4136 * @cd: pointer to command details structure or NULL
4138 * Disable LAN Tx queue (0x0C31)
4140 static enum ice_status
4141 ice_aq_dis_lan_txq(struct ice_hw *hw, u8 num_qgrps,
4142 struct ice_aqc_dis_txq_item *qg_list, u16 buf_size,
4143 enum ice_disq_rst_src rst_src, u16 vmvf_num,
4144 struct ice_sq_cd *cd)
4146 struct ice_aqc_dis_txq_item *item;
4147 struct ice_aqc_dis_txqs *cmd;
4148 struct ice_aq_desc desc;
4149 enum ice_status status;
4152 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
4153 cmd = &desc.params.dis_txqs;
4154 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_dis_txqs);
4156 /* qg_list can be NULL only in VM/VF reset flow */
4157 if (!qg_list && !rst_src)
4158 return ICE_ERR_PARAM;
4160 if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS)
4161 return ICE_ERR_PARAM;
4163 cmd->num_entries = num_qgrps;
4165 cmd->vmvf_and_timeout = CPU_TO_LE16((5 << ICE_AQC_Q_DIS_TIMEOUT_S) &
4166 ICE_AQC_Q_DIS_TIMEOUT_M);
4170 cmd->cmd_type = ICE_AQC_Q_DIS_CMD_VM_RESET;
4171 cmd->vmvf_and_timeout |=
4172 CPU_TO_LE16(vmvf_num & ICE_AQC_Q_DIS_VMVF_NUM_M);
4179 /* flush pipe on time out */
4180 cmd->cmd_type |= ICE_AQC_Q_DIS_CMD_FLUSH_PIPE;
4181 /* If no queue group info, we are in a reset flow. Issue the AQ */
4185 /* set RD bit to indicate that command buffer is provided by the driver
4186 * and it needs to be read by the firmware
4188 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
4190 for (i = 0, item = qg_list; i < num_qgrps; i++) {
4191 u16 item_size = ice_struct_size(item, q_id, item->num_qs);
4193 /* If the num of queues is even, add 2 bytes of padding */
4194 if ((item->num_qs % 2) == 0)
4199 item = (struct ice_aqc_dis_txq_item *)((u8 *)item + item_size);
4203 return ICE_ERR_PARAM;
4206 status = ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd);
4209 ice_debug(hw, ICE_DBG_SCHED, "VM%d disable failed %d\n",
4210 vmvf_num, hw->adminq.sq_last_status);
4212 ice_debug(hw, ICE_DBG_SCHED, "disable queue %d failed %d\n",
4213 LE16_TO_CPU(qg_list[0].q_id[0]),
4214 hw->adminq.sq_last_status);
4220 * ice_aq_move_recfg_lan_txq
4221 * @hw: pointer to the hardware structure
4222 * @num_qs: number of queues to move/reconfigure
4223 * @is_move: true if this operation involves node movement
4224 * @is_tc_change: true if this operation involves a TC change
4225 * @subseq_call: true if this operation is a subsequent call
4226 * @flush_pipe: on timeout, true to flush pipe, false to return EAGAIN
4227 * @timeout: timeout in units of 100 usec (valid values 0-50)
4228 * @blocked_cgds: out param, bitmap of CGDs that timed out if returning EAGAIN
4229 * @buf: struct containing src/dest TEID and per-queue info
4230 * @buf_size: size of buffer for indirect command
4231 * @txqs_moved: out param, number of queues successfully moved
4232 * @cd: pointer to command details structure or NULL
4234 * Move / Reconfigure Tx LAN queues (0x0C32)
4237 ice_aq_move_recfg_lan_txq(struct ice_hw *hw, u8 num_qs, bool is_move,
4238 bool is_tc_change, bool subseq_call, bool flush_pipe,
4239 u8 timeout, u32 *blocked_cgds,
4240 struct ice_aqc_move_txqs_data *buf, u16 buf_size,
4241 u8 *txqs_moved, struct ice_sq_cd *cd)
4243 struct ice_aqc_move_txqs *cmd;
4244 struct ice_aq_desc desc;
4245 enum ice_status status;
4247 cmd = &desc.params.move_txqs;
4248 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_move_recfg_txqs);
4250 #define ICE_LAN_TXQ_MOVE_TIMEOUT_MAX 50
4251 if (timeout > ICE_LAN_TXQ_MOVE_TIMEOUT_MAX)
4252 return ICE_ERR_PARAM;
4254 if (is_tc_change && !flush_pipe && !blocked_cgds)
4255 return ICE_ERR_PARAM;
4257 if (!is_move && !is_tc_change)
4258 return ICE_ERR_PARAM;
4260 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
4263 cmd->cmd_type |= ICE_AQC_Q_CMD_TYPE_MOVE;
4266 cmd->cmd_type |= ICE_AQC_Q_CMD_TYPE_TC_CHANGE;
4269 cmd->cmd_type |= ICE_AQC_Q_CMD_SUBSEQ_CALL;
4272 cmd->cmd_type |= ICE_AQC_Q_CMD_FLUSH_PIPE;
4274 cmd->num_qs = num_qs;
4275 cmd->timeout = ((timeout << ICE_AQC_Q_CMD_TIMEOUT_S) &
4276 ICE_AQC_Q_CMD_TIMEOUT_M);
4278 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);
4280 if (!status && txqs_moved)
4281 *txqs_moved = cmd->num_qs;
4283 if (hw->adminq.sq_last_status == ICE_AQ_RC_EAGAIN &&
4284 is_tc_change && !flush_pipe)
4285 *blocked_cgds = LE32_TO_CPU(cmd->blocked_cgds);
4290 /* End of FW Admin Queue command wrappers */
4293 * ice_write_byte - write a byte to a packed context structure
4294 * @src_ctx: the context structure to read from
4295 * @dest_ctx: the context to be written to
4296 * @ce_info: a description of the struct to be filled
4299 ice_write_byte(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)
4301 u8 src_byte, dest_byte, mask;
4305 /* copy from the next struct field */
4306 from = src_ctx + ce_info->offset;
4308 /* prepare the bits and mask */
4309 shift_width = ce_info->lsb % 8;
4310 mask = (u8)(BIT(ce_info->width) - 1);
4315 /* shift to correct alignment */
4316 mask <<= shift_width;
4317 src_byte <<= shift_width;
4319 /* get the current bits from the target bit string */
4320 dest = dest_ctx + (ce_info->lsb / 8);
4322 ice_memcpy(&dest_byte, dest, sizeof(dest_byte), ICE_DMA_TO_NONDMA);
4324 dest_byte &= ~mask; /* get the bits not changing */
4325 dest_byte |= src_byte; /* add in the new bits */
4327 /* put it all back */
4328 ice_memcpy(dest, &dest_byte, sizeof(dest_byte), ICE_NONDMA_TO_DMA);
4332 * ice_write_word - write a word to a packed context structure
4333 * @src_ctx: the context structure to read from
4334 * @dest_ctx: the context to be written to
4335 * @ce_info: a description of the struct to be filled
4338 ice_write_word(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)
4345 /* copy from the next struct field */
4346 from = src_ctx + ce_info->offset;
4348 /* prepare the bits and mask */
4349 shift_width = ce_info->lsb % 8;
4350 mask = BIT(ce_info->width) - 1;
4352 /* don't swizzle the bits until after the mask because the mask bits
4353 * will be in a different bit position on big endian machines
4355 src_word = *(u16 *)from;
4358 /* shift to correct alignment */
4359 mask <<= shift_width;
4360 src_word <<= shift_width;
4362 /* get the current bits from the target bit string */
4363 dest = dest_ctx + (ce_info->lsb / 8);
4365 ice_memcpy(&dest_word, dest, sizeof(dest_word), ICE_DMA_TO_NONDMA);
4367 dest_word &= ~(CPU_TO_LE16(mask)); /* get the bits not changing */
4368 dest_word |= CPU_TO_LE16(src_word); /* add in the new bits */
4370 /* put it all back */
4371 ice_memcpy(dest, &dest_word, sizeof(dest_word), ICE_NONDMA_TO_DMA);
4375 * ice_write_dword - write a dword to a packed context structure
4376 * @src_ctx: the context structure to read from
4377 * @dest_ctx: the context to be written to
4378 * @ce_info: a description of the struct to be filled
4381 ice_write_dword(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)
4383 u32 src_dword, mask;
4388 /* copy from the next struct field */
4389 from = src_ctx + ce_info->offset;
4391 /* prepare the bits and mask */
4392 shift_width = ce_info->lsb % 8;
4394 /* if the field width is exactly 32 on an x86 machine, then the shift
4395 * operation will not work because the SHL instructions count is masked
4396 * to 5 bits so the shift will do nothing
4398 if (ce_info->width < 32)
4399 mask = BIT(ce_info->width) - 1;
4403 /* don't swizzle the bits until after the mask because the mask bits
4404 * will be in a different bit position on big endian machines
4406 src_dword = *(u32 *)from;
4409 /* shift to correct alignment */
4410 mask <<= shift_width;
4411 src_dword <<= shift_width;
4413 /* get the current bits from the target bit string */
4414 dest = dest_ctx + (ce_info->lsb / 8);
4416 ice_memcpy(&dest_dword, dest, sizeof(dest_dword), ICE_DMA_TO_NONDMA);
4418 dest_dword &= ~(CPU_TO_LE32(mask)); /* get the bits not changing */
4419 dest_dword |= CPU_TO_LE32(src_dword); /* add in the new bits */
4421 /* put it all back */
4422 ice_memcpy(dest, &dest_dword, sizeof(dest_dword), ICE_NONDMA_TO_DMA);
4426 * ice_write_qword - write a qword to a packed context structure
4427 * @src_ctx: the context structure to read from
4428 * @dest_ctx: the context to be written to
4429 * @ce_info: a description of the struct to be filled
4432 ice_write_qword(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)
4434 u64 src_qword, mask;
4439 /* copy from the next struct field */
4440 from = src_ctx + ce_info->offset;
4442 /* prepare the bits and mask */
4443 shift_width = ce_info->lsb % 8;
4445 /* if the field width is exactly 64 on an x86 machine, then the shift
4446 * operation will not work because the SHL instructions count is masked
4447 * to 6 bits so the shift will do nothing
4449 if (ce_info->width < 64)
4450 mask = BIT_ULL(ce_info->width) - 1;
4454 /* don't swizzle the bits until after the mask because the mask bits
4455 * will be in a different bit position on big endian machines
4457 src_qword = *(u64 *)from;
4460 /* shift to correct alignment */
4461 mask <<= shift_width;
4462 src_qword <<= shift_width;
4464 /* get the current bits from the target bit string */
4465 dest = dest_ctx + (ce_info->lsb / 8);
4467 ice_memcpy(&dest_qword, dest, sizeof(dest_qword), ICE_DMA_TO_NONDMA);
4469 dest_qword &= ~(CPU_TO_LE64(mask)); /* get the bits not changing */
4470 dest_qword |= CPU_TO_LE64(src_qword); /* add in the new bits */
4472 /* put it all back */
4473 ice_memcpy(dest, &dest_qword, sizeof(dest_qword), ICE_NONDMA_TO_DMA);
4477 * ice_set_ctx - set context bits in packed structure
4478 * @hw: pointer to the hardware structure
4479 * @src_ctx: pointer to a generic non-packed context structure
4480 * @dest_ctx: pointer to memory for the packed structure
4481 * @ce_info: a description of the structure to be transformed
4484 ice_set_ctx(struct ice_hw *hw, u8 *src_ctx, u8 *dest_ctx,
4485 const struct ice_ctx_ele *ce_info)
4489 for (f = 0; ce_info[f].width; f++) {
4490 /* We have to deal with each element of the FW response
4491 * using the correct size so that we are correct regardless
4492 * of the endianness of the machine.
4494 if (ce_info[f].width > (ce_info[f].size_of * BITS_PER_BYTE)) {
4495 ice_debug(hw, ICE_DBG_QCTX, "Field %d width of %d bits larger than size of %d byte(s) ... skipping write\n",
4496 f, ce_info[f].width, ce_info[f].size_of);
4499 switch (ce_info[f].size_of) {
4501 ice_write_byte(src_ctx, dest_ctx, &ce_info[f]);
4504 ice_write_word(src_ctx, dest_ctx, &ce_info[f]);
4507 ice_write_dword(src_ctx, dest_ctx, &ce_info[f]);
4510 ice_write_qword(src_ctx, dest_ctx, &ce_info[f]);
4513 return ICE_ERR_INVAL_SIZE;
4521 * ice_aq_get_internal_data
4522 * @hw: pointer to the hardware structure
4523 * @cluster_id: specific cluster to dump
4524 * @table_id: table ID within cluster
4525 * @start: index of line in the block to read
4527 * @buf_size: dump buffer size
4528 * @ret_buf_size: return buffer size (returned by FW)
4529 * @ret_next_table: next block to read (returned by FW)
4530 * @ret_next_index: next index to read (returned by FW)
4531 * @cd: pointer to command details structure
4533 * Get internal FW/HW data (0xFF08) for debug purposes.
4536 ice_aq_get_internal_data(struct ice_hw *hw, u8 cluster_id, u16 table_id,
4537 u32 start, void *buf, u16 buf_size, u16 *ret_buf_size,
4538 u16 *ret_next_table, u32 *ret_next_index,
4539 struct ice_sq_cd *cd)
4541 struct ice_aqc_debug_dump_internals *cmd;
4542 struct ice_aq_desc desc;
4543 enum ice_status status;
4545 cmd = &desc.params.debug_dump;
4547 if (buf_size == 0 || !buf)
4548 return ICE_ERR_PARAM;
4550 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_debug_dump_internals);
4552 cmd->cluster_id = cluster_id;
4553 cmd->table_id = CPU_TO_LE16(table_id);
4554 cmd->idx = CPU_TO_LE32(start);
4556 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);
4560 *ret_buf_size = LE16_TO_CPU(desc.datalen);
4562 *ret_next_table = LE16_TO_CPU(cmd->table_id);
4564 *ret_next_index = LE32_TO_CPU(cmd->idx);
4571 * ice_read_byte - read context byte into struct
4572 * @src_ctx: the context structure to read from
4573 * @dest_ctx: the context to be written to
4574 * @ce_info: a description of the struct to be filled
4577 ice_read_byte(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info)
4583 /* prepare the bits and mask */
4584 shift_width = ce_info->lsb % 8;
4585 mask = (u8)(BIT(ce_info->width) - 1);
4587 /* shift to correct alignment */
4588 mask <<= shift_width;
4590 /* get the current bits from the src bit string */
4591 src = src_ctx + (ce_info->lsb / 8);
4593 ice_memcpy(&dest_byte, src, sizeof(dest_byte), ICE_DMA_TO_NONDMA);
4595 dest_byte &= ~(mask);
4597 dest_byte >>= shift_width;
4599 /* get the address from the struct field */
4600 target = dest_ctx + ce_info->offset;
4602 /* put it back in the struct */
4603 ice_memcpy(target, &dest_byte, sizeof(dest_byte), ICE_NONDMA_TO_DMA);
4607 * ice_read_word - read context word into struct
4608 * @src_ctx: the context structure to read from
4609 * @dest_ctx: the context to be written to
4610 * @ce_info: a description of the struct to be filled
4613 ice_read_word(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info)
4615 u16 dest_word, mask;
4620 /* prepare the bits and mask */
4621 shift_width = ce_info->lsb % 8;
4622 mask = BIT(ce_info->width) - 1;
4624 /* shift to correct alignment */
4625 mask <<= shift_width;
4627 /* get the current bits from the src bit string */
4628 src = src_ctx + (ce_info->lsb / 8);
4630 ice_memcpy(&src_word, src, sizeof(src_word), ICE_DMA_TO_NONDMA);
4632 /* the data in the memory is stored as little endian so mask it
4635 src_word &= ~(CPU_TO_LE16(mask));
4637 /* get the data back into host order before shifting */
4638 dest_word = LE16_TO_CPU(src_word);
4640 dest_word >>= shift_width;
4642 /* get the address from the struct field */
4643 target = dest_ctx + ce_info->offset;
4645 /* put it back in the struct */
4646 ice_memcpy(target, &dest_word, sizeof(dest_word), ICE_NONDMA_TO_DMA);
4650 * ice_read_dword - read context dword into struct
4651 * @src_ctx: the context structure to read from
4652 * @dest_ctx: the context to be written to
4653 * @ce_info: a description of the struct to be filled
4656 ice_read_dword(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info)
4658 u32 dest_dword, mask;
4663 /* prepare the bits and mask */
4664 shift_width = ce_info->lsb % 8;
4666 /* if the field width is exactly 32 on an x86 machine, then the shift
4667 * operation will not work because the SHL instructions count is masked
4668 * to 5 bits so the shift will do nothing
4670 if (ce_info->width < 32)
4671 mask = BIT(ce_info->width) - 1;
4675 /* shift to correct alignment */
4676 mask <<= shift_width;
4678 /* get the current bits from the src bit string */
4679 src = src_ctx + (ce_info->lsb / 8);
4681 ice_memcpy(&src_dword, src, sizeof(src_dword), ICE_DMA_TO_NONDMA);
4683 /* the data in the memory is stored as little endian so mask it
4686 src_dword &= ~(CPU_TO_LE32(mask));
4688 /* get the data back into host order before shifting */
4689 dest_dword = LE32_TO_CPU(src_dword);
4691 dest_dword >>= shift_width;
4693 /* get the address from the struct field */
4694 target = dest_ctx + ce_info->offset;
4696 /* put it back in the struct */
4697 ice_memcpy(target, &dest_dword, sizeof(dest_dword), ICE_NONDMA_TO_DMA);
4701 * ice_read_qword - read context qword into struct
4702 * @src_ctx: the context structure to read from
4703 * @dest_ctx: the context to be written to
4704 * @ce_info: a description of the struct to be filled
4707 ice_read_qword(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info)
4709 u64 dest_qword, mask;
4714 /* prepare the bits and mask */
4715 shift_width = ce_info->lsb % 8;
4717 /* if the field width is exactly 64 on an x86 machine, then the shift
4718 * operation will not work because the SHL instructions count is masked
4719 * to 6 bits so the shift will do nothing
4721 if (ce_info->width < 64)
4722 mask = BIT_ULL(ce_info->width) - 1;
4726 /* shift to correct alignment */
4727 mask <<= shift_width;
4729 /* get the current bits from the src bit string */
4730 src = src_ctx + (ce_info->lsb / 8);
4732 ice_memcpy(&src_qword, src, sizeof(src_qword), ICE_DMA_TO_NONDMA);
4734 /* the data in the memory is stored as little endian so mask it
4737 src_qword &= ~(CPU_TO_LE64(mask));
4739 /* get the data back into host order before shifting */
4740 dest_qword = LE64_TO_CPU(src_qword);
4742 dest_qword >>= shift_width;
4744 /* get the address from the struct field */
4745 target = dest_ctx + ce_info->offset;
4747 /* put it back in the struct */
4748 ice_memcpy(target, &dest_qword, sizeof(dest_qword), ICE_NONDMA_TO_DMA);
4752 * ice_get_ctx - extract context bits from a packed structure
4753 * @src_ctx: pointer to a generic packed context structure
4754 * @dest_ctx: pointer to a generic non-packed context structure
4755 * @ce_info: a description of the structure to be read from
4758 ice_get_ctx(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info)
4762 for (f = 0; ce_info[f].width; f++) {
4763 switch (ce_info[f].size_of) {
4765 ice_read_byte(src_ctx, dest_ctx, &ce_info[f]);
4768 ice_read_word(src_ctx, dest_ctx, &ce_info[f]);
4771 ice_read_dword(src_ctx, dest_ctx, &ce_info[f]);
4774 ice_read_qword(src_ctx, dest_ctx, &ce_info[f]);
4777 /* nothing to do, just keep going */
4786 * ice_get_lan_q_ctx - get the LAN queue context for the given VSI and TC
4787 * @hw: pointer to the HW struct
4788 * @vsi_handle: software VSI handle
4790 * @q_handle: software queue handle
4793 ice_get_lan_q_ctx(struct ice_hw *hw, u16 vsi_handle, u8 tc, u16 q_handle)
4795 struct ice_vsi_ctx *vsi;
4796 struct ice_q_ctx *q_ctx;
4798 vsi = ice_get_vsi_ctx(hw, vsi_handle);
4801 if (q_handle >= vsi->num_lan_q_entries[tc])
4803 if (!vsi->lan_q_ctx[tc])
4805 q_ctx = vsi->lan_q_ctx[tc];
4806 return &q_ctx[q_handle];
4811 * @pi: port information structure
4812 * @vsi_handle: software VSI handle
4814 * @q_handle: software queue handle
4815 * @num_qgrps: Number of added queue groups
4816 * @buf: list of queue groups to be added
4817 * @buf_size: size of buffer for indirect command
4818 * @cd: pointer to command details structure or NULL
4820 * This function adds one LAN queue
4823 ice_ena_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u16 q_handle,
4824 u8 num_qgrps, struct ice_aqc_add_tx_qgrp *buf, u16 buf_size,
4825 struct ice_sq_cd *cd)
4827 struct ice_aqc_txsched_elem_data node = { 0 };
4828 struct ice_sched_node *parent;
4829 struct ice_q_ctx *q_ctx;
4830 enum ice_status status;
4833 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY)
4836 if (num_qgrps > 1 || buf->num_txqs > 1)
4837 return ICE_ERR_MAX_LIMIT;
4841 if (!ice_is_vsi_valid(hw, vsi_handle))
4842 return ICE_ERR_PARAM;
4844 ice_acquire_lock(&pi->sched_lock);
4846 q_ctx = ice_get_lan_q_ctx(hw, vsi_handle, tc, q_handle);
4848 ice_debug(hw, ICE_DBG_SCHED, "Enaq: invalid queue handle %d\n",
4850 status = ICE_ERR_PARAM;
4854 /* find a parent node */
4855 parent = ice_sched_get_free_qparent(pi, vsi_handle, tc,
4856 ICE_SCHED_NODE_OWNER_LAN);
4858 status = ICE_ERR_PARAM;
4862 buf->parent_teid = parent->info.node_teid;
4863 node.parent_teid = parent->info.node_teid;
4864 /* Mark that the values in the "generic" section as valid. The default
4865 * value in the "generic" section is zero. This means that :
4866 * - Scheduling mode is Bytes Per Second (BPS), indicated by Bit 0.
4867 * - 0 priority among siblings, indicated by Bit 1-3.
4868 * - WFQ, indicated by Bit 4.
4869 * - 0 Adjustment value is used in PSM credit update flow, indicated by
4871 * - Bit 7 is reserved.
4872 * Without setting the generic section as valid in valid_sections, the
4873 * Admin queue command will fail with error code ICE_AQ_RC_EINVAL.
4875 buf->txqs[0].info.valid_sections =
4876 ICE_AQC_ELEM_VALID_GENERIC | ICE_AQC_ELEM_VALID_CIR |
4877 ICE_AQC_ELEM_VALID_EIR;
4878 buf->txqs[0].info.generic = 0;
4879 buf->txqs[0].info.cir_bw.bw_profile_idx =
4880 CPU_TO_LE16(ICE_SCHED_DFLT_RL_PROF_ID);
4881 buf->txqs[0].info.cir_bw.bw_alloc =
4882 CPU_TO_LE16(ICE_SCHED_DFLT_BW_WT);
4883 buf->txqs[0].info.eir_bw.bw_profile_idx =
4884 CPU_TO_LE16(ICE_SCHED_DFLT_RL_PROF_ID);
4885 buf->txqs[0].info.eir_bw.bw_alloc =
4886 CPU_TO_LE16(ICE_SCHED_DFLT_BW_WT);
4888 /* add the LAN queue */
4889 status = ice_aq_add_lan_txq(hw, num_qgrps, buf, buf_size, cd);
4890 if (status != ICE_SUCCESS) {
4891 ice_debug(hw, ICE_DBG_SCHED, "enable queue %d failed %d\n",
4892 LE16_TO_CPU(buf->txqs[0].txq_id),
4893 hw->adminq.sq_last_status);
4897 node.node_teid = buf->txqs[0].q_teid;
4898 node.data.elem_type = ICE_AQC_ELEM_TYPE_LEAF;
4899 q_ctx->q_handle = q_handle;
4900 q_ctx->q_teid = LE32_TO_CPU(node.node_teid);
4902 /* add a leaf node into scheduler tree queue layer */
4903 status = ice_sched_add_node(pi, hw->num_tx_sched_layers - 1, &node);
4905 status = ice_sched_replay_q_bw(pi, q_ctx);
4908 ice_release_lock(&pi->sched_lock);
4914 * @pi: port information structure
4915 * @vsi_handle: software VSI handle
4917 * @num_queues: number of queues
4918 * @q_handles: pointer to software queue handle array
4919 * @q_ids: pointer to the q_id array
4920 * @q_teids: pointer to queue node teids
4921 * @rst_src: if called due to reset, specifies the reset source
4922 * @vmvf_num: the relative VM or VF number that is undergoing the reset
4923 * @cd: pointer to command details structure or NULL
4925 * This function removes queues and their corresponding nodes in SW DB
4928 ice_dis_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u8 num_queues,
4929 u16 *q_handles, u16 *q_ids, u32 *q_teids,
4930 enum ice_disq_rst_src rst_src, u16 vmvf_num,
4931 struct ice_sq_cd *cd)
4933 enum ice_status status = ICE_ERR_DOES_NOT_EXIST;
4934 struct ice_aqc_dis_txq_item *qg_list;
4935 struct ice_q_ctx *q_ctx;
4939 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY)
4945 /* if queue is disabled already yet the disable queue command
4946 * has to be sent to complete the VF reset, then call
4947 * ice_aq_dis_lan_txq without any queue information
4950 return ice_aq_dis_lan_txq(hw, 0, NULL, 0, rst_src,
4955 buf_size = ice_struct_size(qg_list, q_id, 1);
4956 qg_list = (struct ice_aqc_dis_txq_item *)ice_malloc(hw, buf_size);
4958 return ICE_ERR_NO_MEMORY;
4960 ice_acquire_lock(&pi->sched_lock);
4962 for (i = 0; i < num_queues; i++) {
4963 struct ice_sched_node *node;
4965 node = ice_sched_find_node_by_teid(pi->root, q_teids[i]);
4968 q_ctx = ice_get_lan_q_ctx(hw, vsi_handle, tc, q_handles[i]);
4970 ice_debug(hw, ICE_DBG_SCHED, "invalid queue handle%d\n",
4974 if (q_ctx->q_handle != q_handles[i]) {
4975 ice_debug(hw, ICE_DBG_SCHED, "Err:handles %d %d\n",
4976 q_ctx->q_handle, q_handles[i]);
4979 qg_list->parent_teid = node->info.parent_teid;
4980 qg_list->num_qs = 1;
4981 qg_list->q_id[0] = CPU_TO_LE16(q_ids[i]);
4982 status = ice_aq_dis_lan_txq(hw, 1, qg_list, buf_size, rst_src,
4985 if (status != ICE_SUCCESS)
4987 ice_free_sched_node(pi, node);
4988 q_ctx->q_handle = ICE_INVAL_Q_HANDLE;
4990 ice_release_lock(&pi->sched_lock);
4991 ice_free(hw, qg_list);
4996 * ice_cfg_vsi_qs - configure the new/existing VSI queues
4997 * @pi: port information structure
4998 * @vsi_handle: software VSI handle
4999 * @tc_bitmap: TC bitmap
5000 * @maxqs: max queues array per TC
5001 * @owner: LAN or RDMA
5003 * This function adds/updates the VSI queues per TC.
5005 static enum ice_status
5006 ice_cfg_vsi_qs(struct ice_port_info *pi, u16 vsi_handle, u16 tc_bitmap,
5007 u16 *maxqs, u8 owner)
5009 enum ice_status status = ICE_SUCCESS;
5012 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY)
5015 if (!ice_is_vsi_valid(pi->hw, vsi_handle))
5016 return ICE_ERR_PARAM;
5018 ice_acquire_lock(&pi->sched_lock);
5020 ice_for_each_traffic_class(i) {
5021 /* configuration is possible only if TC node is present */
5022 if (!ice_sched_get_tc_node(pi, i))
5025 status = ice_sched_cfg_vsi(pi, vsi_handle, i, maxqs[i], owner,
5026 ice_is_tc_ena(tc_bitmap, i));
5031 ice_release_lock(&pi->sched_lock);
5036 * ice_cfg_vsi_lan - configure VSI LAN queues
5037 * @pi: port information structure
5038 * @vsi_handle: software VSI handle
5039 * @tc_bitmap: TC bitmap
5040 * @max_lanqs: max LAN queues array per TC
5042 * This function adds/updates the VSI LAN queues per TC.
5045 ice_cfg_vsi_lan(struct ice_port_info *pi, u16 vsi_handle, u16 tc_bitmap,
5048 return ice_cfg_vsi_qs(pi, vsi_handle, tc_bitmap, max_lanqs,
5049 ICE_SCHED_NODE_OWNER_LAN);
5053 * ice_is_main_vsi - checks whether the VSI is main VSI
5054 * @hw: pointer to the HW struct
5055 * @vsi_handle: VSI handle
5057 * Checks whether the VSI is the main VSI (the first PF VSI created on
5060 static bool ice_is_main_vsi(struct ice_hw *hw, u16 vsi_handle)
5062 return vsi_handle == ICE_MAIN_VSI_HANDLE && hw->vsi_ctx[vsi_handle];
5066 * ice_replay_pre_init - replay pre initialization
5067 * @hw: pointer to the HW struct
5068 * @sw: pointer to switch info struct for which function initializes filters
5070 * Initializes required config data for VSI, FD, ACL, and RSS before replay.
5072 static enum ice_status
5073 ice_replay_pre_init(struct ice_hw *hw, struct ice_switch_info *sw)
5075 enum ice_status status;
5078 /* Delete old entries from replay filter list head if there is any */
5079 ice_rm_sw_replay_rule_info(hw, sw);
5080 /* In start of replay, move entries into replay_rules list, it
5081 * will allow adding rules entries back to filt_rules list,
5082 * which is operational list.
5084 for (i = 0; i < ICE_MAX_NUM_RECIPES; i++)
5085 LIST_REPLACE_INIT(&sw->recp_list[i].filt_rules,
5086 &sw->recp_list[i].filt_replay_rules);
5087 ice_sched_replay_agg_vsi_preinit(hw);
5089 status = ice_sched_replay_root_node_bw(hw->port_info);
5093 return ice_sched_replay_tc_node_bw(hw->port_info);
5097 * ice_replay_vsi - replay VSI configuration
5098 * @hw: pointer to the HW struct
5099 * @vsi_handle: driver VSI handle
5101 * Restore all VSI configuration after reset. It is required to call this
5102 * function with main VSI first.
5104 enum ice_status ice_replay_vsi(struct ice_hw *hw, u16 vsi_handle)
5106 struct ice_switch_info *sw = hw->switch_info;
5107 struct ice_port_info *pi = hw->port_info;
5108 enum ice_status status;
5110 if (!ice_is_vsi_valid(hw, vsi_handle))
5111 return ICE_ERR_PARAM;
5113 /* Replay pre-initialization if there is any */
5114 if (ice_is_main_vsi(hw, vsi_handle)) {
5115 status = ice_replay_pre_init(hw, sw);
5119 /* Replay per VSI all RSS configurations */
5120 status = ice_replay_rss_cfg(hw, vsi_handle);
5123 /* Replay per VSI all filters */
5124 status = ice_replay_vsi_all_fltr(hw, pi, vsi_handle);
5126 status = ice_replay_vsi_agg(hw, vsi_handle);
5131 * ice_replay_post - post replay configuration cleanup
5132 * @hw: pointer to the HW struct
5134 * Post replay cleanup.
5136 void ice_replay_post(struct ice_hw *hw)
5138 /* Delete old entries from replay filter list head */
5139 ice_rm_all_sw_replay_rule_info(hw);
5140 ice_sched_replay_agg(hw);
5144 * ice_stat_update40 - read 40 bit stat from the chip and update stat values
5145 * @hw: ptr to the hardware info
5146 * @reg: offset of 64 bit HW register to read from
5147 * @prev_stat_loaded: bool to specify if previous stats are loaded
5148 * @prev_stat: ptr to previous loaded stat value
5149 * @cur_stat: ptr to current stat value
5152 ice_stat_update40(struct ice_hw *hw, u32 reg, bool prev_stat_loaded,
5153 u64 *prev_stat, u64 *cur_stat)
5155 u64 new_data = rd64(hw, reg) & (BIT_ULL(40) - 1);
5157 /* device stats are not reset at PFR, they likely will not be zeroed
5158 * when the driver starts. Thus, save the value from the first read
5159 * without adding to the statistic value so that we report stats which
5160 * count up from zero.
5162 if (!prev_stat_loaded) {
5163 *prev_stat = new_data;
5167 /* Calculate the difference between the new and old values, and then
5168 * add it to the software stat value.
5170 if (new_data >= *prev_stat)
5171 *cur_stat += new_data - *prev_stat;
5173 /* to manage the potential roll-over */
5174 *cur_stat += (new_data + BIT_ULL(40)) - *prev_stat;
5176 /* Update the previously stored value to prepare for next read */
5177 *prev_stat = new_data;
5181 * ice_stat_update32 - read 32 bit stat from the chip and update stat values
5182 * @hw: ptr to the hardware info
5183 * @reg: offset of HW register to read from
5184 * @prev_stat_loaded: bool to specify if previous stats are loaded
5185 * @prev_stat: ptr to previous loaded stat value
5186 * @cur_stat: ptr to current stat value
5189 ice_stat_update32(struct ice_hw *hw, u32 reg, bool prev_stat_loaded,
5190 u64 *prev_stat, u64 *cur_stat)
5194 new_data = rd32(hw, reg);
5196 /* device stats are not reset at PFR, they likely will not be zeroed
5197 * when the driver starts. Thus, save the value from the first read
5198 * without adding to the statistic value so that we report stats which
5199 * count up from zero.
5201 if (!prev_stat_loaded) {
5202 *prev_stat = new_data;
5206 /* Calculate the difference between the new and old values, and then
5207 * add it to the software stat value.
5209 if (new_data >= *prev_stat)
5210 *cur_stat += new_data - *prev_stat;
5212 /* to manage the potential roll-over */
5213 *cur_stat += (new_data + BIT_ULL(32)) - *prev_stat;
5215 /* Update the previously stored value to prepare for next read */
5216 *prev_stat = new_data;
5220 * ice_stat_update_repc - read GLV_REPC stats from chip and update stat values
5221 * @hw: ptr to the hardware info
5222 * @vsi_handle: VSI handle
5223 * @prev_stat_loaded: bool to specify if the previous stat values are loaded
5224 * @cur_stats: ptr to current stats structure
5226 * The GLV_REPC statistic register actually tracks two 16bit statistics, and
5227 * thus cannot be read using the normal ice_stat_update32 function.
5229 * Read the GLV_REPC register associated with the given VSI, and update the
5230 * rx_no_desc and rx_error values in the ice_eth_stats structure.
5232 * Because the statistics in GLV_REPC stick at 0xFFFF, the register must be
5233 * cleared each time it's read.
5235 * Note that the GLV_RDPC register also counts the causes that would trigger
5236 * GLV_REPC. However, it does not give the finer grained detail about why the
5237 * packets are being dropped. The GLV_REPC values can be used to distinguish
5238 * whether Rx packets are dropped due to errors or due to no available
5242 ice_stat_update_repc(struct ice_hw *hw, u16 vsi_handle, bool prev_stat_loaded,
5243 struct ice_eth_stats *cur_stats)
5245 u16 vsi_num, no_desc, error_cnt;
5248 if (!ice_is_vsi_valid(hw, vsi_handle))
5251 vsi_num = ice_get_hw_vsi_num(hw, vsi_handle);
5253 /* If we haven't loaded stats yet, just clear the current value */
5254 if (!prev_stat_loaded) {
5255 wr32(hw, GLV_REPC(vsi_num), 0);
5259 repc = rd32(hw, GLV_REPC(vsi_num));
5260 no_desc = (repc & GLV_REPC_NO_DESC_CNT_M) >> GLV_REPC_NO_DESC_CNT_S;
5261 error_cnt = (repc & GLV_REPC_ERROR_CNT_M) >> GLV_REPC_ERROR_CNT_S;
5263 /* Clear the count by writing to the stats register */
5264 wr32(hw, GLV_REPC(vsi_num), 0);
5266 cur_stats->rx_no_desc += no_desc;
5267 cur_stats->rx_errors += error_cnt;
5271 * ice_sched_query_elem - query element information from HW
5272 * @hw: pointer to the HW struct
5273 * @node_teid: node TEID to be queried
5274 * @buf: buffer to element information
5276 * This function queries HW element information
5279 ice_sched_query_elem(struct ice_hw *hw, u32 node_teid,
5280 struct ice_aqc_txsched_elem_data *buf)
5282 u16 buf_size, num_elem_ret = 0;
5283 enum ice_status status;
5285 buf_size = sizeof(*buf);
5286 ice_memset(buf, 0, buf_size, ICE_NONDMA_MEM);
5287 buf->node_teid = CPU_TO_LE32(node_teid);
5288 status = ice_aq_query_sched_elems(hw, 1, buf, buf_size, &num_elem_ret,
5290 if (status != ICE_SUCCESS || num_elem_ret != 1)
5291 ice_debug(hw, ICE_DBG_SCHED, "query element failed\n");
5296 * ice_get_fw_mode - returns FW mode
5297 * @hw: pointer to the HW struct
5299 enum ice_fw_modes ice_get_fw_mode(struct ice_hw *hw)
5301 #define ICE_FW_MODE_DBG_M BIT(0)
5302 #define ICE_FW_MODE_REC_M BIT(1)
5303 #define ICE_FW_MODE_ROLLBACK_M BIT(2)
5306 /* check the current FW mode */
5307 fw_mode = rd32(hw, GL_MNG_FWSM) & GL_MNG_FWSM_FW_MODES_M;
5309 if (fw_mode & ICE_FW_MODE_DBG_M)
5310 return ICE_FW_MODE_DBG;
5311 else if (fw_mode & ICE_FW_MODE_REC_M)
5312 return ICE_FW_MODE_REC;
5313 else if (fw_mode & ICE_FW_MODE_ROLLBACK_M)
5314 return ICE_FW_MODE_ROLLBACK;
5316 return ICE_FW_MODE_NORMAL;
5321 * @hw: pointer to the hw struct
5322 * @topo_addr: topology address for a device to communicate with
5323 * @bus_addr: 7-bit I2C bus address
5324 * @addr: I2C memory address (I2C offset) with up to 16 bits
5325 * @params: I2C parameters: bit [7] - Repeated start, bits [6:5] data offset size,
5326 * bit [4] - I2C address type, bits [3:0] - data size to read (0-16 bytes)
5327 * @data: pointer to data (0 to 16 bytes) to be read from the I2C device
5328 * @cd: pointer to command details structure or NULL
5333 ice_aq_read_i2c(struct ice_hw *hw, struct ice_aqc_link_topo_addr topo_addr,
5334 u16 bus_addr, __le16 addr, u8 params, u8 *data,
5335 struct ice_sq_cd *cd)
5337 struct ice_aq_desc desc = { 0 };
5338 struct ice_aqc_i2c *cmd;
5339 enum ice_status status;
5342 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_read_i2c);
5343 cmd = &desc.params.read_write_i2c;
5346 return ICE_ERR_PARAM;
5348 data_size = (params & ICE_AQC_I2C_DATA_SIZE_M) >> ICE_AQC_I2C_DATA_SIZE_S;
5350 cmd->i2c_bus_addr = CPU_TO_LE16(bus_addr);
5351 cmd->topo_addr = topo_addr;
5352 cmd->i2c_params = params;
5353 cmd->i2c_addr = addr;
5355 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
5357 struct ice_aqc_read_i2c_resp *resp;
5360 resp = &desc.params.read_i2c_resp;
5361 for (i = 0; i < data_size; i++) {
5362 *data = resp->i2c_data[i];
5372 * @hw: pointer to the hw struct
5373 * @topo_addr: topology address for a device to communicate with
5374 * @bus_addr: 7-bit I2C bus address
5375 * @addr: I2C memory address (I2C offset) with up to 16 bits
5376 * @params: I2C parameters: bit [4] - I2C address type, bits [3:0] - data size to write (0-7 bytes)
5377 * @data: pointer to data (0 to 4 bytes) to be written to the I2C device
5378 * @cd: pointer to command details structure or NULL
5380 * Write I2C (0x06E3)
5383 ice_aq_write_i2c(struct ice_hw *hw, struct ice_aqc_link_topo_addr topo_addr,
5384 u16 bus_addr, __le16 addr, u8 params, u8 *data,
5385 struct ice_sq_cd *cd)
5387 struct ice_aq_desc desc = { 0 };
5388 struct ice_aqc_i2c *cmd;
5391 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_write_i2c);
5392 cmd = &desc.params.read_write_i2c;
5394 data_size = (params & ICE_AQC_I2C_DATA_SIZE_M) >> ICE_AQC_I2C_DATA_SIZE_S;
5396 /* data_size limited to 4 */
5398 return ICE_ERR_PARAM;
5400 cmd->i2c_bus_addr = CPU_TO_LE16(bus_addr);
5401 cmd->topo_addr = topo_addr;
5402 cmd->i2c_params = params;
5403 cmd->i2c_addr = addr;
5405 for (i = 0; i < data_size; i++) {
5406 cmd->i2c_data[i] = *data;
5410 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
5415 * @hw: pointer to the hw struct
5416 * @gpio_ctrl_handle: GPIO controller node handle
5417 * @pin_idx: IO Number of the GPIO that needs to be set
5418 * @value: SW provide IO value to set in the LSB
5419 * @cd: pointer to command details structure or NULL
5421 * Sends 0x06EC AQ command to set the GPIO pin state that's part of the topology
5424 ice_aq_set_gpio(struct ice_hw *hw, u16 gpio_ctrl_handle, u8 pin_idx, bool value,
5425 struct ice_sq_cd *cd)
5427 struct ice_aqc_gpio *cmd;
5428 struct ice_aq_desc desc;
5430 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_gpio);
5431 cmd = &desc.params.read_write_gpio;
5432 cmd->gpio_ctrl_handle = gpio_ctrl_handle;
5433 cmd->gpio_num = pin_idx;
5434 cmd->gpio_val = value ? 1 : 0;
5436 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
5441 * @hw: pointer to the hw struct
5442 * @gpio_ctrl_handle: GPIO controller node handle
5443 * @pin_idx: IO Number of the GPIO that needs to be set
5444 * @value: IO value read
5445 * @cd: pointer to command details structure or NULL
5447 * Sends 0x06ED AQ command to get the value of a GPIO signal which is part of
5451 ice_aq_get_gpio(struct ice_hw *hw, u16 gpio_ctrl_handle, u8 pin_idx,
5452 bool *value, struct ice_sq_cd *cd)
5454 struct ice_aqc_gpio *cmd;
5455 struct ice_aq_desc desc;
5456 enum ice_status status;
5458 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_gpio);
5459 cmd = &desc.params.read_write_gpio;
5460 cmd->gpio_ctrl_handle = gpio_ctrl_handle;
5461 cmd->gpio_num = pin_idx;
5463 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
5467 *value = !!cmd->gpio_val;
5472 * ice_fw_supports_link_override
5473 * @hw: pointer to the hardware structure
5475 * Checks if the firmware supports link override
5477 bool ice_fw_supports_link_override(struct ice_hw *hw)
5479 if (hw->api_maj_ver == ICE_FW_API_LINK_OVERRIDE_MAJ) {
5480 if (hw->api_min_ver > ICE_FW_API_LINK_OVERRIDE_MIN)
5482 if (hw->api_min_ver == ICE_FW_API_LINK_OVERRIDE_MIN &&
5483 hw->api_patch >= ICE_FW_API_LINK_OVERRIDE_PATCH)
5485 } else if (hw->api_maj_ver > ICE_FW_API_LINK_OVERRIDE_MAJ) {
5493 * ice_get_link_default_override
5494 * @ldo: pointer to the link default override struct
5495 * @pi: pointer to the port info struct
5497 * Gets the link default override for a port
5500 ice_get_link_default_override(struct ice_link_default_override_tlv *ldo,
5501 struct ice_port_info *pi)
5503 u16 i, tlv, tlv_len, tlv_start, buf, offset;
5504 struct ice_hw *hw = pi->hw;
5505 enum ice_status status;
5507 status = ice_get_pfa_module_tlv(hw, &tlv, &tlv_len,
5508 ICE_SR_LINK_DEFAULT_OVERRIDE_PTR);
5510 ice_debug(hw, ICE_DBG_INIT, "Failed to read link override TLV.\n");
5514 /* Each port has its own config; calculate for our port */
5515 tlv_start = tlv + pi->lport * ICE_SR_PFA_LINK_OVERRIDE_WORDS +
5516 ICE_SR_PFA_LINK_OVERRIDE_OFFSET;
5518 /* link options first */
5519 status = ice_read_sr_word(hw, tlv_start, &buf);
5521 ice_debug(hw, ICE_DBG_INIT, "Failed to read override link options.\n");
5524 ldo->options = buf & ICE_LINK_OVERRIDE_OPT_M;
5525 ldo->phy_config = (buf & ICE_LINK_OVERRIDE_PHY_CFG_M) >>
5526 ICE_LINK_OVERRIDE_PHY_CFG_S;
5528 /* link PHY config */
5529 offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_FEC_OFFSET;
5530 status = ice_read_sr_word(hw, offset, &buf);
5532 ice_debug(hw, ICE_DBG_INIT, "Failed to read override phy config.\n");
5535 ldo->fec_options = buf & ICE_LINK_OVERRIDE_FEC_OPT_M;
5538 offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_PHY_OFFSET;
5539 for (i = 0; i < ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS; i++) {
5540 status = ice_read_sr_word(hw, (offset + i), &buf);
5542 ice_debug(hw, ICE_DBG_INIT, "Failed to read override link options.\n");
5545 /* shift 16 bits at a time to fill 64 bits */
5546 ldo->phy_type_low |= ((u64)buf << (i * 16));
5549 /* PHY types high */
5550 offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_PHY_OFFSET +
5551 ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS;
5552 for (i = 0; i < ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS; i++) {
5553 status = ice_read_sr_word(hw, (offset + i), &buf);
5555 ice_debug(hw, ICE_DBG_INIT, "Failed to read override link options.\n");
5558 /* shift 16 bits at a time to fill 64 bits */
5559 ldo->phy_type_high |= ((u64)buf << (i * 16));
5566 * ice_is_phy_caps_an_enabled - check if PHY capabilities autoneg is enabled
5567 * @caps: get PHY capability data
5569 bool ice_is_phy_caps_an_enabled(struct ice_aqc_get_phy_caps_data *caps)
5571 if (caps->caps & ICE_AQC_PHY_AN_MODE ||
5572 caps->low_power_ctrl_an & (ICE_AQC_PHY_AN_EN_CLAUSE28 |
5573 ICE_AQC_PHY_AN_EN_CLAUSE73 |
5574 ICE_AQC_PHY_AN_EN_CLAUSE37))
5581 * ice_aq_set_lldp_mib - Set the LLDP MIB
5582 * @hw: pointer to the HW struct
5583 * @mib_type: Local, Remote or both Local and Remote MIBs
5584 * @buf: pointer to the caller-supplied buffer to store the MIB block
5585 * @buf_size: size of the buffer (in bytes)
5586 * @cd: pointer to command details structure or NULL
5588 * Set the LLDP MIB. (0x0A08)
5591 ice_aq_set_lldp_mib(struct ice_hw *hw, u8 mib_type, void *buf, u16 buf_size,
5592 struct ice_sq_cd *cd)
5594 struct ice_aqc_lldp_set_local_mib *cmd;
5595 struct ice_aq_desc desc;
5597 cmd = &desc.params.lldp_set_mib;
5599 if (buf_size == 0 || !buf)
5600 return ICE_ERR_PARAM;
5602 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_lldp_set_local_mib);
5604 desc.flags |= CPU_TO_LE16((u16)ICE_AQ_FLAG_RD);
5605 desc.datalen = CPU_TO_LE16(buf_size);
5607 cmd->type = mib_type;
5608 cmd->length = CPU_TO_LE16(buf_size);
5610 return ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);
5614 * ice_fw_supports_lldp_fltr_ctrl - check NVM version supports lldp_fltr_ctrl
5615 * @hw: pointer to HW struct
5617 bool ice_fw_supports_lldp_fltr_ctrl(struct ice_hw *hw)
5619 if (hw->mac_type != ICE_MAC_E810)
5622 if (hw->api_maj_ver == ICE_FW_API_LLDP_FLTR_MAJ) {
5623 if (hw->api_min_ver > ICE_FW_API_LLDP_FLTR_MIN)
5625 if (hw->api_min_ver == ICE_FW_API_LLDP_FLTR_MIN &&
5626 hw->api_patch >= ICE_FW_API_LLDP_FLTR_PATCH)
5628 } else if (hw->api_maj_ver > ICE_FW_API_LLDP_FLTR_MAJ) {
5635 * ice_lldp_fltr_add_remove - add or remove a LLDP Rx switch filter
5636 * @hw: pointer to HW struct
5637 * @vsi_num: absolute HW index for VSI
5638 * @add: boolean for if adding or removing a filter
5641 ice_lldp_fltr_add_remove(struct ice_hw *hw, u16 vsi_num, bool add)
5643 struct ice_aqc_lldp_filter_ctrl *cmd;
5644 struct ice_aq_desc desc;
5646 cmd = &desc.params.lldp_filter_ctrl;
5648 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_lldp_filter_ctrl);
5651 cmd->cmd_flags = ICE_AQC_LLDP_FILTER_ACTION_ADD;
5653 cmd->cmd_flags = ICE_AQC_LLDP_FILTER_ACTION_DELETE;
5655 cmd->vsi_num = CPU_TO_LE16(vsi_num);
5657 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
5661 * ice_fw_supports_report_dflt_cfg
5662 * @hw: pointer to the hardware structure
5664 * Checks if the firmware supports report default configuration
5666 bool ice_fw_supports_report_dflt_cfg(struct ice_hw *hw)
5668 if (hw->api_maj_ver == ICE_FW_API_REPORT_DFLT_CFG_MAJ) {
5669 if (hw->api_min_ver > ICE_FW_API_REPORT_DFLT_CFG_MIN)
5671 if (hw->api_min_ver == ICE_FW_API_REPORT_DFLT_CFG_MIN &&
5672 hw->api_patch >= ICE_FW_API_REPORT_DFLT_CFG_PATCH)
5674 } else if (hw->api_maj_ver > ICE_FW_API_REPORT_DFLT_CFG_MAJ) {