1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2001-2021 Intel Corporation
5 #include "ice_common.h"
7 #include "ice_adminq_cmd.h"
10 #include "ice_switch.h"
12 #define ICE_PF_RESET_WAIT_COUNT 300
15 * dump_phy_type - helper function that prints PHY type strings
16 * @hw: pointer to the HW structure
17 * @phy: 64 bit PHY type to decipher
18 * @i: bit index within phy
19 * @phy_string: string corresponding to bit i in phy
20 * @prefix: prefix string to differentiate multiple dumps
23 dump_phy_type(struct ice_hw *hw, u64 phy, u8 i, const char *phy_string,
27 ice_debug(hw, ICE_DBG_PHY, "%s: bit(%d): %s\n", prefix, i,
32 * ice_dump_phy_type_low - helper function to dump phy_type_low
33 * @hw: pointer to the HW structure
34 * @low: 64 bit value for phy_type_low
35 * @prefix: prefix string to differentiate multiple dumps
38 ice_dump_phy_type_low(struct ice_hw *hw, u64 low, const char *prefix)
40 ice_debug(hw, ICE_DBG_PHY, "%s: phy_type_low: 0x%016llx\n", prefix,
41 (unsigned long long)low);
43 dump_phy_type(hw, low, 0, "100BASE_TX", prefix);
44 dump_phy_type(hw, low, 1, "100M_SGMII", prefix);
45 dump_phy_type(hw, low, 2, "1000BASE_T", prefix);
46 dump_phy_type(hw, low, 3, "1000BASE_SX", prefix);
47 dump_phy_type(hw, low, 4, "1000BASE_LX", prefix);
48 dump_phy_type(hw, low, 5, "1000BASE_KX", prefix);
49 dump_phy_type(hw, low, 6, "1G_SGMII", prefix);
50 dump_phy_type(hw, low, 7, "2500BASE_T", prefix);
51 dump_phy_type(hw, low, 8, "2500BASE_X", prefix);
52 dump_phy_type(hw, low, 9, "2500BASE_KX", prefix);
53 dump_phy_type(hw, low, 10, "5GBASE_T", prefix);
54 dump_phy_type(hw, low, 11, "5GBASE_KR", prefix);
55 dump_phy_type(hw, low, 12, "10GBASE_T", prefix);
56 dump_phy_type(hw, low, 13, "10G_SFI_DA", prefix);
57 dump_phy_type(hw, low, 14, "10GBASE_SR", prefix);
58 dump_phy_type(hw, low, 15, "10GBASE_LR", prefix);
59 dump_phy_type(hw, low, 16, "10GBASE_KR_CR1", prefix);
60 dump_phy_type(hw, low, 17, "10G_SFI_AOC_ACC", prefix);
61 dump_phy_type(hw, low, 18, "10G_SFI_C2C", prefix);
62 dump_phy_type(hw, low, 19, "25GBASE_T", prefix);
63 dump_phy_type(hw, low, 20, "25GBASE_CR", prefix);
64 dump_phy_type(hw, low, 21, "25GBASE_CR_S", prefix);
65 dump_phy_type(hw, low, 22, "25GBASE_CR1", prefix);
66 dump_phy_type(hw, low, 23, "25GBASE_SR", prefix);
67 dump_phy_type(hw, low, 24, "25GBASE_LR", prefix);
68 dump_phy_type(hw, low, 25, "25GBASE_KR", prefix);
69 dump_phy_type(hw, low, 26, "25GBASE_KR_S", prefix);
70 dump_phy_type(hw, low, 27, "25GBASE_KR1", prefix);
71 dump_phy_type(hw, low, 28, "25G_AUI_AOC_ACC", prefix);
72 dump_phy_type(hw, low, 29, "25G_AUI_C2C", prefix);
73 dump_phy_type(hw, low, 30, "40GBASE_CR4", prefix);
74 dump_phy_type(hw, low, 31, "40GBASE_SR4", prefix);
75 dump_phy_type(hw, low, 32, "40GBASE_LR4", prefix);
76 dump_phy_type(hw, low, 33, "40GBASE_KR4", prefix);
77 dump_phy_type(hw, low, 34, "40G_XLAUI_AOC_ACC", prefix);
78 dump_phy_type(hw, low, 35, "40G_XLAUI", prefix);
79 dump_phy_type(hw, low, 36, "50GBASE_CR2", prefix);
80 dump_phy_type(hw, low, 37, "50GBASE_SR2", prefix);
81 dump_phy_type(hw, low, 38, "50GBASE_LR2", prefix);
82 dump_phy_type(hw, low, 39, "50GBASE_KR2", prefix);
83 dump_phy_type(hw, low, 40, "50G_LAUI2_AOC_ACC", prefix);
84 dump_phy_type(hw, low, 41, "50G_LAUI2", prefix);
85 dump_phy_type(hw, low, 42, "50G_AUI2_AOC_ACC", prefix);
86 dump_phy_type(hw, low, 43, "50G_AUI2", prefix);
87 dump_phy_type(hw, low, 44, "50GBASE_CP", prefix);
88 dump_phy_type(hw, low, 45, "50GBASE_SR", prefix);
89 dump_phy_type(hw, low, 46, "50GBASE_FR", prefix);
90 dump_phy_type(hw, low, 47, "50GBASE_LR", prefix);
91 dump_phy_type(hw, low, 48, "50GBASE_KR_PAM4", prefix);
92 dump_phy_type(hw, low, 49, "50G_AUI1_AOC_ACC", prefix);
93 dump_phy_type(hw, low, 50, "50G_AUI1", prefix);
94 dump_phy_type(hw, low, 51, "100GBASE_CR4", prefix);
95 dump_phy_type(hw, low, 52, "100GBASE_SR4", prefix);
96 dump_phy_type(hw, low, 53, "100GBASE_LR4", prefix);
97 dump_phy_type(hw, low, 54, "100GBASE_KR4", prefix);
98 dump_phy_type(hw, low, 55, "100G_CAUI4_AOC_ACC", prefix);
99 dump_phy_type(hw, low, 56, "100G_CAUI4", prefix);
100 dump_phy_type(hw, low, 57, "100G_AUI4_AOC_ACC", prefix);
101 dump_phy_type(hw, low, 58, "100G_AUI4", prefix);
102 dump_phy_type(hw, low, 59, "100GBASE_CR_PAM4", prefix);
103 dump_phy_type(hw, low, 60, "100GBASE_KR_PAM4", prefix);
104 dump_phy_type(hw, low, 61, "100GBASE_CP2", prefix);
105 dump_phy_type(hw, low, 62, "100GBASE_SR2", prefix);
106 dump_phy_type(hw, low, 63, "100GBASE_DR", prefix);
110 * ice_dump_phy_type_high - helper function to dump phy_type_high
111 * @hw: pointer to the HW structure
112 * @high: 64 bit value for phy_type_high
113 * @prefix: prefix string to differentiate multiple dumps
116 ice_dump_phy_type_high(struct ice_hw *hw, u64 high, const char *prefix)
118 ice_debug(hw, ICE_DBG_PHY, "%s: phy_type_high: 0x%016llx\n", prefix,
119 (unsigned long long)high);
121 dump_phy_type(hw, high, 0, "100GBASE_KR2_PAM4", prefix);
122 dump_phy_type(hw, high, 1, "100G_CAUI2_AOC_ACC", prefix);
123 dump_phy_type(hw, high, 2, "100G_CAUI2", prefix);
124 dump_phy_type(hw, high, 3, "100G_AUI2_AOC_ACC", prefix);
125 dump_phy_type(hw, high, 4, "100G_AUI2", prefix);
129 * ice_set_mac_type - Sets MAC type
130 * @hw: pointer to the HW structure
132 * This function sets the MAC type of the adapter based on the
133 * vendor ID and device ID stored in the HW structure.
135 static enum ice_status ice_set_mac_type(struct ice_hw *hw)
137 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
139 if (hw->vendor_id != ICE_INTEL_VENDOR_ID)
140 return ICE_ERR_DEVICE_NOT_SUPPORTED;
142 switch (hw->device_id) {
143 case ICE_DEV_ID_E810C_BACKPLANE:
144 case ICE_DEV_ID_E810C_QSFP:
145 case ICE_DEV_ID_E810C_SFP:
146 case ICE_DEV_ID_E810_XXV_BACKPLANE:
147 case ICE_DEV_ID_E810_XXV_QSFP:
148 case ICE_DEV_ID_E810_XXV_SFP:
149 hw->mac_type = ICE_MAC_E810;
151 case ICE_DEV_ID_E822C_10G_BASE_T:
152 case ICE_DEV_ID_E822C_BACKPLANE:
153 case ICE_DEV_ID_E822C_QSFP:
154 case ICE_DEV_ID_E822C_SFP:
155 case ICE_DEV_ID_E822C_SGMII:
156 case ICE_DEV_ID_E822L_10G_BASE_T:
157 case ICE_DEV_ID_E822L_BACKPLANE:
158 case ICE_DEV_ID_E822L_SFP:
159 case ICE_DEV_ID_E822L_SGMII:
160 case ICE_DEV_ID_E823L_10G_BASE_T:
161 case ICE_DEV_ID_E823L_1GBE:
162 case ICE_DEV_ID_E823L_BACKPLANE:
163 case ICE_DEV_ID_E823L_QSFP:
164 case ICE_DEV_ID_E823L_SFP:
165 case ICE_DEV_ID_E823C_10G_BASE_T:
166 case ICE_DEV_ID_E823C_BACKPLANE:
167 case ICE_DEV_ID_E823C_QSFP:
168 case ICE_DEV_ID_E823C_SFP:
169 case ICE_DEV_ID_E823C_SGMII:
170 case ICE_DEV_ID_E824S:
171 case ICE_DEV_ID_E825C_BACKPLANE:
172 case ICE_DEV_ID_E825C_QSFP:
173 case ICE_DEV_ID_E825C_SFP:
174 case ICE_DEV_ID_E825C_1GBE:
175 case ICE_DEV_ID_E825X:
176 hw->mac_type = ICE_MAC_GENERIC;
179 hw->mac_type = ICE_MAC_UNKNOWN;
183 ice_debug(hw, ICE_DBG_INIT, "mac_type: %d\n", hw->mac_type);
189 * @hw: pointer to the hardware structure
191 * returns true if mac_type is ICE_MAC_GENERIC, false if not
193 bool ice_is_generic_mac(struct ice_hw *hw)
195 return hw->mac_type == ICE_MAC_GENERIC;
200 * @hw: pointer to the hardware structure
202 * returns true if the device is E810 based, false if not.
204 bool ice_is_e810(struct ice_hw *hw)
206 return hw->mac_type == ICE_MAC_E810;
211 * @hw: pointer to the hardware structure
213 * returns true if the device is E810T based, false if not.
215 bool ice_is_e810t(struct ice_hw *hw)
217 switch (hw->device_id) {
218 case ICE_DEV_ID_E810C_SFP:
219 if (hw->subsystem_device_id == ICE_SUBDEV_ID_E810T ||
220 hw->subsystem_device_id == ICE_SUBDEV_ID_E810T2)
223 case ICE_DEV_ID_E810C_QSFP:
224 if (hw->subsystem_device_id == ICE_SUBDEV_ID_E810T2)
235 * ice_clear_pf_cfg - Clear PF configuration
236 * @hw: pointer to the hardware structure
238 * Clears any existing PF configuration (VSIs, VSI lists, switch rules, port
239 * configuration, flow director filters, etc.).
241 enum ice_status ice_clear_pf_cfg(struct ice_hw *hw)
243 struct ice_aq_desc desc;
245 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pf_cfg);
247 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
251 * ice_aq_manage_mac_read - manage MAC address read command
252 * @hw: pointer to the HW struct
253 * @buf: a virtual buffer to hold the manage MAC read response
254 * @buf_size: Size of the virtual buffer
255 * @cd: pointer to command details structure or NULL
257 * This function is used to return per PF station MAC address (0x0107).
258 * NOTE: Upon successful completion of this command, MAC address information
259 * is returned in user specified buffer. Please interpret user specified
260 * buffer as "manage_mac_read" response.
261 * Response such as various MAC addresses are stored in HW struct (port.mac)
262 * ice_discover_dev_caps is expected to be called before this function is
265 static enum ice_status
266 ice_aq_manage_mac_read(struct ice_hw *hw, void *buf, u16 buf_size,
267 struct ice_sq_cd *cd)
269 struct ice_aqc_manage_mac_read_resp *resp;
270 struct ice_aqc_manage_mac_read *cmd;
271 struct ice_aq_desc desc;
272 enum ice_status status;
276 cmd = &desc.params.mac_read;
278 if (buf_size < sizeof(*resp))
279 return ICE_ERR_BUF_TOO_SHORT;
281 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_read);
283 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);
287 resp = (struct ice_aqc_manage_mac_read_resp *)buf;
288 flags = LE16_TO_CPU(cmd->flags) & ICE_AQC_MAN_MAC_READ_M;
290 if (!(flags & ICE_AQC_MAN_MAC_LAN_ADDR_VALID)) {
291 ice_debug(hw, ICE_DBG_LAN, "got invalid MAC address\n");
295 /* A single port can report up to two (LAN and WoL) addresses */
296 for (i = 0; i < cmd->num_addr; i++)
297 if (resp[i].addr_type == ICE_AQC_MAN_MAC_ADDR_TYPE_LAN) {
298 ice_memcpy(hw->port_info->mac.lan_addr,
299 resp[i].mac_addr, ETH_ALEN,
301 ice_memcpy(hw->port_info->mac.perm_addr,
303 ETH_ALEN, ICE_DMA_TO_NONDMA);
310 * ice_aq_get_phy_caps - returns PHY capabilities
311 * @pi: port information structure
312 * @qual_mods: report qualified modules
313 * @report_mode: report mode capabilities
314 * @pcaps: structure for PHY capabilities to be filled
315 * @cd: pointer to command details structure or NULL
317 * Returns the various PHY capabilities supported on the Port (0x0600)
320 ice_aq_get_phy_caps(struct ice_port_info *pi, bool qual_mods, u8 report_mode,
321 struct ice_aqc_get_phy_caps_data *pcaps,
322 struct ice_sq_cd *cd)
324 struct ice_aqc_get_phy_caps *cmd;
325 u16 pcaps_size = sizeof(*pcaps);
326 struct ice_aq_desc desc;
327 enum ice_status status;
331 cmd = &desc.params.get_phy;
333 if (!pcaps || (report_mode & ~ICE_AQC_REPORT_MODE_M) || !pi)
334 return ICE_ERR_PARAM;
337 if (report_mode == ICE_AQC_REPORT_DFLT_CFG &&
338 !ice_fw_supports_report_dflt_cfg(hw))
339 return ICE_ERR_PARAM;
341 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_phy_caps);
344 cmd->param0 |= CPU_TO_LE16(ICE_AQC_GET_PHY_RQM);
346 cmd->param0 |= CPU_TO_LE16(report_mode);
347 status = ice_aq_send_cmd(hw, &desc, pcaps, pcaps_size, cd);
349 ice_debug(hw, ICE_DBG_LINK, "get phy caps dump\n");
351 if (report_mode == ICE_AQC_REPORT_TOPO_CAP_MEDIA)
352 prefix = "phy_caps_media";
353 else if (report_mode == ICE_AQC_REPORT_TOPO_CAP_NO_MEDIA)
354 prefix = "phy_caps_no_media";
355 else if (report_mode == ICE_AQC_REPORT_ACTIVE_CFG)
356 prefix = "phy_caps_active";
357 else if (report_mode == ICE_AQC_REPORT_DFLT_CFG)
358 prefix = "phy_caps_default";
360 prefix = "phy_caps_invalid";
362 ice_dump_phy_type_low(hw, LE64_TO_CPU(pcaps->phy_type_low), prefix);
363 ice_dump_phy_type_high(hw, LE64_TO_CPU(pcaps->phy_type_high), prefix);
365 ice_debug(hw, ICE_DBG_LINK, "%s: report_mode = 0x%x\n",
366 prefix, report_mode);
367 ice_debug(hw, ICE_DBG_LINK, "%s: caps = 0x%x\n", prefix, pcaps->caps);
368 ice_debug(hw, ICE_DBG_LINK, "%s: low_power_ctrl_an = 0x%x\n", prefix,
369 pcaps->low_power_ctrl_an);
370 ice_debug(hw, ICE_DBG_LINK, "%s: eee_cap = 0x%x\n", prefix,
372 ice_debug(hw, ICE_DBG_LINK, "%s: eeer_value = 0x%x\n", prefix,
374 ice_debug(hw, ICE_DBG_LINK, "%s: link_fec_options = 0x%x\n", prefix,
375 pcaps->link_fec_options);
376 ice_debug(hw, ICE_DBG_LINK, "%s: module_compliance_enforcement = 0x%x\n",
377 prefix, pcaps->module_compliance_enforcement);
378 ice_debug(hw, ICE_DBG_LINK, "%s: extended_compliance_code = 0x%x\n",
379 prefix, pcaps->extended_compliance_code);
380 ice_debug(hw, ICE_DBG_LINK, "%s: module_type[0] = 0x%x\n", prefix,
381 pcaps->module_type[0]);
382 ice_debug(hw, ICE_DBG_LINK, "%s: module_type[1] = 0x%x\n", prefix,
383 pcaps->module_type[1]);
384 ice_debug(hw, ICE_DBG_LINK, "%s: module_type[2] = 0x%x\n", prefix,
385 pcaps->module_type[2]);
387 if (status == ICE_SUCCESS && report_mode == ICE_AQC_REPORT_TOPO_CAP_MEDIA) {
388 pi->phy.phy_type_low = LE64_TO_CPU(pcaps->phy_type_low);
389 pi->phy.phy_type_high = LE64_TO_CPU(pcaps->phy_type_high);
390 ice_memcpy(pi->phy.link_info.module_type, &pcaps->module_type,
391 sizeof(pi->phy.link_info.module_type),
392 ICE_NONDMA_TO_NONDMA);
399 * ice_aq_get_link_topo_handle - get link topology node return status
400 * @pi: port information structure
401 * @node_type: requested node type
402 * @cd: pointer to command details structure or NULL
404 * Get link topology node return status for specified node type (0x06E0)
406 * Node type cage can be used to determine if cage is present. If AQC
407 * returns error (ENOENT), then no cage present. If no cage present, then
408 * connection type is backplane or BASE-T.
410 static enum ice_status
411 ice_aq_get_link_topo_handle(struct ice_port_info *pi, u8 node_type,
412 struct ice_sq_cd *cd)
414 struct ice_aqc_get_link_topo *cmd;
415 struct ice_aq_desc desc;
417 cmd = &desc.params.get_link_topo;
419 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_topo);
421 cmd->addr.topo_params.node_type_ctx =
422 (ICE_AQC_LINK_TOPO_NODE_CTX_PORT <<
423 ICE_AQC_LINK_TOPO_NODE_CTX_S);
426 cmd->addr.topo_params.node_type_ctx |=
427 (ICE_AQC_LINK_TOPO_NODE_TYPE_M & node_type);
429 return ice_aq_send_cmd(pi->hw, &desc, NULL, 0, cd);
433 * ice_is_media_cage_present
434 * @pi: port information structure
436 * Returns true if media cage is present, else false. If no cage, then
437 * media type is backplane or BASE-T.
439 static bool ice_is_media_cage_present(struct ice_port_info *pi)
441 /* Node type cage can be used to determine if cage is present. If AQC
442 * returns error (ENOENT), then no cage present. If no cage present then
443 * connection type is backplane or BASE-T.
445 return !ice_aq_get_link_topo_handle(pi,
446 ICE_AQC_LINK_TOPO_NODE_TYPE_CAGE,
451 * ice_get_media_type - Gets media type
452 * @pi: port information structure
454 static enum ice_media_type ice_get_media_type(struct ice_port_info *pi)
456 struct ice_link_status *hw_link_info;
459 return ICE_MEDIA_UNKNOWN;
461 hw_link_info = &pi->phy.link_info;
462 if (hw_link_info->phy_type_low && hw_link_info->phy_type_high)
463 /* If more than one media type is selected, report unknown */
464 return ICE_MEDIA_UNKNOWN;
466 if (hw_link_info->phy_type_low) {
467 /* 1G SGMII is a special case where some DA cable PHYs
468 * may show this as an option when it really shouldn't
469 * be since SGMII is meant to be between a MAC and a PHY
470 * in a backplane. Try to detect this case and handle it
472 if (hw_link_info->phy_type_low == ICE_PHY_TYPE_LOW_1G_SGMII &&
473 (hw_link_info->module_type[ICE_AQC_MOD_TYPE_IDENT] ==
474 ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_ACTIVE ||
475 hw_link_info->module_type[ICE_AQC_MOD_TYPE_IDENT] ==
476 ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_PASSIVE))
479 switch (hw_link_info->phy_type_low) {
480 case ICE_PHY_TYPE_LOW_1000BASE_SX:
481 case ICE_PHY_TYPE_LOW_1000BASE_LX:
482 case ICE_PHY_TYPE_LOW_10GBASE_SR:
483 case ICE_PHY_TYPE_LOW_10GBASE_LR:
484 case ICE_PHY_TYPE_LOW_10G_SFI_C2C:
485 case ICE_PHY_TYPE_LOW_25GBASE_SR:
486 case ICE_PHY_TYPE_LOW_25GBASE_LR:
487 case ICE_PHY_TYPE_LOW_40GBASE_SR4:
488 case ICE_PHY_TYPE_LOW_40GBASE_LR4:
489 case ICE_PHY_TYPE_LOW_50GBASE_SR2:
490 case ICE_PHY_TYPE_LOW_50GBASE_LR2:
491 case ICE_PHY_TYPE_LOW_50GBASE_SR:
492 case ICE_PHY_TYPE_LOW_50GBASE_FR:
493 case ICE_PHY_TYPE_LOW_50GBASE_LR:
494 case ICE_PHY_TYPE_LOW_100GBASE_SR4:
495 case ICE_PHY_TYPE_LOW_100GBASE_LR4:
496 case ICE_PHY_TYPE_LOW_100GBASE_SR2:
497 case ICE_PHY_TYPE_LOW_100GBASE_DR:
498 return ICE_MEDIA_FIBER;
499 case ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC:
500 case ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC:
501 case ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC:
502 case ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC:
503 case ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC:
504 case ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC:
505 case ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC:
506 case ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC:
507 return ICE_MEDIA_FIBER;
508 case ICE_PHY_TYPE_LOW_100BASE_TX:
509 case ICE_PHY_TYPE_LOW_1000BASE_T:
510 case ICE_PHY_TYPE_LOW_2500BASE_T:
511 case ICE_PHY_TYPE_LOW_5GBASE_T:
512 case ICE_PHY_TYPE_LOW_10GBASE_T:
513 case ICE_PHY_TYPE_LOW_25GBASE_T:
514 return ICE_MEDIA_BASET;
515 case ICE_PHY_TYPE_LOW_10G_SFI_DA:
516 case ICE_PHY_TYPE_LOW_25GBASE_CR:
517 case ICE_PHY_TYPE_LOW_25GBASE_CR_S:
518 case ICE_PHY_TYPE_LOW_25GBASE_CR1:
519 case ICE_PHY_TYPE_LOW_40GBASE_CR4:
520 case ICE_PHY_TYPE_LOW_50GBASE_CR2:
521 case ICE_PHY_TYPE_LOW_50GBASE_CP:
522 case ICE_PHY_TYPE_LOW_100GBASE_CR4:
523 case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4:
524 case ICE_PHY_TYPE_LOW_100GBASE_CP2:
526 case ICE_PHY_TYPE_LOW_25G_AUI_C2C:
527 case ICE_PHY_TYPE_LOW_40G_XLAUI:
528 case ICE_PHY_TYPE_LOW_50G_LAUI2:
529 case ICE_PHY_TYPE_LOW_50G_AUI2:
530 case ICE_PHY_TYPE_LOW_50G_AUI1:
531 case ICE_PHY_TYPE_LOW_100G_AUI4:
532 case ICE_PHY_TYPE_LOW_100G_CAUI4:
533 if (ice_is_media_cage_present(pi))
534 return ICE_MEDIA_AUI;
536 case ICE_PHY_TYPE_LOW_1000BASE_KX:
537 case ICE_PHY_TYPE_LOW_2500BASE_KX:
538 case ICE_PHY_TYPE_LOW_2500BASE_X:
539 case ICE_PHY_TYPE_LOW_5GBASE_KR:
540 case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1:
541 case ICE_PHY_TYPE_LOW_25GBASE_KR:
542 case ICE_PHY_TYPE_LOW_25GBASE_KR1:
543 case ICE_PHY_TYPE_LOW_25GBASE_KR_S:
544 case ICE_PHY_TYPE_LOW_40GBASE_KR4:
545 case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4:
546 case ICE_PHY_TYPE_LOW_50GBASE_KR2:
547 case ICE_PHY_TYPE_LOW_100GBASE_KR4:
548 case ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4:
549 return ICE_MEDIA_BACKPLANE;
552 switch (hw_link_info->phy_type_high) {
553 case ICE_PHY_TYPE_HIGH_100G_AUI2:
554 case ICE_PHY_TYPE_HIGH_100G_CAUI2:
555 if (ice_is_media_cage_present(pi))
556 return ICE_MEDIA_AUI;
558 case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4:
559 return ICE_MEDIA_BACKPLANE;
560 case ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC:
561 case ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC:
562 return ICE_MEDIA_FIBER;
565 return ICE_MEDIA_UNKNOWN;
569 * ice_aq_get_link_info
570 * @pi: port information structure
571 * @ena_lse: enable/disable LinkStatusEvent reporting
572 * @link: pointer to link status structure - optional
573 * @cd: pointer to command details structure or NULL
575 * Get Link Status (0x607). Returns the link status of the adapter.
578 ice_aq_get_link_info(struct ice_port_info *pi, bool ena_lse,
579 struct ice_link_status *link, struct ice_sq_cd *cd)
581 struct ice_aqc_get_link_status_data link_data = { 0 };
582 struct ice_aqc_get_link_status *resp;
583 struct ice_link_status *li_old, *li;
584 enum ice_media_type *hw_media_type;
585 struct ice_fc_info *hw_fc_info;
586 bool tx_pause, rx_pause;
587 struct ice_aq_desc desc;
588 enum ice_status status;
593 return ICE_ERR_PARAM;
595 li_old = &pi->phy.link_info_old;
596 hw_media_type = &pi->phy.media_type;
597 li = &pi->phy.link_info;
598 hw_fc_info = &pi->fc;
600 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_status);
601 cmd_flags = (ena_lse) ? ICE_AQ_LSE_ENA : ICE_AQ_LSE_DIS;
602 resp = &desc.params.get_link_status;
603 resp->cmd_flags = CPU_TO_LE16(cmd_flags);
604 resp->lport_num = pi->lport;
606 status = ice_aq_send_cmd(hw, &desc, &link_data, sizeof(link_data), cd);
608 if (status != ICE_SUCCESS)
611 /* save off old link status information */
614 /* update current link status information */
615 li->link_speed = LE16_TO_CPU(link_data.link_speed);
616 li->phy_type_low = LE64_TO_CPU(link_data.phy_type_low);
617 li->phy_type_high = LE64_TO_CPU(link_data.phy_type_high);
618 *hw_media_type = ice_get_media_type(pi);
619 li->link_info = link_data.link_info;
620 li->link_cfg_err = link_data.link_cfg_err;
621 li->an_info = link_data.an_info;
622 li->ext_info = link_data.ext_info;
623 li->max_frame_size = LE16_TO_CPU(link_data.max_frame_size);
624 li->fec_info = link_data.cfg & ICE_AQ_FEC_MASK;
625 li->topo_media_conflict = link_data.topo_media_conflict;
626 li->pacing = link_data.cfg & (ICE_AQ_CFG_PACING_M |
627 ICE_AQ_CFG_PACING_TYPE_M);
630 tx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_TX);
631 rx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_RX);
632 if (tx_pause && rx_pause)
633 hw_fc_info->current_mode = ICE_FC_FULL;
635 hw_fc_info->current_mode = ICE_FC_TX_PAUSE;
637 hw_fc_info->current_mode = ICE_FC_RX_PAUSE;
639 hw_fc_info->current_mode = ICE_FC_NONE;
641 li->lse_ena = !!(resp->cmd_flags & CPU_TO_LE16(ICE_AQ_LSE_IS_ENABLED));
643 ice_debug(hw, ICE_DBG_LINK, "get link info\n");
644 ice_debug(hw, ICE_DBG_LINK, " link_speed = 0x%x\n", li->link_speed);
645 ice_debug(hw, ICE_DBG_LINK, " phy_type_low = 0x%llx\n",
646 (unsigned long long)li->phy_type_low);
647 ice_debug(hw, ICE_DBG_LINK, " phy_type_high = 0x%llx\n",
648 (unsigned long long)li->phy_type_high);
649 ice_debug(hw, ICE_DBG_LINK, " media_type = 0x%x\n", *hw_media_type);
650 ice_debug(hw, ICE_DBG_LINK, " link_info = 0x%x\n", li->link_info);
651 ice_debug(hw, ICE_DBG_LINK, " link_cfg_err = 0x%x\n", li->link_cfg_err);
652 ice_debug(hw, ICE_DBG_LINK, " an_info = 0x%x\n", li->an_info);
653 ice_debug(hw, ICE_DBG_LINK, " ext_info = 0x%x\n", li->ext_info);
654 ice_debug(hw, ICE_DBG_LINK, " fec_info = 0x%x\n", li->fec_info);
655 ice_debug(hw, ICE_DBG_LINK, " lse_ena = 0x%x\n", li->lse_ena);
656 ice_debug(hw, ICE_DBG_LINK, " max_frame = 0x%x\n",
658 ice_debug(hw, ICE_DBG_LINK, " pacing = 0x%x\n", li->pacing);
660 /* save link status information */
664 /* flag cleared so calling functions don't call AQ again */
665 pi->phy.get_link_info = false;
671 * ice_fill_tx_timer_and_fc_thresh
672 * @hw: pointer to the HW struct
673 * @cmd: pointer to MAC cfg structure
675 * Add Tx timer and FC refresh threshold info to Set MAC Config AQ command
679 ice_fill_tx_timer_and_fc_thresh(struct ice_hw *hw,
680 struct ice_aqc_set_mac_cfg *cmd)
682 u16 fc_thres_val, tx_timer_val;
685 /* We read back the transmit timer and fc threshold value of
686 * LFC. Thus, we will use index =
687 * PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX.
689 * Also, because we are opearating on transmit timer and fc
690 * threshold of LFC, we don't turn on any bit in tx_tmr_priority
692 #define IDX_OF_LFC PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX
694 /* Retrieve the transmit timer */
695 val = rd32(hw, PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(IDX_OF_LFC));
697 PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_HSEC_CTL_TX_PAUSE_QUANTA_M;
698 cmd->tx_tmr_value = CPU_TO_LE16(tx_timer_val);
700 /* Retrieve the fc threshold */
701 val = rd32(hw, PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(IDX_OF_LFC));
702 fc_thres_val = val & PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_M;
704 cmd->fc_refresh_threshold = CPU_TO_LE16(fc_thres_val);
709 * @hw: pointer to the HW struct
710 * @max_frame_size: Maximum Frame Size to be supported
711 * @cd: pointer to command details structure or NULL
713 * Set MAC configuration (0x0603)
716 ice_aq_set_mac_cfg(struct ice_hw *hw, u16 max_frame_size, struct ice_sq_cd *cd)
718 struct ice_aqc_set_mac_cfg *cmd;
719 struct ice_aq_desc desc;
721 cmd = &desc.params.set_mac_cfg;
723 if (max_frame_size == 0)
724 return ICE_ERR_PARAM;
726 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_mac_cfg);
728 cmd->max_frame_size = CPU_TO_LE16(max_frame_size);
730 ice_fill_tx_timer_and_fc_thresh(hw, cmd);
732 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
736 * ice_init_fltr_mgmt_struct - initializes filter management list and locks
737 * @hw: pointer to the HW struct
739 enum ice_status ice_init_fltr_mgmt_struct(struct ice_hw *hw)
741 struct ice_switch_info *sw;
742 enum ice_status status;
744 hw->switch_info = (struct ice_switch_info *)
745 ice_malloc(hw, sizeof(*hw->switch_info));
747 sw = hw->switch_info;
750 return ICE_ERR_NO_MEMORY;
752 INIT_LIST_HEAD(&sw->vsi_list_map_head);
753 sw->prof_res_bm_init = 0;
755 status = ice_init_def_sw_recp(hw, &hw->switch_info->recp_list);
757 ice_free(hw, hw->switch_info);
764 * ice_cleanup_fltr_mgmt_single - clears single filter mngt struct
765 * @hw: pointer to the HW struct
766 * @sw: pointer to switch info struct for which function clears filters
769 ice_cleanup_fltr_mgmt_single(struct ice_hw *hw, struct ice_switch_info *sw)
771 struct ice_vsi_list_map_info *v_pos_map;
772 struct ice_vsi_list_map_info *v_tmp_map;
773 struct ice_sw_recipe *recps;
779 LIST_FOR_EACH_ENTRY_SAFE(v_pos_map, v_tmp_map, &sw->vsi_list_map_head,
780 ice_vsi_list_map_info, list_entry) {
781 LIST_DEL(&v_pos_map->list_entry);
782 ice_free(hw, v_pos_map);
784 recps = sw->recp_list;
785 for (i = 0; i < ICE_MAX_NUM_RECIPES; i++) {
786 struct ice_recp_grp_entry *rg_entry, *tmprg_entry;
788 recps[i].root_rid = i;
789 LIST_FOR_EACH_ENTRY_SAFE(rg_entry, tmprg_entry,
790 &recps[i].rg_list, ice_recp_grp_entry,
792 LIST_DEL(&rg_entry->l_entry);
793 ice_free(hw, rg_entry);
796 if (recps[i].adv_rule) {
797 struct ice_adv_fltr_mgmt_list_entry *tmp_entry;
798 struct ice_adv_fltr_mgmt_list_entry *lst_itr;
800 ice_destroy_lock(&recps[i].filt_rule_lock);
801 LIST_FOR_EACH_ENTRY_SAFE(lst_itr, tmp_entry,
802 &recps[i].filt_rules,
803 ice_adv_fltr_mgmt_list_entry,
805 LIST_DEL(&lst_itr->list_entry);
806 ice_free(hw, lst_itr->lkups);
807 ice_free(hw, lst_itr);
810 struct ice_fltr_mgmt_list_entry *lst_itr, *tmp_entry;
812 ice_destroy_lock(&recps[i].filt_rule_lock);
813 LIST_FOR_EACH_ENTRY_SAFE(lst_itr, tmp_entry,
814 &recps[i].filt_rules,
815 ice_fltr_mgmt_list_entry,
817 LIST_DEL(&lst_itr->list_entry);
818 ice_free(hw, lst_itr);
821 if (recps[i].root_buf)
822 ice_free(hw, recps[i].root_buf);
824 ice_rm_sw_replay_rule_info(hw, sw);
825 ice_free(hw, sw->recp_list);
830 * ice_cleanup_fltr_mgmt_struct - cleanup filter management list and locks
831 * @hw: pointer to the HW struct
833 void ice_cleanup_fltr_mgmt_struct(struct ice_hw *hw)
835 ice_cleanup_fltr_mgmt_single(hw, hw->switch_info);
839 * ice_get_itr_intrl_gran
840 * @hw: pointer to the HW struct
842 * Determines the ITR/INTRL granularities based on the maximum aggregate
843 * bandwidth according to the device's configuration during power-on.
845 static void ice_get_itr_intrl_gran(struct ice_hw *hw)
847 u8 max_agg_bw = (rd32(hw, GL_PWR_MODE_CTL) &
848 GL_PWR_MODE_CTL_CAR_MAX_BW_M) >>
849 GL_PWR_MODE_CTL_CAR_MAX_BW_S;
851 switch (max_agg_bw) {
852 case ICE_MAX_AGG_BW_200G:
853 case ICE_MAX_AGG_BW_100G:
854 case ICE_MAX_AGG_BW_50G:
855 hw->itr_gran = ICE_ITR_GRAN_ABOVE_25;
856 hw->intrl_gran = ICE_INTRL_GRAN_ABOVE_25;
858 case ICE_MAX_AGG_BW_25G:
859 hw->itr_gran = ICE_ITR_GRAN_MAX_25;
860 hw->intrl_gran = ICE_INTRL_GRAN_MAX_25;
866 * ice_print_rollback_msg - print FW rollback message
867 * @hw: pointer to the hardware structure
869 void ice_print_rollback_msg(struct ice_hw *hw)
871 char nvm_str[ICE_NVM_VER_LEN] = { 0 };
872 struct ice_orom_info *orom;
873 struct ice_nvm_info *nvm;
875 orom = &hw->flash.orom;
876 nvm = &hw->flash.nvm;
878 SNPRINTF(nvm_str, sizeof(nvm_str), "%x.%02x 0x%x %d.%d.%d",
879 nvm->major, nvm->minor, nvm->eetrack, orom->major,
880 orom->build, orom->patch);
882 "Firmware rollback mode detected. Current version is NVM: %s, FW: %d.%d. Device may exhibit limited functionality. Refer to the Intel(R) Ethernet Adapters and Devices User Guide for details on firmware rollback mode\n",
883 nvm_str, hw->fw_maj_ver, hw->fw_min_ver);
887 * ice_set_umac_shared
888 * @hw: pointer to the hw struct
890 * Set boolean flag to allow unicast MAC sharing
892 void ice_set_umac_shared(struct ice_hw *hw)
894 hw->umac_shared = true;
898 * ice_init_hw - main hardware initialization routine
899 * @hw: pointer to the hardware structure
901 enum ice_status ice_init_hw(struct ice_hw *hw)
903 struct ice_aqc_get_phy_caps_data *pcaps;
904 enum ice_status status;
908 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
910 /* Set MAC type based on DeviceID */
911 status = ice_set_mac_type(hw);
915 hw->pf_id = (u8)(rd32(hw, PF_FUNC_RID) &
916 PF_FUNC_RID_FUNCTION_NUMBER_M) >>
917 PF_FUNC_RID_FUNCTION_NUMBER_S;
919 status = ice_reset(hw, ICE_RESET_PFR);
923 ice_get_itr_intrl_gran(hw);
925 status = ice_create_all_ctrlq(hw);
927 goto err_unroll_cqinit;
929 status = ice_init_nvm(hw);
931 goto err_unroll_cqinit;
933 if (ice_get_fw_mode(hw) == ICE_FW_MODE_ROLLBACK)
934 ice_print_rollback_msg(hw);
936 status = ice_clear_pf_cfg(hw);
938 goto err_unroll_cqinit;
940 /* Set bit to enable Flow Director filters */
941 wr32(hw, PFQF_FD_ENA, PFQF_FD_ENA_FD_ENA_M);
942 INIT_LIST_HEAD(&hw->fdir_list_head);
944 ice_clear_pxe_mode(hw);
946 status = ice_get_caps(hw);
948 goto err_unroll_cqinit;
950 hw->port_info = (struct ice_port_info *)
951 ice_malloc(hw, sizeof(*hw->port_info));
952 if (!hw->port_info) {
953 status = ICE_ERR_NO_MEMORY;
954 goto err_unroll_cqinit;
957 /* set the back pointer to HW */
958 hw->port_info->hw = hw;
960 /* Initialize port_info struct with switch configuration data */
961 status = ice_get_initial_sw_cfg(hw);
963 goto err_unroll_alloc;
966 /* Query the allocated resources for Tx scheduler */
967 status = ice_sched_query_res_alloc(hw);
969 ice_debug(hw, ICE_DBG_SCHED, "Failed to get scheduler allocated resources\n");
970 goto err_unroll_alloc;
972 ice_sched_get_psm_clk_freq(hw);
974 /* Initialize port_info struct with scheduler data */
975 status = ice_sched_init_port(hw->port_info);
977 goto err_unroll_sched;
978 pcaps = (struct ice_aqc_get_phy_caps_data *)
979 ice_malloc(hw, sizeof(*pcaps));
981 status = ICE_ERR_NO_MEMORY;
982 goto err_unroll_sched;
985 /* Initialize port_info struct with PHY capabilities */
986 status = ice_aq_get_phy_caps(hw->port_info, false,
987 ICE_AQC_REPORT_TOPO_CAP_MEDIA, pcaps, NULL);
990 ice_warn(hw, "Get PHY capabilities failed status = %d, continuing anyway\n",
993 /* Initialize port_info struct with link information */
994 status = ice_aq_get_link_info(hw->port_info, false, NULL, NULL);
996 goto err_unroll_sched;
997 /* need a valid SW entry point to build a Tx tree */
998 if (!hw->sw_entry_point_layer) {
999 ice_debug(hw, ICE_DBG_SCHED, "invalid sw entry point\n");
1000 status = ICE_ERR_CFG;
1001 goto err_unroll_sched;
1003 INIT_LIST_HEAD(&hw->agg_list);
1004 /* Initialize max burst size */
1005 if (!hw->max_burst_size)
1006 ice_cfg_rl_burst_size(hw, ICE_SCHED_DFLT_BURST_SIZE);
1007 status = ice_init_fltr_mgmt_struct(hw);
1009 goto err_unroll_sched;
1011 /* Get MAC information */
1012 /* A single port can report up to two (LAN and WoL) addresses */
1013 mac_buf = ice_calloc(hw, 2,
1014 sizeof(struct ice_aqc_manage_mac_read_resp));
1015 mac_buf_len = 2 * sizeof(struct ice_aqc_manage_mac_read_resp);
1018 status = ICE_ERR_NO_MEMORY;
1019 goto err_unroll_fltr_mgmt_struct;
1022 status = ice_aq_manage_mac_read(hw, mac_buf, mac_buf_len, NULL);
1023 ice_free(hw, mac_buf);
1026 goto err_unroll_fltr_mgmt_struct;
1028 /* enable jumbo frame support at MAC level */
1029 status = ice_aq_set_mac_cfg(hw, ICE_AQ_SET_MAC_FRAME_SIZE_MAX, NULL);
1031 goto err_unroll_fltr_mgmt_struct;
1033 /* Obtain counter base index which would be used by flow director */
1034 status = ice_alloc_fd_res_cntr(hw, &hw->fd_ctr_base);
1036 goto err_unroll_fltr_mgmt_struct;
1037 status = ice_init_hw_tbls(hw);
1039 goto err_unroll_fltr_mgmt_struct;
1040 ice_init_lock(&hw->tnl_lock);
1044 err_unroll_fltr_mgmt_struct:
1045 ice_cleanup_fltr_mgmt_struct(hw);
1047 ice_sched_cleanup_all(hw);
1049 ice_free(hw, hw->port_info);
1050 hw->port_info = NULL;
1052 ice_destroy_all_ctrlq(hw);
1057 * ice_deinit_hw - unroll initialization operations done by ice_init_hw
1058 * @hw: pointer to the hardware structure
1060 * This should be called only during nominal operation, not as a result of
1061 * ice_init_hw() failing since ice_init_hw() will take care of unrolling
1062 * applicable initializations if it fails for any reason.
1064 void ice_deinit_hw(struct ice_hw *hw)
1066 ice_free_fd_res_cntr(hw, hw->fd_ctr_base);
1067 ice_cleanup_fltr_mgmt_struct(hw);
1069 ice_sched_cleanup_all(hw);
1070 ice_sched_clear_agg(hw);
1072 ice_free_hw_tbls(hw);
1073 ice_destroy_lock(&hw->tnl_lock);
1075 if (hw->port_info) {
1076 ice_free(hw, hw->port_info);
1077 hw->port_info = NULL;
1080 ice_destroy_all_ctrlq(hw);
1082 /* Clear VSI contexts if not already cleared */
1083 ice_clear_all_vsi_ctx(hw);
1087 * ice_check_reset - Check to see if a global reset is complete
1088 * @hw: pointer to the hardware structure
1090 enum ice_status ice_check_reset(struct ice_hw *hw)
1092 u32 cnt, reg = 0, grst_timeout, uld_mask;
1094 /* Poll for Device Active state in case a recent CORER, GLOBR,
1095 * or EMPR has occurred. The grst delay value is in 100ms units.
1096 * Add 1sec for outstanding AQ commands that can take a long time.
1098 grst_timeout = ((rd32(hw, GLGEN_RSTCTL) & GLGEN_RSTCTL_GRSTDEL_M) >>
1099 GLGEN_RSTCTL_GRSTDEL_S) + 10;
1101 for (cnt = 0; cnt < grst_timeout; cnt++) {
1102 ice_msec_delay(100, true);
1103 reg = rd32(hw, GLGEN_RSTAT);
1104 if (!(reg & GLGEN_RSTAT_DEVSTATE_M))
1108 if (cnt == grst_timeout) {
1109 ice_debug(hw, ICE_DBG_INIT, "Global reset polling failed to complete.\n");
1110 return ICE_ERR_RESET_FAILED;
1113 #define ICE_RESET_DONE_MASK (GLNVM_ULD_PCIER_DONE_M |\
1114 GLNVM_ULD_PCIER_DONE_1_M |\
1115 GLNVM_ULD_CORER_DONE_M |\
1116 GLNVM_ULD_GLOBR_DONE_M |\
1117 GLNVM_ULD_POR_DONE_M |\
1118 GLNVM_ULD_POR_DONE_1_M |\
1119 GLNVM_ULD_PCIER_DONE_2_M)
1121 uld_mask = ICE_RESET_DONE_MASK;
1123 /* Device is Active; check Global Reset processes are done */
1124 for (cnt = 0; cnt < ICE_PF_RESET_WAIT_COUNT; cnt++) {
1125 reg = rd32(hw, GLNVM_ULD) & uld_mask;
1126 if (reg == uld_mask) {
1127 ice_debug(hw, ICE_DBG_INIT, "Global reset processes done. %d\n", cnt);
1130 ice_msec_delay(10, true);
1133 if (cnt == ICE_PF_RESET_WAIT_COUNT) {
1134 ice_debug(hw, ICE_DBG_INIT, "Wait for Reset Done timed out. GLNVM_ULD = 0x%x\n",
1136 return ICE_ERR_RESET_FAILED;
1143 * ice_pf_reset - Reset the PF
1144 * @hw: pointer to the hardware structure
1146 * If a global reset has been triggered, this function checks
1147 * for its completion and then issues the PF reset
1149 static enum ice_status ice_pf_reset(struct ice_hw *hw)
1153 /* If at function entry a global reset was already in progress, i.e.
1154 * state is not 'device active' or any of the reset done bits are not
1155 * set in GLNVM_ULD, there is no need for a PF Reset; poll until the
1156 * global reset is done.
1158 if ((rd32(hw, GLGEN_RSTAT) & GLGEN_RSTAT_DEVSTATE_M) ||
1159 (rd32(hw, GLNVM_ULD) & ICE_RESET_DONE_MASK) ^ ICE_RESET_DONE_MASK) {
1160 /* poll on global reset currently in progress until done */
1161 if (ice_check_reset(hw))
1162 return ICE_ERR_RESET_FAILED;
1168 reg = rd32(hw, PFGEN_CTRL);
1170 wr32(hw, PFGEN_CTRL, (reg | PFGEN_CTRL_PFSWR_M));
1172 /* Wait for the PFR to complete. The wait time is the global config lock
1173 * timeout plus the PFR timeout which will account for a possible reset
1174 * that is occurring during a download package operation.
1176 for (cnt = 0; cnt < ICE_GLOBAL_CFG_LOCK_TIMEOUT +
1177 ICE_PF_RESET_WAIT_COUNT; cnt++) {
1178 reg = rd32(hw, PFGEN_CTRL);
1179 if (!(reg & PFGEN_CTRL_PFSWR_M))
1182 ice_msec_delay(1, true);
1185 if (cnt == ICE_PF_RESET_WAIT_COUNT) {
1186 ice_debug(hw, ICE_DBG_INIT, "PF reset polling failed to complete.\n");
1187 return ICE_ERR_RESET_FAILED;
1194 * ice_reset - Perform different types of reset
1195 * @hw: pointer to the hardware structure
1196 * @req: reset request
1198 * This function triggers a reset as specified by the req parameter.
1201 * If anything other than a PF reset is triggered, PXE mode is restored.
1202 * This has to be cleared using ice_clear_pxe_mode again, once the AQ
1203 * interface has been restored in the rebuild flow.
1205 enum ice_status ice_reset(struct ice_hw *hw, enum ice_reset_req req)
1211 return ice_pf_reset(hw);
1212 case ICE_RESET_CORER:
1213 ice_debug(hw, ICE_DBG_INIT, "CoreR requested\n");
1214 val = GLGEN_RTRIG_CORER_M;
1216 case ICE_RESET_GLOBR:
1217 ice_debug(hw, ICE_DBG_INIT, "GlobalR requested\n");
1218 val = GLGEN_RTRIG_GLOBR_M;
1221 return ICE_ERR_PARAM;
1224 val |= rd32(hw, GLGEN_RTRIG);
1225 wr32(hw, GLGEN_RTRIG, val);
1228 /* wait for the FW to be ready */
1229 return ice_check_reset(hw);
1233 * ice_copy_rxq_ctx_to_hw
1234 * @hw: pointer to the hardware structure
1235 * @ice_rxq_ctx: pointer to the rxq context
1236 * @rxq_index: the index of the Rx queue
1238 * Copies rxq context from dense structure to HW register space
1240 static enum ice_status
1241 ice_copy_rxq_ctx_to_hw(struct ice_hw *hw, u8 *ice_rxq_ctx, u32 rxq_index)
1246 return ICE_ERR_BAD_PTR;
1248 if (rxq_index > QRX_CTRL_MAX_INDEX)
1249 return ICE_ERR_PARAM;
1251 /* Copy each dword separately to HW */
1252 for (i = 0; i < ICE_RXQ_CTX_SIZE_DWORDS; i++) {
1253 wr32(hw, QRX_CONTEXT(i, rxq_index),
1254 *((u32 *)(ice_rxq_ctx + (i * sizeof(u32)))));
1256 ice_debug(hw, ICE_DBG_QCTX, "qrxdata[%d]: %08X\n", i,
1257 *((u32 *)(ice_rxq_ctx + (i * sizeof(u32)))));
1263 /* LAN Rx Queue Context */
1264 static const struct ice_ctx_ele ice_rlan_ctx_info[] = {
1265 /* Field Width LSB */
1266 ICE_CTX_STORE(ice_rlan_ctx, head, 13, 0),
1267 ICE_CTX_STORE(ice_rlan_ctx, cpuid, 8, 13),
1268 ICE_CTX_STORE(ice_rlan_ctx, base, 57, 32),
1269 ICE_CTX_STORE(ice_rlan_ctx, qlen, 13, 89),
1270 ICE_CTX_STORE(ice_rlan_ctx, dbuf, 7, 102),
1271 ICE_CTX_STORE(ice_rlan_ctx, hbuf, 5, 109),
1272 ICE_CTX_STORE(ice_rlan_ctx, dtype, 2, 114),
1273 ICE_CTX_STORE(ice_rlan_ctx, dsize, 1, 116),
1274 ICE_CTX_STORE(ice_rlan_ctx, crcstrip, 1, 117),
1275 ICE_CTX_STORE(ice_rlan_ctx, l2tsel, 1, 119),
1276 ICE_CTX_STORE(ice_rlan_ctx, hsplit_0, 4, 120),
1277 ICE_CTX_STORE(ice_rlan_ctx, hsplit_1, 2, 124),
1278 ICE_CTX_STORE(ice_rlan_ctx, showiv, 1, 127),
1279 ICE_CTX_STORE(ice_rlan_ctx, rxmax, 14, 174),
1280 ICE_CTX_STORE(ice_rlan_ctx, tphrdesc_ena, 1, 193),
1281 ICE_CTX_STORE(ice_rlan_ctx, tphwdesc_ena, 1, 194),
1282 ICE_CTX_STORE(ice_rlan_ctx, tphdata_ena, 1, 195),
1283 ICE_CTX_STORE(ice_rlan_ctx, tphhead_ena, 1, 196),
1284 ICE_CTX_STORE(ice_rlan_ctx, lrxqthresh, 3, 198),
1285 ICE_CTX_STORE(ice_rlan_ctx, prefena, 1, 201),
1291 * @hw: pointer to the hardware structure
1292 * @rlan_ctx: pointer to the rxq context
1293 * @rxq_index: the index of the Rx queue
1295 * Converts rxq context from sparse to dense structure and then writes
1296 * it to HW register space and enables the hardware to prefetch descriptors
1297 * instead of only fetching them on demand
1300 ice_write_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx,
1303 u8 ctx_buf[ICE_RXQ_CTX_SZ] = { 0 };
1306 return ICE_ERR_BAD_PTR;
1308 rlan_ctx->prefena = 1;
1310 ice_set_ctx(hw, (u8 *)rlan_ctx, ctx_buf, ice_rlan_ctx_info);
1311 return ice_copy_rxq_ctx_to_hw(hw, ctx_buf, rxq_index);
1316 * @hw: pointer to the hardware structure
1317 * @rxq_index: the index of the Rx queue to clear
1319 * Clears rxq context in HW register space
1321 enum ice_status ice_clear_rxq_ctx(struct ice_hw *hw, u32 rxq_index)
1325 if (rxq_index > QRX_CTRL_MAX_INDEX)
1326 return ICE_ERR_PARAM;
1328 /* Clear each dword register separately */
1329 for (i = 0; i < ICE_RXQ_CTX_SIZE_DWORDS; i++)
1330 wr32(hw, QRX_CONTEXT(i, rxq_index), 0);
1335 /* LAN Tx Queue Context */
1336 const struct ice_ctx_ele ice_tlan_ctx_info[] = {
1337 /* Field Width LSB */
1338 ICE_CTX_STORE(ice_tlan_ctx, base, 57, 0),
1339 ICE_CTX_STORE(ice_tlan_ctx, port_num, 3, 57),
1340 ICE_CTX_STORE(ice_tlan_ctx, cgd_num, 5, 60),
1341 ICE_CTX_STORE(ice_tlan_ctx, pf_num, 3, 65),
1342 ICE_CTX_STORE(ice_tlan_ctx, vmvf_num, 10, 68),
1343 ICE_CTX_STORE(ice_tlan_ctx, vmvf_type, 2, 78),
1344 ICE_CTX_STORE(ice_tlan_ctx, src_vsi, 10, 80),
1345 ICE_CTX_STORE(ice_tlan_ctx, tsyn_ena, 1, 90),
1346 ICE_CTX_STORE(ice_tlan_ctx, internal_usage_flag, 1, 91),
1347 ICE_CTX_STORE(ice_tlan_ctx, alt_vlan, 1, 92),
1348 ICE_CTX_STORE(ice_tlan_ctx, cpuid, 8, 93),
1349 ICE_CTX_STORE(ice_tlan_ctx, wb_mode, 1, 101),
1350 ICE_CTX_STORE(ice_tlan_ctx, tphrd_desc, 1, 102),
1351 ICE_CTX_STORE(ice_tlan_ctx, tphrd, 1, 103),
1352 ICE_CTX_STORE(ice_tlan_ctx, tphwr_desc, 1, 104),
1353 ICE_CTX_STORE(ice_tlan_ctx, cmpq_id, 9, 105),
1354 ICE_CTX_STORE(ice_tlan_ctx, qnum_in_func, 14, 114),
1355 ICE_CTX_STORE(ice_tlan_ctx, itr_notification_mode, 1, 128),
1356 ICE_CTX_STORE(ice_tlan_ctx, adjust_prof_id, 6, 129),
1357 ICE_CTX_STORE(ice_tlan_ctx, qlen, 13, 135),
1358 ICE_CTX_STORE(ice_tlan_ctx, quanta_prof_idx, 4, 148),
1359 ICE_CTX_STORE(ice_tlan_ctx, tso_ena, 1, 152),
1360 ICE_CTX_STORE(ice_tlan_ctx, tso_qnum, 11, 153),
1361 ICE_CTX_STORE(ice_tlan_ctx, legacy_int, 1, 164),
1362 ICE_CTX_STORE(ice_tlan_ctx, drop_ena, 1, 165),
1363 ICE_CTX_STORE(ice_tlan_ctx, cache_prof_idx, 2, 166),
1364 ICE_CTX_STORE(ice_tlan_ctx, pkt_shaper_prof_idx, 3, 168),
1365 ICE_CTX_STORE(ice_tlan_ctx, int_q_state, 122, 171),
1366 ICE_CTX_STORE(ice_tlan_ctx, gsc_ena, 1, 172),
1371 * ice_copy_tx_cmpltnq_ctx_to_hw
1372 * @hw: pointer to the hardware structure
1373 * @ice_tx_cmpltnq_ctx: pointer to the Tx completion queue context
1374 * @tx_cmpltnq_index: the index of the completion queue
1376 * Copies Tx completion queue context from dense structure to HW register space
1378 static enum ice_status
1379 ice_copy_tx_cmpltnq_ctx_to_hw(struct ice_hw *hw, u8 *ice_tx_cmpltnq_ctx,
1380 u32 tx_cmpltnq_index)
1384 if (!ice_tx_cmpltnq_ctx)
1385 return ICE_ERR_BAD_PTR;
1387 if (tx_cmpltnq_index > GLTCLAN_CQ_CNTX0_MAX_INDEX)
1388 return ICE_ERR_PARAM;
1390 /* Copy each dword separately to HW */
1391 for (i = 0; i < ICE_TX_CMPLTNQ_CTX_SIZE_DWORDS; i++) {
1392 wr32(hw, GLTCLAN_CQ_CNTX(i, tx_cmpltnq_index),
1393 *((u32 *)(ice_tx_cmpltnq_ctx + (i * sizeof(u32)))));
1395 ice_debug(hw, ICE_DBG_QCTX, "cmpltnqdata[%d]: %08X\n", i,
1396 *((u32 *)(ice_tx_cmpltnq_ctx + (i * sizeof(u32)))));
1402 /* LAN Tx Completion Queue Context */
1403 static const struct ice_ctx_ele ice_tx_cmpltnq_ctx_info[] = {
1404 /* Field Width LSB */
1405 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, base, 57, 0),
1406 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, q_len, 18, 64),
1407 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, generation, 1, 96),
1408 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, wrt_ptr, 22, 97),
1409 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, pf_num, 3, 128),
1410 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, vmvf_num, 10, 131),
1411 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, vmvf_type, 2, 141),
1412 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, tph_desc_wr, 1, 160),
1413 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, cpuid, 8, 161),
1414 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, cmpltn_cache, 512, 192),
1419 * ice_write_tx_cmpltnq_ctx
1420 * @hw: pointer to the hardware structure
1421 * @tx_cmpltnq_ctx: pointer to the completion queue context
1422 * @tx_cmpltnq_index: the index of the completion queue
1424 * Converts completion queue context from sparse to dense structure and then
1425 * writes it to HW register space
1428 ice_write_tx_cmpltnq_ctx(struct ice_hw *hw,
1429 struct ice_tx_cmpltnq_ctx *tx_cmpltnq_ctx,
1430 u32 tx_cmpltnq_index)
1432 u8 ctx_buf[ICE_TX_CMPLTNQ_CTX_SIZE_DWORDS * sizeof(u32)] = { 0 };
1434 ice_set_ctx(hw, (u8 *)tx_cmpltnq_ctx, ctx_buf, ice_tx_cmpltnq_ctx_info);
1435 return ice_copy_tx_cmpltnq_ctx_to_hw(hw, ctx_buf, tx_cmpltnq_index);
1439 * ice_clear_tx_cmpltnq_ctx
1440 * @hw: pointer to the hardware structure
1441 * @tx_cmpltnq_index: the index of the completion queue to clear
1443 * Clears Tx completion queue context in HW register space
1446 ice_clear_tx_cmpltnq_ctx(struct ice_hw *hw, u32 tx_cmpltnq_index)
1450 if (tx_cmpltnq_index > GLTCLAN_CQ_CNTX0_MAX_INDEX)
1451 return ICE_ERR_PARAM;
1453 /* Clear each dword register separately */
1454 for (i = 0; i < ICE_TX_CMPLTNQ_CTX_SIZE_DWORDS; i++)
1455 wr32(hw, GLTCLAN_CQ_CNTX(i, tx_cmpltnq_index), 0);
1461 * ice_copy_tx_drbell_q_ctx_to_hw
1462 * @hw: pointer to the hardware structure
1463 * @ice_tx_drbell_q_ctx: pointer to the doorbell queue context
1464 * @tx_drbell_q_index: the index of the doorbell queue
1466 * Copies doorbell queue context from dense structure to HW register space
1468 static enum ice_status
1469 ice_copy_tx_drbell_q_ctx_to_hw(struct ice_hw *hw, u8 *ice_tx_drbell_q_ctx,
1470 u32 tx_drbell_q_index)
1474 if (!ice_tx_drbell_q_ctx)
1475 return ICE_ERR_BAD_PTR;
1477 if (tx_drbell_q_index > QTX_COMM_DBLQ_DBELL_MAX_INDEX)
1478 return ICE_ERR_PARAM;
1480 /* Copy each dword separately to HW */
1481 for (i = 0; i < ICE_TX_DRBELL_Q_CTX_SIZE_DWORDS; i++) {
1482 wr32(hw, QTX_COMM_DBLQ_CNTX(i, tx_drbell_q_index),
1483 *((u32 *)(ice_tx_drbell_q_ctx + (i * sizeof(u32)))));
1485 ice_debug(hw, ICE_DBG_QCTX, "tx_drbell_qdata[%d]: %08X\n", i,
1486 *((u32 *)(ice_tx_drbell_q_ctx + (i * sizeof(u32)))));
1492 /* LAN Tx Doorbell Queue Context info */
1493 static const struct ice_ctx_ele ice_tx_drbell_q_ctx_info[] = {
1494 /* Field Width LSB */
1495 ICE_CTX_STORE(ice_tx_drbell_q_ctx, base, 57, 0),
1496 ICE_CTX_STORE(ice_tx_drbell_q_ctx, ring_len, 13, 64),
1497 ICE_CTX_STORE(ice_tx_drbell_q_ctx, pf_num, 3, 80),
1498 ICE_CTX_STORE(ice_tx_drbell_q_ctx, vf_num, 8, 84),
1499 ICE_CTX_STORE(ice_tx_drbell_q_ctx, vmvf_type, 2, 94),
1500 ICE_CTX_STORE(ice_tx_drbell_q_ctx, cpuid, 8, 96),
1501 ICE_CTX_STORE(ice_tx_drbell_q_ctx, tph_desc_rd, 1, 104),
1502 ICE_CTX_STORE(ice_tx_drbell_q_ctx, tph_desc_wr, 1, 108),
1503 ICE_CTX_STORE(ice_tx_drbell_q_ctx, db_q_en, 1, 112),
1504 ICE_CTX_STORE(ice_tx_drbell_q_ctx, rd_head, 13, 128),
1505 ICE_CTX_STORE(ice_tx_drbell_q_ctx, rd_tail, 13, 144),
1510 * ice_write_tx_drbell_q_ctx
1511 * @hw: pointer to the hardware structure
1512 * @tx_drbell_q_ctx: pointer to the doorbell queue context
1513 * @tx_drbell_q_index: the index of the doorbell queue
1515 * Converts doorbell queue context from sparse to dense structure and then
1516 * writes it to HW register space
1519 ice_write_tx_drbell_q_ctx(struct ice_hw *hw,
1520 struct ice_tx_drbell_q_ctx *tx_drbell_q_ctx,
1521 u32 tx_drbell_q_index)
1523 u8 ctx_buf[ICE_TX_DRBELL_Q_CTX_SIZE_DWORDS * sizeof(u32)] = { 0 };
1525 ice_set_ctx(hw, (u8 *)tx_drbell_q_ctx, ctx_buf,
1526 ice_tx_drbell_q_ctx_info);
1527 return ice_copy_tx_drbell_q_ctx_to_hw(hw, ctx_buf, tx_drbell_q_index);
1531 * ice_clear_tx_drbell_q_ctx
1532 * @hw: pointer to the hardware structure
1533 * @tx_drbell_q_index: the index of the doorbell queue to clear
1535 * Clears doorbell queue context in HW register space
1538 ice_clear_tx_drbell_q_ctx(struct ice_hw *hw, u32 tx_drbell_q_index)
1542 if (tx_drbell_q_index > QTX_COMM_DBLQ_DBELL_MAX_INDEX)
1543 return ICE_ERR_PARAM;
1545 /* Clear each dword register separately */
1546 for (i = 0; i < ICE_TX_DRBELL_Q_CTX_SIZE_DWORDS; i++)
1547 wr32(hw, QTX_COMM_DBLQ_CNTX(i, tx_drbell_q_index), 0);
1552 /* Sideband Queue command wrappers */
1555 * ice_get_sbq - returns the right control queue to use for sideband
1556 * @hw: pointer to the hardware structure
1558 static struct ice_ctl_q_info *ice_get_sbq(struct ice_hw *hw)
1560 if (!ice_is_generic_mac(hw))
1566 * ice_sbq_send_cmd - send Sideband Queue command to Sideband Queue
1567 * @hw: pointer to the HW struct
1568 * @desc: descriptor describing the command
1569 * @buf: buffer to use for indirect commands (NULL for direct commands)
1570 * @buf_size: size of buffer for indirect commands (0 for direct commands)
1571 * @cd: pointer to command details structure
1573 static enum ice_status
1574 ice_sbq_send_cmd(struct ice_hw *hw, struct ice_sbq_cmd_desc *desc,
1575 void *buf, u16 buf_size, struct ice_sq_cd *cd)
1577 return ice_sq_send_cmd(hw, ice_get_sbq(hw), (struct ice_aq_desc *)desc,
1582 * ice_sbq_send_cmd_nolock - send Sideband Queue command to Sideband Queue
1583 * but do not lock sq_lock
1584 * @hw: pointer to the HW struct
1585 * @desc: descriptor describing the command
1586 * @buf: buffer to use for indirect commands (NULL for direct commands)
1587 * @buf_size: size of buffer for indirect commands (0 for direct commands)
1588 * @cd: pointer to command details structure
1590 static enum ice_status
1591 ice_sbq_send_cmd_nolock(struct ice_hw *hw, struct ice_sbq_cmd_desc *desc,
1592 void *buf, u16 buf_size, struct ice_sq_cd *cd)
1594 return ice_sq_send_cmd_nolock(hw, ice_get_sbq(hw),
1595 (struct ice_aq_desc *)desc, buf,
1600 * ice_sbq_rw_reg_lp - Fill Sideband Queue command, with lock parameter
1601 * @hw: pointer to the HW struct
1602 * @in: message info to be filled in descriptor
1603 * @lock: true to lock the sq_lock (the usual case); false if the sq_lock has
1604 * already been locked at a higher level
1606 enum ice_status ice_sbq_rw_reg_lp(struct ice_hw *hw,
1607 struct ice_sbq_msg_input *in, bool lock)
1609 struct ice_sbq_cmd_desc desc = {0};
1610 struct ice_sbq_msg_req msg = {0};
1611 enum ice_status status;
1614 msg_len = sizeof(msg);
1616 msg.dest_dev = in->dest_dev;
1617 msg.opcode = in->opcode;
1618 msg.flags = ICE_SBQ_MSG_FLAGS;
1619 msg.sbe_fbe = ICE_SBQ_MSG_SBE_FBE;
1620 msg.msg_addr_low = CPU_TO_LE16(in->msg_addr_low);
1621 msg.msg_addr_high = CPU_TO_LE32(in->msg_addr_high);
1624 msg.data = CPU_TO_LE32(in->data);
1626 /* data read comes back in completion, so shorten the struct by
1629 msg_len -= sizeof(msg.data);
1631 desc.flags = CPU_TO_LE16(ICE_AQ_FLAG_RD);
1632 desc.opcode = CPU_TO_LE16(ice_sbq_opc_neigh_dev_req);
1633 desc.param0.cmd_len = CPU_TO_LE16(msg_len);
1635 status = ice_sbq_send_cmd(hw, &desc, &msg, msg_len, NULL);
1637 status = ice_sbq_send_cmd_nolock(hw, &desc, &msg, msg_len,
1639 if (!status && !in->opcode)
1640 in->data = LE32_TO_CPU
1641 (((struct ice_sbq_msg_cmpl *)&msg)->data);
1646 * ice_sbq_rw_reg - Fill Sideband Queue command
1647 * @hw: pointer to the HW struct
1648 * @in: message info to be filled in descriptor
1650 enum ice_status ice_sbq_rw_reg(struct ice_hw *hw, struct ice_sbq_msg_input *in)
1652 return ice_sbq_rw_reg_lp(hw, in, true);
1656 * ice_sbq_lock - Lock the sideband queue's sq_lock
1657 * @hw: pointer to the HW struct
1659 void ice_sbq_lock(struct ice_hw *hw)
1661 ice_acquire_lock(&ice_get_sbq(hw)->sq_lock);
1665 * ice_sbq_unlock - Unlock the sideband queue's sq_lock
1666 * @hw: pointer to the HW struct
1668 void ice_sbq_unlock(struct ice_hw *hw)
1670 ice_release_lock(&ice_get_sbq(hw)->sq_lock);
1673 /* FW Admin Queue command wrappers */
1676 * ice_should_retry_sq_send_cmd
1677 * @opcode: AQ opcode
1679 * Decide if we should retry the send command routine for the ATQ, depending
1682 static bool ice_should_retry_sq_send_cmd(u16 opcode)
1685 case ice_aqc_opc_get_link_topo:
1686 case ice_aqc_opc_lldp_stop:
1687 case ice_aqc_opc_lldp_start:
1688 case ice_aqc_opc_lldp_filter_ctrl:
1696 * ice_sq_send_cmd_retry - send command to Control Queue (ATQ)
1697 * @hw: pointer to the HW struct
1698 * @cq: pointer to the specific Control queue
1699 * @desc: prefilled descriptor describing the command
1700 * @buf: buffer to use for indirect commands (or NULL for direct commands)
1701 * @buf_size: size of buffer for indirect commands (or 0 for direct commands)
1702 * @cd: pointer to command details structure
1704 * Retry sending the FW Admin Queue command, multiple times, to the FW Admin
1705 * Queue if the EBUSY AQ error is returned.
1707 static enum ice_status
1708 ice_sq_send_cmd_retry(struct ice_hw *hw, struct ice_ctl_q_info *cq,
1709 struct ice_aq_desc *desc, void *buf, u16 buf_size,
1710 struct ice_sq_cd *cd)
1712 struct ice_aq_desc desc_cpy;
1713 enum ice_status status;
1714 bool is_cmd_for_retry;
1719 opcode = LE16_TO_CPU(desc->opcode);
1720 is_cmd_for_retry = ice_should_retry_sq_send_cmd(opcode);
1721 ice_memset(&desc_cpy, 0, sizeof(desc_cpy), ICE_NONDMA_MEM);
1723 if (is_cmd_for_retry) {
1725 buf_cpy = (u8 *)ice_malloc(hw, buf_size);
1727 return ICE_ERR_NO_MEMORY;
1730 ice_memcpy(&desc_cpy, desc, sizeof(desc_cpy),
1731 ICE_NONDMA_TO_NONDMA);
1735 status = ice_sq_send_cmd(hw, cq, desc, buf, buf_size, cd);
1737 if (!is_cmd_for_retry || status == ICE_SUCCESS ||
1738 hw->adminq.sq_last_status != ICE_AQ_RC_EBUSY)
1742 ice_memcpy(buf, buf_cpy, buf_size,
1743 ICE_NONDMA_TO_NONDMA);
1745 ice_memcpy(desc, &desc_cpy, sizeof(desc_cpy),
1746 ICE_NONDMA_TO_NONDMA);
1748 ice_msec_delay(ICE_SQ_SEND_DELAY_TIME_MS, false);
1750 } while (++idx < ICE_SQ_SEND_MAX_EXECUTE);
1753 ice_free(hw, buf_cpy);
1759 * ice_aq_send_cmd - send FW Admin Queue command to FW Admin Queue
1760 * @hw: pointer to the HW struct
1761 * @desc: descriptor describing the command
1762 * @buf: buffer to use for indirect commands (NULL for direct commands)
1763 * @buf_size: size of buffer for indirect commands (0 for direct commands)
1764 * @cd: pointer to command details structure
1766 * Helper function to send FW Admin Queue commands to the FW Admin Queue.
1769 ice_aq_send_cmd(struct ice_hw *hw, struct ice_aq_desc *desc, void *buf,
1770 u16 buf_size, struct ice_sq_cd *cd)
1772 if (hw->aq_send_cmd_fn) {
1773 enum ice_status status = ICE_ERR_NOT_READY;
1774 u16 retval = ICE_AQ_RC_OK;
1776 ice_acquire_lock(&hw->adminq.sq_lock);
1777 if (!hw->aq_send_cmd_fn(hw->aq_send_cmd_param, desc,
1779 retval = LE16_TO_CPU(desc->retval);
1780 /* strip off FW internal code */
1783 if (retval == ICE_AQ_RC_OK)
1784 status = ICE_SUCCESS;
1786 status = ICE_ERR_AQ_ERROR;
1789 hw->adminq.sq_last_status = (enum ice_aq_err)retval;
1790 ice_release_lock(&hw->adminq.sq_lock);
1794 return ice_sq_send_cmd_retry(hw, &hw->adminq, desc, buf, buf_size, cd);
1799 * @hw: pointer to the HW struct
1800 * @cd: pointer to command details structure or NULL
1802 * Get the firmware version (0x0001) from the admin queue commands
1804 enum ice_status ice_aq_get_fw_ver(struct ice_hw *hw, struct ice_sq_cd *cd)
1806 struct ice_aqc_get_ver *resp;
1807 struct ice_aq_desc desc;
1808 enum ice_status status;
1810 resp = &desc.params.get_ver;
1812 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_ver);
1814 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
1817 hw->fw_branch = resp->fw_branch;
1818 hw->fw_maj_ver = resp->fw_major;
1819 hw->fw_min_ver = resp->fw_minor;
1820 hw->fw_patch = resp->fw_patch;
1821 hw->fw_build = LE32_TO_CPU(resp->fw_build);
1822 hw->api_branch = resp->api_branch;
1823 hw->api_maj_ver = resp->api_major;
1824 hw->api_min_ver = resp->api_minor;
1825 hw->api_patch = resp->api_patch;
1832 * ice_aq_send_driver_ver
1833 * @hw: pointer to the HW struct
1834 * @dv: driver's major, minor version
1835 * @cd: pointer to command details structure or NULL
1837 * Send the driver version (0x0002) to the firmware
1840 ice_aq_send_driver_ver(struct ice_hw *hw, struct ice_driver_ver *dv,
1841 struct ice_sq_cd *cd)
1843 struct ice_aqc_driver_ver *cmd;
1844 struct ice_aq_desc desc;
1847 cmd = &desc.params.driver_ver;
1850 return ICE_ERR_PARAM;
1852 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_driver_ver);
1854 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
1855 cmd->major_ver = dv->major_ver;
1856 cmd->minor_ver = dv->minor_ver;
1857 cmd->build_ver = dv->build_ver;
1858 cmd->subbuild_ver = dv->subbuild_ver;
1861 while (len < sizeof(dv->driver_string) &&
1862 IS_ASCII(dv->driver_string[len]) && dv->driver_string[len])
1865 return ice_aq_send_cmd(hw, &desc, dv->driver_string, len, cd);
1870 * @hw: pointer to the HW struct
1871 * @unloading: is the driver unloading itself
1873 * Tell the Firmware that we're shutting down the AdminQ and whether
1874 * or not the driver is unloading as well (0x0003).
1876 enum ice_status ice_aq_q_shutdown(struct ice_hw *hw, bool unloading)
1878 struct ice_aqc_q_shutdown *cmd;
1879 struct ice_aq_desc desc;
1881 cmd = &desc.params.q_shutdown;
1883 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_q_shutdown);
1886 cmd->driver_unloading = ICE_AQC_DRIVER_UNLOADING;
1888 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
1893 * @hw: pointer to the HW struct
1895 * @access: access type
1896 * @sdp_number: resource number
1897 * @timeout: the maximum time in ms that the driver may hold the resource
1898 * @cd: pointer to command details structure or NULL
1900 * Requests common resource using the admin queue commands (0x0008).
1901 * When attempting to acquire the Global Config Lock, the driver can
1902 * learn of three states:
1903 * 1) ICE_SUCCESS - acquired lock, and can perform download package
1904 * 2) ICE_ERR_AQ_ERROR - did not get lock, driver should fail to load
1905 * 3) ICE_ERR_AQ_NO_WORK - did not get lock, but another driver has
1906 * successfully downloaded the package; the driver does
1907 * not have to download the package and can continue
1910 * Note that if the caller is in an acquire lock, perform action, release lock
1911 * phase of operation, it is possible that the FW may detect a timeout and issue
1912 * a CORER. In this case, the driver will receive a CORER interrupt and will
1913 * have to determine its cause. The calling thread that is handling this flow
1914 * will likely get an error propagated back to it indicating the Download
1915 * Package, Update Package or the Release Resource AQ commands timed out.
1917 static enum ice_status
1918 ice_aq_req_res(struct ice_hw *hw, enum ice_aq_res_ids res,
1919 enum ice_aq_res_access_type access, u8 sdp_number, u32 *timeout,
1920 struct ice_sq_cd *cd)
1922 struct ice_aqc_req_res *cmd_resp;
1923 struct ice_aq_desc desc;
1924 enum ice_status status;
1926 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
1928 cmd_resp = &desc.params.res_owner;
1930 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_req_res);
1932 cmd_resp->res_id = CPU_TO_LE16(res);
1933 cmd_resp->access_type = CPU_TO_LE16(access);
1934 cmd_resp->res_number = CPU_TO_LE32(sdp_number);
1935 cmd_resp->timeout = CPU_TO_LE32(*timeout);
1938 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
1940 /* The completion specifies the maximum time in ms that the driver
1941 * may hold the resource in the Timeout field.
1944 /* Global config lock response utilizes an additional status field.
1946 * If the Global config lock resource is held by some other driver, the
1947 * command completes with ICE_AQ_RES_GLBL_IN_PROG in the status field
1948 * and the timeout field indicates the maximum time the current owner
1949 * of the resource has to free it.
1951 if (res == ICE_GLOBAL_CFG_LOCK_RES_ID) {
1952 if (LE16_TO_CPU(cmd_resp->status) == ICE_AQ_RES_GLBL_SUCCESS) {
1953 *timeout = LE32_TO_CPU(cmd_resp->timeout);
1955 } else if (LE16_TO_CPU(cmd_resp->status) ==
1956 ICE_AQ_RES_GLBL_IN_PROG) {
1957 *timeout = LE32_TO_CPU(cmd_resp->timeout);
1958 return ICE_ERR_AQ_ERROR;
1959 } else if (LE16_TO_CPU(cmd_resp->status) ==
1960 ICE_AQ_RES_GLBL_DONE) {
1961 return ICE_ERR_AQ_NO_WORK;
1964 /* invalid FW response, force a timeout immediately */
1966 return ICE_ERR_AQ_ERROR;
1969 /* If the resource is held by some other driver, the command completes
1970 * with a busy return value and the timeout field indicates the maximum
1971 * time the current owner of the resource has to free it.
1973 if (!status || hw->adminq.sq_last_status == ICE_AQ_RC_EBUSY)
1974 *timeout = LE32_TO_CPU(cmd_resp->timeout);
1980 * ice_aq_release_res
1981 * @hw: pointer to the HW struct
1983 * @sdp_number: resource number
1984 * @cd: pointer to command details structure or NULL
1986 * release common resource using the admin queue commands (0x0009)
1988 static enum ice_status
1989 ice_aq_release_res(struct ice_hw *hw, enum ice_aq_res_ids res, u8 sdp_number,
1990 struct ice_sq_cd *cd)
1992 struct ice_aqc_req_res *cmd;
1993 struct ice_aq_desc desc;
1995 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
1997 cmd = &desc.params.res_owner;
1999 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_release_res);
2001 cmd->res_id = CPU_TO_LE16(res);
2002 cmd->res_number = CPU_TO_LE32(sdp_number);
2004 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
2009 * @hw: pointer to the HW structure
2011 * @access: access type (read or write)
2012 * @timeout: timeout in milliseconds
2014 * This function will attempt to acquire the ownership of a resource.
2017 ice_acquire_res(struct ice_hw *hw, enum ice_aq_res_ids res,
2018 enum ice_aq_res_access_type access, u32 timeout)
2020 #define ICE_RES_POLLING_DELAY_MS 10
2021 u32 delay = ICE_RES_POLLING_DELAY_MS;
2022 u32 time_left = timeout;
2023 enum ice_status status;
2025 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
2027 status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL);
2029 /* A return code of ICE_ERR_AQ_NO_WORK means that another driver has
2030 * previously acquired the resource and performed any necessary updates;
2031 * in this case the caller does not obtain the resource and has no
2032 * further work to do.
2034 if (status == ICE_ERR_AQ_NO_WORK)
2035 goto ice_acquire_res_exit;
2038 ice_debug(hw, ICE_DBG_RES, "resource %d acquire type %d failed.\n", res, access);
2040 /* If necessary, poll until the current lock owner timeouts */
2041 timeout = time_left;
2042 while (status && timeout && time_left) {
2043 ice_msec_delay(delay, true);
2044 timeout = (timeout > delay) ? timeout - delay : 0;
2045 status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL);
2047 if (status == ICE_ERR_AQ_NO_WORK)
2048 /* lock free, but no work to do */
2055 if (status && status != ICE_ERR_AQ_NO_WORK)
2056 ice_debug(hw, ICE_DBG_RES, "resource acquire timed out.\n");
2058 ice_acquire_res_exit:
2059 if (status == ICE_ERR_AQ_NO_WORK) {
2060 if (access == ICE_RES_WRITE)
2061 ice_debug(hw, ICE_DBG_RES, "resource indicates no work to do.\n");
2063 ice_debug(hw, ICE_DBG_RES, "Warning: ICE_ERR_AQ_NO_WORK not expected\n");
2070 * @hw: pointer to the HW structure
2073 * This function will release a resource using the proper Admin Command.
2075 void ice_release_res(struct ice_hw *hw, enum ice_aq_res_ids res)
2077 enum ice_status status;
2078 u32 total_delay = 0;
2080 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
2082 status = ice_aq_release_res(hw, res, 0, NULL);
2084 /* there are some rare cases when trying to release the resource
2085 * results in an admin queue timeout, so handle them correctly
2087 while ((status == ICE_ERR_AQ_TIMEOUT) &&
2088 (total_delay < hw->adminq.sq_cmd_timeout)) {
2089 ice_msec_delay(1, true);
2090 status = ice_aq_release_res(hw, res, 0, NULL);
2096 * ice_aq_alloc_free_res - command to allocate/free resources
2097 * @hw: pointer to the HW struct
2098 * @num_entries: number of resource entries in buffer
2099 * @buf: Indirect buffer to hold data parameters and response
2100 * @buf_size: size of buffer for indirect commands
2101 * @opc: pass in the command opcode
2102 * @cd: pointer to command details structure or NULL
2104 * Helper function to allocate/free resources using the admin queue commands
2107 ice_aq_alloc_free_res(struct ice_hw *hw, u16 num_entries,
2108 struct ice_aqc_alloc_free_res_elem *buf, u16 buf_size,
2109 enum ice_adminq_opc opc, struct ice_sq_cd *cd)
2111 struct ice_aqc_alloc_free_res_cmd *cmd;
2112 struct ice_aq_desc desc;
2114 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
2116 cmd = &desc.params.sw_res_ctrl;
2119 return ICE_ERR_PARAM;
2121 if (buf_size < FLEX_ARRAY_SIZE(buf, elem, num_entries))
2122 return ICE_ERR_PARAM;
2124 ice_fill_dflt_direct_cmd_desc(&desc, opc);
2126 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
2128 cmd->num_entries = CPU_TO_LE16(num_entries);
2130 return ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);
2134 * ice_alloc_hw_res - allocate resource
2135 * @hw: pointer to the HW struct
2136 * @type: type of resource
2137 * @num: number of resources to allocate
2138 * @btm: allocate from bottom
2139 * @res: pointer to array that will receive the resources
2142 ice_alloc_hw_res(struct ice_hw *hw, u16 type, u16 num, bool btm, u16 *res)
2144 struct ice_aqc_alloc_free_res_elem *buf;
2145 enum ice_status status;
2148 buf_len = ice_struct_size(buf, elem, num);
2149 buf = (struct ice_aqc_alloc_free_res_elem *)ice_malloc(hw, buf_len);
2151 return ICE_ERR_NO_MEMORY;
2153 /* Prepare buffer to allocate resource. */
2154 buf->num_elems = CPU_TO_LE16(num);
2155 buf->res_type = CPU_TO_LE16(type | ICE_AQC_RES_TYPE_FLAG_DEDICATED |
2156 ICE_AQC_RES_TYPE_FLAG_IGNORE_INDEX);
2158 buf->res_type |= CPU_TO_LE16(ICE_AQC_RES_TYPE_FLAG_SCAN_BOTTOM);
2160 status = ice_aq_alloc_free_res(hw, 1, buf, buf_len,
2161 ice_aqc_opc_alloc_res, NULL);
2163 goto ice_alloc_res_exit;
2165 ice_memcpy(res, buf->elem, sizeof(*buf->elem) * num,
2166 ICE_NONDMA_TO_NONDMA);
2174 * ice_free_hw_res - free allocated HW resource
2175 * @hw: pointer to the HW struct
2176 * @type: type of resource to free
2177 * @num: number of resources
2178 * @res: pointer to array that contains the resources to free
2180 enum ice_status ice_free_hw_res(struct ice_hw *hw, u16 type, u16 num, u16 *res)
2182 struct ice_aqc_alloc_free_res_elem *buf;
2183 enum ice_status status;
2186 buf_len = ice_struct_size(buf, elem, num);
2187 buf = (struct ice_aqc_alloc_free_res_elem *)ice_malloc(hw, buf_len);
2189 return ICE_ERR_NO_MEMORY;
2191 /* Prepare buffer to free resource. */
2192 buf->num_elems = CPU_TO_LE16(num);
2193 buf->res_type = CPU_TO_LE16(type);
2194 ice_memcpy(buf->elem, res, sizeof(*buf->elem) * num,
2195 ICE_NONDMA_TO_NONDMA);
2197 status = ice_aq_alloc_free_res(hw, num, buf, buf_len,
2198 ice_aqc_opc_free_res, NULL);
2200 ice_debug(hw, ICE_DBG_SW, "CQ CMD Buffer:\n");
2207 * ice_get_num_per_func - determine number of resources per PF
2208 * @hw: pointer to the HW structure
2209 * @max: value to be evenly split between each PF
2211 * Determine the number of valid functions by going through the bitmap returned
2212 * from parsing capabilities and use this to calculate the number of resources
2213 * per PF based on the max value passed in.
2215 static u32 ice_get_num_per_func(struct ice_hw *hw, u32 max)
2219 #define ICE_CAPS_VALID_FUNCS_M 0xFF
2220 funcs = ice_hweight8(hw->dev_caps.common_cap.valid_functions &
2221 ICE_CAPS_VALID_FUNCS_M);
2230 * ice_parse_common_caps - parse common device/function capabilities
2231 * @hw: pointer to the HW struct
2232 * @caps: pointer to common capabilities structure
2233 * @elem: the capability element to parse
2234 * @prefix: message prefix for tracing capabilities
2236 * Given a capability element, extract relevant details into the common
2237 * capability structure.
2239 * Returns: true if the capability matches one of the common capability ids,
2243 ice_parse_common_caps(struct ice_hw *hw, struct ice_hw_common_caps *caps,
2244 struct ice_aqc_list_caps_elem *elem, const char *prefix)
2246 u32 logical_id = LE32_TO_CPU(elem->logical_id);
2247 u32 phys_id = LE32_TO_CPU(elem->phys_id);
2248 u32 number = LE32_TO_CPU(elem->number);
2249 u16 cap = LE16_TO_CPU(elem->cap);
2253 case ICE_AQC_CAPS_VALID_FUNCTIONS:
2254 caps->valid_functions = number;
2255 ice_debug(hw, ICE_DBG_INIT, "%s: valid_functions (bitmap) = %d\n", prefix,
2256 caps->valid_functions);
2258 case ICE_AQC_CAPS_DCB:
2259 caps->dcb = (number == 1);
2260 caps->active_tc_bitmap = logical_id;
2261 caps->maxtc = phys_id;
2262 ice_debug(hw, ICE_DBG_INIT, "%s: dcb = %d\n", prefix, caps->dcb);
2263 ice_debug(hw, ICE_DBG_INIT, "%s: active_tc_bitmap = %d\n", prefix,
2264 caps->active_tc_bitmap);
2265 ice_debug(hw, ICE_DBG_INIT, "%s: maxtc = %d\n", prefix, caps->maxtc);
2267 case ICE_AQC_CAPS_RSS:
2268 caps->rss_table_size = number;
2269 caps->rss_table_entry_width = logical_id;
2270 ice_debug(hw, ICE_DBG_INIT, "%s: rss_table_size = %d\n", prefix,
2271 caps->rss_table_size);
2272 ice_debug(hw, ICE_DBG_INIT, "%s: rss_table_entry_width = %d\n", prefix,
2273 caps->rss_table_entry_width);
2275 case ICE_AQC_CAPS_RXQS:
2276 caps->num_rxq = number;
2277 caps->rxq_first_id = phys_id;
2278 ice_debug(hw, ICE_DBG_INIT, "%s: num_rxq = %d\n", prefix,
2280 ice_debug(hw, ICE_DBG_INIT, "%s: rxq_first_id = %d\n", prefix,
2281 caps->rxq_first_id);
2283 case ICE_AQC_CAPS_TXQS:
2284 caps->num_txq = number;
2285 caps->txq_first_id = phys_id;
2286 ice_debug(hw, ICE_DBG_INIT, "%s: num_txq = %d\n", prefix,
2288 ice_debug(hw, ICE_DBG_INIT, "%s: txq_first_id = %d\n", prefix,
2289 caps->txq_first_id);
2291 case ICE_AQC_CAPS_MSIX:
2292 caps->num_msix_vectors = number;
2293 caps->msix_vector_first_id = phys_id;
2294 ice_debug(hw, ICE_DBG_INIT, "%s: num_msix_vectors = %d\n", prefix,
2295 caps->num_msix_vectors);
2296 ice_debug(hw, ICE_DBG_INIT, "%s: msix_vector_first_id = %d\n", prefix,
2297 caps->msix_vector_first_id);
2299 case ICE_AQC_CAPS_NVM_MGMT:
2300 caps->sec_rev_disabled =
2301 (number & ICE_NVM_MGMT_SEC_REV_DISABLED) ?
2303 ice_debug(hw, ICE_DBG_INIT, "%s: sec_rev_disabled = %d\n", prefix,
2304 caps->sec_rev_disabled);
2305 caps->update_disabled =
2306 (number & ICE_NVM_MGMT_UPDATE_DISABLED) ?
2308 ice_debug(hw, ICE_DBG_INIT, "%s: update_disabled = %d\n", prefix,
2309 caps->update_disabled);
2310 caps->nvm_unified_update =
2311 (number & ICE_NVM_MGMT_UNIFIED_UPD_SUPPORT) ?
2313 ice_debug(hw, ICE_DBG_INIT, "%s: nvm_unified_update = %d\n", prefix,
2314 caps->nvm_unified_update);
2316 case ICE_AQC_CAPS_MAX_MTU:
2317 caps->max_mtu = number;
2318 ice_debug(hw, ICE_DBG_INIT, "%s: max_mtu = %d\n",
2319 prefix, caps->max_mtu);
2321 case ICE_AQC_CAPS_PCIE_RESET_AVOIDANCE:
2322 caps->pcie_reset_avoidance = (number > 0);
2323 ice_debug(hw, ICE_DBG_INIT,
2324 "%s: pcie_reset_avoidance = %d\n", prefix,
2325 caps->pcie_reset_avoidance);
2327 case ICE_AQC_CAPS_POST_UPDATE_RESET_RESTRICT:
2328 caps->reset_restrict_support = (number == 1);
2329 ice_debug(hw, ICE_DBG_INIT,
2330 "%s: reset_restrict_support = %d\n", prefix,
2331 caps->reset_restrict_support);
2333 case ICE_AQC_CAPS_EXT_TOPO_DEV_IMG0:
2334 case ICE_AQC_CAPS_EXT_TOPO_DEV_IMG1:
2335 case ICE_AQC_CAPS_EXT_TOPO_DEV_IMG2:
2336 case ICE_AQC_CAPS_EXT_TOPO_DEV_IMG3:
2338 u8 index = cap - ICE_AQC_CAPS_EXT_TOPO_DEV_IMG0;
2340 caps->ext_topo_dev_img_ver_high[index] = number;
2341 caps->ext_topo_dev_img_ver_low[index] = logical_id;
2342 caps->ext_topo_dev_img_part_num[index] =
2343 (phys_id & ICE_EXT_TOPO_DEV_IMG_PART_NUM_M) >>
2344 ICE_EXT_TOPO_DEV_IMG_PART_NUM_S;
2345 caps->ext_topo_dev_img_load_en[index] =
2346 (phys_id & ICE_EXT_TOPO_DEV_IMG_LOAD_EN) != 0;
2347 caps->ext_topo_dev_img_prog_en[index] =
2348 (phys_id & ICE_EXT_TOPO_DEV_IMG_PROG_EN) != 0;
2349 ice_debug(hw, ICE_DBG_INIT,
2350 "%s: ext_topo_dev_img_ver_high[%d] = %d\n",
2352 caps->ext_topo_dev_img_ver_high[index]);
2353 ice_debug(hw, ICE_DBG_INIT,
2354 "%s: ext_topo_dev_img_ver_low[%d] = %d\n",
2356 caps->ext_topo_dev_img_ver_low[index]);
2357 ice_debug(hw, ICE_DBG_INIT,
2358 "%s: ext_topo_dev_img_part_num[%d] = %d\n",
2360 caps->ext_topo_dev_img_part_num[index]);
2361 ice_debug(hw, ICE_DBG_INIT,
2362 "%s: ext_topo_dev_img_load_en[%d] = %d\n",
2364 caps->ext_topo_dev_img_load_en[index]);
2365 ice_debug(hw, ICE_DBG_INIT,
2366 "%s: ext_topo_dev_img_prog_en[%d] = %d\n",
2368 caps->ext_topo_dev_img_prog_en[index]);
2372 /* Not one of the recognized common capabilities */
2380 * ice_recalc_port_limited_caps - Recalculate port limited capabilities
2381 * @hw: pointer to the HW structure
2382 * @caps: pointer to capabilities structure to fix
2384 * Re-calculate the capabilities that are dependent on the number of physical
2385 * ports; i.e. some features are not supported or function differently on
2386 * devices with more than 4 ports.
2389 ice_recalc_port_limited_caps(struct ice_hw *hw, struct ice_hw_common_caps *caps)
2391 /* This assumes device capabilities are always scanned before function
2392 * capabilities during the initialization flow.
2394 if (hw->dev_caps.num_funcs > 4) {
2395 /* Max 4 TCs per port */
2397 ice_debug(hw, ICE_DBG_INIT, "reducing maxtc to %d (based on #ports)\n",
2403 * ice_parse_vsi_func_caps - Parse ICE_AQC_CAPS_VSI function caps
2404 * @hw: pointer to the HW struct
2405 * @func_p: pointer to function capabilities structure
2406 * @cap: pointer to the capability element to parse
2408 * Extract function capabilities for ICE_AQC_CAPS_VSI.
2411 ice_parse_vsi_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p,
2412 struct ice_aqc_list_caps_elem *cap)
2414 func_p->guar_num_vsi = ice_get_num_per_func(hw, ICE_MAX_VSI);
2415 ice_debug(hw, ICE_DBG_INIT, "func caps: guar_num_vsi (fw) = %d\n",
2416 LE32_TO_CPU(cap->number));
2417 ice_debug(hw, ICE_DBG_INIT, "func caps: guar_num_vsi = %d\n",
2418 func_p->guar_num_vsi);
2422 * ice_parse_1588_func_caps - Parse ICE_AQC_CAPS_1588 function caps
2423 * @hw: pointer to the HW struct
2424 * @func_p: pointer to function capabilities structure
2425 * @cap: pointer to the capability element to parse
2427 * Extract function capabilities for ICE_AQC_CAPS_1588.
2430 ice_parse_1588_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p,
2431 struct ice_aqc_list_caps_elem *cap)
2433 struct ice_ts_func_info *info = &func_p->ts_func_info;
2434 u32 number = LE32_TO_CPU(cap->number);
2436 info->ena = ((number & ICE_TS_FUNC_ENA_M) != 0);
2437 func_p->common_cap.ieee_1588 = info->ena;
2439 info->src_tmr_owned = ((number & ICE_TS_SRC_TMR_OWND_M) != 0);
2440 info->tmr_ena = ((number & ICE_TS_TMR_ENA_M) != 0);
2441 info->tmr_index_owned = ((number & ICE_TS_TMR_IDX_OWND_M) != 0);
2442 info->tmr_index_assoc = ((number & ICE_TS_TMR_IDX_ASSOC_M) != 0);
2444 info->clk_freq = (number & ICE_TS_CLK_FREQ_M) >> ICE_TS_CLK_FREQ_S;
2445 info->clk_src = ((number & ICE_TS_CLK_SRC_M) != 0);
2447 if (info->clk_freq < NUM_ICE_TIME_REF_FREQ) {
2448 info->time_ref = (enum ice_time_ref_freq)info->clk_freq;
2450 /* Unknown clock frequency, so assume a (probably incorrect)
2451 * default to avoid out-of-bounds look ups of frequency
2452 * related information.
2454 ice_debug(hw, ICE_DBG_INIT, "1588 func caps: unknown clock frequency %u\n",
2456 info->time_ref = ICE_TIME_REF_FREQ_25_000;
2459 ice_debug(hw, ICE_DBG_INIT, "func caps: ieee_1588 = %u\n",
2460 func_p->common_cap.ieee_1588);
2461 ice_debug(hw, ICE_DBG_INIT, "func caps: src_tmr_owned = %u\n",
2462 info->src_tmr_owned);
2463 ice_debug(hw, ICE_DBG_INIT, "func caps: tmr_ena = %u\n",
2465 ice_debug(hw, ICE_DBG_INIT, "func caps: tmr_index_owned = %u\n",
2466 info->tmr_index_owned);
2467 ice_debug(hw, ICE_DBG_INIT, "func caps: tmr_index_assoc = %u\n",
2468 info->tmr_index_assoc);
2469 ice_debug(hw, ICE_DBG_INIT, "func caps: clk_freq = %u\n",
2471 ice_debug(hw, ICE_DBG_INIT, "func caps: clk_src = %u\n",
2476 * ice_parse_fdir_func_caps - Parse ICE_AQC_CAPS_FD function caps
2477 * @hw: pointer to the HW struct
2478 * @func_p: pointer to function capabilities structure
2480 * Extract function capabilities for ICE_AQC_CAPS_FD.
2483 ice_parse_fdir_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p)
2487 if (hw->dcf_enabled)
2489 reg_val = rd32(hw, GLQF_FD_SIZE);
2490 val = (reg_val & GLQF_FD_SIZE_FD_GSIZE_M) >>
2491 GLQF_FD_SIZE_FD_GSIZE_S;
2492 func_p->fd_fltr_guar =
2493 ice_get_num_per_func(hw, val);
2494 val = (reg_val & GLQF_FD_SIZE_FD_BSIZE_M) >>
2495 GLQF_FD_SIZE_FD_BSIZE_S;
2496 func_p->fd_fltr_best_effort = val;
2498 ice_debug(hw, ICE_DBG_INIT, "func caps: fd_fltr_guar = %d\n",
2499 func_p->fd_fltr_guar);
2500 ice_debug(hw, ICE_DBG_INIT, "func caps: fd_fltr_best_effort = %d\n",
2501 func_p->fd_fltr_best_effort);
2505 * ice_parse_func_caps - Parse function capabilities
2506 * @hw: pointer to the HW struct
2507 * @func_p: pointer to function capabilities structure
2508 * @buf: buffer containing the function capability records
2509 * @cap_count: the number of capabilities
2511 * Helper function to parse function (0x000A) capabilities list. For
2512 * capabilities shared between device and function, this relies on
2513 * ice_parse_common_caps.
2515 * Loop through the list of provided capabilities and extract the relevant
2516 * data into the function capabilities structured.
2519 ice_parse_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p,
2520 void *buf, u32 cap_count)
2522 struct ice_aqc_list_caps_elem *cap_resp;
2525 cap_resp = (struct ice_aqc_list_caps_elem *)buf;
2527 ice_memset(func_p, 0, sizeof(*func_p), ICE_NONDMA_MEM);
2529 for (i = 0; i < cap_count; i++) {
2530 u16 cap = LE16_TO_CPU(cap_resp[i].cap);
2533 found = ice_parse_common_caps(hw, &func_p->common_cap,
2534 &cap_resp[i], "func caps");
2537 case ICE_AQC_CAPS_VSI:
2538 ice_parse_vsi_func_caps(hw, func_p, &cap_resp[i]);
2540 case ICE_AQC_CAPS_1588:
2541 ice_parse_1588_func_caps(hw, func_p, &cap_resp[i]);
2543 case ICE_AQC_CAPS_FD:
2544 ice_parse_fdir_func_caps(hw, func_p);
2547 /* Don't list common capabilities as unknown */
2549 ice_debug(hw, ICE_DBG_INIT, "func caps: unknown capability[%d]: 0x%x\n",
2555 ice_recalc_port_limited_caps(hw, &func_p->common_cap);
2559 * ice_func_id_to_logical_id - map from function id to logical pf id
2560 * @active_function_bitmap: active function bitmap
2561 * @pf_id: function number of device
2563 static int ice_func_id_to_logical_id(u32 active_function_bitmap, u8 pf_id)
2568 for (i = 0; i < pf_id; i++)
2569 if (active_function_bitmap & BIT(i))
2576 * ice_parse_valid_functions_cap - Parse ICE_AQC_CAPS_VALID_FUNCTIONS caps
2577 * @hw: pointer to the HW struct
2578 * @dev_p: pointer to device capabilities structure
2579 * @cap: capability element to parse
2581 * Parse ICE_AQC_CAPS_VALID_FUNCTIONS for device capabilities.
2584 ice_parse_valid_functions_cap(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p,
2585 struct ice_aqc_list_caps_elem *cap)
2587 u32 number = LE32_TO_CPU(cap->number);
2589 dev_p->num_funcs = ice_hweight32(number);
2590 ice_debug(hw, ICE_DBG_INIT, "dev caps: num_funcs = %d\n",
2593 hw->logical_pf_id = ice_func_id_to_logical_id(number, hw->pf_id);
2597 * ice_parse_vsi_dev_caps - Parse ICE_AQC_CAPS_VSI device caps
2598 * @hw: pointer to the HW struct
2599 * @dev_p: pointer to device capabilities structure
2600 * @cap: capability element to parse
2602 * Parse ICE_AQC_CAPS_VSI for device capabilities.
2605 ice_parse_vsi_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p,
2606 struct ice_aqc_list_caps_elem *cap)
2608 u32 number = LE32_TO_CPU(cap->number);
2610 dev_p->num_vsi_allocd_to_host = number;
2611 ice_debug(hw, ICE_DBG_INIT, "dev caps: num_vsi_allocd_to_host = %d\n",
2612 dev_p->num_vsi_allocd_to_host);
2616 * ice_parse_1588_dev_caps - Parse ICE_AQC_CAPS_1588 device caps
2617 * @hw: pointer to the HW struct
2618 * @dev_p: pointer to device capabilities structure
2619 * @cap: capability element to parse
2621 * Parse ICE_AQC_CAPS_1588 for device capabilities.
2624 ice_parse_1588_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p,
2625 struct ice_aqc_list_caps_elem *cap)
2627 struct ice_ts_dev_info *info = &dev_p->ts_dev_info;
2628 u32 logical_id = LE32_TO_CPU(cap->logical_id);
2629 u32 phys_id = LE32_TO_CPU(cap->phys_id);
2630 u32 number = LE32_TO_CPU(cap->number);
2632 info->ena = ((number & ICE_TS_DEV_ENA_M) != 0);
2633 dev_p->common_cap.ieee_1588 = info->ena;
2635 info->tmr0_owner = number & ICE_TS_TMR0_OWNR_M;
2636 info->tmr0_owned = ((number & ICE_TS_TMR0_OWND_M) != 0);
2637 info->tmr0_ena = ((number & ICE_TS_TMR0_ENA_M) != 0);
2639 info->tmr1_owner = (number & ICE_TS_TMR1_OWNR_M) >> ICE_TS_TMR1_OWNR_S;
2640 info->tmr1_owned = ((number & ICE_TS_TMR1_OWND_M) != 0);
2641 info->tmr1_ena = ((number & ICE_TS_TMR1_ENA_M) != 0);
2643 info->ena_ports = logical_id;
2644 info->tmr_own_map = phys_id;
2646 ice_debug(hw, ICE_DBG_INIT, "dev caps: ieee_1588 = %u\n",
2647 dev_p->common_cap.ieee_1588);
2648 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr0_owner = %u\n",
2650 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr0_owned = %u\n",
2652 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr0_ena = %u\n",
2654 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr1_owner = %u\n",
2656 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr1_owned = %u\n",
2658 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr1_ena = %u\n",
2660 ice_debug(hw, ICE_DBG_INIT, "dev caps: ieee_1588 ena_ports = %u\n",
2662 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr_own_map = %u\n",
2667 * ice_parse_fdir_dev_caps - Parse ICE_AQC_CAPS_FD device caps
2668 * @hw: pointer to the HW struct
2669 * @dev_p: pointer to device capabilities structure
2670 * @cap: capability element to parse
2672 * Parse ICE_AQC_CAPS_FD for device capabilities.
2675 ice_parse_fdir_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p,
2676 struct ice_aqc_list_caps_elem *cap)
2678 u32 number = LE32_TO_CPU(cap->number);
2680 dev_p->num_flow_director_fltr = number;
2681 ice_debug(hw, ICE_DBG_INIT, "dev caps: num_flow_director_fltr = %d\n",
2682 dev_p->num_flow_director_fltr);
2686 * ice_parse_dev_caps - Parse device capabilities
2687 * @hw: pointer to the HW struct
2688 * @dev_p: pointer to device capabilities structure
2689 * @buf: buffer containing the device capability records
2690 * @cap_count: the number of capabilities
2692 * Helper device to parse device (0x000B) capabilities list. For
2693 * capabilities shared between device and function, this relies on
2694 * ice_parse_common_caps.
2696 * Loop through the list of provided capabilities and extract the relevant
2697 * data into the device capabilities structured.
2700 ice_parse_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p,
2701 void *buf, u32 cap_count)
2703 struct ice_aqc_list_caps_elem *cap_resp;
2706 cap_resp = (struct ice_aqc_list_caps_elem *)buf;
2708 ice_memset(dev_p, 0, sizeof(*dev_p), ICE_NONDMA_MEM);
2710 for (i = 0; i < cap_count; i++) {
2711 u16 cap = LE16_TO_CPU(cap_resp[i].cap);
2714 found = ice_parse_common_caps(hw, &dev_p->common_cap,
2715 &cap_resp[i], "dev caps");
2718 case ICE_AQC_CAPS_VALID_FUNCTIONS:
2719 ice_parse_valid_functions_cap(hw, dev_p, &cap_resp[i]);
2721 case ICE_AQC_CAPS_VSI:
2722 ice_parse_vsi_dev_caps(hw, dev_p, &cap_resp[i]);
2724 case ICE_AQC_CAPS_1588:
2725 ice_parse_1588_dev_caps(hw, dev_p, &cap_resp[i]);
2727 case ICE_AQC_CAPS_FD:
2728 ice_parse_fdir_dev_caps(hw, dev_p, &cap_resp[i]);
2731 /* Don't list common capabilities as unknown */
2733 ice_debug(hw, ICE_DBG_INIT, "dev caps: unknown capability[%d]: 0x%x\n",
2739 ice_recalc_port_limited_caps(hw, &dev_p->common_cap);
2743 * ice_aq_list_caps - query function/device capabilities
2744 * @hw: pointer to the HW struct
2745 * @buf: a buffer to hold the capabilities
2746 * @buf_size: size of the buffer
2747 * @cap_count: if not NULL, set to the number of capabilities reported
2748 * @opc: capabilities type to discover, device or function
2749 * @cd: pointer to command details structure or NULL
2751 * Get the function (0x000A) or device (0x000B) capabilities description from
2752 * firmware and store it in the buffer.
2754 * If the cap_count pointer is not NULL, then it is set to the number of
2755 * capabilities firmware will report. Note that if the buffer size is too
2756 * small, it is possible the command will return ICE_AQ_ERR_ENOMEM. The
2757 * cap_count will still be updated in this case. It is recommended that the
2758 * buffer size be set to ICE_AQ_MAX_BUF_LEN (the largest possible buffer that
2759 * firmware could return) to avoid this.
2761 static enum ice_status
2762 ice_aq_list_caps(struct ice_hw *hw, void *buf, u16 buf_size, u32 *cap_count,
2763 enum ice_adminq_opc opc, struct ice_sq_cd *cd)
2765 struct ice_aqc_list_caps *cmd;
2766 struct ice_aq_desc desc;
2767 enum ice_status status;
2769 cmd = &desc.params.get_cap;
2771 if (opc != ice_aqc_opc_list_func_caps &&
2772 opc != ice_aqc_opc_list_dev_caps)
2773 return ICE_ERR_PARAM;
2775 ice_fill_dflt_direct_cmd_desc(&desc, opc);
2776 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);
2779 *cap_count = LE32_TO_CPU(cmd->count);
2785 * ice_discover_dev_caps - Read and extract device capabilities
2786 * @hw: pointer to the hardware structure
2787 * @dev_caps: pointer to device capabilities structure
2789 * Read the device capabilities and extract them into the dev_caps structure
2792 static enum ice_status
2793 ice_discover_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_caps)
2795 enum ice_status status;
2799 cbuf = ice_malloc(hw, ICE_AQ_MAX_BUF_LEN);
2801 return ICE_ERR_NO_MEMORY;
2803 /* Although the driver doesn't know the number of capabilities the
2804 * device will return, we can simply send a 4KB buffer, the maximum
2805 * possible size that firmware can return.
2807 cap_count = ICE_AQ_MAX_BUF_LEN / sizeof(struct ice_aqc_list_caps_elem);
2809 status = ice_aq_list_caps(hw, cbuf, ICE_AQ_MAX_BUF_LEN, &cap_count,
2810 ice_aqc_opc_list_dev_caps, NULL);
2812 ice_parse_dev_caps(hw, dev_caps, cbuf, cap_count);
2819 * ice_discover_func_caps - Read and extract function capabilities
2820 * @hw: pointer to the hardware structure
2821 * @func_caps: pointer to function capabilities structure
2823 * Read the function capabilities and extract them into the func_caps structure
2826 static enum ice_status
2827 ice_discover_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_caps)
2829 enum ice_status status;
2833 cbuf = ice_malloc(hw, ICE_AQ_MAX_BUF_LEN);
2835 return ICE_ERR_NO_MEMORY;
2837 /* Although the driver doesn't know the number of capabilities the
2838 * device will return, we can simply send a 4KB buffer, the maximum
2839 * possible size that firmware can return.
2841 cap_count = ICE_AQ_MAX_BUF_LEN / sizeof(struct ice_aqc_list_caps_elem);
2843 status = ice_aq_list_caps(hw, cbuf, ICE_AQ_MAX_BUF_LEN, &cap_count,
2844 ice_aqc_opc_list_func_caps, NULL);
2846 ice_parse_func_caps(hw, func_caps, cbuf, cap_count);
2853 * ice_set_safe_mode_caps - Override dev/func capabilities when in safe mode
2854 * @hw: pointer to the hardware structure
2856 void ice_set_safe_mode_caps(struct ice_hw *hw)
2858 struct ice_hw_func_caps *func_caps = &hw->func_caps;
2859 struct ice_hw_dev_caps *dev_caps = &hw->dev_caps;
2860 struct ice_hw_common_caps cached_caps;
2863 /* cache some func_caps values that should be restored after memset */
2864 cached_caps = func_caps->common_cap;
2866 /* unset func capabilities */
2867 memset(func_caps, 0, sizeof(*func_caps));
2869 #define ICE_RESTORE_FUNC_CAP(name) \
2870 func_caps->common_cap.name = cached_caps.name
2872 /* restore cached values */
2873 ICE_RESTORE_FUNC_CAP(valid_functions);
2874 ICE_RESTORE_FUNC_CAP(txq_first_id);
2875 ICE_RESTORE_FUNC_CAP(rxq_first_id);
2876 ICE_RESTORE_FUNC_CAP(msix_vector_first_id);
2877 ICE_RESTORE_FUNC_CAP(max_mtu);
2878 ICE_RESTORE_FUNC_CAP(nvm_unified_update);
2880 /* one Tx and one Rx queue in safe mode */
2881 func_caps->common_cap.num_rxq = 1;
2882 func_caps->common_cap.num_txq = 1;
2884 /* two MSIX vectors, one for traffic and one for misc causes */
2885 func_caps->common_cap.num_msix_vectors = 2;
2886 func_caps->guar_num_vsi = 1;
2888 /* cache some dev_caps values that should be restored after memset */
2889 cached_caps = dev_caps->common_cap;
2890 num_funcs = dev_caps->num_funcs;
2892 /* unset dev capabilities */
2893 memset(dev_caps, 0, sizeof(*dev_caps));
2895 #define ICE_RESTORE_DEV_CAP(name) \
2896 dev_caps->common_cap.name = cached_caps.name
2898 /* restore cached values */
2899 ICE_RESTORE_DEV_CAP(valid_functions);
2900 ICE_RESTORE_DEV_CAP(txq_first_id);
2901 ICE_RESTORE_DEV_CAP(rxq_first_id);
2902 ICE_RESTORE_DEV_CAP(msix_vector_first_id);
2903 ICE_RESTORE_DEV_CAP(max_mtu);
2904 ICE_RESTORE_DEV_CAP(nvm_unified_update);
2905 dev_caps->num_funcs = num_funcs;
2907 /* one Tx and one Rx queue per function in safe mode */
2908 dev_caps->common_cap.num_rxq = num_funcs;
2909 dev_caps->common_cap.num_txq = num_funcs;
2911 /* two MSIX vectors per function */
2912 dev_caps->common_cap.num_msix_vectors = 2 * num_funcs;
2916 * ice_get_caps - get info about the HW
2917 * @hw: pointer to the hardware structure
2919 enum ice_status ice_get_caps(struct ice_hw *hw)
2921 enum ice_status status;
2923 status = ice_discover_dev_caps(hw, &hw->dev_caps);
2927 return ice_discover_func_caps(hw, &hw->func_caps);
2931 * ice_aq_manage_mac_write - manage MAC address write command
2932 * @hw: pointer to the HW struct
2933 * @mac_addr: MAC address to be written as LAA/LAA+WoL/Port address
2934 * @flags: flags to control write behavior
2935 * @cd: pointer to command details structure or NULL
2937 * This function is used to write MAC address to the NVM (0x0108).
2940 ice_aq_manage_mac_write(struct ice_hw *hw, const u8 *mac_addr, u8 flags,
2941 struct ice_sq_cd *cd)
2943 struct ice_aqc_manage_mac_write *cmd;
2944 struct ice_aq_desc desc;
2946 cmd = &desc.params.mac_write;
2947 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_write);
2950 ice_memcpy(cmd->mac_addr, mac_addr, ETH_ALEN, ICE_NONDMA_TO_NONDMA);
2952 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
2956 * ice_aq_clear_pxe_mode
2957 * @hw: pointer to the HW struct
2959 * Tell the firmware that the driver is taking over from PXE (0x0110).
2961 static enum ice_status ice_aq_clear_pxe_mode(struct ice_hw *hw)
2963 struct ice_aq_desc desc;
2965 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pxe_mode);
2966 desc.params.clear_pxe.rx_cnt = ICE_AQC_CLEAR_PXE_RX_CNT;
2968 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
2972 * ice_clear_pxe_mode - clear pxe operations mode
2973 * @hw: pointer to the HW struct
2975 * Make sure all PXE mode settings are cleared, including things
2976 * like descriptor fetch/write-back mode.
2978 void ice_clear_pxe_mode(struct ice_hw *hw)
2980 if (ice_check_sq_alive(hw, &hw->adminq))
2981 ice_aq_clear_pxe_mode(hw);
2985 * ice_aq_set_port_params - set physical port parameters.
2986 * @pi: pointer to the port info struct
2987 * @bad_frame_vsi: defines the VSI to which bad frames are forwarded
2988 * @save_bad_pac: if set packets with errors are forwarded to the bad frames VSI
2989 * @pad_short_pac: if set transmit packets smaller than 60 bytes are padded
2990 * @double_vlan: if set double VLAN is enabled
2991 * @cd: pointer to command details structure or NULL
2993 * Set Physical port parameters (0x0203)
2996 ice_aq_set_port_params(struct ice_port_info *pi, u16 bad_frame_vsi,
2997 bool save_bad_pac, bool pad_short_pac, bool double_vlan,
2998 struct ice_sq_cd *cd)
3001 struct ice_aqc_set_port_params *cmd;
3002 struct ice_hw *hw = pi->hw;
3003 struct ice_aq_desc desc;
3006 cmd = &desc.params.set_port_params;
3008 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_port_params);
3009 cmd->bad_frame_vsi = CPU_TO_LE16(bad_frame_vsi);
3011 cmd_flags |= ICE_AQC_SET_P_PARAMS_SAVE_BAD_PACKETS;
3013 cmd_flags |= ICE_AQC_SET_P_PARAMS_PAD_SHORT_PACKETS;
3015 cmd_flags |= ICE_AQC_SET_P_PARAMS_DOUBLE_VLAN_ENA;
3016 cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
3018 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
3022 * ice_is_100m_speed_supported
3023 * @hw: pointer to the HW struct
3025 * returns true if 100M speeds are supported by the device,
3028 bool ice_is_100m_speed_supported(struct ice_hw *hw)
3030 switch (hw->device_id) {
3031 case ICE_DEV_ID_E822C_10G_BASE_T:
3032 case ICE_DEV_ID_E822C_SGMII:
3033 case ICE_DEV_ID_E822L_10G_BASE_T:
3034 case ICE_DEV_ID_E822L_SGMII:
3035 case ICE_DEV_ID_E823L_10G_BASE_T:
3036 case ICE_DEV_ID_E823L_1GBE:
3044 * ice_get_link_speed_based_on_phy_type - returns link speed
3045 * @phy_type_low: lower part of phy_type
3046 * @phy_type_high: higher part of phy_type
3048 * This helper function will convert an entry in PHY type structure
3049 * [phy_type_low, phy_type_high] to its corresponding link speed.
3050 * Note: In the structure of [phy_type_low, phy_type_high], there should
3051 * be one bit set, as this function will convert one PHY type to its
3053 * If no bit gets set, ICE_LINK_SPEED_UNKNOWN will be returned
3054 * If more than one bit gets set, ICE_LINK_SPEED_UNKNOWN will be returned
3057 ice_get_link_speed_based_on_phy_type(u64 phy_type_low, u64 phy_type_high)
3059 u16 speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN;
3060 u16 speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN;
3062 switch (phy_type_low) {
3063 case ICE_PHY_TYPE_LOW_100BASE_TX:
3064 case ICE_PHY_TYPE_LOW_100M_SGMII:
3065 speed_phy_type_low = ICE_AQ_LINK_SPEED_100MB;
3067 case ICE_PHY_TYPE_LOW_1000BASE_T:
3068 case ICE_PHY_TYPE_LOW_1000BASE_SX:
3069 case ICE_PHY_TYPE_LOW_1000BASE_LX:
3070 case ICE_PHY_TYPE_LOW_1000BASE_KX:
3071 case ICE_PHY_TYPE_LOW_1G_SGMII:
3072 speed_phy_type_low = ICE_AQ_LINK_SPEED_1000MB;
3074 case ICE_PHY_TYPE_LOW_2500BASE_T:
3075 case ICE_PHY_TYPE_LOW_2500BASE_X:
3076 case ICE_PHY_TYPE_LOW_2500BASE_KX:
3077 speed_phy_type_low = ICE_AQ_LINK_SPEED_2500MB;
3079 case ICE_PHY_TYPE_LOW_5GBASE_T:
3080 case ICE_PHY_TYPE_LOW_5GBASE_KR:
3081 speed_phy_type_low = ICE_AQ_LINK_SPEED_5GB;
3083 case ICE_PHY_TYPE_LOW_10GBASE_T:
3084 case ICE_PHY_TYPE_LOW_10G_SFI_DA:
3085 case ICE_PHY_TYPE_LOW_10GBASE_SR:
3086 case ICE_PHY_TYPE_LOW_10GBASE_LR:
3087 case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1:
3088 case ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC:
3089 case ICE_PHY_TYPE_LOW_10G_SFI_C2C:
3090 speed_phy_type_low = ICE_AQ_LINK_SPEED_10GB;
3092 case ICE_PHY_TYPE_LOW_25GBASE_T:
3093 case ICE_PHY_TYPE_LOW_25GBASE_CR:
3094 case ICE_PHY_TYPE_LOW_25GBASE_CR_S:
3095 case ICE_PHY_TYPE_LOW_25GBASE_CR1:
3096 case ICE_PHY_TYPE_LOW_25GBASE_SR:
3097 case ICE_PHY_TYPE_LOW_25GBASE_LR:
3098 case ICE_PHY_TYPE_LOW_25GBASE_KR:
3099 case ICE_PHY_TYPE_LOW_25GBASE_KR_S:
3100 case ICE_PHY_TYPE_LOW_25GBASE_KR1:
3101 case ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC:
3102 case ICE_PHY_TYPE_LOW_25G_AUI_C2C:
3103 speed_phy_type_low = ICE_AQ_LINK_SPEED_25GB;
3105 case ICE_PHY_TYPE_LOW_40GBASE_CR4:
3106 case ICE_PHY_TYPE_LOW_40GBASE_SR4:
3107 case ICE_PHY_TYPE_LOW_40GBASE_LR4:
3108 case ICE_PHY_TYPE_LOW_40GBASE_KR4:
3109 case ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC:
3110 case ICE_PHY_TYPE_LOW_40G_XLAUI:
3111 speed_phy_type_low = ICE_AQ_LINK_SPEED_40GB;
3113 case ICE_PHY_TYPE_LOW_50GBASE_CR2:
3114 case ICE_PHY_TYPE_LOW_50GBASE_SR2:
3115 case ICE_PHY_TYPE_LOW_50GBASE_LR2:
3116 case ICE_PHY_TYPE_LOW_50GBASE_KR2:
3117 case ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC:
3118 case ICE_PHY_TYPE_LOW_50G_LAUI2:
3119 case ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC:
3120 case ICE_PHY_TYPE_LOW_50G_AUI2:
3121 case ICE_PHY_TYPE_LOW_50GBASE_CP:
3122 case ICE_PHY_TYPE_LOW_50GBASE_SR:
3123 case ICE_PHY_TYPE_LOW_50GBASE_FR:
3124 case ICE_PHY_TYPE_LOW_50GBASE_LR:
3125 case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4:
3126 case ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC:
3127 case ICE_PHY_TYPE_LOW_50G_AUI1:
3128 speed_phy_type_low = ICE_AQ_LINK_SPEED_50GB;
3130 case ICE_PHY_TYPE_LOW_100GBASE_CR4:
3131 case ICE_PHY_TYPE_LOW_100GBASE_SR4:
3132 case ICE_PHY_TYPE_LOW_100GBASE_LR4:
3133 case ICE_PHY_TYPE_LOW_100GBASE_KR4:
3134 case ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC:
3135 case ICE_PHY_TYPE_LOW_100G_CAUI4:
3136 case ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC:
3137 case ICE_PHY_TYPE_LOW_100G_AUI4:
3138 case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4:
3139 case ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4:
3140 case ICE_PHY_TYPE_LOW_100GBASE_CP2:
3141 case ICE_PHY_TYPE_LOW_100GBASE_SR2:
3142 case ICE_PHY_TYPE_LOW_100GBASE_DR:
3143 speed_phy_type_low = ICE_AQ_LINK_SPEED_100GB;
3146 speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN;
3150 switch (phy_type_high) {
3151 case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4:
3152 case ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC:
3153 case ICE_PHY_TYPE_HIGH_100G_CAUI2:
3154 case ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC:
3155 case ICE_PHY_TYPE_HIGH_100G_AUI2:
3156 speed_phy_type_high = ICE_AQ_LINK_SPEED_100GB;
3159 speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN;
3163 if (speed_phy_type_low == ICE_AQ_LINK_SPEED_UNKNOWN &&
3164 speed_phy_type_high == ICE_AQ_LINK_SPEED_UNKNOWN)
3165 return ICE_AQ_LINK_SPEED_UNKNOWN;
3166 else if (speed_phy_type_low != ICE_AQ_LINK_SPEED_UNKNOWN &&
3167 speed_phy_type_high != ICE_AQ_LINK_SPEED_UNKNOWN)
3168 return ICE_AQ_LINK_SPEED_UNKNOWN;
3169 else if (speed_phy_type_low != ICE_AQ_LINK_SPEED_UNKNOWN &&
3170 speed_phy_type_high == ICE_AQ_LINK_SPEED_UNKNOWN)
3171 return speed_phy_type_low;
3173 return speed_phy_type_high;
3177 * ice_update_phy_type
3178 * @phy_type_low: pointer to the lower part of phy_type
3179 * @phy_type_high: pointer to the higher part of phy_type
3180 * @link_speeds_bitmap: targeted link speeds bitmap
3182 * Note: For the link_speeds_bitmap structure, you can check it at
3183 * [ice_aqc_get_link_status->link_speed]. Caller can pass in
3184 * link_speeds_bitmap include multiple speeds.
3186 * Each entry in this [phy_type_low, phy_type_high] structure will
3187 * present a certain link speed. This helper function will turn on bits
3188 * in [phy_type_low, phy_type_high] structure based on the value of
3189 * link_speeds_bitmap input parameter.
3192 ice_update_phy_type(u64 *phy_type_low, u64 *phy_type_high,
3193 u16 link_speeds_bitmap)
3200 /* We first check with low part of phy_type */
3201 for (index = 0; index <= ICE_PHY_TYPE_LOW_MAX_INDEX; index++) {
3202 pt_low = BIT_ULL(index);
3203 speed = ice_get_link_speed_based_on_phy_type(pt_low, 0);
3205 if (link_speeds_bitmap & speed)
3206 *phy_type_low |= BIT_ULL(index);
3209 /* We then check with high part of phy_type */
3210 for (index = 0; index <= ICE_PHY_TYPE_HIGH_MAX_INDEX; index++) {
3211 pt_high = BIT_ULL(index);
3212 speed = ice_get_link_speed_based_on_phy_type(0, pt_high);
3214 if (link_speeds_bitmap & speed)
3215 *phy_type_high |= BIT_ULL(index);
3220 * ice_aq_set_phy_cfg
3221 * @hw: pointer to the HW struct
3222 * @pi: port info structure of the interested logical port
3223 * @cfg: structure with PHY configuration data to be set
3224 * @cd: pointer to command details structure or NULL
3226 * Set the various PHY configuration parameters supported on the Port.
3227 * One or more of the Set PHY config parameters may be ignored in an MFP
3228 * mode as the PF may not have the privilege to set some of the PHY Config
3229 * parameters. This status will be indicated by the command response (0x0601).
3232 ice_aq_set_phy_cfg(struct ice_hw *hw, struct ice_port_info *pi,
3233 struct ice_aqc_set_phy_cfg_data *cfg, struct ice_sq_cd *cd)
3235 struct ice_aq_desc desc;
3236 enum ice_status status;
3239 return ICE_ERR_PARAM;
3241 /* Ensure that only valid bits of cfg->caps can be turned on. */
3242 if (cfg->caps & ~ICE_AQ_PHY_ENA_VALID_MASK) {
3243 ice_debug(hw, ICE_DBG_PHY, "Invalid bit is set in ice_aqc_set_phy_cfg_data->caps : 0x%x\n",
3246 cfg->caps &= ICE_AQ_PHY_ENA_VALID_MASK;
3249 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_phy_cfg);
3250 desc.params.set_phy.lport_num = pi->lport;
3251 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
3253 ice_debug(hw, ICE_DBG_LINK, "set phy cfg\n");
3254 ice_debug(hw, ICE_DBG_LINK, " phy_type_low = 0x%llx\n",
3255 (unsigned long long)LE64_TO_CPU(cfg->phy_type_low));
3256 ice_debug(hw, ICE_DBG_LINK, " phy_type_high = 0x%llx\n",
3257 (unsigned long long)LE64_TO_CPU(cfg->phy_type_high));
3258 ice_debug(hw, ICE_DBG_LINK, " caps = 0x%x\n", cfg->caps);
3259 ice_debug(hw, ICE_DBG_LINK, " low_power_ctrl_an = 0x%x\n",
3260 cfg->low_power_ctrl_an);
3261 ice_debug(hw, ICE_DBG_LINK, " eee_cap = 0x%x\n", cfg->eee_cap);
3262 ice_debug(hw, ICE_DBG_LINK, " eeer_value = 0x%x\n", cfg->eeer_value);
3263 ice_debug(hw, ICE_DBG_LINK, " link_fec_opt = 0x%x\n",
3266 status = ice_aq_send_cmd(hw, &desc, cfg, sizeof(*cfg), cd);
3268 if (hw->adminq.sq_last_status == ICE_AQ_RC_EMODE)
3269 status = ICE_SUCCESS;
3272 pi->phy.curr_user_phy_cfg = *cfg;
3278 * ice_update_link_info - update status of the HW network link
3279 * @pi: port info structure of the interested logical port
3281 enum ice_status ice_update_link_info(struct ice_port_info *pi)
3283 struct ice_link_status *li;
3284 enum ice_status status;
3287 return ICE_ERR_PARAM;
3289 li = &pi->phy.link_info;
3291 status = ice_aq_get_link_info(pi, true, NULL, NULL);
3295 if (li->link_info & ICE_AQ_MEDIA_AVAILABLE) {
3296 struct ice_aqc_get_phy_caps_data *pcaps;
3300 pcaps = (struct ice_aqc_get_phy_caps_data *)
3301 ice_malloc(hw, sizeof(*pcaps));
3303 return ICE_ERR_NO_MEMORY;
3305 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_TOPO_CAP_MEDIA,
3308 if (status == ICE_SUCCESS)
3309 ice_memcpy(li->module_type, &pcaps->module_type,
3310 sizeof(li->module_type),
3311 ICE_NONDMA_TO_NONDMA);
3313 ice_free(hw, pcaps);
3320 * ice_cache_phy_user_req
3321 * @pi: port information structure
3322 * @cache_data: PHY logging data
3323 * @cache_mode: PHY logging mode
3325 * Log the user request on (FC, FEC, SPEED) for later user.
3328 ice_cache_phy_user_req(struct ice_port_info *pi,
3329 struct ice_phy_cache_mode_data cache_data,
3330 enum ice_phy_cache_mode cache_mode)
3335 switch (cache_mode) {
3337 pi->phy.curr_user_fc_req = cache_data.data.curr_user_fc_req;
3339 case ICE_SPEED_MODE:
3340 pi->phy.curr_user_speed_req =
3341 cache_data.data.curr_user_speed_req;
3344 pi->phy.curr_user_fec_req = cache_data.data.curr_user_fec_req;
3352 * ice_caps_to_fc_mode
3353 * @caps: PHY capabilities
3355 * Convert PHY FC capabilities to ice FC mode
3357 enum ice_fc_mode ice_caps_to_fc_mode(u8 caps)
3359 if (caps & ICE_AQC_PHY_EN_TX_LINK_PAUSE &&
3360 caps & ICE_AQC_PHY_EN_RX_LINK_PAUSE)
3363 if (caps & ICE_AQC_PHY_EN_TX_LINK_PAUSE)
3364 return ICE_FC_TX_PAUSE;
3366 if (caps & ICE_AQC_PHY_EN_RX_LINK_PAUSE)
3367 return ICE_FC_RX_PAUSE;
3373 * ice_caps_to_fec_mode
3374 * @caps: PHY capabilities
3375 * @fec_options: Link FEC options
3377 * Convert PHY FEC capabilities to ice FEC mode
3379 enum ice_fec_mode ice_caps_to_fec_mode(u8 caps, u8 fec_options)
3381 if (caps & ICE_AQC_PHY_EN_AUTO_FEC)
3382 return ICE_FEC_AUTO;
3384 if (fec_options & (ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN |
3385 ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ |
3386 ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN |
3387 ICE_AQC_PHY_FEC_25G_KR_REQ))
3388 return ICE_FEC_BASER;
3390 if (fec_options & (ICE_AQC_PHY_FEC_25G_RS_528_REQ |
3391 ICE_AQC_PHY_FEC_25G_RS_544_REQ |
3392 ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN))
3395 return ICE_FEC_NONE;
3399 * ice_cfg_phy_fc - Configure PHY FC data based on FC mode
3400 * @pi: port information structure
3401 * @cfg: PHY configuration data to set FC mode
3402 * @req_mode: FC mode to configure
3404 static enum ice_status
3405 ice_cfg_phy_fc(struct ice_port_info *pi, struct ice_aqc_set_phy_cfg_data *cfg,
3406 enum ice_fc_mode req_mode)
3408 struct ice_phy_cache_mode_data cache_data;
3409 u8 pause_mask = 0x0;
3412 return ICE_ERR_BAD_PTR;
3417 struct ice_aqc_get_phy_caps_data *pcaps;
3418 enum ice_status status;
3420 pcaps = (struct ice_aqc_get_phy_caps_data *)
3421 ice_malloc(pi->hw, sizeof(*pcaps));
3423 return ICE_ERR_NO_MEMORY;
3425 /* Query the value of FC that both the NIC and attached media
3428 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_TOPO_CAP_MEDIA,
3431 ice_free(pi->hw, pcaps);
3435 pause_mask |= pcaps->caps & ICE_AQC_PHY_EN_TX_LINK_PAUSE;
3436 pause_mask |= pcaps->caps & ICE_AQC_PHY_EN_RX_LINK_PAUSE;
3438 ice_free(pi->hw, pcaps);
3442 pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE;
3443 pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE;
3445 case ICE_FC_RX_PAUSE:
3446 pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE;
3448 case ICE_FC_TX_PAUSE:
3449 pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE;
3455 /* clear the old pause settings */
3456 cfg->caps &= ~(ICE_AQC_PHY_EN_TX_LINK_PAUSE |
3457 ICE_AQC_PHY_EN_RX_LINK_PAUSE);
3459 /* set the new capabilities */
3460 cfg->caps |= pause_mask;
3462 /* Cache user FC request */
3463 cache_data.data.curr_user_fc_req = req_mode;
3464 ice_cache_phy_user_req(pi, cache_data, ICE_FC_MODE);
3471 * @pi: port information structure
3472 * @aq_failures: pointer to status code, specific to ice_set_fc routine
3473 * @ena_auto_link_update: enable automatic link update
3475 * Set the requested flow control mode.
3478 ice_set_fc(struct ice_port_info *pi, u8 *aq_failures, bool ena_auto_link_update)
3480 struct ice_aqc_set_phy_cfg_data cfg = { 0 };
3481 struct ice_aqc_get_phy_caps_data *pcaps;
3482 enum ice_status status;
3485 if (!pi || !aq_failures)
3486 return ICE_ERR_BAD_PTR;
3491 pcaps = (struct ice_aqc_get_phy_caps_data *)
3492 ice_malloc(hw, sizeof(*pcaps));
3494 return ICE_ERR_NO_MEMORY;
3496 /* Get the current PHY config */
3497 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_ACTIVE_CFG,
3501 *aq_failures = ICE_SET_FC_AQ_FAIL_GET;
3505 ice_copy_phy_caps_to_cfg(pi, pcaps, &cfg);
3507 /* Configure the set PHY data */
3508 status = ice_cfg_phy_fc(pi, &cfg, pi->fc.req_mode);
3510 if (status != ICE_ERR_BAD_PTR)
3511 *aq_failures = ICE_SET_FC_AQ_FAIL_GET;
3516 /* If the capabilities have changed, then set the new config */
3517 if (cfg.caps != pcaps->caps) {
3518 int retry_count, retry_max = 10;
3520 /* Auto restart link so settings take effect */
3521 if (ena_auto_link_update)
3522 cfg.caps |= ICE_AQ_PHY_ENA_AUTO_LINK_UPDT;
3524 status = ice_aq_set_phy_cfg(hw, pi, &cfg, NULL);
3526 *aq_failures = ICE_SET_FC_AQ_FAIL_SET;
3530 /* Update the link info
3531 * It sometimes takes a really long time for link to
3532 * come back from the atomic reset. Thus, we wait a
3535 for (retry_count = 0; retry_count < retry_max; retry_count++) {
3536 status = ice_update_link_info(pi);
3538 if (status == ICE_SUCCESS)
3541 ice_msec_delay(100, true);
3545 *aq_failures = ICE_SET_FC_AQ_FAIL_UPDATE;
3549 ice_free(hw, pcaps);
3554 * ice_phy_caps_equals_cfg
3555 * @phy_caps: PHY capabilities
3556 * @phy_cfg: PHY configuration
3558 * Helper function to determine if PHY capabilities matches PHY
3562 ice_phy_caps_equals_cfg(struct ice_aqc_get_phy_caps_data *phy_caps,
3563 struct ice_aqc_set_phy_cfg_data *phy_cfg)
3565 u8 caps_mask, cfg_mask;
3567 if (!phy_caps || !phy_cfg)
3570 /* These bits are not common between capabilities and configuration.
3571 * Do not use them to determine equality.
3573 caps_mask = ICE_AQC_PHY_CAPS_MASK & ~(ICE_AQC_PHY_AN_MODE |
3574 ICE_AQC_PHY_EN_MOD_QUAL);
3575 cfg_mask = ICE_AQ_PHY_ENA_VALID_MASK & ~ICE_AQ_PHY_ENA_AUTO_LINK_UPDT;
3577 if (phy_caps->phy_type_low != phy_cfg->phy_type_low ||
3578 phy_caps->phy_type_high != phy_cfg->phy_type_high ||
3579 ((phy_caps->caps & caps_mask) != (phy_cfg->caps & cfg_mask)) ||
3580 phy_caps->low_power_ctrl_an != phy_cfg->low_power_ctrl_an ||
3581 phy_caps->eee_cap != phy_cfg->eee_cap ||
3582 phy_caps->eeer_value != phy_cfg->eeer_value ||
3583 phy_caps->link_fec_options != phy_cfg->link_fec_opt)
3590 * ice_copy_phy_caps_to_cfg - Copy PHY ability data to configuration data
3591 * @pi: port information structure
3592 * @caps: PHY ability structure to copy data from
3593 * @cfg: PHY configuration structure to copy data to
3595 * Helper function to copy AQC PHY get ability data to PHY set configuration
3599 ice_copy_phy_caps_to_cfg(struct ice_port_info *pi,
3600 struct ice_aqc_get_phy_caps_data *caps,
3601 struct ice_aqc_set_phy_cfg_data *cfg)
3603 if (!pi || !caps || !cfg)
3606 ice_memset(cfg, 0, sizeof(*cfg), ICE_NONDMA_MEM);
3607 cfg->phy_type_low = caps->phy_type_low;
3608 cfg->phy_type_high = caps->phy_type_high;
3609 cfg->caps = caps->caps;
3610 cfg->low_power_ctrl_an = caps->low_power_ctrl_an;
3611 cfg->eee_cap = caps->eee_cap;
3612 cfg->eeer_value = caps->eeer_value;
3613 cfg->link_fec_opt = caps->link_fec_options;
3614 cfg->module_compliance_enforcement =
3615 caps->module_compliance_enforcement;
3619 * ice_cfg_phy_fec - Configure PHY FEC data based on FEC mode
3620 * @pi: port information structure
3621 * @cfg: PHY configuration data to set FEC mode
3622 * @fec: FEC mode to configure
3625 ice_cfg_phy_fec(struct ice_port_info *pi, struct ice_aqc_set_phy_cfg_data *cfg,
3626 enum ice_fec_mode fec)
3628 struct ice_aqc_get_phy_caps_data *pcaps;
3629 enum ice_status status = ICE_SUCCESS;
3633 return ICE_ERR_BAD_PTR;
3637 pcaps = (struct ice_aqc_get_phy_caps_data *)
3638 ice_malloc(hw, sizeof(*pcaps));
3640 return ICE_ERR_NO_MEMORY;
3642 status = ice_aq_get_phy_caps(pi, false,
3643 (ice_fw_supports_report_dflt_cfg(hw) ?
3644 ICE_AQC_REPORT_DFLT_CFG :
3645 ICE_AQC_REPORT_TOPO_CAP_MEDIA), pcaps, NULL);
3650 cfg->caps |= (pcaps->caps & ICE_AQC_PHY_EN_AUTO_FEC);
3651 cfg->link_fec_opt = pcaps->link_fec_options;
3655 /* Clear RS bits, and AND BASE-R ability
3656 * bits and OR request bits.
3658 cfg->link_fec_opt &= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN |
3659 ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN;
3660 cfg->link_fec_opt |= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ |
3661 ICE_AQC_PHY_FEC_25G_KR_REQ;
3664 /* Clear BASE-R bits, and AND RS ability
3665 * bits and OR request bits.
3667 cfg->link_fec_opt &= ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN;
3668 cfg->link_fec_opt |= ICE_AQC_PHY_FEC_25G_RS_528_REQ |
3669 ICE_AQC_PHY_FEC_25G_RS_544_REQ;
3672 /* Clear all FEC option bits. */
3673 cfg->link_fec_opt &= ~ICE_AQC_PHY_FEC_MASK;
3676 /* AND auto FEC bit, and all caps bits. */
3677 cfg->caps &= ICE_AQC_PHY_CAPS_MASK;
3678 cfg->link_fec_opt |= pcaps->link_fec_options;
3681 status = ICE_ERR_PARAM;
3685 if (fec == ICE_FEC_AUTO && ice_fw_supports_link_override(pi->hw) &&
3686 !ice_fw_supports_report_dflt_cfg(pi->hw)) {
3687 struct ice_link_default_override_tlv tlv;
3689 if (ice_get_link_default_override(&tlv, pi))
3692 if (!(tlv.options & ICE_LINK_OVERRIDE_STRICT_MODE) &&
3693 (tlv.options & ICE_LINK_OVERRIDE_EN))
3694 cfg->link_fec_opt = tlv.fec_options;
3698 ice_free(hw, pcaps);
3704 * ice_get_link_status - get status of the HW network link
3705 * @pi: port information structure
3706 * @link_up: pointer to bool (true/false = linkup/linkdown)
3708 * Variable link_up is true if link is up, false if link is down.
3709 * The variable link_up is invalid if status is non zero. As a
3710 * result of this call, link status reporting becomes enabled
3712 enum ice_status ice_get_link_status(struct ice_port_info *pi, bool *link_up)
3714 struct ice_phy_info *phy_info;
3715 enum ice_status status = ICE_SUCCESS;
3717 if (!pi || !link_up)
3718 return ICE_ERR_PARAM;
3720 phy_info = &pi->phy;
3722 if (phy_info->get_link_info) {
3723 status = ice_update_link_info(pi);
3726 ice_debug(pi->hw, ICE_DBG_LINK, "get link status error, status = %d\n",
3730 *link_up = phy_info->link_info.link_info & ICE_AQ_LINK_UP;
3736 * ice_aq_set_link_restart_an
3737 * @pi: pointer to the port information structure
3738 * @ena_link: if true: enable link, if false: disable link
3739 * @cd: pointer to command details structure or NULL
3741 * Sets up the link and restarts the Auto-Negotiation over the link.
3744 ice_aq_set_link_restart_an(struct ice_port_info *pi, bool ena_link,
3745 struct ice_sq_cd *cd)
3747 struct ice_aqc_restart_an *cmd;
3748 struct ice_aq_desc desc;
3750 cmd = &desc.params.restart_an;
3752 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_restart_an);
3754 cmd->cmd_flags = ICE_AQC_RESTART_AN_LINK_RESTART;
3755 cmd->lport_num = pi->lport;
3757 cmd->cmd_flags |= ICE_AQC_RESTART_AN_LINK_ENABLE;
3759 cmd->cmd_flags &= ~ICE_AQC_RESTART_AN_LINK_ENABLE;
3761 return ice_aq_send_cmd(pi->hw, &desc, NULL, 0, cd);
3765 * ice_aq_set_event_mask
3766 * @hw: pointer to the HW struct
3767 * @port_num: port number of the physical function
3768 * @mask: event mask to be set
3769 * @cd: pointer to command details structure or NULL
3771 * Set event mask (0x0613)
3774 ice_aq_set_event_mask(struct ice_hw *hw, u8 port_num, u16 mask,
3775 struct ice_sq_cd *cd)
3777 struct ice_aqc_set_event_mask *cmd;
3778 struct ice_aq_desc desc;
3780 cmd = &desc.params.set_event_mask;
3782 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_event_mask);
3784 cmd->lport_num = port_num;
3786 cmd->event_mask = CPU_TO_LE16(mask);
3787 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
3791 * ice_aq_set_mac_loopback
3792 * @hw: pointer to the HW struct
3793 * @ena_lpbk: Enable or Disable loopback
3794 * @cd: pointer to command details structure or NULL
3796 * Enable/disable loopback on a given port
3799 ice_aq_set_mac_loopback(struct ice_hw *hw, bool ena_lpbk, struct ice_sq_cd *cd)
3801 struct ice_aqc_set_mac_lb *cmd;
3802 struct ice_aq_desc desc;
3804 cmd = &desc.params.set_mac_lb;
3806 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_mac_lb);
3808 cmd->lb_mode = ICE_AQ_MAC_LB_EN;
3810 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
3814 * ice_aq_set_port_id_led
3815 * @pi: pointer to the port information
3816 * @is_orig_mode: is this LED set to original mode (by the net-list)
3817 * @cd: pointer to command details structure or NULL
3819 * Set LED value for the given port (0x06e9)
3822 ice_aq_set_port_id_led(struct ice_port_info *pi, bool is_orig_mode,
3823 struct ice_sq_cd *cd)
3825 struct ice_aqc_set_port_id_led *cmd;
3826 struct ice_hw *hw = pi->hw;
3827 struct ice_aq_desc desc;
3829 cmd = &desc.params.set_port_id_led;
3831 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_port_id_led);
3834 cmd->ident_mode = ICE_AQC_PORT_IDENT_LED_ORIG;
3836 cmd->ident_mode = ICE_AQC_PORT_IDENT_LED_BLINK;
3838 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
3843 * @hw: pointer to the HW struct
3844 * @lport: bits [7:0] = logical port, bit [8] = logical port valid
3845 * @bus_addr: I2C bus address of the eeprom (typically 0xA0, 0=topo default)
3846 * @mem_addr: I2C offset. lower 8 bits for address, 8 upper bits zero padding.
3848 * @set_page: set or ignore the page
3849 * @data: pointer to data buffer to be read/written to the I2C device.
3850 * @length: 1-16 for read, 1 for write.
3851 * @write: 0 read, 1 for write.
3852 * @cd: pointer to command details structure or NULL
3854 * Read/Write SFF EEPROM (0x06EE)
3857 ice_aq_sff_eeprom(struct ice_hw *hw, u16 lport, u8 bus_addr,
3858 u16 mem_addr, u8 page, u8 set_page, u8 *data, u8 length,
3859 bool write, struct ice_sq_cd *cd)
3861 struct ice_aqc_sff_eeprom *cmd;
3862 struct ice_aq_desc desc;
3863 enum ice_status status;
3865 if (!data || (mem_addr & 0xff00))
3866 return ICE_ERR_PARAM;
3868 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_sff_eeprom);
3869 cmd = &desc.params.read_write_sff_param;
3870 desc.flags = CPU_TO_LE16(ICE_AQ_FLAG_RD);
3871 cmd->lport_num = (u8)(lport & 0xff);
3872 cmd->lport_num_valid = (u8)((lport >> 8) & 0x01);
3873 cmd->i2c_bus_addr = CPU_TO_LE16(((bus_addr >> 1) &
3874 ICE_AQC_SFF_I2CBUS_7BIT_M) |
3876 ICE_AQC_SFF_SET_EEPROM_PAGE_S) &
3877 ICE_AQC_SFF_SET_EEPROM_PAGE_M));
3878 cmd->i2c_mem_addr = CPU_TO_LE16(mem_addr & 0xff);
3879 cmd->eeprom_page = CPU_TO_LE16((u16)page << ICE_AQC_SFF_EEPROM_PAGE_S);
3881 cmd->i2c_bus_addr |= CPU_TO_LE16(ICE_AQC_SFF_IS_WRITE);
3883 status = ice_aq_send_cmd(hw, &desc, data, length, cd);
3888 * ice_aq_prog_topo_dev_nvm
3889 * @hw: pointer to the hardware structure
3890 * @topo_params: pointer to structure storing topology parameters for a device
3891 * @cd: pointer to command details structure or NULL
3893 * Program Topology Device NVM (0x06F2)
3897 ice_aq_prog_topo_dev_nvm(struct ice_hw *hw,
3898 struct ice_aqc_link_topo_params *topo_params,
3899 struct ice_sq_cd *cd)
3901 struct ice_aqc_prog_topo_dev_nvm *cmd;
3902 struct ice_aq_desc desc;
3904 cmd = &desc.params.prog_topo_dev_nvm;
3906 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_prog_topo_dev_nvm);
3908 ice_memcpy(&cmd->topo_params, topo_params, sizeof(*topo_params),
3909 ICE_NONDMA_TO_NONDMA);
3911 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
3915 * ice_aq_read_topo_dev_nvm
3916 * @hw: pointer to the hardware structure
3917 * @topo_params: pointer to structure storing topology parameters for a device
3918 * @start_address: byte offset in the topology device NVM
3919 * @data: pointer to data buffer
3920 * @data_size: number of bytes to be read from the topology device NVM
3921 * @cd: pointer to command details structure or NULL
3922 * Read Topology Device NVM (0x06F3)
3926 ice_aq_read_topo_dev_nvm(struct ice_hw *hw,
3927 struct ice_aqc_link_topo_params *topo_params,
3928 u32 start_address, u8 *data, u8 data_size,
3929 struct ice_sq_cd *cd)
3931 struct ice_aqc_read_topo_dev_nvm *cmd;
3932 struct ice_aq_desc desc;
3933 enum ice_status status;
3935 if (!data || data_size == 0 ||
3936 data_size > ICE_AQC_READ_TOPO_DEV_NVM_DATA_READ_SIZE)
3937 return ICE_ERR_PARAM;
3939 cmd = &desc.params.read_topo_dev_nvm;
3941 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_read_topo_dev_nvm);
3943 desc.datalen = data_size;
3944 ice_memcpy(&cmd->topo_params, topo_params, sizeof(*topo_params),
3945 ICE_NONDMA_TO_NONDMA);
3946 cmd->start_address = CPU_TO_LE32(start_address);
3948 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
3952 ice_memcpy(data, cmd->data_read, data_size, ICE_NONDMA_TO_NONDMA);
3958 * __ice_aq_get_set_rss_lut
3959 * @hw: pointer to the hardware structure
3960 * @params: RSS LUT parameters
3961 * @set: set true to set the table, false to get the table
3963 * Internal function to get (0x0B05) or set (0x0B03) RSS look up table
3965 static enum ice_status
3966 __ice_aq_get_set_rss_lut(struct ice_hw *hw, struct ice_aq_get_set_rss_lut_params *params, bool set)
3968 u16 flags = 0, vsi_id, lut_type, lut_size, glob_lut_idx, vsi_handle;
3969 struct ice_aqc_get_set_rss_lut *cmd_resp;
3970 struct ice_aq_desc desc;
3971 enum ice_status status;
3975 return ICE_ERR_PARAM;
3977 vsi_handle = params->vsi_handle;
3980 if (!ice_is_vsi_valid(hw, vsi_handle) || !lut)
3981 return ICE_ERR_PARAM;
3983 lut_size = params->lut_size;
3984 lut_type = params->lut_type;
3985 glob_lut_idx = params->global_lut_id;
3986 vsi_id = ice_get_hw_vsi_num(hw, vsi_handle);
3988 cmd_resp = &desc.params.get_set_rss_lut;
3991 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_rss_lut);
3992 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
3994 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_rss_lut);
3997 cmd_resp->vsi_id = CPU_TO_LE16(((vsi_id <<
3998 ICE_AQC_GSET_RSS_LUT_VSI_ID_S) &
3999 ICE_AQC_GSET_RSS_LUT_VSI_ID_M) |
4000 ICE_AQC_GSET_RSS_LUT_VSI_VALID);
4003 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_VSI:
4004 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF:
4005 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL:
4006 flags |= ((lut_type << ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S) &
4007 ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_M);
4010 status = ICE_ERR_PARAM;
4011 goto ice_aq_get_set_rss_lut_exit;
4014 if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL) {
4015 flags |= ((glob_lut_idx << ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S) &
4016 ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_M);
4019 goto ice_aq_get_set_rss_lut_send;
4020 } else if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF) {
4022 goto ice_aq_get_set_rss_lut_send;
4024 goto ice_aq_get_set_rss_lut_send;
4027 /* LUT size is only valid for Global and PF table types */
4029 case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128:
4030 flags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128_FLAG <<
4031 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) &
4032 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M;
4034 case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512:
4035 flags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512_FLAG <<
4036 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) &
4037 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M;
4039 case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K:
4040 if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF) {
4041 flags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K_FLAG <<
4042 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) &
4043 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M;
4048 status = ICE_ERR_PARAM;
4049 goto ice_aq_get_set_rss_lut_exit;
4052 ice_aq_get_set_rss_lut_send:
4053 cmd_resp->flags = CPU_TO_LE16(flags);
4054 status = ice_aq_send_cmd(hw, &desc, lut, lut_size, NULL);
4056 ice_aq_get_set_rss_lut_exit:
4061 * ice_aq_get_rss_lut
4062 * @hw: pointer to the hardware structure
4063 * @get_params: RSS LUT parameters used to specify which RSS LUT to get
4065 * get the RSS lookup table, PF or VSI type
4068 ice_aq_get_rss_lut(struct ice_hw *hw, struct ice_aq_get_set_rss_lut_params *get_params)
4070 return __ice_aq_get_set_rss_lut(hw, get_params, false);
4074 * ice_aq_set_rss_lut
4075 * @hw: pointer to the hardware structure
4076 * @set_params: RSS LUT parameters used to specify how to set the RSS LUT
4078 * set the RSS lookup table, PF or VSI type
4081 ice_aq_set_rss_lut(struct ice_hw *hw, struct ice_aq_get_set_rss_lut_params *set_params)
4083 return __ice_aq_get_set_rss_lut(hw, set_params, true);
4087 * __ice_aq_get_set_rss_key
4088 * @hw: pointer to the HW struct
4089 * @vsi_id: VSI FW index
4090 * @key: pointer to key info struct
4091 * @set: set true to set the key, false to get the key
4093 * get (0x0B04) or set (0x0B02) the RSS key per VSI
4096 ice_status __ice_aq_get_set_rss_key(struct ice_hw *hw, u16 vsi_id,
4097 struct ice_aqc_get_set_rss_keys *key,
4100 struct ice_aqc_get_set_rss_key *cmd_resp;
4101 u16 key_size = sizeof(*key);
4102 struct ice_aq_desc desc;
4104 cmd_resp = &desc.params.get_set_rss_key;
4107 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_rss_key);
4108 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
4110 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_rss_key);
4113 cmd_resp->vsi_id = CPU_TO_LE16(((vsi_id <<
4114 ICE_AQC_GSET_RSS_KEY_VSI_ID_S) &
4115 ICE_AQC_GSET_RSS_KEY_VSI_ID_M) |
4116 ICE_AQC_GSET_RSS_KEY_VSI_VALID);
4118 return ice_aq_send_cmd(hw, &desc, key, key_size, NULL);
4122 * ice_aq_get_rss_key
4123 * @hw: pointer to the HW struct
4124 * @vsi_handle: software VSI handle
4125 * @key: pointer to key info struct
4127 * get the RSS key per VSI
4130 ice_aq_get_rss_key(struct ice_hw *hw, u16 vsi_handle,
4131 struct ice_aqc_get_set_rss_keys *key)
4133 if (!ice_is_vsi_valid(hw, vsi_handle) || !key)
4134 return ICE_ERR_PARAM;
4136 return __ice_aq_get_set_rss_key(hw, ice_get_hw_vsi_num(hw, vsi_handle),
4141 * ice_aq_set_rss_key
4142 * @hw: pointer to the HW struct
4143 * @vsi_handle: software VSI handle
4144 * @keys: pointer to key info struct
4146 * set the RSS key per VSI
4149 ice_aq_set_rss_key(struct ice_hw *hw, u16 vsi_handle,
4150 struct ice_aqc_get_set_rss_keys *keys)
4152 if (!ice_is_vsi_valid(hw, vsi_handle) || !keys)
4153 return ICE_ERR_PARAM;
4155 return __ice_aq_get_set_rss_key(hw, ice_get_hw_vsi_num(hw, vsi_handle),
4160 * ice_aq_add_lan_txq
4161 * @hw: pointer to the hardware structure
4162 * @num_qgrps: Number of added queue groups
4163 * @qg_list: list of queue groups to be added
4164 * @buf_size: size of buffer for indirect command
4165 * @cd: pointer to command details structure or NULL
4167 * Add Tx LAN queue (0x0C30)
4170 * Prior to calling add Tx LAN queue:
4171 * Initialize the following as part of the Tx queue context:
4172 * Completion queue ID if the queue uses Completion queue, Quanta profile,
4173 * Cache profile and Packet shaper profile.
4175 * After add Tx LAN queue AQ command is completed:
4176 * Interrupts should be associated with specific queues,
4177 * Association of Tx queue to Doorbell queue is not part of Add LAN Tx queue
4181 ice_aq_add_lan_txq(struct ice_hw *hw, u8 num_qgrps,
4182 struct ice_aqc_add_tx_qgrp *qg_list, u16 buf_size,
4183 struct ice_sq_cd *cd)
4185 struct ice_aqc_add_tx_qgrp *list;
4186 struct ice_aqc_add_txqs *cmd;
4187 struct ice_aq_desc desc;
4188 u16 i, sum_size = 0;
4190 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
4192 cmd = &desc.params.add_txqs;
4194 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_add_txqs);
4197 return ICE_ERR_PARAM;
4199 if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS)
4200 return ICE_ERR_PARAM;
4202 for (i = 0, list = qg_list; i < num_qgrps; i++) {
4203 sum_size += ice_struct_size(list, txqs, list->num_txqs);
4204 list = (struct ice_aqc_add_tx_qgrp *)(list->txqs +
4208 if (buf_size != sum_size)
4209 return ICE_ERR_PARAM;
4211 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
4213 cmd->num_qgrps = num_qgrps;
4215 return ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd);
4219 * ice_aq_dis_lan_txq
4220 * @hw: pointer to the hardware structure
4221 * @num_qgrps: number of groups in the list
4222 * @qg_list: the list of groups to disable
4223 * @buf_size: the total size of the qg_list buffer in bytes
4224 * @rst_src: if called due to reset, specifies the reset source
4225 * @vmvf_num: the relative VM or VF number that is undergoing the reset
4226 * @cd: pointer to command details structure or NULL
4228 * Disable LAN Tx queue (0x0C31)
4230 static enum ice_status
4231 ice_aq_dis_lan_txq(struct ice_hw *hw, u8 num_qgrps,
4232 struct ice_aqc_dis_txq_item *qg_list, u16 buf_size,
4233 enum ice_disq_rst_src rst_src, u16 vmvf_num,
4234 struct ice_sq_cd *cd)
4236 struct ice_aqc_dis_txq_item *item;
4237 struct ice_aqc_dis_txqs *cmd;
4238 struct ice_aq_desc desc;
4239 enum ice_status status;
4242 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
4243 cmd = &desc.params.dis_txqs;
4244 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_dis_txqs);
4246 /* qg_list can be NULL only in VM/VF reset flow */
4247 if (!qg_list && !rst_src)
4248 return ICE_ERR_PARAM;
4250 if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS)
4251 return ICE_ERR_PARAM;
4253 cmd->num_entries = num_qgrps;
4255 cmd->vmvf_and_timeout = CPU_TO_LE16((5 << ICE_AQC_Q_DIS_TIMEOUT_S) &
4256 ICE_AQC_Q_DIS_TIMEOUT_M);
4260 cmd->cmd_type = ICE_AQC_Q_DIS_CMD_VM_RESET;
4261 cmd->vmvf_and_timeout |=
4262 CPU_TO_LE16(vmvf_num & ICE_AQC_Q_DIS_VMVF_NUM_M);
4269 /* flush pipe on time out */
4270 cmd->cmd_type |= ICE_AQC_Q_DIS_CMD_FLUSH_PIPE;
4271 /* If no queue group info, we are in a reset flow. Issue the AQ */
4275 /* set RD bit to indicate that command buffer is provided by the driver
4276 * and it needs to be read by the firmware
4278 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
4280 for (i = 0, item = qg_list; i < num_qgrps; i++) {
4281 u16 item_size = ice_struct_size(item, q_id, item->num_qs);
4283 /* If the num of queues is even, add 2 bytes of padding */
4284 if ((item->num_qs % 2) == 0)
4289 item = (struct ice_aqc_dis_txq_item *)((u8 *)item + item_size);
4293 return ICE_ERR_PARAM;
4296 status = ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd);
4299 ice_debug(hw, ICE_DBG_SCHED, "VM%d disable failed %d\n",
4300 vmvf_num, hw->adminq.sq_last_status);
4302 ice_debug(hw, ICE_DBG_SCHED, "disable queue %d failed %d\n",
4303 LE16_TO_CPU(qg_list[0].q_id[0]),
4304 hw->adminq.sq_last_status);
4310 * ice_aq_move_recfg_lan_txq
4311 * @hw: pointer to the hardware structure
4312 * @num_qs: number of queues to move/reconfigure
4313 * @is_move: true if this operation involves node movement
4314 * @is_tc_change: true if this operation involves a TC change
4315 * @subseq_call: true if this operation is a subsequent call
4316 * @flush_pipe: on timeout, true to flush pipe, false to return EAGAIN
4317 * @timeout: timeout in units of 100 usec (valid values 0-50)
4318 * @blocked_cgds: out param, bitmap of CGDs that timed out if returning EAGAIN
4319 * @buf: struct containing src/dest TEID and per-queue info
4320 * @buf_size: size of buffer for indirect command
4321 * @txqs_moved: out param, number of queues successfully moved
4322 * @cd: pointer to command details structure or NULL
4324 * Move / Reconfigure Tx LAN queues (0x0C32)
4327 ice_aq_move_recfg_lan_txq(struct ice_hw *hw, u8 num_qs, bool is_move,
4328 bool is_tc_change, bool subseq_call, bool flush_pipe,
4329 u8 timeout, u32 *blocked_cgds,
4330 struct ice_aqc_move_txqs_data *buf, u16 buf_size,
4331 u8 *txqs_moved, struct ice_sq_cd *cd)
4333 struct ice_aqc_move_txqs *cmd;
4334 struct ice_aq_desc desc;
4335 enum ice_status status;
4337 cmd = &desc.params.move_txqs;
4338 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_move_recfg_txqs);
4340 #define ICE_LAN_TXQ_MOVE_TIMEOUT_MAX 50
4341 if (timeout > ICE_LAN_TXQ_MOVE_TIMEOUT_MAX)
4342 return ICE_ERR_PARAM;
4344 if (is_tc_change && !flush_pipe && !blocked_cgds)
4345 return ICE_ERR_PARAM;
4347 if (!is_move && !is_tc_change)
4348 return ICE_ERR_PARAM;
4350 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
4353 cmd->cmd_type |= ICE_AQC_Q_CMD_TYPE_MOVE;
4356 cmd->cmd_type |= ICE_AQC_Q_CMD_TYPE_TC_CHANGE;
4359 cmd->cmd_type |= ICE_AQC_Q_CMD_SUBSEQ_CALL;
4362 cmd->cmd_type |= ICE_AQC_Q_CMD_FLUSH_PIPE;
4364 cmd->num_qs = num_qs;
4365 cmd->timeout = ((timeout << ICE_AQC_Q_CMD_TIMEOUT_S) &
4366 ICE_AQC_Q_CMD_TIMEOUT_M);
4368 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);
4370 if (!status && txqs_moved)
4371 *txqs_moved = cmd->num_qs;
4373 if (hw->adminq.sq_last_status == ICE_AQ_RC_EAGAIN &&
4374 is_tc_change && !flush_pipe)
4375 *blocked_cgds = LE32_TO_CPU(cmd->blocked_cgds);
4380 /* End of FW Admin Queue command wrappers */
4383 * ice_write_byte - write a byte to a packed context structure
4384 * @src_ctx: the context structure to read from
4385 * @dest_ctx: the context to be written to
4386 * @ce_info: a description of the struct to be filled
4389 ice_write_byte(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)
4391 u8 src_byte, dest_byte, mask;
4395 /* copy from the next struct field */
4396 from = src_ctx + ce_info->offset;
4398 /* prepare the bits and mask */
4399 shift_width = ce_info->lsb % 8;
4400 mask = (u8)(BIT(ce_info->width) - 1);
4405 /* shift to correct alignment */
4406 mask <<= shift_width;
4407 src_byte <<= shift_width;
4409 /* get the current bits from the target bit string */
4410 dest = dest_ctx + (ce_info->lsb / 8);
4412 ice_memcpy(&dest_byte, dest, sizeof(dest_byte), ICE_DMA_TO_NONDMA);
4414 dest_byte &= ~mask; /* get the bits not changing */
4415 dest_byte |= src_byte; /* add in the new bits */
4417 /* put it all back */
4418 ice_memcpy(dest, &dest_byte, sizeof(dest_byte), ICE_NONDMA_TO_DMA);
4422 * ice_write_word - write a word to a packed context structure
4423 * @src_ctx: the context structure to read from
4424 * @dest_ctx: the context to be written to
4425 * @ce_info: a description of the struct to be filled
4428 ice_write_word(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)
4435 /* copy from the next struct field */
4436 from = src_ctx + ce_info->offset;
4438 /* prepare the bits and mask */
4439 shift_width = ce_info->lsb % 8;
4440 mask = BIT(ce_info->width) - 1;
4442 /* don't swizzle the bits until after the mask because the mask bits
4443 * will be in a different bit position on big endian machines
4445 src_word = *(u16 *)from;
4448 /* shift to correct alignment */
4449 mask <<= shift_width;
4450 src_word <<= shift_width;
4452 /* get the current bits from the target bit string */
4453 dest = dest_ctx + (ce_info->lsb / 8);
4455 ice_memcpy(&dest_word, dest, sizeof(dest_word), ICE_DMA_TO_NONDMA);
4457 dest_word &= ~(CPU_TO_LE16(mask)); /* get the bits not changing */
4458 dest_word |= CPU_TO_LE16(src_word); /* add in the new bits */
4460 /* put it all back */
4461 ice_memcpy(dest, &dest_word, sizeof(dest_word), ICE_NONDMA_TO_DMA);
4465 * ice_write_dword - write a dword to a packed context structure
4466 * @src_ctx: the context structure to read from
4467 * @dest_ctx: the context to be written to
4468 * @ce_info: a description of the struct to be filled
4471 ice_write_dword(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)
4473 u32 src_dword, mask;
4478 /* copy from the next struct field */
4479 from = src_ctx + ce_info->offset;
4481 /* prepare the bits and mask */
4482 shift_width = ce_info->lsb % 8;
4484 /* if the field width is exactly 32 on an x86 machine, then the shift
4485 * operation will not work because the SHL instructions count is masked
4486 * to 5 bits so the shift will do nothing
4488 if (ce_info->width < 32)
4489 mask = BIT(ce_info->width) - 1;
4493 /* don't swizzle the bits until after the mask because the mask bits
4494 * will be in a different bit position on big endian machines
4496 src_dword = *(u32 *)from;
4499 /* shift to correct alignment */
4500 mask <<= shift_width;
4501 src_dword <<= shift_width;
4503 /* get the current bits from the target bit string */
4504 dest = dest_ctx + (ce_info->lsb / 8);
4506 ice_memcpy(&dest_dword, dest, sizeof(dest_dword), ICE_DMA_TO_NONDMA);
4508 dest_dword &= ~(CPU_TO_LE32(mask)); /* get the bits not changing */
4509 dest_dword |= CPU_TO_LE32(src_dword); /* add in the new bits */
4511 /* put it all back */
4512 ice_memcpy(dest, &dest_dword, sizeof(dest_dword), ICE_NONDMA_TO_DMA);
4516 * ice_write_qword - write a qword to a packed context structure
4517 * @src_ctx: the context structure to read from
4518 * @dest_ctx: the context to be written to
4519 * @ce_info: a description of the struct to be filled
4522 ice_write_qword(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)
4524 u64 src_qword, mask;
4529 /* copy from the next struct field */
4530 from = src_ctx + ce_info->offset;
4532 /* prepare the bits and mask */
4533 shift_width = ce_info->lsb % 8;
4535 /* if the field width is exactly 64 on an x86 machine, then the shift
4536 * operation will not work because the SHL instructions count is masked
4537 * to 6 bits so the shift will do nothing
4539 if (ce_info->width < 64)
4540 mask = BIT_ULL(ce_info->width) - 1;
4544 /* don't swizzle the bits until after the mask because the mask bits
4545 * will be in a different bit position on big endian machines
4547 src_qword = *(u64 *)from;
4550 /* shift to correct alignment */
4551 mask <<= shift_width;
4552 src_qword <<= shift_width;
4554 /* get the current bits from the target bit string */
4555 dest = dest_ctx + (ce_info->lsb / 8);
4557 ice_memcpy(&dest_qword, dest, sizeof(dest_qword), ICE_DMA_TO_NONDMA);
4559 dest_qword &= ~(CPU_TO_LE64(mask)); /* get the bits not changing */
4560 dest_qword |= CPU_TO_LE64(src_qword); /* add in the new bits */
4562 /* put it all back */
4563 ice_memcpy(dest, &dest_qword, sizeof(dest_qword), ICE_NONDMA_TO_DMA);
4567 * ice_set_ctx - set context bits in packed structure
4568 * @hw: pointer to the hardware structure
4569 * @src_ctx: pointer to a generic non-packed context structure
4570 * @dest_ctx: pointer to memory for the packed structure
4571 * @ce_info: a description of the structure to be transformed
4574 ice_set_ctx(struct ice_hw *hw, u8 *src_ctx, u8 *dest_ctx,
4575 const struct ice_ctx_ele *ce_info)
4579 for (f = 0; ce_info[f].width; f++) {
4580 /* We have to deal with each element of the FW response
4581 * using the correct size so that we are correct regardless
4582 * of the endianness of the machine.
4584 if (ce_info[f].width > (ce_info[f].size_of * BITS_PER_BYTE)) {
4585 ice_debug(hw, ICE_DBG_QCTX, "Field %d width of %d bits larger than size of %d byte(s) ... skipping write\n",
4586 f, ce_info[f].width, ce_info[f].size_of);
4589 switch (ce_info[f].size_of) {
4591 ice_write_byte(src_ctx, dest_ctx, &ce_info[f]);
4594 ice_write_word(src_ctx, dest_ctx, &ce_info[f]);
4597 ice_write_dword(src_ctx, dest_ctx, &ce_info[f]);
4600 ice_write_qword(src_ctx, dest_ctx, &ce_info[f]);
4603 return ICE_ERR_INVAL_SIZE;
4611 * ice_aq_get_internal_data
4612 * @hw: pointer to the hardware structure
4613 * @cluster_id: specific cluster to dump
4614 * @table_id: table ID within cluster
4615 * @start: index of line in the block to read
4617 * @buf_size: dump buffer size
4618 * @ret_buf_size: return buffer size (returned by FW)
4619 * @ret_next_table: next block to read (returned by FW)
4620 * @ret_next_index: next index to read (returned by FW)
4621 * @cd: pointer to command details structure
4623 * Get internal FW/HW data (0xFF08) for debug purposes.
4626 ice_aq_get_internal_data(struct ice_hw *hw, u8 cluster_id, u16 table_id,
4627 u32 start, void *buf, u16 buf_size, u16 *ret_buf_size,
4628 u16 *ret_next_table, u32 *ret_next_index,
4629 struct ice_sq_cd *cd)
4631 struct ice_aqc_debug_dump_internals *cmd;
4632 struct ice_aq_desc desc;
4633 enum ice_status status;
4635 cmd = &desc.params.debug_dump;
4637 if (buf_size == 0 || !buf)
4638 return ICE_ERR_PARAM;
4640 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_debug_dump_internals);
4642 cmd->cluster_id = cluster_id;
4643 cmd->table_id = CPU_TO_LE16(table_id);
4644 cmd->idx = CPU_TO_LE32(start);
4646 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);
4650 *ret_buf_size = LE16_TO_CPU(desc.datalen);
4652 *ret_next_table = LE16_TO_CPU(cmd->table_id);
4654 *ret_next_index = LE32_TO_CPU(cmd->idx);
4661 * ice_read_byte - read context byte into struct
4662 * @src_ctx: the context structure to read from
4663 * @dest_ctx: the context to be written to
4664 * @ce_info: a description of the struct to be filled
4667 ice_read_byte(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info)
4673 /* prepare the bits and mask */
4674 shift_width = ce_info->lsb % 8;
4675 mask = (u8)(BIT(ce_info->width) - 1);
4677 /* shift to correct alignment */
4678 mask <<= shift_width;
4680 /* get the current bits from the src bit string */
4681 src = src_ctx + (ce_info->lsb / 8);
4683 ice_memcpy(&dest_byte, src, sizeof(dest_byte), ICE_DMA_TO_NONDMA);
4685 dest_byte &= ~(mask);
4687 dest_byte >>= shift_width;
4689 /* get the address from the struct field */
4690 target = dest_ctx + ce_info->offset;
4692 /* put it back in the struct */
4693 ice_memcpy(target, &dest_byte, sizeof(dest_byte), ICE_NONDMA_TO_DMA);
4697 * ice_read_word - read context word into struct
4698 * @src_ctx: the context structure to read from
4699 * @dest_ctx: the context to be written to
4700 * @ce_info: a description of the struct to be filled
4703 ice_read_word(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info)
4705 u16 dest_word, mask;
4710 /* prepare the bits and mask */
4711 shift_width = ce_info->lsb % 8;
4712 mask = BIT(ce_info->width) - 1;
4714 /* shift to correct alignment */
4715 mask <<= shift_width;
4717 /* get the current bits from the src bit string */
4718 src = src_ctx + (ce_info->lsb / 8);
4720 ice_memcpy(&src_word, src, sizeof(src_word), ICE_DMA_TO_NONDMA);
4722 /* the data in the memory is stored as little endian so mask it
4725 src_word &= ~(CPU_TO_LE16(mask));
4727 /* get the data back into host order before shifting */
4728 dest_word = LE16_TO_CPU(src_word);
4730 dest_word >>= shift_width;
4732 /* get the address from the struct field */
4733 target = dest_ctx + ce_info->offset;
4735 /* put it back in the struct */
4736 ice_memcpy(target, &dest_word, sizeof(dest_word), ICE_NONDMA_TO_DMA);
4740 * ice_read_dword - read context dword into struct
4741 * @src_ctx: the context structure to read from
4742 * @dest_ctx: the context to be written to
4743 * @ce_info: a description of the struct to be filled
4746 ice_read_dword(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info)
4748 u32 dest_dword, mask;
4753 /* prepare the bits and mask */
4754 shift_width = ce_info->lsb % 8;
4756 /* if the field width is exactly 32 on an x86 machine, then the shift
4757 * operation will not work because the SHL instructions count is masked
4758 * to 5 bits so the shift will do nothing
4760 if (ce_info->width < 32)
4761 mask = BIT(ce_info->width) - 1;
4765 /* shift to correct alignment */
4766 mask <<= shift_width;
4768 /* get the current bits from the src bit string */
4769 src = src_ctx + (ce_info->lsb / 8);
4771 ice_memcpy(&src_dword, src, sizeof(src_dword), ICE_DMA_TO_NONDMA);
4773 /* the data in the memory is stored as little endian so mask it
4776 src_dword &= ~(CPU_TO_LE32(mask));
4778 /* get the data back into host order before shifting */
4779 dest_dword = LE32_TO_CPU(src_dword);
4781 dest_dword >>= shift_width;
4783 /* get the address from the struct field */
4784 target = dest_ctx + ce_info->offset;
4786 /* put it back in the struct */
4787 ice_memcpy(target, &dest_dword, sizeof(dest_dword), ICE_NONDMA_TO_DMA);
4791 * ice_read_qword - read context qword into struct
4792 * @src_ctx: the context structure to read from
4793 * @dest_ctx: the context to be written to
4794 * @ce_info: a description of the struct to be filled
4797 ice_read_qword(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info)
4799 u64 dest_qword, mask;
4804 /* prepare the bits and mask */
4805 shift_width = ce_info->lsb % 8;
4807 /* if the field width is exactly 64 on an x86 machine, then the shift
4808 * operation will not work because the SHL instructions count is masked
4809 * to 6 bits so the shift will do nothing
4811 if (ce_info->width < 64)
4812 mask = BIT_ULL(ce_info->width) - 1;
4816 /* shift to correct alignment */
4817 mask <<= shift_width;
4819 /* get the current bits from the src bit string */
4820 src = src_ctx + (ce_info->lsb / 8);
4822 ice_memcpy(&src_qword, src, sizeof(src_qword), ICE_DMA_TO_NONDMA);
4824 /* the data in the memory is stored as little endian so mask it
4827 src_qword &= ~(CPU_TO_LE64(mask));
4829 /* get the data back into host order before shifting */
4830 dest_qword = LE64_TO_CPU(src_qword);
4832 dest_qword >>= shift_width;
4834 /* get the address from the struct field */
4835 target = dest_ctx + ce_info->offset;
4837 /* put it back in the struct */
4838 ice_memcpy(target, &dest_qword, sizeof(dest_qword), ICE_NONDMA_TO_DMA);
4842 * ice_get_ctx - extract context bits from a packed structure
4843 * @src_ctx: pointer to a generic packed context structure
4844 * @dest_ctx: pointer to a generic non-packed context structure
4845 * @ce_info: a description of the structure to be read from
4848 ice_get_ctx(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info)
4852 for (f = 0; ce_info[f].width; f++) {
4853 switch (ce_info[f].size_of) {
4855 ice_read_byte(src_ctx, dest_ctx, &ce_info[f]);
4858 ice_read_word(src_ctx, dest_ctx, &ce_info[f]);
4861 ice_read_dword(src_ctx, dest_ctx, &ce_info[f]);
4864 ice_read_qword(src_ctx, dest_ctx, &ce_info[f]);
4867 /* nothing to do, just keep going */
4876 * ice_get_lan_q_ctx - get the LAN queue context for the given VSI and TC
4877 * @hw: pointer to the HW struct
4878 * @vsi_handle: software VSI handle
4880 * @q_handle: software queue handle
4883 ice_get_lan_q_ctx(struct ice_hw *hw, u16 vsi_handle, u8 tc, u16 q_handle)
4885 struct ice_vsi_ctx *vsi;
4886 struct ice_q_ctx *q_ctx;
4888 vsi = ice_get_vsi_ctx(hw, vsi_handle);
4891 if (q_handle >= vsi->num_lan_q_entries[tc])
4893 if (!vsi->lan_q_ctx[tc])
4895 q_ctx = vsi->lan_q_ctx[tc];
4896 return &q_ctx[q_handle];
4901 * @pi: port information structure
4902 * @vsi_handle: software VSI handle
4904 * @q_handle: software queue handle
4905 * @num_qgrps: Number of added queue groups
4906 * @buf: list of queue groups to be added
4907 * @buf_size: size of buffer for indirect command
4908 * @cd: pointer to command details structure or NULL
4910 * This function adds one LAN queue
4913 ice_ena_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u16 q_handle,
4914 u8 num_qgrps, struct ice_aqc_add_tx_qgrp *buf, u16 buf_size,
4915 struct ice_sq_cd *cd)
4917 struct ice_aqc_txsched_elem_data node = { 0 };
4918 struct ice_sched_node *parent;
4919 struct ice_q_ctx *q_ctx;
4920 enum ice_status status;
4923 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY)
4926 if (num_qgrps > 1 || buf->num_txqs > 1)
4927 return ICE_ERR_MAX_LIMIT;
4931 if (!ice_is_vsi_valid(hw, vsi_handle))
4932 return ICE_ERR_PARAM;
4934 ice_acquire_lock(&pi->sched_lock);
4936 q_ctx = ice_get_lan_q_ctx(hw, vsi_handle, tc, q_handle);
4938 ice_debug(hw, ICE_DBG_SCHED, "Enaq: invalid queue handle %d\n",
4940 status = ICE_ERR_PARAM;
4944 /* find a parent node */
4945 parent = ice_sched_get_free_qparent(pi, vsi_handle, tc,
4946 ICE_SCHED_NODE_OWNER_LAN);
4948 status = ICE_ERR_PARAM;
4952 buf->parent_teid = parent->info.node_teid;
4953 node.parent_teid = parent->info.node_teid;
4954 /* Mark that the values in the "generic" section as valid. The default
4955 * value in the "generic" section is zero. This means that :
4956 * - Scheduling mode is Bytes Per Second (BPS), indicated by Bit 0.
4957 * - 0 priority among siblings, indicated by Bit 1-3.
4958 * - WFQ, indicated by Bit 4.
4959 * - 0 Adjustment value is used in PSM credit update flow, indicated by
4961 * - Bit 7 is reserved.
4962 * Without setting the generic section as valid in valid_sections, the
4963 * Admin queue command will fail with error code ICE_AQ_RC_EINVAL.
4965 buf->txqs[0].info.valid_sections =
4966 ICE_AQC_ELEM_VALID_GENERIC | ICE_AQC_ELEM_VALID_CIR |
4967 ICE_AQC_ELEM_VALID_EIR;
4968 buf->txqs[0].info.generic = 0;
4969 buf->txqs[0].info.cir_bw.bw_profile_idx =
4970 CPU_TO_LE16(ICE_SCHED_DFLT_RL_PROF_ID);
4971 buf->txqs[0].info.cir_bw.bw_alloc =
4972 CPU_TO_LE16(ICE_SCHED_DFLT_BW_WT);
4973 buf->txqs[0].info.eir_bw.bw_profile_idx =
4974 CPU_TO_LE16(ICE_SCHED_DFLT_RL_PROF_ID);
4975 buf->txqs[0].info.eir_bw.bw_alloc =
4976 CPU_TO_LE16(ICE_SCHED_DFLT_BW_WT);
4978 /* add the LAN queue */
4979 status = ice_aq_add_lan_txq(hw, num_qgrps, buf, buf_size, cd);
4980 if (status != ICE_SUCCESS) {
4981 ice_debug(hw, ICE_DBG_SCHED, "enable queue %d failed %d\n",
4982 LE16_TO_CPU(buf->txqs[0].txq_id),
4983 hw->adminq.sq_last_status);
4987 node.node_teid = buf->txqs[0].q_teid;
4988 node.data.elem_type = ICE_AQC_ELEM_TYPE_LEAF;
4989 q_ctx->q_handle = q_handle;
4990 q_ctx->q_teid = LE32_TO_CPU(node.node_teid);
4992 /* add a leaf node into scheduler tree queue layer */
4993 status = ice_sched_add_node(pi, hw->num_tx_sched_layers - 1, &node);
4995 status = ice_sched_replay_q_bw(pi, q_ctx);
4998 ice_release_lock(&pi->sched_lock);
5004 * @pi: port information structure
5005 * @vsi_handle: software VSI handle
5007 * @num_queues: number of queues
5008 * @q_handles: pointer to software queue handle array
5009 * @q_ids: pointer to the q_id array
5010 * @q_teids: pointer to queue node teids
5011 * @rst_src: if called due to reset, specifies the reset source
5012 * @vmvf_num: the relative VM or VF number that is undergoing the reset
5013 * @cd: pointer to command details structure or NULL
5015 * This function removes queues and their corresponding nodes in SW DB
5018 ice_dis_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u8 num_queues,
5019 u16 *q_handles, u16 *q_ids, u32 *q_teids,
5020 enum ice_disq_rst_src rst_src, u16 vmvf_num,
5021 struct ice_sq_cd *cd)
5023 enum ice_status status = ICE_ERR_DOES_NOT_EXIST;
5024 struct ice_aqc_dis_txq_item *qg_list;
5025 struct ice_q_ctx *q_ctx;
5029 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY)
5035 /* if queue is disabled already yet the disable queue command
5036 * has to be sent to complete the VF reset, then call
5037 * ice_aq_dis_lan_txq without any queue information
5040 return ice_aq_dis_lan_txq(hw, 0, NULL, 0, rst_src,
5045 buf_size = ice_struct_size(qg_list, q_id, 1);
5046 qg_list = (struct ice_aqc_dis_txq_item *)ice_malloc(hw, buf_size);
5048 return ICE_ERR_NO_MEMORY;
5050 ice_acquire_lock(&pi->sched_lock);
5052 for (i = 0; i < num_queues; i++) {
5053 struct ice_sched_node *node;
5055 node = ice_sched_find_node_by_teid(pi->root, q_teids[i]);
5058 q_ctx = ice_get_lan_q_ctx(hw, vsi_handle, tc, q_handles[i]);
5060 ice_debug(hw, ICE_DBG_SCHED, "invalid queue handle%d\n",
5064 if (q_ctx->q_handle != q_handles[i]) {
5065 ice_debug(hw, ICE_DBG_SCHED, "Err:handles %d %d\n",
5066 q_ctx->q_handle, q_handles[i]);
5069 qg_list->parent_teid = node->info.parent_teid;
5070 qg_list->num_qs = 1;
5071 qg_list->q_id[0] = CPU_TO_LE16(q_ids[i]);
5072 status = ice_aq_dis_lan_txq(hw, 1, qg_list, buf_size, rst_src,
5075 if (status != ICE_SUCCESS)
5077 ice_free_sched_node(pi, node);
5078 q_ctx->q_handle = ICE_INVAL_Q_HANDLE;
5080 ice_release_lock(&pi->sched_lock);
5081 ice_free(hw, qg_list);
5086 * ice_cfg_vsi_qs - configure the new/existing VSI queues
5087 * @pi: port information structure
5088 * @vsi_handle: software VSI handle
5089 * @tc_bitmap: TC bitmap
5090 * @maxqs: max queues array per TC
5091 * @owner: LAN or RDMA
5093 * This function adds/updates the VSI queues per TC.
5095 static enum ice_status
5096 ice_cfg_vsi_qs(struct ice_port_info *pi, u16 vsi_handle, u16 tc_bitmap,
5097 u16 *maxqs, u8 owner)
5099 enum ice_status status = ICE_SUCCESS;
5102 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY)
5105 if (!ice_is_vsi_valid(pi->hw, vsi_handle))
5106 return ICE_ERR_PARAM;
5108 ice_acquire_lock(&pi->sched_lock);
5110 ice_for_each_traffic_class(i) {
5111 /* configuration is possible only if TC node is present */
5112 if (!ice_sched_get_tc_node(pi, i))
5115 status = ice_sched_cfg_vsi(pi, vsi_handle, i, maxqs[i], owner,
5116 ice_is_tc_ena(tc_bitmap, i));
5121 ice_release_lock(&pi->sched_lock);
5126 * ice_cfg_vsi_lan - configure VSI LAN queues
5127 * @pi: port information structure
5128 * @vsi_handle: software VSI handle
5129 * @tc_bitmap: TC bitmap
5130 * @max_lanqs: max LAN queues array per TC
5132 * This function adds/updates the VSI LAN queues per TC.
5135 ice_cfg_vsi_lan(struct ice_port_info *pi, u16 vsi_handle, u16 tc_bitmap,
5138 return ice_cfg_vsi_qs(pi, vsi_handle, tc_bitmap, max_lanqs,
5139 ICE_SCHED_NODE_OWNER_LAN);
5143 * ice_is_main_vsi - checks whether the VSI is main VSI
5144 * @hw: pointer to the HW struct
5145 * @vsi_handle: VSI handle
5147 * Checks whether the VSI is the main VSI (the first PF VSI created on
5150 static bool ice_is_main_vsi(struct ice_hw *hw, u16 vsi_handle)
5152 return vsi_handle == ICE_MAIN_VSI_HANDLE && hw->vsi_ctx[vsi_handle];
5156 * ice_replay_pre_init - replay pre initialization
5157 * @hw: pointer to the HW struct
5158 * @sw: pointer to switch info struct for which function initializes filters
5160 * Initializes required config data for VSI, FD, ACL, and RSS before replay.
5163 ice_replay_pre_init(struct ice_hw *hw, struct ice_switch_info *sw)
5165 enum ice_status status;
5168 /* Delete old entries from replay filter list head if there is any */
5169 ice_rm_sw_replay_rule_info(hw, sw);
5170 /* In start of replay, move entries into replay_rules list, it
5171 * will allow adding rules entries back to filt_rules list,
5172 * which is operational list.
5174 for (i = 0; i < ICE_MAX_NUM_RECIPES; i++)
5175 LIST_REPLACE_INIT(&sw->recp_list[i].filt_rules,
5176 &sw->recp_list[i].filt_replay_rules);
5177 ice_sched_replay_agg_vsi_preinit(hw);
5179 status = ice_sched_replay_root_node_bw(hw->port_info);
5183 return ice_sched_replay_tc_node_bw(hw->port_info);
5187 * ice_replay_vsi - replay VSI configuration
5188 * @hw: pointer to the HW struct
5189 * @vsi_handle: driver VSI handle
5191 * Restore all VSI configuration after reset. It is required to call this
5192 * function with main VSI first.
5194 enum ice_status ice_replay_vsi(struct ice_hw *hw, u16 vsi_handle)
5196 struct ice_switch_info *sw = hw->switch_info;
5197 struct ice_port_info *pi = hw->port_info;
5198 enum ice_status status;
5200 if (!ice_is_vsi_valid(hw, vsi_handle))
5201 return ICE_ERR_PARAM;
5203 /* Replay pre-initialization if there is any */
5204 if (ice_is_main_vsi(hw, vsi_handle)) {
5205 status = ice_replay_pre_init(hw, sw);
5209 /* Replay per VSI all RSS configurations */
5210 status = ice_replay_rss_cfg(hw, vsi_handle);
5213 /* Replay per VSI all filters */
5214 status = ice_replay_vsi_all_fltr(hw, pi, vsi_handle);
5216 status = ice_replay_vsi_agg(hw, vsi_handle);
5221 * ice_replay_post - post replay configuration cleanup
5222 * @hw: pointer to the HW struct
5224 * Post replay cleanup.
5226 void ice_replay_post(struct ice_hw *hw)
5228 /* Delete old entries from replay filter list head */
5229 ice_rm_all_sw_replay_rule_info(hw);
5230 ice_sched_replay_agg(hw);
5234 * ice_stat_update40 - read 40 bit stat from the chip and update stat values
5235 * @hw: ptr to the hardware info
5236 * @reg: offset of 64 bit HW register to read from
5237 * @prev_stat_loaded: bool to specify if previous stats are loaded
5238 * @prev_stat: ptr to previous loaded stat value
5239 * @cur_stat: ptr to current stat value
5242 ice_stat_update40(struct ice_hw *hw, u32 reg, bool prev_stat_loaded,
5243 u64 *prev_stat, u64 *cur_stat)
5245 u64 new_data = rd64(hw, reg) & (BIT_ULL(40) - 1);
5247 /* device stats are not reset at PFR, they likely will not be zeroed
5248 * when the driver starts. Thus, save the value from the first read
5249 * without adding to the statistic value so that we report stats which
5250 * count up from zero.
5252 if (!prev_stat_loaded) {
5253 *prev_stat = new_data;
5257 /* Calculate the difference between the new and old values, and then
5258 * add it to the software stat value.
5260 if (new_data >= *prev_stat)
5261 *cur_stat += new_data - *prev_stat;
5263 /* to manage the potential roll-over */
5264 *cur_stat += (new_data + BIT_ULL(40)) - *prev_stat;
5266 /* Update the previously stored value to prepare for next read */
5267 *prev_stat = new_data;
5271 * ice_stat_update32 - read 32 bit stat from the chip and update stat values
5272 * @hw: ptr to the hardware info
5273 * @reg: offset of HW register to read from
5274 * @prev_stat_loaded: bool to specify if previous stats are loaded
5275 * @prev_stat: ptr to previous loaded stat value
5276 * @cur_stat: ptr to current stat value
5279 ice_stat_update32(struct ice_hw *hw, u32 reg, bool prev_stat_loaded,
5280 u64 *prev_stat, u64 *cur_stat)
5284 new_data = rd32(hw, reg);
5286 /* device stats are not reset at PFR, they likely will not be zeroed
5287 * when the driver starts. Thus, save the value from the first read
5288 * without adding to the statistic value so that we report stats which
5289 * count up from zero.
5291 if (!prev_stat_loaded) {
5292 *prev_stat = new_data;
5296 /* Calculate the difference between the new and old values, and then
5297 * add it to the software stat value.
5299 if (new_data >= *prev_stat)
5300 *cur_stat += new_data - *prev_stat;
5302 /* to manage the potential roll-over */
5303 *cur_stat += (new_data + BIT_ULL(32)) - *prev_stat;
5305 /* Update the previously stored value to prepare for next read */
5306 *prev_stat = new_data;
5310 * ice_stat_update_repc - read GLV_REPC stats from chip and update stat values
5311 * @hw: ptr to the hardware info
5312 * @vsi_handle: VSI handle
5313 * @prev_stat_loaded: bool to specify if the previous stat values are loaded
5314 * @cur_stats: ptr to current stats structure
5316 * The GLV_REPC statistic register actually tracks two 16bit statistics, and
5317 * thus cannot be read using the normal ice_stat_update32 function.
5319 * Read the GLV_REPC register associated with the given VSI, and update the
5320 * rx_no_desc and rx_error values in the ice_eth_stats structure.
5322 * Because the statistics in GLV_REPC stick at 0xFFFF, the register must be
5323 * cleared each time it's read.
5325 * Note that the GLV_RDPC register also counts the causes that would trigger
5326 * GLV_REPC. However, it does not give the finer grained detail about why the
5327 * packets are being dropped. The GLV_REPC values can be used to distinguish
5328 * whether Rx packets are dropped due to errors or due to no available
5332 ice_stat_update_repc(struct ice_hw *hw, u16 vsi_handle, bool prev_stat_loaded,
5333 struct ice_eth_stats *cur_stats)
5335 u16 vsi_num, no_desc, error_cnt;
5338 if (!ice_is_vsi_valid(hw, vsi_handle))
5341 vsi_num = ice_get_hw_vsi_num(hw, vsi_handle);
5343 /* If we haven't loaded stats yet, just clear the current value */
5344 if (!prev_stat_loaded) {
5345 wr32(hw, GLV_REPC(vsi_num), 0);
5349 repc = rd32(hw, GLV_REPC(vsi_num));
5350 no_desc = (repc & GLV_REPC_NO_DESC_CNT_M) >> GLV_REPC_NO_DESC_CNT_S;
5351 error_cnt = (repc & GLV_REPC_ERROR_CNT_M) >> GLV_REPC_ERROR_CNT_S;
5353 /* Clear the count by writing to the stats register */
5354 wr32(hw, GLV_REPC(vsi_num), 0);
5356 cur_stats->rx_no_desc += no_desc;
5357 cur_stats->rx_errors += error_cnt;
5361 * ice_sched_query_elem - query element information from HW
5362 * @hw: pointer to the HW struct
5363 * @node_teid: node TEID to be queried
5364 * @buf: buffer to element information
5366 * This function queries HW element information
5369 ice_sched_query_elem(struct ice_hw *hw, u32 node_teid,
5370 struct ice_aqc_txsched_elem_data *buf)
5372 u16 buf_size, num_elem_ret = 0;
5373 enum ice_status status;
5375 buf_size = sizeof(*buf);
5376 ice_memset(buf, 0, buf_size, ICE_NONDMA_MEM);
5377 buf->node_teid = CPU_TO_LE32(node_teid);
5378 status = ice_aq_query_sched_elems(hw, 1, buf, buf_size, &num_elem_ret,
5380 if (status != ICE_SUCCESS || num_elem_ret != 1)
5381 ice_debug(hw, ICE_DBG_SCHED, "query element failed\n");
5386 * ice_get_fw_mode - returns FW mode
5387 * @hw: pointer to the HW struct
5389 enum ice_fw_modes ice_get_fw_mode(struct ice_hw *hw)
5391 #define ICE_FW_MODE_DBG_M BIT(0)
5392 #define ICE_FW_MODE_REC_M BIT(1)
5393 #define ICE_FW_MODE_ROLLBACK_M BIT(2)
5396 /* check the current FW mode */
5397 fw_mode = rd32(hw, GL_MNG_FWSM) & GL_MNG_FWSM_FW_MODES_M;
5399 if (fw_mode & ICE_FW_MODE_DBG_M)
5400 return ICE_FW_MODE_DBG;
5401 else if (fw_mode & ICE_FW_MODE_REC_M)
5402 return ICE_FW_MODE_REC;
5403 else if (fw_mode & ICE_FW_MODE_ROLLBACK_M)
5404 return ICE_FW_MODE_ROLLBACK;
5406 return ICE_FW_MODE_NORMAL;
5411 * @hw: pointer to the hw struct
5412 * @topo_addr: topology address for a device to communicate with
5413 * @bus_addr: 7-bit I2C bus address
5414 * @addr: I2C memory address (I2C offset) with up to 16 bits
5415 * @params: I2C parameters: bit [7] - Repeated start, bits [6:5] data offset size,
5416 * bit [4] - I2C address type, bits [3:0] - data size to read (0-16 bytes)
5417 * @data: pointer to data (0 to 16 bytes) to be read from the I2C device
5418 * @cd: pointer to command details structure or NULL
5423 ice_aq_read_i2c(struct ice_hw *hw, struct ice_aqc_link_topo_addr topo_addr,
5424 u16 bus_addr, __le16 addr, u8 params, u8 *data,
5425 struct ice_sq_cd *cd)
5427 struct ice_aq_desc desc = { 0 };
5428 struct ice_aqc_i2c *cmd;
5429 enum ice_status status;
5432 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_read_i2c);
5433 cmd = &desc.params.read_write_i2c;
5436 return ICE_ERR_PARAM;
5438 data_size = (params & ICE_AQC_I2C_DATA_SIZE_M) >> ICE_AQC_I2C_DATA_SIZE_S;
5440 cmd->i2c_bus_addr = CPU_TO_LE16(bus_addr);
5441 cmd->topo_addr = topo_addr;
5442 cmd->i2c_params = params;
5443 cmd->i2c_addr = addr;
5445 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
5447 struct ice_aqc_read_i2c_resp *resp;
5450 resp = &desc.params.read_i2c_resp;
5451 for (i = 0; i < data_size; i++) {
5452 *data = resp->i2c_data[i];
5462 * @hw: pointer to the hw struct
5463 * @topo_addr: topology address for a device to communicate with
5464 * @bus_addr: 7-bit I2C bus address
5465 * @addr: I2C memory address (I2C offset) with up to 16 bits
5466 * @params: I2C parameters: bit [4] - I2C address type, bits [3:0] - data size to write (0-7 bytes)
5467 * @data: pointer to data (0 to 4 bytes) to be written to the I2C device
5468 * @cd: pointer to command details structure or NULL
5470 * Write I2C (0x06E3)
5473 ice_aq_write_i2c(struct ice_hw *hw, struct ice_aqc_link_topo_addr topo_addr,
5474 u16 bus_addr, __le16 addr, u8 params, u8 *data,
5475 struct ice_sq_cd *cd)
5477 struct ice_aq_desc desc = { 0 };
5478 struct ice_aqc_i2c *cmd;
5481 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_write_i2c);
5482 cmd = &desc.params.read_write_i2c;
5484 data_size = (params & ICE_AQC_I2C_DATA_SIZE_M) >> ICE_AQC_I2C_DATA_SIZE_S;
5486 /* data_size limited to 4 */
5488 return ICE_ERR_PARAM;
5490 cmd->i2c_bus_addr = CPU_TO_LE16(bus_addr);
5491 cmd->topo_addr = topo_addr;
5492 cmd->i2c_params = params;
5493 cmd->i2c_addr = addr;
5495 for (i = 0; i < data_size; i++) {
5496 cmd->i2c_data[i] = *data;
5500 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
5504 * ice_aq_set_driver_param - Set driver parameter to share via firmware
5505 * @hw: pointer to the HW struct
5506 * @idx: parameter index to set
5507 * @value: the value to set the parameter to
5508 * @cd: pointer to command details structure or NULL
5510 * Set the value of one of the software defined parameters. All PFs connected
5511 * to this device can read the value using ice_aq_get_driver_param.
5513 * Note that firmware provides no synchronization or locking, and will not
5514 * save the parameter value during a device reset. It is expected that
5515 * a single PF will write the parameter value, while all other PFs will only
5519 ice_aq_set_driver_param(struct ice_hw *hw, enum ice_aqc_driver_params idx,
5520 u32 value, struct ice_sq_cd *cd)
5522 struct ice_aqc_driver_shared_params *cmd;
5523 struct ice_aq_desc desc;
5525 if (idx >= ICE_AQC_DRIVER_PARAM_MAX)
5526 return ICE_ERR_OUT_OF_RANGE;
5528 cmd = &desc.params.drv_shared_params;
5530 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_driver_shared_params);
5532 cmd->set_or_get_op = ICE_AQC_DRIVER_PARAM_SET;
5533 cmd->param_indx = idx;
5534 cmd->param_val = CPU_TO_LE32(value);
5536 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
5540 * ice_aq_get_driver_param - Get driver parameter shared via firmware
5541 * @hw: pointer to the HW struct
5542 * @idx: parameter index to set
5543 * @value: storage to return the shared parameter
5544 * @cd: pointer to command details structure or NULL
5546 * Get the value of one of the software defined parameters.
5548 * Note that firmware provides no synchronization or locking. It is expected
5549 * that only a single PF will write a given parameter.
5552 ice_aq_get_driver_param(struct ice_hw *hw, enum ice_aqc_driver_params idx,
5553 u32 *value, struct ice_sq_cd *cd)
5555 struct ice_aqc_driver_shared_params *cmd;
5556 struct ice_aq_desc desc;
5557 enum ice_status status;
5559 if (idx >= ICE_AQC_DRIVER_PARAM_MAX)
5560 return ICE_ERR_OUT_OF_RANGE;
5562 cmd = &desc.params.drv_shared_params;
5564 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_driver_shared_params);
5566 cmd->set_or_get_op = ICE_AQC_DRIVER_PARAM_GET;
5567 cmd->param_indx = idx;
5569 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
5573 *value = LE32_TO_CPU(cmd->param_val);
5580 * @hw: pointer to the hw struct
5581 * @gpio_ctrl_handle: GPIO controller node handle
5582 * @pin_idx: IO Number of the GPIO that needs to be set
5583 * @value: SW provide IO value to set in the LSB
5584 * @cd: pointer to command details structure or NULL
5586 * Sends 0x06EC AQ command to set the GPIO pin state that's part of the topology
5589 ice_aq_set_gpio(struct ice_hw *hw, u16 gpio_ctrl_handle, u8 pin_idx, bool value,
5590 struct ice_sq_cd *cd)
5592 struct ice_aqc_gpio *cmd;
5593 struct ice_aq_desc desc;
5595 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_gpio);
5596 cmd = &desc.params.read_write_gpio;
5597 cmd->gpio_ctrl_handle = gpio_ctrl_handle;
5598 cmd->gpio_num = pin_idx;
5599 cmd->gpio_val = value ? 1 : 0;
5601 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
5606 * @hw: pointer to the hw struct
5607 * @gpio_ctrl_handle: GPIO controller node handle
5608 * @pin_idx: IO Number of the GPIO that needs to be set
5609 * @value: IO value read
5610 * @cd: pointer to command details structure or NULL
5612 * Sends 0x06ED AQ command to get the value of a GPIO signal which is part of
5616 ice_aq_get_gpio(struct ice_hw *hw, u16 gpio_ctrl_handle, u8 pin_idx,
5617 bool *value, struct ice_sq_cd *cd)
5619 struct ice_aqc_gpio *cmd;
5620 struct ice_aq_desc desc;
5621 enum ice_status status;
5623 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_gpio);
5624 cmd = &desc.params.read_write_gpio;
5625 cmd->gpio_ctrl_handle = gpio_ctrl_handle;
5626 cmd->gpio_num = pin_idx;
5628 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
5632 *value = !!cmd->gpio_val;
5637 * ice_fw_supports_link_override
5638 * @hw: pointer to the hardware structure
5640 * Checks if the firmware supports link override
5642 bool ice_fw_supports_link_override(struct ice_hw *hw)
5644 if (hw->api_maj_ver == ICE_FW_API_LINK_OVERRIDE_MAJ) {
5645 if (hw->api_min_ver > ICE_FW_API_LINK_OVERRIDE_MIN)
5647 if (hw->api_min_ver == ICE_FW_API_LINK_OVERRIDE_MIN &&
5648 hw->api_patch >= ICE_FW_API_LINK_OVERRIDE_PATCH)
5650 } else if (hw->api_maj_ver > ICE_FW_API_LINK_OVERRIDE_MAJ) {
5658 * ice_get_link_default_override
5659 * @ldo: pointer to the link default override struct
5660 * @pi: pointer to the port info struct
5662 * Gets the link default override for a port
5665 ice_get_link_default_override(struct ice_link_default_override_tlv *ldo,
5666 struct ice_port_info *pi)
5668 u16 i, tlv, tlv_len, tlv_start, buf, offset;
5669 struct ice_hw *hw = pi->hw;
5670 enum ice_status status;
5672 status = ice_get_pfa_module_tlv(hw, &tlv, &tlv_len,
5673 ICE_SR_LINK_DEFAULT_OVERRIDE_PTR);
5675 ice_debug(hw, ICE_DBG_INIT, "Failed to read link override TLV.\n");
5679 /* Each port has its own config; calculate for our port */
5680 tlv_start = tlv + pi->lport * ICE_SR_PFA_LINK_OVERRIDE_WORDS +
5681 ICE_SR_PFA_LINK_OVERRIDE_OFFSET;
5683 /* link options first */
5684 status = ice_read_sr_word(hw, tlv_start, &buf);
5686 ice_debug(hw, ICE_DBG_INIT, "Failed to read override link options.\n");
5689 ldo->options = buf & ICE_LINK_OVERRIDE_OPT_M;
5690 ldo->phy_config = (buf & ICE_LINK_OVERRIDE_PHY_CFG_M) >>
5691 ICE_LINK_OVERRIDE_PHY_CFG_S;
5693 /* link PHY config */
5694 offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_FEC_OFFSET;
5695 status = ice_read_sr_word(hw, offset, &buf);
5697 ice_debug(hw, ICE_DBG_INIT, "Failed to read override phy config.\n");
5700 ldo->fec_options = buf & ICE_LINK_OVERRIDE_FEC_OPT_M;
5703 offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_PHY_OFFSET;
5704 for (i = 0; i < ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS; i++) {
5705 status = ice_read_sr_word(hw, (offset + i), &buf);
5707 ice_debug(hw, ICE_DBG_INIT, "Failed to read override link options.\n");
5710 /* shift 16 bits at a time to fill 64 bits */
5711 ldo->phy_type_low |= ((u64)buf << (i * 16));
5714 /* PHY types high */
5715 offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_PHY_OFFSET +
5716 ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS;
5717 for (i = 0; i < ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS; i++) {
5718 status = ice_read_sr_word(hw, (offset + i), &buf);
5720 ice_debug(hw, ICE_DBG_INIT, "Failed to read override link options.\n");
5723 /* shift 16 bits at a time to fill 64 bits */
5724 ldo->phy_type_high |= ((u64)buf << (i * 16));
5731 * ice_is_phy_caps_an_enabled - check if PHY capabilities autoneg is enabled
5732 * @caps: get PHY capability data
5734 bool ice_is_phy_caps_an_enabled(struct ice_aqc_get_phy_caps_data *caps)
5736 if (caps->caps & ICE_AQC_PHY_AN_MODE ||
5737 caps->low_power_ctrl_an & (ICE_AQC_PHY_AN_EN_CLAUSE28 |
5738 ICE_AQC_PHY_AN_EN_CLAUSE73 |
5739 ICE_AQC_PHY_AN_EN_CLAUSE37))
5746 * ice_aq_set_lldp_mib - Set the LLDP MIB
5747 * @hw: pointer to the HW struct
5748 * @mib_type: Local, Remote or both Local and Remote MIBs
5749 * @buf: pointer to the caller-supplied buffer to store the MIB block
5750 * @buf_size: size of the buffer (in bytes)
5751 * @cd: pointer to command details structure or NULL
5753 * Set the LLDP MIB. (0x0A08)
5756 ice_aq_set_lldp_mib(struct ice_hw *hw, u8 mib_type, void *buf, u16 buf_size,
5757 struct ice_sq_cd *cd)
5759 struct ice_aqc_lldp_set_local_mib *cmd;
5760 struct ice_aq_desc desc;
5762 cmd = &desc.params.lldp_set_mib;
5764 if (buf_size == 0 || !buf)
5765 return ICE_ERR_PARAM;
5767 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_lldp_set_local_mib);
5769 desc.flags |= CPU_TO_LE16((u16)ICE_AQ_FLAG_RD);
5770 desc.datalen = CPU_TO_LE16(buf_size);
5772 cmd->type = mib_type;
5773 cmd->length = CPU_TO_LE16(buf_size);
5775 return ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);
5779 * ice_fw_supports_lldp_fltr_ctrl - check NVM version supports lldp_fltr_ctrl
5780 * @hw: pointer to HW struct
5782 bool ice_fw_supports_lldp_fltr_ctrl(struct ice_hw *hw)
5784 if (hw->mac_type != ICE_MAC_E810)
5787 if (hw->api_maj_ver == ICE_FW_API_LLDP_FLTR_MAJ) {
5788 if (hw->api_min_ver > ICE_FW_API_LLDP_FLTR_MIN)
5790 if (hw->api_min_ver == ICE_FW_API_LLDP_FLTR_MIN &&
5791 hw->api_patch >= ICE_FW_API_LLDP_FLTR_PATCH)
5793 } else if (hw->api_maj_ver > ICE_FW_API_LLDP_FLTR_MAJ) {
5800 * ice_lldp_fltr_add_remove - add or remove a LLDP Rx switch filter
5801 * @hw: pointer to HW struct
5802 * @vsi_num: absolute HW index for VSI
5803 * @add: boolean for if adding or removing a filter
5806 ice_lldp_fltr_add_remove(struct ice_hw *hw, u16 vsi_num, bool add)
5808 struct ice_aqc_lldp_filter_ctrl *cmd;
5809 struct ice_aq_desc desc;
5811 cmd = &desc.params.lldp_filter_ctrl;
5813 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_lldp_filter_ctrl);
5816 cmd->cmd_flags = ICE_AQC_LLDP_FILTER_ACTION_ADD;
5818 cmd->cmd_flags = ICE_AQC_LLDP_FILTER_ACTION_DELETE;
5820 cmd->vsi_num = CPU_TO_LE16(vsi_num);
5822 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
5826 * ice_fw_supports_report_dflt_cfg
5827 * @hw: pointer to the hardware structure
5829 * Checks if the firmware supports report default configuration
5831 bool ice_fw_supports_report_dflt_cfg(struct ice_hw *hw)
5833 if (hw->api_maj_ver == ICE_FW_API_REPORT_DFLT_CFG_MAJ) {
5834 if (hw->api_min_ver > ICE_FW_API_REPORT_DFLT_CFG_MIN)
5836 if (hw->api_min_ver == ICE_FW_API_REPORT_DFLT_CFG_MIN &&
5837 hw->api_patch >= ICE_FW_API_REPORT_DFLT_CFG_PATCH)
5839 } else if (hw->api_maj_ver > ICE_FW_API_REPORT_DFLT_CFG_MAJ) {