1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2001-2020 Intel Corporation
5 #include "ice_common.h"
7 #include "ice_adminq_cmd.h"
10 #include "ice_switch.h"
12 #define ICE_PF_RESET_WAIT_COUNT 300
15 * ice_set_mac_type - Sets MAC type
16 * @hw: pointer to the HW structure
18 * This function sets the MAC type of the adapter based on the
19 * vendor ID and device ID stored in the HW structure.
21 static enum ice_status ice_set_mac_type(struct ice_hw *hw)
23 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
25 if (hw->vendor_id != ICE_INTEL_VENDOR_ID)
26 return ICE_ERR_DEVICE_NOT_SUPPORTED;
28 switch (hw->device_id) {
29 case ICE_DEV_ID_E810C_BACKPLANE:
30 case ICE_DEV_ID_E810C_QSFP:
31 case ICE_DEV_ID_E810C_SFP:
32 case ICE_DEV_ID_E810_XXV_BACKPLANE:
33 case ICE_DEV_ID_E810_XXV_QSFP:
34 case ICE_DEV_ID_E810_XXV_SFP:
35 hw->mac_type = ICE_MAC_E810;
37 case ICE_DEV_ID_E822C_10G_BASE_T:
38 case ICE_DEV_ID_E822C_BACKPLANE:
39 case ICE_DEV_ID_E822C_QSFP:
40 case ICE_DEV_ID_E822C_SFP:
41 case ICE_DEV_ID_E822C_SGMII:
42 case ICE_DEV_ID_E822L_10G_BASE_T:
43 case ICE_DEV_ID_E822L_BACKPLANE:
44 case ICE_DEV_ID_E822L_SFP:
45 case ICE_DEV_ID_E822L_SGMII:
46 hw->mac_type = ICE_MAC_GENERIC;
49 hw->mac_type = ICE_MAC_UNKNOWN;
53 ice_debug(hw, ICE_DBG_INIT, "mac_type: %d\n", hw->mac_type);
58 * ice_clear_pf_cfg - Clear PF configuration
59 * @hw: pointer to the hardware structure
61 * Clears any existing PF configuration (VSIs, VSI lists, switch rules, port
62 * configuration, flow director filters, etc.).
64 enum ice_status ice_clear_pf_cfg(struct ice_hw *hw)
66 struct ice_aq_desc desc;
68 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pf_cfg);
70 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
74 * ice_aq_manage_mac_read - manage MAC address read command
75 * @hw: pointer to the HW struct
76 * @buf: a virtual buffer to hold the manage MAC read response
77 * @buf_size: Size of the virtual buffer
78 * @cd: pointer to command details structure or NULL
80 * This function is used to return per PF station MAC address (0x0107).
81 * NOTE: Upon successful completion of this command, MAC address information
82 * is returned in user specified buffer. Please interpret user specified
83 * buffer as "manage_mac_read" response.
84 * Response such as various MAC addresses are stored in HW struct (port.mac)
85 * ice_aq_discover_caps is expected to be called before this function is called.
87 static enum ice_status
88 ice_aq_manage_mac_read(struct ice_hw *hw, void *buf, u16 buf_size,
91 struct ice_aqc_manage_mac_read_resp *resp;
92 struct ice_aqc_manage_mac_read *cmd;
93 struct ice_aq_desc desc;
94 enum ice_status status;
98 cmd = &desc.params.mac_read;
100 if (buf_size < sizeof(*resp))
101 return ICE_ERR_BUF_TOO_SHORT;
103 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_read);
105 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);
109 resp = (struct ice_aqc_manage_mac_read_resp *)buf;
110 flags = LE16_TO_CPU(cmd->flags) & ICE_AQC_MAN_MAC_READ_M;
112 if (!(flags & ICE_AQC_MAN_MAC_LAN_ADDR_VALID)) {
113 ice_debug(hw, ICE_DBG_LAN, "got invalid MAC address\n");
117 /* A single port can report up to two (LAN and WoL) addresses */
118 for (i = 0; i < cmd->num_addr; i++)
119 if (resp[i].addr_type == ICE_AQC_MAN_MAC_ADDR_TYPE_LAN) {
120 ice_memcpy(hw->port_info->mac.lan_addr,
121 resp[i].mac_addr, ETH_ALEN,
123 ice_memcpy(hw->port_info->mac.perm_addr,
125 ETH_ALEN, ICE_DMA_TO_NONDMA);
132 * ice_aq_get_phy_caps - returns PHY capabilities
133 * @pi: port information structure
134 * @qual_mods: report qualified modules
135 * @report_mode: report mode capabilities
136 * @pcaps: structure for PHY capabilities to be filled
137 * @cd: pointer to command details structure or NULL
139 * Returns the various PHY capabilities supported on the Port (0x0600)
142 ice_aq_get_phy_caps(struct ice_port_info *pi, bool qual_mods, u8 report_mode,
143 struct ice_aqc_get_phy_caps_data *pcaps,
144 struct ice_sq_cd *cd)
146 struct ice_aqc_get_phy_caps *cmd;
147 u16 pcaps_size = sizeof(*pcaps);
148 struct ice_aq_desc desc;
149 enum ice_status status;
151 cmd = &desc.params.get_phy;
153 if (!pcaps || (report_mode & ~ICE_AQC_REPORT_MODE_M) || !pi)
154 return ICE_ERR_PARAM;
156 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_phy_caps);
159 cmd->param0 |= CPU_TO_LE16(ICE_AQC_GET_PHY_RQM);
161 cmd->param0 |= CPU_TO_LE16(report_mode);
162 status = ice_aq_send_cmd(pi->hw, &desc, pcaps, pcaps_size, cd);
164 if (status == ICE_SUCCESS && report_mode == ICE_AQC_REPORT_TOPO_CAP) {
165 pi->phy.phy_type_low = LE64_TO_CPU(pcaps->phy_type_low);
166 pi->phy.phy_type_high = LE64_TO_CPU(pcaps->phy_type_high);
173 * ice_aq_get_link_topo_handle - get link topology node return status
174 * @pi: port information structure
175 * @node_type: requested node type
176 * @cd: pointer to command details structure or NULL
178 * Get link topology node return status for specified node type (0x06E0)
180 * Node type cage can be used to determine if cage is present. If AQC
181 * returns error (ENOENT), then no cage present. If no cage present, then
182 * connection type is backplane or BASE-T.
184 static enum ice_status
185 ice_aq_get_link_topo_handle(struct ice_port_info *pi, u8 node_type,
186 struct ice_sq_cd *cd)
188 struct ice_aqc_get_link_topo *cmd;
189 struct ice_aq_desc desc;
191 cmd = &desc.params.get_link_topo;
193 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_topo);
195 cmd->addr.node_type_ctx = (ICE_AQC_LINK_TOPO_NODE_CTX_PORT <<
196 ICE_AQC_LINK_TOPO_NODE_CTX_S);
199 cmd->addr.node_type_ctx |= (ICE_AQC_LINK_TOPO_NODE_TYPE_M & node_type);
201 return ice_aq_send_cmd(pi->hw, &desc, NULL, 0, cd);
205 * ice_is_media_cage_present
206 * @pi: port information structure
208 * Returns true if media cage is present, else false. If no cage, then
209 * media type is backplane or BASE-T.
211 static bool ice_is_media_cage_present(struct ice_port_info *pi)
213 /* Node type cage can be used to determine if cage is present. If AQC
214 * returns error (ENOENT), then no cage present. If no cage present then
215 * connection type is backplane or BASE-T.
217 return !ice_aq_get_link_topo_handle(pi,
218 ICE_AQC_LINK_TOPO_NODE_TYPE_CAGE,
223 * ice_get_media_type - Gets media type
224 * @pi: port information structure
226 static enum ice_media_type ice_get_media_type(struct ice_port_info *pi)
228 struct ice_link_status *hw_link_info;
231 return ICE_MEDIA_UNKNOWN;
233 hw_link_info = &pi->phy.link_info;
234 if (hw_link_info->phy_type_low && hw_link_info->phy_type_high)
235 /* If more than one media type is selected, report unknown */
236 return ICE_MEDIA_UNKNOWN;
238 if (hw_link_info->phy_type_low) {
239 switch (hw_link_info->phy_type_low) {
240 case ICE_PHY_TYPE_LOW_1000BASE_SX:
241 case ICE_PHY_TYPE_LOW_1000BASE_LX:
242 case ICE_PHY_TYPE_LOW_10GBASE_SR:
243 case ICE_PHY_TYPE_LOW_10GBASE_LR:
244 case ICE_PHY_TYPE_LOW_10G_SFI_C2C:
245 case ICE_PHY_TYPE_LOW_25GBASE_SR:
246 case ICE_PHY_TYPE_LOW_25GBASE_LR:
247 case ICE_PHY_TYPE_LOW_40GBASE_SR4:
248 case ICE_PHY_TYPE_LOW_40GBASE_LR4:
249 case ICE_PHY_TYPE_LOW_50GBASE_SR2:
250 case ICE_PHY_TYPE_LOW_50GBASE_LR2:
251 case ICE_PHY_TYPE_LOW_50GBASE_SR:
252 case ICE_PHY_TYPE_LOW_50GBASE_FR:
253 case ICE_PHY_TYPE_LOW_50GBASE_LR:
254 case ICE_PHY_TYPE_LOW_100GBASE_SR4:
255 case ICE_PHY_TYPE_LOW_100GBASE_LR4:
256 case ICE_PHY_TYPE_LOW_100GBASE_SR2:
257 case ICE_PHY_TYPE_LOW_100GBASE_DR:
258 return ICE_MEDIA_FIBER;
259 case ICE_PHY_TYPE_LOW_100BASE_TX:
260 case ICE_PHY_TYPE_LOW_1000BASE_T:
261 case ICE_PHY_TYPE_LOW_2500BASE_T:
262 case ICE_PHY_TYPE_LOW_5GBASE_T:
263 case ICE_PHY_TYPE_LOW_10GBASE_T:
264 case ICE_PHY_TYPE_LOW_25GBASE_T:
265 return ICE_MEDIA_BASET;
266 case ICE_PHY_TYPE_LOW_10G_SFI_DA:
267 case ICE_PHY_TYPE_LOW_25GBASE_CR:
268 case ICE_PHY_TYPE_LOW_25GBASE_CR_S:
269 case ICE_PHY_TYPE_LOW_25GBASE_CR1:
270 case ICE_PHY_TYPE_LOW_40GBASE_CR4:
271 case ICE_PHY_TYPE_LOW_50GBASE_CR2:
272 case ICE_PHY_TYPE_LOW_50GBASE_CP:
273 case ICE_PHY_TYPE_LOW_100GBASE_CR4:
274 case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4:
275 case ICE_PHY_TYPE_LOW_100GBASE_CP2:
277 case ICE_PHY_TYPE_LOW_25G_AUI_C2C:
278 case ICE_PHY_TYPE_LOW_40G_XLAUI:
279 case ICE_PHY_TYPE_LOW_50G_LAUI2:
280 case ICE_PHY_TYPE_LOW_50G_AUI2:
281 case ICE_PHY_TYPE_LOW_50G_AUI1:
282 case ICE_PHY_TYPE_LOW_100G_AUI4:
283 case ICE_PHY_TYPE_LOW_100G_CAUI4:
284 if (ice_is_media_cage_present(pi))
287 case ICE_PHY_TYPE_LOW_1000BASE_KX:
288 case ICE_PHY_TYPE_LOW_2500BASE_KX:
289 case ICE_PHY_TYPE_LOW_2500BASE_X:
290 case ICE_PHY_TYPE_LOW_5GBASE_KR:
291 case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1:
292 case ICE_PHY_TYPE_LOW_25GBASE_KR:
293 case ICE_PHY_TYPE_LOW_25GBASE_KR1:
294 case ICE_PHY_TYPE_LOW_25GBASE_KR_S:
295 case ICE_PHY_TYPE_LOW_40GBASE_KR4:
296 case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4:
297 case ICE_PHY_TYPE_LOW_50GBASE_KR2:
298 case ICE_PHY_TYPE_LOW_100GBASE_KR4:
299 case ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4:
300 return ICE_MEDIA_BACKPLANE;
303 switch (hw_link_info->phy_type_high) {
304 case ICE_PHY_TYPE_HIGH_100G_AUI2:
305 if (ice_is_media_cage_present(pi))
308 case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4:
309 return ICE_MEDIA_BACKPLANE;
312 return ICE_MEDIA_UNKNOWN;
316 * ice_aq_get_link_info
317 * @pi: port information structure
318 * @ena_lse: enable/disable LinkStatusEvent reporting
319 * @link: pointer to link status structure - optional
320 * @cd: pointer to command details structure or NULL
322 * Get Link Status (0x607). Returns the link status of the adapter.
325 ice_aq_get_link_info(struct ice_port_info *pi, bool ena_lse,
326 struct ice_link_status *link, struct ice_sq_cd *cd)
328 struct ice_aqc_get_link_status_data link_data = { 0 };
329 struct ice_aqc_get_link_status *resp;
330 struct ice_link_status *li_old, *li;
331 enum ice_media_type *hw_media_type;
332 struct ice_fc_info *hw_fc_info;
333 bool tx_pause, rx_pause;
334 struct ice_aq_desc desc;
335 enum ice_status status;
340 return ICE_ERR_PARAM;
342 li_old = &pi->phy.link_info_old;
343 hw_media_type = &pi->phy.media_type;
344 li = &pi->phy.link_info;
345 hw_fc_info = &pi->fc;
347 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_status);
348 cmd_flags = (ena_lse) ? ICE_AQ_LSE_ENA : ICE_AQ_LSE_DIS;
349 resp = &desc.params.get_link_status;
350 resp->cmd_flags = CPU_TO_LE16(cmd_flags);
351 resp->lport_num = pi->lport;
353 status = ice_aq_send_cmd(hw, &desc, &link_data, sizeof(link_data), cd);
355 if (status != ICE_SUCCESS)
358 /* save off old link status information */
361 /* update current link status information */
362 li->link_speed = LE16_TO_CPU(link_data.link_speed);
363 li->phy_type_low = LE64_TO_CPU(link_data.phy_type_low);
364 li->phy_type_high = LE64_TO_CPU(link_data.phy_type_high);
365 *hw_media_type = ice_get_media_type(pi);
366 li->link_info = link_data.link_info;
367 li->an_info = link_data.an_info;
368 li->ext_info = link_data.ext_info;
369 li->max_frame_size = LE16_TO_CPU(link_data.max_frame_size);
370 li->fec_info = link_data.cfg & ICE_AQ_FEC_MASK;
371 li->topo_media_conflict = link_data.topo_media_conflict;
372 li->pacing = link_data.cfg & (ICE_AQ_CFG_PACING_M |
373 ICE_AQ_CFG_PACING_TYPE_M);
376 tx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_TX);
377 rx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_RX);
378 if (tx_pause && rx_pause)
379 hw_fc_info->current_mode = ICE_FC_FULL;
381 hw_fc_info->current_mode = ICE_FC_TX_PAUSE;
383 hw_fc_info->current_mode = ICE_FC_RX_PAUSE;
385 hw_fc_info->current_mode = ICE_FC_NONE;
387 li->lse_ena = !!(resp->cmd_flags & CPU_TO_LE16(ICE_AQ_LSE_IS_ENABLED));
389 ice_debug(hw, ICE_DBG_LINK, "link_speed = 0x%x\n", li->link_speed);
390 ice_debug(hw, ICE_DBG_LINK, "phy_type_low = 0x%llx\n",
391 (unsigned long long)li->phy_type_low);
392 ice_debug(hw, ICE_DBG_LINK, "phy_type_high = 0x%llx\n",
393 (unsigned long long)li->phy_type_high);
394 ice_debug(hw, ICE_DBG_LINK, "media_type = 0x%x\n", *hw_media_type);
395 ice_debug(hw, ICE_DBG_LINK, "link_info = 0x%x\n", li->link_info);
396 ice_debug(hw, ICE_DBG_LINK, "an_info = 0x%x\n", li->an_info);
397 ice_debug(hw, ICE_DBG_LINK, "ext_info = 0x%x\n", li->ext_info);
398 ice_debug(hw, ICE_DBG_LINK, "lse_ena = 0x%x\n", li->lse_ena);
399 ice_debug(hw, ICE_DBG_LINK, "max_frame = 0x%x\n", li->max_frame_size);
400 ice_debug(hw, ICE_DBG_LINK, "pacing = 0x%x\n", li->pacing);
402 /* save link status information */
406 /* flag cleared so calling functions don't call AQ again */
407 pi->phy.get_link_info = false;
413 * ice_fill_tx_timer_and_fc_thresh
414 * @hw: pointer to the HW struct
415 * @cmd: pointer to MAC cfg structure
417 * Add Tx timer and FC refresh threshold info to Set MAC Config AQ command
421 ice_fill_tx_timer_and_fc_thresh(struct ice_hw *hw,
422 struct ice_aqc_set_mac_cfg *cmd)
424 u16 fc_thres_val, tx_timer_val;
427 /* We read back the transmit timer and fc threshold value of
428 * LFC. Thus, we will use index =
429 * PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX.
431 * Also, because we are opearating on transmit timer and fc
432 * threshold of LFC, we don't turn on any bit in tx_tmr_priority
434 #define IDX_OF_LFC PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX
436 /* Retrieve the transmit timer */
437 val = rd32(hw, PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(IDX_OF_LFC));
439 PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_HSEC_CTL_TX_PAUSE_QUANTA_M;
440 cmd->tx_tmr_value = CPU_TO_LE16(tx_timer_val);
442 /* Retrieve the fc threshold */
443 val = rd32(hw, PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(IDX_OF_LFC));
444 fc_thres_val = val & PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_M;
446 cmd->fc_refresh_threshold = CPU_TO_LE16(fc_thres_val);
451 * @hw: pointer to the HW struct
452 * @max_frame_size: Maximum Frame Size to be supported
453 * @cd: pointer to command details structure or NULL
455 * Set MAC configuration (0x0603)
458 ice_aq_set_mac_cfg(struct ice_hw *hw, u16 max_frame_size, struct ice_sq_cd *cd)
460 struct ice_aqc_set_mac_cfg *cmd;
461 struct ice_aq_desc desc;
463 cmd = &desc.params.set_mac_cfg;
465 if (max_frame_size == 0)
466 return ICE_ERR_PARAM;
468 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_mac_cfg);
470 cmd->max_frame_size = CPU_TO_LE16(max_frame_size);
472 ice_fill_tx_timer_and_fc_thresh(hw, cmd);
474 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
478 * ice_init_fltr_mgmt_struct - initializes filter management list and locks
479 * @hw: pointer to the HW struct
481 enum ice_status ice_init_fltr_mgmt_struct(struct ice_hw *hw)
483 struct ice_switch_info *sw;
485 hw->switch_info = (struct ice_switch_info *)
486 ice_malloc(hw, sizeof(*hw->switch_info));
488 sw = hw->switch_info;
491 return ICE_ERR_NO_MEMORY;
493 INIT_LIST_HEAD(&sw->vsi_list_map_head);
495 return ice_init_def_sw_recp(hw, &hw->switch_info->recp_list);
499 * ice_cleanup_fltr_mgmt_struct - cleanup filter management list and locks
500 * @hw: pointer to the HW struct
502 void ice_cleanup_fltr_mgmt_struct(struct ice_hw *hw)
504 struct ice_switch_info *sw = hw->switch_info;
505 struct ice_vsi_list_map_info *v_pos_map;
506 struct ice_vsi_list_map_info *v_tmp_map;
507 struct ice_sw_recipe *recps;
510 LIST_FOR_EACH_ENTRY_SAFE(v_pos_map, v_tmp_map, &sw->vsi_list_map_head,
511 ice_vsi_list_map_info, list_entry) {
512 LIST_DEL(&v_pos_map->list_entry);
513 ice_free(hw, v_pos_map);
515 recps = hw->switch_info->recp_list;
516 for (i = 0; i < ICE_MAX_NUM_RECIPES; i++) {
517 struct ice_recp_grp_entry *rg_entry, *tmprg_entry;
519 recps[i].root_rid = i;
520 LIST_FOR_EACH_ENTRY_SAFE(rg_entry, tmprg_entry,
521 &recps[i].rg_list, ice_recp_grp_entry,
523 LIST_DEL(&rg_entry->l_entry);
524 ice_free(hw, rg_entry);
527 if (recps[i].adv_rule) {
528 struct ice_adv_fltr_mgmt_list_entry *tmp_entry;
529 struct ice_adv_fltr_mgmt_list_entry *lst_itr;
531 ice_destroy_lock(&recps[i].filt_rule_lock);
532 LIST_FOR_EACH_ENTRY_SAFE(lst_itr, tmp_entry,
533 &recps[i].filt_rules,
534 ice_adv_fltr_mgmt_list_entry,
536 LIST_DEL(&lst_itr->list_entry);
537 ice_free(hw, lst_itr->lkups);
538 ice_free(hw, lst_itr);
541 struct ice_fltr_mgmt_list_entry *lst_itr, *tmp_entry;
543 ice_destroy_lock(&recps[i].filt_rule_lock);
544 LIST_FOR_EACH_ENTRY_SAFE(lst_itr, tmp_entry,
545 &recps[i].filt_rules,
546 ice_fltr_mgmt_list_entry,
548 LIST_DEL(&lst_itr->list_entry);
549 ice_free(hw, lst_itr);
552 if (recps[i].root_buf)
553 ice_free(hw, recps[i].root_buf);
555 ice_rm_all_sw_replay_rule_info(hw);
556 ice_free(hw, sw->recp_list);
561 * ice_get_itr_intrl_gran
562 * @hw: pointer to the HW struct
564 * Determines the ITR/INTRL granularities based on the maximum aggregate
565 * bandwidth according to the device's configuration during power-on.
567 static void ice_get_itr_intrl_gran(struct ice_hw *hw)
569 u8 max_agg_bw = (rd32(hw, GL_PWR_MODE_CTL) &
570 GL_PWR_MODE_CTL_CAR_MAX_BW_M) >>
571 GL_PWR_MODE_CTL_CAR_MAX_BW_S;
573 switch (max_agg_bw) {
574 case ICE_MAX_AGG_BW_200G:
575 case ICE_MAX_AGG_BW_100G:
576 case ICE_MAX_AGG_BW_50G:
577 hw->itr_gran = ICE_ITR_GRAN_ABOVE_25;
578 hw->intrl_gran = ICE_INTRL_GRAN_ABOVE_25;
580 case ICE_MAX_AGG_BW_25G:
581 hw->itr_gran = ICE_ITR_GRAN_MAX_25;
582 hw->intrl_gran = ICE_INTRL_GRAN_MAX_25;
588 * ice_print_rollback_msg - print FW rollback message
589 * @hw: pointer to the hardware structure
591 void ice_print_rollback_msg(struct ice_hw *hw)
593 char nvm_str[ICE_NVM_VER_LEN] = { 0 };
594 struct ice_nvm_info *nvm = &hw->nvm;
595 struct ice_orom_info *orom;
599 SNPRINTF(nvm_str, sizeof(nvm_str), "%x.%02x 0x%x %d.%d.%d",
600 nvm->major_ver, nvm->minor_ver, nvm->eetrack, orom->major,
601 orom->build, orom->patch);
603 "Firmware rollback mode detected. Current version is NVM: %s, FW: %d.%d. Device may exhibit limited functionality. Refer to the Intel(R) Ethernet Adapters and Devices User Guide for details on firmware rollback mode\n",
604 nvm_str, hw->fw_maj_ver, hw->fw_min_ver);
608 * ice_init_hw - main hardware initialization routine
609 * @hw: pointer to the hardware structure
611 enum ice_status ice_init_hw(struct ice_hw *hw)
613 struct ice_aqc_get_phy_caps_data *pcaps;
614 enum ice_status status;
618 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
620 /* Set MAC type based on DeviceID */
621 status = ice_set_mac_type(hw);
625 hw->pf_id = (u8)(rd32(hw, PF_FUNC_RID) &
626 PF_FUNC_RID_FUNCTION_NUMBER_M) >>
627 PF_FUNC_RID_FUNCTION_NUMBER_S;
629 status = ice_reset(hw, ICE_RESET_PFR);
633 ice_get_itr_intrl_gran(hw);
635 status = ice_create_all_ctrlq(hw);
637 goto err_unroll_cqinit;
639 status = ice_init_nvm(hw);
641 goto err_unroll_cqinit;
643 if (ice_get_fw_mode(hw) == ICE_FW_MODE_ROLLBACK)
644 ice_print_rollback_msg(hw);
646 status = ice_clear_pf_cfg(hw);
648 goto err_unroll_cqinit;
650 /* Set bit to enable Flow Director filters */
651 wr32(hw, PFQF_FD_ENA, PFQF_FD_ENA_FD_ENA_M);
652 INIT_LIST_HEAD(&hw->fdir_list_head);
654 ice_clear_pxe_mode(hw);
656 status = ice_get_caps(hw);
658 goto err_unroll_cqinit;
660 hw->port_info = (struct ice_port_info *)
661 ice_malloc(hw, sizeof(*hw->port_info));
662 if (!hw->port_info) {
663 status = ICE_ERR_NO_MEMORY;
664 goto err_unroll_cqinit;
667 /* set the back pointer to HW */
668 hw->port_info->hw = hw;
670 /* Initialize port_info struct with switch configuration data */
671 status = ice_get_initial_sw_cfg(hw);
673 goto err_unroll_alloc;
676 /* Query the allocated resources for Tx scheduler */
677 status = ice_sched_query_res_alloc(hw);
679 ice_debug(hw, ICE_DBG_SCHED,
680 "Failed to get scheduler allocated resources\n");
681 goto err_unroll_alloc;
683 ice_sched_get_psm_clk_freq(hw);
685 /* Initialize port_info struct with scheduler data */
686 status = ice_sched_init_port(hw->port_info);
688 goto err_unroll_sched;
690 pcaps = (struct ice_aqc_get_phy_caps_data *)
691 ice_malloc(hw, sizeof(*pcaps));
693 status = ICE_ERR_NO_MEMORY;
694 goto err_unroll_sched;
697 /* Initialize port_info struct with PHY capabilities */
698 status = ice_aq_get_phy_caps(hw->port_info, false,
699 ICE_AQC_REPORT_TOPO_CAP, pcaps, NULL);
702 goto err_unroll_sched;
704 /* Initialize port_info struct with link information */
705 status = ice_aq_get_link_info(hw->port_info, false, NULL, NULL);
707 goto err_unroll_sched;
708 /* need a valid SW entry point to build a Tx tree */
709 if (!hw->sw_entry_point_layer) {
710 ice_debug(hw, ICE_DBG_SCHED, "invalid sw entry point\n");
711 status = ICE_ERR_CFG;
712 goto err_unroll_sched;
714 INIT_LIST_HEAD(&hw->agg_list);
715 /* Initialize max burst size */
716 if (!hw->max_burst_size)
717 ice_cfg_rl_burst_size(hw, ICE_SCHED_DFLT_BURST_SIZE);
719 status = ice_init_fltr_mgmt_struct(hw);
721 goto err_unroll_sched;
723 /* Get MAC information */
724 /* A single port can report up to two (LAN and WoL) addresses */
725 mac_buf = ice_calloc(hw, 2,
726 sizeof(struct ice_aqc_manage_mac_read_resp));
727 mac_buf_len = 2 * sizeof(struct ice_aqc_manage_mac_read_resp);
730 status = ICE_ERR_NO_MEMORY;
731 goto err_unroll_fltr_mgmt_struct;
734 status = ice_aq_manage_mac_read(hw, mac_buf, mac_buf_len, NULL);
735 ice_free(hw, mac_buf);
738 goto err_unroll_fltr_mgmt_struct;
739 /* enable jumbo frame support at MAC level */
740 status = ice_aq_set_mac_cfg(hw, ICE_AQ_SET_MAC_FRAME_SIZE_MAX, NULL);
742 goto err_unroll_fltr_mgmt_struct;
743 /* Obtain counter base index which would be used by flow director */
744 status = ice_alloc_fd_res_cntr(hw, &hw->fd_ctr_base);
746 goto err_unroll_fltr_mgmt_struct;
747 status = ice_init_hw_tbls(hw);
749 goto err_unroll_fltr_mgmt_struct;
750 ice_init_lock(&hw->tnl_lock);
753 err_unroll_fltr_mgmt_struct:
754 ice_cleanup_fltr_mgmt_struct(hw);
756 ice_sched_cleanup_all(hw);
758 ice_free(hw, hw->port_info);
759 hw->port_info = NULL;
761 ice_destroy_all_ctrlq(hw);
766 * ice_deinit_hw - unroll initialization operations done by ice_init_hw
767 * @hw: pointer to the hardware structure
769 * This should be called only during nominal operation, not as a result of
770 * ice_init_hw() failing since ice_init_hw() will take care of unrolling
771 * applicable initializations if it fails for any reason.
773 void ice_deinit_hw(struct ice_hw *hw)
775 ice_free_fd_res_cntr(hw, hw->fd_ctr_base);
776 ice_cleanup_fltr_mgmt_struct(hw);
778 ice_sched_cleanup_all(hw);
779 ice_sched_clear_agg(hw);
781 ice_free_hw_tbls(hw);
782 ice_destroy_lock(&hw->tnl_lock);
785 ice_free(hw, hw->port_info);
786 hw->port_info = NULL;
789 ice_destroy_all_ctrlq(hw);
791 /* Clear VSI contexts if not already cleared */
792 ice_clear_all_vsi_ctx(hw);
796 * ice_check_reset - Check to see if a global reset is complete
797 * @hw: pointer to the hardware structure
799 enum ice_status ice_check_reset(struct ice_hw *hw)
801 u32 cnt, reg = 0, grst_delay, uld_mask;
803 /* Poll for Device Active state in case a recent CORER, GLOBR,
804 * or EMPR has occurred. The grst delay value is in 100ms units.
805 * Add 1sec for outstanding AQ commands that can take a long time.
807 grst_delay = ((rd32(hw, GLGEN_RSTCTL) & GLGEN_RSTCTL_GRSTDEL_M) >>
808 GLGEN_RSTCTL_GRSTDEL_S) + 10;
810 for (cnt = 0; cnt < grst_delay; cnt++) {
811 ice_msec_delay(100, true);
812 reg = rd32(hw, GLGEN_RSTAT);
813 if (!(reg & GLGEN_RSTAT_DEVSTATE_M))
817 if (cnt == grst_delay) {
818 ice_debug(hw, ICE_DBG_INIT,
819 "Global reset polling failed to complete.\n");
820 return ICE_ERR_RESET_FAILED;
823 #define ICE_RESET_DONE_MASK (GLNVM_ULD_PCIER_DONE_M |\
824 GLNVM_ULD_PCIER_DONE_1_M |\
825 GLNVM_ULD_CORER_DONE_M |\
826 GLNVM_ULD_GLOBR_DONE_M |\
827 GLNVM_ULD_POR_DONE_M |\
828 GLNVM_ULD_POR_DONE_1_M |\
829 GLNVM_ULD_PCIER_DONE_2_M)
831 uld_mask = ICE_RESET_DONE_MASK;
833 /* Device is Active; check Global Reset processes are done */
834 for (cnt = 0; cnt < ICE_PF_RESET_WAIT_COUNT; cnt++) {
835 reg = rd32(hw, GLNVM_ULD) & uld_mask;
836 if (reg == uld_mask) {
837 ice_debug(hw, ICE_DBG_INIT,
838 "Global reset processes done. %d\n", cnt);
841 ice_msec_delay(10, true);
844 if (cnt == ICE_PF_RESET_WAIT_COUNT) {
845 ice_debug(hw, ICE_DBG_INIT,
846 "Wait for Reset Done timed out. GLNVM_ULD = 0x%x\n",
848 return ICE_ERR_RESET_FAILED;
855 * ice_pf_reset - Reset the PF
856 * @hw: pointer to the hardware structure
858 * If a global reset has been triggered, this function checks
859 * for its completion and then issues the PF reset
861 static enum ice_status ice_pf_reset(struct ice_hw *hw)
865 /* If at function entry a global reset was already in progress, i.e.
866 * state is not 'device active' or any of the reset done bits are not
867 * set in GLNVM_ULD, there is no need for a PF Reset; poll until the
868 * global reset is done.
870 if ((rd32(hw, GLGEN_RSTAT) & GLGEN_RSTAT_DEVSTATE_M) ||
871 (rd32(hw, GLNVM_ULD) & ICE_RESET_DONE_MASK) ^ ICE_RESET_DONE_MASK) {
872 /* poll on global reset currently in progress until done */
873 if (ice_check_reset(hw))
874 return ICE_ERR_RESET_FAILED;
880 reg = rd32(hw, PFGEN_CTRL);
882 wr32(hw, PFGEN_CTRL, (reg | PFGEN_CTRL_PFSWR_M));
884 for (cnt = 0; cnt < ICE_PF_RESET_WAIT_COUNT; cnt++) {
885 reg = rd32(hw, PFGEN_CTRL);
886 if (!(reg & PFGEN_CTRL_PFSWR_M))
889 ice_msec_delay(1, true);
892 if (cnt == ICE_PF_RESET_WAIT_COUNT) {
893 ice_debug(hw, ICE_DBG_INIT,
894 "PF reset polling failed to complete.\n");
895 return ICE_ERR_RESET_FAILED;
902 * ice_reset - Perform different types of reset
903 * @hw: pointer to the hardware structure
904 * @req: reset request
906 * This function triggers a reset as specified by the req parameter.
909 * If anything other than a PF reset is triggered, PXE mode is restored.
910 * This has to be cleared using ice_clear_pxe_mode again, once the AQ
911 * interface has been restored in the rebuild flow.
913 enum ice_status ice_reset(struct ice_hw *hw, enum ice_reset_req req)
919 return ice_pf_reset(hw);
920 case ICE_RESET_CORER:
921 ice_debug(hw, ICE_DBG_INIT, "CoreR requested\n");
922 val = GLGEN_RTRIG_CORER_M;
924 case ICE_RESET_GLOBR:
925 ice_debug(hw, ICE_DBG_INIT, "GlobalR requested\n");
926 val = GLGEN_RTRIG_GLOBR_M;
929 return ICE_ERR_PARAM;
932 val |= rd32(hw, GLGEN_RTRIG);
933 wr32(hw, GLGEN_RTRIG, val);
936 /* wait for the FW to be ready */
937 return ice_check_reset(hw);
941 * ice_copy_rxq_ctx_to_hw
942 * @hw: pointer to the hardware structure
943 * @ice_rxq_ctx: pointer to the rxq context
944 * @rxq_index: the index of the Rx queue
946 * Copies rxq context from dense structure to HW register space
948 static enum ice_status
949 ice_copy_rxq_ctx_to_hw(struct ice_hw *hw, u8 *ice_rxq_ctx, u32 rxq_index)
954 return ICE_ERR_BAD_PTR;
956 if (rxq_index > QRX_CTRL_MAX_INDEX)
957 return ICE_ERR_PARAM;
959 /* Copy each dword separately to HW */
960 for (i = 0; i < ICE_RXQ_CTX_SIZE_DWORDS; i++) {
961 wr32(hw, QRX_CONTEXT(i, rxq_index),
962 *((u32 *)(ice_rxq_ctx + (i * sizeof(u32)))));
964 ice_debug(hw, ICE_DBG_QCTX, "qrxdata[%d]: %08X\n", i,
965 *((u32 *)(ice_rxq_ctx + (i * sizeof(u32)))));
971 /* LAN Rx Queue Context */
972 static const struct ice_ctx_ele ice_rlan_ctx_info[] = {
973 /* Field Width LSB */
974 ICE_CTX_STORE(ice_rlan_ctx, head, 13, 0),
975 ICE_CTX_STORE(ice_rlan_ctx, cpuid, 8, 13),
976 ICE_CTX_STORE(ice_rlan_ctx, base, 57, 32),
977 ICE_CTX_STORE(ice_rlan_ctx, qlen, 13, 89),
978 ICE_CTX_STORE(ice_rlan_ctx, dbuf, 7, 102),
979 ICE_CTX_STORE(ice_rlan_ctx, hbuf, 5, 109),
980 ICE_CTX_STORE(ice_rlan_ctx, dtype, 2, 114),
981 ICE_CTX_STORE(ice_rlan_ctx, dsize, 1, 116),
982 ICE_CTX_STORE(ice_rlan_ctx, crcstrip, 1, 117),
983 ICE_CTX_STORE(ice_rlan_ctx, l2tsel, 1, 119),
984 ICE_CTX_STORE(ice_rlan_ctx, hsplit_0, 4, 120),
985 ICE_CTX_STORE(ice_rlan_ctx, hsplit_1, 2, 124),
986 ICE_CTX_STORE(ice_rlan_ctx, showiv, 1, 127),
987 ICE_CTX_STORE(ice_rlan_ctx, rxmax, 14, 174),
988 ICE_CTX_STORE(ice_rlan_ctx, tphrdesc_ena, 1, 193),
989 ICE_CTX_STORE(ice_rlan_ctx, tphwdesc_ena, 1, 194),
990 ICE_CTX_STORE(ice_rlan_ctx, tphdata_ena, 1, 195),
991 ICE_CTX_STORE(ice_rlan_ctx, tphhead_ena, 1, 196),
992 ICE_CTX_STORE(ice_rlan_ctx, lrxqthresh, 3, 198),
993 ICE_CTX_STORE(ice_rlan_ctx, prefena, 1, 201),
999 * @hw: pointer to the hardware structure
1000 * @rlan_ctx: pointer to the rxq context
1001 * @rxq_index: the index of the Rx queue
1003 * Converts rxq context from sparse to dense structure and then writes
1004 * it to HW register space and enables the hardware to prefetch descriptors
1005 * instead of only fetching them on demand
1008 ice_write_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx,
1011 u8 ctx_buf[ICE_RXQ_CTX_SZ] = { 0 };
1014 return ICE_ERR_BAD_PTR;
1016 rlan_ctx->prefena = 1;
1018 ice_set_ctx(hw, (u8 *)rlan_ctx, ctx_buf, ice_rlan_ctx_info);
1019 return ice_copy_rxq_ctx_to_hw(hw, ctx_buf, rxq_index);
1024 * @hw: pointer to the hardware structure
1025 * @rxq_index: the index of the Rx queue to clear
1027 * Clears rxq context in HW register space
1029 enum ice_status ice_clear_rxq_ctx(struct ice_hw *hw, u32 rxq_index)
1033 if (rxq_index > QRX_CTRL_MAX_INDEX)
1034 return ICE_ERR_PARAM;
1036 /* Clear each dword register separately */
1037 for (i = 0; i < ICE_RXQ_CTX_SIZE_DWORDS; i++)
1038 wr32(hw, QRX_CONTEXT(i, rxq_index), 0);
1043 /* LAN Tx Queue Context */
1044 const struct ice_ctx_ele ice_tlan_ctx_info[] = {
1045 /* Field Width LSB */
1046 ICE_CTX_STORE(ice_tlan_ctx, base, 57, 0),
1047 ICE_CTX_STORE(ice_tlan_ctx, port_num, 3, 57),
1048 ICE_CTX_STORE(ice_tlan_ctx, cgd_num, 5, 60),
1049 ICE_CTX_STORE(ice_tlan_ctx, pf_num, 3, 65),
1050 ICE_CTX_STORE(ice_tlan_ctx, vmvf_num, 10, 68),
1051 ICE_CTX_STORE(ice_tlan_ctx, vmvf_type, 2, 78),
1052 ICE_CTX_STORE(ice_tlan_ctx, src_vsi, 10, 80),
1053 ICE_CTX_STORE(ice_tlan_ctx, tsyn_ena, 1, 90),
1054 ICE_CTX_STORE(ice_tlan_ctx, internal_usage_flag, 1, 91),
1055 ICE_CTX_STORE(ice_tlan_ctx, alt_vlan, 1, 92),
1056 ICE_CTX_STORE(ice_tlan_ctx, cpuid, 8, 93),
1057 ICE_CTX_STORE(ice_tlan_ctx, wb_mode, 1, 101),
1058 ICE_CTX_STORE(ice_tlan_ctx, tphrd_desc, 1, 102),
1059 ICE_CTX_STORE(ice_tlan_ctx, tphrd, 1, 103),
1060 ICE_CTX_STORE(ice_tlan_ctx, tphwr_desc, 1, 104),
1061 ICE_CTX_STORE(ice_tlan_ctx, cmpq_id, 9, 105),
1062 ICE_CTX_STORE(ice_tlan_ctx, qnum_in_func, 14, 114),
1063 ICE_CTX_STORE(ice_tlan_ctx, itr_notification_mode, 1, 128),
1064 ICE_CTX_STORE(ice_tlan_ctx, adjust_prof_id, 6, 129),
1065 ICE_CTX_STORE(ice_tlan_ctx, qlen, 13, 135),
1066 ICE_CTX_STORE(ice_tlan_ctx, quanta_prof_idx, 4, 148),
1067 ICE_CTX_STORE(ice_tlan_ctx, tso_ena, 1, 152),
1068 ICE_CTX_STORE(ice_tlan_ctx, tso_qnum, 11, 153),
1069 ICE_CTX_STORE(ice_tlan_ctx, legacy_int, 1, 164),
1070 ICE_CTX_STORE(ice_tlan_ctx, drop_ena, 1, 165),
1071 ICE_CTX_STORE(ice_tlan_ctx, cache_prof_idx, 2, 166),
1072 ICE_CTX_STORE(ice_tlan_ctx, pkt_shaper_prof_idx, 3, 168),
1073 ICE_CTX_STORE(ice_tlan_ctx, int_q_state, 122, 171),
1078 * ice_copy_tx_cmpltnq_ctx_to_hw
1079 * @hw: pointer to the hardware structure
1080 * @ice_tx_cmpltnq_ctx: pointer to the Tx completion queue context
1081 * @tx_cmpltnq_index: the index of the completion queue
1083 * Copies Tx completion queue context from dense structure to HW register space
1085 static enum ice_status
1086 ice_copy_tx_cmpltnq_ctx_to_hw(struct ice_hw *hw, u8 *ice_tx_cmpltnq_ctx,
1087 u32 tx_cmpltnq_index)
1091 if (!ice_tx_cmpltnq_ctx)
1092 return ICE_ERR_BAD_PTR;
1094 if (tx_cmpltnq_index > GLTCLAN_CQ_CNTX0_MAX_INDEX)
1095 return ICE_ERR_PARAM;
1097 /* Copy each dword separately to HW */
1098 for (i = 0; i < ICE_TX_CMPLTNQ_CTX_SIZE_DWORDS; i++) {
1099 wr32(hw, GLTCLAN_CQ_CNTX(i, tx_cmpltnq_index),
1100 *((u32 *)(ice_tx_cmpltnq_ctx + (i * sizeof(u32)))));
1102 ice_debug(hw, ICE_DBG_QCTX, "cmpltnqdata[%d]: %08X\n", i,
1103 *((u32 *)(ice_tx_cmpltnq_ctx + (i * sizeof(u32)))));
1109 /* LAN Tx Completion Queue Context */
1110 static const struct ice_ctx_ele ice_tx_cmpltnq_ctx_info[] = {
1111 /* Field Width LSB */
1112 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, base, 57, 0),
1113 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, q_len, 18, 64),
1114 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, generation, 1, 96),
1115 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, wrt_ptr, 22, 97),
1116 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, pf_num, 3, 128),
1117 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, vmvf_num, 10, 131),
1118 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, vmvf_type, 2, 141),
1119 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, tph_desc_wr, 1, 160),
1120 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, cpuid, 8, 161),
1121 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, cmpltn_cache, 512, 192),
1126 * ice_write_tx_cmpltnq_ctx
1127 * @hw: pointer to the hardware structure
1128 * @tx_cmpltnq_ctx: pointer to the completion queue context
1129 * @tx_cmpltnq_index: the index of the completion queue
1131 * Converts completion queue context from sparse to dense structure and then
1132 * writes it to HW register space
1135 ice_write_tx_cmpltnq_ctx(struct ice_hw *hw,
1136 struct ice_tx_cmpltnq_ctx *tx_cmpltnq_ctx,
1137 u32 tx_cmpltnq_index)
1139 u8 ctx_buf[ICE_TX_CMPLTNQ_CTX_SIZE_DWORDS * sizeof(u32)] = { 0 };
1141 ice_set_ctx(hw, (u8 *)tx_cmpltnq_ctx, ctx_buf, ice_tx_cmpltnq_ctx_info);
1142 return ice_copy_tx_cmpltnq_ctx_to_hw(hw, ctx_buf, tx_cmpltnq_index);
1146 * ice_clear_tx_cmpltnq_ctx
1147 * @hw: pointer to the hardware structure
1148 * @tx_cmpltnq_index: the index of the completion queue to clear
1150 * Clears Tx completion queue context in HW register space
1153 ice_clear_tx_cmpltnq_ctx(struct ice_hw *hw, u32 tx_cmpltnq_index)
1157 if (tx_cmpltnq_index > GLTCLAN_CQ_CNTX0_MAX_INDEX)
1158 return ICE_ERR_PARAM;
1160 /* Clear each dword register separately */
1161 for (i = 0; i < ICE_TX_CMPLTNQ_CTX_SIZE_DWORDS; i++)
1162 wr32(hw, GLTCLAN_CQ_CNTX(i, tx_cmpltnq_index), 0);
1168 * ice_copy_tx_drbell_q_ctx_to_hw
1169 * @hw: pointer to the hardware structure
1170 * @ice_tx_drbell_q_ctx: pointer to the doorbell queue context
1171 * @tx_drbell_q_index: the index of the doorbell queue
1173 * Copies doorbell queue context from dense structure to HW register space
1175 static enum ice_status
1176 ice_copy_tx_drbell_q_ctx_to_hw(struct ice_hw *hw, u8 *ice_tx_drbell_q_ctx,
1177 u32 tx_drbell_q_index)
1181 if (!ice_tx_drbell_q_ctx)
1182 return ICE_ERR_BAD_PTR;
1184 if (tx_drbell_q_index > QTX_COMM_DBLQ_DBELL_MAX_INDEX)
1185 return ICE_ERR_PARAM;
1187 /* Copy each dword separately to HW */
1188 for (i = 0; i < ICE_TX_DRBELL_Q_CTX_SIZE_DWORDS; i++) {
1189 wr32(hw, QTX_COMM_DBLQ_CNTX(i, tx_drbell_q_index),
1190 *((u32 *)(ice_tx_drbell_q_ctx + (i * sizeof(u32)))));
1192 ice_debug(hw, ICE_DBG_QCTX, "tx_drbell_qdata[%d]: %08X\n", i,
1193 *((u32 *)(ice_tx_drbell_q_ctx + (i * sizeof(u32)))));
1199 /* LAN Tx Doorbell Queue Context info */
1200 static const struct ice_ctx_ele ice_tx_drbell_q_ctx_info[] = {
1201 /* Field Width LSB */
1202 ICE_CTX_STORE(ice_tx_drbell_q_ctx, base, 57, 0),
1203 ICE_CTX_STORE(ice_tx_drbell_q_ctx, ring_len, 13, 64),
1204 ICE_CTX_STORE(ice_tx_drbell_q_ctx, pf_num, 3, 80),
1205 ICE_CTX_STORE(ice_tx_drbell_q_ctx, vf_num, 8, 84),
1206 ICE_CTX_STORE(ice_tx_drbell_q_ctx, vmvf_type, 2, 94),
1207 ICE_CTX_STORE(ice_tx_drbell_q_ctx, cpuid, 8, 96),
1208 ICE_CTX_STORE(ice_tx_drbell_q_ctx, tph_desc_rd, 1, 104),
1209 ICE_CTX_STORE(ice_tx_drbell_q_ctx, tph_desc_wr, 1, 108),
1210 ICE_CTX_STORE(ice_tx_drbell_q_ctx, db_q_en, 1, 112),
1211 ICE_CTX_STORE(ice_tx_drbell_q_ctx, rd_head, 13, 128),
1212 ICE_CTX_STORE(ice_tx_drbell_q_ctx, rd_tail, 13, 144),
1217 * ice_write_tx_drbell_q_ctx
1218 * @hw: pointer to the hardware structure
1219 * @tx_drbell_q_ctx: pointer to the doorbell queue context
1220 * @tx_drbell_q_index: the index of the doorbell queue
1222 * Converts doorbell queue context from sparse to dense structure and then
1223 * writes it to HW register space
1226 ice_write_tx_drbell_q_ctx(struct ice_hw *hw,
1227 struct ice_tx_drbell_q_ctx *tx_drbell_q_ctx,
1228 u32 tx_drbell_q_index)
1230 u8 ctx_buf[ICE_TX_DRBELL_Q_CTX_SIZE_DWORDS * sizeof(u32)] = { 0 };
1232 ice_set_ctx(hw, (u8 *)tx_drbell_q_ctx, ctx_buf,
1233 ice_tx_drbell_q_ctx_info);
1234 return ice_copy_tx_drbell_q_ctx_to_hw(hw, ctx_buf, tx_drbell_q_index);
1238 * ice_clear_tx_drbell_q_ctx
1239 * @hw: pointer to the hardware structure
1240 * @tx_drbell_q_index: the index of the doorbell queue to clear
1242 * Clears doorbell queue context in HW register space
1245 ice_clear_tx_drbell_q_ctx(struct ice_hw *hw, u32 tx_drbell_q_index)
1249 if (tx_drbell_q_index > QTX_COMM_DBLQ_DBELL_MAX_INDEX)
1250 return ICE_ERR_PARAM;
1252 /* Clear each dword register separately */
1253 for (i = 0; i < ICE_TX_DRBELL_Q_CTX_SIZE_DWORDS; i++)
1254 wr32(hw, QTX_COMM_DBLQ_CNTX(i, tx_drbell_q_index), 0);
1259 /* FW Admin Queue command wrappers */
1262 * ice_aq_send_cmd - send FW Admin Queue command to FW Admin Queue
1263 * @hw: pointer to the HW struct
1264 * @desc: descriptor describing the command
1265 * @buf: buffer to use for indirect commands (NULL for direct commands)
1266 * @buf_size: size of buffer for indirect commands (0 for direct commands)
1267 * @cd: pointer to command details structure
1269 * Helper function to send FW Admin Queue commands to the FW Admin Queue.
1272 ice_aq_send_cmd(struct ice_hw *hw, struct ice_aq_desc *desc, void *buf,
1273 u16 buf_size, struct ice_sq_cd *cd)
1275 if (hw->aq_send_cmd_fn) {
1276 enum ice_status status = ICE_ERR_NOT_READY;
1277 u16 retval = ICE_AQ_RC_OK;
1279 ice_acquire_lock(&hw->adminq.sq_lock);
1280 if (!hw->aq_send_cmd_fn(hw->aq_send_cmd_param, desc,
1282 retval = LE16_TO_CPU(desc->retval);
1283 /* strip off FW internal code */
1286 if (retval == ICE_AQ_RC_OK)
1287 status = ICE_SUCCESS;
1289 status = ICE_ERR_AQ_ERROR;
1292 hw->adminq.sq_last_status = (enum ice_aq_err)retval;
1293 ice_release_lock(&hw->adminq.sq_lock);
1297 return ice_sq_send_cmd(hw, &hw->adminq, desc, buf, buf_size, cd);
1302 * @hw: pointer to the HW struct
1303 * @cd: pointer to command details structure or NULL
1305 * Get the firmware version (0x0001) from the admin queue commands
1307 enum ice_status ice_aq_get_fw_ver(struct ice_hw *hw, struct ice_sq_cd *cd)
1309 struct ice_aqc_get_ver *resp;
1310 struct ice_aq_desc desc;
1311 enum ice_status status;
1313 resp = &desc.params.get_ver;
1315 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_ver);
1317 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
1320 hw->fw_branch = resp->fw_branch;
1321 hw->fw_maj_ver = resp->fw_major;
1322 hw->fw_min_ver = resp->fw_minor;
1323 hw->fw_patch = resp->fw_patch;
1324 hw->fw_build = LE32_TO_CPU(resp->fw_build);
1325 hw->api_branch = resp->api_branch;
1326 hw->api_maj_ver = resp->api_major;
1327 hw->api_min_ver = resp->api_minor;
1328 hw->api_patch = resp->api_patch;
1335 * ice_aq_send_driver_ver
1336 * @hw: pointer to the HW struct
1337 * @dv: driver's major, minor version
1338 * @cd: pointer to command details structure or NULL
1340 * Send the driver version (0x0002) to the firmware
1343 ice_aq_send_driver_ver(struct ice_hw *hw, struct ice_driver_ver *dv,
1344 struct ice_sq_cd *cd)
1346 struct ice_aqc_driver_ver *cmd;
1347 struct ice_aq_desc desc;
1350 cmd = &desc.params.driver_ver;
1353 return ICE_ERR_PARAM;
1355 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_driver_ver);
1357 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
1358 cmd->major_ver = dv->major_ver;
1359 cmd->minor_ver = dv->minor_ver;
1360 cmd->build_ver = dv->build_ver;
1361 cmd->subbuild_ver = dv->subbuild_ver;
1364 while (len < sizeof(dv->driver_string) &&
1365 IS_ASCII(dv->driver_string[len]) && dv->driver_string[len])
1368 return ice_aq_send_cmd(hw, &desc, dv->driver_string, len, cd);
1373 * @hw: pointer to the HW struct
1374 * @unloading: is the driver unloading itself
1376 * Tell the Firmware that we're shutting down the AdminQ and whether
1377 * or not the driver is unloading as well (0x0003).
1379 enum ice_status ice_aq_q_shutdown(struct ice_hw *hw, bool unloading)
1381 struct ice_aqc_q_shutdown *cmd;
1382 struct ice_aq_desc desc;
1384 cmd = &desc.params.q_shutdown;
1386 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_q_shutdown);
1389 cmd->driver_unloading = ICE_AQC_DRIVER_UNLOADING;
1391 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
1396 * @hw: pointer to the HW struct
1398 * @access: access type
1399 * @sdp_number: resource number
1400 * @timeout: the maximum time in ms that the driver may hold the resource
1401 * @cd: pointer to command details structure or NULL
1403 * Requests common resource using the admin queue commands (0x0008).
1404 * When attempting to acquire the Global Config Lock, the driver can
1405 * learn of three states:
1406 * 1) ICE_SUCCESS - acquired lock, and can perform download package
1407 * 2) ICE_ERR_AQ_ERROR - did not get lock, driver should fail to load
1408 * 3) ICE_ERR_AQ_NO_WORK - did not get lock, but another driver has
1409 * successfully downloaded the package; the driver does
1410 * not have to download the package and can continue
1413 * Note that if the caller is in an acquire lock, perform action, release lock
1414 * phase of operation, it is possible that the FW may detect a timeout and issue
1415 * a CORER. In this case, the driver will receive a CORER interrupt and will
1416 * have to determine its cause. The calling thread that is handling this flow
1417 * will likely get an error propagated back to it indicating the Download
1418 * Package, Update Package or the Release Resource AQ commands timed out.
1420 static enum ice_status
1421 ice_aq_req_res(struct ice_hw *hw, enum ice_aq_res_ids res,
1422 enum ice_aq_res_access_type access, u8 sdp_number, u32 *timeout,
1423 struct ice_sq_cd *cd)
1425 struct ice_aqc_req_res *cmd_resp;
1426 struct ice_aq_desc desc;
1427 enum ice_status status;
1429 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
1431 cmd_resp = &desc.params.res_owner;
1433 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_req_res);
1435 cmd_resp->res_id = CPU_TO_LE16(res);
1436 cmd_resp->access_type = CPU_TO_LE16(access);
1437 cmd_resp->res_number = CPU_TO_LE32(sdp_number);
1438 cmd_resp->timeout = CPU_TO_LE32(*timeout);
1441 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
1443 /* The completion specifies the maximum time in ms that the driver
1444 * may hold the resource in the Timeout field.
1447 /* Global config lock response utilizes an additional status field.
1449 * If the Global config lock resource is held by some other driver, the
1450 * command completes with ICE_AQ_RES_GLBL_IN_PROG in the status field
1451 * and the timeout field indicates the maximum time the current owner
1452 * of the resource has to free it.
1454 if (res == ICE_GLOBAL_CFG_LOCK_RES_ID) {
1455 if (LE16_TO_CPU(cmd_resp->status) == ICE_AQ_RES_GLBL_SUCCESS) {
1456 *timeout = LE32_TO_CPU(cmd_resp->timeout);
1458 } else if (LE16_TO_CPU(cmd_resp->status) ==
1459 ICE_AQ_RES_GLBL_IN_PROG) {
1460 *timeout = LE32_TO_CPU(cmd_resp->timeout);
1461 return ICE_ERR_AQ_ERROR;
1462 } else if (LE16_TO_CPU(cmd_resp->status) ==
1463 ICE_AQ_RES_GLBL_DONE) {
1464 return ICE_ERR_AQ_NO_WORK;
1467 /* invalid FW response, force a timeout immediately */
1469 return ICE_ERR_AQ_ERROR;
1472 /* If the resource is held by some other driver, the command completes
1473 * with a busy return value and the timeout field indicates the maximum
1474 * time the current owner of the resource has to free it.
1476 if (!status || hw->adminq.sq_last_status == ICE_AQ_RC_EBUSY)
1477 *timeout = LE32_TO_CPU(cmd_resp->timeout);
1483 * ice_aq_release_res
1484 * @hw: pointer to the HW struct
1486 * @sdp_number: resource number
1487 * @cd: pointer to command details structure or NULL
1489 * release common resource using the admin queue commands (0x0009)
1491 static enum ice_status
1492 ice_aq_release_res(struct ice_hw *hw, enum ice_aq_res_ids res, u8 sdp_number,
1493 struct ice_sq_cd *cd)
1495 struct ice_aqc_req_res *cmd;
1496 struct ice_aq_desc desc;
1498 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
1500 cmd = &desc.params.res_owner;
1502 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_release_res);
1504 cmd->res_id = CPU_TO_LE16(res);
1505 cmd->res_number = CPU_TO_LE32(sdp_number);
1507 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
1512 * @hw: pointer to the HW structure
1514 * @access: access type (read or write)
1515 * @timeout: timeout in milliseconds
1517 * This function will attempt to acquire the ownership of a resource.
1520 ice_acquire_res(struct ice_hw *hw, enum ice_aq_res_ids res,
1521 enum ice_aq_res_access_type access, u32 timeout)
1523 #define ICE_RES_POLLING_DELAY_MS 10
1524 u32 delay = ICE_RES_POLLING_DELAY_MS;
1525 u32 time_left = timeout;
1526 enum ice_status status;
1528 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
1530 status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL);
1532 /* A return code of ICE_ERR_AQ_NO_WORK means that another driver has
1533 * previously acquired the resource and performed any necessary updates;
1534 * in this case the caller does not obtain the resource and has no
1535 * further work to do.
1537 if (status == ICE_ERR_AQ_NO_WORK)
1538 goto ice_acquire_res_exit;
1541 ice_debug(hw, ICE_DBG_RES,
1542 "resource %d acquire type %d failed.\n", res, access);
1544 /* If necessary, poll until the current lock owner timeouts */
1545 timeout = time_left;
1546 while (status && timeout && time_left) {
1547 ice_msec_delay(delay, true);
1548 timeout = (timeout > delay) ? timeout - delay : 0;
1549 status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL);
1551 if (status == ICE_ERR_AQ_NO_WORK)
1552 /* lock free, but no work to do */
1559 if (status && status != ICE_ERR_AQ_NO_WORK)
1560 ice_debug(hw, ICE_DBG_RES, "resource acquire timed out.\n");
1562 ice_acquire_res_exit:
1563 if (status == ICE_ERR_AQ_NO_WORK) {
1564 if (access == ICE_RES_WRITE)
1565 ice_debug(hw, ICE_DBG_RES,
1566 "resource indicates no work to do.\n");
1568 ice_debug(hw, ICE_DBG_RES,
1569 "Warning: ICE_ERR_AQ_NO_WORK not expected\n");
1576 * @hw: pointer to the HW structure
1579 * This function will release a resource using the proper Admin Command.
1581 void ice_release_res(struct ice_hw *hw, enum ice_aq_res_ids res)
1583 enum ice_status status;
1584 u32 total_delay = 0;
1586 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
1588 status = ice_aq_release_res(hw, res, 0, NULL);
1590 /* there are some rare cases when trying to release the resource
1591 * results in an admin queue timeout, so handle them correctly
1593 while ((status == ICE_ERR_AQ_TIMEOUT) &&
1594 (total_delay < hw->adminq.sq_cmd_timeout)) {
1595 ice_msec_delay(1, true);
1596 status = ice_aq_release_res(hw, res, 0, NULL);
1602 * ice_aq_alloc_free_res - command to allocate/free resources
1603 * @hw: pointer to the HW struct
1604 * @num_entries: number of resource entries in buffer
1605 * @buf: Indirect buffer to hold data parameters and response
1606 * @buf_size: size of buffer for indirect commands
1607 * @opc: pass in the command opcode
1608 * @cd: pointer to command details structure or NULL
1610 * Helper function to allocate/free resources using the admin queue commands
1613 ice_aq_alloc_free_res(struct ice_hw *hw, u16 num_entries,
1614 struct ice_aqc_alloc_free_res_elem *buf, u16 buf_size,
1615 enum ice_adminq_opc opc, struct ice_sq_cd *cd)
1617 struct ice_aqc_alloc_free_res_cmd *cmd;
1618 struct ice_aq_desc desc;
1620 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
1622 cmd = &desc.params.sw_res_ctrl;
1625 return ICE_ERR_PARAM;
1627 if (buf_size < (num_entries * sizeof(buf->elem[0])))
1628 return ICE_ERR_PARAM;
1630 ice_fill_dflt_direct_cmd_desc(&desc, opc);
1632 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
1634 cmd->num_entries = CPU_TO_LE16(num_entries);
1636 return ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);
1640 * ice_alloc_hw_res - allocate resource
1641 * @hw: pointer to the HW struct
1642 * @type: type of resource
1643 * @num: number of resources to allocate
1644 * @btm: allocate from bottom
1645 * @res: pointer to array that will receive the resources
1648 ice_alloc_hw_res(struct ice_hw *hw, u16 type, u16 num, bool btm, u16 *res)
1650 struct ice_aqc_alloc_free_res_elem *buf;
1651 enum ice_status status;
1654 buf_len = ice_struct_size(buf, elem, num - 1);
1655 buf = (struct ice_aqc_alloc_free_res_elem *)
1656 ice_malloc(hw, buf_len);
1658 return ICE_ERR_NO_MEMORY;
1660 /* Prepare buffer to allocate resource. */
1661 buf->num_elems = CPU_TO_LE16(num);
1662 buf->res_type = CPU_TO_LE16(type | ICE_AQC_RES_TYPE_FLAG_DEDICATED |
1663 ICE_AQC_RES_TYPE_FLAG_IGNORE_INDEX);
1665 buf->res_type |= CPU_TO_LE16(ICE_AQC_RES_TYPE_FLAG_SCAN_BOTTOM);
1667 status = ice_aq_alloc_free_res(hw, 1, buf, buf_len,
1668 ice_aqc_opc_alloc_res, NULL);
1670 goto ice_alloc_res_exit;
1672 ice_memcpy(res, buf->elem, sizeof(buf->elem) * num,
1673 ICE_NONDMA_TO_NONDMA);
1681 * ice_free_hw_res - free allocated HW resource
1682 * @hw: pointer to the HW struct
1683 * @type: type of resource to free
1684 * @num: number of resources
1685 * @res: pointer to array that contains the resources to free
1688 ice_free_hw_res(struct ice_hw *hw, u16 type, u16 num, u16 *res)
1690 struct ice_aqc_alloc_free_res_elem *buf;
1691 enum ice_status status;
1694 buf_len = ice_struct_size(buf, elem, num - 1);
1695 buf = (struct ice_aqc_alloc_free_res_elem *)ice_malloc(hw, buf_len);
1697 return ICE_ERR_NO_MEMORY;
1699 /* Prepare buffer to free resource. */
1700 buf->num_elems = CPU_TO_LE16(num);
1701 buf->res_type = CPU_TO_LE16(type);
1702 ice_memcpy(buf->elem, res, sizeof(buf->elem) * num,
1703 ICE_NONDMA_TO_NONDMA);
1705 status = ice_aq_alloc_free_res(hw, num, buf, buf_len,
1706 ice_aqc_opc_free_res, NULL);
1708 ice_debug(hw, ICE_DBG_SW, "CQ CMD Buffer:\n");
1715 * ice_get_num_per_func - determine number of resources per PF
1716 * @hw: pointer to the HW structure
1717 * @max: value to be evenly split between each PF
1719 * Determine the number of valid functions by going through the bitmap returned
1720 * from parsing capabilities and use this to calculate the number of resources
1721 * per PF based on the max value passed in.
1723 static u32 ice_get_num_per_func(struct ice_hw *hw, u32 max)
1727 #define ICE_CAPS_VALID_FUNCS_M 0xFF
1728 funcs = ice_hweight8(hw->dev_caps.common_cap.valid_functions &
1729 ICE_CAPS_VALID_FUNCS_M);
1738 * ice_parse_caps - parse function/device capabilities
1739 * @hw: pointer to the HW struct
1740 * @buf: pointer to a buffer containing function/device capability records
1741 * @cap_count: number of capability records in the list
1742 * @opc: type of capabilities list to parse
1744 * Helper function to parse function(0x000a)/device(0x000b) capabilities list.
1747 ice_parse_caps(struct ice_hw *hw, void *buf, u32 cap_count,
1748 enum ice_adminq_opc opc)
1750 struct ice_aqc_list_caps_elem *cap_resp;
1751 struct ice_hw_func_caps *func_p = NULL;
1752 struct ice_hw_dev_caps *dev_p = NULL;
1753 struct ice_hw_common_caps *caps;
1760 cap_resp = (struct ice_aqc_list_caps_elem *)buf;
1762 if (opc == ice_aqc_opc_list_dev_caps) {
1763 dev_p = &hw->dev_caps;
1764 caps = &dev_p->common_cap;
1766 } else if (opc == ice_aqc_opc_list_func_caps) {
1767 func_p = &hw->func_caps;
1768 caps = &func_p->common_cap;
1769 prefix = "func cap";
1771 ice_debug(hw, ICE_DBG_INIT, "wrong opcode\n");
1775 for (i = 0; caps && i < cap_count; i++, cap_resp++) {
1776 u32 logical_id = LE32_TO_CPU(cap_resp->logical_id);
1777 u32 phys_id = LE32_TO_CPU(cap_resp->phys_id);
1778 u32 number = LE32_TO_CPU(cap_resp->number);
1779 u16 cap = LE16_TO_CPU(cap_resp->cap);
1782 case ICE_AQC_CAPS_VALID_FUNCTIONS:
1783 caps->valid_functions = number;
1784 ice_debug(hw, ICE_DBG_INIT,
1785 "%s: valid_functions (bitmap) = %d\n", prefix,
1786 caps->valid_functions);
1788 /* store func count for resource management purposes */
1790 dev_p->num_funcs = ice_hweight32(number);
1792 case ICE_AQC_CAPS_VSI:
1794 dev_p->num_vsi_allocd_to_host = number;
1795 ice_debug(hw, ICE_DBG_INIT,
1796 "%s: num_vsi_allocd_to_host = %d\n",
1798 dev_p->num_vsi_allocd_to_host);
1799 } else if (func_p) {
1800 func_p->guar_num_vsi =
1801 ice_get_num_per_func(hw, ICE_MAX_VSI);
1802 ice_debug(hw, ICE_DBG_INIT,
1803 "%s: guar_num_vsi (fw) = %d\n",
1805 ice_debug(hw, ICE_DBG_INIT,
1806 "%s: guar_num_vsi = %d\n",
1807 prefix, func_p->guar_num_vsi);
1810 case ICE_AQC_CAPS_DCB:
1811 caps->dcb = (number == 1);
1812 caps->active_tc_bitmap = logical_id;
1813 caps->maxtc = phys_id;
1814 ice_debug(hw, ICE_DBG_INIT,
1815 "%s: dcb = %d\n", prefix, caps->dcb);
1816 ice_debug(hw, ICE_DBG_INIT,
1817 "%s: active_tc_bitmap = %d\n", prefix,
1818 caps->active_tc_bitmap);
1819 ice_debug(hw, ICE_DBG_INIT,
1820 "%s: maxtc = %d\n", prefix, caps->maxtc);
1822 case ICE_AQC_CAPS_RSS:
1823 caps->rss_table_size = number;
1824 caps->rss_table_entry_width = logical_id;
1825 ice_debug(hw, ICE_DBG_INIT,
1826 "%s: rss_table_size = %d\n", prefix,
1827 caps->rss_table_size);
1828 ice_debug(hw, ICE_DBG_INIT,
1829 "%s: rss_table_entry_width = %d\n", prefix,
1830 caps->rss_table_entry_width);
1832 case ICE_AQC_CAPS_RXQS:
1833 caps->num_rxq = number;
1834 caps->rxq_first_id = phys_id;
1835 ice_debug(hw, ICE_DBG_INIT,
1836 "%s: num_rxq = %d\n", prefix,
1838 ice_debug(hw, ICE_DBG_INIT,
1839 "%s: rxq_first_id = %d\n", prefix,
1840 caps->rxq_first_id);
1842 case ICE_AQC_CAPS_TXQS:
1843 caps->num_txq = number;
1844 caps->txq_first_id = phys_id;
1845 ice_debug(hw, ICE_DBG_INIT,
1846 "%s: num_txq = %d\n", prefix,
1848 ice_debug(hw, ICE_DBG_INIT,
1849 "%s: txq_first_id = %d\n", prefix,
1850 caps->txq_first_id);
1852 case ICE_AQC_CAPS_MSIX:
1853 caps->num_msix_vectors = number;
1854 caps->msix_vector_first_id = phys_id;
1855 ice_debug(hw, ICE_DBG_INIT,
1856 "%s: num_msix_vectors = %d\n", prefix,
1857 caps->num_msix_vectors);
1858 ice_debug(hw, ICE_DBG_INIT,
1859 "%s: msix_vector_first_id = %d\n", prefix,
1860 caps->msix_vector_first_id);
1862 case ICE_AQC_CAPS_FD:
1864 dev_p->num_flow_director_fltr = number;
1865 ice_debug(hw, ICE_DBG_INIT,
1866 "%s: num_flow_director_fltr = %d\n",
1868 dev_p->num_flow_director_fltr);
1872 if (hw->dcf_enabled)
1874 reg_val = rd32(hw, GLQF_FD_SIZE);
1875 val = (reg_val & GLQF_FD_SIZE_FD_GSIZE_M) >>
1876 GLQF_FD_SIZE_FD_GSIZE_S;
1877 func_p->fd_fltr_guar =
1878 ice_get_num_per_func(hw, val);
1879 val = (reg_val & GLQF_FD_SIZE_FD_BSIZE_M) >>
1880 GLQF_FD_SIZE_FD_BSIZE_S;
1881 func_p->fd_fltr_best_effort = val;
1882 ice_debug(hw, ICE_DBG_INIT,
1883 "%s: fd_fltr_guar = %d\n",
1884 prefix, func_p->fd_fltr_guar);
1885 ice_debug(hw, ICE_DBG_INIT,
1886 "%s: fd_fltr_best_effort = %d\n",
1887 prefix, func_p->fd_fltr_best_effort);
1890 case ICE_AQC_CAPS_MAX_MTU:
1891 caps->max_mtu = number;
1892 ice_debug(hw, ICE_DBG_INIT, "%s: max_mtu = %d\n",
1893 prefix, caps->max_mtu);
1896 ice_debug(hw, ICE_DBG_INIT,
1897 "%s: unknown capability[%d]: 0x%x\n", prefix,
1903 /* Re-calculate capabilities that are dependent on the number of
1904 * physical ports; i.e. some features are not supported or function
1905 * differently on devices with more than 4 ports.
1907 if (hw->dev_caps.num_funcs > 4) {
1908 /* Max 4 TCs per port */
1910 ice_debug(hw, ICE_DBG_INIT,
1911 "%s: maxtc = %d (based on #ports)\n", prefix,
1917 * ice_aq_discover_caps - query function/device capabilities
1918 * @hw: pointer to the HW struct
1919 * @buf: a virtual buffer to hold the capabilities
1920 * @buf_size: Size of the virtual buffer
1921 * @cap_count: cap count needed if AQ err==ENOMEM
1922 * @opc: capabilities type to discover - pass in the command opcode
1923 * @cd: pointer to command details structure or NULL
1925 * Get the function(0x000a)/device(0x000b) capabilities description from
1928 static enum ice_status
1929 ice_aq_discover_caps(struct ice_hw *hw, void *buf, u16 buf_size, u32 *cap_count,
1930 enum ice_adminq_opc opc, struct ice_sq_cd *cd)
1932 struct ice_aqc_list_caps *cmd;
1933 struct ice_aq_desc desc;
1934 enum ice_status status;
1936 cmd = &desc.params.get_cap;
1938 if (opc != ice_aqc_opc_list_func_caps &&
1939 opc != ice_aqc_opc_list_dev_caps)
1940 return ICE_ERR_PARAM;
1942 ice_fill_dflt_direct_cmd_desc(&desc, opc);
1944 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);
1946 ice_parse_caps(hw, buf, LE32_TO_CPU(cmd->count), opc);
1947 else if (hw->adminq.sq_last_status == ICE_AQ_RC_ENOMEM)
1948 *cap_count = LE32_TO_CPU(cmd->count);
1953 * ice_discover_caps - get info about the HW
1954 * @hw: pointer to the hardware structure
1955 * @opc: capabilities type to discover - pass in the command opcode
1957 static enum ice_status
1958 ice_discover_caps(struct ice_hw *hw, enum ice_adminq_opc opc)
1960 enum ice_status status;
1965 /* The driver doesn't know how many capabilities the device will return
1966 * so the buffer size required isn't known ahead of time. The driver
1967 * starts with cbuf_len and if this turns out to be insufficient, the
1968 * device returns ICE_AQ_RC_ENOMEM and also the cap_count it needs.
1969 * The driver then allocates the buffer based on the count and retries
1970 * the operation. So it follows that the retry count is 2.
1972 #define ICE_GET_CAP_BUF_COUNT 40
1973 #define ICE_GET_CAP_RETRY_COUNT 2
1975 cap_count = ICE_GET_CAP_BUF_COUNT;
1976 retries = ICE_GET_CAP_RETRY_COUNT;
1981 cbuf_len = (u16)(cap_count *
1982 sizeof(struct ice_aqc_list_caps_elem));
1983 cbuf = ice_malloc(hw, cbuf_len);
1985 return ICE_ERR_NO_MEMORY;
1987 status = ice_aq_discover_caps(hw, cbuf, cbuf_len, &cap_count,
1991 if (!status || hw->adminq.sq_last_status != ICE_AQ_RC_ENOMEM)
1994 /* If ENOMEM is returned, try again with bigger buffer */
1995 } while (--retries);
2001 * ice_set_safe_mode_caps - Override dev/func capabilities when in safe mode
2002 * @hw: pointer to the hardware structure
2004 void ice_set_safe_mode_caps(struct ice_hw *hw)
2006 struct ice_hw_func_caps *func_caps = &hw->func_caps;
2007 struct ice_hw_dev_caps *dev_caps = &hw->dev_caps;
2008 u32 valid_func, rxq_first_id, txq_first_id;
2009 u32 msix_vector_first_id, max_mtu;
2012 /* cache some func_caps values that should be restored after memset */
2013 valid_func = func_caps->common_cap.valid_functions;
2014 txq_first_id = func_caps->common_cap.txq_first_id;
2015 rxq_first_id = func_caps->common_cap.rxq_first_id;
2016 msix_vector_first_id = func_caps->common_cap.msix_vector_first_id;
2017 max_mtu = func_caps->common_cap.max_mtu;
2019 /* unset func capabilities */
2020 memset(func_caps, 0, sizeof(*func_caps));
2022 /* restore cached values */
2023 func_caps->common_cap.valid_functions = valid_func;
2024 func_caps->common_cap.txq_first_id = txq_first_id;
2025 func_caps->common_cap.rxq_first_id = rxq_first_id;
2026 func_caps->common_cap.msix_vector_first_id = msix_vector_first_id;
2027 func_caps->common_cap.max_mtu = max_mtu;
2029 /* one Tx and one Rx queue in safe mode */
2030 func_caps->common_cap.num_rxq = 1;
2031 func_caps->common_cap.num_txq = 1;
2033 /* two MSIX vectors, one for traffic and one for misc causes */
2034 func_caps->common_cap.num_msix_vectors = 2;
2035 func_caps->guar_num_vsi = 1;
2037 /* cache some dev_caps values that should be restored after memset */
2038 valid_func = dev_caps->common_cap.valid_functions;
2039 txq_first_id = dev_caps->common_cap.txq_first_id;
2040 rxq_first_id = dev_caps->common_cap.rxq_first_id;
2041 msix_vector_first_id = dev_caps->common_cap.msix_vector_first_id;
2042 max_mtu = dev_caps->common_cap.max_mtu;
2043 num_funcs = dev_caps->num_funcs;
2045 /* unset dev capabilities */
2046 memset(dev_caps, 0, sizeof(*dev_caps));
2048 /* restore cached values */
2049 dev_caps->common_cap.valid_functions = valid_func;
2050 dev_caps->common_cap.txq_first_id = txq_first_id;
2051 dev_caps->common_cap.rxq_first_id = rxq_first_id;
2052 dev_caps->common_cap.msix_vector_first_id = msix_vector_first_id;
2053 dev_caps->common_cap.max_mtu = max_mtu;
2054 dev_caps->num_funcs = num_funcs;
2056 /* one Tx and one Rx queue per function in safe mode */
2057 dev_caps->common_cap.num_rxq = num_funcs;
2058 dev_caps->common_cap.num_txq = num_funcs;
2060 /* two MSIX vectors per function */
2061 dev_caps->common_cap.num_msix_vectors = 2 * num_funcs;
2065 * ice_get_caps - get info about the HW
2066 * @hw: pointer to the hardware structure
2068 enum ice_status ice_get_caps(struct ice_hw *hw)
2070 enum ice_status status;
2072 status = ice_discover_caps(hw, ice_aqc_opc_list_dev_caps);
2074 status = ice_discover_caps(hw, ice_aqc_opc_list_func_caps);
2080 * ice_aq_manage_mac_write - manage MAC address write command
2081 * @hw: pointer to the HW struct
2082 * @mac_addr: MAC address to be written as LAA/LAA+WoL/Port address
2083 * @flags: flags to control write behavior
2084 * @cd: pointer to command details structure or NULL
2086 * This function is used to write MAC address to the NVM (0x0108).
2089 ice_aq_manage_mac_write(struct ice_hw *hw, const u8 *mac_addr, u8 flags,
2090 struct ice_sq_cd *cd)
2092 struct ice_aqc_manage_mac_write *cmd;
2093 struct ice_aq_desc desc;
2095 cmd = &desc.params.mac_write;
2096 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_write);
2099 ice_memcpy(cmd->mac_addr, mac_addr, ETH_ALEN, ICE_NONDMA_TO_DMA);
2101 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
2105 * ice_aq_clear_pxe_mode
2106 * @hw: pointer to the HW struct
2108 * Tell the firmware that the driver is taking over from PXE (0x0110).
2110 static enum ice_status ice_aq_clear_pxe_mode(struct ice_hw *hw)
2112 struct ice_aq_desc desc;
2114 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pxe_mode);
2115 desc.params.clear_pxe.rx_cnt = ICE_AQC_CLEAR_PXE_RX_CNT;
2117 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
2121 * ice_clear_pxe_mode - clear pxe operations mode
2122 * @hw: pointer to the HW struct
2124 * Make sure all PXE mode settings are cleared, including things
2125 * like descriptor fetch/write-back mode.
2127 void ice_clear_pxe_mode(struct ice_hw *hw)
2129 if (ice_check_sq_alive(hw, &hw->adminq))
2130 ice_aq_clear_pxe_mode(hw);
2134 * ice_get_link_speed_based_on_phy_type - returns link speed
2135 * @phy_type_low: lower part of phy_type
2136 * @phy_type_high: higher part of phy_type
2138 * This helper function will convert an entry in PHY type structure
2139 * [phy_type_low, phy_type_high] to its corresponding link speed.
2140 * Note: In the structure of [phy_type_low, phy_type_high], there should
2141 * be one bit set, as this function will convert one PHY type to its
2143 * If no bit gets set, ICE_LINK_SPEED_UNKNOWN will be returned
2144 * If more than one bit gets set, ICE_LINK_SPEED_UNKNOWN will be returned
2147 ice_get_link_speed_based_on_phy_type(u64 phy_type_low, u64 phy_type_high)
2149 u16 speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN;
2150 u16 speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN;
2152 switch (phy_type_low) {
2153 case ICE_PHY_TYPE_LOW_100BASE_TX:
2154 case ICE_PHY_TYPE_LOW_100M_SGMII:
2155 speed_phy_type_low = ICE_AQ_LINK_SPEED_100MB;
2157 case ICE_PHY_TYPE_LOW_1000BASE_T:
2158 case ICE_PHY_TYPE_LOW_1000BASE_SX:
2159 case ICE_PHY_TYPE_LOW_1000BASE_LX:
2160 case ICE_PHY_TYPE_LOW_1000BASE_KX:
2161 case ICE_PHY_TYPE_LOW_1G_SGMII:
2162 speed_phy_type_low = ICE_AQ_LINK_SPEED_1000MB;
2164 case ICE_PHY_TYPE_LOW_2500BASE_T:
2165 case ICE_PHY_TYPE_LOW_2500BASE_X:
2166 case ICE_PHY_TYPE_LOW_2500BASE_KX:
2167 speed_phy_type_low = ICE_AQ_LINK_SPEED_2500MB;
2169 case ICE_PHY_TYPE_LOW_5GBASE_T:
2170 case ICE_PHY_TYPE_LOW_5GBASE_KR:
2171 speed_phy_type_low = ICE_AQ_LINK_SPEED_5GB;
2173 case ICE_PHY_TYPE_LOW_10GBASE_T:
2174 case ICE_PHY_TYPE_LOW_10G_SFI_DA:
2175 case ICE_PHY_TYPE_LOW_10GBASE_SR:
2176 case ICE_PHY_TYPE_LOW_10GBASE_LR:
2177 case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1:
2178 case ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC:
2179 case ICE_PHY_TYPE_LOW_10G_SFI_C2C:
2180 speed_phy_type_low = ICE_AQ_LINK_SPEED_10GB;
2182 case ICE_PHY_TYPE_LOW_25GBASE_T:
2183 case ICE_PHY_TYPE_LOW_25GBASE_CR:
2184 case ICE_PHY_TYPE_LOW_25GBASE_CR_S:
2185 case ICE_PHY_TYPE_LOW_25GBASE_CR1:
2186 case ICE_PHY_TYPE_LOW_25GBASE_SR:
2187 case ICE_PHY_TYPE_LOW_25GBASE_LR:
2188 case ICE_PHY_TYPE_LOW_25GBASE_KR:
2189 case ICE_PHY_TYPE_LOW_25GBASE_KR_S:
2190 case ICE_PHY_TYPE_LOW_25GBASE_KR1:
2191 case ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC:
2192 case ICE_PHY_TYPE_LOW_25G_AUI_C2C:
2193 speed_phy_type_low = ICE_AQ_LINK_SPEED_25GB;
2195 case ICE_PHY_TYPE_LOW_40GBASE_CR4:
2196 case ICE_PHY_TYPE_LOW_40GBASE_SR4:
2197 case ICE_PHY_TYPE_LOW_40GBASE_LR4:
2198 case ICE_PHY_TYPE_LOW_40GBASE_KR4:
2199 case ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC:
2200 case ICE_PHY_TYPE_LOW_40G_XLAUI:
2201 speed_phy_type_low = ICE_AQ_LINK_SPEED_40GB;
2203 case ICE_PHY_TYPE_LOW_50GBASE_CR2:
2204 case ICE_PHY_TYPE_LOW_50GBASE_SR2:
2205 case ICE_PHY_TYPE_LOW_50GBASE_LR2:
2206 case ICE_PHY_TYPE_LOW_50GBASE_KR2:
2207 case ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC:
2208 case ICE_PHY_TYPE_LOW_50G_LAUI2:
2209 case ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC:
2210 case ICE_PHY_TYPE_LOW_50G_AUI2:
2211 case ICE_PHY_TYPE_LOW_50GBASE_CP:
2212 case ICE_PHY_TYPE_LOW_50GBASE_SR:
2213 case ICE_PHY_TYPE_LOW_50GBASE_FR:
2214 case ICE_PHY_TYPE_LOW_50GBASE_LR:
2215 case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4:
2216 case ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC:
2217 case ICE_PHY_TYPE_LOW_50G_AUI1:
2218 speed_phy_type_low = ICE_AQ_LINK_SPEED_50GB;
2220 case ICE_PHY_TYPE_LOW_100GBASE_CR4:
2221 case ICE_PHY_TYPE_LOW_100GBASE_SR4:
2222 case ICE_PHY_TYPE_LOW_100GBASE_LR4:
2223 case ICE_PHY_TYPE_LOW_100GBASE_KR4:
2224 case ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC:
2225 case ICE_PHY_TYPE_LOW_100G_CAUI4:
2226 case ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC:
2227 case ICE_PHY_TYPE_LOW_100G_AUI4:
2228 case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4:
2229 case ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4:
2230 case ICE_PHY_TYPE_LOW_100GBASE_CP2:
2231 case ICE_PHY_TYPE_LOW_100GBASE_SR2:
2232 case ICE_PHY_TYPE_LOW_100GBASE_DR:
2233 speed_phy_type_low = ICE_AQ_LINK_SPEED_100GB;
2236 speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN;
2240 switch (phy_type_high) {
2241 case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4:
2242 case ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC:
2243 case ICE_PHY_TYPE_HIGH_100G_CAUI2:
2244 case ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC:
2245 case ICE_PHY_TYPE_HIGH_100G_AUI2:
2246 speed_phy_type_high = ICE_AQ_LINK_SPEED_100GB;
2249 speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN;
2253 if (speed_phy_type_low == ICE_AQ_LINK_SPEED_UNKNOWN &&
2254 speed_phy_type_high == ICE_AQ_LINK_SPEED_UNKNOWN)
2255 return ICE_AQ_LINK_SPEED_UNKNOWN;
2256 else if (speed_phy_type_low != ICE_AQ_LINK_SPEED_UNKNOWN &&
2257 speed_phy_type_high != ICE_AQ_LINK_SPEED_UNKNOWN)
2258 return ICE_AQ_LINK_SPEED_UNKNOWN;
2259 else if (speed_phy_type_low != ICE_AQ_LINK_SPEED_UNKNOWN &&
2260 speed_phy_type_high == ICE_AQ_LINK_SPEED_UNKNOWN)
2261 return speed_phy_type_low;
2263 return speed_phy_type_high;
2267 * ice_update_phy_type
2268 * @phy_type_low: pointer to the lower part of phy_type
2269 * @phy_type_high: pointer to the higher part of phy_type
2270 * @link_speeds_bitmap: targeted link speeds bitmap
2272 * Note: For the link_speeds_bitmap structure, you can check it at
2273 * [ice_aqc_get_link_status->link_speed]. Caller can pass in
2274 * link_speeds_bitmap include multiple speeds.
2276 * Each entry in this [phy_type_low, phy_type_high] structure will
2277 * present a certain link speed. This helper function will turn on bits
2278 * in [phy_type_low, phy_type_high] structure based on the value of
2279 * link_speeds_bitmap input parameter.
2282 ice_update_phy_type(u64 *phy_type_low, u64 *phy_type_high,
2283 u16 link_speeds_bitmap)
2290 /* We first check with low part of phy_type */
2291 for (index = 0; index <= ICE_PHY_TYPE_LOW_MAX_INDEX; index++) {
2292 pt_low = BIT_ULL(index);
2293 speed = ice_get_link_speed_based_on_phy_type(pt_low, 0);
2295 if (link_speeds_bitmap & speed)
2296 *phy_type_low |= BIT_ULL(index);
2299 /* We then check with high part of phy_type */
2300 for (index = 0; index <= ICE_PHY_TYPE_HIGH_MAX_INDEX; index++) {
2301 pt_high = BIT_ULL(index);
2302 speed = ice_get_link_speed_based_on_phy_type(0, pt_high);
2304 if (link_speeds_bitmap & speed)
2305 *phy_type_high |= BIT_ULL(index);
2310 * ice_aq_set_phy_cfg
2311 * @hw: pointer to the HW struct
2312 * @pi: port info structure of the interested logical port
2313 * @cfg: structure with PHY configuration data to be set
2314 * @cd: pointer to command details structure or NULL
2316 * Set the various PHY configuration parameters supported on the Port.
2317 * One or more of the Set PHY config parameters may be ignored in an MFP
2318 * mode as the PF may not have the privilege to set some of the PHY Config
2319 * parameters. This status will be indicated by the command response (0x0601).
2322 ice_aq_set_phy_cfg(struct ice_hw *hw, struct ice_port_info *pi,
2323 struct ice_aqc_set_phy_cfg_data *cfg, struct ice_sq_cd *cd)
2325 struct ice_aq_desc desc;
2326 enum ice_status status;
2329 return ICE_ERR_PARAM;
2331 /* Ensure that only valid bits of cfg->caps can be turned on. */
2332 if (cfg->caps & ~ICE_AQ_PHY_ENA_VALID_MASK) {
2333 ice_debug(hw, ICE_DBG_PHY,
2334 "Invalid bit is set in ice_aqc_set_phy_cfg_data->caps : 0x%x\n",
2337 cfg->caps &= ICE_AQ_PHY_ENA_VALID_MASK;
2340 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_phy_cfg);
2341 desc.params.set_phy.lport_num = pi->lport;
2342 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
2344 ice_debug(hw, ICE_DBG_LINK, "phy_type_low = 0x%llx\n",
2345 (unsigned long long)LE64_TO_CPU(cfg->phy_type_low));
2346 ice_debug(hw, ICE_DBG_LINK, "phy_type_high = 0x%llx\n",
2347 (unsigned long long)LE64_TO_CPU(cfg->phy_type_high));
2348 ice_debug(hw, ICE_DBG_LINK, "caps = 0x%x\n", cfg->caps);
2349 ice_debug(hw, ICE_DBG_LINK, "low_power_ctrl_an = 0x%x\n",
2350 cfg->low_power_ctrl_an);
2351 ice_debug(hw, ICE_DBG_LINK, "eee_cap = 0x%x\n", cfg->eee_cap);
2352 ice_debug(hw, ICE_DBG_LINK, "eeer_value = 0x%x\n", cfg->eeer_value);
2353 ice_debug(hw, ICE_DBG_LINK, "link_fec_opt = 0x%x\n", cfg->link_fec_opt);
2355 status = ice_aq_send_cmd(hw, &desc, cfg, sizeof(*cfg), cd);
2357 if (hw->adminq.sq_last_status == ICE_AQ_RC_EMODE)
2358 status = ICE_SUCCESS;
2361 pi->phy.curr_user_phy_cfg = *cfg;
2367 * ice_update_link_info - update status of the HW network link
2368 * @pi: port info structure of the interested logical port
2370 enum ice_status ice_update_link_info(struct ice_port_info *pi)
2372 struct ice_link_status *li;
2373 enum ice_status status;
2376 return ICE_ERR_PARAM;
2378 li = &pi->phy.link_info;
2380 status = ice_aq_get_link_info(pi, true, NULL, NULL);
2384 if (li->link_info & ICE_AQ_MEDIA_AVAILABLE) {
2385 struct ice_aqc_get_phy_caps_data *pcaps;
2389 pcaps = (struct ice_aqc_get_phy_caps_data *)
2390 ice_malloc(hw, sizeof(*pcaps));
2392 return ICE_ERR_NO_MEMORY;
2394 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_TOPO_CAP,
2396 if (status == ICE_SUCCESS)
2397 ice_memcpy(li->module_type, &pcaps->module_type,
2398 sizeof(li->module_type),
2399 ICE_NONDMA_TO_NONDMA);
2401 ice_free(hw, pcaps);
2408 * ice_cache_phy_user_req
2409 * @pi: port information structure
2410 * @cache_data: PHY logging data
2411 * @cache_mode: PHY logging mode
2413 * Log the user request on (FC, FEC, SPEED) for later user.
2416 ice_cache_phy_user_req(struct ice_port_info *pi,
2417 struct ice_phy_cache_mode_data cache_data,
2418 enum ice_phy_cache_mode cache_mode)
2423 switch (cache_mode) {
2425 pi->phy.curr_user_fc_req = cache_data.data.curr_user_fc_req;
2427 case ICE_SPEED_MODE:
2428 pi->phy.curr_user_speed_req =
2429 cache_data.data.curr_user_speed_req;
2432 pi->phy.curr_user_fec_req = cache_data.data.curr_user_fec_req;
2440 * ice_caps_to_fc_mode
2441 * @caps: PHY capabilities
2443 * Convert PHY FC capabilities to ice FC mode
2445 enum ice_fc_mode ice_caps_to_fc_mode(u8 caps)
2447 if (caps & ICE_AQC_PHY_EN_TX_LINK_PAUSE &&
2448 caps & ICE_AQC_PHY_EN_RX_LINK_PAUSE)
2451 if (caps & ICE_AQC_PHY_EN_TX_LINK_PAUSE)
2452 return ICE_FC_TX_PAUSE;
2454 if (caps & ICE_AQC_PHY_EN_RX_LINK_PAUSE)
2455 return ICE_FC_RX_PAUSE;
2461 * ice_caps_to_fec_mode
2462 * @caps: PHY capabilities
2463 * @fec_options: Link FEC options
2465 * Convert PHY FEC capabilities to ice FEC mode
2467 enum ice_fec_mode ice_caps_to_fec_mode(u8 caps, u8 fec_options)
2469 if (caps & ICE_AQC_PHY_EN_AUTO_FEC)
2470 return ICE_FEC_AUTO;
2472 if (fec_options & (ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN |
2473 ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ |
2474 ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN |
2475 ICE_AQC_PHY_FEC_25G_KR_REQ))
2476 return ICE_FEC_BASER;
2478 if (fec_options & (ICE_AQC_PHY_FEC_25G_RS_528_REQ |
2479 ICE_AQC_PHY_FEC_25G_RS_544_REQ |
2480 ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN))
2483 return ICE_FEC_NONE;
2486 static enum ice_status
2487 ice_cfg_phy_fc(struct ice_port_info *pi, struct ice_aqc_set_phy_cfg_data *cfg,
2488 enum ice_fc_mode req_mode)
2490 struct ice_aqc_get_phy_caps_data *pcaps = NULL;
2491 struct ice_phy_cache_mode_data cache_data;
2492 enum ice_status status = ICE_SUCCESS;
2493 u8 pause_mask = 0x0;
2496 return ICE_ERR_BAD_PTR;
2498 pcaps = (struct ice_aqc_get_phy_caps_data *)
2499 ice_malloc(pi->hw, sizeof(*pcaps));
2501 return ICE_ERR_NO_MEMORY;
2503 /* Cache user FC request */
2504 cache_data.data.curr_user_fc_req = req_mode;
2505 ice_cache_phy_user_req(pi, cache_data, ICE_FC_MODE);
2509 /* Query the value of FC that both the NIC and attached media
2512 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_TOPO_CAP,
2517 pause_mask |= pcaps->caps & ICE_AQC_PHY_EN_TX_LINK_PAUSE;
2518 pause_mask |= pcaps->caps & ICE_AQC_PHY_EN_RX_LINK_PAUSE;
2521 pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE;
2522 pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE;
2524 case ICE_FC_RX_PAUSE:
2525 pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE;
2527 case ICE_FC_TX_PAUSE:
2528 pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE;
2534 /* clear the old pause settings */
2535 cfg->caps &= ~(ICE_AQC_PHY_EN_TX_LINK_PAUSE |
2536 ICE_AQC_PHY_EN_RX_LINK_PAUSE);
2538 /* set the new capabilities */
2539 cfg->caps |= pause_mask;
2542 ice_free(pi->hw, pcaps);
2548 * @pi: port information structure
2549 * @aq_failures: pointer to status code, specific to ice_set_fc routine
2550 * @ena_auto_link_update: enable automatic link update
2552 * Set the requested flow control mode.
2555 ice_set_fc(struct ice_port_info *pi, u8 *aq_failures, bool ena_auto_link_update)
2557 struct ice_aqc_set_phy_cfg_data cfg = { 0 };
2558 struct ice_aqc_get_phy_caps_data *pcaps;
2559 enum ice_status status;
2562 if (!pi || !aq_failures)
2563 return ICE_ERR_BAD_PTR;
2567 pcaps = (struct ice_aqc_get_phy_caps_data *)
2568 ice_malloc(hw, sizeof(*pcaps));
2570 return ICE_ERR_NO_MEMORY;
2572 /* Get the current PHY config */
2573 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_SW_CFG, pcaps,
2576 *aq_failures = ICE_SET_FC_AQ_FAIL_GET;
2580 ice_copy_phy_caps_to_cfg(pi, pcaps, &cfg);
2582 /* Configure the set phy data */
2583 status = ice_cfg_phy_fc(pi, &cfg, pi->fc.req_mode);
2585 if (status != ICE_ERR_BAD_PTR)
2586 *aq_failures = ICE_SET_FC_AQ_FAIL_GET;
2591 /* If the capabilities have changed, then set the new config */
2592 if (cfg.caps != pcaps->caps) {
2593 int retry_count, retry_max = 10;
2595 /* Auto restart link so settings take effect */
2596 if (ena_auto_link_update)
2597 cfg.caps |= ICE_AQ_PHY_ENA_AUTO_LINK_UPDT;
2599 status = ice_aq_set_phy_cfg(hw, pi, &cfg, NULL);
2601 *aq_failures = ICE_SET_FC_AQ_FAIL_SET;
2605 /* Update the link info
2606 * It sometimes takes a really long time for link to
2607 * come back from the atomic reset. Thus, we wait a
2610 for (retry_count = 0; retry_count < retry_max; retry_count++) {
2611 status = ice_update_link_info(pi);
2613 if (status == ICE_SUCCESS)
2616 ice_msec_delay(100, true);
2620 *aq_failures = ICE_SET_FC_AQ_FAIL_UPDATE;
2624 ice_free(hw, pcaps);
2629 * ice_phy_caps_equals_cfg
2630 * @phy_caps: PHY capabilities
2631 * @phy_cfg: PHY configuration
2633 * Helper function to determine if PHY capabilities matches PHY
2637 ice_phy_caps_equals_cfg(struct ice_aqc_get_phy_caps_data *phy_caps,
2638 struct ice_aqc_set_phy_cfg_data *phy_cfg)
2640 u8 caps_mask, cfg_mask;
2642 if (!phy_caps || !phy_cfg)
2645 /* These bits are not common between capabilities and configuration.
2646 * Do not use them to determine equality.
2648 caps_mask = ICE_AQC_PHY_CAPS_MASK & ~(ICE_AQC_PHY_AN_MODE |
2649 ICE_AQC_PHY_EN_MOD_QUAL);
2650 cfg_mask = ICE_AQ_PHY_ENA_VALID_MASK & ~ICE_AQ_PHY_ENA_AUTO_LINK_UPDT;
2652 if (phy_caps->phy_type_low != phy_cfg->phy_type_low ||
2653 phy_caps->phy_type_high != phy_cfg->phy_type_high ||
2654 ((phy_caps->caps & caps_mask) != (phy_cfg->caps & cfg_mask)) ||
2655 phy_caps->low_power_ctrl_an != phy_cfg->low_power_ctrl_an ||
2656 phy_caps->eee_cap != phy_cfg->eee_cap ||
2657 phy_caps->eeer_value != phy_cfg->eeer_value ||
2658 phy_caps->link_fec_options != phy_cfg->link_fec_opt)
2665 * ice_copy_phy_caps_to_cfg - Copy PHY ability data to configuration data
2666 * @pi: port information structure
2667 * @caps: PHY ability structure to copy date from
2668 * @cfg: PHY configuration structure to copy data to
2670 * Helper function to copy AQC PHY get ability data to PHY set configuration
2674 ice_copy_phy_caps_to_cfg(struct ice_port_info *pi,
2675 struct ice_aqc_get_phy_caps_data *caps,
2676 struct ice_aqc_set_phy_cfg_data *cfg)
2678 if (!pi || !caps || !cfg)
2681 ice_memset(cfg, 0, sizeof(*cfg), ICE_NONDMA_MEM);
2682 cfg->phy_type_low = caps->phy_type_low;
2683 cfg->phy_type_high = caps->phy_type_high;
2684 cfg->caps = caps->caps;
2685 cfg->low_power_ctrl_an = caps->low_power_ctrl_an;
2686 cfg->eee_cap = caps->eee_cap;
2687 cfg->eeer_value = caps->eeer_value;
2688 cfg->link_fec_opt = caps->link_fec_options;
2689 cfg->module_compliance_enforcement =
2690 caps->module_compliance_enforcement;
2692 if (ice_fw_supports_link_override(pi->hw)) {
2693 struct ice_link_default_override_tlv tlv;
2695 if (ice_get_link_default_override(&tlv, pi))
2698 if (tlv.options & ICE_LINK_OVERRIDE_STRICT_MODE)
2699 cfg->module_compliance_enforcement |=
2700 ICE_LINK_OVERRIDE_STRICT_MODE;
2705 * ice_cfg_phy_fec - Configure PHY FEC data based on FEC mode
2706 * @pi: port information structure
2707 * @cfg: PHY configuration data to set FEC mode
2708 * @fec: FEC mode to configure
2711 ice_cfg_phy_fec(struct ice_port_info *pi, struct ice_aqc_set_phy_cfg_data *cfg,
2712 enum ice_fec_mode fec)
2714 struct ice_aqc_get_phy_caps_data *pcaps;
2715 enum ice_status status = ICE_SUCCESS;
2719 return ICE_ERR_BAD_PTR;
2723 pcaps = (struct ice_aqc_get_phy_caps_data *)
2724 ice_malloc(hw, sizeof(*pcaps));
2726 return ICE_ERR_NO_MEMORY;
2728 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_TOPO_CAP, pcaps,
2735 /* Clear RS bits, and AND BASE-R ability
2736 * bits and OR request bits.
2738 cfg->link_fec_opt &= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN |
2739 ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN;
2740 cfg->link_fec_opt |= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ |
2741 ICE_AQC_PHY_FEC_25G_KR_REQ;
2744 /* Clear BASE-R bits, and AND RS ability
2745 * bits and OR request bits.
2747 cfg->link_fec_opt &= ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN;
2748 cfg->link_fec_opt |= ICE_AQC_PHY_FEC_25G_RS_528_REQ |
2749 ICE_AQC_PHY_FEC_25G_RS_544_REQ;
2752 /* Clear all FEC option bits. */
2753 cfg->link_fec_opt &= ~ICE_AQC_PHY_FEC_MASK;
2756 /* AND auto FEC bit, and all caps bits. */
2757 cfg->caps &= ICE_AQC_PHY_CAPS_MASK;
2758 cfg->link_fec_opt |= pcaps->link_fec_options;
2761 status = ICE_ERR_PARAM;
2765 if (fec == ICE_FEC_AUTO && ice_fw_supports_link_override(pi->hw)) {
2766 struct ice_link_default_override_tlv tlv;
2768 if (ice_get_link_default_override(&tlv, pi))
2771 if (!(tlv.options & ICE_LINK_OVERRIDE_STRICT_MODE) &&
2772 (tlv.options & ICE_LINK_OVERRIDE_EN))
2773 cfg->link_fec_opt = tlv.fec_options;
2777 ice_free(hw, pcaps);
2783 * ice_get_link_status - get status of the HW network link
2784 * @pi: port information structure
2785 * @link_up: pointer to bool (true/false = linkup/linkdown)
2787 * Variable link_up is true if link is up, false if link is down.
2788 * The variable link_up is invalid if status is non zero. As a
2789 * result of this call, link status reporting becomes enabled
2791 enum ice_status ice_get_link_status(struct ice_port_info *pi, bool *link_up)
2793 struct ice_phy_info *phy_info;
2794 enum ice_status status = ICE_SUCCESS;
2796 if (!pi || !link_up)
2797 return ICE_ERR_PARAM;
2799 phy_info = &pi->phy;
2801 if (phy_info->get_link_info) {
2802 status = ice_update_link_info(pi);
2805 ice_debug(pi->hw, ICE_DBG_LINK,
2806 "get link status error, status = %d\n",
2810 *link_up = phy_info->link_info.link_info & ICE_AQ_LINK_UP;
2816 * ice_aq_set_link_restart_an
2817 * @pi: pointer to the port information structure
2818 * @ena_link: if true: enable link, if false: disable link
2819 * @cd: pointer to command details structure or NULL
2821 * Sets up the link and restarts the Auto-Negotiation over the link.
2824 ice_aq_set_link_restart_an(struct ice_port_info *pi, bool ena_link,
2825 struct ice_sq_cd *cd)
2827 struct ice_aqc_restart_an *cmd;
2828 struct ice_aq_desc desc;
2830 cmd = &desc.params.restart_an;
2832 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_restart_an);
2834 cmd->cmd_flags = ICE_AQC_RESTART_AN_LINK_RESTART;
2835 cmd->lport_num = pi->lport;
2837 cmd->cmd_flags |= ICE_AQC_RESTART_AN_LINK_ENABLE;
2839 cmd->cmd_flags &= ~ICE_AQC_RESTART_AN_LINK_ENABLE;
2841 return ice_aq_send_cmd(pi->hw, &desc, NULL, 0, cd);
2845 * ice_aq_set_event_mask
2846 * @hw: pointer to the HW struct
2847 * @port_num: port number of the physical function
2848 * @mask: event mask to be set
2849 * @cd: pointer to command details structure or NULL
2851 * Set event mask (0x0613)
2854 ice_aq_set_event_mask(struct ice_hw *hw, u8 port_num, u16 mask,
2855 struct ice_sq_cd *cd)
2857 struct ice_aqc_set_event_mask *cmd;
2858 struct ice_aq_desc desc;
2860 cmd = &desc.params.set_event_mask;
2862 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_event_mask);
2864 cmd->lport_num = port_num;
2866 cmd->event_mask = CPU_TO_LE16(mask);
2867 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
2871 * ice_aq_set_mac_loopback
2872 * @hw: pointer to the HW struct
2873 * @ena_lpbk: Enable or Disable loopback
2874 * @cd: pointer to command details structure or NULL
2876 * Enable/disable loopback on a given port
2879 ice_aq_set_mac_loopback(struct ice_hw *hw, bool ena_lpbk, struct ice_sq_cd *cd)
2881 struct ice_aqc_set_mac_lb *cmd;
2882 struct ice_aq_desc desc;
2884 cmd = &desc.params.set_mac_lb;
2886 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_mac_lb);
2888 cmd->lb_mode = ICE_AQ_MAC_LB_EN;
2890 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
2894 * ice_aq_set_port_id_led
2895 * @pi: pointer to the port information
2896 * @is_orig_mode: is this LED set to original mode (by the net-list)
2897 * @cd: pointer to command details structure or NULL
2899 * Set LED value for the given port (0x06e9)
2902 ice_aq_set_port_id_led(struct ice_port_info *pi, bool is_orig_mode,
2903 struct ice_sq_cd *cd)
2905 struct ice_aqc_set_port_id_led *cmd;
2906 struct ice_hw *hw = pi->hw;
2907 struct ice_aq_desc desc;
2909 cmd = &desc.params.set_port_id_led;
2911 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_port_id_led);
2914 cmd->ident_mode = ICE_AQC_PORT_IDENT_LED_ORIG;
2916 cmd->ident_mode = ICE_AQC_PORT_IDENT_LED_BLINK;
2918 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
2923 * @hw: pointer to the HW struct
2924 * @lport: bits [7:0] = logical port, bit [8] = logical port valid
2925 * @bus_addr: I2C bus address of the eeprom (typically 0xA0, 0=topo default)
2926 * @mem_addr: I2C offset. lower 8 bits for address, 8 upper bits zero padding.
2928 * @set_page: set or ignore the page
2929 * @data: pointer to data buffer to be read/written to the I2C device.
2930 * @length: 1-16 for read, 1 for write.
2931 * @write: 0 read, 1 for write.
2932 * @cd: pointer to command details structure or NULL
2934 * Read/Write SFF EEPROM (0x06EE)
2937 ice_aq_sff_eeprom(struct ice_hw *hw, u16 lport, u8 bus_addr,
2938 u16 mem_addr, u8 page, u8 set_page, u8 *data, u8 length,
2939 bool write, struct ice_sq_cd *cd)
2941 struct ice_aqc_sff_eeprom *cmd;
2942 struct ice_aq_desc desc;
2943 enum ice_status status;
2945 if (!data || (mem_addr & 0xff00))
2946 return ICE_ERR_PARAM;
2948 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_sff_eeprom);
2949 cmd = &desc.params.read_write_sff_param;
2950 desc.flags = CPU_TO_LE16(ICE_AQ_FLAG_RD | ICE_AQ_FLAG_BUF);
2951 cmd->lport_num = (u8)(lport & 0xff);
2952 cmd->lport_num_valid = (u8)((lport >> 8) & 0x01);
2953 cmd->i2c_bus_addr = CPU_TO_LE16(((bus_addr >> 1) &
2954 ICE_AQC_SFF_I2CBUS_7BIT_M) |
2956 ICE_AQC_SFF_SET_EEPROM_PAGE_S) &
2957 ICE_AQC_SFF_SET_EEPROM_PAGE_M));
2958 cmd->i2c_mem_addr = CPU_TO_LE16(mem_addr & 0xff);
2959 cmd->eeprom_page = CPU_TO_LE16((u16)page << ICE_AQC_SFF_EEPROM_PAGE_S);
2961 cmd->i2c_bus_addr |= CPU_TO_LE16(ICE_AQC_SFF_IS_WRITE);
2963 status = ice_aq_send_cmd(hw, &desc, data, length, cd);
2968 * __ice_aq_get_set_rss_lut
2969 * @hw: pointer to the hardware structure
2970 * @vsi_id: VSI FW index
2971 * @lut_type: LUT table type
2972 * @lut: pointer to the LUT buffer provided by the caller
2973 * @lut_size: size of the LUT buffer
2974 * @glob_lut_idx: global LUT index
2975 * @set: set true to set the table, false to get the table
2977 * Internal function to get (0x0B05) or set (0x0B03) RSS look up table
2979 static enum ice_status
2980 __ice_aq_get_set_rss_lut(struct ice_hw *hw, u16 vsi_id, u8 lut_type, u8 *lut,
2981 u16 lut_size, u8 glob_lut_idx, bool set)
2983 struct ice_aqc_get_set_rss_lut *cmd_resp;
2984 struct ice_aq_desc desc;
2985 enum ice_status status;
2988 cmd_resp = &desc.params.get_set_rss_lut;
2991 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_rss_lut);
2992 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
2994 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_rss_lut);
2997 cmd_resp->vsi_id = CPU_TO_LE16(((vsi_id <<
2998 ICE_AQC_GSET_RSS_LUT_VSI_ID_S) &
2999 ICE_AQC_GSET_RSS_LUT_VSI_ID_M) |
3000 ICE_AQC_GSET_RSS_LUT_VSI_VALID);
3003 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_VSI:
3004 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF:
3005 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL:
3006 flags |= ((lut_type << ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S) &
3007 ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_M);
3010 status = ICE_ERR_PARAM;
3011 goto ice_aq_get_set_rss_lut_exit;
3014 if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL) {
3015 flags |= ((glob_lut_idx << ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S) &
3016 ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_M);
3019 goto ice_aq_get_set_rss_lut_send;
3020 } else if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF) {
3022 goto ice_aq_get_set_rss_lut_send;
3024 goto ice_aq_get_set_rss_lut_send;
3027 /* LUT size is only valid for Global and PF table types */
3029 case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128:
3030 flags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128_FLAG <<
3031 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) &
3032 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M;
3034 case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512:
3035 flags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512_FLAG <<
3036 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) &
3037 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M;
3039 case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K:
3040 if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF) {
3041 flags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K_FLAG <<
3042 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) &
3043 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M;
3048 status = ICE_ERR_PARAM;
3049 goto ice_aq_get_set_rss_lut_exit;
3052 ice_aq_get_set_rss_lut_send:
3053 cmd_resp->flags = CPU_TO_LE16(flags);
3054 status = ice_aq_send_cmd(hw, &desc, lut, lut_size, NULL);
3056 ice_aq_get_set_rss_lut_exit:
3061 * ice_aq_get_rss_lut
3062 * @hw: pointer to the hardware structure
3063 * @vsi_handle: software VSI handle
3064 * @lut_type: LUT table type
3065 * @lut: pointer to the LUT buffer provided by the caller
3066 * @lut_size: size of the LUT buffer
3068 * get the RSS lookup table, PF or VSI type
3071 ice_aq_get_rss_lut(struct ice_hw *hw, u16 vsi_handle, u8 lut_type,
3072 u8 *lut, u16 lut_size)
3074 if (!ice_is_vsi_valid(hw, vsi_handle) || !lut)
3075 return ICE_ERR_PARAM;
3077 return __ice_aq_get_set_rss_lut(hw, ice_get_hw_vsi_num(hw, vsi_handle),
3078 lut_type, lut, lut_size, 0, false);
3082 * ice_aq_set_rss_lut
3083 * @hw: pointer to the hardware structure
3084 * @vsi_handle: software VSI handle
3085 * @lut_type: LUT table type
3086 * @lut: pointer to the LUT buffer provided by the caller
3087 * @lut_size: size of the LUT buffer
3089 * set the RSS lookup table, PF or VSI type
3092 ice_aq_set_rss_lut(struct ice_hw *hw, u16 vsi_handle, u8 lut_type,
3093 u8 *lut, u16 lut_size)
3095 if (!ice_is_vsi_valid(hw, vsi_handle) || !lut)
3096 return ICE_ERR_PARAM;
3098 return __ice_aq_get_set_rss_lut(hw, ice_get_hw_vsi_num(hw, vsi_handle),
3099 lut_type, lut, lut_size, 0, true);
3103 * __ice_aq_get_set_rss_key
3104 * @hw: pointer to the HW struct
3105 * @vsi_id: VSI FW index
3106 * @key: pointer to key info struct
3107 * @set: set true to set the key, false to get the key
3109 * get (0x0B04) or set (0x0B02) the RSS key per VSI
3112 ice_status __ice_aq_get_set_rss_key(struct ice_hw *hw, u16 vsi_id,
3113 struct ice_aqc_get_set_rss_keys *key,
3116 struct ice_aqc_get_set_rss_key *cmd_resp;
3117 u16 key_size = sizeof(*key);
3118 struct ice_aq_desc desc;
3120 cmd_resp = &desc.params.get_set_rss_key;
3123 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_rss_key);
3124 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
3126 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_rss_key);
3129 cmd_resp->vsi_id = CPU_TO_LE16(((vsi_id <<
3130 ICE_AQC_GSET_RSS_KEY_VSI_ID_S) &
3131 ICE_AQC_GSET_RSS_KEY_VSI_ID_M) |
3132 ICE_AQC_GSET_RSS_KEY_VSI_VALID);
3134 return ice_aq_send_cmd(hw, &desc, key, key_size, NULL);
3138 * ice_aq_get_rss_key
3139 * @hw: pointer to the HW struct
3140 * @vsi_handle: software VSI handle
3141 * @key: pointer to key info struct
3143 * get the RSS key per VSI
3146 ice_aq_get_rss_key(struct ice_hw *hw, u16 vsi_handle,
3147 struct ice_aqc_get_set_rss_keys *key)
3149 if (!ice_is_vsi_valid(hw, vsi_handle) || !key)
3150 return ICE_ERR_PARAM;
3152 return __ice_aq_get_set_rss_key(hw, ice_get_hw_vsi_num(hw, vsi_handle),
3157 * ice_aq_set_rss_key
3158 * @hw: pointer to the HW struct
3159 * @vsi_handle: software VSI handle
3160 * @keys: pointer to key info struct
3162 * set the RSS key per VSI
3165 ice_aq_set_rss_key(struct ice_hw *hw, u16 vsi_handle,
3166 struct ice_aqc_get_set_rss_keys *keys)
3168 if (!ice_is_vsi_valid(hw, vsi_handle) || !keys)
3169 return ICE_ERR_PARAM;
3171 return __ice_aq_get_set_rss_key(hw, ice_get_hw_vsi_num(hw, vsi_handle),
3176 * ice_aq_add_lan_txq
3177 * @hw: pointer to the hardware structure
3178 * @num_qgrps: Number of added queue groups
3179 * @qg_list: list of queue groups to be added
3180 * @buf_size: size of buffer for indirect command
3181 * @cd: pointer to command details structure or NULL
3183 * Add Tx LAN queue (0x0C30)
3186 * Prior to calling add Tx LAN queue:
3187 * Initialize the following as part of the Tx queue context:
3188 * Completion queue ID if the queue uses Completion queue, Quanta profile,
3189 * Cache profile and Packet shaper profile.
3191 * After add Tx LAN queue AQ command is completed:
3192 * Interrupts should be associated with specific queues,
3193 * Association of Tx queue to Doorbell queue is not part of Add LAN Tx queue
3197 ice_aq_add_lan_txq(struct ice_hw *hw, u8 num_qgrps,
3198 struct ice_aqc_add_tx_qgrp *qg_list, u16 buf_size,
3199 struct ice_sq_cd *cd)
3201 u16 i, sum_header_size, sum_q_size = 0;
3202 struct ice_aqc_add_tx_qgrp *list;
3203 struct ice_aqc_add_txqs *cmd;
3204 struct ice_aq_desc desc;
3206 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
3208 cmd = &desc.params.add_txqs;
3210 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_add_txqs);
3213 return ICE_ERR_PARAM;
3215 if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS)
3216 return ICE_ERR_PARAM;
3218 sum_header_size = num_qgrps *
3219 (sizeof(*qg_list) - sizeof(*qg_list->txqs));
3222 for (i = 0; i < num_qgrps; i++) {
3223 struct ice_aqc_add_txqs_perq *q = list->txqs;
3225 sum_q_size += list->num_txqs * sizeof(*q);
3226 list = (struct ice_aqc_add_tx_qgrp *)(q + list->num_txqs);
3229 if (buf_size != (sum_header_size + sum_q_size))
3230 return ICE_ERR_PARAM;
3232 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
3234 cmd->num_qgrps = num_qgrps;
3236 return ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd);
3240 * ice_aq_dis_lan_txq
3241 * @hw: pointer to the hardware structure
3242 * @num_qgrps: number of groups in the list
3243 * @qg_list: the list of groups to disable
3244 * @buf_size: the total size of the qg_list buffer in bytes
3245 * @rst_src: if called due to reset, specifies the reset source
3246 * @vmvf_num: the relative VM or VF number that is undergoing the reset
3247 * @cd: pointer to command details structure or NULL
3249 * Disable LAN Tx queue (0x0C31)
3251 static enum ice_status
3252 ice_aq_dis_lan_txq(struct ice_hw *hw, u8 num_qgrps,
3253 struct ice_aqc_dis_txq_item *qg_list, u16 buf_size,
3254 enum ice_disq_rst_src rst_src, u16 vmvf_num,
3255 struct ice_sq_cd *cd)
3257 struct ice_aqc_dis_txqs *cmd;
3258 struct ice_aq_desc desc;
3259 enum ice_status status;
3262 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
3263 cmd = &desc.params.dis_txqs;
3264 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_dis_txqs);
3266 /* qg_list can be NULL only in VM/VF reset flow */
3267 if (!qg_list && !rst_src)
3268 return ICE_ERR_PARAM;
3270 if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS)
3271 return ICE_ERR_PARAM;
3273 cmd->num_entries = num_qgrps;
3275 cmd->vmvf_and_timeout = CPU_TO_LE16((5 << ICE_AQC_Q_DIS_TIMEOUT_S) &
3276 ICE_AQC_Q_DIS_TIMEOUT_M);
3280 cmd->cmd_type = ICE_AQC_Q_DIS_CMD_VM_RESET;
3281 cmd->vmvf_and_timeout |=
3282 CPU_TO_LE16(vmvf_num & ICE_AQC_Q_DIS_VMVF_NUM_M);
3289 /* flush pipe on time out */
3290 cmd->cmd_type |= ICE_AQC_Q_DIS_CMD_FLUSH_PIPE;
3291 /* If no queue group info, we are in a reset flow. Issue the AQ */
3295 /* set RD bit to indicate that command buffer is provided by the driver
3296 * and it needs to be read by the firmware
3298 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
3300 for (i = 0; i < num_qgrps; ++i) {
3301 /* Calculate the size taken up by the queue IDs in this group */
3302 sz += qg_list[i].num_qs * sizeof(qg_list[i].q_id);
3304 /* Add the size of the group header */
3305 sz += sizeof(qg_list[i]) - sizeof(qg_list[i].q_id);
3307 /* If the num of queues is even, add 2 bytes of padding */
3308 if ((qg_list[i].num_qs % 2) == 0)
3313 return ICE_ERR_PARAM;
3316 status = ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd);
3319 ice_debug(hw, ICE_DBG_SCHED, "VM%d disable failed %d\n",
3320 vmvf_num, hw->adminq.sq_last_status);
3322 ice_debug(hw, ICE_DBG_SCHED, "disable queue %d failed %d\n",
3323 LE16_TO_CPU(qg_list[0].q_id[0]),
3324 hw->adminq.sq_last_status);
3330 * ice_aq_move_recfg_lan_txq
3331 * @hw: pointer to the hardware structure
3332 * @num_qs: number of queues to move/reconfigure
3333 * @is_move: true if this operation involves node movement
3334 * @is_tc_change: true if this operation involves a TC change
3335 * @subseq_call: true if this operation is a subsequent call
3336 * @flush_pipe: on timeout, true to flush pipe, false to return EAGAIN
3337 * @timeout: timeout in units of 100 usec (valid values 0-50)
3338 * @blocked_cgds: out param, bitmap of CGDs that timed out if returning EAGAIN
3339 * @buf: struct containing src/dest TEID and per-queue info
3340 * @buf_size: size of buffer for indirect command
3341 * @txqs_moved: out param, number of queues successfully moved
3342 * @cd: pointer to command details structure or NULL
3344 * Move / Reconfigure Tx LAN queues (0x0C32)
3347 ice_aq_move_recfg_lan_txq(struct ice_hw *hw, u8 num_qs, bool is_move,
3348 bool is_tc_change, bool subseq_call, bool flush_pipe,
3349 u8 timeout, u32 *blocked_cgds,
3350 struct ice_aqc_move_txqs_data *buf, u16 buf_size,
3351 u8 *txqs_moved, struct ice_sq_cd *cd)
3353 struct ice_aqc_move_txqs *cmd;
3354 struct ice_aq_desc desc;
3355 enum ice_status status;
3357 cmd = &desc.params.move_txqs;
3358 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_move_recfg_txqs);
3360 #define ICE_LAN_TXQ_MOVE_TIMEOUT_MAX 50
3361 if (timeout > ICE_LAN_TXQ_MOVE_TIMEOUT_MAX)
3362 return ICE_ERR_PARAM;
3364 if (is_tc_change && !flush_pipe && !blocked_cgds)
3365 return ICE_ERR_PARAM;
3367 if (!is_move && !is_tc_change)
3368 return ICE_ERR_PARAM;
3370 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
3373 cmd->cmd_type |= ICE_AQC_Q_CMD_TYPE_MOVE;
3376 cmd->cmd_type |= ICE_AQC_Q_CMD_TYPE_TC_CHANGE;
3379 cmd->cmd_type |= ICE_AQC_Q_CMD_SUBSEQ_CALL;
3382 cmd->cmd_type |= ICE_AQC_Q_CMD_FLUSH_PIPE;
3384 cmd->num_qs = num_qs;
3385 cmd->timeout = ((timeout << ICE_AQC_Q_CMD_TIMEOUT_S) &
3386 ICE_AQC_Q_CMD_TIMEOUT_M);
3388 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);
3390 if (!status && txqs_moved)
3391 *txqs_moved = cmd->num_qs;
3393 if (hw->adminq.sq_last_status == ICE_AQ_RC_EAGAIN &&
3394 is_tc_change && !flush_pipe)
3395 *blocked_cgds = LE32_TO_CPU(cmd->blocked_cgds);
3400 /* End of FW Admin Queue command wrappers */
3403 * ice_write_byte - write a byte to a packed context structure
3404 * @src_ctx: the context structure to read from
3405 * @dest_ctx: the context to be written to
3406 * @ce_info: a description of the struct to be filled
3409 ice_write_byte(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)
3411 u8 src_byte, dest_byte, mask;
3415 /* copy from the next struct field */
3416 from = src_ctx + ce_info->offset;
3418 /* prepare the bits and mask */
3419 shift_width = ce_info->lsb % 8;
3420 mask = (u8)(BIT(ce_info->width) - 1);
3425 /* shift to correct alignment */
3426 mask <<= shift_width;
3427 src_byte <<= shift_width;
3429 /* get the current bits from the target bit string */
3430 dest = dest_ctx + (ce_info->lsb / 8);
3432 ice_memcpy(&dest_byte, dest, sizeof(dest_byte), ICE_DMA_TO_NONDMA);
3434 dest_byte &= ~mask; /* get the bits not changing */
3435 dest_byte |= src_byte; /* add in the new bits */
3437 /* put it all back */
3438 ice_memcpy(dest, &dest_byte, sizeof(dest_byte), ICE_NONDMA_TO_DMA);
3442 * ice_write_word - write a word to a packed context structure
3443 * @src_ctx: the context structure to read from
3444 * @dest_ctx: the context to be written to
3445 * @ce_info: a description of the struct to be filled
3448 ice_write_word(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)
3455 /* copy from the next struct field */
3456 from = src_ctx + ce_info->offset;
3458 /* prepare the bits and mask */
3459 shift_width = ce_info->lsb % 8;
3460 mask = BIT(ce_info->width) - 1;
3462 /* don't swizzle the bits until after the mask because the mask bits
3463 * will be in a different bit position on big endian machines
3465 src_word = *(u16 *)from;
3468 /* shift to correct alignment */
3469 mask <<= shift_width;
3470 src_word <<= shift_width;
3472 /* get the current bits from the target bit string */
3473 dest = dest_ctx + (ce_info->lsb / 8);
3475 ice_memcpy(&dest_word, dest, sizeof(dest_word), ICE_DMA_TO_NONDMA);
3477 dest_word &= ~(CPU_TO_LE16(mask)); /* get the bits not changing */
3478 dest_word |= CPU_TO_LE16(src_word); /* add in the new bits */
3480 /* put it all back */
3481 ice_memcpy(dest, &dest_word, sizeof(dest_word), ICE_NONDMA_TO_DMA);
3485 * ice_write_dword - write a dword to a packed context structure
3486 * @src_ctx: the context structure to read from
3487 * @dest_ctx: the context to be written to
3488 * @ce_info: a description of the struct to be filled
3491 ice_write_dword(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)
3493 u32 src_dword, mask;
3498 /* copy from the next struct field */
3499 from = src_ctx + ce_info->offset;
3501 /* prepare the bits and mask */
3502 shift_width = ce_info->lsb % 8;
3504 /* if the field width is exactly 32 on an x86 machine, then the shift
3505 * operation will not work because the SHL instructions count is masked
3506 * to 5 bits so the shift will do nothing
3508 if (ce_info->width < 32)
3509 mask = BIT(ce_info->width) - 1;
3513 /* don't swizzle the bits until after the mask because the mask bits
3514 * will be in a different bit position on big endian machines
3516 src_dword = *(u32 *)from;
3519 /* shift to correct alignment */
3520 mask <<= shift_width;
3521 src_dword <<= shift_width;
3523 /* get the current bits from the target bit string */
3524 dest = dest_ctx + (ce_info->lsb / 8);
3526 ice_memcpy(&dest_dword, dest, sizeof(dest_dword), ICE_DMA_TO_NONDMA);
3528 dest_dword &= ~(CPU_TO_LE32(mask)); /* get the bits not changing */
3529 dest_dword |= CPU_TO_LE32(src_dword); /* add in the new bits */
3531 /* put it all back */
3532 ice_memcpy(dest, &dest_dword, sizeof(dest_dword), ICE_NONDMA_TO_DMA);
3536 * ice_write_qword - write a qword to a packed context structure
3537 * @src_ctx: the context structure to read from
3538 * @dest_ctx: the context to be written to
3539 * @ce_info: a description of the struct to be filled
3542 ice_write_qword(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)
3544 u64 src_qword, mask;
3549 /* copy from the next struct field */
3550 from = src_ctx + ce_info->offset;
3552 /* prepare the bits and mask */
3553 shift_width = ce_info->lsb % 8;
3555 /* if the field width is exactly 64 on an x86 machine, then the shift
3556 * operation will not work because the SHL instructions count is masked
3557 * to 6 bits so the shift will do nothing
3559 if (ce_info->width < 64)
3560 mask = BIT_ULL(ce_info->width) - 1;
3564 /* don't swizzle the bits until after the mask because the mask bits
3565 * will be in a different bit position on big endian machines
3567 src_qword = *(u64 *)from;
3570 /* shift to correct alignment */
3571 mask <<= shift_width;
3572 src_qword <<= shift_width;
3574 /* get the current bits from the target bit string */
3575 dest = dest_ctx + (ce_info->lsb / 8);
3577 ice_memcpy(&dest_qword, dest, sizeof(dest_qword), ICE_DMA_TO_NONDMA);
3579 dest_qword &= ~(CPU_TO_LE64(mask)); /* get the bits not changing */
3580 dest_qword |= CPU_TO_LE64(src_qword); /* add in the new bits */
3582 /* put it all back */
3583 ice_memcpy(dest, &dest_qword, sizeof(dest_qword), ICE_NONDMA_TO_DMA);
3587 * ice_set_ctx - set context bits in packed structure
3588 * @hw: pointer to the hardware structure
3589 * @src_ctx: pointer to a generic non-packed context structure
3590 * @dest_ctx: pointer to memory for the packed structure
3591 * @ce_info: a description of the structure to be transformed
3594 ice_set_ctx(struct ice_hw *hw, u8 *src_ctx, u8 *dest_ctx,
3595 const struct ice_ctx_ele *ce_info)
3599 for (f = 0; ce_info[f].width; f++) {
3600 /* We have to deal with each element of the FW response
3601 * using the correct size so that we are correct regardless
3602 * of the endianness of the machine.
3604 if (ce_info[f].width > (ce_info[f].size_of * BITS_PER_BYTE)) {
3605 ice_debug(hw, ICE_DBG_QCTX,
3606 "Field %d width of %d bits larger than size of %d byte(s) ... skipping write\n",
3607 f, ce_info[f].width, ce_info[f].size_of);
3610 switch (ce_info[f].size_of) {
3612 ice_write_byte(src_ctx, dest_ctx, &ce_info[f]);
3615 ice_write_word(src_ctx, dest_ctx, &ce_info[f]);
3618 ice_write_dword(src_ctx, dest_ctx, &ce_info[f]);
3621 ice_write_qword(src_ctx, dest_ctx, &ce_info[f]);
3624 return ICE_ERR_INVAL_SIZE;
3632 * ice_read_byte - read context byte into struct
3633 * @src_ctx: the context structure to read from
3634 * @dest_ctx: the context to be written to
3635 * @ce_info: a description of the struct to be filled
3638 ice_read_byte(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info)
3644 /* prepare the bits and mask */
3645 shift_width = ce_info->lsb % 8;
3646 mask = (u8)(BIT(ce_info->width) - 1);
3648 /* shift to correct alignment */
3649 mask <<= shift_width;
3651 /* get the current bits from the src bit string */
3652 src = src_ctx + (ce_info->lsb / 8);
3654 ice_memcpy(&dest_byte, src, sizeof(dest_byte), ICE_DMA_TO_NONDMA);
3656 dest_byte &= ~(mask);
3658 dest_byte >>= shift_width;
3660 /* get the address from the struct field */
3661 target = dest_ctx + ce_info->offset;
3663 /* put it back in the struct */
3664 ice_memcpy(target, &dest_byte, sizeof(dest_byte), ICE_NONDMA_TO_DMA);
3668 * ice_read_word - read context word into struct
3669 * @src_ctx: the context structure to read from
3670 * @dest_ctx: the context to be written to
3671 * @ce_info: a description of the struct to be filled
3674 ice_read_word(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info)
3676 u16 dest_word, mask;
3681 /* prepare the bits and mask */
3682 shift_width = ce_info->lsb % 8;
3683 mask = BIT(ce_info->width) - 1;
3685 /* shift to correct alignment */
3686 mask <<= shift_width;
3688 /* get the current bits from the src bit string */
3689 src = src_ctx + (ce_info->lsb / 8);
3691 ice_memcpy(&src_word, src, sizeof(src_word), ICE_DMA_TO_NONDMA);
3693 /* the data in the memory is stored as little endian so mask it
3696 src_word &= ~(CPU_TO_LE16(mask));
3698 /* get the data back into host order before shifting */
3699 dest_word = LE16_TO_CPU(src_word);
3701 dest_word >>= shift_width;
3703 /* get the address from the struct field */
3704 target = dest_ctx + ce_info->offset;
3706 /* put it back in the struct */
3707 ice_memcpy(target, &dest_word, sizeof(dest_word), ICE_NONDMA_TO_DMA);
3711 * ice_read_dword - read context dword into struct
3712 * @src_ctx: the context structure to read from
3713 * @dest_ctx: the context to be written to
3714 * @ce_info: a description of the struct to be filled
3717 ice_read_dword(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info)
3719 u32 dest_dword, mask;
3724 /* prepare the bits and mask */
3725 shift_width = ce_info->lsb % 8;
3727 /* if the field width is exactly 32 on an x86 machine, then the shift
3728 * operation will not work because the SHL instructions count is masked
3729 * to 5 bits so the shift will do nothing
3731 if (ce_info->width < 32)
3732 mask = BIT(ce_info->width) - 1;
3736 /* shift to correct alignment */
3737 mask <<= shift_width;
3739 /* get the current bits from the src bit string */
3740 src = src_ctx + (ce_info->lsb / 8);
3742 ice_memcpy(&src_dword, src, sizeof(src_dword), ICE_DMA_TO_NONDMA);
3744 /* the data in the memory is stored as little endian so mask it
3747 src_dword &= ~(CPU_TO_LE32(mask));
3749 /* get the data back into host order before shifting */
3750 dest_dword = LE32_TO_CPU(src_dword);
3752 dest_dword >>= shift_width;
3754 /* get the address from the struct field */
3755 target = dest_ctx + ce_info->offset;
3757 /* put it back in the struct */
3758 ice_memcpy(target, &dest_dword, sizeof(dest_dword), ICE_NONDMA_TO_DMA);
3762 * ice_read_qword - read context qword into struct
3763 * @src_ctx: the context structure to read from
3764 * @dest_ctx: the context to be written to
3765 * @ce_info: a description of the struct to be filled
3768 ice_read_qword(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info)
3770 u64 dest_qword, mask;
3775 /* prepare the bits and mask */
3776 shift_width = ce_info->lsb % 8;
3778 /* if the field width is exactly 64 on an x86 machine, then the shift
3779 * operation will not work because the SHL instructions count is masked
3780 * to 6 bits so the shift will do nothing
3782 if (ce_info->width < 64)
3783 mask = BIT_ULL(ce_info->width) - 1;
3787 /* shift to correct alignment */
3788 mask <<= shift_width;
3790 /* get the current bits from the src bit string */
3791 src = src_ctx + (ce_info->lsb / 8);
3793 ice_memcpy(&src_qword, src, sizeof(src_qword), ICE_DMA_TO_NONDMA);
3795 /* the data in the memory is stored as little endian so mask it
3798 src_qword &= ~(CPU_TO_LE64(mask));
3800 /* get the data back into host order before shifting */
3801 dest_qword = LE64_TO_CPU(src_qword);
3803 dest_qword >>= shift_width;
3805 /* get the address from the struct field */
3806 target = dest_ctx + ce_info->offset;
3808 /* put it back in the struct */
3809 ice_memcpy(target, &dest_qword, sizeof(dest_qword), ICE_NONDMA_TO_DMA);
3813 * ice_get_ctx - extract context bits from a packed structure
3814 * @src_ctx: pointer to a generic packed context structure
3815 * @dest_ctx: pointer to a generic non-packed context structure
3816 * @ce_info: a description of the structure to be read from
3819 ice_get_ctx(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info)
3823 for (f = 0; ce_info[f].width; f++) {
3824 switch (ce_info[f].size_of) {
3826 ice_read_byte(src_ctx, dest_ctx, &ce_info[f]);
3829 ice_read_word(src_ctx, dest_ctx, &ce_info[f]);
3832 ice_read_dword(src_ctx, dest_ctx, &ce_info[f]);
3835 ice_read_qword(src_ctx, dest_ctx, &ce_info[f]);
3838 /* nothing to do, just keep going */
3847 * ice_get_lan_q_ctx - get the LAN queue context for the given VSI and TC
3848 * @hw: pointer to the HW struct
3849 * @vsi_handle: software VSI handle
3851 * @q_handle: software queue handle
3854 ice_get_lan_q_ctx(struct ice_hw *hw, u16 vsi_handle, u8 tc, u16 q_handle)
3856 struct ice_vsi_ctx *vsi;
3857 struct ice_q_ctx *q_ctx;
3859 vsi = ice_get_vsi_ctx(hw, vsi_handle);
3862 if (q_handle >= vsi->num_lan_q_entries[tc])
3864 if (!vsi->lan_q_ctx[tc])
3866 q_ctx = vsi->lan_q_ctx[tc];
3867 return &q_ctx[q_handle];
3872 * @pi: port information structure
3873 * @vsi_handle: software VSI handle
3875 * @q_handle: software queue handle
3876 * @num_qgrps: Number of added queue groups
3877 * @buf: list of queue groups to be added
3878 * @buf_size: size of buffer for indirect command
3879 * @cd: pointer to command details structure or NULL
3881 * This function adds one LAN queue
3884 ice_ena_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u16 q_handle,
3885 u8 num_qgrps, struct ice_aqc_add_tx_qgrp *buf, u16 buf_size,
3886 struct ice_sq_cd *cd)
3888 struct ice_aqc_txsched_elem_data node = { 0 };
3889 struct ice_sched_node *parent;
3890 struct ice_q_ctx *q_ctx;
3891 enum ice_status status;
3894 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY)
3897 if (num_qgrps > 1 || buf->num_txqs > 1)
3898 return ICE_ERR_MAX_LIMIT;
3902 if (!ice_is_vsi_valid(hw, vsi_handle))
3903 return ICE_ERR_PARAM;
3905 ice_acquire_lock(&pi->sched_lock);
3907 q_ctx = ice_get_lan_q_ctx(hw, vsi_handle, tc, q_handle);
3909 ice_debug(hw, ICE_DBG_SCHED, "Enaq: invalid queue handle %d\n",
3911 status = ICE_ERR_PARAM;
3915 /* find a parent node */
3916 parent = ice_sched_get_free_qparent(pi, vsi_handle, tc,
3917 ICE_SCHED_NODE_OWNER_LAN);
3919 status = ICE_ERR_PARAM;
3923 buf->parent_teid = parent->info.node_teid;
3924 node.parent_teid = parent->info.node_teid;
3925 /* Mark that the values in the "generic" section as valid. The default
3926 * value in the "generic" section is zero. This means that :
3927 * - Scheduling mode is Bytes Per Second (BPS), indicated by Bit 0.
3928 * - 0 priority among siblings, indicated by Bit 1-3.
3929 * - WFQ, indicated by Bit 4.
3930 * - 0 Adjustment value is used in PSM credit update flow, indicated by
3932 * - Bit 7 is reserved.
3933 * Without setting the generic section as valid in valid_sections, the
3934 * Admin queue command will fail with error code ICE_AQ_RC_EINVAL.
3936 buf->txqs[0].info.valid_sections = ICE_AQC_ELEM_VALID_GENERIC;
3938 /* add the LAN queue */
3939 status = ice_aq_add_lan_txq(hw, num_qgrps, buf, buf_size, cd);
3940 if (status != ICE_SUCCESS) {
3941 ice_debug(hw, ICE_DBG_SCHED, "enable queue %d failed %d\n",
3942 LE16_TO_CPU(buf->txqs[0].txq_id),
3943 hw->adminq.sq_last_status);
3947 node.node_teid = buf->txqs[0].q_teid;
3948 node.data.elem_type = ICE_AQC_ELEM_TYPE_LEAF;
3949 q_ctx->q_handle = q_handle;
3950 q_ctx->q_teid = LE32_TO_CPU(node.node_teid);
3952 /* add a leaf node into scheduler tree queue layer */
3953 status = ice_sched_add_node(pi, hw->num_tx_sched_layers - 1, &node);
3955 status = ice_sched_replay_q_bw(pi, q_ctx);
3958 ice_release_lock(&pi->sched_lock);
3964 * @pi: port information structure
3965 * @vsi_handle: software VSI handle
3967 * @num_queues: number of queues
3968 * @q_handles: pointer to software queue handle array
3969 * @q_ids: pointer to the q_id array
3970 * @q_teids: pointer to queue node teids
3971 * @rst_src: if called due to reset, specifies the reset source
3972 * @vmvf_num: the relative VM or VF number that is undergoing the reset
3973 * @cd: pointer to command details structure or NULL
3975 * This function removes queues and their corresponding nodes in SW DB
3978 ice_dis_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u8 num_queues,
3979 u16 *q_handles, u16 *q_ids, u32 *q_teids,
3980 enum ice_disq_rst_src rst_src, u16 vmvf_num,
3981 struct ice_sq_cd *cd)
3983 enum ice_status status = ICE_ERR_DOES_NOT_EXIST;
3984 struct ice_aqc_dis_txq_item qg_list;
3985 struct ice_q_ctx *q_ctx;
3988 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY)
3992 /* if queue is disabled already yet the disable queue command
3993 * has to be sent to complete the VF reset, then call
3994 * ice_aq_dis_lan_txq without any queue information
3997 return ice_aq_dis_lan_txq(pi->hw, 0, NULL, 0, rst_src,
4002 ice_acquire_lock(&pi->sched_lock);
4004 for (i = 0; i < num_queues; i++) {
4005 struct ice_sched_node *node;
4007 node = ice_sched_find_node_by_teid(pi->root, q_teids[i]);
4010 q_ctx = ice_get_lan_q_ctx(pi->hw, vsi_handle, tc, q_handles[i]);
4012 ice_debug(pi->hw, ICE_DBG_SCHED, "invalid queue handle%d\n",
4016 if (q_ctx->q_handle != q_handles[i]) {
4017 ice_debug(pi->hw, ICE_DBG_SCHED, "Err:handles %d %d\n",
4018 q_ctx->q_handle, q_handles[i]);
4021 qg_list.parent_teid = node->info.parent_teid;
4023 qg_list.q_id[0] = CPU_TO_LE16(q_ids[i]);
4024 status = ice_aq_dis_lan_txq(pi->hw, 1, &qg_list,
4025 sizeof(qg_list), rst_src, vmvf_num,
4028 if (status != ICE_SUCCESS)
4030 ice_free_sched_node(pi, node);
4031 q_ctx->q_handle = ICE_INVAL_Q_HANDLE;
4033 ice_release_lock(&pi->sched_lock);
4038 * ice_cfg_vsi_qs - configure the new/existing VSI queues
4039 * @pi: port information structure
4040 * @vsi_handle: software VSI handle
4041 * @tc_bitmap: TC bitmap
4042 * @maxqs: max queues array per TC
4043 * @owner: LAN or RDMA
4045 * This function adds/updates the VSI queues per TC.
4047 static enum ice_status
4048 ice_cfg_vsi_qs(struct ice_port_info *pi, u16 vsi_handle, u16 tc_bitmap,
4049 u16 *maxqs, u8 owner)
4051 enum ice_status status = ICE_SUCCESS;
4054 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY)
4057 if (!ice_is_vsi_valid(pi->hw, vsi_handle))
4058 return ICE_ERR_PARAM;
4060 ice_acquire_lock(&pi->sched_lock);
4062 ice_for_each_traffic_class(i) {
4063 /* configuration is possible only if TC node is present */
4064 if (!ice_sched_get_tc_node(pi, i))
4067 status = ice_sched_cfg_vsi(pi, vsi_handle, i, maxqs[i], owner,
4068 ice_is_tc_ena(tc_bitmap, i));
4073 ice_release_lock(&pi->sched_lock);
4078 * ice_cfg_vsi_lan - configure VSI LAN queues
4079 * @pi: port information structure
4080 * @vsi_handle: software VSI handle
4081 * @tc_bitmap: TC bitmap
4082 * @max_lanqs: max LAN queues array per TC
4084 * This function adds/updates the VSI LAN queues per TC.
4087 ice_cfg_vsi_lan(struct ice_port_info *pi, u16 vsi_handle, u16 tc_bitmap,
4090 return ice_cfg_vsi_qs(pi, vsi_handle, tc_bitmap, max_lanqs,
4091 ICE_SCHED_NODE_OWNER_LAN);
4095 * ice_replay_pre_init - replay pre initialization
4096 * @hw: pointer to the HW struct
4098 * Initializes required config data for VSI, FD, ACL, and RSS before replay.
4100 static enum ice_status ice_replay_pre_init(struct ice_hw *hw)
4102 struct ice_switch_info *sw = hw->switch_info;
4105 /* Delete old entries from replay filter list head if there is any */
4106 ice_rm_all_sw_replay_rule_info(hw);
4107 /* In start of replay, move entries into replay_rules list, it
4108 * will allow adding rules entries back to filt_rules list,
4109 * which is operational list.
4111 for (i = 0; i < ICE_MAX_NUM_RECIPES; i++)
4112 LIST_REPLACE_INIT(&sw->recp_list[i].filt_rules,
4113 &sw->recp_list[i].filt_replay_rules);
4114 ice_sched_replay_agg_vsi_preinit(hw);
4116 return ice_sched_replay_tc_node_bw(hw->port_info);
4120 * ice_replay_vsi - replay VSI configuration
4121 * @hw: pointer to the HW struct
4122 * @vsi_handle: driver VSI handle
4124 * Restore all VSI configuration after reset. It is required to call this
4125 * function with main VSI first.
4127 enum ice_status ice_replay_vsi(struct ice_hw *hw, u16 vsi_handle)
4129 enum ice_status status;
4131 if (!ice_is_vsi_valid(hw, vsi_handle))
4132 return ICE_ERR_PARAM;
4134 /* Replay pre-initialization if there is any */
4135 if (vsi_handle == ICE_MAIN_VSI_HANDLE) {
4136 status = ice_replay_pre_init(hw);
4140 /* Replay per VSI all RSS configurations */
4141 status = ice_replay_rss_cfg(hw, vsi_handle);
4144 /* Replay per VSI all filters */
4145 status = ice_replay_vsi_all_fltr(hw, vsi_handle);
4147 status = ice_replay_vsi_agg(hw, vsi_handle);
4152 * ice_replay_post - post replay configuration cleanup
4153 * @hw: pointer to the HW struct
4155 * Post replay cleanup.
4157 void ice_replay_post(struct ice_hw *hw)
4159 /* Delete old entries from replay filter list head */
4160 ice_rm_all_sw_replay_rule_info(hw);
4161 ice_sched_replay_agg(hw);
4165 * ice_stat_update40 - read 40 bit stat from the chip and update stat values
4166 * @hw: ptr to the hardware info
4167 * @reg: offset of 64 bit HW register to read from
4168 * @prev_stat_loaded: bool to specify if previous stats are loaded
4169 * @prev_stat: ptr to previous loaded stat value
4170 * @cur_stat: ptr to current stat value
4173 ice_stat_update40(struct ice_hw *hw, u32 reg, bool prev_stat_loaded,
4174 u64 *prev_stat, u64 *cur_stat)
4176 u64 new_data = rd64(hw, reg) & (BIT_ULL(40) - 1);
4178 /* device stats are not reset at PFR, they likely will not be zeroed
4179 * when the driver starts. Thus, save the value from the first read
4180 * without adding to the statistic value so that we report stats which
4181 * count up from zero.
4183 if (!prev_stat_loaded) {
4184 *prev_stat = new_data;
4188 /* Calculate the difference between the new and old values, and then
4189 * add it to the software stat value.
4191 if (new_data >= *prev_stat)
4192 *cur_stat += new_data - *prev_stat;
4194 /* to manage the potential roll-over */
4195 *cur_stat += (new_data + BIT_ULL(40)) - *prev_stat;
4197 /* Update the previously stored value to prepare for next read */
4198 *prev_stat = new_data;
4202 * ice_stat_update32 - read 32 bit stat from the chip and update stat values
4203 * @hw: ptr to the hardware info
4204 * @reg: offset of HW register to read from
4205 * @prev_stat_loaded: bool to specify if previous stats are loaded
4206 * @prev_stat: ptr to previous loaded stat value
4207 * @cur_stat: ptr to current stat value
4210 ice_stat_update32(struct ice_hw *hw, u32 reg, bool prev_stat_loaded,
4211 u64 *prev_stat, u64 *cur_stat)
4215 new_data = rd32(hw, reg);
4217 /* device stats are not reset at PFR, they likely will not be zeroed
4218 * when the driver starts. Thus, save the value from the first read
4219 * without adding to the statistic value so that we report stats which
4220 * count up from zero.
4222 if (!prev_stat_loaded) {
4223 *prev_stat = new_data;
4227 /* Calculate the difference between the new and old values, and then
4228 * add it to the software stat value.
4230 if (new_data >= *prev_stat)
4231 *cur_stat += new_data - *prev_stat;
4233 /* to manage the potential roll-over */
4234 *cur_stat += (new_data + BIT_ULL(32)) - *prev_stat;
4236 /* Update the previously stored value to prepare for next read */
4237 *prev_stat = new_data;
4241 * ice_stat_update_repc - read GLV_REPC stats from chip and update stat values
4242 * @hw: ptr to the hardware info
4243 * @vsi_handle: VSI handle
4244 * @prev_stat_loaded: bool to specify if the previous stat values are loaded
4245 * @cur_stats: ptr to current stats structure
4247 * The GLV_REPC statistic register actually tracks two 16bit statistics, and
4248 * thus cannot be read using the normal ice_stat_update32 function.
4250 * Read the GLV_REPC register associated with the given VSI, and update the
4251 * rx_no_desc and rx_error values in the ice_eth_stats structure.
4253 * Because the statistics in GLV_REPC stick at 0xFFFF, the register must be
4254 * cleared each time it's read.
4256 * Note that the GLV_RDPC register also counts the causes that would trigger
4257 * GLV_REPC. However, it does not give the finer grained detail about why the
4258 * packets are being dropped. The GLV_REPC values can be used to distinguish
4259 * whether Rx packets are dropped due to errors or due to no available
4263 ice_stat_update_repc(struct ice_hw *hw, u16 vsi_handle, bool prev_stat_loaded,
4264 struct ice_eth_stats *cur_stats)
4266 u16 vsi_num, no_desc, error_cnt;
4269 if (!ice_is_vsi_valid(hw, vsi_handle))
4272 vsi_num = ice_get_hw_vsi_num(hw, vsi_handle);
4274 /* If we haven't loaded stats yet, just clear the current value */
4275 if (!prev_stat_loaded) {
4276 wr32(hw, GLV_REPC(vsi_num), 0);
4280 repc = rd32(hw, GLV_REPC(vsi_num));
4281 no_desc = (repc & GLV_REPC_NO_DESC_CNT_M) >> GLV_REPC_NO_DESC_CNT_S;
4282 error_cnt = (repc & GLV_REPC_ERROR_CNT_M) >> GLV_REPC_ERROR_CNT_S;
4284 /* Clear the count by writing to the stats register */
4285 wr32(hw, GLV_REPC(vsi_num), 0);
4287 cur_stats->rx_no_desc += no_desc;
4288 cur_stats->rx_errors += error_cnt;
4292 * ice_sched_query_elem - query element information from HW
4293 * @hw: pointer to the HW struct
4294 * @node_teid: node TEID to be queried
4295 * @buf: buffer to element information
4297 * This function queries HW element information
4300 ice_sched_query_elem(struct ice_hw *hw, u32 node_teid,
4301 struct ice_aqc_get_elem *buf)
4303 u16 buf_size, num_elem_ret = 0;
4304 enum ice_status status;
4306 buf_size = sizeof(*buf);
4307 ice_memset(buf, 0, buf_size, ICE_NONDMA_MEM);
4308 buf->generic[0].node_teid = CPU_TO_LE32(node_teid);
4309 status = ice_aq_query_sched_elems(hw, 1, buf, buf_size, &num_elem_ret,
4311 if (status != ICE_SUCCESS || num_elem_ret != 1)
4312 ice_debug(hw, ICE_DBG_SCHED, "query element failed\n");
4317 * ice_get_fw_mode - returns FW mode
4318 * @hw: pointer to the HW struct
4320 enum ice_fw_modes ice_get_fw_mode(struct ice_hw *hw)
4322 #define ICE_FW_MODE_DBG_M BIT(0)
4323 #define ICE_FW_MODE_REC_M BIT(1)
4324 #define ICE_FW_MODE_ROLLBACK_M BIT(2)
4327 /* check the current FW mode */
4328 fw_mode = rd32(hw, GL_MNG_FWSM) & GL_MNG_FWSM_FW_MODES_M;
4330 if (fw_mode & ICE_FW_MODE_DBG_M)
4331 return ICE_FW_MODE_DBG;
4332 else if (fw_mode & ICE_FW_MODE_REC_M)
4333 return ICE_FW_MODE_REC;
4334 else if (fw_mode & ICE_FW_MODE_ROLLBACK_M)
4335 return ICE_FW_MODE_ROLLBACK;
4337 return ICE_FW_MODE_NORMAL;
4341 * ice_fw_supports_link_override
4342 * @hw: pointer to the hardware structure
4344 * Checks if the firmware supports link override
4346 bool ice_fw_supports_link_override(struct ice_hw *hw)
4348 if (hw->api_maj_ver == ICE_FW_API_LINK_OVERRIDE_MAJ) {
4349 if (hw->api_min_ver > ICE_FW_API_LINK_OVERRIDE_MIN)
4351 if (hw->api_min_ver == ICE_FW_API_LINK_OVERRIDE_MIN &&
4352 hw->api_patch >= ICE_FW_API_LINK_OVERRIDE_PATCH)
4354 } else if (hw->api_maj_ver > ICE_FW_API_LINK_OVERRIDE_MAJ) {
4362 * ice_get_link_default_override
4363 * @ldo: pointer to the link default override struct
4364 * @pi: pointer to the port info struct
4366 * Gets the link default override for a port
4369 ice_get_link_default_override(struct ice_link_default_override_tlv *ldo,
4370 struct ice_port_info *pi)
4372 u16 i, tlv, tlv_len, tlv_start, buf, offset;
4373 struct ice_hw *hw = pi->hw;
4374 enum ice_status status;
4376 status = ice_get_pfa_module_tlv(hw, &tlv, &tlv_len,
4377 ICE_SR_LINK_DEFAULT_OVERRIDE_PTR);
4379 ice_debug(hw, ICE_DBG_INIT,
4380 "Failed to read link override TLV.\n");
4384 /* Each port has its own config; calculate for our port */
4385 tlv_start = tlv + pi->lport * ICE_SR_PFA_LINK_OVERRIDE_WORDS +
4386 ICE_SR_PFA_LINK_OVERRIDE_OFFSET;
4388 /* link options first */
4389 status = ice_read_sr_word(hw, tlv_start, &buf);
4391 ice_debug(hw, ICE_DBG_INIT,
4392 "Failed to read override link options.\n");
4395 ldo->options = buf & ICE_LINK_OVERRIDE_OPT_M;
4396 ldo->phy_config = (buf & ICE_LINK_OVERRIDE_PHY_CFG_M) >>
4397 ICE_LINK_OVERRIDE_PHY_CFG_S;
4399 /* link PHY config */
4400 offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_FEC_OFFSET;
4401 status = ice_read_sr_word(hw, offset, &buf);
4403 ice_debug(hw, ICE_DBG_INIT,
4404 "Failed to read override phy config.\n");
4407 ldo->fec_options = buf & ICE_LINK_OVERRIDE_FEC_OPT_M;
4410 offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_PHY_OFFSET;
4411 for (i = 0; i < ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS; i++) {
4412 status = ice_read_sr_word(hw, (offset + i), &buf);
4414 ice_debug(hw, ICE_DBG_INIT,
4415 "Failed to read override link options.\n");
4418 /* shift 16 bits at a time to fill 64 bits */
4419 ldo->phy_type_low |= ((u64)buf << (i * 16));
4422 /* PHY types high */
4423 offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_PHY_OFFSET +
4424 ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS;
4425 for (i = 0; i < ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS; i++) {
4426 status = ice_read_sr_word(hw, (offset + i), &buf);
4428 ice_debug(hw, ICE_DBG_INIT,
4429 "Failed to read override link options.\n");
4432 /* shift 16 bits at a time to fill 64 bits */
4433 ldo->phy_type_high |= ((u64)buf << (i * 16));