1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2001-2019
5 #include "ice_common.h"
7 #include "ice_adminq_cmd.h"
10 #include "ice_switch.h"
12 #define ICE_PF_RESET_WAIT_COUNT 200
14 #define ICE_PROG_FLEX_ENTRY(hw, rxdid, mdid, idx) \
15 wr32((hw), GLFLXP_RXDID_FLX_WRD_##idx(rxdid), \
16 ((ICE_RX_OPC_MDID << \
17 GLFLXP_RXDID_FLX_WRD_##idx##_RXDID_OPCODE_S) & \
18 GLFLXP_RXDID_FLX_WRD_##idx##_RXDID_OPCODE_M) | \
19 (((mdid) << GLFLXP_RXDID_FLX_WRD_##idx##_PROT_MDID_S) & \
20 GLFLXP_RXDID_FLX_WRD_##idx##_PROT_MDID_M))
22 #define ICE_PROG_FLG_ENTRY(hw, rxdid, flg_0, flg_1, flg_2, flg_3, idx) \
23 wr32((hw), GLFLXP_RXDID_FLAGS(rxdid, idx), \
24 (((flg_0) << GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_S) & \
25 GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_M) | \
26 (((flg_1) << GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_1_S) & \
27 GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_1_M) | \
28 (((flg_2) << GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_2_S) & \
29 GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_2_M) | \
30 (((flg_3) << GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_3_S) & \
31 GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_3_M))
35 * ice_set_mac_type - Sets MAC type
36 * @hw: pointer to the HW structure
38 * This function sets the MAC type of the adapter based on the
39 * vendor ID and device ID stored in the HW structure.
41 static enum ice_status ice_set_mac_type(struct ice_hw *hw)
43 enum ice_status status = ICE_SUCCESS;
45 ice_debug(hw, ICE_DBG_TRACE, "ice_set_mac_type\n");
47 if (hw->vendor_id == ICE_INTEL_VENDOR_ID) {
48 switch (hw->device_id) {
50 hw->mac_type = ICE_MAC_GENERIC;
54 status = ICE_ERR_DEVICE_NOT_SUPPORTED;
57 ice_debug(hw, ICE_DBG_INIT, "found mac_type: %d, status: %d\n",
58 hw->mac_type, status);
65 * ice_clear_pf_cfg - Clear PF configuration
66 * @hw: pointer to the hardware structure
68 * Clears any existing PF configuration (VSIs, VSI lists, switch rules, port
69 * configuration, flow director filters, etc.).
71 enum ice_status ice_clear_pf_cfg(struct ice_hw *hw)
73 struct ice_aq_desc desc;
75 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pf_cfg);
77 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
81 * ice_aq_manage_mac_read - manage MAC address read command
82 * @hw: pointer to the HW struct
83 * @buf: a virtual buffer to hold the manage MAC read response
84 * @buf_size: Size of the virtual buffer
85 * @cd: pointer to command details structure or NULL
87 * This function is used to return per PF station MAC address (0x0107).
88 * NOTE: Upon successful completion of this command, MAC address information
89 * is returned in user specified buffer. Please interpret user specified
90 * buffer as "manage_mac_read" response.
91 * Response such as various MAC addresses are stored in HW struct (port.mac)
92 * ice_aq_discover_caps is expected to be called before this function is called.
94 static enum ice_status
95 ice_aq_manage_mac_read(struct ice_hw *hw, void *buf, u16 buf_size,
98 struct ice_aqc_manage_mac_read_resp *resp;
99 struct ice_aqc_manage_mac_read *cmd;
100 struct ice_aq_desc desc;
101 enum ice_status status;
105 cmd = &desc.params.mac_read;
107 if (buf_size < sizeof(*resp))
108 return ICE_ERR_BUF_TOO_SHORT;
110 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_read);
112 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);
116 resp = (struct ice_aqc_manage_mac_read_resp *)buf;
117 flags = LE16_TO_CPU(cmd->flags) & ICE_AQC_MAN_MAC_READ_M;
119 if (!(flags & ICE_AQC_MAN_MAC_LAN_ADDR_VALID)) {
120 ice_debug(hw, ICE_DBG_LAN, "got invalid MAC address\n");
124 /* A single port can report up to two (LAN and WoL) addresses */
125 for (i = 0; i < cmd->num_addr; i++)
126 if (resp[i].addr_type == ICE_AQC_MAN_MAC_ADDR_TYPE_LAN) {
127 ice_memcpy(hw->port_info->mac.lan_addr,
128 resp[i].mac_addr, ETH_ALEN,
130 ice_memcpy(hw->port_info->mac.perm_addr,
132 ETH_ALEN, ICE_DMA_TO_NONDMA);
140 * ice_aq_get_phy_caps - returns PHY capabilities
141 * @pi: port information structure
142 * @qual_mods: report qualified modules
143 * @report_mode: report mode capabilities
144 * @pcaps: structure for PHY capabilities to be filled
145 * @cd: pointer to command details structure or NULL
147 * Returns the various PHY capabilities supported on the Port (0x0600)
150 ice_aq_get_phy_caps(struct ice_port_info *pi, bool qual_mods, u8 report_mode,
151 struct ice_aqc_get_phy_caps_data *pcaps,
152 struct ice_sq_cd *cd)
154 struct ice_aqc_get_phy_caps *cmd;
155 u16 pcaps_size = sizeof(*pcaps);
156 struct ice_aq_desc desc;
157 enum ice_status status;
159 cmd = &desc.params.get_phy;
161 if (!pcaps || (report_mode & ~ICE_AQC_REPORT_MODE_M) || !pi)
162 return ICE_ERR_PARAM;
164 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_phy_caps);
167 cmd->param0 |= CPU_TO_LE16(ICE_AQC_GET_PHY_RQM);
169 cmd->param0 |= CPU_TO_LE16(report_mode);
170 status = ice_aq_send_cmd(pi->hw, &desc, pcaps, pcaps_size, cd);
172 if (status == ICE_SUCCESS && report_mode == ICE_AQC_REPORT_TOPO_CAP) {
173 pi->phy.phy_type_low = LE64_TO_CPU(pcaps->phy_type_low);
174 pi->phy.phy_type_high = LE64_TO_CPU(pcaps->phy_type_high);
181 * ice_get_media_type - Gets media type
182 * @pi: port information structure
184 static enum ice_media_type ice_get_media_type(struct ice_port_info *pi)
186 struct ice_link_status *hw_link_info;
189 return ICE_MEDIA_UNKNOWN;
191 hw_link_info = &pi->phy.link_info;
192 if (hw_link_info->phy_type_low && hw_link_info->phy_type_high)
193 /* If more than one media type is selected, report unknown */
194 return ICE_MEDIA_UNKNOWN;
196 if (hw_link_info->phy_type_low) {
197 switch (hw_link_info->phy_type_low) {
198 case ICE_PHY_TYPE_LOW_1000BASE_SX:
199 case ICE_PHY_TYPE_LOW_1000BASE_LX:
200 case ICE_PHY_TYPE_LOW_10GBASE_SR:
201 case ICE_PHY_TYPE_LOW_10GBASE_LR:
202 case ICE_PHY_TYPE_LOW_10G_SFI_C2C:
203 case ICE_PHY_TYPE_LOW_25GBASE_SR:
204 case ICE_PHY_TYPE_LOW_25GBASE_LR:
205 case ICE_PHY_TYPE_LOW_25G_AUI_C2C:
206 case ICE_PHY_TYPE_LOW_40GBASE_SR4:
207 case ICE_PHY_TYPE_LOW_40GBASE_LR4:
208 case ICE_PHY_TYPE_LOW_50GBASE_SR2:
209 case ICE_PHY_TYPE_LOW_50GBASE_LR2:
210 case ICE_PHY_TYPE_LOW_50GBASE_SR:
211 case ICE_PHY_TYPE_LOW_50GBASE_FR:
212 case ICE_PHY_TYPE_LOW_50GBASE_LR:
213 case ICE_PHY_TYPE_LOW_100GBASE_SR4:
214 case ICE_PHY_TYPE_LOW_100GBASE_LR4:
215 case ICE_PHY_TYPE_LOW_100GBASE_SR2:
216 case ICE_PHY_TYPE_LOW_100GBASE_DR:
217 return ICE_MEDIA_FIBER;
218 case ICE_PHY_TYPE_LOW_100BASE_TX:
219 case ICE_PHY_TYPE_LOW_1000BASE_T:
220 case ICE_PHY_TYPE_LOW_2500BASE_T:
221 case ICE_PHY_TYPE_LOW_5GBASE_T:
222 case ICE_PHY_TYPE_LOW_10GBASE_T:
223 case ICE_PHY_TYPE_LOW_25GBASE_T:
224 return ICE_MEDIA_BASET;
225 case ICE_PHY_TYPE_LOW_10G_SFI_DA:
226 case ICE_PHY_TYPE_LOW_25GBASE_CR:
227 case ICE_PHY_TYPE_LOW_25GBASE_CR_S:
228 case ICE_PHY_TYPE_LOW_25GBASE_CR1:
229 case ICE_PHY_TYPE_LOW_40GBASE_CR4:
230 case ICE_PHY_TYPE_LOW_50GBASE_CR2:
231 case ICE_PHY_TYPE_LOW_50GBASE_CP:
232 case ICE_PHY_TYPE_LOW_100GBASE_CR4:
233 case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4:
234 case ICE_PHY_TYPE_LOW_100GBASE_CP2:
236 case ICE_PHY_TYPE_LOW_1000BASE_KX:
237 case ICE_PHY_TYPE_LOW_2500BASE_KX:
238 case ICE_PHY_TYPE_LOW_2500BASE_X:
239 case ICE_PHY_TYPE_LOW_5GBASE_KR:
240 case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1:
241 case ICE_PHY_TYPE_LOW_25GBASE_KR:
242 case ICE_PHY_TYPE_LOW_25GBASE_KR1:
243 case ICE_PHY_TYPE_LOW_25GBASE_KR_S:
244 case ICE_PHY_TYPE_LOW_40GBASE_KR4:
245 case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4:
246 case ICE_PHY_TYPE_LOW_50GBASE_KR2:
247 case ICE_PHY_TYPE_LOW_100GBASE_KR4:
248 case ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4:
249 return ICE_MEDIA_BACKPLANE;
252 switch (hw_link_info->phy_type_high) {
253 case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4:
254 return ICE_MEDIA_BACKPLANE;
257 return ICE_MEDIA_UNKNOWN;
261 * ice_aq_get_link_info
262 * @pi: port information structure
263 * @ena_lse: enable/disable LinkStatusEvent reporting
264 * @link: pointer to link status structure - optional
265 * @cd: pointer to command details structure or NULL
267 * Get Link Status (0x607). Returns the link status of the adapter.
270 ice_aq_get_link_info(struct ice_port_info *pi, bool ena_lse,
271 struct ice_link_status *link, struct ice_sq_cd *cd)
273 struct ice_link_status *hw_link_info_old, *hw_link_info;
274 struct ice_aqc_get_link_status_data link_data = { 0 };
275 struct ice_aqc_get_link_status *resp;
276 enum ice_media_type *hw_media_type;
277 struct ice_fc_info *hw_fc_info;
278 bool tx_pause, rx_pause;
279 struct ice_aq_desc desc;
280 enum ice_status status;
284 return ICE_ERR_PARAM;
285 hw_link_info_old = &pi->phy.link_info_old;
286 hw_media_type = &pi->phy.media_type;
287 hw_link_info = &pi->phy.link_info;
288 hw_fc_info = &pi->fc;
290 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_status);
291 cmd_flags = (ena_lse) ? ICE_AQ_LSE_ENA : ICE_AQ_LSE_DIS;
292 resp = &desc.params.get_link_status;
293 resp->cmd_flags = CPU_TO_LE16(cmd_flags);
294 resp->lport_num = pi->lport;
296 status = ice_aq_send_cmd(pi->hw, &desc, &link_data, sizeof(link_data),
299 if (status != ICE_SUCCESS)
302 /* save off old link status information */
303 *hw_link_info_old = *hw_link_info;
305 /* update current link status information */
306 hw_link_info->link_speed = LE16_TO_CPU(link_data.link_speed);
307 hw_link_info->phy_type_low = LE64_TO_CPU(link_data.phy_type_low);
308 hw_link_info->phy_type_high = LE64_TO_CPU(link_data.phy_type_high);
309 *hw_media_type = ice_get_media_type(pi);
310 hw_link_info->link_info = link_data.link_info;
311 hw_link_info->an_info = link_data.an_info;
312 hw_link_info->ext_info = link_data.ext_info;
313 hw_link_info->max_frame_size = LE16_TO_CPU(link_data.max_frame_size);
314 hw_link_info->fec_info = link_data.cfg & ICE_AQ_FEC_MASK;
315 hw_link_info->topo_media_conflict = link_data.topo_media_conflict;
316 hw_link_info->pacing = link_data.cfg & ICE_AQ_CFG_PACING_M;
319 tx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_TX);
320 rx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_RX);
321 if (tx_pause && rx_pause)
322 hw_fc_info->current_mode = ICE_FC_FULL;
324 hw_fc_info->current_mode = ICE_FC_TX_PAUSE;
326 hw_fc_info->current_mode = ICE_FC_RX_PAUSE;
328 hw_fc_info->current_mode = ICE_FC_NONE;
330 hw_link_info->lse_ena =
331 !!(resp->cmd_flags & CPU_TO_LE16(ICE_AQ_LSE_IS_ENABLED));
334 /* save link status information */
336 *link = *hw_link_info;
338 /* flag cleared so calling functions don't call AQ again */
339 pi->phy.get_link_info = false;
345 * ice_init_flex_flags
346 * @hw: pointer to the hardware structure
347 * @prof_id: Rx Descriptor Builder profile ID
349 * Function to initialize Rx flex flags
351 static void ice_init_flex_flags(struct ice_hw *hw, enum ice_rxdid prof_id)
355 /* Flex-flag fields (0-2) are programmed with FLG64 bits with layout:
356 * flexiflags0[5:0] - TCP flags, is_packet_fragmented, is_packet_UDP_GRE
357 * flexiflags1[3:0] - Not used for flag programming
358 * flexiflags2[7:0] - Tunnel and VLAN types
359 * 2 invalid fields in last index
362 /* Rx flex flags are currently programmed for the NIC profiles only.
363 * Different flag bit programming configurations can be added per
366 case ICE_RXDID_FLEX_NIC:
367 case ICE_RXDID_FLEX_NIC_2:
368 ICE_PROG_FLG_ENTRY(hw, prof_id, ICE_FLG_PKT_FRG,
369 ICE_FLG_UDP_GRE, ICE_FLG_PKT_DSI,
371 /* flex flag 1 is not used for flexi-flag programming, skipping
372 * these four FLG64 bits.
374 ICE_PROG_FLG_ENTRY(hw, prof_id, ICE_FLG_SYN, ICE_FLG_RST,
375 ICE_FLG_PKT_DSI, ICE_FLG_PKT_DSI, idx++);
376 ICE_PROG_FLG_ENTRY(hw, prof_id, ICE_FLG_PKT_DSI,
377 ICE_FLG_PKT_DSI, ICE_FLG_EVLAN_x8100,
378 ICE_FLG_EVLAN_x9100, idx++);
379 ICE_PROG_FLG_ENTRY(hw, prof_id, ICE_FLG_VLAN_x8100,
380 ICE_FLG_TNL_VLAN, ICE_FLG_TNL_MAC,
381 ICE_FLG_TNL0, idx++);
382 ICE_PROG_FLG_ENTRY(hw, prof_id, ICE_FLG_TNL1, ICE_FLG_TNL2,
383 ICE_FLG_PKT_DSI, ICE_FLG_PKT_DSI, idx);
387 ice_debug(hw, ICE_DBG_INIT,
388 "Flag programming for profile ID %d not supported\n",
395 * @hw: pointer to the hardware structure
396 * @prof_id: Rx Descriptor Builder profile ID
398 * Function to initialize flex descriptors
400 static void ice_init_flex_flds(struct ice_hw *hw, enum ice_rxdid prof_id)
402 enum ice_flex_mdid mdid;
405 case ICE_RXDID_FLEX_NIC:
406 case ICE_RXDID_FLEX_NIC_2:
407 ICE_PROG_FLEX_ENTRY(hw, prof_id, ICE_MDID_RX_HASH_LOW, 0);
408 ICE_PROG_FLEX_ENTRY(hw, prof_id, ICE_MDID_RX_HASH_HIGH, 1);
409 ICE_PROG_FLEX_ENTRY(hw, prof_id, ICE_MDID_FLOW_ID_LOWER, 2);
411 mdid = (prof_id == ICE_RXDID_FLEX_NIC_2) ?
412 ICE_MDID_SRC_VSI : ICE_MDID_FLOW_ID_HIGH;
414 ICE_PROG_FLEX_ENTRY(hw, prof_id, mdid, 3);
416 ice_init_flex_flags(hw, prof_id);
420 ice_debug(hw, ICE_DBG_INIT,
421 "Field init for profile ID %d not supported\n",
428 * @hw: pointer to the HW struct
429 * @max_frame_size: Maximum Frame Size to be supported
430 * @cd: pointer to command details structure or NULL
432 * Set MAC configuration (0x0603)
435 ice_aq_set_mac_cfg(struct ice_hw *hw, u16 max_frame_size, struct ice_sq_cd *cd)
437 u16 fc_threshold_val, tx_timer_val;
438 struct ice_aqc_set_mac_cfg *cmd;
439 struct ice_port_info *pi;
440 struct ice_aq_desc desc;
441 enum ice_status status;
446 cmd = &desc.params.set_mac_cfg;
448 if (max_frame_size == 0)
449 return ICE_ERR_PARAM;
451 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_mac_cfg);
453 cmd->max_frame_size = CPU_TO_LE16(max_frame_size);
455 /* Retrieve the current data_pacing value in FW*/
456 pi = &hw->port_info[port_num];
458 /* We turn on the get_link_info so that ice_update_link_info(...)
461 pi->phy.get_link_info = 1;
463 status = ice_get_link_status(pi, &link_up);
468 cmd->params = pi->phy.link_info.pacing;
470 /* We read back the transmit timer and fc threshold value of
471 * LFC. Thus, we will use index =
472 * PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX.
474 * Also, because we are opearating on transmit timer and fc
475 * threshold of LFC, we don't turn on any bit in tx_tmr_priority
477 #define IDX_OF_LFC PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX
479 /* Retrieve the transmit timer */
481 PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(IDX_OF_LFC));
482 tx_timer_val = reg_val &
483 PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_HSEC_CTL_TX_PAUSE_QUANTA_M;
484 cmd->tx_tmr_value = CPU_TO_LE16(tx_timer_val);
486 /* Retrieve the fc threshold */
488 PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(IDX_OF_LFC));
489 fc_threshold_val = reg_val & MAKEMASK(0xFFFF, 0);
490 cmd->fc_refresh_threshold = CPU_TO_LE16(fc_threshold_val);
492 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
496 * ice_init_fltr_mgmt_struct - initializes filter management list and locks
497 * @hw: pointer to the HW struct
499 static enum ice_status ice_init_fltr_mgmt_struct(struct ice_hw *hw)
501 struct ice_switch_info *sw;
503 hw->switch_info = (struct ice_switch_info *)
504 ice_malloc(hw, sizeof(*hw->switch_info));
505 sw = hw->switch_info;
508 return ICE_ERR_NO_MEMORY;
510 INIT_LIST_HEAD(&sw->vsi_list_map_head);
512 return ice_init_def_sw_recp(hw);
516 * ice_cleanup_fltr_mgmt_struct - cleanup filter management list and locks
517 * @hw: pointer to the HW struct
519 static void ice_cleanup_fltr_mgmt_struct(struct ice_hw *hw)
521 struct ice_switch_info *sw = hw->switch_info;
522 struct ice_vsi_list_map_info *v_pos_map;
523 struct ice_vsi_list_map_info *v_tmp_map;
524 struct ice_sw_recipe *recps;
527 LIST_FOR_EACH_ENTRY_SAFE(v_pos_map, v_tmp_map, &sw->vsi_list_map_head,
528 ice_vsi_list_map_info, list_entry) {
529 LIST_DEL(&v_pos_map->list_entry);
530 ice_free(hw, v_pos_map);
532 recps = hw->switch_info->recp_list;
533 for (i = 0; i < ICE_MAX_NUM_RECIPES; i++) {
534 recps[i].root_rid = i;
536 if (recps[i].adv_rule) {
537 struct ice_adv_fltr_mgmt_list_entry *tmp_entry;
538 struct ice_adv_fltr_mgmt_list_entry *lst_itr;
540 ice_destroy_lock(&recps[i].filt_rule_lock);
541 LIST_FOR_EACH_ENTRY_SAFE(lst_itr, tmp_entry,
542 &recps[i].filt_rules,
543 ice_adv_fltr_mgmt_list_entry,
545 LIST_DEL(&lst_itr->list_entry);
546 ice_free(hw, lst_itr->lkups);
547 ice_free(hw, lst_itr);
550 struct ice_fltr_mgmt_list_entry *lst_itr, *tmp_entry;
552 ice_destroy_lock(&recps[i].filt_rule_lock);
553 LIST_FOR_EACH_ENTRY_SAFE(lst_itr, tmp_entry,
554 &recps[i].filt_rules,
555 ice_fltr_mgmt_list_entry,
557 LIST_DEL(&lst_itr->list_entry);
558 ice_free(hw, lst_itr);
562 ice_rm_all_sw_replay_rule_info(hw);
563 ice_free(hw, sw->recp_list);
567 #define ICE_FW_LOG_DESC_SIZE(n) (sizeof(struct ice_aqc_fw_logging_data) + \
568 (((n) - 1) * sizeof(((struct ice_aqc_fw_logging_data *)0)->entry)))
569 #define ICE_FW_LOG_DESC_SIZE_MAX \
570 ICE_FW_LOG_DESC_SIZE(ICE_AQC_FW_LOG_ID_MAX)
573 * ice_cfg_fw_log - configure FW logging
574 * @hw: pointer to the HW struct
575 * @enable: enable certain FW logging events if true, disable all if false
577 * This function enables/disables the FW logging via Rx CQ events and a UART
578 * port based on predetermined configurations. FW logging via the Rx CQ can be
579 * enabled/disabled for individual PF's. However, FW logging via the UART can
580 * only be enabled/disabled for all PFs on the same device.
582 * To enable overall FW logging, the "cq_en" and "uart_en" enable bits in
583 * hw->fw_log need to be set accordingly, e.g. based on user-provided input,
584 * before initializing the device.
586 * When re/configuring FW logging, callers need to update the "cfg" elements of
587 * the hw->fw_log.evnts array with the desired logging event configurations for
588 * modules of interest. When disabling FW logging completely, the callers can
589 * just pass false in the "enable" parameter. On completion, the function will
590 * update the "cur" element of the hw->fw_log.evnts array with the resulting
591 * logging event configurations of the modules that are being re/configured. FW
592 * logging modules that are not part of a reconfiguration operation retain their
595 * Before resetting the device, it is recommended that the driver disables FW
596 * logging before shutting down the control queue. When disabling FW logging
597 * ("enable" = false), the latest configurations of FW logging events stored in
598 * hw->fw_log.evnts[] are not overridden to allow them to be reconfigured after
601 * When enabling FW logging to emit log messages via the Rx CQ during the
602 * device's initialization phase, a mechanism alternative to interrupt handlers
603 * needs to be used to extract FW log messages from the Rx CQ periodically and
604 * to prevent the Rx CQ from being full and stalling other types of control
605 * messages from FW to SW. Interrupts are typically disabled during the device's
606 * initialization phase.
608 static enum ice_status ice_cfg_fw_log(struct ice_hw *hw, bool enable)
610 struct ice_aqc_fw_logging_data *data = NULL;
611 struct ice_aqc_fw_logging *cmd;
612 enum ice_status status = ICE_SUCCESS;
613 u16 i, chgs = 0, len = 0;
614 struct ice_aq_desc desc;
618 if (!hw->fw_log.cq_en && !hw->fw_log.uart_en)
621 /* Disable FW logging only when the control queue is still responsive */
623 (!hw->fw_log.actv_evnts || !ice_check_sq_alive(hw, &hw->adminq)))
626 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_fw_logging);
627 cmd = &desc.params.fw_logging;
629 /* Indicate which controls are valid */
630 if (hw->fw_log.cq_en)
631 cmd->log_ctrl_valid |= ICE_AQC_FW_LOG_AQ_VALID;
633 if (hw->fw_log.uart_en)
634 cmd->log_ctrl_valid |= ICE_AQC_FW_LOG_UART_VALID;
637 /* Fill in an array of entries with FW logging modules and
638 * logging events being reconfigured.
640 for (i = 0; i < ICE_AQC_FW_LOG_ID_MAX; i++) {
643 /* Keep track of enabled event types */
644 actv_evnts |= hw->fw_log.evnts[i].cfg;
646 if (hw->fw_log.evnts[i].cfg == hw->fw_log.evnts[i].cur)
650 data = (struct ice_aqc_fw_logging_data *)
652 ICE_FW_LOG_DESC_SIZE_MAX);
654 return ICE_ERR_NO_MEMORY;
657 val = i << ICE_AQC_FW_LOG_ID_S;
658 val |= hw->fw_log.evnts[i].cfg << ICE_AQC_FW_LOG_EN_S;
659 data->entry[chgs++] = CPU_TO_LE16(val);
662 /* Only enable FW logging if at least one module is specified.
663 * If FW logging is currently enabled but all modules are not
664 * enabled to emit log messages, disable FW logging altogether.
667 /* Leave if there is effectively no change */
671 if (hw->fw_log.cq_en)
672 cmd->log_ctrl |= ICE_AQC_FW_LOG_AQ_EN;
674 if (hw->fw_log.uart_en)
675 cmd->log_ctrl |= ICE_AQC_FW_LOG_UART_EN;
678 len = ICE_FW_LOG_DESC_SIZE(chgs);
679 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
683 status = ice_aq_send_cmd(hw, &desc, buf, len, NULL);
685 /* Update the current configuration to reflect events enabled.
686 * hw->fw_log.cq_en and hw->fw_log.uart_en indicate if the FW
687 * logging mode is enabled for the device. They do not reflect
688 * actual modules being enabled to emit log messages. So, their
689 * values remain unchanged even when all modules are disabled.
691 u16 cnt = enable ? chgs : (u16)ICE_AQC_FW_LOG_ID_MAX;
693 hw->fw_log.actv_evnts = actv_evnts;
694 for (i = 0; i < cnt; i++) {
698 /* When disabling all FW logging events as part
699 * of device's de-initialization, the original
700 * configurations are retained, and can be used
701 * to reconfigure FW logging later if the device
704 hw->fw_log.evnts[i].cur = 0;
708 v = LE16_TO_CPU(data->entry[i]);
709 m = (v & ICE_AQC_FW_LOG_ID_M) >> ICE_AQC_FW_LOG_ID_S;
710 hw->fw_log.evnts[m].cur = hw->fw_log.evnts[m].cfg;
723 * @hw: pointer to the HW struct
724 * @desc: pointer to the AQ message descriptor
725 * @buf: pointer to the buffer accompanying the AQ message
727 * Formats a FW Log message and outputs it via the standard driver logs.
729 void ice_output_fw_log(struct ice_hw *hw, struct ice_aq_desc *desc, void *buf)
731 ice_debug(hw, ICE_DBG_AQ_MSG, "[ FW Log Msg Start ]\n");
732 ice_debug_array(hw, ICE_DBG_AQ_MSG, 16, 1, (u8 *)buf,
733 LE16_TO_CPU(desc->datalen));
734 ice_debug(hw, ICE_DBG_AQ_MSG, "[ FW Log Msg End ]\n");
738 * ice_get_itr_intrl_gran - determine int/intrl granularity
739 * @hw: pointer to the HW struct
741 * Determines the itr/intrl granularities based on the maximum aggregate
742 * bandwidth according to the device's configuration during power-on.
744 static void ice_get_itr_intrl_gran(struct ice_hw *hw)
746 u8 max_agg_bw = (rd32(hw, GL_PWR_MODE_CTL) &
747 GL_PWR_MODE_CTL_CAR_MAX_BW_M) >>
748 GL_PWR_MODE_CTL_CAR_MAX_BW_S;
750 switch (max_agg_bw) {
751 case ICE_MAX_AGG_BW_200G:
752 case ICE_MAX_AGG_BW_100G:
753 case ICE_MAX_AGG_BW_50G:
754 hw->itr_gran = ICE_ITR_GRAN_ABOVE_25;
755 hw->intrl_gran = ICE_INTRL_GRAN_ABOVE_25;
757 case ICE_MAX_AGG_BW_25G:
758 hw->itr_gran = ICE_ITR_GRAN_MAX_25;
759 hw->intrl_gran = ICE_INTRL_GRAN_MAX_25;
765 * ice_init_hw - main hardware initialization routine
766 * @hw: pointer to the hardware structure
768 enum ice_status ice_init_hw(struct ice_hw *hw)
770 struct ice_aqc_get_phy_caps_data *pcaps;
771 enum ice_status status;
775 ice_debug(hw, ICE_DBG_TRACE, "ice_init_hw");
778 /* Set MAC type based on DeviceID */
779 status = ice_set_mac_type(hw);
783 hw->pf_id = (u8)(rd32(hw, PF_FUNC_RID) &
784 PF_FUNC_RID_FUNCTION_NUMBER_M) >>
785 PF_FUNC_RID_FUNCTION_NUMBER_S;
788 status = ice_reset(hw, ICE_RESET_PFR);
792 ice_get_itr_intrl_gran(hw);
795 status = ice_init_all_ctrlq(hw);
797 goto err_unroll_cqinit;
799 /* Enable FW logging. Not fatal if this fails. */
800 status = ice_cfg_fw_log(hw, true);
802 ice_debug(hw, ICE_DBG_INIT, "Failed to enable FW logging.\n");
804 status = ice_clear_pf_cfg(hw);
806 goto err_unroll_cqinit;
809 ice_clear_pxe_mode(hw);
811 status = ice_init_nvm(hw);
813 goto err_unroll_cqinit;
815 status = ice_get_caps(hw);
817 goto err_unroll_cqinit;
819 hw->port_info = (struct ice_port_info *)
820 ice_malloc(hw, sizeof(*hw->port_info));
821 if (!hw->port_info) {
822 status = ICE_ERR_NO_MEMORY;
823 goto err_unroll_cqinit;
826 /* set the back pointer to HW */
827 hw->port_info->hw = hw;
829 /* Initialize port_info struct with switch configuration data */
830 status = ice_get_initial_sw_cfg(hw);
832 goto err_unroll_alloc;
836 /* Query the allocated resources for Tx scheduler */
837 status = ice_sched_query_res_alloc(hw);
839 ice_debug(hw, ICE_DBG_SCHED,
840 "Failed to get scheduler allocated resources\n");
841 goto err_unroll_alloc;
845 /* Initialize port_info struct with scheduler data */
846 status = ice_sched_init_port(hw->port_info);
848 goto err_unroll_sched;
850 pcaps = (struct ice_aqc_get_phy_caps_data *)
851 ice_malloc(hw, sizeof(*pcaps));
853 status = ICE_ERR_NO_MEMORY;
854 goto err_unroll_sched;
857 /* Initialize port_info struct with PHY capabilities */
858 status = ice_aq_get_phy_caps(hw->port_info, false,
859 ICE_AQC_REPORT_TOPO_CAP, pcaps, NULL);
862 goto err_unroll_sched;
864 /* Initialize port_info struct with link information */
865 status = ice_aq_get_link_info(hw->port_info, false, NULL, NULL);
867 goto err_unroll_sched;
868 /* need a valid SW entry point to build a Tx tree */
869 if (!hw->sw_entry_point_layer) {
870 ice_debug(hw, ICE_DBG_SCHED, "invalid sw entry point\n");
871 status = ICE_ERR_CFG;
872 goto err_unroll_sched;
874 INIT_LIST_HEAD(&hw->agg_list);
875 /* Initialize max burst size */
876 if (!hw->max_burst_size)
877 ice_cfg_rl_burst_size(hw, ICE_SCHED_DFLT_BURST_SIZE);
879 status = ice_init_fltr_mgmt_struct(hw);
881 goto err_unroll_sched;
884 /* Get MAC information */
885 /* A single port can report up to two (LAN and WoL) addresses */
886 mac_buf = ice_calloc(hw, 2,
887 sizeof(struct ice_aqc_manage_mac_read_resp));
888 mac_buf_len = 2 * sizeof(struct ice_aqc_manage_mac_read_resp);
891 status = ICE_ERR_NO_MEMORY;
892 goto err_unroll_fltr_mgmt_struct;
895 status = ice_aq_manage_mac_read(hw, mac_buf, mac_buf_len, NULL);
896 ice_free(hw, mac_buf);
899 goto err_unroll_fltr_mgmt_struct;
901 ice_init_flex_flds(hw, ICE_RXDID_FLEX_NIC);
902 ice_init_flex_flds(hw, ICE_RXDID_FLEX_NIC_2);
907 err_unroll_fltr_mgmt_struct:
908 ice_cleanup_fltr_mgmt_struct(hw);
910 ice_sched_cleanup_all(hw);
912 ice_free(hw, hw->port_info);
913 hw->port_info = NULL;
915 ice_shutdown_all_ctrlq(hw);
920 * ice_deinit_hw - unroll initialization operations done by ice_init_hw
921 * @hw: pointer to the hardware structure
923 * This should be called only during nominal operation, not as a result of
924 * ice_init_hw() failing since ice_init_hw() will take care of unrolling
925 * applicable initializations if it fails for any reason.
927 void ice_deinit_hw(struct ice_hw *hw)
929 ice_cleanup_fltr_mgmt_struct(hw);
931 ice_sched_cleanup_all(hw);
932 ice_sched_clear_agg(hw);
936 ice_free(hw, hw->port_info);
937 hw->port_info = NULL;
940 /* Attempt to disable FW logging before shutting down control queues */
941 ice_cfg_fw_log(hw, false);
942 ice_shutdown_all_ctrlq(hw);
944 /* Clear VSI contexts if not already cleared */
945 ice_clear_all_vsi_ctx(hw);
949 * ice_check_reset - Check to see if a global reset is complete
950 * @hw: pointer to the hardware structure
952 enum ice_status ice_check_reset(struct ice_hw *hw)
954 u32 cnt, reg = 0, grst_delay;
956 /* Poll for Device Active state in case a recent CORER, GLOBR,
957 * or EMPR has occurred. The grst delay value is in 100ms units.
958 * Add 1sec for outstanding AQ commands that can take a long time.
960 #define GLGEN_RSTCTL 0x000B8180 /* Reset Source: POR */
961 #define GLGEN_RSTCTL_GRSTDEL_S 0
962 #define GLGEN_RSTCTL_GRSTDEL_M MAKEMASK(0x3F, GLGEN_RSTCTL_GRSTDEL_S)
963 grst_delay = ((rd32(hw, GLGEN_RSTCTL) & GLGEN_RSTCTL_GRSTDEL_M) >>
964 GLGEN_RSTCTL_GRSTDEL_S) + 10;
966 for (cnt = 0; cnt < grst_delay; cnt++) {
967 ice_msec_delay(100, true);
968 reg = rd32(hw, GLGEN_RSTAT);
969 if (!(reg & GLGEN_RSTAT_DEVSTATE_M))
973 if (cnt == grst_delay) {
974 ice_debug(hw, ICE_DBG_INIT,
975 "Global reset polling failed to complete.\n");
976 return ICE_ERR_RESET_FAILED;
979 #define ICE_RESET_DONE_MASK (GLNVM_ULD_CORER_DONE_M | \
980 GLNVM_ULD_GLOBR_DONE_M)
982 /* Device is Active; check Global Reset processes are done */
983 for (cnt = 0; cnt < ICE_PF_RESET_WAIT_COUNT; cnt++) {
984 reg = rd32(hw, GLNVM_ULD) & ICE_RESET_DONE_MASK;
985 if (reg == ICE_RESET_DONE_MASK) {
986 ice_debug(hw, ICE_DBG_INIT,
987 "Global reset processes done. %d\n", cnt);
990 ice_msec_delay(10, true);
993 if (cnt == ICE_PF_RESET_WAIT_COUNT) {
994 ice_debug(hw, ICE_DBG_INIT,
995 "Wait for Reset Done timed out. GLNVM_ULD = 0x%x\n",
997 return ICE_ERR_RESET_FAILED;
1004 * ice_pf_reset - Reset the PF
1005 * @hw: pointer to the hardware structure
1007 * If a global reset has been triggered, this function checks
1008 * for its completion and then issues the PF reset
1010 static enum ice_status ice_pf_reset(struct ice_hw *hw)
1014 /* If at function entry a global reset was already in progress, i.e.
1015 * state is not 'device active' or any of the reset done bits are not
1016 * set in GLNVM_ULD, there is no need for a PF Reset; poll until the
1017 * global reset is done.
1019 if ((rd32(hw, GLGEN_RSTAT) & GLGEN_RSTAT_DEVSTATE_M) ||
1020 (rd32(hw, GLNVM_ULD) & ICE_RESET_DONE_MASK) ^ ICE_RESET_DONE_MASK) {
1021 /* poll on global reset currently in progress until done */
1022 if (ice_check_reset(hw))
1023 return ICE_ERR_RESET_FAILED;
1029 reg = rd32(hw, PFGEN_CTRL);
1031 wr32(hw, PFGEN_CTRL, (reg | PFGEN_CTRL_PFSWR_M));
1033 for (cnt = 0; cnt < ICE_PF_RESET_WAIT_COUNT; cnt++) {
1034 reg = rd32(hw, PFGEN_CTRL);
1035 if (!(reg & PFGEN_CTRL_PFSWR_M))
1038 ice_msec_delay(1, true);
1041 if (cnt == ICE_PF_RESET_WAIT_COUNT) {
1042 ice_debug(hw, ICE_DBG_INIT,
1043 "PF reset polling failed to complete.\n");
1044 return ICE_ERR_RESET_FAILED;
1051 * ice_reset - Perform different types of reset
1052 * @hw: pointer to the hardware structure
1053 * @req: reset request
1055 * This function triggers a reset as specified by the req parameter.
1058 * If anything other than a PF reset is triggered, PXE mode is restored.
1059 * This has to be cleared using ice_clear_pxe_mode again, once the AQ
1060 * interface has been restored in the rebuild flow.
1062 enum ice_status ice_reset(struct ice_hw *hw, enum ice_reset_req req)
1068 return ice_pf_reset(hw);
1069 case ICE_RESET_CORER:
1070 ice_debug(hw, ICE_DBG_INIT, "CoreR requested\n");
1071 val = GLGEN_RTRIG_CORER_M;
1073 case ICE_RESET_GLOBR:
1074 ice_debug(hw, ICE_DBG_INIT, "GlobalR requested\n");
1075 val = GLGEN_RTRIG_GLOBR_M;
1078 return ICE_ERR_PARAM;
1081 val |= rd32(hw, GLGEN_RTRIG);
1082 wr32(hw, GLGEN_RTRIG, val);
1086 /* wait for the FW to be ready */
1087 return ice_check_reset(hw);
1093 * ice_copy_rxq_ctx_to_hw
1094 * @hw: pointer to the hardware structure
1095 * @ice_rxq_ctx: pointer to the rxq context
1096 * @rxq_index: the index of the Rx queue
1098 * Copies rxq context from dense structure to HW register space
1100 static enum ice_status
1101 ice_copy_rxq_ctx_to_hw(struct ice_hw *hw, u8 *ice_rxq_ctx, u32 rxq_index)
1106 return ICE_ERR_BAD_PTR;
1108 if (rxq_index > QRX_CTRL_MAX_INDEX)
1109 return ICE_ERR_PARAM;
1111 /* Copy each dword separately to HW */
1112 for (i = 0; i < ICE_RXQ_CTX_SIZE_DWORDS; i++) {
1113 wr32(hw, QRX_CONTEXT(i, rxq_index),
1114 *((u32 *)(ice_rxq_ctx + (i * sizeof(u32)))));
1116 ice_debug(hw, ICE_DBG_QCTX, "qrxdata[%d]: %08X\n", i,
1117 *((u32 *)(ice_rxq_ctx + (i * sizeof(u32)))));
1123 /* LAN Rx Queue Context */
1124 static const struct ice_ctx_ele ice_rlan_ctx_info[] = {
1125 /* Field Width LSB */
1126 ICE_CTX_STORE(ice_rlan_ctx, head, 13, 0),
1127 ICE_CTX_STORE(ice_rlan_ctx, cpuid, 8, 13),
1128 ICE_CTX_STORE(ice_rlan_ctx, base, 57, 32),
1129 ICE_CTX_STORE(ice_rlan_ctx, qlen, 13, 89),
1130 ICE_CTX_STORE(ice_rlan_ctx, dbuf, 7, 102),
1131 ICE_CTX_STORE(ice_rlan_ctx, hbuf, 5, 109),
1132 ICE_CTX_STORE(ice_rlan_ctx, dtype, 2, 114),
1133 ICE_CTX_STORE(ice_rlan_ctx, dsize, 1, 116),
1134 ICE_CTX_STORE(ice_rlan_ctx, crcstrip, 1, 117),
1135 ICE_CTX_STORE(ice_rlan_ctx, l2tsel, 1, 119),
1136 ICE_CTX_STORE(ice_rlan_ctx, hsplit_0, 4, 120),
1137 ICE_CTX_STORE(ice_rlan_ctx, hsplit_1, 2, 124),
1138 ICE_CTX_STORE(ice_rlan_ctx, showiv, 1, 127),
1139 ICE_CTX_STORE(ice_rlan_ctx, rxmax, 14, 174),
1140 ICE_CTX_STORE(ice_rlan_ctx, tphrdesc_ena, 1, 193),
1141 ICE_CTX_STORE(ice_rlan_ctx, tphwdesc_ena, 1, 194),
1142 ICE_CTX_STORE(ice_rlan_ctx, tphdata_ena, 1, 195),
1143 ICE_CTX_STORE(ice_rlan_ctx, tphhead_ena, 1, 196),
1144 ICE_CTX_STORE(ice_rlan_ctx, lrxqthresh, 3, 198),
1150 * @hw: pointer to the hardware structure
1151 * @rlan_ctx: pointer to the rxq context
1152 * @rxq_index: the index of the Rx queue
1154 * Converts rxq context from sparse to dense structure and then writes
1155 * it to HW register space
1158 ice_write_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx,
1161 u8 ctx_buf[ICE_RXQ_CTX_SZ] = { 0 };
1163 ice_set_ctx((u8 *)rlan_ctx, ctx_buf, ice_rlan_ctx_info);
1164 return ice_copy_rxq_ctx_to_hw(hw, ctx_buf, rxq_index);
1167 #if !defined(NO_UNUSED_CTX_CODE) || defined(AE_DRIVER)
1170 * @hw: pointer to the hardware structure
1171 * @rxq_index: the index of the Rx queue to clear
1173 * Clears rxq context in HW register space
1175 enum ice_status ice_clear_rxq_ctx(struct ice_hw *hw, u32 rxq_index)
1179 if (rxq_index > QRX_CTRL_MAX_INDEX)
1180 return ICE_ERR_PARAM;
1182 /* Clear each dword register separately */
1183 for (i = 0; i < ICE_RXQ_CTX_SIZE_DWORDS; i++)
1184 wr32(hw, QRX_CONTEXT(i, rxq_index), 0);
1188 #endif /* !NO_UNUSED_CTX_CODE || AE_DRIVER */
1190 /* LAN Tx Queue Context */
1191 const struct ice_ctx_ele ice_tlan_ctx_info[] = {
1192 /* Field Width LSB */
1193 ICE_CTX_STORE(ice_tlan_ctx, base, 57, 0),
1194 ICE_CTX_STORE(ice_tlan_ctx, port_num, 3, 57),
1195 ICE_CTX_STORE(ice_tlan_ctx, cgd_num, 5, 60),
1196 ICE_CTX_STORE(ice_tlan_ctx, pf_num, 3, 65),
1197 ICE_CTX_STORE(ice_tlan_ctx, vmvf_num, 10, 68),
1198 ICE_CTX_STORE(ice_tlan_ctx, vmvf_type, 2, 78),
1199 ICE_CTX_STORE(ice_tlan_ctx, src_vsi, 10, 80),
1200 ICE_CTX_STORE(ice_tlan_ctx, tsyn_ena, 1, 90),
1201 ICE_CTX_STORE(ice_tlan_ctx, alt_vlan, 1, 92),
1202 ICE_CTX_STORE(ice_tlan_ctx, cpuid, 8, 93),
1203 ICE_CTX_STORE(ice_tlan_ctx, wb_mode, 1, 101),
1204 ICE_CTX_STORE(ice_tlan_ctx, tphrd_desc, 1, 102),
1205 ICE_CTX_STORE(ice_tlan_ctx, tphrd, 1, 103),
1206 ICE_CTX_STORE(ice_tlan_ctx, tphwr_desc, 1, 104),
1207 ICE_CTX_STORE(ice_tlan_ctx, cmpq_id, 9, 105),
1208 ICE_CTX_STORE(ice_tlan_ctx, qnum_in_func, 14, 114),
1209 ICE_CTX_STORE(ice_tlan_ctx, itr_notification_mode, 1, 128),
1210 ICE_CTX_STORE(ice_tlan_ctx, adjust_prof_id, 6, 129),
1211 ICE_CTX_STORE(ice_tlan_ctx, qlen, 13, 135),
1212 ICE_CTX_STORE(ice_tlan_ctx, quanta_prof_idx, 4, 148),
1213 ICE_CTX_STORE(ice_tlan_ctx, tso_ena, 1, 152),
1214 ICE_CTX_STORE(ice_tlan_ctx, tso_qnum, 11, 153),
1215 ICE_CTX_STORE(ice_tlan_ctx, legacy_int, 1, 164),
1216 ICE_CTX_STORE(ice_tlan_ctx, drop_ena, 1, 165),
1217 ICE_CTX_STORE(ice_tlan_ctx, cache_prof_idx, 2, 166),
1218 ICE_CTX_STORE(ice_tlan_ctx, pkt_shaper_prof_idx, 3, 168),
1219 ICE_CTX_STORE(ice_tlan_ctx, int_q_state, 110, 171),
1223 #if !defined(NO_UNUSED_CTX_CODE) || defined(AE_DRIVER)
1225 * ice_copy_tx_cmpltnq_ctx_to_hw
1226 * @hw: pointer to the hardware structure
1227 * @ice_tx_cmpltnq_ctx: pointer to the Tx completion queue context
1228 * @tx_cmpltnq_index: the index of the completion queue
1230 * Copies Tx completion queue context from dense structure to HW register space
1232 static enum ice_status
1233 ice_copy_tx_cmpltnq_ctx_to_hw(struct ice_hw *hw, u8 *ice_tx_cmpltnq_ctx,
1234 u32 tx_cmpltnq_index)
1238 if (!ice_tx_cmpltnq_ctx)
1239 return ICE_ERR_BAD_PTR;
1241 if (tx_cmpltnq_index > GLTCLAN_CQ_CNTX0_MAX_INDEX)
1242 return ICE_ERR_PARAM;
1244 /* Copy each dword separately to HW */
1245 for (i = 0; i < ICE_TX_CMPLTNQ_CTX_SIZE_DWORDS; i++) {
1246 wr32(hw, GLTCLAN_CQ_CNTX(i, tx_cmpltnq_index),
1247 *((u32 *)(ice_tx_cmpltnq_ctx + (i * sizeof(u32)))));
1249 ice_debug(hw, ICE_DBG_QCTX, "cmpltnqdata[%d]: %08X\n", i,
1250 *((u32 *)(ice_tx_cmpltnq_ctx + (i * sizeof(u32)))));
1256 /* LAN Tx Completion Queue Context */
1257 static const struct ice_ctx_ele ice_tx_cmpltnq_ctx_info[] = {
1258 /* Field Width LSB */
1259 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, base, 57, 0),
1260 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, q_len, 18, 64),
1261 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, generation, 1, 96),
1262 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, wrt_ptr, 22, 97),
1263 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, pf_num, 3, 128),
1264 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, vmvf_num, 10, 131),
1265 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, vmvf_type, 2, 141),
1266 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, tph_desc_wr, 1, 160),
1267 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, cpuid, 8, 161),
1268 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, cmpltn_cache, 512, 192),
1273 * ice_write_tx_cmpltnq_ctx
1274 * @hw: pointer to the hardware structure
1275 * @tx_cmpltnq_ctx: pointer to the completion queue context
1276 * @tx_cmpltnq_index: the index of the completion queue
1278 * Converts completion queue context from sparse to dense structure and then
1279 * writes it to HW register space
1282 ice_write_tx_cmpltnq_ctx(struct ice_hw *hw,
1283 struct ice_tx_cmpltnq_ctx *tx_cmpltnq_ctx,
1284 u32 tx_cmpltnq_index)
1286 u8 ctx_buf[ICE_TX_CMPLTNQ_CTX_SIZE_DWORDS * sizeof(u32)] = { 0 };
1288 ice_set_ctx((u8 *)tx_cmpltnq_ctx, ctx_buf, ice_tx_cmpltnq_ctx_info);
1289 return ice_copy_tx_cmpltnq_ctx_to_hw(hw, ctx_buf, tx_cmpltnq_index);
1293 * ice_clear_tx_cmpltnq_ctx
1294 * @hw: pointer to the hardware structure
1295 * @tx_cmpltnq_index: the index of the completion queue to clear
1297 * Clears Tx completion queue context in HW register space
1300 ice_clear_tx_cmpltnq_ctx(struct ice_hw *hw, u32 tx_cmpltnq_index)
1304 if (tx_cmpltnq_index > GLTCLAN_CQ_CNTX0_MAX_INDEX)
1305 return ICE_ERR_PARAM;
1307 /* Clear each dword register separately */
1308 for (i = 0; i < ICE_TX_CMPLTNQ_CTX_SIZE_DWORDS; i++)
1309 wr32(hw, GLTCLAN_CQ_CNTX(i, tx_cmpltnq_index), 0);
1315 * ice_copy_tx_drbell_q_ctx_to_hw
1316 * @hw: pointer to the hardware structure
1317 * @ice_tx_drbell_q_ctx: pointer to the doorbell queue context
1318 * @tx_drbell_q_index: the index of the doorbell queue
1320 * Copies doorbell queue context from dense structure to HW register space
1322 static enum ice_status
1323 ice_copy_tx_drbell_q_ctx_to_hw(struct ice_hw *hw, u8 *ice_tx_drbell_q_ctx,
1324 u32 tx_drbell_q_index)
1328 if (!ice_tx_drbell_q_ctx)
1329 return ICE_ERR_BAD_PTR;
1331 if (tx_drbell_q_index > QTX_COMM_DBLQ_DBELL_MAX_INDEX)
1332 return ICE_ERR_PARAM;
1334 /* Copy each dword separately to HW */
1335 for (i = 0; i < ICE_TX_DRBELL_Q_CTX_SIZE_DWORDS; i++) {
1336 wr32(hw, QTX_COMM_DBLQ_CNTX(i, tx_drbell_q_index),
1337 *((u32 *)(ice_tx_drbell_q_ctx + (i * sizeof(u32)))));
1339 ice_debug(hw, ICE_DBG_QCTX, "tx_drbell_qdata[%d]: %08X\n", i,
1340 *((u32 *)(ice_tx_drbell_q_ctx + (i * sizeof(u32)))));
1346 /* LAN Tx Doorbell Queue Context info */
1347 static const struct ice_ctx_ele ice_tx_drbell_q_ctx_info[] = {
1348 /* Field Width LSB */
1349 ICE_CTX_STORE(ice_tx_drbell_q_ctx, base, 57, 0),
1350 ICE_CTX_STORE(ice_tx_drbell_q_ctx, ring_len, 13, 64),
1351 ICE_CTX_STORE(ice_tx_drbell_q_ctx, pf_num, 3, 80),
1352 ICE_CTX_STORE(ice_tx_drbell_q_ctx, vf_num, 8, 84),
1353 ICE_CTX_STORE(ice_tx_drbell_q_ctx, vmvf_type, 2, 94),
1354 ICE_CTX_STORE(ice_tx_drbell_q_ctx, cpuid, 8, 96),
1355 ICE_CTX_STORE(ice_tx_drbell_q_ctx, tph_desc_rd, 1, 104),
1356 ICE_CTX_STORE(ice_tx_drbell_q_ctx, tph_desc_wr, 1, 108),
1357 ICE_CTX_STORE(ice_tx_drbell_q_ctx, db_q_en, 1, 112),
1358 ICE_CTX_STORE(ice_tx_drbell_q_ctx, rd_head, 13, 128),
1359 ICE_CTX_STORE(ice_tx_drbell_q_ctx, rd_tail, 13, 144),
1364 * ice_write_tx_drbell_q_ctx
1365 * @hw: pointer to the hardware structure
1366 * @tx_drbell_q_ctx: pointer to the doorbell queue context
1367 * @tx_drbell_q_index: the index of the doorbell queue
1369 * Converts doorbell queue context from sparse to dense structure and then
1370 * writes it to HW register space
1373 ice_write_tx_drbell_q_ctx(struct ice_hw *hw,
1374 struct ice_tx_drbell_q_ctx *tx_drbell_q_ctx,
1375 u32 tx_drbell_q_index)
1377 u8 ctx_buf[ICE_TX_DRBELL_Q_CTX_SIZE_DWORDS * sizeof(u32)] = { 0 };
1379 ice_set_ctx((u8 *)tx_drbell_q_ctx, ctx_buf, ice_tx_drbell_q_ctx_info);
1380 return ice_copy_tx_drbell_q_ctx_to_hw(hw, ctx_buf, tx_drbell_q_index);
1384 * ice_clear_tx_drbell_q_ctx
1385 * @hw: pointer to the hardware structure
1386 * @tx_drbell_q_index: the index of the doorbell queue to clear
1388 * Clears doorbell queue context in HW register space
1391 ice_clear_tx_drbell_q_ctx(struct ice_hw *hw, u32 tx_drbell_q_index)
1395 if (tx_drbell_q_index > QTX_COMM_DBLQ_DBELL_MAX_INDEX)
1396 return ICE_ERR_PARAM;
1398 /* Clear each dword register separately */
1399 for (i = 0; i < ICE_TX_DRBELL_Q_CTX_SIZE_DWORDS; i++)
1400 wr32(hw, QTX_COMM_DBLQ_CNTX(i, tx_drbell_q_index), 0);
1404 #endif /* !NO_UNUSED_CTX_CODE || AE_DRIVER */
1408 * @hw: pointer to the hardware structure
1410 * @desc: pointer to control queue descriptor
1411 * @buf: pointer to command buffer
1412 * @buf_len: max length of buf
1414 * Dumps debug log about control command with descriptor contents.
1417 ice_debug_cq(struct ice_hw *hw, u32 mask, void *desc, void *buf, u16 buf_len)
1419 struct ice_aq_desc *cq_desc = (struct ice_aq_desc *)desc;
1422 if (!(mask & hw->debug_mask))
1428 len = LE16_TO_CPU(cq_desc->datalen);
1431 "CQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
1432 LE16_TO_CPU(cq_desc->opcode),
1433 LE16_TO_CPU(cq_desc->flags),
1434 LE16_TO_CPU(cq_desc->datalen), LE16_TO_CPU(cq_desc->retval));
1435 ice_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n",
1436 LE32_TO_CPU(cq_desc->cookie_high),
1437 LE32_TO_CPU(cq_desc->cookie_low));
1438 ice_debug(hw, mask, "\tparam (0,1) 0x%08X 0x%08X\n",
1439 LE32_TO_CPU(cq_desc->params.generic.param0),
1440 LE32_TO_CPU(cq_desc->params.generic.param1));
1441 ice_debug(hw, mask, "\taddr (h,l) 0x%08X 0x%08X\n",
1442 LE32_TO_CPU(cq_desc->params.generic.addr_high),
1443 LE32_TO_CPU(cq_desc->params.generic.addr_low));
1444 if (buf && cq_desc->datalen != 0) {
1445 ice_debug(hw, mask, "Buffer:\n");
1449 ice_debug_array(hw, mask, 16, 1, (u8 *)buf, len);
1454 /* FW Admin Queue command wrappers */
1457 * ice_aq_send_cmd - send FW Admin Queue command to FW Admin Queue
1458 * @hw: pointer to the HW struct
1459 * @desc: descriptor describing the command
1460 * @buf: buffer to use for indirect commands (NULL for direct commands)
1461 * @buf_size: size of buffer for indirect commands (0 for direct commands)
1462 * @cd: pointer to command details structure
1464 * Helper function to send FW Admin Queue commands to the FW Admin Queue.
1467 ice_aq_send_cmd(struct ice_hw *hw, struct ice_aq_desc *desc, void *buf,
1468 u16 buf_size, struct ice_sq_cd *cd)
1470 return ice_sq_send_cmd(hw, &hw->adminq, desc, buf, buf_size, cd);
1475 * @hw: pointer to the HW struct
1476 * @cd: pointer to command details structure or NULL
1478 * Get the firmware version (0x0001) from the admin queue commands
1480 enum ice_status ice_aq_get_fw_ver(struct ice_hw *hw, struct ice_sq_cd *cd)
1482 struct ice_aqc_get_ver *resp;
1483 struct ice_aq_desc desc;
1484 enum ice_status status;
1486 resp = &desc.params.get_ver;
1488 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_ver);
1490 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
1493 hw->fw_branch = resp->fw_branch;
1494 hw->fw_maj_ver = resp->fw_major;
1495 hw->fw_min_ver = resp->fw_minor;
1496 hw->fw_patch = resp->fw_patch;
1497 hw->fw_build = LE32_TO_CPU(resp->fw_build);
1498 hw->api_branch = resp->api_branch;
1499 hw->api_maj_ver = resp->api_major;
1500 hw->api_min_ver = resp->api_minor;
1501 hw->api_patch = resp->api_patch;
1510 * @hw: pointer to the HW struct
1511 * @unloading: is the driver unloading itself
1513 * Tell the Firmware that we're shutting down the AdminQ and whether
1514 * or not the driver is unloading as well (0x0003).
1516 enum ice_status ice_aq_q_shutdown(struct ice_hw *hw, bool unloading)
1518 struct ice_aqc_q_shutdown *cmd;
1519 struct ice_aq_desc desc;
1521 cmd = &desc.params.q_shutdown;
1523 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_q_shutdown);
1526 cmd->driver_unloading = CPU_TO_LE32(ICE_AQC_DRIVER_UNLOADING);
1528 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
1533 * @hw: pointer to the HW struct
1535 * @access: access type
1536 * @sdp_number: resource number
1537 * @timeout: the maximum time in ms that the driver may hold the resource
1538 * @cd: pointer to command details structure or NULL
1540 * Requests common resource using the admin queue commands (0x0008).
1541 * When attempting to acquire the Global Config Lock, the driver can
1542 * learn of three states:
1543 * 1) ICE_SUCCESS - acquired lock, and can perform download package
1544 * 2) ICE_ERR_AQ_ERROR - did not get lock, driver should fail to load
1545 * 3) ICE_ERR_AQ_NO_WORK - did not get lock, but another driver has
1546 * successfully downloaded the package; the driver does
1547 * not have to download the package and can continue
1550 * Note that if the caller is in an acquire lock, perform action, release lock
1551 * phase of operation, it is possible that the FW may detect a timeout and issue
1552 * a CORER. In this case, the driver will receive a CORER interrupt and will
1553 * have to determine its cause. The calling thread that is handling this flow
1554 * will likely get an error propagated back to it indicating the Download
1555 * Package, Update Package or the Release Resource AQ commands timed out.
1557 static enum ice_status
1558 ice_aq_req_res(struct ice_hw *hw, enum ice_aq_res_ids res,
1559 enum ice_aq_res_access_type access, u8 sdp_number, u32 *timeout,
1560 struct ice_sq_cd *cd)
1562 struct ice_aqc_req_res *cmd_resp;
1563 struct ice_aq_desc desc;
1564 enum ice_status status;
1566 ice_debug(hw, ICE_DBG_TRACE, "ice_aq_req_res");
1568 cmd_resp = &desc.params.res_owner;
1570 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_req_res);
1572 cmd_resp->res_id = CPU_TO_LE16(res);
1573 cmd_resp->access_type = CPU_TO_LE16(access);
1574 cmd_resp->res_number = CPU_TO_LE32(sdp_number);
1575 cmd_resp->timeout = CPU_TO_LE32(*timeout);
1578 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
1580 /* The completion specifies the maximum time in ms that the driver
1581 * may hold the resource in the Timeout field.
1584 /* Global config lock response utilizes an additional status field.
1586 * If the Global config lock resource is held by some other driver, the
1587 * command completes with ICE_AQ_RES_GLBL_IN_PROG in the status field
1588 * and the timeout field indicates the maximum time the current owner
1589 * of the resource has to free it.
1591 if (res == ICE_GLOBAL_CFG_LOCK_RES_ID) {
1592 if (LE16_TO_CPU(cmd_resp->status) == ICE_AQ_RES_GLBL_SUCCESS) {
1593 *timeout = LE32_TO_CPU(cmd_resp->timeout);
1595 } else if (LE16_TO_CPU(cmd_resp->status) ==
1596 ICE_AQ_RES_GLBL_IN_PROG) {
1597 *timeout = LE32_TO_CPU(cmd_resp->timeout);
1598 return ICE_ERR_AQ_ERROR;
1599 } else if (LE16_TO_CPU(cmd_resp->status) ==
1600 ICE_AQ_RES_GLBL_DONE) {
1601 return ICE_ERR_AQ_NO_WORK;
1604 /* invalid FW response, force a timeout immediately */
1606 return ICE_ERR_AQ_ERROR;
1609 /* If the resource is held by some other driver, the command completes
1610 * with a busy return value and the timeout field indicates the maximum
1611 * time the current owner of the resource has to free it.
1613 if (!status || hw->adminq.sq_last_status == ICE_AQ_RC_EBUSY)
1614 *timeout = LE32_TO_CPU(cmd_resp->timeout);
1620 * ice_aq_release_res
1621 * @hw: pointer to the HW struct
1623 * @sdp_number: resource number
1624 * @cd: pointer to command details structure or NULL
1626 * release common resource using the admin queue commands (0x0009)
1628 static enum ice_status
1629 ice_aq_release_res(struct ice_hw *hw, enum ice_aq_res_ids res, u8 sdp_number,
1630 struct ice_sq_cd *cd)
1632 struct ice_aqc_req_res *cmd;
1633 struct ice_aq_desc desc;
1635 ice_debug(hw, ICE_DBG_TRACE, "ice_aq_release_res");
1637 cmd = &desc.params.res_owner;
1639 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_release_res);
1641 cmd->res_id = CPU_TO_LE16(res);
1642 cmd->res_number = CPU_TO_LE32(sdp_number);
1644 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
1649 * @hw: pointer to the HW structure
1651 * @access: access type (read or write)
1652 * @timeout: timeout in milliseconds
1654 * This function will attempt to acquire the ownership of a resource.
1657 ice_acquire_res(struct ice_hw *hw, enum ice_aq_res_ids res,
1658 enum ice_aq_res_access_type access, u32 timeout)
1660 #define ICE_RES_POLLING_DELAY_MS 10
1661 u32 delay = ICE_RES_POLLING_DELAY_MS;
1662 u32 time_left = timeout;
1663 enum ice_status status;
1665 ice_debug(hw, ICE_DBG_TRACE, "ice_acquire_res");
1667 status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL);
1669 /* A return code of ICE_ERR_AQ_NO_WORK means that another driver has
1670 * previously acquired the resource and performed any necessary updates;
1671 * in this case the caller does not obtain the resource and has no
1672 * further work to do.
1674 if (status == ICE_ERR_AQ_NO_WORK)
1675 goto ice_acquire_res_exit;
1678 ice_debug(hw, ICE_DBG_RES,
1679 "resource %d acquire type %d failed.\n", res, access);
1681 /* If necessary, poll until the current lock owner timeouts */
1682 timeout = time_left;
1683 while (status && timeout && time_left) {
1684 ice_msec_delay(delay, true);
1685 timeout = (timeout > delay) ? timeout - delay : 0;
1686 status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL);
1688 if (status == ICE_ERR_AQ_NO_WORK)
1689 /* lock free, but no work to do */
1696 if (status && status != ICE_ERR_AQ_NO_WORK)
1697 ice_debug(hw, ICE_DBG_RES, "resource acquire timed out.\n");
1699 ice_acquire_res_exit:
1700 if (status == ICE_ERR_AQ_NO_WORK) {
1701 if (access == ICE_RES_WRITE)
1702 ice_debug(hw, ICE_DBG_RES,
1703 "resource indicates no work to do.\n");
1705 ice_debug(hw, ICE_DBG_RES,
1706 "Warning: ICE_ERR_AQ_NO_WORK not expected\n");
1713 * @hw: pointer to the HW structure
1716 * This function will release a resource using the proper Admin Command.
1718 void ice_release_res(struct ice_hw *hw, enum ice_aq_res_ids res)
1720 enum ice_status status;
1721 u32 total_delay = 0;
1723 ice_debug(hw, ICE_DBG_TRACE, "ice_release_res");
1725 status = ice_aq_release_res(hw, res, 0, NULL);
1727 /* there are some rare cases when trying to release the resource
1728 * results in an admin queue timeout, so handle them correctly
1730 while ((status == ICE_ERR_AQ_TIMEOUT) &&
1731 (total_delay < hw->adminq.sq_cmd_timeout)) {
1732 ice_msec_delay(1, true);
1733 status = ice_aq_release_res(hw, res, 0, NULL);
1739 * ice_aq_alloc_free_res - command to allocate/free resources
1740 * @hw: pointer to the HW struct
1741 * @num_entries: number of resource entries in buffer
1742 * @buf: Indirect buffer to hold data parameters and response
1743 * @buf_size: size of buffer for indirect commands
1744 * @opc: pass in the command opcode
1745 * @cd: pointer to command details structure or NULL
1747 * Helper function to allocate/free resources using the admin queue commands
1750 ice_aq_alloc_free_res(struct ice_hw *hw, u16 num_entries,
1751 struct ice_aqc_alloc_free_res_elem *buf, u16 buf_size,
1752 enum ice_adminq_opc opc, struct ice_sq_cd *cd)
1754 struct ice_aqc_alloc_free_res_cmd *cmd;
1755 struct ice_aq_desc desc;
1757 ice_debug(hw, ICE_DBG_TRACE, "ice_aq_alloc_free_res");
1759 cmd = &desc.params.sw_res_ctrl;
1762 return ICE_ERR_PARAM;
1764 if (buf_size < (num_entries * sizeof(buf->elem[0])))
1765 return ICE_ERR_PARAM;
1767 ice_fill_dflt_direct_cmd_desc(&desc, opc);
1769 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
1771 cmd->num_entries = CPU_TO_LE16(num_entries);
1773 return ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);
1777 * ice_alloc_hw_res - allocate resource
1778 * @hw: pointer to the HW struct
1779 * @type: type of resource
1780 * @num: number of resources to allocate
1781 * @sh: shared if true, dedicated if false
1782 * @res: pointer to array that will receive the resources
1785 ice_alloc_hw_res(struct ice_hw *hw, u16 type, u16 num, bool sh, u16 *res)
1787 struct ice_aqc_alloc_free_res_elem *buf;
1788 enum ice_status status;
1791 buf_len = sizeof(*buf) + sizeof(buf->elem) * (num - 1);
1792 buf = (struct ice_aqc_alloc_free_res_elem *)
1793 ice_malloc(hw, buf_len);
1795 return ICE_ERR_NO_MEMORY;
1797 /* Prepare buffer to allocate resource. */
1798 buf->num_elems = CPU_TO_LE16(num);
1799 buf->res_type = CPU_TO_LE16(type | (sh ? ICE_AQC_RES_TYPE_FLAG_SHARED :
1800 ICE_AQC_RES_TYPE_FLAG_DEDICATED));
1801 status = ice_aq_alloc_free_res(hw, 1, buf, buf_len,
1802 ice_aqc_opc_alloc_res, NULL);
1804 goto ice_alloc_res_exit;
1806 ice_memcpy(res, buf->elem, sizeof(buf->elem) * num,
1807 ICE_NONDMA_TO_NONDMA);
1815 * ice_free_hw_res - free allocated HW resource
1816 * @hw: pointer to the HW struct
1817 * @type: type of resource to free
1818 * @num: number of resources
1819 * @res: pointer to array that contains the resources to free
1822 ice_free_hw_res(struct ice_hw *hw, u16 type, u16 num, u16 *res)
1824 struct ice_aqc_alloc_free_res_elem *buf;
1825 enum ice_status status;
1828 buf_len = sizeof(*buf) + sizeof(buf->elem) * (num - 1);
1829 buf = (struct ice_aqc_alloc_free_res_elem *)ice_malloc(hw, buf_len);
1831 return ICE_ERR_NO_MEMORY;
1833 /* Prepare buffer to free resource. */
1834 buf->num_elems = CPU_TO_LE16(num);
1835 buf->res_type = CPU_TO_LE16(type);
1836 ice_memcpy(buf->elem, res, sizeof(buf->elem) * num,
1837 ICE_NONDMA_TO_NONDMA);
1839 status = ice_aq_alloc_free_res(hw, num, buf, buf_len,
1840 ice_aqc_opc_free_res, NULL);
1842 ice_debug(hw, ICE_DBG_SW, "CQ CMD Buffer:\n");
1849 * ice_get_num_per_func - determine number of resources per PF
1850 * @hw: pointer to the HW structure
1851 * @max: value to be evenly split between each PF
1853 * Determine the number of valid functions by going through the bitmap returned
1854 * from parsing capabilities and use this to calculate the number of resources
1855 * per PF based on the max value passed in.
1857 static u32 ice_get_num_per_func(struct ice_hw *hw, u32 max)
1861 #define ICE_CAPS_VALID_FUNCS_M 0xFF
1862 funcs = ice_hweight8(hw->dev_caps.common_cap.valid_functions &
1863 ICE_CAPS_VALID_FUNCS_M);
1872 * ice_parse_caps - parse function/device capabilities
1873 * @hw: pointer to the HW struct
1874 * @buf: pointer to a buffer containing function/device capability records
1875 * @cap_count: number of capability records in the list
1876 * @opc: type of capabilities list to parse
1878 * Helper function to parse function(0x000a)/device(0x000b) capabilities list.
1881 ice_parse_caps(struct ice_hw *hw, void *buf, u32 cap_count,
1882 enum ice_adminq_opc opc)
1884 struct ice_aqc_list_caps_elem *cap_resp;
1885 struct ice_hw_func_caps *func_p = NULL;
1886 struct ice_hw_dev_caps *dev_p = NULL;
1887 struct ice_hw_common_caps *caps;
1893 cap_resp = (struct ice_aqc_list_caps_elem *)buf;
1895 if (opc == ice_aqc_opc_list_dev_caps) {
1896 dev_p = &hw->dev_caps;
1897 caps = &dev_p->common_cap;
1898 } else if (opc == ice_aqc_opc_list_func_caps) {
1899 func_p = &hw->func_caps;
1900 caps = &func_p->common_cap;
1902 ice_debug(hw, ICE_DBG_INIT, "wrong opcode\n");
1906 for (i = 0; caps && i < cap_count; i++, cap_resp++) {
1907 u32 logical_id = LE32_TO_CPU(cap_resp->logical_id);
1908 u32 phys_id = LE32_TO_CPU(cap_resp->phys_id);
1909 u32 number = LE32_TO_CPU(cap_resp->number);
1910 u16 cap = LE16_TO_CPU(cap_resp->cap);
1913 case ICE_AQC_CAPS_VALID_FUNCTIONS:
1914 caps->valid_functions = number;
1915 ice_debug(hw, ICE_DBG_INIT,
1916 "HW caps: Valid Functions = %d\n",
1917 caps->valid_functions);
1919 case ICE_AQC_CAPS_VSI:
1921 dev_p->num_vsi_allocd_to_host = number;
1922 ice_debug(hw, ICE_DBG_INIT,
1923 "HW caps: Dev.VSI cnt = %d\n",
1924 dev_p->num_vsi_allocd_to_host);
1925 } else if (func_p) {
1926 func_p->guar_num_vsi =
1927 ice_get_num_per_func(hw, ICE_MAX_VSI);
1928 ice_debug(hw, ICE_DBG_INIT,
1929 "HW caps: Func.VSI cnt = %d\n",
1933 case ICE_AQC_CAPS_RSS:
1934 caps->rss_table_size = number;
1935 caps->rss_table_entry_width = logical_id;
1936 ice_debug(hw, ICE_DBG_INIT,
1937 "HW caps: RSS table size = %d\n",
1938 caps->rss_table_size);
1939 ice_debug(hw, ICE_DBG_INIT,
1940 "HW caps: RSS table width = %d\n",
1941 caps->rss_table_entry_width);
1943 case ICE_AQC_CAPS_RXQS:
1944 caps->num_rxq = number;
1945 caps->rxq_first_id = phys_id;
1946 ice_debug(hw, ICE_DBG_INIT,
1947 "HW caps: Num Rx Qs = %d\n", caps->num_rxq);
1948 ice_debug(hw, ICE_DBG_INIT,
1949 "HW caps: Rx first queue ID = %d\n",
1950 caps->rxq_first_id);
1952 case ICE_AQC_CAPS_TXQS:
1953 caps->num_txq = number;
1954 caps->txq_first_id = phys_id;
1955 ice_debug(hw, ICE_DBG_INIT,
1956 "HW caps: Num Tx Qs = %d\n", caps->num_txq);
1957 ice_debug(hw, ICE_DBG_INIT,
1958 "HW caps: Tx first queue ID = %d\n",
1959 caps->txq_first_id);
1961 case ICE_AQC_CAPS_MSIX:
1962 caps->num_msix_vectors = number;
1963 caps->msix_vector_first_id = phys_id;
1964 ice_debug(hw, ICE_DBG_INIT,
1965 "HW caps: MSIX vector count = %d\n",
1966 caps->num_msix_vectors);
1967 ice_debug(hw, ICE_DBG_INIT,
1968 "HW caps: MSIX first vector index = %d\n",
1969 caps->msix_vector_first_id);
1971 case ICE_AQC_CAPS_MAX_MTU:
1972 caps->max_mtu = number;
1974 ice_debug(hw, ICE_DBG_INIT,
1975 "HW caps: Dev.MaxMTU = %d\n",
1978 ice_debug(hw, ICE_DBG_INIT,
1979 "HW caps: func.MaxMTU = %d\n",
1983 ice_debug(hw, ICE_DBG_INIT,
1984 "HW caps: Unknown capability[%d]: 0x%x\n", i,
1992 * ice_aq_discover_caps - query function/device capabilities
1993 * @hw: pointer to the HW struct
1994 * @buf: a virtual buffer to hold the capabilities
1995 * @buf_size: Size of the virtual buffer
1996 * @cap_count: cap count needed if AQ err==ENOMEM
1997 * @opc: capabilities type to discover - pass in the command opcode
1998 * @cd: pointer to command details structure or NULL
2000 * Get the function(0x000a)/device(0x000b) capabilities description from
2003 static enum ice_status
2004 ice_aq_discover_caps(struct ice_hw *hw, void *buf, u16 buf_size, u32 *cap_count,
2005 enum ice_adminq_opc opc, struct ice_sq_cd *cd)
2007 struct ice_aqc_list_caps *cmd;
2008 struct ice_aq_desc desc;
2009 enum ice_status status;
2011 cmd = &desc.params.get_cap;
2013 if (opc != ice_aqc_opc_list_func_caps &&
2014 opc != ice_aqc_opc_list_dev_caps)
2015 return ICE_ERR_PARAM;
2017 ice_fill_dflt_direct_cmd_desc(&desc, opc);
2019 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);
2021 ice_parse_caps(hw, buf, LE32_TO_CPU(cmd->count), opc);
2022 else if (hw->adminq.sq_last_status == ICE_AQ_RC_ENOMEM)
2023 *cap_count = LE32_TO_CPU(cmd->count);
2028 * ice_discover_caps - get info about the HW
2029 * @hw: pointer to the hardware structure
2030 * @opc: capabilities type to discover - pass in the command opcode
2032 static enum ice_status
2033 ice_discover_caps(struct ice_hw *hw, enum ice_adminq_opc opc)
2035 enum ice_status status;
2040 /* The driver doesn't know how many capabilities the device will return
2041 * so the buffer size required isn't known ahead of time. The driver
2042 * starts with cbuf_len and if this turns out to be insufficient, the
2043 * device returns ICE_AQ_RC_ENOMEM and also the cap_count it needs.
2044 * The driver then allocates the buffer based on the count and retries
2045 * the operation. So it follows that the retry count is 2.
2047 #define ICE_GET_CAP_BUF_COUNT 40
2048 #define ICE_GET_CAP_RETRY_COUNT 2
2050 cap_count = ICE_GET_CAP_BUF_COUNT;
2051 retries = ICE_GET_CAP_RETRY_COUNT;
2056 cbuf_len = (u16)(cap_count *
2057 sizeof(struct ice_aqc_list_caps_elem));
2058 cbuf = ice_malloc(hw, cbuf_len);
2060 return ICE_ERR_NO_MEMORY;
2062 status = ice_aq_discover_caps(hw, cbuf, cbuf_len, &cap_count,
2066 if (!status || hw->adminq.sq_last_status != ICE_AQ_RC_ENOMEM)
2069 /* If ENOMEM is returned, try again with bigger buffer */
2070 } while (--retries);
2076 * ice_get_caps - get info about the HW
2077 * @hw: pointer to the hardware structure
2079 enum ice_status ice_get_caps(struct ice_hw *hw)
2081 enum ice_status status;
2083 status = ice_discover_caps(hw, ice_aqc_opc_list_dev_caps);
2085 status = ice_discover_caps(hw, ice_aqc_opc_list_func_caps);
2091 * ice_aq_manage_mac_write - manage MAC address write command
2092 * @hw: pointer to the HW struct
2093 * @mac_addr: MAC address to be written as LAA/LAA+WoL/Port address
2094 * @flags: flags to control write behavior
2095 * @cd: pointer to command details structure or NULL
2097 * This function is used to write MAC address to the NVM (0x0108).
2100 ice_aq_manage_mac_write(struct ice_hw *hw, const u8 *mac_addr, u8 flags,
2101 struct ice_sq_cd *cd)
2103 struct ice_aqc_manage_mac_write *cmd;
2104 struct ice_aq_desc desc;
2106 cmd = &desc.params.mac_write;
2107 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_write);
2112 /* Prep values for flags, sah, sal */
2113 cmd->sah = HTONS(*((const u16 *)mac_addr));
2114 cmd->sal = HTONL(*((const u32 *)(mac_addr + 2)));
2116 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
2120 * ice_aq_clear_pxe_mode
2121 * @hw: pointer to the HW struct
2123 * Tell the firmware that the driver is taking over from PXE (0x0110).
2125 static enum ice_status ice_aq_clear_pxe_mode(struct ice_hw *hw)
2127 struct ice_aq_desc desc;
2129 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pxe_mode);
2130 desc.params.clear_pxe.rx_cnt = ICE_AQC_CLEAR_PXE_RX_CNT;
2132 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
2136 * ice_clear_pxe_mode - clear pxe operations mode
2137 * @hw: pointer to the HW struct
2139 * Make sure all PXE mode settings are cleared, including things
2140 * like descriptor fetch/write-back mode.
2142 void ice_clear_pxe_mode(struct ice_hw *hw)
2144 if (ice_check_sq_alive(hw, &hw->adminq))
2145 ice_aq_clear_pxe_mode(hw);
2150 * ice_get_link_speed_based_on_phy_type - returns link speed
2151 * @phy_type_low: lower part of phy_type
2152 * @phy_type_high: higher part of phy_type
2154 * This helper function will convert an entry in PHY type structure
2155 * [phy_type_low, phy_type_high] to its corresponding link speed.
2156 * Note: In the structure of [phy_type_low, phy_type_high], there should
2157 * be one bit set, as this function will convert one PHY type to its
2159 * If no bit gets set, ICE_LINK_SPEED_UNKNOWN will be returned
2160 * If more than one bit gets set, ICE_LINK_SPEED_UNKNOWN will be returned
2163 ice_get_link_speed_based_on_phy_type(u64 phy_type_low, u64 phy_type_high)
2165 u16 speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN;
2166 u16 speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN;
2168 switch (phy_type_low) {
2169 case ICE_PHY_TYPE_LOW_100BASE_TX:
2170 case ICE_PHY_TYPE_LOW_100M_SGMII:
2171 speed_phy_type_low = ICE_AQ_LINK_SPEED_100MB;
2173 case ICE_PHY_TYPE_LOW_1000BASE_T:
2174 case ICE_PHY_TYPE_LOW_1000BASE_SX:
2175 case ICE_PHY_TYPE_LOW_1000BASE_LX:
2176 case ICE_PHY_TYPE_LOW_1000BASE_KX:
2177 case ICE_PHY_TYPE_LOW_1G_SGMII:
2178 speed_phy_type_low = ICE_AQ_LINK_SPEED_1000MB;
2180 case ICE_PHY_TYPE_LOW_2500BASE_T:
2181 case ICE_PHY_TYPE_LOW_2500BASE_X:
2182 case ICE_PHY_TYPE_LOW_2500BASE_KX:
2183 speed_phy_type_low = ICE_AQ_LINK_SPEED_2500MB;
2185 case ICE_PHY_TYPE_LOW_5GBASE_T:
2186 case ICE_PHY_TYPE_LOW_5GBASE_KR:
2187 speed_phy_type_low = ICE_AQ_LINK_SPEED_5GB;
2189 case ICE_PHY_TYPE_LOW_10GBASE_T:
2190 case ICE_PHY_TYPE_LOW_10G_SFI_DA:
2191 case ICE_PHY_TYPE_LOW_10GBASE_SR:
2192 case ICE_PHY_TYPE_LOW_10GBASE_LR:
2193 case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1:
2194 case ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC:
2195 case ICE_PHY_TYPE_LOW_10G_SFI_C2C:
2196 speed_phy_type_low = ICE_AQ_LINK_SPEED_10GB;
2198 case ICE_PHY_TYPE_LOW_25GBASE_T:
2199 case ICE_PHY_TYPE_LOW_25GBASE_CR:
2200 case ICE_PHY_TYPE_LOW_25GBASE_CR_S:
2201 case ICE_PHY_TYPE_LOW_25GBASE_CR1:
2202 case ICE_PHY_TYPE_LOW_25GBASE_SR:
2203 case ICE_PHY_TYPE_LOW_25GBASE_LR:
2204 case ICE_PHY_TYPE_LOW_25GBASE_KR:
2205 case ICE_PHY_TYPE_LOW_25GBASE_KR_S:
2206 case ICE_PHY_TYPE_LOW_25GBASE_KR1:
2207 case ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC:
2208 case ICE_PHY_TYPE_LOW_25G_AUI_C2C:
2209 speed_phy_type_low = ICE_AQ_LINK_SPEED_25GB;
2211 case ICE_PHY_TYPE_LOW_40GBASE_CR4:
2212 case ICE_PHY_TYPE_LOW_40GBASE_SR4:
2213 case ICE_PHY_TYPE_LOW_40GBASE_LR4:
2214 case ICE_PHY_TYPE_LOW_40GBASE_KR4:
2215 case ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC:
2216 case ICE_PHY_TYPE_LOW_40G_XLAUI:
2217 speed_phy_type_low = ICE_AQ_LINK_SPEED_40GB;
2219 case ICE_PHY_TYPE_LOW_50GBASE_CR2:
2220 case ICE_PHY_TYPE_LOW_50GBASE_SR2:
2221 case ICE_PHY_TYPE_LOW_50GBASE_LR2:
2222 case ICE_PHY_TYPE_LOW_50GBASE_KR2:
2223 case ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC:
2224 case ICE_PHY_TYPE_LOW_50G_LAUI2:
2225 case ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC:
2226 case ICE_PHY_TYPE_LOW_50G_AUI2:
2227 case ICE_PHY_TYPE_LOW_50GBASE_CP:
2228 case ICE_PHY_TYPE_LOW_50GBASE_SR:
2229 case ICE_PHY_TYPE_LOW_50GBASE_FR:
2230 case ICE_PHY_TYPE_LOW_50GBASE_LR:
2231 case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4:
2232 case ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC:
2233 case ICE_PHY_TYPE_LOW_50G_AUI1:
2234 speed_phy_type_low = ICE_AQ_LINK_SPEED_50GB;
2236 case ICE_PHY_TYPE_LOW_100GBASE_CR4:
2237 case ICE_PHY_TYPE_LOW_100GBASE_SR4:
2238 case ICE_PHY_TYPE_LOW_100GBASE_LR4:
2239 case ICE_PHY_TYPE_LOW_100GBASE_KR4:
2240 case ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC:
2241 case ICE_PHY_TYPE_LOW_100G_CAUI4:
2242 case ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC:
2243 case ICE_PHY_TYPE_LOW_100G_AUI4:
2244 case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4:
2245 case ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4:
2246 case ICE_PHY_TYPE_LOW_100GBASE_CP2:
2247 case ICE_PHY_TYPE_LOW_100GBASE_SR2:
2248 case ICE_PHY_TYPE_LOW_100GBASE_DR:
2249 speed_phy_type_low = ICE_AQ_LINK_SPEED_100GB;
2252 speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN;
2256 switch (phy_type_high) {
2257 case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4:
2258 case ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC:
2259 case ICE_PHY_TYPE_HIGH_100G_CAUI2:
2260 case ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC:
2261 case ICE_PHY_TYPE_HIGH_100G_AUI2:
2262 speed_phy_type_high = ICE_AQ_LINK_SPEED_100GB;
2265 speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN;
2269 if (speed_phy_type_low == ICE_AQ_LINK_SPEED_UNKNOWN &&
2270 speed_phy_type_high == ICE_AQ_LINK_SPEED_UNKNOWN)
2271 return ICE_AQ_LINK_SPEED_UNKNOWN;
2272 else if (speed_phy_type_low != ICE_AQ_LINK_SPEED_UNKNOWN &&
2273 speed_phy_type_high != ICE_AQ_LINK_SPEED_UNKNOWN)
2274 return ICE_AQ_LINK_SPEED_UNKNOWN;
2275 else if (speed_phy_type_low != ICE_AQ_LINK_SPEED_UNKNOWN &&
2276 speed_phy_type_high == ICE_AQ_LINK_SPEED_UNKNOWN)
2277 return speed_phy_type_low;
2279 return speed_phy_type_high;
2283 * ice_update_phy_type
2284 * @phy_type_low: pointer to the lower part of phy_type
2285 * @phy_type_high: pointer to the higher part of phy_type
2286 * @link_speeds_bitmap: targeted link speeds bitmap
2288 * Note: For the link_speeds_bitmap structure, you can check it at
2289 * [ice_aqc_get_link_status->link_speed]. Caller can pass in
2290 * link_speeds_bitmap include multiple speeds.
2292 * Each entry in this [phy_type_low, phy_type_high] structure will
2293 * present a certain link speed. This helper function will turn on bits
2294 * in [phy_type_low, phy_type_high] structure based on the value of
2295 * link_speeds_bitmap input parameter.
2298 ice_update_phy_type(u64 *phy_type_low, u64 *phy_type_high,
2299 u16 link_speeds_bitmap)
2301 u16 speed = ICE_AQ_LINK_SPEED_UNKNOWN;
2306 /* We first check with low part of phy_type */
2307 for (index = 0; index <= ICE_PHY_TYPE_LOW_MAX_INDEX; index++) {
2308 pt_low = BIT_ULL(index);
2309 speed = ice_get_link_speed_based_on_phy_type(pt_low, 0);
2311 if (link_speeds_bitmap & speed)
2312 *phy_type_low |= BIT_ULL(index);
2315 /* We then check with high part of phy_type */
2316 for (index = 0; index <= ICE_PHY_TYPE_HIGH_MAX_INDEX; index++) {
2317 pt_high = BIT_ULL(index);
2318 speed = ice_get_link_speed_based_on_phy_type(0, pt_high);
2320 if (link_speeds_bitmap & speed)
2321 *phy_type_high |= BIT_ULL(index);
2326 * ice_aq_set_phy_cfg
2327 * @hw: pointer to the HW struct
2328 * @lport: logical port number
2329 * @cfg: structure with PHY configuration data to be set
2330 * @cd: pointer to command details structure or NULL
2332 * Set the various PHY configuration parameters supported on the Port.
2333 * One or more of the Set PHY config parameters may be ignored in an MFP
2334 * mode as the PF may not have the privilege to set some of the PHY Config
2335 * parameters. This status will be indicated by the command response (0x0601).
2338 ice_aq_set_phy_cfg(struct ice_hw *hw, u8 lport,
2339 struct ice_aqc_set_phy_cfg_data *cfg, struct ice_sq_cd *cd)
2341 struct ice_aq_desc desc;
2344 return ICE_ERR_PARAM;
2346 /* Ensure that only valid bits of cfg->caps can be turned on. */
2347 if (cfg->caps & ~ICE_AQ_PHY_ENA_VALID_MASK) {
2348 ice_debug(hw, ICE_DBG_PHY,
2349 "Invalid bit is set in ice_aqc_set_phy_cfg_data->caps : 0x%x\n",
2352 cfg->caps &= ICE_AQ_PHY_ENA_VALID_MASK;
2355 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_phy_cfg);
2356 desc.params.set_phy.lport_num = lport;
2357 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
2359 return ice_aq_send_cmd(hw, &desc, cfg, sizeof(*cfg), cd);
2363 * ice_update_link_info - update status of the HW network link
2364 * @pi: port info structure of the interested logical port
2366 enum ice_status ice_update_link_info(struct ice_port_info *pi)
2368 struct ice_aqc_get_phy_caps_data *pcaps;
2369 struct ice_phy_info *phy_info;
2370 enum ice_status status;
2374 return ICE_ERR_PARAM;
2378 pcaps = (struct ice_aqc_get_phy_caps_data *)
2379 ice_malloc(hw, sizeof(*pcaps));
2381 return ICE_ERR_NO_MEMORY;
2383 phy_info = &pi->phy;
2384 status = ice_aq_get_link_info(pi, true, NULL, NULL);
2388 if (phy_info->link_info.link_info & ICE_AQ_MEDIA_AVAILABLE) {
2389 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_SW_CFG,
2394 ice_memcpy(phy_info->link_info.module_type, &pcaps->module_type,
2395 sizeof(phy_info->link_info.module_type),
2396 ICE_NONDMA_TO_NONDMA);
2399 ice_free(hw, pcaps);
2405 * @pi: port information structure
2406 * @aq_failures: pointer to status code, specific to ice_set_fc routine
2407 * @ena_auto_link_update: enable automatic link update
2409 * Set the requested flow control mode.
2412 ice_set_fc(struct ice_port_info *pi, u8 *aq_failures, bool ena_auto_link_update)
2414 struct ice_aqc_set_phy_cfg_data cfg = { 0 };
2415 struct ice_aqc_get_phy_caps_data *pcaps;
2416 enum ice_status status;
2417 u8 pause_mask = 0x0;
2421 return ICE_ERR_PARAM;
2423 *aq_failures = ICE_SET_FC_AQ_FAIL_NONE;
2425 switch (pi->fc.req_mode) {
2427 pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE;
2428 pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE;
2430 case ICE_FC_RX_PAUSE:
2431 pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE;
2433 case ICE_FC_TX_PAUSE:
2434 pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE;
2440 pcaps = (struct ice_aqc_get_phy_caps_data *)
2441 ice_malloc(hw, sizeof(*pcaps));
2443 return ICE_ERR_NO_MEMORY;
2445 /* Get the current PHY config */
2446 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_SW_CFG, pcaps,
2449 *aq_failures = ICE_SET_FC_AQ_FAIL_GET;
2453 /* clear the old pause settings */
2454 cfg.caps = pcaps->caps & ~(ICE_AQC_PHY_EN_TX_LINK_PAUSE |
2455 ICE_AQC_PHY_EN_RX_LINK_PAUSE);
2456 /* set the new capabilities */
2457 cfg.caps |= pause_mask;
2458 /* If the capabilities have changed, then set the new config */
2459 if (cfg.caps != pcaps->caps) {
2460 int retry_count, retry_max = 10;
2462 /* Auto restart link so settings take effect */
2463 if (ena_auto_link_update)
2464 cfg.caps |= ICE_AQ_PHY_ENA_AUTO_LINK_UPDT;
2465 /* Copy over all the old settings */
2466 cfg.phy_type_high = pcaps->phy_type_high;
2467 cfg.phy_type_low = pcaps->phy_type_low;
2468 cfg.low_power_ctrl = pcaps->low_power_ctrl;
2469 cfg.eee_cap = pcaps->eee_cap;
2470 cfg.eeer_value = pcaps->eeer_value;
2471 cfg.link_fec_opt = pcaps->link_fec_options;
2473 status = ice_aq_set_phy_cfg(hw, pi->lport, &cfg, NULL);
2475 *aq_failures = ICE_SET_FC_AQ_FAIL_SET;
2479 /* Update the link info
2480 * It sometimes takes a really long time for link to
2481 * come back from the atomic reset. Thus, we wait a
2484 for (retry_count = 0; retry_count < retry_max; retry_count++) {
2485 status = ice_update_link_info(pi);
2487 if (status == ICE_SUCCESS)
2490 ice_msec_delay(100, true);
2494 *aq_failures = ICE_SET_FC_AQ_FAIL_UPDATE;
2498 ice_free(hw, pcaps);
2503 * ice_copy_phy_caps_to_cfg - Copy PHY ability data to configuration data
2504 * @caps: PHY ability structure to copy date from
2505 * @cfg: PHY configuration structure to copy data to
2507 * Helper function to copy AQC PHY get ability data to PHY set configuration
2511 ice_copy_phy_caps_to_cfg(struct ice_aqc_get_phy_caps_data *caps,
2512 struct ice_aqc_set_phy_cfg_data *cfg)
2517 cfg->phy_type_low = caps->phy_type_low;
2518 cfg->phy_type_high = caps->phy_type_high;
2519 cfg->caps = caps->caps;
2520 cfg->low_power_ctrl = caps->low_power_ctrl;
2521 cfg->eee_cap = caps->eee_cap;
2522 cfg->eeer_value = caps->eeer_value;
2523 cfg->link_fec_opt = caps->link_fec_options;
2527 * ice_cfg_phy_fec - Configure PHY FEC data based on FEC mode
2528 * @cfg: PHY configuration data to set FEC mode
2529 * @fec: FEC mode to configure
2531 * Caller should copy ice_aqc_get_phy_caps_data.caps ICE_AQC_PHY_EN_AUTO_FEC
2532 * (bit 7) and ice_aqc_get_phy_caps_data.link_fec_options to cfg.caps
2533 * ICE_AQ_PHY_ENA_AUTO_FEC (bit 7) and cfg.link_fec_options before calling.
2536 ice_cfg_phy_fec(struct ice_aqc_set_phy_cfg_data *cfg, enum ice_fec_mode fec)
2540 /* Clear auto FEC and RS bits, and AND BASE-R ability
2541 * bits and OR request bits.
2543 cfg->caps &= ~ICE_AQC_PHY_EN_AUTO_FEC;
2544 cfg->link_fec_opt &= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN |
2545 ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN;
2546 cfg->link_fec_opt |= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ |
2547 ICE_AQC_PHY_FEC_25G_KR_REQ;
2550 /* Clear auto FEC and BASE-R bits, and AND RS ability
2551 * bits and OR request bits.
2553 cfg->caps &= ~ICE_AQC_PHY_EN_AUTO_FEC;
2554 cfg->link_fec_opt &= ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN;
2555 cfg->link_fec_opt |= ICE_AQC_PHY_FEC_25G_RS_528_REQ |
2556 ICE_AQC_PHY_FEC_25G_RS_544_REQ;
2559 /* Clear auto FEC and all FEC option bits. */
2560 cfg->caps &= ~ICE_AQC_PHY_EN_AUTO_FEC;
2561 cfg->link_fec_opt &= ~ICE_AQC_PHY_FEC_MASK;
2564 /* AND auto FEC bit, and all caps bits. */
2565 cfg->caps &= ICE_AQC_PHY_CAPS_MASK;
2571 * ice_get_link_status - get status of the HW network link
2572 * @pi: port information structure
2573 * @link_up: pointer to bool (true/false = linkup/linkdown)
2575 * Variable link_up is true if link is up, false if link is down.
2576 * The variable link_up is invalid if status is non zero. As a
2577 * result of this call, link status reporting becomes enabled
2579 enum ice_status ice_get_link_status(struct ice_port_info *pi, bool *link_up)
2581 struct ice_phy_info *phy_info;
2582 enum ice_status status = ICE_SUCCESS;
2584 if (!pi || !link_up)
2585 return ICE_ERR_PARAM;
2587 phy_info = &pi->phy;
2589 if (phy_info->get_link_info) {
2590 status = ice_update_link_info(pi);
2593 ice_debug(pi->hw, ICE_DBG_LINK,
2594 "get link status error, status = %d\n",
2598 *link_up = phy_info->link_info.link_info & ICE_AQ_LINK_UP;
2604 * ice_aq_set_link_restart_an
2605 * @pi: pointer to the port information structure
2606 * @ena_link: if true: enable link, if false: disable link
2607 * @cd: pointer to command details structure or NULL
2609 * Sets up the link and restarts the Auto-Negotiation over the link.
2612 ice_aq_set_link_restart_an(struct ice_port_info *pi, bool ena_link,
2613 struct ice_sq_cd *cd)
2615 struct ice_aqc_restart_an *cmd;
2616 struct ice_aq_desc desc;
2618 cmd = &desc.params.restart_an;
2620 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_restart_an);
2622 cmd->cmd_flags = ICE_AQC_RESTART_AN_LINK_RESTART;
2623 cmd->lport_num = pi->lport;
2625 cmd->cmd_flags |= ICE_AQC_RESTART_AN_LINK_ENABLE;
2627 cmd->cmd_flags &= ~ICE_AQC_RESTART_AN_LINK_ENABLE;
2629 return ice_aq_send_cmd(pi->hw, &desc, NULL, 0, cd);
2633 * ice_aq_set_event_mask
2634 * @hw: pointer to the HW struct
2635 * @port_num: port number of the physical function
2636 * @mask: event mask to be set
2637 * @cd: pointer to command details structure or NULL
2639 * Set event mask (0x0613)
2642 ice_aq_set_event_mask(struct ice_hw *hw, u8 port_num, u16 mask,
2643 struct ice_sq_cd *cd)
2645 struct ice_aqc_set_event_mask *cmd;
2646 struct ice_aq_desc desc;
2648 cmd = &desc.params.set_event_mask;
2650 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_event_mask);
2652 cmd->lport_num = port_num;
2654 cmd->event_mask = CPU_TO_LE16(mask);
2655 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
2659 * ice_aq_set_mac_loopback
2660 * @hw: pointer to the HW struct
2661 * @ena_lpbk: Enable or Disable loopback
2662 * @cd: pointer to command details structure or NULL
2664 * Enable/disable loopback on a given port
2667 ice_aq_set_mac_loopback(struct ice_hw *hw, bool ena_lpbk, struct ice_sq_cd *cd)
2669 struct ice_aqc_set_mac_lb *cmd;
2670 struct ice_aq_desc desc;
2672 cmd = &desc.params.set_mac_lb;
2674 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_mac_lb);
2676 cmd->lb_mode = ICE_AQ_MAC_LB_EN;
2678 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
2683 * ice_aq_set_port_id_led
2684 * @pi: pointer to the port information
2685 * @is_orig_mode: is this LED set to original mode (by the net-list)
2686 * @cd: pointer to command details structure or NULL
2688 * Set LED value for the given port (0x06e9)
2691 ice_aq_set_port_id_led(struct ice_port_info *pi, bool is_orig_mode,
2692 struct ice_sq_cd *cd)
2694 struct ice_aqc_set_port_id_led *cmd;
2695 struct ice_hw *hw = pi->hw;
2696 struct ice_aq_desc desc;
2698 cmd = &desc.params.set_port_id_led;
2700 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_port_id_led);
2704 cmd->ident_mode = ICE_AQC_PORT_IDENT_LED_ORIG;
2706 cmd->ident_mode = ICE_AQC_PORT_IDENT_LED_BLINK;
2708 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
2712 * __ice_aq_get_set_rss_lut
2713 * @hw: pointer to the hardware structure
2714 * @vsi_id: VSI FW index
2715 * @lut_type: LUT table type
2716 * @lut: pointer to the LUT buffer provided by the caller
2717 * @lut_size: size of the LUT buffer
2718 * @glob_lut_idx: global LUT index
2719 * @set: set true to set the table, false to get the table
2721 * Internal function to get (0x0B05) or set (0x0B03) RSS look up table
2723 static enum ice_status
2724 __ice_aq_get_set_rss_lut(struct ice_hw *hw, u16 vsi_id, u8 lut_type, u8 *lut,
2725 u16 lut_size, u8 glob_lut_idx, bool set)
2727 struct ice_aqc_get_set_rss_lut *cmd_resp;
2728 struct ice_aq_desc desc;
2729 enum ice_status status;
2732 cmd_resp = &desc.params.get_set_rss_lut;
2735 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_rss_lut);
2736 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
2738 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_rss_lut);
2741 cmd_resp->vsi_id = CPU_TO_LE16(((vsi_id <<
2742 ICE_AQC_GSET_RSS_LUT_VSI_ID_S) &
2743 ICE_AQC_GSET_RSS_LUT_VSI_ID_M) |
2744 ICE_AQC_GSET_RSS_LUT_VSI_VALID);
2747 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_VSI:
2748 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF:
2749 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL:
2750 flags |= ((lut_type << ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S) &
2751 ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_M);
2754 status = ICE_ERR_PARAM;
2755 goto ice_aq_get_set_rss_lut_exit;
2758 if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL) {
2759 flags |= ((glob_lut_idx << ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S) &
2760 ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_M);
2763 goto ice_aq_get_set_rss_lut_send;
2764 } else if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF) {
2766 goto ice_aq_get_set_rss_lut_send;
2768 goto ice_aq_get_set_rss_lut_send;
2771 /* LUT size is only valid for Global and PF table types */
2773 case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128:
2774 flags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128_FLAG <<
2775 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) &
2776 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M;
2778 case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512:
2779 flags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512_FLAG <<
2780 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) &
2781 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M;
2783 case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K:
2784 if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF) {
2785 flags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K_FLAG <<
2786 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) &
2787 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M;
2792 status = ICE_ERR_PARAM;
2793 goto ice_aq_get_set_rss_lut_exit;
2796 ice_aq_get_set_rss_lut_send:
2797 cmd_resp->flags = CPU_TO_LE16(flags);
2798 status = ice_aq_send_cmd(hw, &desc, lut, lut_size, NULL);
2800 ice_aq_get_set_rss_lut_exit:
2805 * ice_aq_get_rss_lut
2806 * @hw: pointer to the hardware structure
2807 * @vsi_handle: software VSI handle
2808 * @lut_type: LUT table type
2809 * @lut: pointer to the LUT buffer provided by the caller
2810 * @lut_size: size of the LUT buffer
2812 * get the RSS lookup table, PF or VSI type
2815 ice_aq_get_rss_lut(struct ice_hw *hw, u16 vsi_handle, u8 lut_type,
2816 u8 *lut, u16 lut_size)
2818 if (!ice_is_vsi_valid(hw, vsi_handle) || !lut)
2819 return ICE_ERR_PARAM;
2821 return __ice_aq_get_set_rss_lut(hw, ice_get_hw_vsi_num(hw, vsi_handle),
2822 lut_type, lut, lut_size, 0, false);
2826 * ice_aq_set_rss_lut
2827 * @hw: pointer to the hardware structure
2828 * @vsi_handle: software VSI handle
2829 * @lut_type: LUT table type
2830 * @lut: pointer to the LUT buffer provided by the caller
2831 * @lut_size: size of the LUT buffer
2833 * set the RSS lookup table, PF or VSI type
2836 ice_aq_set_rss_lut(struct ice_hw *hw, u16 vsi_handle, u8 lut_type,
2837 u8 *lut, u16 lut_size)
2839 if (!ice_is_vsi_valid(hw, vsi_handle) || !lut)
2840 return ICE_ERR_PARAM;
2842 return __ice_aq_get_set_rss_lut(hw, ice_get_hw_vsi_num(hw, vsi_handle),
2843 lut_type, lut, lut_size, 0, true);
2847 * __ice_aq_get_set_rss_key
2848 * @hw: pointer to the HW struct
2849 * @vsi_id: VSI FW index
2850 * @key: pointer to key info struct
2851 * @set: set true to set the key, false to get the key
2853 * get (0x0B04) or set (0x0B02) the RSS key per VSI
2856 ice_status __ice_aq_get_set_rss_key(struct ice_hw *hw, u16 vsi_id,
2857 struct ice_aqc_get_set_rss_keys *key,
2860 struct ice_aqc_get_set_rss_key *cmd_resp;
2861 u16 key_size = sizeof(*key);
2862 struct ice_aq_desc desc;
2864 cmd_resp = &desc.params.get_set_rss_key;
2867 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_rss_key);
2868 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
2870 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_rss_key);
2873 cmd_resp->vsi_id = CPU_TO_LE16(((vsi_id <<
2874 ICE_AQC_GSET_RSS_KEY_VSI_ID_S) &
2875 ICE_AQC_GSET_RSS_KEY_VSI_ID_M) |
2876 ICE_AQC_GSET_RSS_KEY_VSI_VALID);
2878 return ice_aq_send_cmd(hw, &desc, key, key_size, NULL);
2882 * ice_aq_get_rss_key
2883 * @hw: pointer to the HW struct
2884 * @vsi_handle: software VSI handle
2885 * @key: pointer to key info struct
2887 * get the RSS key per VSI
2890 ice_aq_get_rss_key(struct ice_hw *hw, u16 vsi_handle,
2891 struct ice_aqc_get_set_rss_keys *key)
2893 if (!ice_is_vsi_valid(hw, vsi_handle) || !key)
2894 return ICE_ERR_PARAM;
2896 return __ice_aq_get_set_rss_key(hw, ice_get_hw_vsi_num(hw, vsi_handle),
2901 * ice_aq_set_rss_key
2902 * @hw: pointer to the HW struct
2903 * @vsi_handle: software VSI handle
2904 * @keys: pointer to key info struct
2906 * set the RSS key per VSI
2909 ice_aq_set_rss_key(struct ice_hw *hw, u16 vsi_handle,
2910 struct ice_aqc_get_set_rss_keys *keys)
2912 if (!ice_is_vsi_valid(hw, vsi_handle) || !keys)
2913 return ICE_ERR_PARAM;
2915 return __ice_aq_get_set_rss_key(hw, ice_get_hw_vsi_num(hw, vsi_handle),
2920 * ice_aq_add_lan_txq
2921 * @hw: pointer to the hardware structure
2922 * @num_qgrps: Number of added queue groups
2923 * @qg_list: list of queue groups to be added
2924 * @buf_size: size of buffer for indirect command
2925 * @cd: pointer to command details structure or NULL
2927 * Add Tx LAN queue (0x0C30)
2930 * Prior to calling add Tx LAN queue:
2931 * Initialize the following as part of the Tx queue context:
2932 * Completion queue ID if the queue uses Completion queue, Quanta profile,
2933 * Cache profile and Packet shaper profile.
2935 * After add Tx LAN queue AQ command is completed:
2936 * Interrupts should be associated with specific queues,
2937 * Association of Tx queue to Doorbell queue is not part of Add LAN Tx queue
2941 ice_aq_add_lan_txq(struct ice_hw *hw, u8 num_qgrps,
2942 struct ice_aqc_add_tx_qgrp *qg_list, u16 buf_size,
2943 struct ice_sq_cd *cd)
2945 u16 i, sum_header_size, sum_q_size = 0;
2946 struct ice_aqc_add_tx_qgrp *list;
2947 struct ice_aqc_add_txqs *cmd;
2948 struct ice_aq_desc desc;
2950 ice_debug(hw, ICE_DBG_TRACE, "ice_aq_add_lan_txq");
2952 cmd = &desc.params.add_txqs;
2954 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_add_txqs);
2957 return ICE_ERR_PARAM;
2959 if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS)
2960 return ICE_ERR_PARAM;
2962 sum_header_size = num_qgrps *
2963 (sizeof(*qg_list) - sizeof(*qg_list->txqs));
2966 for (i = 0; i < num_qgrps; i++) {
2967 struct ice_aqc_add_txqs_perq *q = list->txqs;
2969 sum_q_size += list->num_txqs * sizeof(*q);
2970 list = (struct ice_aqc_add_tx_qgrp *)(q + list->num_txqs);
2973 if (buf_size != (sum_header_size + sum_q_size))
2974 return ICE_ERR_PARAM;
2976 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
2978 cmd->num_qgrps = num_qgrps;
2980 return ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd);
2984 * ice_aq_dis_lan_txq
2985 * @hw: pointer to the hardware structure
2986 * @num_qgrps: number of groups in the list
2987 * @qg_list: the list of groups to disable
2988 * @buf_size: the total size of the qg_list buffer in bytes
2989 * @rst_src: if called due to reset, specifies the reset source
2990 * @vmvf_num: the relative VM or VF number that is undergoing the reset
2991 * @cd: pointer to command details structure or NULL
2993 * Disable LAN Tx queue (0x0C31)
2995 static enum ice_status
2996 ice_aq_dis_lan_txq(struct ice_hw *hw, u8 num_qgrps,
2997 struct ice_aqc_dis_txq_item *qg_list, u16 buf_size,
2998 enum ice_disq_rst_src rst_src, u16 vmvf_num,
2999 struct ice_sq_cd *cd)
3001 struct ice_aqc_dis_txqs *cmd;
3002 struct ice_aq_desc desc;
3003 enum ice_status status;
3006 ice_debug(hw, ICE_DBG_TRACE, "ice_aq_dis_lan_txq");
3007 cmd = &desc.params.dis_txqs;
3008 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_dis_txqs);
3010 /* qg_list can be NULL only in VM/VF reset flow */
3011 if (!qg_list && !rst_src)
3012 return ICE_ERR_PARAM;
3014 if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS)
3015 return ICE_ERR_PARAM;
3017 cmd->num_entries = num_qgrps;
3019 cmd->vmvf_and_timeout = CPU_TO_LE16((5 << ICE_AQC_Q_DIS_TIMEOUT_S) &
3020 ICE_AQC_Q_DIS_TIMEOUT_M);
3024 cmd->cmd_type = ICE_AQC_Q_DIS_CMD_VM_RESET;
3025 cmd->vmvf_and_timeout |=
3026 CPU_TO_LE16(vmvf_num & ICE_AQC_Q_DIS_VMVF_NUM_M);
3033 /* flush pipe on time out */
3034 cmd->cmd_type |= ICE_AQC_Q_DIS_CMD_FLUSH_PIPE;
3035 /* If no queue group info, we are in a reset flow. Issue the AQ */
3039 /* set RD bit to indicate that command buffer is provided by the driver
3040 * and it needs to be read by the firmware
3042 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
3044 for (i = 0; i < num_qgrps; ++i) {
3045 /* Calculate the size taken up by the queue IDs in this group */
3046 sz += qg_list[i].num_qs * sizeof(qg_list[i].q_id);
3048 /* Add the size of the group header */
3049 sz += sizeof(qg_list[i]) - sizeof(qg_list[i].q_id);
3051 /* If the num of queues is even, add 2 bytes of padding */
3052 if ((qg_list[i].num_qs % 2) == 0)
3057 return ICE_ERR_PARAM;
3060 status = ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd);
3063 ice_debug(hw, ICE_DBG_SCHED, "VM%d disable failed %d\n",
3064 vmvf_num, hw->adminq.sq_last_status);
3066 ice_debug(hw, ICE_DBG_SCHED, "disable queue %d failed %d\n",
3067 LE16_TO_CPU(qg_list[0].q_id[0]),
3068 hw->adminq.sq_last_status);
3074 /* End of FW Admin Queue command wrappers */
3077 * ice_write_byte - write a byte to a packed context structure
3078 * @src_ctx: the context structure to read from
3079 * @dest_ctx: the context to be written to
3080 * @ce_info: a description of the struct to be filled
3083 ice_write_byte(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)
3085 u8 src_byte, dest_byte, mask;
3089 /* copy from the next struct field */
3090 from = src_ctx + ce_info->offset;
3092 /* prepare the bits and mask */
3093 shift_width = ce_info->lsb % 8;
3094 mask = (u8)(BIT(ce_info->width) - 1);
3099 /* shift to correct alignment */
3100 mask <<= shift_width;
3101 src_byte <<= shift_width;
3103 /* get the current bits from the target bit string */
3104 dest = dest_ctx + (ce_info->lsb / 8);
3106 ice_memcpy(&dest_byte, dest, sizeof(dest_byte), ICE_DMA_TO_NONDMA);
3108 dest_byte &= ~mask; /* get the bits not changing */
3109 dest_byte |= src_byte; /* add in the new bits */
3111 /* put it all back */
3112 ice_memcpy(dest, &dest_byte, sizeof(dest_byte), ICE_NONDMA_TO_DMA);
3116 * ice_write_word - write a word to a packed context structure
3117 * @src_ctx: the context structure to read from
3118 * @dest_ctx: the context to be written to
3119 * @ce_info: a description of the struct to be filled
3122 ice_write_word(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)
3129 /* copy from the next struct field */
3130 from = src_ctx + ce_info->offset;
3132 /* prepare the bits and mask */
3133 shift_width = ce_info->lsb % 8;
3134 mask = BIT(ce_info->width) - 1;
3136 /* don't swizzle the bits until after the mask because the mask bits
3137 * will be in a different bit position on big endian machines
3139 src_word = *(u16 *)from;
3142 /* shift to correct alignment */
3143 mask <<= shift_width;
3144 src_word <<= shift_width;
3146 /* get the current bits from the target bit string */
3147 dest = dest_ctx + (ce_info->lsb / 8);
3149 ice_memcpy(&dest_word, dest, sizeof(dest_word), ICE_DMA_TO_NONDMA);
3151 dest_word &= ~(CPU_TO_LE16(mask)); /* get the bits not changing */
3152 dest_word |= CPU_TO_LE16(src_word); /* add in the new bits */
3154 /* put it all back */
3155 ice_memcpy(dest, &dest_word, sizeof(dest_word), ICE_NONDMA_TO_DMA);
3159 * ice_write_dword - write a dword to a packed context structure
3160 * @src_ctx: the context structure to read from
3161 * @dest_ctx: the context to be written to
3162 * @ce_info: a description of the struct to be filled
3165 ice_write_dword(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)
3167 u32 src_dword, mask;
3172 /* copy from the next struct field */
3173 from = src_ctx + ce_info->offset;
3175 /* prepare the bits and mask */
3176 shift_width = ce_info->lsb % 8;
3178 /* if the field width is exactly 32 on an x86 machine, then the shift
3179 * operation will not work because the SHL instructions count is masked
3180 * to 5 bits so the shift will do nothing
3182 if (ce_info->width < 32)
3183 mask = BIT(ce_info->width) - 1;
3187 /* don't swizzle the bits until after the mask because the mask bits
3188 * will be in a different bit position on big endian machines
3190 src_dword = *(u32 *)from;
3193 /* shift to correct alignment */
3194 mask <<= shift_width;
3195 src_dword <<= shift_width;
3197 /* get the current bits from the target bit string */
3198 dest = dest_ctx + (ce_info->lsb / 8);
3200 ice_memcpy(&dest_dword, dest, sizeof(dest_dword), ICE_DMA_TO_NONDMA);
3202 dest_dword &= ~(CPU_TO_LE32(mask)); /* get the bits not changing */
3203 dest_dword |= CPU_TO_LE32(src_dword); /* add in the new bits */
3205 /* put it all back */
3206 ice_memcpy(dest, &dest_dword, sizeof(dest_dword), ICE_NONDMA_TO_DMA);
3210 * ice_write_qword - write a qword to a packed context structure
3211 * @src_ctx: the context structure to read from
3212 * @dest_ctx: the context to be written to
3213 * @ce_info: a description of the struct to be filled
3216 ice_write_qword(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)
3218 u64 src_qword, mask;
3223 /* copy from the next struct field */
3224 from = src_ctx + ce_info->offset;
3226 /* prepare the bits and mask */
3227 shift_width = ce_info->lsb % 8;
3229 /* if the field width is exactly 64 on an x86 machine, then the shift
3230 * operation will not work because the SHL instructions count is masked
3231 * to 6 bits so the shift will do nothing
3233 if (ce_info->width < 64)
3234 mask = BIT_ULL(ce_info->width) - 1;
3238 /* don't swizzle the bits until after the mask because the mask bits
3239 * will be in a different bit position on big endian machines
3241 src_qword = *(u64 *)from;
3244 /* shift to correct alignment */
3245 mask <<= shift_width;
3246 src_qword <<= shift_width;
3248 /* get the current bits from the target bit string */
3249 dest = dest_ctx + (ce_info->lsb / 8);
3251 ice_memcpy(&dest_qword, dest, sizeof(dest_qword), ICE_DMA_TO_NONDMA);
3253 dest_qword &= ~(CPU_TO_LE64(mask)); /* get the bits not changing */
3254 dest_qword |= CPU_TO_LE64(src_qword); /* add in the new bits */
3256 /* put it all back */
3257 ice_memcpy(dest, &dest_qword, sizeof(dest_qword), ICE_NONDMA_TO_DMA);
3261 * ice_set_ctx - set context bits in packed structure
3262 * @src_ctx: pointer to a generic non-packed context structure
3263 * @dest_ctx: pointer to memory for the packed structure
3264 * @ce_info: a description of the structure to be transformed
3267 ice_set_ctx(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)
3271 for (f = 0; ce_info[f].width; f++) {
3272 /* We have to deal with each element of the FW response
3273 * using the correct size so that we are correct regardless
3274 * of the endianness of the machine.
3276 switch (ce_info[f].size_of) {
3278 ice_write_byte(src_ctx, dest_ctx, &ce_info[f]);
3281 ice_write_word(src_ctx, dest_ctx, &ce_info[f]);
3284 ice_write_dword(src_ctx, dest_ctx, &ce_info[f]);
3287 ice_write_qword(src_ctx, dest_ctx, &ce_info[f]);
3290 return ICE_ERR_INVAL_SIZE;
3301 * ice_read_byte - read context byte into struct
3302 * @src_ctx: the context structure to read from
3303 * @dest_ctx: the context to be written to
3304 * @ce_info: a description of the struct to be filled
3307 ice_read_byte(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info)
3313 /* prepare the bits and mask */
3314 shift_width = ce_info->lsb % 8;
3315 mask = (u8)(BIT(ce_info->width) - 1);
3317 /* shift to correct alignment */
3318 mask <<= shift_width;
3320 /* get the current bits from the src bit string */
3321 src = src_ctx + (ce_info->lsb / 8);
3323 ice_memcpy(&dest_byte, src, sizeof(dest_byte), ICE_DMA_TO_NONDMA);
3325 dest_byte &= ~(mask);
3327 dest_byte >>= shift_width;
3329 /* get the address from the struct field */
3330 target = dest_ctx + ce_info->offset;
3332 /* put it back in the struct */
3333 ice_memcpy(target, &dest_byte, sizeof(dest_byte), ICE_NONDMA_TO_DMA);
3337 * ice_read_word - read context word into struct
3338 * @src_ctx: the context structure to read from
3339 * @dest_ctx: the context to be written to
3340 * @ce_info: a description of the struct to be filled
3343 ice_read_word(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info)
3345 u16 dest_word, mask;
3350 /* prepare the bits and mask */
3351 shift_width = ce_info->lsb % 8;
3352 mask = BIT(ce_info->width) - 1;
3354 /* shift to correct alignment */
3355 mask <<= shift_width;
3357 /* get the current bits from the src bit string */
3358 src = src_ctx + (ce_info->lsb / 8);
3360 ice_memcpy(&src_word, src, sizeof(src_word), ICE_DMA_TO_NONDMA);
3362 /* the data in the memory is stored as little endian so mask it
3365 src_word &= ~(CPU_TO_LE16(mask));
3367 /* get the data back into host order before shifting */
3368 dest_word = LE16_TO_CPU(src_word);
3370 dest_word >>= shift_width;
3372 /* get the address from the struct field */
3373 target = dest_ctx + ce_info->offset;
3375 /* put it back in the struct */
3376 ice_memcpy(target, &dest_word, sizeof(dest_word), ICE_NONDMA_TO_DMA);
3380 * ice_read_dword - read context dword into struct
3381 * @src_ctx: the context structure to read from
3382 * @dest_ctx: the context to be written to
3383 * @ce_info: a description of the struct to be filled
3386 ice_read_dword(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info)
3388 u32 dest_dword, mask;
3393 /* prepare the bits and mask */
3394 shift_width = ce_info->lsb % 8;
3396 /* if the field width is exactly 32 on an x86 machine, then the shift
3397 * operation will not work because the SHL instructions count is masked
3398 * to 5 bits so the shift will do nothing
3400 if (ce_info->width < 32)
3401 mask = BIT(ce_info->width) - 1;
3405 /* shift to correct alignment */
3406 mask <<= shift_width;
3408 /* get the current bits from the src bit string */
3409 src = src_ctx + (ce_info->lsb / 8);
3411 ice_memcpy(&src_dword, src, sizeof(src_dword), ICE_DMA_TO_NONDMA);
3413 /* the data in the memory is stored as little endian so mask it
3416 src_dword &= ~(CPU_TO_LE32(mask));
3418 /* get the data back into host order before shifting */
3419 dest_dword = LE32_TO_CPU(src_dword);
3421 dest_dword >>= shift_width;
3423 /* get the address from the struct field */
3424 target = dest_ctx + ce_info->offset;
3426 /* put it back in the struct */
3427 ice_memcpy(target, &dest_dword, sizeof(dest_dword), ICE_NONDMA_TO_DMA);
3431 * ice_read_qword - read context qword into struct
3432 * @src_ctx: the context structure to read from
3433 * @dest_ctx: the context to be written to
3434 * @ce_info: a description of the struct to be filled
3437 ice_read_qword(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info)
3439 u64 dest_qword, mask;
3444 /* prepare the bits and mask */
3445 shift_width = ce_info->lsb % 8;
3447 /* if the field width is exactly 64 on an x86 machine, then the shift
3448 * operation will not work because the SHL instructions count is masked
3449 * to 6 bits so the shift will do nothing
3451 if (ce_info->width < 64)
3452 mask = BIT_ULL(ce_info->width) - 1;
3456 /* shift to correct alignment */
3457 mask <<= shift_width;
3459 /* get the current bits from the src bit string */
3460 src = src_ctx + (ce_info->lsb / 8);
3462 ice_memcpy(&src_qword, src, sizeof(src_qword), ICE_DMA_TO_NONDMA);
3464 /* the data in the memory is stored as little endian so mask it
3467 src_qword &= ~(CPU_TO_LE64(mask));
3469 /* get the data back into host order before shifting */
3470 dest_qword = LE64_TO_CPU(src_qword);
3472 dest_qword >>= shift_width;
3474 /* get the address from the struct field */
3475 target = dest_ctx + ce_info->offset;
3477 /* put it back in the struct */
3478 ice_memcpy(target, &dest_qword, sizeof(dest_qword), ICE_NONDMA_TO_DMA);
3482 * ice_get_ctx - extract context bits from a packed structure
3483 * @src_ctx: pointer to a generic packed context structure
3484 * @dest_ctx: pointer to a generic non-packed context structure
3485 * @ce_info: a description of the structure to be read from
3488 ice_get_ctx(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info)
3492 for (f = 0; ce_info[f].width; f++) {
3493 switch (ce_info[f].size_of) {
3495 ice_read_byte(src_ctx, dest_ctx, &ce_info[f]);
3498 ice_read_word(src_ctx, dest_ctx, &ce_info[f]);
3501 ice_read_dword(src_ctx, dest_ctx, &ce_info[f]);
3504 ice_read_qword(src_ctx, dest_ctx, &ce_info[f]);
3507 /* nothing to do, just keep going */
3516 * ice_get_lan_q_ctx - get the LAN queue context for the given VSI and TC
3517 * @hw: pointer to the HW struct
3518 * @vsi_handle: software VSI handle
3520 * @q_handle: software queue handle
3522 static struct ice_q_ctx *
3523 ice_get_lan_q_ctx(struct ice_hw *hw, u16 vsi_handle, u8 tc, u16 q_handle)
3525 struct ice_vsi_ctx *vsi;
3526 struct ice_q_ctx *q_ctx;
3528 vsi = ice_get_vsi_ctx(hw, vsi_handle);
3531 if (q_handle >= vsi->num_lan_q_entries[tc])
3533 if (!vsi->lan_q_ctx[tc])
3535 q_ctx = vsi->lan_q_ctx[tc];
3536 return &q_ctx[q_handle];
3541 * @pi: port information structure
3542 * @vsi_handle: software VSI handle
3544 * @q_handle: software queue handle
3545 * @num_qgrps: Number of added queue groups
3546 * @buf: list of queue groups to be added
3547 * @buf_size: size of buffer for indirect command
3548 * @cd: pointer to command details structure or NULL
3550 * This function adds one LAN queue
3553 ice_ena_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u16 q_handle,
3554 u8 num_qgrps, struct ice_aqc_add_tx_qgrp *buf, u16 buf_size,
3555 struct ice_sq_cd *cd)
3557 struct ice_aqc_txsched_elem_data node = { 0 };
3558 struct ice_sched_node *parent;
3559 struct ice_q_ctx *q_ctx;
3560 enum ice_status status;
3563 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY)
3566 if (num_qgrps > 1 || buf->num_txqs > 1)
3567 return ICE_ERR_MAX_LIMIT;
3571 if (!ice_is_vsi_valid(hw, vsi_handle))
3572 return ICE_ERR_PARAM;
3574 ice_acquire_lock(&pi->sched_lock);
3576 q_ctx = ice_get_lan_q_ctx(hw, vsi_handle, tc, q_handle);
3578 ice_debug(hw, ICE_DBG_SCHED, "Enaq: invalid queue handle %d\n",
3580 status = ICE_ERR_PARAM;
3584 /* find a parent node */
3585 parent = ice_sched_get_free_qparent(pi, vsi_handle, tc,
3586 ICE_SCHED_NODE_OWNER_LAN);
3588 status = ICE_ERR_PARAM;
3592 buf->parent_teid = parent->info.node_teid;
3593 node.parent_teid = parent->info.node_teid;
3594 /* Mark that the values in the "generic" section as valid. The default
3595 * value in the "generic" section is zero. This means that :
3596 * - Scheduling mode is Bytes Per Second (BPS), indicated by Bit 0.
3597 * - 0 priority among siblings, indicated by Bit 1-3.
3598 * - WFQ, indicated by Bit 4.
3599 * - 0 Adjustment value is used in PSM credit update flow, indicated by
3601 * - Bit 7 is reserved.
3602 * Without setting the generic section as valid in valid_sections, the
3603 * Admin queue command will fail with error code ICE_AQ_RC_EINVAL.
3605 buf->txqs[0].info.valid_sections = ICE_AQC_ELEM_VALID_GENERIC;
3607 /* add the LAN queue */
3608 status = ice_aq_add_lan_txq(hw, num_qgrps, buf, buf_size, cd);
3609 if (status != ICE_SUCCESS) {
3610 ice_debug(hw, ICE_DBG_SCHED, "enable queue %d failed %d\n",
3611 LE16_TO_CPU(buf->txqs[0].txq_id),
3612 hw->adminq.sq_last_status);
3616 node.node_teid = buf->txqs[0].q_teid;
3617 node.data.elem_type = ICE_AQC_ELEM_TYPE_LEAF;
3618 q_ctx->q_handle = q_handle;
3620 /* add a leaf node into schduler tree queue layer */
3621 status = ice_sched_add_node(pi, hw->num_tx_sched_layers - 1, &node);
3624 ice_release_lock(&pi->sched_lock);
3630 * @pi: port information structure
3631 * @vsi_handle: software VSI handle
3633 * @num_queues: number of queues
3634 * @q_handles: pointer to software queue handle array
3635 * @q_ids: pointer to the q_id array
3636 * @q_teids: pointer to queue node teids
3637 * @rst_src: if called due to reset, specifies the reset source
3638 * @vmvf_num: the relative VM or VF number that is undergoing the reset
3639 * @cd: pointer to command details structure or NULL
3641 * This function removes queues and their corresponding nodes in SW DB
3644 ice_dis_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u8 num_queues,
3645 u16 *q_handles, u16 *q_ids, u32 *q_teids,
3646 enum ice_disq_rst_src rst_src, u16 vmvf_num,
3647 struct ice_sq_cd *cd)
3649 enum ice_status status = ICE_ERR_DOES_NOT_EXIST;
3650 struct ice_aqc_dis_txq_item qg_list;
3651 struct ice_q_ctx *q_ctx;
3654 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY)
3657 /* if queue is disabled already yet the disable queue command has to be
3658 * sent to complete the VF reset, then call ice_aq_dis_lan_txq without
3659 * any queue information
3662 if (!num_queues && rst_src)
3663 return ice_aq_dis_lan_txq(pi->hw, 0, NULL, 0, rst_src, vmvf_num,
3666 ice_acquire_lock(&pi->sched_lock);
3668 for (i = 0; i < num_queues; i++) {
3669 struct ice_sched_node *node;
3671 node = ice_sched_find_node_by_teid(pi->root, q_teids[i]);
3674 q_ctx = ice_get_lan_q_ctx(pi->hw, vsi_handle, tc, q_handles[i]);
3676 ice_debug(pi->hw, ICE_DBG_SCHED, "invalid queue handle%d\n",
3680 if (q_ctx->q_handle != q_handles[i]) {
3681 ice_debug(pi->hw, ICE_DBG_SCHED, "Err:handles %d %d\n",
3682 q_ctx->q_handle, q_handles[i]);
3685 qg_list.parent_teid = node->info.parent_teid;
3687 qg_list.q_id[0] = CPU_TO_LE16(q_ids[i]);
3688 status = ice_aq_dis_lan_txq(pi->hw, 1, &qg_list,
3689 sizeof(qg_list), rst_src, vmvf_num,
3692 if (status != ICE_SUCCESS)
3694 ice_free_sched_node(pi, node);
3695 q_ctx->q_handle = ICE_INVAL_Q_HANDLE;
3697 ice_release_lock(&pi->sched_lock);
3702 * ice_cfg_vsi_qs - configure the new/existing VSI queues
3703 * @pi: port information structure
3704 * @vsi_handle: software VSI handle
3705 * @tc_bitmap: TC bitmap
3706 * @maxqs: max queues array per TC
3707 * @owner: LAN or RDMA
3709 * This function adds/updates the VSI queues per TC.
3711 static enum ice_status
3712 ice_cfg_vsi_qs(struct ice_port_info *pi, u16 vsi_handle, u8 tc_bitmap,
3713 u16 *maxqs, u8 owner)
3715 enum ice_status status = ICE_SUCCESS;
3718 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY)
3721 if (!ice_is_vsi_valid(pi->hw, vsi_handle))
3722 return ICE_ERR_PARAM;
3724 ice_acquire_lock(&pi->sched_lock);
3726 ice_for_each_traffic_class(i) {
3727 /* configuration is possible only if TC node is present */
3728 if (!ice_sched_get_tc_node(pi, i))
3731 status = ice_sched_cfg_vsi(pi, vsi_handle, i, maxqs[i], owner,
3732 ice_is_tc_ena(tc_bitmap, i));
3737 ice_release_lock(&pi->sched_lock);
3742 * ice_cfg_vsi_lan - configure VSI LAN queues
3743 * @pi: port information structure
3744 * @vsi_handle: software VSI handle
3745 * @tc_bitmap: TC bitmap
3746 * @max_lanqs: max LAN queues array per TC
3748 * This function adds/updates the VSI LAN queues per TC.
3751 ice_cfg_vsi_lan(struct ice_port_info *pi, u16 vsi_handle, u8 tc_bitmap,
3754 return ice_cfg_vsi_qs(pi, vsi_handle, tc_bitmap, max_lanqs,
3755 ICE_SCHED_NODE_OWNER_LAN);
3761 * ice_replay_pre_init - replay pre initialization
3762 * @hw: pointer to the HW struct
3764 * Initializes required config data for VSI, FD, ACL, and RSS before replay.
3766 static enum ice_status ice_replay_pre_init(struct ice_hw *hw)
3768 struct ice_switch_info *sw = hw->switch_info;
3771 /* Delete old entries from replay filter list head if there is any */
3772 ice_rm_all_sw_replay_rule_info(hw);
3773 /* In start of replay, move entries into replay_rules list, it
3774 * will allow adding rules entries back to filt_rules list,
3775 * which is operational list.
3777 for (i = 0; i < ICE_MAX_NUM_RECIPES; i++)
3778 LIST_REPLACE_INIT(&sw->recp_list[i].filt_rules,
3779 &sw->recp_list[i].filt_replay_rules);
3780 ice_sched_replay_agg_vsi_preinit(hw);
3782 return ice_sched_replay_tc_node_bw(hw);
3786 * ice_replay_vsi - replay VSI configuration
3787 * @hw: pointer to the HW struct
3788 * @vsi_handle: driver VSI handle
3790 * Restore all VSI configuration after reset. It is required to call this
3791 * function with main VSI first.
3793 enum ice_status ice_replay_vsi(struct ice_hw *hw, u16 vsi_handle)
3795 enum ice_status status;
3797 if (!ice_is_vsi_valid(hw, vsi_handle))
3798 return ICE_ERR_PARAM;
3800 /* Replay pre-initialization if there is any */
3801 if (vsi_handle == ICE_MAIN_VSI_HANDLE) {
3802 status = ice_replay_pre_init(hw);
3807 /* Replay per VSI all filters */
3808 status = ice_replay_vsi_all_fltr(hw, vsi_handle);
3810 status = ice_replay_vsi_agg(hw, vsi_handle);
3815 * ice_replay_post - post replay configuration cleanup
3816 * @hw: pointer to the HW struct
3818 * Post replay cleanup.
3820 void ice_replay_post(struct ice_hw *hw)
3822 /* Delete old entries from replay filter list head */
3823 ice_rm_all_sw_replay_rule_info(hw);
3824 ice_sched_replay_agg(hw);
3828 * ice_stat_update40 - read 40 bit stat from the chip and update stat values
3829 * @hw: ptr to the hardware info
3830 * @hireg: high 32 bit HW register to read from
3831 * @loreg: low 32 bit HW register to read from
3832 * @prev_stat_loaded: bool to specify if previous stats are loaded
3833 * @prev_stat: ptr to previous loaded stat value
3834 * @cur_stat: ptr to current stat value
3837 ice_stat_update40(struct ice_hw *hw, u32 hireg, u32 loreg,
3838 bool prev_stat_loaded, u64 *prev_stat, u64 *cur_stat)
3842 new_data = rd32(hw, loreg);
3843 new_data |= ((u64)(rd32(hw, hireg) & 0xFFFF)) << 32;
3845 /* device stats are not reset at PFR, they likely will not be zeroed
3846 * when the driver starts. So save the first values read and use them as
3847 * offsets to be subtracted from the raw values in order to report stats
3848 * that count from zero.
3850 if (!prev_stat_loaded)
3851 *prev_stat = new_data;
3852 if (new_data >= *prev_stat)
3853 *cur_stat = new_data - *prev_stat;
3855 /* to manage the potential roll-over */
3856 *cur_stat = (new_data + BIT_ULL(40)) - *prev_stat;
3857 *cur_stat &= 0xFFFFFFFFFFULL;
3861 * ice_stat_update32 - read 32 bit stat from the chip and update stat values
3862 * @hw: ptr to the hardware info
3863 * @reg: HW register to read from
3864 * @prev_stat_loaded: bool to specify if previous stats are loaded
3865 * @prev_stat: ptr to previous loaded stat value
3866 * @cur_stat: ptr to current stat value
3869 ice_stat_update32(struct ice_hw *hw, u32 reg, bool prev_stat_loaded,
3870 u64 *prev_stat, u64 *cur_stat)
3874 new_data = rd32(hw, reg);
3876 /* device stats are not reset at PFR, they likely will not be zeroed
3877 * when the driver starts. So save the first values read and use them as
3878 * offsets to be subtracted from the raw values in order to report stats
3879 * that count from zero.
3881 if (!prev_stat_loaded)
3882 *prev_stat = new_data;
3883 if (new_data >= *prev_stat)
3884 *cur_stat = new_data - *prev_stat;
3886 /* to manage the potential roll-over */
3887 *cur_stat = (new_data + BIT_ULL(32)) - *prev_stat;
3892 * ice_sched_query_elem - query element information from HW
3893 * @hw: pointer to the HW struct
3894 * @node_teid: node TEID to be queried
3895 * @buf: buffer to element information
3897 * This function queries HW element information
3900 ice_sched_query_elem(struct ice_hw *hw, u32 node_teid,
3901 struct ice_aqc_get_elem *buf)
3903 u16 buf_size, num_elem_ret = 0;
3904 enum ice_status status;
3906 buf_size = sizeof(*buf);
3907 ice_memset(buf, 0, buf_size, ICE_NONDMA_MEM);
3908 buf->generic[0].node_teid = CPU_TO_LE32(node_teid);
3909 status = ice_aq_query_sched_elems(hw, 1, buf, buf_size, &num_elem_ret,
3911 if (status != ICE_SUCCESS || num_elem_ret != 1)
3912 ice_debug(hw, ICE_DBG_SCHED, "query element failed\n");