1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2001-2019
5 #include "ice_common.h"
7 #include "ice_adminq_cmd.h"
10 #include "ice_switch.h"
12 #define ICE_PF_RESET_WAIT_COUNT 200
14 #define ICE_PROG_FLEX_ENTRY(hw, rxdid, mdid, idx) \
15 wr32((hw), GLFLXP_RXDID_FLX_WRD_##idx(rxdid), \
16 ((ICE_RX_OPC_MDID << \
17 GLFLXP_RXDID_FLX_WRD_##idx##_RXDID_OPCODE_S) & \
18 GLFLXP_RXDID_FLX_WRD_##idx##_RXDID_OPCODE_M) | \
19 (((mdid) << GLFLXP_RXDID_FLX_WRD_##idx##_PROT_MDID_S) & \
20 GLFLXP_RXDID_FLX_WRD_##idx##_PROT_MDID_M))
22 #define ICE_PROG_FLEX_ENTRY_EXTRACT(hw, rxdid, protid, off, idx) \
23 wr32((hw), GLFLXP_RXDID_FLX_WRD_##idx(rxdid), \
24 ((ICE_RX_OPC_EXTRACT << \
25 GLFLXP_RXDID_FLX_WRD_##idx##_RXDID_OPCODE_S) & \
26 GLFLXP_RXDID_FLX_WRD_##idx##_RXDID_OPCODE_M) | \
27 (((protid) << GLFLXP_RXDID_FLX_WRD_##idx##_PROT_MDID_S) & \
28 GLFLXP_RXDID_FLX_WRD_##idx##_PROT_MDID_M) | \
29 (((off) << GLFLXP_RXDID_FLX_WRD_##idx##_EXTRACTION_OFFSET_S) & \
30 GLFLXP_RXDID_FLX_WRD_##idx##_EXTRACTION_OFFSET_M))
32 #define ICE_PROG_FLG_ENTRY(hw, rxdid, flg_0, flg_1, flg_2, flg_3, idx) \
33 wr32((hw), GLFLXP_RXDID_FLAGS(rxdid, idx), \
34 (((flg_0) << GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_S) & \
35 GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_M) | \
36 (((flg_1) << GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_1_S) & \
37 GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_1_M) | \
38 (((flg_2) << GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_2_S) & \
39 GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_2_M) | \
40 (((flg_3) << GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_3_S) & \
41 GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_3_M))
45 * ice_set_mac_type - Sets MAC type
46 * @hw: pointer to the HW structure
48 * This function sets the MAC type of the adapter based on the
49 * vendor ID and device ID stored in the HW structure.
51 static enum ice_status ice_set_mac_type(struct ice_hw *hw)
53 enum ice_status status = ICE_SUCCESS;
55 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
57 if (hw->vendor_id == ICE_INTEL_VENDOR_ID) {
58 switch (hw->device_id) {
60 hw->mac_type = ICE_MAC_GENERIC;
64 status = ICE_ERR_DEVICE_NOT_SUPPORTED;
67 ice_debug(hw, ICE_DBG_INIT, "found mac_type: %d, status: %d\n",
68 hw->mac_type, status);
75 * ice_clear_pf_cfg - Clear PF configuration
76 * @hw: pointer to the hardware structure
78 * Clears any existing PF configuration (VSIs, VSI lists, switch rules, port
79 * configuration, flow director filters, etc.).
81 enum ice_status ice_clear_pf_cfg(struct ice_hw *hw)
83 struct ice_aq_desc desc;
85 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pf_cfg);
87 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
91 * ice_aq_manage_mac_read - manage MAC address read command
92 * @hw: pointer to the HW struct
93 * @buf: a virtual buffer to hold the manage MAC read response
94 * @buf_size: Size of the virtual buffer
95 * @cd: pointer to command details structure or NULL
97 * This function is used to return per PF station MAC address (0x0107).
98 * NOTE: Upon successful completion of this command, MAC address information
99 * is returned in user specified buffer. Please interpret user specified
100 * buffer as "manage_mac_read" response.
101 * Response such as various MAC addresses are stored in HW struct (port.mac)
102 * ice_aq_discover_caps is expected to be called before this function is called.
104 static enum ice_status
105 ice_aq_manage_mac_read(struct ice_hw *hw, void *buf, u16 buf_size,
106 struct ice_sq_cd *cd)
108 struct ice_aqc_manage_mac_read_resp *resp;
109 struct ice_aqc_manage_mac_read *cmd;
110 struct ice_aq_desc desc;
111 enum ice_status status;
115 cmd = &desc.params.mac_read;
117 if (buf_size < sizeof(*resp))
118 return ICE_ERR_BUF_TOO_SHORT;
120 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_read);
122 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);
126 resp = (struct ice_aqc_manage_mac_read_resp *)buf;
127 flags = LE16_TO_CPU(cmd->flags) & ICE_AQC_MAN_MAC_READ_M;
129 if (!(flags & ICE_AQC_MAN_MAC_LAN_ADDR_VALID)) {
130 ice_debug(hw, ICE_DBG_LAN, "got invalid MAC address\n");
134 /* A single port can report up to two (LAN and WoL) addresses */
135 for (i = 0; i < cmd->num_addr; i++)
136 if (resp[i].addr_type == ICE_AQC_MAN_MAC_ADDR_TYPE_LAN) {
137 ice_memcpy(hw->port_info->mac.lan_addr,
138 resp[i].mac_addr, ETH_ALEN,
140 ice_memcpy(hw->port_info->mac.perm_addr,
142 ETH_ALEN, ICE_DMA_TO_NONDMA);
150 * ice_aq_get_phy_caps - returns PHY capabilities
151 * @pi: port information structure
152 * @qual_mods: report qualified modules
153 * @report_mode: report mode capabilities
154 * @pcaps: structure for PHY capabilities to be filled
155 * @cd: pointer to command details structure or NULL
157 * Returns the various PHY capabilities supported on the Port (0x0600)
160 ice_aq_get_phy_caps(struct ice_port_info *pi, bool qual_mods, u8 report_mode,
161 struct ice_aqc_get_phy_caps_data *pcaps,
162 struct ice_sq_cd *cd)
164 struct ice_aqc_get_phy_caps *cmd;
165 u16 pcaps_size = sizeof(*pcaps);
166 struct ice_aq_desc desc;
167 enum ice_status status;
169 cmd = &desc.params.get_phy;
171 if (!pcaps || (report_mode & ~ICE_AQC_REPORT_MODE_M) || !pi)
172 return ICE_ERR_PARAM;
174 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_phy_caps);
177 cmd->param0 |= CPU_TO_LE16(ICE_AQC_GET_PHY_RQM);
179 cmd->param0 |= CPU_TO_LE16(report_mode);
180 status = ice_aq_send_cmd(pi->hw, &desc, pcaps, pcaps_size, cd);
182 if (status == ICE_SUCCESS && report_mode == ICE_AQC_REPORT_TOPO_CAP) {
183 pi->phy.phy_type_low = LE64_TO_CPU(pcaps->phy_type_low);
184 pi->phy.phy_type_high = LE64_TO_CPU(pcaps->phy_type_high);
191 * ice_aq_get_link_topo_handle - get link topology node return status
192 * @pi: port information structure
193 * @node_type: requested node type
194 * @cd: pointer to command details structure or NULL
196 * Get link topology node return status for specified node type (0x06E0)
198 * Node type cage can be used to determine if cage is present. If AQC
199 * returns error (ENOENT), then no cage present. If no cage present, then
200 * connection type is backplane or BASE-T.
202 static enum ice_status
203 ice_aq_get_link_topo_handle(struct ice_port_info *pi, u8 node_type,
204 struct ice_sq_cd *cd)
206 struct ice_aqc_get_link_topo *cmd;
207 struct ice_aq_desc desc;
209 cmd = &desc.params.get_link_topo;
212 return ICE_ERR_PARAM;
214 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_topo);
216 cmd->addr.node_type_ctx = (ICE_AQC_LINK_TOPO_NODE_CTX_PORT <<
217 ICE_AQC_LINK_TOPO_NODE_CTX_S);
220 cmd->addr.node_type_ctx |= (ICE_AQC_LINK_TOPO_NODE_TYPE_M & node_type);
222 return ice_aq_send_cmd(pi->hw, &desc, NULL, 0, cd);
226 * ice_is_media_cage_present
227 * @pi: port information structure
229 * Returns true if media cage is present, else false. If no cage, then
230 * media type is backplane or BASE-T.
232 static bool ice_is_media_cage_present(struct ice_port_info *pi)
234 /* Node type cage can be used to determine if cage is present. If AQC
235 * returns error (ENOENT), then no cage present. If no cage present then
236 * connection type is backplane or BASE-T.
238 return !ice_aq_get_link_topo_handle(pi,
239 ICE_AQC_LINK_TOPO_NODE_TYPE_CAGE,
244 * ice_get_media_type - Gets media type
245 * @pi: port information structure
247 static enum ice_media_type ice_get_media_type(struct ice_port_info *pi)
249 struct ice_link_status *hw_link_info;
252 return ICE_MEDIA_UNKNOWN;
254 hw_link_info = &pi->phy.link_info;
255 if (hw_link_info->phy_type_low && hw_link_info->phy_type_high)
256 /* If more than one media type is selected, report unknown */
257 return ICE_MEDIA_UNKNOWN;
259 if (hw_link_info->phy_type_low) {
260 switch (hw_link_info->phy_type_low) {
261 case ICE_PHY_TYPE_LOW_1000BASE_SX:
262 case ICE_PHY_TYPE_LOW_1000BASE_LX:
263 case ICE_PHY_TYPE_LOW_10GBASE_SR:
264 case ICE_PHY_TYPE_LOW_10GBASE_LR:
265 case ICE_PHY_TYPE_LOW_10G_SFI_C2C:
266 case ICE_PHY_TYPE_LOW_25GBASE_SR:
267 case ICE_PHY_TYPE_LOW_25GBASE_LR:
268 case ICE_PHY_TYPE_LOW_40GBASE_SR4:
269 case ICE_PHY_TYPE_LOW_40GBASE_LR4:
270 case ICE_PHY_TYPE_LOW_50GBASE_SR2:
271 case ICE_PHY_TYPE_LOW_50GBASE_LR2:
272 case ICE_PHY_TYPE_LOW_50GBASE_SR:
273 case ICE_PHY_TYPE_LOW_50GBASE_FR:
274 case ICE_PHY_TYPE_LOW_50GBASE_LR:
275 case ICE_PHY_TYPE_LOW_100GBASE_SR4:
276 case ICE_PHY_TYPE_LOW_100GBASE_LR4:
277 case ICE_PHY_TYPE_LOW_100GBASE_SR2:
278 case ICE_PHY_TYPE_LOW_100GBASE_DR:
279 return ICE_MEDIA_FIBER;
280 case ICE_PHY_TYPE_LOW_100BASE_TX:
281 case ICE_PHY_TYPE_LOW_1000BASE_T:
282 case ICE_PHY_TYPE_LOW_2500BASE_T:
283 case ICE_PHY_TYPE_LOW_5GBASE_T:
284 case ICE_PHY_TYPE_LOW_10GBASE_T:
285 case ICE_PHY_TYPE_LOW_25GBASE_T:
286 return ICE_MEDIA_BASET;
287 case ICE_PHY_TYPE_LOW_10G_SFI_DA:
288 case ICE_PHY_TYPE_LOW_25GBASE_CR:
289 case ICE_PHY_TYPE_LOW_25GBASE_CR_S:
290 case ICE_PHY_TYPE_LOW_25GBASE_CR1:
291 case ICE_PHY_TYPE_LOW_40GBASE_CR4:
292 case ICE_PHY_TYPE_LOW_50GBASE_CR2:
293 case ICE_PHY_TYPE_LOW_50GBASE_CP:
294 case ICE_PHY_TYPE_LOW_100GBASE_CR4:
295 case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4:
296 case ICE_PHY_TYPE_LOW_100GBASE_CP2:
298 case ICE_PHY_TYPE_LOW_25G_AUI_C2C:
299 case ICE_PHY_TYPE_LOW_40G_XLAUI:
300 case ICE_PHY_TYPE_LOW_50G_LAUI2:
301 case ICE_PHY_TYPE_LOW_50G_AUI2:
302 case ICE_PHY_TYPE_LOW_50G_AUI1:
303 case ICE_PHY_TYPE_LOW_100G_AUI4:
304 case ICE_PHY_TYPE_LOW_100G_CAUI4:
305 if (ice_is_media_cage_present(pi))
308 case ICE_PHY_TYPE_LOW_1000BASE_KX:
309 case ICE_PHY_TYPE_LOW_2500BASE_KX:
310 case ICE_PHY_TYPE_LOW_2500BASE_X:
311 case ICE_PHY_TYPE_LOW_5GBASE_KR:
312 case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1:
313 case ICE_PHY_TYPE_LOW_25GBASE_KR:
314 case ICE_PHY_TYPE_LOW_25GBASE_KR1:
315 case ICE_PHY_TYPE_LOW_25GBASE_KR_S:
316 case ICE_PHY_TYPE_LOW_40GBASE_KR4:
317 case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4:
318 case ICE_PHY_TYPE_LOW_50GBASE_KR2:
319 case ICE_PHY_TYPE_LOW_100GBASE_KR4:
320 case ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4:
321 return ICE_MEDIA_BACKPLANE;
324 switch (hw_link_info->phy_type_high) {
325 case ICE_PHY_TYPE_HIGH_100G_AUI2:
326 if (ice_is_media_cage_present(pi))
329 case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4:
330 return ICE_MEDIA_BACKPLANE;
333 return ICE_MEDIA_UNKNOWN;
337 * ice_aq_get_link_info
338 * @pi: port information structure
339 * @ena_lse: enable/disable LinkStatusEvent reporting
340 * @link: pointer to link status structure - optional
341 * @cd: pointer to command details structure or NULL
343 * Get Link Status (0x607). Returns the link status of the adapter.
346 ice_aq_get_link_info(struct ice_port_info *pi, bool ena_lse,
347 struct ice_link_status *link, struct ice_sq_cd *cd)
349 struct ice_aqc_get_link_status_data link_data = { 0 };
350 struct ice_aqc_get_link_status *resp;
351 struct ice_link_status *li_old, *li;
352 enum ice_media_type *hw_media_type;
353 struct ice_fc_info *hw_fc_info;
354 bool tx_pause, rx_pause;
355 struct ice_aq_desc desc;
356 enum ice_status status;
361 return ICE_ERR_PARAM;
363 li_old = &pi->phy.link_info_old;
364 hw_media_type = &pi->phy.media_type;
365 li = &pi->phy.link_info;
366 hw_fc_info = &pi->fc;
368 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_status);
369 cmd_flags = (ena_lse) ? ICE_AQ_LSE_ENA : ICE_AQ_LSE_DIS;
370 resp = &desc.params.get_link_status;
371 resp->cmd_flags = CPU_TO_LE16(cmd_flags);
372 resp->lport_num = pi->lport;
374 status = ice_aq_send_cmd(hw, &desc, &link_data, sizeof(link_data), cd);
376 if (status != ICE_SUCCESS)
379 /* save off old link status information */
382 /* update current link status information */
383 li->link_speed = LE16_TO_CPU(link_data.link_speed);
384 li->phy_type_low = LE64_TO_CPU(link_data.phy_type_low);
385 li->phy_type_high = LE64_TO_CPU(link_data.phy_type_high);
386 *hw_media_type = ice_get_media_type(pi);
387 li->link_info = link_data.link_info;
388 li->an_info = link_data.an_info;
389 li->ext_info = link_data.ext_info;
390 li->max_frame_size = LE16_TO_CPU(link_data.max_frame_size);
391 li->fec_info = link_data.cfg & ICE_AQ_FEC_MASK;
392 li->topo_media_conflict = link_data.topo_media_conflict;
393 li->pacing = link_data.cfg & (ICE_AQ_CFG_PACING_M |
394 ICE_AQ_CFG_PACING_TYPE_M);
397 tx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_TX);
398 rx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_RX);
399 if (tx_pause && rx_pause)
400 hw_fc_info->current_mode = ICE_FC_FULL;
402 hw_fc_info->current_mode = ICE_FC_TX_PAUSE;
404 hw_fc_info->current_mode = ICE_FC_RX_PAUSE;
406 hw_fc_info->current_mode = ICE_FC_NONE;
408 li->lse_ena = !!(resp->cmd_flags & CPU_TO_LE16(ICE_AQ_LSE_IS_ENABLED));
410 ice_debug(hw, ICE_DBG_LINK, "link_speed = 0x%x\n", li->link_speed);
411 ice_debug(hw, ICE_DBG_LINK, "phy_type_low = 0x%llx\n",
412 (unsigned long long)li->phy_type_low);
413 ice_debug(hw, ICE_DBG_LINK, "phy_type_high = 0x%llx\n",
414 (unsigned long long)li->phy_type_high);
415 ice_debug(hw, ICE_DBG_LINK, "media_type = 0x%x\n", *hw_media_type);
416 ice_debug(hw, ICE_DBG_LINK, "link_info = 0x%x\n", li->link_info);
417 ice_debug(hw, ICE_DBG_LINK, "an_info = 0x%x\n", li->an_info);
418 ice_debug(hw, ICE_DBG_LINK, "ext_info = 0x%x\n", li->ext_info);
419 ice_debug(hw, ICE_DBG_LINK, "lse_ena = 0x%x\n", li->lse_ena);
420 ice_debug(hw, ICE_DBG_LINK, "max_frame = 0x%x\n", li->max_frame_size);
421 ice_debug(hw, ICE_DBG_LINK, "pacing = 0x%x\n", li->pacing);
423 /* save link status information */
427 /* flag cleared so calling functions don't call AQ again */
428 pi->phy.get_link_info = false;
434 * ice_init_flex_flags
435 * @hw: pointer to the hardware structure
436 * @prof_id: Rx Descriptor Builder profile ID
438 * Function to initialize Rx flex flags
440 static void ice_init_flex_flags(struct ice_hw *hw, enum ice_rxdid prof_id)
444 /* Flex-flag fields (0-2) are programmed with FLG64 bits with layout:
445 * flexiflags0[5:0] - TCP flags, is_packet_fragmented, is_packet_UDP_GRE
446 * flexiflags1[3:0] - Not used for flag programming
447 * flexiflags2[7:0] - Tunnel and VLAN types
448 * 2 invalid fields in last index
451 /* Rx flex flags are currently programmed for the NIC profiles only.
452 * Different flag bit programming configurations can be added per
455 case ICE_RXDID_FLEX_NIC:
456 case ICE_RXDID_FLEX_NIC_2:
457 ICE_PROG_FLG_ENTRY(hw, prof_id, ICE_FLG_PKT_FRG,
458 ICE_FLG_UDP_GRE, ICE_FLG_PKT_DSI,
460 /* flex flag 1 is not used for flexi-flag programming, skipping
461 * these four FLG64 bits.
463 ICE_PROG_FLG_ENTRY(hw, prof_id, ICE_FLG_SYN, ICE_FLG_RST,
464 ICE_FLG_PKT_DSI, ICE_FLG_PKT_DSI, idx++);
465 ICE_PROG_FLG_ENTRY(hw, prof_id, ICE_FLG_PKT_DSI,
466 ICE_FLG_PKT_DSI, ICE_FLG_EVLAN_x8100,
467 ICE_FLG_EVLAN_x9100, idx++);
468 ICE_PROG_FLG_ENTRY(hw, prof_id, ICE_FLG_VLAN_x8100,
469 ICE_FLG_TNL_VLAN, ICE_FLG_TNL_MAC,
470 ICE_FLG_TNL0, idx++);
471 ICE_PROG_FLG_ENTRY(hw, prof_id, ICE_FLG_TNL1, ICE_FLG_TNL2,
472 ICE_FLG_PKT_DSI, ICE_FLG_PKT_DSI, idx);
476 ice_debug(hw, ICE_DBG_INIT,
477 "Flag programming for profile ID %d not supported\n",
484 * @hw: pointer to the hardware structure
485 * @prof_id: Rx Descriptor Builder profile ID
487 * Function to initialize flex descriptors
489 static void ice_init_flex_flds(struct ice_hw *hw, enum ice_rxdid prof_id)
491 enum ice_prot_id protid_0, protid_1;
492 u16 offset_0, offset_1;
493 enum ice_flex_mdid mdid;
496 case ICE_RXDID_FLEX_NIC:
497 case ICE_RXDID_FLEX_NIC_2:
498 ICE_PROG_FLEX_ENTRY(hw, prof_id, ICE_MDID_RX_HASH_LOW, 0);
499 ICE_PROG_FLEX_ENTRY(hw, prof_id, ICE_MDID_RX_HASH_HIGH, 1);
500 ICE_PROG_FLEX_ENTRY(hw, prof_id, ICE_MDID_FLOW_ID_LOWER, 2);
502 mdid = (prof_id == ICE_RXDID_FLEX_NIC_2) ?
503 ICE_MDID_SRC_VSI : ICE_MDID_FLOW_ID_HIGH;
505 ICE_PROG_FLEX_ENTRY(hw, prof_id, mdid, 3);
507 ice_init_flex_flags(hw, prof_id);
509 case ICE_RXDID_COMMS_GENERIC:
510 case ICE_RXDID_COMMS_AUX_VLAN:
511 case ICE_RXDID_COMMS_AUX_IPV4:
512 case ICE_RXDID_COMMS_AUX_IPV6:
513 case ICE_RXDID_COMMS_AUX_IPV6_FLOW:
514 case ICE_RXDID_COMMS_AUX_TCP:
515 ICE_PROG_FLEX_ENTRY(hw, prof_id, ICE_MDID_RX_HASH_LOW, 0);
516 ICE_PROG_FLEX_ENTRY(hw, prof_id, ICE_MDID_RX_HASH_HIGH, 1);
517 ICE_PROG_FLEX_ENTRY(hw, prof_id, ICE_MDID_FLOW_ID_LOWER, 2);
518 ICE_PROG_FLEX_ENTRY(hw, prof_id, ICE_MDID_FLOW_ID_HIGH, 3);
520 if (prof_id == ICE_RXDID_COMMS_AUX_VLAN) {
521 /* FlexiMD.4: VLAN1 - single or EVLAN (first for QinQ).
522 * FlexiMD.5: VLAN2 - C-VLAN (second for QinQ).
524 protid_0 = ICE_PROT_EVLAN_O;
526 protid_1 = ICE_PROT_VLAN_O;
528 } else if (prof_id == ICE_RXDID_COMMS_AUX_IPV4) {
529 /* FlexiMD.4: IPHDR1 - IPv4 header word 4, "TTL" and
531 * FlexiMD.5: IPHDR0 - IPv4 header word 0, "Ver",
532 * "Hdr Len" and "Type of Service" fields.
534 protid_0 = ICE_PROT_IPV4_OF_OR_S;
536 protid_1 = ICE_PROT_IPV4_OF_OR_S;
538 } else if (prof_id == ICE_RXDID_COMMS_AUX_IPV6) {
539 /* FlexiMD.4: IPHDR1 - IPv6 header word 3,
540 * "Next Header" and "Hop Limit" fields.
541 * FlexiMD.5: IPHDR0 - IPv6 header word 0,
542 * "Ver", "Traffic class" and high 4 bits of
543 * "Flow Label" fields.
545 protid_0 = ICE_PROT_IPV6_OF_OR_S;
547 protid_1 = ICE_PROT_IPV6_OF_OR_S;
549 } else if (prof_id == ICE_RXDID_COMMS_AUX_IPV6_FLOW) {
550 /* FlexiMD.4: IPHDR1 - IPv6 header word 1,
551 * 16 low bits of the "Flow Label" field.
552 * FlexiMD.5: IPHDR0 - IPv6 header word 0,
553 * "Ver", "Traffic class" and high 4 bits
554 * of "Flow Label" fields.
556 protid_0 = ICE_PROT_IPV6_OF_OR_S;
558 protid_1 = ICE_PROT_IPV6_OF_OR_S;
560 } else if (prof_id == ICE_RXDID_COMMS_AUX_TCP) {
561 /* FlexiMD.4: TCPHDR - TCP header word 6,
562 * "Data Offset" and "Flags" fields.
563 * FlexiMD.5: Reserved
565 protid_0 = ICE_PROT_TCP_IL;
567 protid_1 = ICE_PROT_ID_INVAL;
570 protid_0 = ICE_PROT_ID_INVAL;
572 protid_1 = ICE_PROT_ID_INVAL;
576 ICE_PROG_FLEX_ENTRY_EXTRACT(hw, prof_id,
577 protid_0, offset_0, 4);
578 ICE_PROG_FLEX_ENTRY_EXTRACT(hw, prof_id,
579 protid_1, offset_1, 5);
581 ice_init_flex_flags(hw, prof_id);
584 ice_debug(hw, ICE_DBG_INIT,
585 "Field init for profile ID %d not supported\n",
592 * @hw: pointer to the HW struct
593 * @max_frame_size: Maximum Frame Size to be supported
594 * @cd: pointer to command details structure or NULL
596 * Set MAC configuration (0x0603)
599 ice_aq_set_mac_cfg(struct ice_hw *hw, u16 max_frame_size, struct ice_sq_cd *cd)
601 u16 fc_threshold_val, tx_timer_val;
602 struct ice_aqc_set_mac_cfg *cmd;
603 struct ice_aq_desc desc;
606 cmd = &desc.params.set_mac_cfg;
608 if (max_frame_size == 0)
609 return ICE_ERR_PARAM;
611 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_mac_cfg);
613 cmd->max_frame_size = CPU_TO_LE16(max_frame_size);
615 /* We read back the transmit timer and fc threshold value of
616 * LFC. Thus, we will use index =
617 * PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX.
619 * Also, because we are opearating on transmit timer and fc
620 * threshold of LFC, we don't turn on any bit in tx_tmr_priority
622 #define IDX_OF_LFC PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX
624 /* Retrieve the transmit timer */
626 PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(IDX_OF_LFC));
627 tx_timer_val = reg_val &
628 PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_HSEC_CTL_TX_PAUSE_QUANTA_M;
629 cmd->tx_tmr_value = CPU_TO_LE16(tx_timer_val);
631 /* Retrieve the fc threshold */
633 PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(IDX_OF_LFC));
634 fc_threshold_val = reg_val & MAKEMASK(0xFFFF, 0);
635 cmd->fc_refresh_threshold = CPU_TO_LE16(fc_threshold_val);
637 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
641 * ice_init_fltr_mgmt_struct - initializes filter management list and locks
642 * @hw: pointer to the HW struct
644 static enum ice_status ice_init_fltr_mgmt_struct(struct ice_hw *hw)
646 struct ice_switch_info *sw;
648 hw->switch_info = (struct ice_switch_info *)
649 ice_malloc(hw, sizeof(*hw->switch_info));
650 sw = hw->switch_info;
653 return ICE_ERR_NO_MEMORY;
655 INIT_LIST_HEAD(&sw->vsi_list_map_head);
657 return ice_init_def_sw_recp(hw);
661 * ice_cleanup_fltr_mgmt_struct - cleanup filter management list and locks
662 * @hw: pointer to the HW struct
664 static void ice_cleanup_fltr_mgmt_struct(struct ice_hw *hw)
666 struct ice_switch_info *sw = hw->switch_info;
667 struct ice_vsi_list_map_info *v_pos_map;
668 struct ice_vsi_list_map_info *v_tmp_map;
669 struct ice_sw_recipe *recps;
672 LIST_FOR_EACH_ENTRY_SAFE(v_pos_map, v_tmp_map, &sw->vsi_list_map_head,
673 ice_vsi_list_map_info, list_entry) {
674 LIST_DEL(&v_pos_map->list_entry);
675 ice_free(hw, v_pos_map);
677 recps = hw->switch_info->recp_list;
678 for (i = 0; i < ICE_MAX_NUM_RECIPES; i++) {
679 struct ice_recp_grp_entry *rg_entry, *tmprg_entry;
681 recps[i].root_rid = i;
682 LIST_FOR_EACH_ENTRY_SAFE(rg_entry, tmprg_entry,
683 &recps[i].rg_list, ice_recp_grp_entry,
685 LIST_DEL(&rg_entry->l_entry);
686 ice_free(hw, rg_entry);
689 if (recps[i].adv_rule) {
690 struct ice_adv_fltr_mgmt_list_entry *tmp_entry;
691 struct ice_adv_fltr_mgmt_list_entry *lst_itr;
693 ice_destroy_lock(&recps[i].filt_rule_lock);
694 LIST_FOR_EACH_ENTRY_SAFE(lst_itr, tmp_entry,
695 &recps[i].filt_rules,
696 ice_adv_fltr_mgmt_list_entry,
698 LIST_DEL(&lst_itr->list_entry);
699 ice_free(hw, lst_itr->lkups);
700 ice_free(hw, lst_itr);
703 struct ice_fltr_mgmt_list_entry *lst_itr, *tmp_entry;
705 ice_destroy_lock(&recps[i].filt_rule_lock);
706 LIST_FOR_EACH_ENTRY_SAFE(lst_itr, tmp_entry,
707 &recps[i].filt_rules,
708 ice_fltr_mgmt_list_entry,
710 LIST_DEL(&lst_itr->list_entry);
711 ice_free(hw, lst_itr);
714 if (recps[i].root_buf)
715 ice_free(hw, recps[i].root_buf);
717 ice_rm_all_sw_replay_rule_info(hw);
718 ice_free(hw, sw->recp_list);
724 * ice_get_itr_intrl_gran
725 * @hw: pointer to the HW struct
727 * Determines the ITR/INTRL granularities based on the maximum aggregate
728 * bandwidth according to the device's configuration during power-on.
730 static void ice_get_itr_intrl_gran(struct ice_hw *hw)
732 u8 max_agg_bw = (rd32(hw, GL_PWR_MODE_CTL) &
733 GL_PWR_MODE_CTL_CAR_MAX_BW_M) >>
734 GL_PWR_MODE_CTL_CAR_MAX_BW_S;
736 switch (max_agg_bw) {
737 case ICE_MAX_AGG_BW_200G:
738 case ICE_MAX_AGG_BW_100G:
739 case ICE_MAX_AGG_BW_50G:
740 hw->itr_gran = ICE_ITR_GRAN_ABOVE_25;
741 hw->intrl_gran = ICE_INTRL_GRAN_ABOVE_25;
743 case ICE_MAX_AGG_BW_25G:
744 hw->itr_gran = ICE_ITR_GRAN_MAX_25;
745 hw->intrl_gran = ICE_INTRL_GRAN_MAX_25;
751 * ice_get_nvm_version - get cached NVM version data
752 * @hw: pointer to the hardware structure
753 * @oem_ver: 8 bit NVM version
754 * @oem_build: 16 bit NVM build number
755 * @oem_patch: 8 NVM patch number
756 * @ver_hi: high 16 bits of the NVM version
757 * @ver_lo: low 16 bits of the NVM version
760 ice_get_nvm_version(struct ice_hw *hw, u8 *oem_ver, u16 *oem_build,
761 u8 *oem_patch, u8 *ver_hi, u8 *ver_lo)
763 struct ice_nvm_info *nvm = &hw->nvm;
765 *oem_ver = (u8)((nvm->oem_ver & ICE_OEM_VER_MASK) >> ICE_OEM_VER_SHIFT);
766 *oem_patch = (u8)(nvm->oem_ver & ICE_OEM_VER_PATCH_MASK);
767 *oem_build = (u16)((nvm->oem_ver & ICE_OEM_VER_BUILD_MASK) >>
768 ICE_OEM_VER_BUILD_SHIFT);
769 *ver_hi = (nvm->ver & ICE_NVM_VER_HI_MASK) >> ICE_NVM_VER_HI_SHIFT;
770 *ver_lo = (nvm->ver & ICE_NVM_VER_LO_MASK) >> ICE_NVM_VER_LO_SHIFT;
774 * ice_print_rollback_msg - print FW rollback message
775 * @hw: pointer to the hardware structure
777 void ice_print_rollback_msg(struct ice_hw *hw)
779 char nvm_str[ICE_NVM_VER_LEN] = { 0 };
780 u8 oem_ver, oem_patch, ver_hi, ver_lo;
783 ice_get_nvm_version(hw, &oem_ver, &oem_build, &oem_patch, &ver_hi,
785 SNPRINTF(nvm_str, sizeof(nvm_str), "%x.%02x 0x%x %d.%d.%d", ver_hi,
786 ver_lo, hw->nvm.eetrack, oem_ver, oem_build, oem_patch);
789 "Firmware rollback mode detected. Current version is NVM: %s, FW: %d.%d. Device may exhibit limited functionality. Refer to the Intel(R) Ethernet Adapters and Devices User Guide for details on firmware rollback mode",
790 nvm_str, hw->fw_maj_ver, hw->fw_min_ver);
794 * ice_init_hw - main hardware initialization routine
795 * @hw: pointer to the hardware structure
797 enum ice_status ice_init_hw(struct ice_hw *hw)
799 struct ice_aqc_get_phy_caps_data *pcaps;
800 enum ice_status status;
804 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
807 /* Set MAC type based on DeviceID */
808 status = ice_set_mac_type(hw);
812 hw->pf_id = (u8)(rd32(hw, PF_FUNC_RID) &
813 PF_FUNC_RID_FUNCTION_NUMBER_M) >>
814 PF_FUNC_RID_FUNCTION_NUMBER_S;
817 status = ice_reset(hw, ICE_RESET_PFR);
821 ice_get_itr_intrl_gran(hw);
824 status = ice_create_all_ctrlq(hw);
826 goto err_unroll_cqinit;
828 status = ice_init_nvm(hw);
830 goto err_unroll_cqinit;
832 if (ice_get_fw_mode(hw) == ICE_FW_MODE_ROLLBACK)
833 ice_print_rollback_msg(hw);
835 status = ice_clear_pf_cfg(hw);
837 goto err_unroll_cqinit;
839 /* Set bit to enable Flow Director filters */
840 wr32(hw, PFQF_FD_ENA, PFQF_FD_ENA_FD_ENA_M);
841 INIT_LIST_HEAD(&hw->fdir_list_head);
843 ice_clear_pxe_mode(hw);
846 status = ice_get_caps(hw);
848 goto err_unroll_cqinit;
850 hw->port_info = (struct ice_port_info *)
851 ice_malloc(hw, sizeof(*hw->port_info));
852 if (!hw->port_info) {
853 status = ICE_ERR_NO_MEMORY;
854 goto err_unroll_cqinit;
857 /* set the back pointer to HW */
858 hw->port_info->hw = hw;
860 /* Initialize port_info struct with switch configuration data */
861 status = ice_get_initial_sw_cfg(hw);
863 goto err_unroll_alloc;
867 /* Query the allocated resources for Tx scheduler */
868 status = ice_sched_query_res_alloc(hw);
870 ice_debug(hw, ICE_DBG_SCHED,
871 "Failed to get scheduler allocated resources\n");
872 goto err_unroll_alloc;
876 /* Initialize port_info struct with scheduler data */
877 status = ice_sched_init_port(hw->port_info);
879 goto err_unroll_sched;
881 pcaps = (struct ice_aqc_get_phy_caps_data *)
882 ice_malloc(hw, sizeof(*pcaps));
884 status = ICE_ERR_NO_MEMORY;
885 goto err_unroll_sched;
888 /* Initialize port_info struct with PHY capabilities */
889 status = ice_aq_get_phy_caps(hw->port_info, false,
890 ICE_AQC_REPORT_TOPO_CAP, pcaps, NULL);
893 goto err_unroll_sched;
895 /* Initialize port_info struct with link information */
896 status = ice_aq_get_link_info(hw->port_info, false, NULL, NULL);
898 goto err_unroll_sched;
899 /* need a valid SW entry point to build a Tx tree */
900 if (!hw->sw_entry_point_layer) {
901 ice_debug(hw, ICE_DBG_SCHED, "invalid sw entry point\n");
902 status = ICE_ERR_CFG;
903 goto err_unroll_sched;
905 INIT_LIST_HEAD(&hw->agg_list);
906 /* Initialize max burst size */
907 if (!hw->max_burst_size)
908 ice_cfg_rl_burst_size(hw, ICE_SCHED_DFLT_BURST_SIZE);
910 status = ice_init_fltr_mgmt_struct(hw);
912 goto err_unroll_sched;
915 /* Get MAC information */
916 /* A single port can report up to two (LAN and WoL) addresses */
917 mac_buf = ice_calloc(hw, 2,
918 sizeof(struct ice_aqc_manage_mac_read_resp));
919 mac_buf_len = 2 * sizeof(struct ice_aqc_manage_mac_read_resp);
922 status = ICE_ERR_NO_MEMORY;
923 goto err_unroll_fltr_mgmt_struct;
926 status = ice_aq_manage_mac_read(hw, mac_buf, mac_buf_len, NULL);
927 ice_free(hw, mac_buf);
930 goto err_unroll_fltr_mgmt_struct;
932 ice_init_flex_flds(hw, ICE_RXDID_FLEX_NIC);
933 ice_init_flex_flds(hw, ICE_RXDID_FLEX_NIC_2);
934 ice_init_flex_flds(hw, ICE_RXDID_COMMS_GENERIC);
935 ice_init_flex_flds(hw, ICE_RXDID_COMMS_AUX_VLAN);
936 ice_init_flex_flds(hw, ICE_RXDID_COMMS_AUX_IPV4);
937 ice_init_flex_flds(hw, ICE_RXDID_COMMS_AUX_IPV6);
938 ice_init_flex_flds(hw, ICE_RXDID_COMMS_AUX_IPV6_FLOW);
939 ice_init_flex_flds(hw, ICE_RXDID_COMMS_AUX_TCP);
940 /* Obtain counter base index which would be used by flow director */
941 status = ice_alloc_fd_res_cntr(hw, &hw->fd_ctr_base);
943 goto err_unroll_fltr_mgmt_struct;
944 status = ice_init_hw_tbls(hw);
946 goto err_unroll_fltr_mgmt_struct;
949 err_unroll_fltr_mgmt_struct:
950 ice_cleanup_fltr_mgmt_struct(hw);
952 ice_sched_cleanup_all(hw);
954 ice_free(hw, hw->port_info);
955 hw->port_info = NULL;
957 ice_destroy_all_ctrlq(hw);
962 * ice_deinit_hw - unroll initialization operations done by ice_init_hw
963 * @hw: pointer to the hardware structure
965 * This should be called only during nominal operation, not as a result of
966 * ice_init_hw() failing since ice_init_hw() will take care of unrolling
967 * applicable initializations if it fails for any reason.
969 void ice_deinit_hw(struct ice_hw *hw)
971 ice_free_fd_res_cntr(hw, hw->fd_ctr_base);
972 ice_cleanup_fltr_mgmt_struct(hw);
974 ice_sched_cleanup_all(hw);
975 ice_sched_clear_agg(hw);
977 ice_free_hw_tbls(hw);
980 ice_free(hw, hw->port_info);
981 hw->port_info = NULL;
984 ice_destroy_all_ctrlq(hw);
986 /* Clear VSI contexts if not already cleared */
987 ice_clear_all_vsi_ctx(hw);
991 * ice_check_reset - Check to see if a global reset is complete
992 * @hw: pointer to the hardware structure
994 enum ice_status ice_check_reset(struct ice_hw *hw)
996 u32 cnt, reg = 0, grst_delay;
998 /* Poll for Device Active state in case a recent CORER, GLOBR,
999 * or EMPR has occurred. The grst delay value is in 100ms units.
1000 * Add 1sec for outstanding AQ commands that can take a long time.
1002 grst_delay = ((rd32(hw, GLGEN_RSTCTL) & GLGEN_RSTCTL_GRSTDEL_M) >>
1003 GLGEN_RSTCTL_GRSTDEL_S) + 10;
1005 for (cnt = 0; cnt < grst_delay; cnt++) {
1006 ice_msec_delay(100, true);
1007 reg = rd32(hw, GLGEN_RSTAT);
1008 if (!(reg & GLGEN_RSTAT_DEVSTATE_M))
1012 if (cnt == grst_delay) {
1013 ice_debug(hw, ICE_DBG_INIT,
1014 "Global reset polling failed to complete.\n");
1015 return ICE_ERR_RESET_FAILED;
1018 #define ICE_RESET_DONE_MASK (GLNVM_ULD_CORER_DONE_M | \
1019 GLNVM_ULD_GLOBR_DONE_M)
1021 /* Device is Active; check Global Reset processes are done */
1022 for (cnt = 0; cnt < ICE_PF_RESET_WAIT_COUNT; cnt++) {
1023 reg = rd32(hw, GLNVM_ULD) & ICE_RESET_DONE_MASK;
1024 if (reg == ICE_RESET_DONE_MASK) {
1025 ice_debug(hw, ICE_DBG_INIT,
1026 "Global reset processes done. %d\n", cnt);
1029 ice_msec_delay(10, true);
1032 if (cnt == ICE_PF_RESET_WAIT_COUNT) {
1033 ice_debug(hw, ICE_DBG_INIT,
1034 "Wait for Reset Done timed out. GLNVM_ULD = 0x%x\n",
1036 return ICE_ERR_RESET_FAILED;
1043 * ice_pf_reset - Reset the PF
1044 * @hw: pointer to the hardware structure
1046 * If a global reset has been triggered, this function checks
1047 * for its completion and then issues the PF reset
1049 static enum ice_status ice_pf_reset(struct ice_hw *hw)
1053 /* If at function entry a global reset was already in progress, i.e.
1054 * state is not 'device active' or any of the reset done bits are not
1055 * set in GLNVM_ULD, there is no need for a PF Reset; poll until the
1056 * global reset is done.
1058 if ((rd32(hw, GLGEN_RSTAT) & GLGEN_RSTAT_DEVSTATE_M) ||
1059 (rd32(hw, GLNVM_ULD) & ICE_RESET_DONE_MASK) ^ ICE_RESET_DONE_MASK) {
1060 /* poll on global reset currently in progress until done */
1061 if (ice_check_reset(hw))
1062 return ICE_ERR_RESET_FAILED;
1068 reg = rd32(hw, PFGEN_CTRL);
1070 wr32(hw, PFGEN_CTRL, (reg | PFGEN_CTRL_PFSWR_M));
1072 for (cnt = 0; cnt < ICE_PF_RESET_WAIT_COUNT; cnt++) {
1073 reg = rd32(hw, PFGEN_CTRL);
1074 if (!(reg & PFGEN_CTRL_PFSWR_M))
1077 ice_msec_delay(1, true);
1080 if (cnt == ICE_PF_RESET_WAIT_COUNT) {
1081 ice_debug(hw, ICE_DBG_INIT,
1082 "PF reset polling failed to complete.\n");
1083 return ICE_ERR_RESET_FAILED;
1090 * ice_reset - Perform different types of reset
1091 * @hw: pointer to the hardware structure
1092 * @req: reset request
1094 * This function triggers a reset as specified by the req parameter.
1097 * If anything other than a PF reset is triggered, PXE mode is restored.
1098 * This has to be cleared using ice_clear_pxe_mode again, once the AQ
1099 * interface has been restored in the rebuild flow.
1101 enum ice_status ice_reset(struct ice_hw *hw, enum ice_reset_req req)
1107 return ice_pf_reset(hw);
1108 case ICE_RESET_CORER:
1109 ice_debug(hw, ICE_DBG_INIT, "CoreR requested\n");
1110 val = GLGEN_RTRIG_CORER_M;
1112 case ICE_RESET_GLOBR:
1113 ice_debug(hw, ICE_DBG_INIT, "GlobalR requested\n");
1114 val = GLGEN_RTRIG_GLOBR_M;
1117 return ICE_ERR_PARAM;
1120 val |= rd32(hw, GLGEN_RTRIG);
1121 wr32(hw, GLGEN_RTRIG, val);
1125 /* wait for the FW to be ready */
1126 return ice_check_reset(hw);
1130 * ice_get_pfa_module_tlv - Reads sub module TLV from NVM PFA
1131 * @hw: pointer to hardware structure
1132 * @module_tlv: pointer to module TLV to return
1133 * @module_tlv_len: pointer to module TLV length to return
1134 * @module_type: module type requested
1136 * Finds the requested sub module TLV type from the Preserved Field
1137 * Area (PFA) and returns the TLV pointer and length. The caller can
1138 * use these to read the variable length TLV value.
1141 ice_get_pfa_module_tlv(struct ice_hw *hw, u16 *module_tlv, u16 *module_tlv_len,
1144 enum ice_status status;
1145 u16 pfa_len, pfa_ptr;
1148 status = ice_read_sr_word(hw, ICE_SR_PFA_PTR, &pfa_ptr);
1149 if (status != ICE_SUCCESS) {
1150 ice_debug(hw, ICE_DBG_INIT, "Preserved Field Array pointer.\n");
1153 status = ice_read_sr_word(hw, pfa_ptr, &pfa_len);
1154 if (status != ICE_SUCCESS) {
1155 ice_debug(hw, ICE_DBG_INIT, "Failed to read PFA length.\n");
1158 /* Starting with first TLV after PFA length, iterate through the list
1159 * of TLVs to find the requested one.
1161 next_tlv = pfa_ptr + 1;
1162 while (next_tlv < pfa_ptr + pfa_len) {
1163 u16 tlv_sub_module_type;
1167 status = ice_read_sr_word(hw, next_tlv, &tlv_sub_module_type);
1168 if (status != ICE_SUCCESS) {
1169 ice_debug(hw, ICE_DBG_INIT, "Failed to read TLV type.\n");
1172 /* Read TLV length */
1173 status = ice_read_sr_word(hw, next_tlv + 1, &tlv_len);
1174 if (status != ICE_SUCCESS) {
1175 ice_debug(hw, ICE_DBG_INIT, "Failed to read TLV length.\n");
1178 if (tlv_sub_module_type == module_type) {
1180 *module_tlv = next_tlv;
1181 *module_tlv_len = tlv_len;
1184 return ICE_ERR_INVAL_SIZE;
1186 /* Check next TLV, i.e. current TLV pointer + length + 2 words
1187 * (for current TLV's type and length)
1189 next_tlv = next_tlv + tlv_len + 2;
1191 /* Module does not exist */
1192 return ICE_ERR_DOES_NOT_EXIST;
1198 * ice_copy_rxq_ctx_to_hw
1199 * @hw: pointer to the hardware structure
1200 * @ice_rxq_ctx: pointer to the rxq context
1201 * @rxq_index: the index of the Rx queue
1203 * Copies rxq context from dense structure to HW register space
1205 static enum ice_status
1206 ice_copy_rxq_ctx_to_hw(struct ice_hw *hw, u8 *ice_rxq_ctx, u32 rxq_index)
1211 return ICE_ERR_BAD_PTR;
1213 if (rxq_index > QRX_CTRL_MAX_INDEX)
1214 return ICE_ERR_PARAM;
1216 /* Copy each dword separately to HW */
1217 for (i = 0; i < ICE_RXQ_CTX_SIZE_DWORDS; i++) {
1218 wr32(hw, QRX_CONTEXT(i, rxq_index),
1219 *((u32 *)(ice_rxq_ctx + (i * sizeof(u32)))));
1221 ice_debug(hw, ICE_DBG_QCTX, "qrxdata[%d]: %08X\n", i,
1222 *((u32 *)(ice_rxq_ctx + (i * sizeof(u32)))));
1228 /* LAN Rx Queue Context */
1229 static const struct ice_ctx_ele ice_rlan_ctx_info[] = {
1230 /* Field Width LSB */
1231 ICE_CTX_STORE(ice_rlan_ctx, head, 13, 0),
1232 ICE_CTX_STORE(ice_rlan_ctx, cpuid, 8, 13),
1233 ICE_CTX_STORE(ice_rlan_ctx, base, 57, 32),
1234 ICE_CTX_STORE(ice_rlan_ctx, qlen, 13, 89),
1235 ICE_CTX_STORE(ice_rlan_ctx, dbuf, 7, 102),
1236 ICE_CTX_STORE(ice_rlan_ctx, hbuf, 5, 109),
1237 ICE_CTX_STORE(ice_rlan_ctx, dtype, 2, 114),
1238 ICE_CTX_STORE(ice_rlan_ctx, dsize, 1, 116),
1239 ICE_CTX_STORE(ice_rlan_ctx, crcstrip, 1, 117),
1240 ICE_CTX_STORE(ice_rlan_ctx, l2tsel, 1, 119),
1241 ICE_CTX_STORE(ice_rlan_ctx, hsplit_0, 4, 120),
1242 ICE_CTX_STORE(ice_rlan_ctx, hsplit_1, 2, 124),
1243 ICE_CTX_STORE(ice_rlan_ctx, showiv, 1, 127),
1244 ICE_CTX_STORE(ice_rlan_ctx, rxmax, 14, 174),
1245 ICE_CTX_STORE(ice_rlan_ctx, tphrdesc_ena, 1, 193),
1246 ICE_CTX_STORE(ice_rlan_ctx, tphwdesc_ena, 1, 194),
1247 ICE_CTX_STORE(ice_rlan_ctx, tphdata_ena, 1, 195),
1248 ICE_CTX_STORE(ice_rlan_ctx, tphhead_ena, 1, 196),
1249 ICE_CTX_STORE(ice_rlan_ctx, lrxqthresh, 3, 198),
1250 ICE_CTX_STORE(ice_rlan_ctx, prefena, 1, 201),
1256 * @hw: pointer to the hardware structure
1257 * @rlan_ctx: pointer to the rxq context
1258 * @rxq_index: the index of the Rx queue
1260 * Converts rxq context from sparse to dense structure and then writes
1261 * it to HW register space and enables the hardware to prefetch descriptors
1262 * instead of only fetching them on demand
1265 ice_write_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx,
1268 u8 ctx_buf[ICE_RXQ_CTX_SZ] = { 0 };
1271 return ICE_ERR_BAD_PTR;
1273 rlan_ctx->prefena = 1;
1275 ice_set_ctx((u8 *)rlan_ctx, ctx_buf, ice_rlan_ctx_info);
1276 return ice_copy_rxq_ctx_to_hw(hw, ctx_buf, rxq_index);
1279 #if !defined(NO_UNUSED_CTX_CODE) || defined(AE_DRIVER)
1282 * @hw: pointer to the hardware structure
1283 * @rxq_index: the index of the Rx queue to clear
1285 * Clears rxq context in HW register space
1287 enum ice_status ice_clear_rxq_ctx(struct ice_hw *hw, u32 rxq_index)
1291 if (rxq_index > QRX_CTRL_MAX_INDEX)
1292 return ICE_ERR_PARAM;
1294 /* Clear each dword register separately */
1295 for (i = 0; i < ICE_RXQ_CTX_SIZE_DWORDS; i++)
1296 wr32(hw, QRX_CONTEXT(i, rxq_index), 0);
1300 #endif /* !NO_UNUSED_CTX_CODE || AE_DRIVER */
1302 /* LAN Tx Queue Context */
1303 const struct ice_ctx_ele ice_tlan_ctx_info[] = {
1304 /* Field Width LSB */
1305 ICE_CTX_STORE(ice_tlan_ctx, base, 57, 0),
1306 ICE_CTX_STORE(ice_tlan_ctx, port_num, 3, 57),
1307 ICE_CTX_STORE(ice_tlan_ctx, cgd_num, 5, 60),
1308 ICE_CTX_STORE(ice_tlan_ctx, pf_num, 3, 65),
1309 ICE_CTX_STORE(ice_tlan_ctx, vmvf_num, 10, 68),
1310 ICE_CTX_STORE(ice_tlan_ctx, vmvf_type, 2, 78),
1311 ICE_CTX_STORE(ice_tlan_ctx, src_vsi, 10, 80),
1312 ICE_CTX_STORE(ice_tlan_ctx, tsyn_ena, 1, 90),
1313 ICE_CTX_STORE(ice_tlan_ctx, internal_usage_flag, 1, 91),
1314 ICE_CTX_STORE(ice_tlan_ctx, alt_vlan, 1, 92),
1315 ICE_CTX_STORE(ice_tlan_ctx, cpuid, 8, 93),
1316 ICE_CTX_STORE(ice_tlan_ctx, wb_mode, 1, 101),
1317 ICE_CTX_STORE(ice_tlan_ctx, tphrd_desc, 1, 102),
1318 ICE_CTX_STORE(ice_tlan_ctx, tphrd, 1, 103),
1319 ICE_CTX_STORE(ice_tlan_ctx, tphwr_desc, 1, 104),
1320 ICE_CTX_STORE(ice_tlan_ctx, cmpq_id, 9, 105),
1321 ICE_CTX_STORE(ice_tlan_ctx, qnum_in_func, 14, 114),
1322 ICE_CTX_STORE(ice_tlan_ctx, itr_notification_mode, 1, 128),
1323 ICE_CTX_STORE(ice_tlan_ctx, adjust_prof_id, 6, 129),
1324 ICE_CTX_STORE(ice_tlan_ctx, qlen, 13, 135),
1325 ICE_CTX_STORE(ice_tlan_ctx, quanta_prof_idx, 4, 148),
1326 ICE_CTX_STORE(ice_tlan_ctx, tso_ena, 1, 152),
1327 ICE_CTX_STORE(ice_tlan_ctx, tso_qnum, 11, 153),
1328 ICE_CTX_STORE(ice_tlan_ctx, legacy_int, 1, 164),
1329 ICE_CTX_STORE(ice_tlan_ctx, drop_ena, 1, 165),
1330 ICE_CTX_STORE(ice_tlan_ctx, cache_prof_idx, 2, 166),
1331 ICE_CTX_STORE(ice_tlan_ctx, pkt_shaper_prof_idx, 3, 168),
1332 ICE_CTX_STORE(ice_tlan_ctx, int_q_state, 122, 171),
1336 #if !defined(NO_UNUSED_CTX_CODE) || defined(AE_DRIVER)
1338 * ice_copy_tx_cmpltnq_ctx_to_hw
1339 * @hw: pointer to the hardware structure
1340 * @ice_tx_cmpltnq_ctx: pointer to the Tx completion queue context
1341 * @tx_cmpltnq_index: the index of the completion queue
1343 * Copies Tx completion queue context from dense structure to HW register space
1345 static enum ice_status
1346 ice_copy_tx_cmpltnq_ctx_to_hw(struct ice_hw *hw, u8 *ice_tx_cmpltnq_ctx,
1347 u32 tx_cmpltnq_index)
1351 if (!ice_tx_cmpltnq_ctx)
1352 return ICE_ERR_BAD_PTR;
1354 if (tx_cmpltnq_index > GLTCLAN_CQ_CNTX0_MAX_INDEX)
1355 return ICE_ERR_PARAM;
1357 /* Copy each dword separately to HW */
1358 for (i = 0; i < ICE_TX_CMPLTNQ_CTX_SIZE_DWORDS; i++) {
1359 wr32(hw, GLTCLAN_CQ_CNTX(i, tx_cmpltnq_index),
1360 *((u32 *)(ice_tx_cmpltnq_ctx + (i * sizeof(u32)))));
1362 ice_debug(hw, ICE_DBG_QCTX, "cmpltnqdata[%d]: %08X\n", i,
1363 *((u32 *)(ice_tx_cmpltnq_ctx + (i * sizeof(u32)))));
1369 /* LAN Tx Completion Queue Context */
1370 static const struct ice_ctx_ele ice_tx_cmpltnq_ctx_info[] = {
1371 /* Field Width LSB */
1372 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, base, 57, 0),
1373 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, q_len, 18, 64),
1374 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, generation, 1, 96),
1375 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, wrt_ptr, 22, 97),
1376 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, pf_num, 3, 128),
1377 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, vmvf_num, 10, 131),
1378 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, vmvf_type, 2, 141),
1379 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, tph_desc_wr, 1, 160),
1380 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, cpuid, 8, 161),
1381 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, cmpltn_cache, 512, 192),
1386 * ice_write_tx_cmpltnq_ctx
1387 * @hw: pointer to the hardware structure
1388 * @tx_cmpltnq_ctx: pointer to the completion queue context
1389 * @tx_cmpltnq_index: the index of the completion queue
1391 * Converts completion queue context from sparse to dense structure and then
1392 * writes it to HW register space
1395 ice_write_tx_cmpltnq_ctx(struct ice_hw *hw,
1396 struct ice_tx_cmpltnq_ctx *tx_cmpltnq_ctx,
1397 u32 tx_cmpltnq_index)
1399 u8 ctx_buf[ICE_TX_CMPLTNQ_CTX_SIZE_DWORDS * sizeof(u32)] = { 0 };
1401 ice_set_ctx((u8 *)tx_cmpltnq_ctx, ctx_buf, ice_tx_cmpltnq_ctx_info);
1402 return ice_copy_tx_cmpltnq_ctx_to_hw(hw, ctx_buf, tx_cmpltnq_index);
1406 * ice_clear_tx_cmpltnq_ctx
1407 * @hw: pointer to the hardware structure
1408 * @tx_cmpltnq_index: the index of the completion queue to clear
1410 * Clears Tx completion queue context in HW register space
1413 ice_clear_tx_cmpltnq_ctx(struct ice_hw *hw, u32 tx_cmpltnq_index)
1417 if (tx_cmpltnq_index > GLTCLAN_CQ_CNTX0_MAX_INDEX)
1418 return ICE_ERR_PARAM;
1420 /* Clear each dword register separately */
1421 for (i = 0; i < ICE_TX_CMPLTNQ_CTX_SIZE_DWORDS; i++)
1422 wr32(hw, GLTCLAN_CQ_CNTX(i, tx_cmpltnq_index), 0);
1428 * ice_copy_tx_drbell_q_ctx_to_hw
1429 * @hw: pointer to the hardware structure
1430 * @ice_tx_drbell_q_ctx: pointer to the doorbell queue context
1431 * @tx_drbell_q_index: the index of the doorbell queue
1433 * Copies doorbell queue context from dense structure to HW register space
1435 static enum ice_status
1436 ice_copy_tx_drbell_q_ctx_to_hw(struct ice_hw *hw, u8 *ice_tx_drbell_q_ctx,
1437 u32 tx_drbell_q_index)
1441 if (!ice_tx_drbell_q_ctx)
1442 return ICE_ERR_BAD_PTR;
1444 if (tx_drbell_q_index > QTX_COMM_DBLQ_DBELL_MAX_INDEX)
1445 return ICE_ERR_PARAM;
1447 /* Copy each dword separately to HW */
1448 for (i = 0; i < ICE_TX_DRBELL_Q_CTX_SIZE_DWORDS; i++) {
1449 wr32(hw, QTX_COMM_DBLQ_CNTX(i, tx_drbell_q_index),
1450 *((u32 *)(ice_tx_drbell_q_ctx + (i * sizeof(u32)))));
1452 ice_debug(hw, ICE_DBG_QCTX, "tx_drbell_qdata[%d]: %08X\n", i,
1453 *((u32 *)(ice_tx_drbell_q_ctx + (i * sizeof(u32)))));
1459 /* LAN Tx Doorbell Queue Context info */
1460 static const struct ice_ctx_ele ice_tx_drbell_q_ctx_info[] = {
1461 /* Field Width LSB */
1462 ICE_CTX_STORE(ice_tx_drbell_q_ctx, base, 57, 0),
1463 ICE_CTX_STORE(ice_tx_drbell_q_ctx, ring_len, 13, 64),
1464 ICE_CTX_STORE(ice_tx_drbell_q_ctx, pf_num, 3, 80),
1465 ICE_CTX_STORE(ice_tx_drbell_q_ctx, vf_num, 8, 84),
1466 ICE_CTX_STORE(ice_tx_drbell_q_ctx, vmvf_type, 2, 94),
1467 ICE_CTX_STORE(ice_tx_drbell_q_ctx, cpuid, 8, 96),
1468 ICE_CTX_STORE(ice_tx_drbell_q_ctx, tph_desc_rd, 1, 104),
1469 ICE_CTX_STORE(ice_tx_drbell_q_ctx, tph_desc_wr, 1, 108),
1470 ICE_CTX_STORE(ice_tx_drbell_q_ctx, db_q_en, 1, 112),
1471 ICE_CTX_STORE(ice_tx_drbell_q_ctx, rd_head, 13, 128),
1472 ICE_CTX_STORE(ice_tx_drbell_q_ctx, rd_tail, 13, 144),
1477 * ice_write_tx_drbell_q_ctx
1478 * @hw: pointer to the hardware structure
1479 * @tx_drbell_q_ctx: pointer to the doorbell queue context
1480 * @tx_drbell_q_index: the index of the doorbell queue
1482 * Converts doorbell queue context from sparse to dense structure and then
1483 * writes it to HW register space
1486 ice_write_tx_drbell_q_ctx(struct ice_hw *hw,
1487 struct ice_tx_drbell_q_ctx *tx_drbell_q_ctx,
1488 u32 tx_drbell_q_index)
1490 u8 ctx_buf[ICE_TX_DRBELL_Q_CTX_SIZE_DWORDS * sizeof(u32)] = { 0 };
1492 ice_set_ctx((u8 *)tx_drbell_q_ctx, ctx_buf, ice_tx_drbell_q_ctx_info);
1493 return ice_copy_tx_drbell_q_ctx_to_hw(hw, ctx_buf, tx_drbell_q_index);
1497 * ice_clear_tx_drbell_q_ctx
1498 * @hw: pointer to the hardware structure
1499 * @tx_drbell_q_index: the index of the doorbell queue to clear
1501 * Clears doorbell queue context in HW register space
1504 ice_clear_tx_drbell_q_ctx(struct ice_hw *hw, u32 tx_drbell_q_index)
1508 if (tx_drbell_q_index > QTX_COMM_DBLQ_DBELL_MAX_INDEX)
1509 return ICE_ERR_PARAM;
1511 /* Clear each dword register separately */
1512 for (i = 0; i < ICE_TX_DRBELL_Q_CTX_SIZE_DWORDS; i++)
1513 wr32(hw, QTX_COMM_DBLQ_CNTX(i, tx_drbell_q_index), 0);
1517 #endif /* !NO_UNUSED_CTX_CODE || AE_DRIVER */
1520 /* FW Admin Queue command wrappers */
1523 * ice_aq_send_cmd - send FW Admin Queue command to FW Admin Queue
1524 * @hw: pointer to the HW struct
1525 * @desc: descriptor describing the command
1526 * @buf: buffer to use for indirect commands (NULL for direct commands)
1527 * @buf_size: size of buffer for indirect commands (0 for direct commands)
1528 * @cd: pointer to command details structure
1530 * Helper function to send FW Admin Queue commands to the FW Admin Queue.
1533 ice_aq_send_cmd(struct ice_hw *hw, struct ice_aq_desc *desc, void *buf,
1534 u16 buf_size, struct ice_sq_cd *cd)
1536 return ice_sq_send_cmd(hw, &hw->adminq, desc, buf, buf_size, cd);
1541 * @hw: pointer to the HW struct
1542 * @cd: pointer to command details structure or NULL
1544 * Get the firmware version (0x0001) from the admin queue commands
1546 enum ice_status ice_aq_get_fw_ver(struct ice_hw *hw, struct ice_sq_cd *cd)
1548 struct ice_aqc_get_ver *resp;
1549 struct ice_aq_desc desc;
1550 enum ice_status status;
1552 resp = &desc.params.get_ver;
1554 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_ver);
1556 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
1559 hw->fw_branch = resp->fw_branch;
1560 hw->fw_maj_ver = resp->fw_major;
1561 hw->fw_min_ver = resp->fw_minor;
1562 hw->fw_patch = resp->fw_patch;
1563 hw->fw_build = LE32_TO_CPU(resp->fw_build);
1564 hw->api_branch = resp->api_branch;
1565 hw->api_maj_ver = resp->api_major;
1566 hw->api_min_ver = resp->api_minor;
1567 hw->api_patch = resp->api_patch;
1574 * ice_aq_send_driver_ver
1575 * @hw: pointer to the HW struct
1576 * @dv: driver's major, minor version
1577 * @cd: pointer to command details structure or NULL
1579 * Send the driver version (0x0002) to the firmware
1582 ice_aq_send_driver_ver(struct ice_hw *hw, struct ice_driver_ver *dv,
1583 struct ice_sq_cd *cd)
1585 struct ice_aqc_driver_ver *cmd;
1586 struct ice_aq_desc desc;
1589 cmd = &desc.params.driver_ver;
1592 return ICE_ERR_PARAM;
1594 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_driver_ver);
1596 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
1597 cmd->major_ver = dv->major_ver;
1598 cmd->minor_ver = dv->minor_ver;
1599 cmd->build_ver = dv->build_ver;
1600 cmd->subbuild_ver = dv->subbuild_ver;
1603 while (len < sizeof(dv->driver_string) &&
1604 IS_ASCII(dv->driver_string[len]) && dv->driver_string[len])
1607 return ice_aq_send_cmd(hw, &desc, dv->driver_string, len, cd);
1612 * @hw: pointer to the HW struct
1613 * @unloading: is the driver unloading itself
1615 * Tell the Firmware that we're shutting down the AdminQ and whether
1616 * or not the driver is unloading as well (0x0003).
1618 enum ice_status ice_aq_q_shutdown(struct ice_hw *hw, bool unloading)
1620 struct ice_aqc_q_shutdown *cmd;
1621 struct ice_aq_desc desc;
1623 cmd = &desc.params.q_shutdown;
1625 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_q_shutdown);
1628 cmd->driver_unloading = ICE_AQC_DRIVER_UNLOADING;
1630 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
1635 * @hw: pointer to the HW struct
1637 * @access: access type
1638 * @sdp_number: resource number
1639 * @timeout: the maximum time in ms that the driver may hold the resource
1640 * @cd: pointer to command details structure or NULL
1642 * Requests common resource using the admin queue commands (0x0008).
1643 * When attempting to acquire the Global Config Lock, the driver can
1644 * learn of three states:
1645 * 1) ICE_SUCCESS - acquired lock, and can perform download package
1646 * 2) ICE_ERR_AQ_ERROR - did not get lock, driver should fail to load
1647 * 3) ICE_ERR_AQ_NO_WORK - did not get lock, but another driver has
1648 * successfully downloaded the package; the driver does
1649 * not have to download the package and can continue
1652 * Note that if the caller is in an acquire lock, perform action, release lock
1653 * phase of operation, it is possible that the FW may detect a timeout and issue
1654 * a CORER. In this case, the driver will receive a CORER interrupt and will
1655 * have to determine its cause. The calling thread that is handling this flow
1656 * will likely get an error propagated back to it indicating the Download
1657 * Package, Update Package or the Release Resource AQ commands timed out.
1659 static enum ice_status
1660 ice_aq_req_res(struct ice_hw *hw, enum ice_aq_res_ids res,
1661 enum ice_aq_res_access_type access, u8 sdp_number, u32 *timeout,
1662 struct ice_sq_cd *cd)
1664 struct ice_aqc_req_res *cmd_resp;
1665 struct ice_aq_desc desc;
1666 enum ice_status status;
1668 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
1670 cmd_resp = &desc.params.res_owner;
1672 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_req_res);
1674 cmd_resp->res_id = CPU_TO_LE16(res);
1675 cmd_resp->access_type = CPU_TO_LE16(access);
1676 cmd_resp->res_number = CPU_TO_LE32(sdp_number);
1677 cmd_resp->timeout = CPU_TO_LE32(*timeout);
1680 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
1682 /* The completion specifies the maximum time in ms that the driver
1683 * may hold the resource in the Timeout field.
1686 /* Global config lock response utilizes an additional status field.
1688 * If the Global config lock resource is held by some other driver, the
1689 * command completes with ICE_AQ_RES_GLBL_IN_PROG in the status field
1690 * and the timeout field indicates the maximum time the current owner
1691 * of the resource has to free it.
1693 if (res == ICE_GLOBAL_CFG_LOCK_RES_ID) {
1694 if (LE16_TO_CPU(cmd_resp->status) == ICE_AQ_RES_GLBL_SUCCESS) {
1695 *timeout = LE32_TO_CPU(cmd_resp->timeout);
1697 } else if (LE16_TO_CPU(cmd_resp->status) ==
1698 ICE_AQ_RES_GLBL_IN_PROG) {
1699 *timeout = LE32_TO_CPU(cmd_resp->timeout);
1700 return ICE_ERR_AQ_ERROR;
1701 } else if (LE16_TO_CPU(cmd_resp->status) ==
1702 ICE_AQ_RES_GLBL_DONE) {
1703 return ICE_ERR_AQ_NO_WORK;
1706 /* invalid FW response, force a timeout immediately */
1708 return ICE_ERR_AQ_ERROR;
1711 /* If the resource is held by some other driver, the command completes
1712 * with a busy return value and the timeout field indicates the maximum
1713 * time the current owner of the resource has to free it.
1715 if (!status || hw->adminq.sq_last_status == ICE_AQ_RC_EBUSY)
1716 *timeout = LE32_TO_CPU(cmd_resp->timeout);
1722 * ice_aq_release_res
1723 * @hw: pointer to the HW struct
1725 * @sdp_number: resource number
1726 * @cd: pointer to command details structure or NULL
1728 * release common resource using the admin queue commands (0x0009)
1730 static enum ice_status
1731 ice_aq_release_res(struct ice_hw *hw, enum ice_aq_res_ids res, u8 sdp_number,
1732 struct ice_sq_cd *cd)
1734 struct ice_aqc_req_res *cmd;
1735 struct ice_aq_desc desc;
1737 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
1739 cmd = &desc.params.res_owner;
1741 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_release_res);
1743 cmd->res_id = CPU_TO_LE16(res);
1744 cmd->res_number = CPU_TO_LE32(sdp_number);
1746 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
1751 * @hw: pointer to the HW structure
1753 * @access: access type (read or write)
1754 * @timeout: timeout in milliseconds
1756 * This function will attempt to acquire the ownership of a resource.
1759 ice_acquire_res(struct ice_hw *hw, enum ice_aq_res_ids res,
1760 enum ice_aq_res_access_type access, u32 timeout)
1762 #define ICE_RES_POLLING_DELAY_MS 10
1763 u32 delay = ICE_RES_POLLING_DELAY_MS;
1764 u32 time_left = timeout;
1765 enum ice_status status;
1767 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
1769 status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL);
1771 /* A return code of ICE_ERR_AQ_NO_WORK means that another driver has
1772 * previously acquired the resource and performed any necessary updates;
1773 * in this case the caller does not obtain the resource and has no
1774 * further work to do.
1776 if (status == ICE_ERR_AQ_NO_WORK)
1777 goto ice_acquire_res_exit;
1780 ice_debug(hw, ICE_DBG_RES,
1781 "resource %d acquire type %d failed.\n", res, access);
1783 /* If necessary, poll until the current lock owner timeouts */
1784 timeout = time_left;
1785 while (status && timeout && time_left) {
1786 ice_msec_delay(delay, true);
1787 timeout = (timeout > delay) ? timeout - delay : 0;
1788 status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL);
1790 if (status == ICE_ERR_AQ_NO_WORK)
1791 /* lock free, but no work to do */
1798 if (status && status != ICE_ERR_AQ_NO_WORK)
1799 ice_debug(hw, ICE_DBG_RES, "resource acquire timed out.\n");
1801 ice_acquire_res_exit:
1802 if (status == ICE_ERR_AQ_NO_WORK) {
1803 if (access == ICE_RES_WRITE)
1804 ice_debug(hw, ICE_DBG_RES,
1805 "resource indicates no work to do.\n");
1807 ice_debug(hw, ICE_DBG_RES,
1808 "Warning: ICE_ERR_AQ_NO_WORK not expected\n");
1815 * @hw: pointer to the HW structure
1818 * This function will release a resource using the proper Admin Command.
1820 void ice_release_res(struct ice_hw *hw, enum ice_aq_res_ids res)
1822 enum ice_status status;
1823 u32 total_delay = 0;
1825 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
1827 status = ice_aq_release_res(hw, res, 0, NULL);
1829 /* there are some rare cases when trying to release the resource
1830 * results in an admin queue timeout, so handle them correctly
1832 while ((status == ICE_ERR_AQ_TIMEOUT) &&
1833 (total_delay < hw->adminq.sq_cmd_timeout)) {
1834 ice_msec_delay(1, true);
1835 status = ice_aq_release_res(hw, res, 0, NULL);
1841 * ice_aq_alloc_free_res - command to allocate/free resources
1842 * @hw: pointer to the HW struct
1843 * @num_entries: number of resource entries in buffer
1844 * @buf: Indirect buffer to hold data parameters and response
1845 * @buf_size: size of buffer for indirect commands
1846 * @opc: pass in the command opcode
1847 * @cd: pointer to command details structure or NULL
1849 * Helper function to allocate/free resources using the admin queue commands
1852 ice_aq_alloc_free_res(struct ice_hw *hw, u16 num_entries,
1853 struct ice_aqc_alloc_free_res_elem *buf, u16 buf_size,
1854 enum ice_adminq_opc opc, struct ice_sq_cd *cd)
1856 struct ice_aqc_alloc_free_res_cmd *cmd;
1857 struct ice_aq_desc desc;
1859 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
1861 cmd = &desc.params.sw_res_ctrl;
1864 return ICE_ERR_PARAM;
1866 if (buf_size < (num_entries * sizeof(buf->elem[0])))
1867 return ICE_ERR_PARAM;
1869 ice_fill_dflt_direct_cmd_desc(&desc, opc);
1871 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
1873 cmd->num_entries = CPU_TO_LE16(num_entries);
1875 return ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);
1879 * ice_alloc_hw_res - allocate resource
1880 * @hw: pointer to the HW struct
1881 * @type: type of resource
1882 * @num: number of resources to allocate
1883 * @btm: allocate from bottom
1884 * @res: pointer to array that will receive the resources
1887 ice_alloc_hw_res(struct ice_hw *hw, u16 type, u16 num, bool btm, u16 *res)
1889 struct ice_aqc_alloc_free_res_elem *buf;
1890 enum ice_status status;
1893 buf_len = sizeof(*buf) + sizeof(buf->elem) * (num - 1);
1894 buf = (struct ice_aqc_alloc_free_res_elem *)
1895 ice_malloc(hw, buf_len);
1897 return ICE_ERR_NO_MEMORY;
1899 /* Prepare buffer to allocate resource. */
1900 buf->num_elems = CPU_TO_LE16(num);
1901 buf->res_type = CPU_TO_LE16(type | ICE_AQC_RES_TYPE_FLAG_DEDICATED |
1902 ICE_AQC_RES_TYPE_FLAG_IGNORE_INDEX);
1904 buf->res_type |= CPU_TO_LE16(ICE_AQC_RES_TYPE_FLAG_SCAN_BOTTOM);
1906 status = ice_aq_alloc_free_res(hw, 1, buf, buf_len,
1907 ice_aqc_opc_alloc_res, NULL);
1909 goto ice_alloc_res_exit;
1911 ice_memcpy(res, buf->elem, sizeof(buf->elem) * num,
1912 ICE_NONDMA_TO_NONDMA);
1920 * ice_free_hw_res - free allocated HW resource
1921 * @hw: pointer to the HW struct
1922 * @type: type of resource to free
1923 * @num: number of resources
1924 * @res: pointer to array that contains the resources to free
1927 ice_free_hw_res(struct ice_hw *hw, u16 type, u16 num, u16 *res)
1929 struct ice_aqc_alloc_free_res_elem *buf;
1930 enum ice_status status;
1933 buf_len = sizeof(*buf) + sizeof(buf->elem) * (num - 1);
1934 buf = (struct ice_aqc_alloc_free_res_elem *)ice_malloc(hw, buf_len);
1936 return ICE_ERR_NO_MEMORY;
1938 /* Prepare buffer to free resource. */
1939 buf->num_elems = CPU_TO_LE16(num);
1940 buf->res_type = CPU_TO_LE16(type);
1941 ice_memcpy(buf->elem, res, sizeof(buf->elem) * num,
1942 ICE_NONDMA_TO_NONDMA);
1944 status = ice_aq_alloc_free_res(hw, num, buf, buf_len,
1945 ice_aqc_opc_free_res, NULL);
1947 ice_debug(hw, ICE_DBG_SW, "CQ CMD Buffer:\n");
1954 * ice_get_num_per_func - determine number of resources per PF
1955 * @hw: pointer to the HW structure
1956 * @max: value to be evenly split between each PF
1958 * Determine the number of valid functions by going through the bitmap returned
1959 * from parsing capabilities and use this to calculate the number of resources
1960 * per PF based on the max value passed in.
1962 static u32 ice_get_num_per_func(struct ice_hw *hw, u32 max)
1966 #define ICE_CAPS_VALID_FUNCS_M 0xFF
1967 funcs = ice_hweight8(hw->dev_caps.common_cap.valid_functions &
1968 ICE_CAPS_VALID_FUNCS_M);
1977 * ice_parse_caps - parse function/device capabilities
1978 * @hw: pointer to the HW struct
1979 * @buf: pointer to a buffer containing function/device capability records
1980 * @cap_count: number of capability records in the list
1981 * @opc: type of capabilities list to parse
1983 * Helper function to parse function(0x000a)/device(0x000b) capabilities list.
1986 ice_parse_caps(struct ice_hw *hw, void *buf, u32 cap_count,
1987 enum ice_adminq_opc opc)
1989 struct ice_aqc_list_caps_elem *cap_resp;
1990 struct ice_hw_func_caps *func_p = NULL;
1991 struct ice_hw_dev_caps *dev_p = NULL;
1992 struct ice_hw_common_caps *caps;
1999 cap_resp = (struct ice_aqc_list_caps_elem *)buf;
2001 if (opc == ice_aqc_opc_list_dev_caps) {
2002 dev_p = &hw->dev_caps;
2003 caps = &dev_p->common_cap;
2005 } else if (opc == ice_aqc_opc_list_func_caps) {
2006 func_p = &hw->func_caps;
2007 caps = &func_p->common_cap;
2008 prefix = "func cap";
2010 ice_debug(hw, ICE_DBG_INIT, "wrong opcode\n");
2014 for (i = 0; caps && i < cap_count; i++, cap_resp++) {
2015 u32 logical_id = LE32_TO_CPU(cap_resp->logical_id);
2016 u32 phys_id = LE32_TO_CPU(cap_resp->phys_id);
2017 u32 number = LE32_TO_CPU(cap_resp->number);
2018 u16 cap = LE16_TO_CPU(cap_resp->cap);
2021 case ICE_AQC_CAPS_VALID_FUNCTIONS:
2022 caps->valid_functions = number;
2023 ice_debug(hw, ICE_DBG_INIT,
2024 "%s: valid_functions (bitmap) = %d\n", prefix,
2025 caps->valid_functions);
2027 /* store func count for resource management purposes */
2029 dev_p->num_funcs = ice_hweight32(number);
2031 case ICE_AQC_CAPS_VSI:
2033 dev_p->num_vsi_allocd_to_host = number;
2034 ice_debug(hw, ICE_DBG_INIT,
2035 "%s: num_vsi_allocd_to_host = %d\n",
2037 dev_p->num_vsi_allocd_to_host);
2038 } else if (func_p) {
2039 func_p->guar_num_vsi =
2040 ice_get_num_per_func(hw, ICE_MAX_VSI);
2041 ice_debug(hw, ICE_DBG_INIT,
2042 "%s: guar_num_vsi (fw) = %d\n",
2044 ice_debug(hw, ICE_DBG_INIT,
2045 "%s: guar_num_vsi = %d\n",
2046 prefix, func_p->guar_num_vsi);
2049 case ICE_AQC_CAPS_DCB:
2050 caps->dcb = (number == 1);
2051 caps->active_tc_bitmap = logical_id;
2052 caps->maxtc = phys_id;
2053 ice_debug(hw, ICE_DBG_INIT,
2054 "%s: dcb = %d\n", prefix, caps->dcb);
2055 ice_debug(hw, ICE_DBG_INIT,
2056 "%s: active_tc_bitmap = %d\n", prefix,
2057 caps->active_tc_bitmap);
2058 ice_debug(hw, ICE_DBG_INIT,
2059 "%s: maxtc = %d\n", prefix, caps->maxtc);
2061 case ICE_AQC_CAPS_RSS:
2062 caps->rss_table_size = number;
2063 caps->rss_table_entry_width = logical_id;
2064 ice_debug(hw, ICE_DBG_INIT,
2065 "%s: rss_table_size = %d\n", prefix,
2066 caps->rss_table_size);
2067 ice_debug(hw, ICE_DBG_INIT,
2068 "%s: rss_table_entry_width = %d\n", prefix,
2069 caps->rss_table_entry_width);
2071 case ICE_AQC_CAPS_RXQS:
2072 caps->num_rxq = number;
2073 caps->rxq_first_id = phys_id;
2074 ice_debug(hw, ICE_DBG_INIT,
2075 "%s: num_rxq = %d\n", prefix,
2077 ice_debug(hw, ICE_DBG_INIT,
2078 "%s: rxq_first_id = %d\n", prefix,
2079 caps->rxq_first_id);
2081 case ICE_AQC_CAPS_TXQS:
2082 caps->num_txq = number;
2083 caps->txq_first_id = phys_id;
2084 ice_debug(hw, ICE_DBG_INIT,
2085 "%s: num_txq = %d\n", prefix,
2087 ice_debug(hw, ICE_DBG_INIT,
2088 "%s: txq_first_id = %d\n", prefix,
2089 caps->txq_first_id);
2091 case ICE_AQC_CAPS_MSIX:
2092 caps->num_msix_vectors = number;
2093 caps->msix_vector_first_id = phys_id;
2094 ice_debug(hw, ICE_DBG_INIT,
2095 "%s: num_msix_vectors = %d\n", prefix,
2096 caps->num_msix_vectors);
2097 ice_debug(hw, ICE_DBG_INIT,
2098 "%s: msix_vector_first_id = %d\n", prefix,
2099 caps->msix_vector_first_id);
2101 case ICE_AQC_CAPS_FD:
2106 dev_p->num_flow_director_fltr = number;
2107 ice_debug(hw, ICE_DBG_INIT,
2108 "%s: num_flow_director_fltr = %d\n",
2110 dev_p->num_flow_director_fltr);
2113 reg_val = rd32(hw, GLQF_FD_SIZE);
2114 val = (reg_val & GLQF_FD_SIZE_FD_GSIZE_M) >>
2115 GLQF_FD_SIZE_FD_GSIZE_S;
2116 func_p->fd_fltr_guar =
2117 ice_get_num_per_func(hw, val);
2118 val = (reg_val & GLQF_FD_SIZE_FD_BSIZE_M) >>
2119 GLQF_FD_SIZE_FD_BSIZE_S;
2120 func_p->fd_fltr_best_effort = val;
2121 ice_debug(hw, ICE_DBG_INIT,
2122 "%s: fd_fltr_guar = %d\n",
2123 prefix, func_p->fd_fltr_guar);
2124 ice_debug(hw, ICE_DBG_INIT,
2125 "%s: fd_fltr_best_effort = %d\n",
2126 prefix, func_p->fd_fltr_best_effort);
2130 case ICE_AQC_CAPS_MAX_MTU:
2131 caps->max_mtu = number;
2132 ice_debug(hw, ICE_DBG_INIT, "%s: max_mtu = %d\n",
2133 prefix, caps->max_mtu);
2136 ice_debug(hw, ICE_DBG_INIT,
2137 "%s: unknown capability[%d]: 0x%x\n", prefix,
2143 /* Re-calculate capabilities that are dependent on the number of
2144 * physical ports; i.e. some features are not supported or function
2145 * differently on devices with more than 4 ports.
2147 if (hw->dev_caps.num_funcs > 4) {
2148 /* Max 4 TCs per port */
2150 ice_debug(hw, ICE_DBG_INIT,
2151 "%s: maxtc = %d (based on #ports)\n", prefix,
2157 * ice_aq_discover_caps - query function/device capabilities
2158 * @hw: pointer to the HW struct
2159 * @buf: a virtual buffer to hold the capabilities
2160 * @buf_size: Size of the virtual buffer
2161 * @cap_count: cap count needed if AQ err==ENOMEM
2162 * @opc: capabilities type to discover - pass in the command opcode
2163 * @cd: pointer to command details structure or NULL
2165 * Get the function(0x000a)/device(0x000b) capabilities description from
2168 static enum ice_status
2169 ice_aq_discover_caps(struct ice_hw *hw, void *buf, u16 buf_size, u32 *cap_count,
2170 enum ice_adminq_opc opc, struct ice_sq_cd *cd)
2172 struct ice_aqc_list_caps *cmd;
2173 struct ice_aq_desc desc;
2174 enum ice_status status;
2176 cmd = &desc.params.get_cap;
2178 if (opc != ice_aqc_opc_list_func_caps &&
2179 opc != ice_aqc_opc_list_dev_caps)
2180 return ICE_ERR_PARAM;
2182 ice_fill_dflt_direct_cmd_desc(&desc, opc);
2184 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);
2186 ice_parse_caps(hw, buf, LE32_TO_CPU(cmd->count), opc);
2187 else if (hw->adminq.sq_last_status == ICE_AQ_RC_ENOMEM)
2188 *cap_count = LE32_TO_CPU(cmd->count);
2193 * ice_discover_caps - get info about the HW
2194 * @hw: pointer to the hardware structure
2195 * @opc: capabilities type to discover - pass in the command opcode
2197 static enum ice_status
2198 ice_discover_caps(struct ice_hw *hw, enum ice_adminq_opc opc)
2200 enum ice_status status;
2205 /* The driver doesn't know how many capabilities the device will return
2206 * so the buffer size required isn't known ahead of time. The driver
2207 * starts with cbuf_len and if this turns out to be insufficient, the
2208 * device returns ICE_AQ_RC_ENOMEM and also the cap_count it needs.
2209 * The driver then allocates the buffer based on the count and retries
2210 * the operation. So it follows that the retry count is 2.
2212 #define ICE_GET_CAP_BUF_COUNT 40
2213 #define ICE_GET_CAP_RETRY_COUNT 2
2215 cap_count = ICE_GET_CAP_BUF_COUNT;
2216 retries = ICE_GET_CAP_RETRY_COUNT;
2221 cbuf_len = (u16)(cap_count *
2222 sizeof(struct ice_aqc_list_caps_elem));
2223 cbuf = ice_malloc(hw, cbuf_len);
2225 return ICE_ERR_NO_MEMORY;
2227 status = ice_aq_discover_caps(hw, cbuf, cbuf_len, &cap_count,
2231 if (!status || hw->adminq.sq_last_status != ICE_AQ_RC_ENOMEM)
2234 /* If ENOMEM is returned, try again with bigger buffer */
2235 } while (--retries);
2241 * ice_set_safe_mode_caps - Override dev/func capabilities when in safe mode
2242 * @hw: pointer to the hardware structure
2244 void ice_set_safe_mode_caps(struct ice_hw *hw)
2246 struct ice_hw_func_caps *func_caps = &hw->func_caps;
2247 struct ice_hw_dev_caps *dev_caps = &hw->dev_caps;
2248 u32 valid_func, rxq_first_id, txq_first_id;
2249 u32 msix_vector_first_id, max_mtu;
2252 /* cache some func_caps values that should be restored after memset */
2253 valid_func = func_caps->common_cap.valid_functions;
2254 txq_first_id = func_caps->common_cap.txq_first_id;
2255 rxq_first_id = func_caps->common_cap.rxq_first_id;
2256 msix_vector_first_id = func_caps->common_cap.msix_vector_first_id;
2257 max_mtu = func_caps->common_cap.max_mtu;
2259 /* unset func capabilities */
2260 memset(func_caps, 0, sizeof(*func_caps));
2262 /* restore cached values */
2263 func_caps->common_cap.valid_functions = valid_func;
2264 func_caps->common_cap.txq_first_id = txq_first_id;
2265 func_caps->common_cap.rxq_first_id = rxq_first_id;
2266 func_caps->common_cap.msix_vector_first_id = msix_vector_first_id;
2267 func_caps->common_cap.max_mtu = max_mtu;
2269 /* one Tx and one Rx queue in safe mode */
2270 func_caps->common_cap.num_rxq = 1;
2271 func_caps->common_cap.num_txq = 1;
2273 /* two MSIX vectors, one for traffic and one for misc causes */
2274 func_caps->common_cap.num_msix_vectors = 2;
2275 func_caps->guar_num_vsi = 1;
2277 /* cache some dev_caps values that should be restored after memset */
2278 valid_func = dev_caps->common_cap.valid_functions;
2279 txq_first_id = dev_caps->common_cap.txq_first_id;
2280 rxq_first_id = dev_caps->common_cap.rxq_first_id;
2281 msix_vector_first_id = dev_caps->common_cap.msix_vector_first_id;
2282 max_mtu = dev_caps->common_cap.max_mtu;
2283 num_funcs = dev_caps->num_funcs;
2285 /* unset dev capabilities */
2286 memset(dev_caps, 0, sizeof(*dev_caps));
2288 /* restore cached values */
2289 dev_caps->common_cap.valid_functions = valid_func;
2290 dev_caps->common_cap.txq_first_id = txq_first_id;
2291 dev_caps->common_cap.rxq_first_id = rxq_first_id;
2292 dev_caps->common_cap.msix_vector_first_id = msix_vector_first_id;
2293 dev_caps->common_cap.max_mtu = max_mtu;
2294 dev_caps->num_funcs = num_funcs;
2296 /* one Tx and one Rx queue per function in safe mode */
2297 dev_caps->common_cap.num_rxq = num_funcs;
2298 dev_caps->common_cap.num_txq = num_funcs;
2300 /* two MSIX vectors per function */
2301 dev_caps->common_cap.num_msix_vectors = 2 * num_funcs;
2305 * ice_get_caps - get info about the HW
2306 * @hw: pointer to the hardware structure
2308 enum ice_status ice_get_caps(struct ice_hw *hw)
2310 enum ice_status status;
2312 status = ice_discover_caps(hw, ice_aqc_opc_list_dev_caps);
2314 status = ice_discover_caps(hw, ice_aqc_opc_list_func_caps);
2320 * ice_aq_manage_mac_write - manage MAC address write command
2321 * @hw: pointer to the HW struct
2322 * @mac_addr: MAC address to be written as LAA/LAA+WoL/Port address
2323 * @flags: flags to control write behavior
2324 * @cd: pointer to command details structure or NULL
2326 * This function is used to write MAC address to the NVM (0x0108).
2329 ice_aq_manage_mac_write(struct ice_hw *hw, const u8 *mac_addr, u8 flags,
2330 struct ice_sq_cd *cd)
2332 struct ice_aqc_manage_mac_write *cmd;
2333 struct ice_aq_desc desc;
2335 cmd = &desc.params.mac_write;
2336 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_write);
2341 /* Prep values for flags, sah, sal */
2342 cmd->sah = HTONS(*((const u16 *)mac_addr));
2343 cmd->sal = HTONL(*((const u32 *)(mac_addr + 2)));
2345 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
2349 * ice_aq_clear_pxe_mode
2350 * @hw: pointer to the HW struct
2352 * Tell the firmware that the driver is taking over from PXE (0x0110).
2354 static enum ice_status ice_aq_clear_pxe_mode(struct ice_hw *hw)
2356 struct ice_aq_desc desc;
2358 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pxe_mode);
2359 desc.params.clear_pxe.rx_cnt = ICE_AQC_CLEAR_PXE_RX_CNT;
2361 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
2365 * ice_clear_pxe_mode - clear pxe operations mode
2366 * @hw: pointer to the HW struct
2368 * Make sure all PXE mode settings are cleared, including things
2369 * like descriptor fetch/write-back mode.
2371 void ice_clear_pxe_mode(struct ice_hw *hw)
2373 if (ice_check_sq_alive(hw, &hw->adminq))
2374 ice_aq_clear_pxe_mode(hw);
2379 * ice_get_link_speed_based_on_phy_type - returns link speed
2380 * @phy_type_low: lower part of phy_type
2381 * @phy_type_high: higher part of phy_type
2383 * This helper function will convert an entry in PHY type structure
2384 * [phy_type_low, phy_type_high] to its corresponding link speed.
2385 * Note: In the structure of [phy_type_low, phy_type_high], there should
2386 * be one bit set, as this function will convert one PHY type to its
2388 * If no bit gets set, ICE_LINK_SPEED_UNKNOWN will be returned
2389 * If more than one bit gets set, ICE_LINK_SPEED_UNKNOWN will be returned
2392 ice_get_link_speed_based_on_phy_type(u64 phy_type_low, u64 phy_type_high)
2394 u16 speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN;
2395 u16 speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN;
2397 switch (phy_type_low) {
2398 case ICE_PHY_TYPE_LOW_100BASE_TX:
2399 case ICE_PHY_TYPE_LOW_100M_SGMII:
2400 speed_phy_type_low = ICE_AQ_LINK_SPEED_100MB;
2402 case ICE_PHY_TYPE_LOW_1000BASE_T:
2403 case ICE_PHY_TYPE_LOW_1000BASE_SX:
2404 case ICE_PHY_TYPE_LOW_1000BASE_LX:
2405 case ICE_PHY_TYPE_LOW_1000BASE_KX:
2406 case ICE_PHY_TYPE_LOW_1G_SGMII:
2407 speed_phy_type_low = ICE_AQ_LINK_SPEED_1000MB;
2409 case ICE_PHY_TYPE_LOW_2500BASE_T:
2410 case ICE_PHY_TYPE_LOW_2500BASE_X:
2411 case ICE_PHY_TYPE_LOW_2500BASE_KX:
2412 speed_phy_type_low = ICE_AQ_LINK_SPEED_2500MB;
2414 case ICE_PHY_TYPE_LOW_5GBASE_T:
2415 case ICE_PHY_TYPE_LOW_5GBASE_KR:
2416 speed_phy_type_low = ICE_AQ_LINK_SPEED_5GB;
2418 case ICE_PHY_TYPE_LOW_10GBASE_T:
2419 case ICE_PHY_TYPE_LOW_10G_SFI_DA:
2420 case ICE_PHY_TYPE_LOW_10GBASE_SR:
2421 case ICE_PHY_TYPE_LOW_10GBASE_LR:
2422 case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1:
2423 case ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC:
2424 case ICE_PHY_TYPE_LOW_10G_SFI_C2C:
2425 speed_phy_type_low = ICE_AQ_LINK_SPEED_10GB;
2427 case ICE_PHY_TYPE_LOW_25GBASE_T:
2428 case ICE_PHY_TYPE_LOW_25GBASE_CR:
2429 case ICE_PHY_TYPE_LOW_25GBASE_CR_S:
2430 case ICE_PHY_TYPE_LOW_25GBASE_CR1:
2431 case ICE_PHY_TYPE_LOW_25GBASE_SR:
2432 case ICE_PHY_TYPE_LOW_25GBASE_LR:
2433 case ICE_PHY_TYPE_LOW_25GBASE_KR:
2434 case ICE_PHY_TYPE_LOW_25GBASE_KR_S:
2435 case ICE_PHY_TYPE_LOW_25GBASE_KR1:
2436 case ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC:
2437 case ICE_PHY_TYPE_LOW_25G_AUI_C2C:
2438 speed_phy_type_low = ICE_AQ_LINK_SPEED_25GB;
2440 case ICE_PHY_TYPE_LOW_40GBASE_CR4:
2441 case ICE_PHY_TYPE_LOW_40GBASE_SR4:
2442 case ICE_PHY_TYPE_LOW_40GBASE_LR4:
2443 case ICE_PHY_TYPE_LOW_40GBASE_KR4:
2444 case ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC:
2445 case ICE_PHY_TYPE_LOW_40G_XLAUI:
2446 speed_phy_type_low = ICE_AQ_LINK_SPEED_40GB;
2448 case ICE_PHY_TYPE_LOW_50GBASE_CR2:
2449 case ICE_PHY_TYPE_LOW_50GBASE_SR2:
2450 case ICE_PHY_TYPE_LOW_50GBASE_LR2:
2451 case ICE_PHY_TYPE_LOW_50GBASE_KR2:
2452 case ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC:
2453 case ICE_PHY_TYPE_LOW_50G_LAUI2:
2454 case ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC:
2455 case ICE_PHY_TYPE_LOW_50G_AUI2:
2456 case ICE_PHY_TYPE_LOW_50GBASE_CP:
2457 case ICE_PHY_TYPE_LOW_50GBASE_SR:
2458 case ICE_PHY_TYPE_LOW_50GBASE_FR:
2459 case ICE_PHY_TYPE_LOW_50GBASE_LR:
2460 case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4:
2461 case ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC:
2462 case ICE_PHY_TYPE_LOW_50G_AUI1:
2463 speed_phy_type_low = ICE_AQ_LINK_SPEED_50GB;
2465 case ICE_PHY_TYPE_LOW_100GBASE_CR4:
2466 case ICE_PHY_TYPE_LOW_100GBASE_SR4:
2467 case ICE_PHY_TYPE_LOW_100GBASE_LR4:
2468 case ICE_PHY_TYPE_LOW_100GBASE_KR4:
2469 case ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC:
2470 case ICE_PHY_TYPE_LOW_100G_CAUI4:
2471 case ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC:
2472 case ICE_PHY_TYPE_LOW_100G_AUI4:
2473 case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4:
2474 case ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4:
2475 case ICE_PHY_TYPE_LOW_100GBASE_CP2:
2476 case ICE_PHY_TYPE_LOW_100GBASE_SR2:
2477 case ICE_PHY_TYPE_LOW_100GBASE_DR:
2478 speed_phy_type_low = ICE_AQ_LINK_SPEED_100GB;
2481 speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN;
2485 switch (phy_type_high) {
2486 case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4:
2487 case ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC:
2488 case ICE_PHY_TYPE_HIGH_100G_CAUI2:
2489 case ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC:
2490 case ICE_PHY_TYPE_HIGH_100G_AUI2:
2491 speed_phy_type_high = ICE_AQ_LINK_SPEED_100GB;
2494 speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN;
2498 if (speed_phy_type_low == ICE_AQ_LINK_SPEED_UNKNOWN &&
2499 speed_phy_type_high == ICE_AQ_LINK_SPEED_UNKNOWN)
2500 return ICE_AQ_LINK_SPEED_UNKNOWN;
2501 else if (speed_phy_type_low != ICE_AQ_LINK_SPEED_UNKNOWN &&
2502 speed_phy_type_high != ICE_AQ_LINK_SPEED_UNKNOWN)
2503 return ICE_AQ_LINK_SPEED_UNKNOWN;
2504 else if (speed_phy_type_low != ICE_AQ_LINK_SPEED_UNKNOWN &&
2505 speed_phy_type_high == ICE_AQ_LINK_SPEED_UNKNOWN)
2506 return speed_phy_type_low;
2508 return speed_phy_type_high;
2512 * ice_update_phy_type
2513 * @phy_type_low: pointer to the lower part of phy_type
2514 * @phy_type_high: pointer to the higher part of phy_type
2515 * @link_speeds_bitmap: targeted link speeds bitmap
2517 * Note: For the link_speeds_bitmap structure, you can check it at
2518 * [ice_aqc_get_link_status->link_speed]. Caller can pass in
2519 * link_speeds_bitmap include multiple speeds.
2521 * Each entry in this [phy_type_low, phy_type_high] structure will
2522 * present a certain link speed. This helper function will turn on bits
2523 * in [phy_type_low, phy_type_high] structure based on the value of
2524 * link_speeds_bitmap input parameter.
2527 ice_update_phy_type(u64 *phy_type_low, u64 *phy_type_high,
2528 u16 link_speeds_bitmap)
2535 /* We first check with low part of phy_type */
2536 for (index = 0; index <= ICE_PHY_TYPE_LOW_MAX_INDEX; index++) {
2537 pt_low = BIT_ULL(index);
2538 speed = ice_get_link_speed_based_on_phy_type(pt_low, 0);
2540 if (link_speeds_bitmap & speed)
2541 *phy_type_low |= BIT_ULL(index);
2544 /* We then check with high part of phy_type */
2545 for (index = 0; index <= ICE_PHY_TYPE_HIGH_MAX_INDEX; index++) {
2546 pt_high = BIT_ULL(index);
2547 speed = ice_get_link_speed_based_on_phy_type(0, pt_high);
2549 if (link_speeds_bitmap & speed)
2550 *phy_type_high |= BIT_ULL(index);
2555 * ice_aq_set_phy_cfg
2556 * @hw: pointer to the HW struct
2557 * @pi: port info structure of the interested logical port
2558 * @cfg: structure with PHY configuration data to be set
2559 * @cd: pointer to command details structure or NULL
2561 * Set the various PHY configuration parameters supported on the Port.
2562 * One or more of the Set PHY config parameters may be ignored in an MFP
2563 * mode as the PF may not have the privilege to set some of the PHY Config
2564 * parameters. This status will be indicated by the command response (0x0601).
2567 ice_aq_set_phy_cfg(struct ice_hw *hw, struct ice_port_info *pi,
2568 struct ice_aqc_set_phy_cfg_data *cfg, struct ice_sq_cd *cd)
2570 struct ice_aq_desc desc;
2571 enum ice_status status;
2574 return ICE_ERR_PARAM;
2576 /* Ensure that only valid bits of cfg->caps can be turned on. */
2577 if (cfg->caps & ~ICE_AQ_PHY_ENA_VALID_MASK) {
2578 ice_debug(hw, ICE_DBG_PHY,
2579 "Invalid bit is set in ice_aqc_set_phy_cfg_data->caps : 0x%x\n",
2582 cfg->caps &= ICE_AQ_PHY_ENA_VALID_MASK;
2585 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_phy_cfg);
2586 desc.params.set_phy.lport_num = pi->lport;
2587 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
2589 ice_debug(hw, ICE_DBG_LINK, "phy_type_low = 0x%llx\n",
2590 (unsigned long long)LE64_TO_CPU(cfg->phy_type_low));
2591 ice_debug(hw, ICE_DBG_LINK, "phy_type_high = 0x%llx\n",
2592 (unsigned long long)LE64_TO_CPU(cfg->phy_type_high));
2593 ice_debug(hw, ICE_DBG_LINK, "caps = 0x%x\n", cfg->caps);
2594 ice_debug(hw, ICE_DBG_LINK, "low_power_ctrl = 0x%x\n",
2595 cfg->low_power_ctrl);
2596 ice_debug(hw, ICE_DBG_LINK, "eee_cap = 0x%x\n", cfg->eee_cap);
2597 ice_debug(hw, ICE_DBG_LINK, "eeer_value = 0x%x\n", cfg->eeer_value);
2598 ice_debug(hw, ICE_DBG_LINK, "link_fec_opt = 0x%x\n", cfg->link_fec_opt);
2600 status = ice_aq_send_cmd(hw, &desc, cfg, sizeof(*cfg), cd);
2603 pi->phy.curr_user_phy_cfg = *cfg;
2609 * ice_update_link_info - update status of the HW network link
2610 * @pi: port info structure of the interested logical port
2612 enum ice_status ice_update_link_info(struct ice_port_info *pi)
2614 struct ice_link_status *li;
2615 enum ice_status status;
2618 return ICE_ERR_PARAM;
2620 li = &pi->phy.link_info;
2622 status = ice_aq_get_link_info(pi, true, NULL, NULL);
2626 if (li->link_info & ICE_AQ_MEDIA_AVAILABLE) {
2627 struct ice_aqc_get_phy_caps_data *pcaps;
2631 pcaps = (struct ice_aqc_get_phy_caps_data *)
2632 ice_malloc(hw, sizeof(*pcaps));
2634 return ICE_ERR_NO_MEMORY;
2636 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_TOPO_CAP,
2638 if (status == ICE_SUCCESS)
2639 ice_memcpy(li->module_type, &pcaps->module_type,
2640 sizeof(li->module_type),
2641 ICE_NONDMA_TO_NONDMA);
2643 ice_free(hw, pcaps);
2650 * ice_cache_phy_user_req
2651 * @pi: port information structure
2652 * @cache_data: PHY logging data
2653 * @cache_mode: PHY logging mode
2655 * Log the user request on (FC, FEC, SPEED) for later user.
2658 ice_cache_phy_user_req(struct ice_port_info *pi,
2659 struct ice_phy_cache_mode_data cache_data,
2660 enum ice_phy_cache_mode cache_mode)
2665 switch (cache_mode) {
2667 pi->phy.curr_user_fc_req = cache_data.data.curr_user_fc_req;
2669 case ICE_SPEED_MODE:
2670 pi->phy.curr_user_speed_req =
2671 cache_data.data.curr_user_speed_req;
2674 pi->phy.curr_user_fec_req = cache_data.data.curr_user_fec_req;
2682 * ice_caps_to_fc_mode
2683 * @caps: PHY capabilities
2685 * Convert PHY FC capabilities to ice FC mode
2687 enum ice_fc_mode ice_caps_to_fc_mode(u8 caps)
2689 if (caps & ICE_AQC_PHY_EN_TX_LINK_PAUSE &&
2690 caps & ICE_AQC_PHY_EN_RX_LINK_PAUSE)
2693 if (caps & ICE_AQC_PHY_EN_TX_LINK_PAUSE)
2694 return ICE_FC_TX_PAUSE;
2696 if (caps & ICE_AQC_PHY_EN_RX_LINK_PAUSE)
2697 return ICE_FC_RX_PAUSE;
2703 * ice_caps_to_fec_mode
2704 * @caps: PHY capabilities
2705 * @fec_options: Link FEC options
2707 * Convert PHY FEC capabilities to ice FEC mode
2709 enum ice_fec_mode ice_caps_to_fec_mode(u8 caps, u8 fec_options)
2711 if (caps & ICE_AQC_PHY_EN_AUTO_FEC)
2712 return ICE_FEC_AUTO;
2714 if (fec_options & (ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN |
2715 ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ |
2716 ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN |
2717 ICE_AQC_PHY_FEC_25G_KR_REQ))
2718 return ICE_FEC_BASER;
2720 if (fec_options & (ICE_AQC_PHY_FEC_25G_RS_528_REQ |
2721 ICE_AQC_PHY_FEC_25G_RS_544_REQ |
2722 ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN))
2725 return ICE_FEC_NONE;
2730 * @pi: port information structure
2731 * @aq_failures: pointer to status code, specific to ice_set_fc routine
2732 * @ena_auto_link_update: enable automatic link update
2734 * Set the requested flow control mode.
2737 ice_set_fc(struct ice_port_info *pi, u8 *aq_failures, bool ena_auto_link_update)
2739 struct ice_aqc_set_phy_cfg_data cfg = { 0 };
2740 struct ice_phy_cache_mode_data cache_data;
2741 struct ice_aqc_get_phy_caps_data *pcaps;
2742 enum ice_status status;
2743 u8 pause_mask = 0x0;
2747 return ICE_ERR_PARAM;
2749 *aq_failures = ICE_SET_FC_AQ_FAIL_NONE;
2751 /* Cache user FC request */
2752 cache_data.data.curr_user_fc_req = pi->fc.req_mode;
2753 ice_cache_phy_user_req(pi, cache_data, ICE_FC_MODE);
2755 switch (pi->fc.req_mode) {
2757 pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE;
2758 pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE;
2760 case ICE_FC_RX_PAUSE:
2761 pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE;
2763 case ICE_FC_TX_PAUSE:
2764 pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE;
2770 pcaps = (struct ice_aqc_get_phy_caps_data *)
2771 ice_malloc(hw, sizeof(*pcaps));
2773 return ICE_ERR_NO_MEMORY;
2775 /* Get the current PHY config */
2776 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_SW_CFG, pcaps,
2779 *aq_failures = ICE_SET_FC_AQ_FAIL_GET;
2783 /* clear the old pause settings */
2784 cfg.caps = pcaps->caps & ~(ICE_AQC_PHY_EN_TX_LINK_PAUSE |
2785 ICE_AQC_PHY_EN_RX_LINK_PAUSE);
2787 /* set the new capabilities */
2788 cfg.caps |= pause_mask;
2790 /* If the capabilities have changed, then set the new config */
2791 if (cfg.caps != pcaps->caps) {
2792 int retry_count, retry_max = 10;
2794 /* Auto restart link so settings take effect */
2795 if (ena_auto_link_update)
2796 cfg.caps |= ICE_AQ_PHY_ENA_AUTO_LINK_UPDT;
2797 /* Copy over all the old settings */
2798 cfg.phy_type_high = pcaps->phy_type_high;
2799 cfg.phy_type_low = pcaps->phy_type_low;
2800 cfg.low_power_ctrl = pcaps->low_power_ctrl;
2801 cfg.eee_cap = pcaps->eee_cap;
2802 cfg.eeer_value = pcaps->eeer_value;
2803 cfg.link_fec_opt = pcaps->link_fec_options;
2805 status = ice_aq_set_phy_cfg(hw, pi, &cfg, NULL);
2807 *aq_failures = ICE_SET_FC_AQ_FAIL_SET;
2811 /* Update the link info
2812 * It sometimes takes a really long time for link to
2813 * come back from the atomic reset. Thus, we wait a
2816 for (retry_count = 0; retry_count < retry_max; retry_count++) {
2817 status = ice_update_link_info(pi);
2819 if (status == ICE_SUCCESS)
2822 ice_msec_delay(100, true);
2826 *aq_failures = ICE_SET_FC_AQ_FAIL_UPDATE;
2830 ice_free(hw, pcaps);
2835 * ice_phy_caps_equals_cfg
2836 * @phy_caps: PHY capabilities
2837 * @phy_cfg: PHY configuration
2839 * Helper function to determine if PHY capabilities matches PHY
2843 ice_phy_caps_equals_cfg(struct ice_aqc_get_phy_caps_data *phy_caps,
2844 struct ice_aqc_set_phy_cfg_data *phy_cfg)
2846 u8 caps_mask, cfg_mask;
2848 if (!phy_caps || !phy_cfg)
2851 /* These bits are not common between capabilities and configuration.
2852 * Do not use them to determine equality.
2854 caps_mask = ICE_AQC_PHY_CAPS_MASK & ~(ICE_AQC_PHY_AN_MODE |
2855 ICE_AQC_PHY_EN_MOD_QUAL);
2856 cfg_mask = ICE_AQ_PHY_ENA_VALID_MASK & ~ICE_AQ_PHY_ENA_AUTO_LINK_UPDT;
2858 if (phy_caps->phy_type_low != phy_cfg->phy_type_low ||
2859 phy_caps->phy_type_high != phy_cfg->phy_type_high ||
2860 ((phy_caps->caps & caps_mask) != (phy_cfg->caps & cfg_mask)) ||
2861 phy_caps->low_power_ctrl != phy_cfg->low_power_ctrl ||
2862 phy_caps->eee_cap != phy_cfg->eee_cap ||
2863 phy_caps->eeer_value != phy_cfg->eeer_value ||
2864 phy_caps->link_fec_options != phy_cfg->link_fec_opt)
2871 * ice_copy_phy_caps_to_cfg - Copy PHY ability data to configuration data
2872 * @caps: PHY ability structure to copy date from
2873 * @cfg: PHY configuration structure to copy data to
2875 * Helper function to copy AQC PHY get ability data to PHY set configuration
2879 ice_copy_phy_caps_to_cfg(struct ice_aqc_get_phy_caps_data *caps,
2880 struct ice_aqc_set_phy_cfg_data *cfg)
2885 cfg->phy_type_low = caps->phy_type_low;
2886 cfg->phy_type_high = caps->phy_type_high;
2887 cfg->caps = caps->caps;
2888 cfg->low_power_ctrl = caps->low_power_ctrl;
2889 cfg->eee_cap = caps->eee_cap;
2890 cfg->eeer_value = caps->eeer_value;
2891 cfg->link_fec_opt = caps->link_fec_options;
2895 * ice_cfg_phy_fec - Configure PHY FEC data based on FEC mode
2896 * @cfg: PHY configuration data to set FEC mode
2897 * @fec: FEC mode to configure
2899 * Caller should copy ice_aqc_get_phy_caps_data.caps ICE_AQC_PHY_EN_AUTO_FEC
2900 * (bit 7) and ice_aqc_get_phy_caps_data.link_fec_options to cfg.caps
2901 * ICE_AQ_PHY_ENA_AUTO_FEC (bit 7) and cfg.link_fec_options before calling.
2904 ice_cfg_phy_fec(struct ice_aqc_set_phy_cfg_data *cfg, enum ice_fec_mode fec)
2908 /* Clear RS bits, and AND BASE-R ability
2909 * bits and OR request bits.
2911 cfg->link_fec_opt &= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN |
2912 ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN;
2913 cfg->link_fec_opt |= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ |
2914 ICE_AQC_PHY_FEC_25G_KR_REQ;
2917 /* Clear BASE-R bits, and AND RS ability
2918 * bits and OR request bits.
2920 cfg->link_fec_opt &= ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN;
2921 cfg->link_fec_opt |= ICE_AQC_PHY_FEC_25G_RS_528_REQ |
2922 ICE_AQC_PHY_FEC_25G_RS_544_REQ;
2925 /* Clear all FEC option bits. */
2926 cfg->link_fec_opt &= ~ICE_AQC_PHY_FEC_MASK;
2929 /* AND auto FEC bit, and all caps bits. */
2930 cfg->caps &= ICE_AQC_PHY_CAPS_MASK;
2936 * ice_get_link_status - get status of the HW network link
2937 * @pi: port information structure
2938 * @link_up: pointer to bool (true/false = linkup/linkdown)
2940 * Variable link_up is true if link is up, false if link is down.
2941 * The variable link_up is invalid if status is non zero. As a
2942 * result of this call, link status reporting becomes enabled
2944 enum ice_status ice_get_link_status(struct ice_port_info *pi, bool *link_up)
2946 struct ice_phy_info *phy_info;
2947 enum ice_status status = ICE_SUCCESS;
2949 if (!pi || !link_up)
2950 return ICE_ERR_PARAM;
2952 phy_info = &pi->phy;
2954 if (phy_info->get_link_info) {
2955 status = ice_update_link_info(pi);
2958 ice_debug(pi->hw, ICE_DBG_LINK,
2959 "get link status error, status = %d\n",
2963 *link_up = phy_info->link_info.link_info & ICE_AQ_LINK_UP;
2969 * ice_aq_set_link_restart_an
2970 * @pi: pointer to the port information structure
2971 * @ena_link: if true: enable link, if false: disable link
2972 * @cd: pointer to command details structure or NULL
2974 * Sets up the link and restarts the Auto-Negotiation over the link.
2977 ice_aq_set_link_restart_an(struct ice_port_info *pi, bool ena_link,
2978 struct ice_sq_cd *cd)
2980 struct ice_aqc_restart_an *cmd;
2981 struct ice_aq_desc desc;
2983 cmd = &desc.params.restart_an;
2985 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_restart_an);
2987 cmd->cmd_flags = ICE_AQC_RESTART_AN_LINK_RESTART;
2988 cmd->lport_num = pi->lport;
2990 cmd->cmd_flags |= ICE_AQC_RESTART_AN_LINK_ENABLE;
2992 cmd->cmd_flags &= ~ICE_AQC_RESTART_AN_LINK_ENABLE;
2994 return ice_aq_send_cmd(pi->hw, &desc, NULL, 0, cd);
2998 * ice_aq_set_event_mask
2999 * @hw: pointer to the HW struct
3000 * @port_num: port number of the physical function
3001 * @mask: event mask to be set
3002 * @cd: pointer to command details structure or NULL
3004 * Set event mask (0x0613)
3007 ice_aq_set_event_mask(struct ice_hw *hw, u8 port_num, u16 mask,
3008 struct ice_sq_cd *cd)
3010 struct ice_aqc_set_event_mask *cmd;
3011 struct ice_aq_desc desc;
3013 cmd = &desc.params.set_event_mask;
3015 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_event_mask);
3017 cmd->lport_num = port_num;
3019 cmd->event_mask = CPU_TO_LE16(mask);
3020 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
3024 * ice_aq_set_mac_loopback
3025 * @hw: pointer to the HW struct
3026 * @ena_lpbk: Enable or Disable loopback
3027 * @cd: pointer to command details structure or NULL
3029 * Enable/disable loopback on a given port
3032 ice_aq_set_mac_loopback(struct ice_hw *hw, bool ena_lpbk, struct ice_sq_cd *cd)
3034 struct ice_aqc_set_mac_lb *cmd;
3035 struct ice_aq_desc desc;
3037 cmd = &desc.params.set_mac_lb;
3039 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_mac_lb);
3041 cmd->lb_mode = ICE_AQ_MAC_LB_EN;
3043 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
3048 * ice_aq_set_port_id_led
3049 * @pi: pointer to the port information
3050 * @is_orig_mode: is this LED set to original mode (by the net-list)
3051 * @cd: pointer to command details structure or NULL
3053 * Set LED value for the given port (0x06e9)
3056 ice_aq_set_port_id_led(struct ice_port_info *pi, bool is_orig_mode,
3057 struct ice_sq_cd *cd)
3059 struct ice_aqc_set_port_id_led *cmd;
3060 struct ice_hw *hw = pi->hw;
3061 struct ice_aq_desc desc;
3063 cmd = &desc.params.set_port_id_led;
3065 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_port_id_led);
3069 cmd->ident_mode = ICE_AQC_PORT_IDENT_LED_ORIG;
3071 cmd->ident_mode = ICE_AQC_PORT_IDENT_LED_BLINK;
3073 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
3078 * @hw: pointer to the HW struct
3079 * @lport: bits [7:0] = logical port, bit [8] = logical port valid
3080 * @bus_addr: I2C bus address of the eeprom (typically 0xA0, 0=topo default)
3081 * @mem_addr: I2C offset. lower 8 bits for address, 8 upper bits zero padding.
3083 * @set_page: set or ignore the page
3084 * @data: pointer to data buffer to be read/written to the I2C device.
3085 * @length: 1-16 for read, 1 for write.
3086 * @write: 0 read, 1 for write.
3087 * @cd: pointer to command details structure or NULL
3089 * Read/Write SFF EEPROM (0x06EE)
3092 ice_aq_sff_eeprom(struct ice_hw *hw, u16 lport, u8 bus_addr,
3093 u16 mem_addr, u8 page, u8 set_page, u8 *data, u8 length,
3094 bool write, struct ice_sq_cd *cd)
3096 struct ice_aqc_sff_eeprom *cmd;
3097 struct ice_aq_desc desc;
3098 enum ice_status status;
3100 if (!data || (mem_addr & 0xff00))
3101 return ICE_ERR_PARAM;
3103 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_sff_eeprom);
3104 cmd = &desc.params.read_write_sff_param;
3105 desc.flags = CPU_TO_LE16(ICE_AQ_FLAG_RD | ICE_AQ_FLAG_BUF);
3106 cmd->lport_num = (u8)(lport & 0xff);
3107 cmd->lport_num_valid = (u8)((lport >> 8) & 0x01);
3108 cmd->i2c_bus_addr = CPU_TO_LE16(((bus_addr >> 1) &
3109 ICE_AQC_SFF_I2CBUS_7BIT_M) |
3111 ICE_AQC_SFF_SET_EEPROM_PAGE_S) &
3112 ICE_AQC_SFF_SET_EEPROM_PAGE_M));
3113 cmd->i2c_mem_addr = CPU_TO_LE16(mem_addr & 0xff);
3114 cmd->eeprom_page = CPU_TO_LE16((u16)page << ICE_AQC_SFF_EEPROM_PAGE_S);
3116 cmd->i2c_bus_addr |= CPU_TO_LE16(ICE_AQC_SFF_IS_WRITE);
3118 status = ice_aq_send_cmd(hw, &desc, data, length, cd);
3123 * __ice_aq_get_set_rss_lut
3124 * @hw: pointer to the hardware structure
3125 * @vsi_id: VSI FW index
3126 * @lut_type: LUT table type
3127 * @lut: pointer to the LUT buffer provided by the caller
3128 * @lut_size: size of the LUT buffer
3129 * @glob_lut_idx: global LUT index
3130 * @set: set true to set the table, false to get the table
3132 * Internal function to get (0x0B05) or set (0x0B03) RSS look up table
3134 static enum ice_status
3135 __ice_aq_get_set_rss_lut(struct ice_hw *hw, u16 vsi_id, u8 lut_type, u8 *lut,
3136 u16 lut_size, u8 glob_lut_idx, bool set)
3138 struct ice_aqc_get_set_rss_lut *cmd_resp;
3139 struct ice_aq_desc desc;
3140 enum ice_status status;
3143 cmd_resp = &desc.params.get_set_rss_lut;
3146 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_rss_lut);
3147 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
3149 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_rss_lut);
3152 cmd_resp->vsi_id = CPU_TO_LE16(((vsi_id <<
3153 ICE_AQC_GSET_RSS_LUT_VSI_ID_S) &
3154 ICE_AQC_GSET_RSS_LUT_VSI_ID_M) |
3155 ICE_AQC_GSET_RSS_LUT_VSI_VALID);
3158 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_VSI:
3159 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF:
3160 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL:
3161 flags |= ((lut_type << ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S) &
3162 ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_M);
3165 status = ICE_ERR_PARAM;
3166 goto ice_aq_get_set_rss_lut_exit;
3169 if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL) {
3170 flags |= ((glob_lut_idx << ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S) &
3171 ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_M);
3174 goto ice_aq_get_set_rss_lut_send;
3175 } else if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF) {
3177 goto ice_aq_get_set_rss_lut_send;
3179 goto ice_aq_get_set_rss_lut_send;
3182 /* LUT size is only valid for Global and PF table types */
3184 case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128:
3185 flags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128_FLAG <<
3186 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) &
3187 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M;
3189 case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512:
3190 flags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512_FLAG <<
3191 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) &
3192 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M;
3194 case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K:
3195 if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF) {
3196 flags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K_FLAG <<
3197 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) &
3198 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M;
3203 status = ICE_ERR_PARAM;
3204 goto ice_aq_get_set_rss_lut_exit;
3207 ice_aq_get_set_rss_lut_send:
3208 cmd_resp->flags = CPU_TO_LE16(flags);
3209 status = ice_aq_send_cmd(hw, &desc, lut, lut_size, NULL);
3211 ice_aq_get_set_rss_lut_exit:
3216 * ice_aq_get_rss_lut
3217 * @hw: pointer to the hardware structure
3218 * @vsi_handle: software VSI handle
3219 * @lut_type: LUT table type
3220 * @lut: pointer to the LUT buffer provided by the caller
3221 * @lut_size: size of the LUT buffer
3223 * get the RSS lookup table, PF or VSI type
3226 ice_aq_get_rss_lut(struct ice_hw *hw, u16 vsi_handle, u8 lut_type,
3227 u8 *lut, u16 lut_size)
3229 if (!ice_is_vsi_valid(hw, vsi_handle) || !lut)
3230 return ICE_ERR_PARAM;
3232 return __ice_aq_get_set_rss_lut(hw, ice_get_hw_vsi_num(hw, vsi_handle),
3233 lut_type, lut, lut_size, 0, false);
3237 * ice_aq_set_rss_lut
3238 * @hw: pointer to the hardware structure
3239 * @vsi_handle: software VSI handle
3240 * @lut_type: LUT table type
3241 * @lut: pointer to the LUT buffer provided by the caller
3242 * @lut_size: size of the LUT buffer
3244 * set the RSS lookup table, PF or VSI type
3247 ice_aq_set_rss_lut(struct ice_hw *hw, u16 vsi_handle, u8 lut_type,
3248 u8 *lut, u16 lut_size)
3250 if (!ice_is_vsi_valid(hw, vsi_handle) || !lut)
3251 return ICE_ERR_PARAM;
3253 return __ice_aq_get_set_rss_lut(hw, ice_get_hw_vsi_num(hw, vsi_handle),
3254 lut_type, lut, lut_size, 0, true);
3258 * __ice_aq_get_set_rss_key
3259 * @hw: pointer to the HW struct
3260 * @vsi_id: VSI FW index
3261 * @key: pointer to key info struct
3262 * @set: set true to set the key, false to get the key
3264 * get (0x0B04) or set (0x0B02) the RSS key per VSI
3267 ice_status __ice_aq_get_set_rss_key(struct ice_hw *hw, u16 vsi_id,
3268 struct ice_aqc_get_set_rss_keys *key,
3271 struct ice_aqc_get_set_rss_key *cmd_resp;
3272 u16 key_size = sizeof(*key);
3273 struct ice_aq_desc desc;
3275 cmd_resp = &desc.params.get_set_rss_key;
3278 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_rss_key);
3279 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
3281 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_rss_key);
3284 cmd_resp->vsi_id = CPU_TO_LE16(((vsi_id <<
3285 ICE_AQC_GSET_RSS_KEY_VSI_ID_S) &
3286 ICE_AQC_GSET_RSS_KEY_VSI_ID_M) |
3287 ICE_AQC_GSET_RSS_KEY_VSI_VALID);
3289 return ice_aq_send_cmd(hw, &desc, key, key_size, NULL);
3293 * ice_aq_get_rss_key
3294 * @hw: pointer to the HW struct
3295 * @vsi_handle: software VSI handle
3296 * @key: pointer to key info struct
3298 * get the RSS key per VSI
3301 ice_aq_get_rss_key(struct ice_hw *hw, u16 vsi_handle,
3302 struct ice_aqc_get_set_rss_keys *key)
3304 if (!ice_is_vsi_valid(hw, vsi_handle) || !key)
3305 return ICE_ERR_PARAM;
3307 return __ice_aq_get_set_rss_key(hw, ice_get_hw_vsi_num(hw, vsi_handle),
3312 * ice_aq_set_rss_key
3313 * @hw: pointer to the HW struct
3314 * @vsi_handle: software VSI handle
3315 * @keys: pointer to key info struct
3317 * set the RSS key per VSI
3320 ice_aq_set_rss_key(struct ice_hw *hw, u16 vsi_handle,
3321 struct ice_aqc_get_set_rss_keys *keys)
3323 if (!ice_is_vsi_valid(hw, vsi_handle) || !keys)
3324 return ICE_ERR_PARAM;
3326 return __ice_aq_get_set_rss_key(hw, ice_get_hw_vsi_num(hw, vsi_handle),
3331 * ice_aq_add_lan_txq
3332 * @hw: pointer to the hardware structure
3333 * @num_qgrps: Number of added queue groups
3334 * @qg_list: list of queue groups to be added
3335 * @buf_size: size of buffer for indirect command
3336 * @cd: pointer to command details structure or NULL
3338 * Add Tx LAN queue (0x0C30)
3341 * Prior to calling add Tx LAN queue:
3342 * Initialize the following as part of the Tx queue context:
3343 * Completion queue ID if the queue uses Completion queue, Quanta profile,
3344 * Cache profile and Packet shaper profile.
3346 * After add Tx LAN queue AQ command is completed:
3347 * Interrupts should be associated with specific queues,
3348 * Association of Tx queue to Doorbell queue is not part of Add LAN Tx queue
3352 ice_aq_add_lan_txq(struct ice_hw *hw, u8 num_qgrps,
3353 struct ice_aqc_add_tx_qgrp *qg_list, u16 buf_size,
3354 struct ice_sq_cd *cd)
3356 u16 i, sum_header_size, sum_q_size = 0;
3357 struct ice_aqc_add_tx_qgrp *list;
3358 struct ice_aqc_add_txqs *cmd;
3359 struct ice_aq_desc desc;
3361 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
3363 cmd = &desc.params.add_txqs;
3365 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_add_txqs);
3368 return ICE_ERR_PARAM;
3370 if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS)
3371 return ICE_ERR_PARAM;
3373 sum_header_size = num_qgrps *
3374 (sizeof(*qg_list) - sizeof(*qg_list->txqs));
3377 for (i = 0; i < num_qgrps; i++) {
3378 struct ice_aqc_add_txqs_perq *q = list->txqs;
3380 sum_q_size += list->num_txqs * sizeof(*q);
3381 list = (struct ice_aqc_add_tx_qgrp *)(q + list->num_txqs);
3384 if (buf_size != (sum_header_size + sum_q_size))
3385 return ICE_ERR_PARAM;
3387 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
3389 cmd->num_qgrps = num_qgrps;
3391 return ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd);
3395 * ice_aq_dis_lan_txq
3396 * @hw: pointer to the hardware structure
3397 * @num_qgrps: number of groups in the list
3398 * @qg_list: the list of groups to disable
3399 * @buf_size: the total size of the qg_list buffer in bytes
3400 * @rst_src: if called due to reset, specifies the reset source
3401 * @vmvf_num: the relative VM or VF number that is undergoing the reset
3402 * @cd: pointer to command details structure or NULL
3404 * Disable LAN Tx queue (0x0C31)
3406 static enum ice_status
3407 ice_aq_dis_lan_txq(struct ice_hw *hw, u8 num_qgrps,
3408 struct ice_aqc_dis_txq_item *qg_list, u16 buf_size,
3409 enum ice_disq_rst_src rst_src, u16 vmvf_num,
3410 struct ice_sq_cd *cd)
3412 struct ice_aqc_dis_txqs *cmd;
3413 struct ice_aq_desc desc;
3414 enum ice_status status;
3417 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
3418 cmd = &desc.params.dis_txqs;
3419 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_dis_txqs);
3421 /* qg_list can be NULL only in VM/VF reset flow */
3422 if (!qg_list && !rst_src)
3423 return ICE_ERR_PARAM;
3425 if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS)
3426 return ICE_ERR_PARAM;
3428 cmd->num_entries = num_qgrps;
3430 cmd->vmvf_and_timeout = CPU_TO_LE16((5 << ICE_AQC_Q_DIS_TIMEOUT_S) &
3431 ICE_AQC_Q_DIS_TIMEOUT_M);
3435 cmd->cmd_type = ICE_AQC_Q_DIS_CMD_VM_RESET;
3436 cmd->vmvf_and_timeout |=
3437 CPU_TO_LE16(vmvf_num & ICE_AQC_Q_DIS_VMVF_NUM_M);
3444 /* flush pipe on time out */
3445 cmd->cmd_type |= ICE_AQC_Q_DIS_CMD_FLUSH_PIPE;
3446 /* If no queue group info, we are in a reset flow. Issue the AQ */
3450 /* set RD bit to indicate that command buffer is provided by the driver
3451 * and it needs to be read by the firmware
3453 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
3455 for (i = 0; i < num_qgrps; ++i) {
3456 /* Calculate the size taken up by the queue IDs in this group */
3457 sz += qg_list[i].num_qs * sizeof(qg_list[i].q_id);
3459 /* Add the size of the group header */
3460 sz += sizeof(qg_list[i]) - sizeof(qg_list[i].q_id);
3462 /* If the num of queues is even, add 2 bytes of padding */
3463 if ((qg_list[i].num_qs % 2) == 0)
3468 return ICE_ERR_PARAM;
3471 status = ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd);
3474 ice_debug(hw, ICE_DBG_SCHED, "VM%d disable failed %d\n",
3475 vmvf_num, hw->adminq.sq_last_status);
3477 ice_debug(hw, ICE_DBG_SCHED, "disable queue %d failed %d\n",
3478 LE16_TO_CPU(qg_list[0].q_id[0]),
3479 hw->adminq.sq_last_status);
3485 * ice_aq_move_recfg_lan_txq
3486 * @hw: pointer to the hardware structure
3487 * @num_qs: number of queues to move/reconfigure
3488 * @is_move: true if this operation involves node movement
3489 * @is_tc_change: true if this operation involves a TC change
3490 * @subseq_call: true if this operation is a subsequent call
3491 * @flush_pipe: on timeout, true to flush pipe, false to return EAGAIN
3492 * @timeout: timeout in units of 100 usec (valid values 0-50)
3493 * @blocked_cgds: out param, bitmap of CGDs that timed out if returning EAGAIN
3494 * @buf: struct containing src/dest TEID and per-queue info
3495 * @buf_size: size of buffer for indirect command
3496 * @txqs_moved: out param, number of queues successfully moved
3497 * @cd: pointer to command details structure or NULL
3499 * Move / Reconfigure Tx LAN queues (0x0C32)
3502 ice_aq_move_recfg_lan_txq(struct ice_hw *hw, u8 num_qs, bool is_move,
3503 bool is_tc_change, bool subseq_call, bool flush_pipe,
3504 u8 timeout, u32 *blocked_cgds,
3505 struct ice_aqc_move_txqs_data *buf, u16 buf_size,
3506 u8 *txqs_moved, struct ice_sq_cd *cd)
3508 struct ice_aqc_move_txqs *cmd;
3509 struct ice_aq_desc desc;
3510 enum ice_status status;
3512 cmd = &desc.params.move_txqs;
3513 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_move_recfg_txqs);
3515 #define ICE_LAN_TXQ_MOVE_TIMEOUT_MAX 50
3516 if (timeout > ICE_LAN_TXQ_MOVE_TIMEOUT_MAX)
3517 return ICE_ERR_PARAM;
3519 if (is_tc_change && !flush_pipe && !blocked_cgds)
3520 return ICE_ERR_PARAM;
3522 if (!is_move && !is_tc_change)
3523 return ICE_ERR_PARAM;
3525 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
3528 cmd->cmd_type |= ICE_AQC_Q_CMD_TYPE_MOVE;
3531 cmd->cmd_type |= ICE_AQC_Q_CMD_TYPE_TC_CHANGE;
3534 cmd->cmd_type |= ICE_AQC_Q_CMD_SUBSEQ_CALL;
3537 cmd->cmd_type |= ICE_AQC_Q_CMD_FLUSH_PIPE;
3539 cmd->num_qs = num_qs;
3540 cmd->timeout = ((timeout << ICE_AQC_Q_CMD_TIMEOUT_S) &
3541 ICE_AQC_Q_CMD_TIMEOUT_M);
3543 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);
3545 if (!status && txqs_moved)
3546 *txqs_moved = cmd->num_qs;
3548 if (hw->adminq.sq_last_status == ICE_AQ_RC_EAGAIN &&
3549 is_tc_change && !flush_pipe)
3550 *blocked_cgds = LE32_TO_CPU(cmd->blocked_cgds);
3556 /* End of FW Admin Queue command wrappers */
3559 * ice_write_byte - write a byte to a packed context structure
3560 * @src_ctx: the context structure to read from
3561 * @dest_ctx: the context to be written to
3562 * @ce_info: a description of the struct to be filled
3565 ice_write_byte(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)
3567 u8 src_byte, dest_byte, mask;
3571 /* copy from the next struct field */
3572 from = src_ctx + ce_info->offset;
3574 /* prepare the bits and mask */
3575 shift_width = ce_info->lsb % 8;
3576 mask = (u8)(BIT(ce_info->width) - 1);
3581 /* shift to correct alignment */
3582 mask <<= shift_width;
3583 src_byte <<= shift_width;
3585 /* get the current bits from the target bit string */
3586 dest = dest_ctx + (ce_info->lsb / 8);
3588 ice_memcpy(&dest_byte, dest, sizeof(dest_byte), ICE_DMA_TO_NONDMA);
3590 dest_byte &= ~mask; /* get the bits not changing */
3591 dest_byte |= src_byte; /* add in the new bits */
3593 /* put it all back */
3594 ice_memcpy(dest, &dest_byte, sizeof(dest_byte), ICE_NONDMA_TO_DMA);
3598 * ice_write_word - write a word to a packed context structure
3599 * @src_ctx: the context structure to read from
3600 * @dest_ctx: the context to be written to
3601 * @ce_info: a description of the struct to be filled
3604 ice_write_word(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)
3611 /* copy from the next struct field */
3612 from = src_ctx + ce_info->offset;
3614 /* prepare the bits and mask */
3615 shift_width = ce_info->lsb % 8;
3616 mask = BIT(ce_info->width) - 1;
3618 /* don't swizzle the bits until after the mask because the mask bits
3619 * will be in a different bit position on big endian machines
3621 src_word = *(u16 *)from;
3624 /* shift to correct alignment */
3625 mask <<= shift_width;
3626 src_word <<= shift_width;
3628 /* get the current bits from the target bit string */
3629 dest = dest_ctx + (ce_info->lsb / 8);
3631 ice_memcpy(&dest_word, dest, sizeof(dest_word), ICE_DMA_TO_NONDMA);
3633 dest_word &= ~(CPU_TO_LE16(mask)); /* get the bits not changing */
3634 dest_word |= CPU_TO_LE16(src_word); /* add in the new bits */
3636 /* put it all back */
3637 ice_memcpy(dest, &dest_word, sizeof(dest_word), ICE_NONDMA_TO_DMA);
3641 * ice_write_dword - write a dword to a packed context structure
3642 * @src_ctx: the context structure to read from
3643 * @dest_ctx: the context to be written to
3644 * @ce_info: a description of the struct to be filled
3647 ice_write_dword(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)
3649 u32 src_dword, mask;
3654 /* copy from the next struct field */
3655 from = src_ctx + ce_info->offset;
3657 /* prepare the bits and mask */
3658 shift_width = ce_info->lsb % 8;
3660 /* if the field width is exactly 32 on an x86 machine, then the shift
3661 * operation will not work because the SHL instructions count is masked
3662 * to 5 bits so the shift will do nothing
3664 if (ce_info->width < 32)
3665 mask = BIT(ce_info->width) - 1;
3669 /* don't swizzle the bits until after the mask because the mask bits
3670 * will be in a different bit position on big endian machines
3672 src_dword = *(u32 *)from;
3675 /* shift to correct alignment */
3676 mask <<= shift_width;
3677 src_dword <<= shift_width;
3679 /* get the current bits from the target bit string */
3680 dest = dest_ctx + (ce_info->lsb / 8);
3682 ice_memcpy(&dest_dword, dest, sizeof(dest_dword), ICE_DMA_TO_NONDMA);
3684 dest_dword &= ~(CPU_TO_LE32(mask)); /* get the bits not changing */
3685 dest_dword |= CPU_TO_LE32(src_dword); /* add in the new bits */
3687 /* put it all back */
3688 ice_memcpy(dest, &dest_dword, sizeof(dest_dword), ICE_NONDMA_TO_DMA);
3692 * ice_write_qword - write a qword to a packed context structure
3693 * @src_ctx: the context structure to read from
3694 * @dest_ctx: the context to be written to
3695 * @ce_info: a description of the struct to be filled
3698 ice_write_qword(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)
3700 u64 src_qword, mask;
3705 /* copy from the next struct field */
3706 from = src_ctx + ce_info->offset;
3708 /* prepare the bits and mask */
3709 shift_width = ce_info->lsb % 8;
3711 /* if the field width is exactly 64 on an x86 machine, then the shift
3712 * operation will not work because the SHL instructions count is masked
3713 * to 6 bits so the shift will do nothing
3715 if (ce_info->width < 64)
3716 mask = BIT_ULL(ce_info->width) - 1;
3720 /* don't swizzle the bits until after the mask because the mask bits
3721 * will be in a different bit position on big endian machines
3723 src_qword = *(u64 *)from;
3726 /* shift to correct alignment */
3727 mask <<= shift_width;
3728 src_qword <<= shift_width;
3730 /* get the current bits from the target bit string */
3731 dest = dest_ctx + (ce_info->lsb / 8);
3733 ice_memcpy(&dest_qword, dest, sizeof(dest_qword), ICE_DMA_TO_NONDMA);
3735 dest_qword &= ~(CPU_TO_LE64(mask)); /* get the bits not changing */
3736 dest_qword |= CPU_TO_LE64(src_qword); /* add in the new bits */
3738 /* put it all back */
3739 ice_memcpy(dest, &dest_qword, sizeof(dest_qword), ICE_NONDMA_TO_DMA);
3743 * ice_set_ctx - set context bits in packed structure
3744 * @src_ctx: pointer to a generic non-packed context structure
3745 * @dest_ctx: pointer to memory for the packed structure
3746 * @ce_info: a description of the structure to be transformed
3749 ice_set_ctx(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)
3753 for (f = 0; ce_info[f].width; f++) {
3754 /* We have to deal with each element of the FW response
3755 * using the correct size so that we are correct regardless
3756 * of the endianness of the machine.
3758 switch (ce_info[f].size_of) {
3760 ice_write_byte(src_ctx, dest_ctx, &ce_info[f]);
3763 ice_write_word(src_ctx, dest_ctx, &ce_info[f]);
3766 ice_write_dword(src_ctx, dest_ctx, &ce_info[f]);
3769 ice_write_qword(src_ctx, dest_ctx, &ce_info[f]);
3772 return ICE_ERR_INVAL_SIZE;
3783 * ice_read_byte - read context byte into struct
3784 * @src_ctx: the context structure to read from
3785 * @dest_ctx: the context to be written to
3786 * @ce_info: a description of the struct to be filled
3789 ice_read_byte(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info)
3795 /* prepare the bits and mask */
3796 shift_width = ce_info->lsb % 8;
3797 mask = (u8)(BIT(ce_info->width) - 1);
3799 /* shift to correct alignment */
3800 mask <<= shift_width;
3802 /* get the current bits from the src bit string */
3803 src = src_ctx + (ce_info->lsb / 8);
3805 ice_memcpy(&dest_byte, src, sizeof(dest_byte), ICE_DMA_TO_NONDMA);
3807 dest_byte &= ~(mask);
3809 dest_byte >>= shift_width;
3811 /* get the address from the struct field */
3812 target = dest_ctx + ce_info->offset;
3814 /* put it back in the struct */
3815 ice_memcpy(target, &dest_byte, sizeof(dest_byte), ICE_NONDMA_TO_DMA);
3819 * ice_read_word - read context word into struct
3820 * @src_ctx: the context structure to read from
3821 * @dest_ctx: the context to be written to
3822 * @ce_info: a description of the struct to be filled
3825 ice_read_word(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info)
3827 u16 dest_word, mask;
3832 /* prepare the bits and mask */
3833 shift_width = ce_info->lsb % 8;
3834 mask = BIT(ce_info->width) - 1;
3836 /* shift to correct alignment */
3837 mask <<= shift_width;
3839 /* get the current bits from the src bit string */
3840 src = src_ctx + (ce_info->lsb / 8);
3842 ice_memcpy(&src_word, src, sizeof(src_word), ICE_DMA_TO_NONDMA);
3844 /* the data in the memory is stored as little endian so mask it
3847 src_word &= ~(CPU_TO_LE16(mask));
3849 /* get the data back into host order before shifting */
3850 dest_word = LE16_TO_CPU(src_word);
3852 dest_word >>= shift_width;
3854 /* get the address from the struct field */
3855 target = dest_ctx + ce_info->offset;
3857 /* put it back in the struct */
3858 ice_memcpy(target, &dest_word, sizeof(dest_word), ICE_NONDMA_TO_DMA);
3862 * ice_read_dword - read context dword into struct
3863 * @src_ctx: the context structure to read from
3864 * @dest_ctx: the context to be written to
3865 * @ce_info: a description of the struct to be filled
3868 ice_read_dword(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info)
3870 u32 dest_dword, mask;
3875 /* prepare the bits and mask */
3876 shift_width = ce_info->lsb % 8;
3878 /* if the field width is exactly 32 on an x86 machine, then the shift
3879 * operation will not work because the SHL instructions count is masked
3880 * to 5 bits so the shift will do nothing
3882 if (ce_info->width < 32)
3883 mask = BIT(ce_info->width) - 1;
3887 /* shift to correct alignment */
3888 mask <<= shift_width;
3890 /* get the current bits from the src bit string */
3891 src = src_ctx + (ce_info->lsb / 8);
3893 ice_memcpy(&src_dword, src, sizeof(src_dword), ICE_DMA_TO_NONDMA);
3895 /* the data in the memory is stored as little endian so mask it
3898 src_dword &= ~(CPU_TO_LE32(mask));
3900 /* get the data back into host order before shifting */
3901 dest_dword = LE32_TO_CPU(src_dword);
3903 dest_dword >>= shift_width;
3905 /* get the address from the struct field */
3906 target = dest_ctx + ce_info->offset;
3908 /* put it back in the struct */
3909 ice_memcpy(target, &dest_dword, sizeof(dest_dword), ICE_NONDMA_TO_DMA);
3913 * ice_read_qword - read context qword into struct
3914 * @src_ctx: the context structure to read from
3915 * @dest_ctx: the context to be written to
3916 * @ce_info: a description of the struct to be filled
3919 ice_read_qword(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info)
3921 u64 dest_qword, mask;
3926 /* prepare the bits and mask */
3927 shift_width = ce_info->lsb % 8;
3929 /* if the field width is exactly 64 on an x86 machine, then the shift
3930 * operation will not work because the SHL instructions count is masked
3931 * to 6 bits so the shift will do nothing
3933 if (ce_info->width < 64)
3934 mask = BIT_ULL(ce_info->width) - 1;
3938 /* shift to correct alignment */
3939 mask <<= shift_width;
3941 /* get the current bits from the src bit string */
3942 src = src_ctx + (ce_info->lsb / 8);
3944 ice_memcpy(&src_qword, src, sizeof(src_qword), ICE_DMA_TO_NONDMA);
3946 /* the data in the memory is stored as little endian so mask it
3949 src_qword &= ~(CPU_TO_LE64(mask));
3951 /* get the data back into host order before shifting */
3952 dest_qword = LE64_TO_CPU(src_qword);
3954 dest_qword >>= shift_width;
3956 /* get the address from the struct field */
3957 target = dest_ctx + ce_info->offset;
3959 /* put it back in the struct */
3960 ice_memcpy(target, &dest_qword, sizeof(dest_qword), ICE_NONDMA_TO_DMA);
3964 * ice_get_ctx - extract context bits from a packed structure
3965 * @src_ctx: pointer to a generic packed context structure
3966 * @dest_ctx: pointer to a generic non-packed context structure
3967 * @ce_info: a description of the structure to be read from
3970 ice_get_ctx(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info)
3974 for (f = 0; ce_info[f].width; f++) {
3975 switch (ce_info[f].size_of) {
3977 ice_read_byte(src_ctx, dest_ctx, &ce_info[f]);
3980 ice_read_word(src_ctx, dest_ctx, &ce_info[f]);
3983 ice_read_dword(src_ctx, dest_ctx, &ce_info[f]);
3986 ice_read_qword(src_ctx, dest_ctx, &ce_info[f]);
3989 /* nothing to do, just keep going */
3998 * ice_get_lan_q_ctx - get the LAN queue context for the given VSI and TC
3999 * @hw: pointer to the HW struct
4000 * @vsi_handle: software VSI handle
4002 * @q_handle: software queue handle
4005 ice_get_lan_q_ctx(struct ice_hw *hw, u16 vsi_handle, u8 tc, u16 q_handle)
4007 struct ice_vsi_ctx *vsi;
4008 struct ice_q_ctx *q_ctx;
4010 vsi = ice_get_vsi_ctx(hw, vsi_handle);
4013 if (q_handle >= vsi->num_lan_q_entries[tc])
4015 if (!vsi->lan_q_ctx[tc])
4017 q_ctx = vsi->lan_q_ctx[tc];
4018 return &q_ctx[q_handle];
4023 * @pi: port information structure
4024 * @vsi_handle: software VSI handle
4026 * @q_handle: software queue handle
4027 * @num_qgrps: Number of added queue groups
4028 * @buf: list of queue groups to be added
4029 * @buf_size: size of buffer for indirect command
4030 * @cd: pointer to command details structure or NULL
4032 * This function adds one LAN queue
4035 ice_ena_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u16 q_handle,
4036 u8 num_qgrps, struct ice_aqc_add_tx_qgrp *buf, u16 buf_size,
4037 struct ice_sq_cd *cd)
4039 struct ice_aqc_txsched_elem_data node = { 0 };
4040 struct ice_sched_node *parent;
4041 struct ice_q_ctx *q_ctx;
4042 enum ice_status status;
4045 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY)
4048 if (num_qgrps > 1 || buf->num_txqs > 1)
4049 return ICE_ERR_MAX_LIMIT;
4053 if (!ice_is_vsi_valid(hw, vsi_handle))
4054 return ICE_ERR_PARAM;
4056 ice_acquire_lock(&pi->sched_lock);
4058 q_ctx = ice_get_lan_q_ctx(hw, vsi_handle, tc, q_handle);
4060 ice_debug(hw, ICE_DBG_SCHED, "Enaq: invalid queue handle %d\n",
4062 status = ICE_ERR_PARAM;
4066 /* find a parent node */
4067 parent = ice_sched_get_free_qparent(pi, vsi_handle, tc,
4068 ICE_SCHED_NODE_OWNER_LAN);
4070 status = ICE_ERR_PARAM;
4074 buf->parent_teid = parent->info.node_teid;
4075 node.parent_teid = parent->info.node_teid;
4076 /* Mark that the values in the "generic" section as valid. The default
4077 * value in the "generic" section is zero. This means that :
4078 * - Scheduling mode is Bytes Per Second (BPS), indicated by Bit 0.
4079 * - 0 priority among siblings, indicated by Bit 1-3.
4080 * - WFQ, indicated by Bit 4.
4081 * - 0 Adjustment value is used in PSM credit update flow, indicated by
4083 * - Bit 7 is reserved.
4084 * Without setting the generic section as valid in valid_sections, the
4085 * Admin queue command will fail with error code ICE_AQ_RC_EINVAL.
4087 buf->txqs[0].info.valid_sections = ICE_AQC_ELEM_VALID_GENERIC;
4089 /* add the LAN queue */
4090 status = ice_aq_add_lan_txq(hw, num_qgrps, buf, buf_size, cd);
4091 if (status != ICE_SUCCESS) {
4092 ice_debug(hw, ICE_DBG_SCHED, "enable queue %d failed %d\n",
4093 LE16_TO_CPU(buf->txqs[0].txq_id),
4094 hw->adminq.sq_last_status);
4098 node.node_teid = buf->txqs[0].q_teid;
4099 node.data.elem_type = ICE_AQC_ELEM_TYPE_LEAF;
4100 q_ctx->q_handle = q_handle;
4101 q_ctx->q_teid = LE32_TO_CPU(node.node_teid);
4103 /* add a leaf node into scheduler tree queue layer */
4104 status = ice_sched_add_node(pi, hw->num_tx_sched_layers - 1, &node);
4106 status = ice_sched_replay_q_bw(pi, q_ctx);
4109 ice_release_lock(&pi->sched_lock);
4115 * @pi: port information structure
4116 * @vsi_handle: software VSI handle
4118 * @num_queues: number of queues
4119 * @q_handles: pointer to software queue handle array
4120 * @q_ids: pointer to the q_id array
4121 * @q_teids: pointer to queue node teids
4122 * @rst_src: if called due to reset, specifies the reset source
4123 * @vmvf_num: the relative VM or VF number that is undergoing the reset
4124 * @cd: pointer to command details structure or NULL
4126 * This function removes queues and their corresponding nodes in SW DB
4129 ice_dis_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u8 num_queues,
4130 u16 *q_handles, u16 *q_ids, u32 *q_teids,
4131 enum ice_disq_rst_src rst_src, u16 vmvf_num,
4132 struct ice_sq_cd *cd)
4134 enum ice_status status = ICE_ERR_DOES_NOT_EXIST;
4135 struct ice_aqc_dis_txq_item qg_list;
4136 struct ice_q_ctx *q_ctx;
4139 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY)
4143 /* if queue is disabled already yet the disable queue command
4144 * has to be sent to complete the VF reset, then call
4145 * ice_aq_dis_lan_txq without any queue information
4148 return ice_aq_dis_lan_txq(pi->hw, 0, NULL, 0, rst_src,
4153 ice_acquire_lock(&pi->sched_lock);
4155 for (i = 0; i < num_queues; i++) {
4156 struct ice_sched_node *node;
4158 node = ice_sched_find_node_by_teid(pi->root, q_teids[i]);
4161 q_ctx = ice_get_lan_q_ctx(pi->hw, vsi_handle, tc, q_handles[i]);
4163 ice_debug(pi->hw, ICE_DBG_SCHED, "invalid queue handle%d\n",
4167 if (q_ctx->q_handle != q_handles[i]) {
4168 ice_debug(pi->hw, ICE_DBG_SCHED, "Err:handles %d %d\n",
4169 q_ctx->q_handle, q_handles[i]);
4172 qg_list.parent_teid = node->info.parent_teid;
4174 qg_list.q_id[0] = CPU_TO_LE16(q_ids[i]);
4175 status = ice_aq_dis_lan_txq(pi->hw, 1, &qg_list,
4176 sizeof(qg_list), rst_src, vmvf_num,
4179 if (status != ICE_SUCCESS)
4181 ice_free_sched_node(pi, node);
4182 q_ctx->q_handle = ICE_INVAL_Q_HANDLE;
4184 ice_release_lock(&pi->sched_lock);
4189 * ice_cfg_vsi_qs - configure the new/existing VSI queues
4190 * @pi: port information structure
4191 * @vsi_handle: software VSI handle
4192 * @tc_bitmap: TC bitmap
4193 * @maxqs: max queues array per TC
4194 * @owner: LAN or RDMA
4196 * This function adds/updates the VSI queues per TC.
4198 static enum ice_status
4199 ice_cfg_vsi_qs(struct ice_port_info *pi, u16 vsi_handle, u8 tc_bitmap,
4200 u16 *maxqs, u8 owner)
4202 enum ice_status status = ICE_SUCCESS;
4205 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY)
4208 if (!ice_is_vsi_valid(pi->hw, vsi_handle))
4209 return ICE_ERR_PARAM;
4211 ice_acquire_lock(&pi->sched_lock);
4213 ice_for_each_traffic_class(i) {
4214 /* configuration is possible only if TC node is present */
4215 if (!ice_sched_get_tc_node(pi, i))
4218 status = ice_sched_cfg_vsi(pi, vsi_handle, i, maxqs[i], owner,
4219 ice_is_tc_ena(tc_bitmap, i));
4224 ice_release_lock(&pi->sched_lock);
4229 * ice_cfg_vsi_lan - configure VSI LAN queues
4230 * @pi: port information structure
4231 * @vsi_handle: software VSI handle
4232 * @tc_bitmap: TC bitmap
4233 * @max_lanqs: max LAN queues array per TC
4235 * This function adds/updates the VSI LAN queues per TC.
4238 ice_cfg_vsi_lan(struct ice_port_info *pi, u16 vsi_handle, u8 tc_bitmap,
4241 return ice_cfg_vsi_qs(pi, vsi_handle, tc_bitmap, max_lanqs,
4242 ICE_SCHED_NODE_OWNER_LAN);
4248 * ice_replay_pre_init - replay pre initialization
4249 * @hw: pointer to the HW struct
4251 * Initializes required config data for VSI, FD, ACL, and RSS before replay.
4253 static enum ice_status ice_replay_pre_init(struct ice_hw *hw)
4255 struct ice_switch_info *sw = hw->switch_info;
4258 /* Delete old entries from replay filter list head if there is any */
4259 ice_rm_all_sw_replay_rule_info(hw);
4260 /* In start of replay, move entries into replay_rules list, it
4261 * will allow adding rules entries back to filt_rules list,
4262 * which is operational list.
4264 for (i = 0; i < ICE_MAX_NUM_RECIPES; i++)
4265 LIST_REPLACE_INIT(&sw->recp_list[i].filt_rules,
4266 &sw->recp_list[i].filt_replay_rules);
4267 ice_sched_replay_agg_vsi_preinit(hw);
4269 return ice_sched_replay_tc_node_bw(hw->port_info);
4273 * ice_replay_vsi - replay VSI configuration
4274 * @hw: pointer to the HW struct
4275 * @vsi_handle: driver VSI handle
4277 * Restore all VSI configuration after reset. It is required to call this
4278 * function with main VSI first.
4280 enum ice_status ice_replay_vsi(struct ice_hw *hw, u16 vsi_handle)
4282 enum ice_status status;
4284 if (!ice_is_vsi_valid(hw, vsi_handle))
4285 return ICE_ERR_PARAM;
4287 /* Replay pre-initialization if there is any */
4288 if (vsi_handle == ICE_MAIN_VSI_HANDLE) {
4289 status = ice_replay_pre_init(hw);
4293 /* Replay per VSI all RSS configurations */
4294 status = ice_replay_rss_cfg(hw, vsi_handle);
4297 /* Replay per VSI all filters */
4298 status = ice_replay_vsi_all_fltr(hw, vsi_handle);
4300 status = ice_replay_vsi_agg(hw, vsi_handle);
4305 * ice_replay_post - post replay configuration cleanup
4306 * @hw: pointer to the HW struct
4308 * Post replay cleanup.
4310 void ice_replay_post(struct ice_hw *hw)
4312 /* Delete old entries from replay filter list head */
4313 ice_rm_all_sw_replay_rule_info(hw);
4314 ice_sched_replay_agg(hw);
4318 * ice_stat_update40 - read 40 bit stat from the chip and update stat values
4319 * @hw: ptr to the hardware info
4320 * @reg: offset of 64 bit HW register to read from
4321 * @prev_stat_loaded: bool to specify if previous stats are loaded
4322 * @prev_stat: ptr to previous loaded stat value
4323 * @cur_stat: ptr to current stat value
4326 ice_stat_update40(struct ice_hw *hw, u32 reg, bool prev_stat_loaded,
4327 u64 *prev_stat, u64 *cur_stat)
4329 u64 new_data = rd64(hw, reg) & (BIT_ULL(40) - 1);
4331 /* device stats are not reset at PFR, they likely will not be zeroed
4332 * when the driver starts. Thus, save the value from the first read
4333 * without adding to the statistic value so that we report stats which
4334 * count up from zero.
4336 if (!prev_stat_loaded) {
4337 *prev_stat = new_data;
4341 /* Calculate the difference between the new and old values, and then
4342 * add it to the software stat value.
4344 if (new_data >= *prev_stat)
4345 *cur_stat += new_data - *prev_stat;
4347 /* to manage the potential roll-over */
4348 *cur_stat += (new_data + BIT_ULL(40)) - *prev_stat;
4350 /* Update the previously stored value to prepare for next read */
4351 *prev_stat = new_data;
4355 * ice_stat_update32 - read 32 bit stat from the chip and update stat values
4356 * @hw: ptr to the hardware info
4357 * @reg: offset of HW register to read from
4358 * @prev_stat_loaded: bool to specify if previous stats are loaded
4359 * @prev_stat: ptr to previous loaded stat value
4360 * @cur_stat: ptr to current stat value
4363 ice_stat_update32(struct ice_hw *hw, u32 reg, bool prev_stat_loaded,
4364 u64 *prev_stat, u64 *cur_stat)
4368 new_data = rd32(hw, reg);
4370 /* device stats are not reset at PFR, they likely will not be zeroed
4371 * when the driver starts. Thus, save the value from the first read
4372 * without adding to the statistic value so that we report stats which
4373 * count up from zero.
4375 if (!prev_stat_loaded) {
4376 *prev_stat = new_data;
4380 /* Calculate the difference between the new and old values, and then
4381 * add it to the software stat value.
4383 if (new_data >= *prev_stat)
4384 *cur_stat += new_data - *prev_stat;
4386 /* to manage the potential roll-over */
4387 *cur_stat += (new_data + BIT_ULL(32)) - *prev_stat;
4389 /* Update the previously stored value to prepare for next read */
4390 *prev_stat = new_data;
4394 * ice_stat_update_repc - read GLV_REPC stats from chip and update stat values
4395 * @hw: ptr to the hardware info
4396 * @vsi_handle: VSI handle
4397 * @prev_stat_loaded: bool to specify if the previous stat values are loaded
4398 * @cur_stats: ptr to current stats structure
4400 * The GLV_REPC statistic register actually tracks two 16bit statistics, and
4401 * thus cannot be read using the normal ice_stat_update32 function.
4403 * Read the GLV_REPC register associated with the given VSI, and update the
4404 * rx_no_desc and rx_error values in the ice_eth_stats structure.
4406 * Because the statistics in GLV_REPC stick at 0xFFFF, the register must be
4407 * cleared each time it's read.
4409 * Note that the GLV_RDPC register also counts the causes that would trigger
4410 * GLV_REPC. However, it does not give the finer grained detail about why the
4411 * packets are being dropped. The GLV_REPC values can be used to distinguish
4412 * whether Rx packets are dropped due to errors or due to no available
4416 ice_stat_update_repc(struct ice_hw *hw, u16 vsi_handle, bool prev_stat_loaded,
4417 struct ice_eth_stats *cur_stats)
4419 u16 vsi_num, no_desc, error_cnt;
4422 if (!ice_is_vsi_valid(hw, vsi_handle))
4425 vsi_num = ice_get_hw_vsi_num(hw, vsi_handle);
4427 /* If we haven't loaded stats yet, just clear the current value */
4428 if (!prev_stat_loaded) {
4429 wr32(hw, GLV_REPC(vsi_num), 0);
4433 repc = rd32(hw, GLV_REPC(vsi_num));
4434 no_desc = (repc & GLV_REPC_NO_DESC_CNT_M) >> GLV_REPC_NO_DESC_CNT_S;
4435 error_cnt = (repc & GLV_REPC_ERROR_CNT_M) >> GLV_REPC_ERROR_CNT_S;
4437 /* Clear the count by writing to the stats register */
4438 wr32(hw, GLV_REPC(vsi_num), 0);
4440 cur_stats->rx_no_desc += no_desc;
4441 cur_stats->rx_errors += error_cnt;
4446 * ice_sched_query_elem - query element information from HW
4447 * @hw: pointer to the HW struct
4448 * @node_teid: node TEID to be queried
4449 * @buf: buffer to element information
4451 * This function queries HW element information
4454 ice_sched_query_elem(struct ice_hw *hw, u32 node_teid,
4455 struct ice_aqc_get_elem *buf)
4457 u16 buf_size, num_elem_ret = 0;
4458 enum ice_status status;
4460 buf_size = sizeof(*buf);
4461 ice_memset(buf, 0, buf_size, ICE_NONDMA_MEM);
4462 buf->generic[0].node_teid = CPU_TO_LE32(node_teid);
4463 status = ice_aq_query_sched_elems(hw, 1, buf, buf_size, &num_elem_ret,
4465 if (status != ICE_SUCCESS || num_elem_ret != 1)
4466 ice_debug(hw, ICE_DBG_SCHED, "query element failed\n");
4471 * ice_get_fw_mode - returns FW mode
4472 * @hw: pointer to the HW struct
4474 enum ice_fw_modes ice_get_fw_mode(struct ice_hw *hw)
4476 #define ICE_FW_MODE_DBG_M BIT(0)
4477 #define ICE_FW_MODE_REC_M BIT(1)
4478 #define ICE_FW_MODE_ROLLBACK_M BIT(2)
4481 /* check the current FW mode */
4482 fw_mode = rd32(hw, GL_MNG_FWSM) & GL_MNG_FWSM_FW_MODES_M;
4484 if (fw_mode & ICE_FW_MODE_DBG_M)
4485 return ICE_FW_MODE_DBG;
4486 else if (fw_mode & ICE_FW_MODE_REC_M)
4487 return ICE_FW_MODE_REC;
4488 else if (fw_mode & ICE_FW_MODE_ROLLBACK_M)
4489 return ICE_FW_MODE_ROLLBACK;
4491 return ICE_FW_MODE_NORMAL;