1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2001-2019
9 #include "ice_flex_pipe.h"
10 #include "ice_switch.h"
20 enum ice_status ice_nvm_validate_checksum(struct ice_hw *hw);
22 enum ice_status ice_init_hw(struct ice_hw *hw);
23 void ice_deinit_hw(struct ice_hw *hw);
24 enum ice_status ice_check_reset(struct ice_hw *hw);
25 enum ice_status ice_reset(struct ice_hw *hw, enum ice_reset_req req);
27 enum ice_status ice_create_all_ctrlq(struct ice_hw *hw);
28 enum ice_status ice_init_all_ctrlq(struct ice_hw *hw);
29 void ice_shutdown_all_ctrlq(struct ice_hw *hw);
30 void ice_destroy_all_ctrlq(struct ice_hw *hw);
32 ice_clean_rq_elem(struct ice_hw *hw, struct ice_ctl_q_info *cq,
33 struct ice_rq_event_info *e, u16 *pending);
35 ice_get_link_status(struct ice_port_info *pi, bool *link_up);
36 enum ice_status ice_update_link_info(struct ice_port_info *pi);
38 ice_acquire_res(struct ice_hw *hw, enum ice_aq_res_ids res,
39 enum ice_aq_res_access_type access, u32 timeout);
40 void ice_release_res(struct ice_hw *hw, enum ice_aq_res_ids res);
42 ice_alloc_hw_res(struct ice_hw *hw, u16 type, u16 num, bool btm, u16 *res);
44 ice_free_hw_res(struct ice_hw *hw, u16 type, u16 num, u16 *res);
46 ice_aq_alloc_free_res(struct ice_hw *hw, u16 num_entries,
47 struct ice_aqc_alloc_free_res_elem *buf, u16 buf_size,
48 enum ice_adminq_opc opc, struct ice_sq_cd *cd);
49 enum ice_status ice_init_nvm(struct ice_hw *hw);
50 enum ice_status ice_read_sr_word(struct ice_hw *hw, u16 offset, u16 *data);
52 ice_read_sr_buf(struct ice_hw *hw, u16 offset, u16 *words, u16 *data);
54 ice_sq_send_cmd(struct ice_hw *hw, struct ice_ctl_q_info *cq,
55 struct ice_aq_desc *desc, void *buf, u16 buf_size,
56 struct ice_sq_cd *cd);
57 void ice_clear_pxe_mode(struct ice_hw *hw);
59 enum ice_status ice_get_caps(struct ice_hw *hw);
61 /* Define a macro that will align a pointer to point to the next memory address
62 * that falls on the given power of 2 (i.e., 2, 4, 8, 16, 32, 64...). For
63 * example, given the variable pointer = 0x1006, then after the following call:
65 * pointer = ICE_ALIGN(pointer, 4)
67 * ... the value of pointer would equal 0x1008, since 0x1008 is the next
68 * address after 0x1006 which is divisible by 4.
70 #define ICE_ALIGN(ptr, align) (((ptr) + ((align) - 1)) & ~((align) - 1))
73 ice_write_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx,
75 #if !defined(NO_UNUSED_CTX_CODE) || defined(AE_DRIVER)
76 enum ice_status ice_clear_rxq_ctx(struct ice_hw *hw, u32 rxq_index);
78 ice_clear_tx_cmpltnq_ctx(struct ice_hw *hw, u32 tx_cmpltnq_index);
80 ice_write_tx_cmpltnq_ctx(struct ice_hw *hw,
81 struct ice_tx_cmpltnq_ctx *tx_cmpltnq_ctx,
82 u32 tx_cmpltnq_index);
84 ice_clear_tx_drbell_q_ctx(struct ice_hw *hw, u32 tx_drbell_q_index);
86 ice_write_tx_drbell_q_ctx(struct ice_hw *hw,
87 struct ice_tx_drbell_q_ctx *tx_drbell_q_ctx,
88 u32 tx_drbell_q_index);
89 #endif /* !NO_UNUSED_CTX_CODE || AE_DRIVER */
92 ice_aq_get_rss_lut(struct ice_hw *hw, u16 vsi_handle, u8 lut_type, u8 *lut,
95 ice_aq_set_rss_lut(struct ice_hw *hw, u16 vsi_handle, u8 lut_type, u8 *lut,
98 ice_aq_get_rss_key(struct ice_hw *hw, u16 vsi_handle,
99 struct ice_aqc_get_set_rss_keys *keys);
101 ice_aq_set_rss_key(struct ice_hw *hw, u16 vsi_handle,
102 struct ice_aqc_get_set_rss_keys *keys);
104 ice_aq_add_lan_txq(struct ice_hw *hw, u8 count,
105 struct ice_aqc_add_tx_qgrp *qg_list, u16 buf_size,
106 struct ice_sq_cd *cd);
108 bool ice_check_sq_alive(struct ice_hw *hw, struct ice_ctl_q_info *cq);
109 enum ice_status ice_aq_q_shutdown(struct ice_hw *hw, bool unloading);
110 void ice_fill_dflt_direct_cmd_desc(struct ice_aq_desc *desc, u16 opcode);
111 extern const struct ice_ctx_ele ice_tlan_ctx_info[];
113 ice_set_ctx(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info);
115 ice_aq_send_cmd(struct ice_hw *hw, struct ice_aq_desc *desc,
116 void *buf, u16 buf_size, struct ice_sq_cd *cd);
117 enum ice_status ice_aq_get_fw_ver(struct ice_hw *hw, struct ice_sq_cd *cd);
120 ice_aq_send_driver_ver(struct ice_hw *hw, struct ice_driver_ver *dv,
121 struct ice_sq_cd *cd);
123 ice_aq_get_phy_caps(struct ice_port_info *pi, bool qual_mods, u8 report_mode,
124 struct ice_aqc_get_phy_caps_data *caps,
125 struct ice_sq_cd *cd);
127 ice_update_phy_type(u64 *phy_type_low, u64 *phy_type_high,
128 u16 link_speeds_bitmap);
130 ice_aq_manage_mac_write(struct ice_hw *hw, const u8 *mac_addr, u8 flags,
131 struct ice_sq_cd *cd);
133 enum ice_status ice_clear_pf_cfg(struct ice_hw *hw);
135 ice_aq_set_phy_cfg(struct ice_hw *hw, struct ice_port_info *pi,
136 struct ice_aqc_set_phy_cfg_data *cfg, struct ice_sq_cd *cd);
138 ice_set_fc(struct ice_port_info *pi, u8 *aq_failures,
139 bool ena_auto_link_update);
141 ice_cfg_phy_fec(struct ice_aqc_set_phy_cfg_data *cfg, enum ice_fec_mode fec);
143 ice_copy_phy_caps_to_cfg(struct ice_aqc_get_phy_caps_data *caps,
144 struct ice_aqc_set_phy_cfg_data *cfg);
146 ice_aq_set_link_restart_an(struct ice_port_info *pi, bool ena_link,
147 struct ice_sq_cd *cd);
149 ice_aq_set_mac_cfg(struct ice_hw *hw, u16 max_frame_size, struct ice_sq_cd *cd);
151 ice_aq_get_link_info(struct ice_port_info *pi, bool ena_lse,
152 struct ice_link_status *link, struct ice_sq_cd *cd);
154 ice_aq_set_event_mask(struct ice_hw *hw, u8 port_num, u16 mask,
155 struct ice_sq_cd *cd);
157 ice_aq_set_mac_loopback(struct ice_hw *hw, bool ena_lpbk, struct ice_sq_cd *cd);
161 ice_aq_set_port_id_led(struct ice_port_info *pi, bool is_orig_mode,
162 struct ice_sq_cd *cd);
167 ice_get_ctx(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info);
169 ice_dis_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u8 num_queues,
170 u16 *q_handle, u16 *q_ids, u32 *q_teids,
171 enum ice_disq_rst_src rst_src, u16 vmvf_num,
172 struct ice_sq_cd *cd);
174 ice_cfg_vsi_lan(struct ice_port_info *pi, u16 vsi_handle, u8 tc_bitmap,
177 ice_ena_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u16 q_handle,
178 u8 num_qgrps, struct ice_aqc_add_tx_qgrp *buf, u16 buf_size,
179 struct ice_sq_cd *cd);
180 enum ice_status ice_replay_vsi(struct ice_hw *hw, u16 vsi_handle);
181 void ice_replay_post(struct ice_hw *hw);
182 void ice_sched_replay_agg_vsi_preinit(struct ice_hw *hw);
183 void ice_sched_replay_agg(struct ice_hw *hw);
184 enum ice_status ice_sched_replay_tc_node_bw(struct ice_hw *hw);
185 enum ice_status ice_replay_vsi_agg(struct ice_hw *hw, u16 vsi_handle);
187 ice_sched_replay_q_bw(struct ice_port_info *pi, struct ice_q_ctx *q_ctx);
189 ice_get_lan_q_ctx(struct ice_hw *hw, u16 vsi_handle, u8 tc, u16 q_handle);
191 ice_cfg_tc_node_bw_alloc(struct ice_port_info *pi, u8 tc,
192 enum ice_rl_type rl_type, u8 bw_alloc);
193 enum ice_status ice_cfg_rl_burst_size(struct ice_hw *hw, u32 bytes);
194 void ice_output_fw_log(struct ice_hw *hw, struct ice_aq_desc *desc, void *buf);
196 ice_stat_update40(struct ice_hw *hw, u32 reg, bool prev_stat_loaded,
197 u64 *prev_stat, u64 *cur_stat);
199 ice_stat_update32(struct ice_hw *hw, u32 reg, bool prev_stat_loaded,
200 u64 *prev_stat, u64 *cur_stat);
202 ice_sched_query_elem(struct ice_hw *hw, u32 node_teid,
203 struct ice_aqc_get_elem *buf);
204 bool ice_is_fw_in_rec_mode(struct ice_hw *hw);
205 #endif /* _ICE_COMMON_H_ */