1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2001-2020 Intel Corporation
10 #include "ice_flex_pipe.h"
11 #include "ice_switch.h"
21 enum ice_status ice_nvm_validate_checksum(struct ice_hw *hw);
22 enum ice_status ice_init_fltr_mgmt_struct(struct ice_hw *hw);
23 void ice_cleanup_fltr_mgmt_struct(struct ice_hw *hw);
24 enum ice_status ice_init_hw(struct ice_hw *hw);
25 void ice_deinit_hw(struct ice_hw *hw);
26 enum ice_status ice_check_reset(struct ice_hw *hw);
27 enum ice_status ice_reset(struct ice_hw *hw, enum ice_reset_req req);
29 enum ice_status ice_create_all_ctrlq(struct ice_hw *hw);
30 enum ice_status ice_init_all_ctrlq(struct ice_hw *hw);
31 void ice_shutdown_all_ctrlq(struct ice_hw *hw);
32 void ice_destroy_all_ctrlq(struct ice_hw *hw);
34 ice_clean_rq_elem(struct ice_hw *hw, struct ice_ctl_q_info *cq,
35 struct ice_rq_event_info *e, u16 *pending);
37 ice_get_link_status(struct ice_port_info *pi, bool *link_up);
38 enum ice_status ice_update_link_info(struct ice_port_info *pi);
40 ice_acquire_res(struct ice_hw *hw, enum ice_aq_res_ids res,
41 enum ice_aq_res_access_type access, u32 timeout);
42 void ice_release_res(struct ice_hw *hw, enum ice_aq_res_ids res);
44 ice_alloc_hw_res(struct ice_hw *hw, u16 type, u16 num, bool btm, u16 *res);
46 ice_free_hw_res(struct ice_hw *hw, u16 type, u16 num, u16 *res);
48 ice_aq_alloc_free_res(struct ice_hw *hw, u16 num_entries,
49 struct ice_aqc_alloc_free_res_elem *buf, u16 buf_size,
50 enum ice_adminq_opc opc, struct ice_sq_cd *cd);
52 ice_sq_send_cmd(struct ice_hw *hw, struct ice_ctl_q_info *cq,
53 struct ice_aq_desc *desc, void *buf, u16 buf_size,
54 struct ice_sq_cd *cd);
55 void ice_clear_pxe_mode(struct ice_hw *hw);
57 enum ice_status ice_get_caps(struct ice_hw *hw);
59 void ice_set_safe_mode_caps(struct ice_hw *hw);
61 /* Define a macro that will align a pointer to point to the next memory address
62 * that falls on the given power of 2 (i.e., 2, 4, 8, 16, 32, 64...). For
63 * example, given the variable pointer = 0x1006, then after the following call:
65 * pointer = ICE_ALIGN(pointer, 4)
67 * ... the value of pointer would equal 0x1008, since 0x1008 is the next
68 * address after 0x1006 which is divisible by 4.
70 #define ICE_ALIGN(ptr, align) (((ptr) + ((align) - 1)) & ~((align) - 1))
73 ice_write_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx,
75 enum ice_status ice_clear_rxq_ctx(struct ice_hw *hw, u32 rxq_index);
77 ice_clear_tx_cmpltnq_ctx(struct ice_hw *hw, u32 tx_cmpltnq_index);
79 ice_write_tx_cmpltnq_ctx(struct ice_hw *hw,
80 struct ice_tx_cmpltnq_ctx *tx_cmpltnq_ctx,
81 u32 tx_cmpltnq_index);
83 ice_clear_tx_drbell_q_ctx(struct ice_hw *hw, u32 tx_drbell_q_index);
85 ice_write_tx_drbell_q_ctx(struct ice_hw *hw,
86 struct ice_tx_drbell_q_ctx *tx_drbell_q_ctx,
87 u32 tx_drbell_q_index);
90 ice_aq_get_rss_lut(struct ice_hw *hw, u16 vsi_handle, u8 lut_type, u8 *lut,
93 ice_aq_set_rss_lut(struct ice_hw *hw, u16 vsi_handle, u8 lut_type, u8 *lut,
96 ice_aq_get_rss_key(struct ice_hw *hw, u16 vsi_handle,
97 struct ice_aqc_get_set_rss_keys *keys);
99 ice_aq_set_rss_key(struct ice_hw *hw, u16 vsi_handle,
100 struct ice_aqc_get_set_rss_keys *keys);
102 ice_aq_add_lan_txq(struct ice_hw *hw, u8 count,
103 struct ice_aqc_add_tx_qgrp *qg_list, u16 buf_size,
104 struct ice_sq_cd *cd);
106 ice_aq_move_recfg_lan_txq(struct ice_hw *hw, u8 num_qs, bool is_move,
107 bool is_tc_change, bool subseq_call, bool flush_pipe,
108 u8 timeout, u32 *blocked_cgds,
109 struct ice_aqc_move_txqs_data *buf, u16 buf_size,
110 u8 *txqs_moved, struct ice_sq_cd *cd);
112 bool ice_check_sq_alive(struct ice_hw *hw, struct ice_ctl_q_info *cq);
113 enum ice_status ice_aq_q_shutdown(struct ice_hw *hw, bool unloading);
114 void ice_fill_dflt_direct_cmd_desc(struct ice_aq_desc *desc, u16 opcode);
115 extern const struct ice_ctx_ele ice_tlan_ctx_info[];
117 ice_set_ctx(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info);
119 ice_aq_send_cmd(struct ice_hw *hw, struct ice_aq_desc *desc,
120 void *buf, u16 buf_size, struct ice_sq_cd *cd);
121 enum ice_status ice_aq_get_fw_ver(struct ice_hw *hw, struct ice_sq_cd *cd);
124 ice_aq_send_driver_ver(struct ice_hw *hw, struct ice_driver_ver *dv,
125 struct ice_sq_cd *cd);
127 ice_aq_get_phy_caps(struct ice_port_info *pi, bool qual_mods, u8 report_mode,
128 struct ice_aqc_get_phy_caps_data *caps,
129 struct ice_sq_cd *cd);
131 ice_update_phy_type(u64 *phy_type_low, u64 *phy_type_high,
132 u16 link_speeds_bitmap);
134 ice_aq_manage_mac_write(struct ice_hw *hw, const u8 *mac_addr, u8 flags,
135 struct ice_sq_cd *cd);
137 enum ice_status ice_clear_pf_cfg(struct ice_hw *hw);
139 ice_aq_set_phy_cfg(struct ice_hw *hw, struct ice_port_info *pi,
140 struct ice_aqc_set_phy_cfg_data *cfg, struct ice_sq_cd *cd);
141 bool ice_fw_supports_link_override(struct ice_hw *hw);
143 ice_get_link_default_override(struct ice_link_default_override_tlv *ldo,
144 struct ice_port_info *pi);
146 enum ice_fc_mode ice_caps_to_fc_mode(u8 caps);
147 enum ice_fec_mode ice_caps_to_fec_mode(u8 caps, u8 fec_options);
149 ice_set_fc(struct ice_port_info *pi, u8 *aq_failures,
150 bool ena_auto_link_update);
152 ice_phy_caps_equals_cfg(struct ice_aqc_get_phy_caps_data *caps,
153 struct ice_aqc_set_phy_cfg_data *cfg);
155 ice_copy_phy_caps_to_cfg(struct ice_port_info *pi,
156 struct ice_aqc_get_phy_caps_data *caps,
157 struct ice_aqc_set_phy_cfg_data *cfg);
159 ice_cfg_phy_fec(struct ice_port_info *pi, struct ice_aqc_set_phy_cfg_data *cfg,
160 enum ice_fec_mode fec);
162 ice_aq_set_link_restart_an(struct ice_port_info *pi, bool ena_link,
163 struct ice_sq_cd *cd);
165 ice_aq_set_mac_cfg(struct ice_hw *hw, u16 max_frame_size, struct ice_sq_cd *cd);
167 ice_aq_get_link_info(struct ice_port_info *pi, bool ena_lse,
168 struct ice_link_status *link, struct ice_sq_cd *cd);
170 ice_aq_set_event_mask(struct ice_hw *hw, u8 port_num, u16 mask,
171 struct ice_sq_cd *cd);
173 ice_aq_set_mac_loopback(struct ice_hw *hw, bool ena_lpbk, struct ice_sq_cd *cd);
176 ice_aq_set_port_id_led(struct ice_port_info *pi, bool is_orig_mode,
177 struct ice_sq_cd *cd);
179 ice_aq_sff_eeprom(struct ice_hw *hw, u16 lport, u8 bus_addr,
180 u16 mem_addr, u8 page, u8 set_page, u8 *data, u8 length,
181 bool write, struct ice_sq_cd *cd);
184 ice_get_ctx(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info);
186 ice_dis_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u8 num_queues,
187 u16 *q_handle, u16 *q_ids, u32 *q_teids,
188 enum ice_disq_rst_src rst_src, u16 vmvf_num,
189 struct ice_sq_cd *cd);
191 ice_cfg_vsi_lan(struct ice_port_info *pi, u16 vsi_handle, u16 tc_bitmap,
194 ice_ena_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u16 q_handle,
195 u8 num_qgrps, struct ice_aqc_add_tx_qgrp *buf, u16 buf_size,
196 struct ice_sq_cd *cd);
197 enum ice_status ice_replay_vsi(struct ice_hw *hw, u16 vsi_handle);
198 void ice_replay_post(struct ice_hw *hw);
199 void ice_sched_replay_agg_vsi_preinit(struct ice_hw *hw);
200 void ice_sched_replay_agg(struct ice_hw *hw);
201 enum ice_status ice_sched_replay_tc_node_bw(struct ice_port_info *pi);
202 enum ice_status ice_replay_vsi_agg(struct ice_hw *hw, u16 vsi_handle);
204 ice_sched_replay_q_bw(struct ice_port_info *pi, struct ice_q_ctx *q_ctx);
206 ice_get_lan_q_ctx(struct ice_hw *hw, u16 vsi_handle, u8 tc, u16 q_handle);
208 ice_stat_update40(struct ice_hw *hw, u32 reg, bool prev_stat_loaded,
209 u64 *prev_stat, u64 *cur_stat);
211 ice_stat_update32(struct ice_hw *hw, u32 reg, bool prev_stat_loaded,
212 u64 *prev_stat, u64 *cur_stat);
214 ice_stat_update_repc(struct ice_hw *hw, u16 vsi_handle, bool prev_stat_loaded,
215 struct ice_eth_stats *cur_stats);
216 enum ice_fw_modes ice_get_fw_mode(struct ice_hw *hw);
217 void ice_print_rollback_msg(struct ice_hw *hw);
219 ice_sched_query_elem(struct ice_hw *hw, u32 node_teid,
220 struct ice_aqc_get_elem *buf);
221 #endif /* _ICE_COMMON_H_ */