1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2001-2021 Intel Corporation
10 #include "ice_flex_pipe.h"
11 #include "ice_parser.h"
12 #include "ice_switch.h"
15 #define ICE_SQ_SEND_DELAY_TIME_MS 10
16 #define ICE_SQ_SEND_MAX_EXECUTE 3
25 enum ice_status ice_init_fltr_mgmt_struct(struct ice_hw *hw);
26 void ice_cleanup_fltr_mgmt_struct(struct ice_hw *hw);
27 void ice_set_umac_shared(struct ice_hw *hw);
28 enum ice_status ice_init_hw(struct ice_hw *hw);
29 void ice_deinit_hw(struct ice_hw *hw);
30 enum ice_status ice_check_reset(struct ice_hw *hw);
31 enum ice_status ice_reset(struct ice_hw *hw, enum ice_reset_req req);
33 enum ice_status ice_create_all_ctrlq(struct ice_hw *hw);
34 enum ice_status ice_init_all_ctrlq(struct ice_hw *hw);
35 void ice_shutdown_all_ctrlq(struct ice_hw *hw);
36 void ice_destroy_all_ctrlq(struct ice_hw *hw);
38 ice_clean_rq_elem(struct ice_hw *hw, struct ice_ctl_q_info *cq,
39 struct ice_rq_event_info *e, u16 *pending);
41 ice_get_link_status(struct ice_port_info *pi, bool *link_up);
42 enum ice_status ice_update_link_info(struct ice_port_info *pi);
44 ice_acquire_res(struct ice_hw *hw, enum ice_aq_res_ids res,
45 enum ice_aq_res_access_type access, u32 timeout);
46 void ice_release_res(struct ice_hw *hw, enum ice_aq_res_ids res);
48 ice_alloc_hw_res(struct ice_hw *hw, u16 type, u16 num, bool btm, u16 *res);
50 ice_free_hw_res(struct ice_hw *hw, u16 type, u16 num, u16 *res);
52 ice_aq_alloc_free_res(struct ice_hw *hw, u16 num_entries,
53 struct ice_aqc_alloc_free_res_elem *buf, u16 buf_size,
54 enum ice_adminq_opc opc, struct ice_sq_cd *cd);
56 ice_sq_send_cmd_nolock(struct ice_hw *hw, struct ice_ctl_q_info *cq,
57 struct ice_aq_desc *desc, void *buf, u16 buf_size,
58 struct ice_sq_cd *cd);
60 ice_sq_send_cmd(struct ice_hw *hw, struct ice_ctl_q_info *cq,
61 struct ice_aq_desc *desc, void *buf, u16 buf_size,
62 struct ice_sq_cd *cd);
63 void ice_clear_pxe_mode(struct ice_hw *hw);
65 enum ice_status ice_get_caps(struct ice_hw *hw);
67 void ice_set_safe_mode_caps(struct ice_hw *hw);
70 ice_aq_get_internal_data(struct ice_hw *hw, u8 cluster_id, u16 table_id,
71 u32 start, void *buf, u16 buf_size, u16 *ret_buf_size,
72 u16 *ret_next_table, u32 *ret_next_index,
73 struct ice_sq_cd *cd);
75 /* Define a macro that will align a pointer to point to the next memory address
76 * that falls on the given power of 2 (i.e., 2, 4, 8, 16, 32, 64...). For
77 * example, given the variable pointer = 0x1006, then after the following call:
79 * pointer = ICE_ALIGN(pointer, 4)
81 * ... the value of pointer would equal 0x1008, since 0x1008 is the next
82 * address after 0x1006 which is divisible by 4.
84 #define ICE_ALIGN(ptr, align) (((ptr) + ((align) - 1)) & ~((align) - 1))
87 ice_write_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx,
89 enum ice_status ice_clear_rxq_ctx(struct ice_hw *hw, u32 rxq_index);
91 ice_clear_tx_cmpltnq_ctx(struct ice_hw *hw, u32 tx_cmpltnq_index);
93 ice_write_tx_cmpltnq_ctx(struct ice_hw *hw,
94 struct ice_tx_cmpltnq_ctx *tx_cmpltnq_ctx,
95 u32 tx_cmpltnq_index);
97 ice_clear_tx_drbell_q_ctx(struct ice_hw *hw, u32 tx_drbell_q_index);
99 ice_write_tx_drbell_q_ctx(struct ice_hw *hw,
100 struct ice_tx_drbell_q_ctx *tx_drbell_q_ctx,
101 u32 tx_drbell_q_index);
104 ice_aq_get_rss_lut(struct ice_hw *hw, struct ice_aq_get_set_rss_lut_params *get_params);
106 ice_aq_set_rss_lut(struct ice_hw *hw, struct ice_aq_get_set_rss_lut_params *set_params);
108 ice_aq_get_rss_key(struct ice_hw *hw, u16 vsi_handle,
109 struct ice_aqc_get_set_rss_keys *keys);
111 ice_aq_set_rss_key(struct ice_hw *hw, u16 vsi_handle,
112 struct ice_aqc_get_set_rss_keys *keys);
114 ice_aq_add_lan_txq(struct ice_hw *hw, u8 count,
115 struct ice_aqc_add_tx_qgrp *qg_list, u16 buf_size,
116 struct ice_sq_cd *cd);
118 ice_aq_move_recfg_lan_txq(struct ice_hw *hw, u8 num_qs, bool is_move,
119 bool is_tc_change, bool subseq_call, bool flush_pipe,
120 u8 timeout, u32 *blocked_cgds,
121 struct ice_aqc_move_txqs_data *buf, u16 buf_size,
122 u8 *txqs_moved, struct ice_sq_cd *cd);
124 bool ice_check_sq_alive(struct ice_hw *hw, struct ice_ctl_q_info *cq);
125 enum ice_status ice_aq_q_shutdown(struct ice_hw *hw, bool unloading);
126 void ice_fill_dflt_direct_cmd_desc(struct ice_aq_desc *desc, u16 opcode);
127 extern const struct ice_ctx_ele ice_tlan_ctx_info[];
129 ice_set_ctx(struct ice_hw *hw, u8 *src_ctx, u8 *dest_ctx,
130 const struct ice_ctx_ele *ce_info);
133 ice_aq_send_cmd(struct ice_hw *hw, struct ice_aq_desc *desc,
134 void *buf, u16 buf_size, struct ice_sq_cd *cd);
135 enum ice_status ice_aq_get_fw_ver(struct ice_hw *hw, struct ice_sq_cd *cd);
138 ice_aq_send_driver_ver(struct ice_hw *hw, struct ice_driver_ver *dv,
139 struct ice_sq_cd *cd);
141 ice_aq_set_port_params(struct ice_port_info *pi, u16 bad_frame_vsi,
142 bool save_bad_pac, bool pad_short_pac, bool double_vlan,
143 struct ice_sq_cd *cd);
145 ice_aq_get_phy_caps(struct ice_port_info *pi, bool qual_mods, u8 report_mode,
146 struct ice_aqc_get_phy_caps_data *caps,
147 struct ice_sq_cd *cd);
149 ice_update_phy_type(u64 *phy_type_low, u64 *phy_type_high,
150 u16 link_speeds_bitmap);
152 ice_aq_manage_mac_write(struct ice_hw *hw, const u8 *mac_addr, u8 flags,
153 struct ice_sq_cd *cd);
155 enum ice_status ice_clear_pf_cfg(struct ice_hw *hw);
157 ice_aq_set_phy_cfg(struct ice_hw *hw, struct ice_port_info *pi,
158 struct ice_aqc_set_phy_cfg_data *cfg, struct ice_sq_cd *cd);
159 bool ice_fw_supports_link_override(struct ice_hw *hw);
161 ice_get_link_default_override(struct ice_link_default_override_tlv *ldo,
162 struct ice_port_info *pi);
163 bool ice_is_phy_caps_an_enabled(struct ice_aqc_get_phy_caps_data *caps);
165 enum ice_fc_mode ice_caps_to_fc_mode(u8 caps);
166 enum ice_fec_mode ice_caps_to_fec_mode(u8 caps, u8 fec_options);
168 ice_set_fc(struct ice_port_info *pi, u8 *aq_failures,
169 bool ena_auto_link_update);
171 ice_phy_caps_equals_cfg(struct ice_aqc_get_phy_caps_data *caps,
172 struct ice_aqc_set_phy_cfg_data *cfg);
174 ice_copy_phy_caps_to_cfg(struct ice_port_info *pi,
175 struct ice_aqc_get_phy_caps_data *caps,
176 struct ice_aqc_set_phy_cfg_data *cfg);
178 ice_cfg_phy_fec(struct ice_port_info *pi, struct ice_aqc_set_phy_cfg_data *cfg,
179 enum ice_fec_mode fec);
181 ice_aq_set_link_restart_an(struct ice_port_info *pi, bool ena_link,
182 struct ice_sq_cd *cd);
184 ice_aq_set_mac_cfg(struct ice_hw *hw, u16 max_frame_size, struct ice_sq_cd *cd);
186 ice_aq_get_link_info(struct ice_port_info *pi, bool ena_lse,
187 struct ice_link_status *link, struct ice_sq_cd *cd);
189 ice_aq_set_event_mask(struct ice_hw *hw, u8 port_num, u16 mask,
190 struct ice_sq_cd *cd);
192 ice_aq_set_mac_loopback(struct ice_hw *hw, bool ena_lpbk, struct ice_sq_cd *cd);
195 ice_aq_set_port_id_led(struct ice_port_info *pi, bool is_orig_mode,
196 struct ice_sq_cd *cd);
198 ice_aq_sff_eeprom(struct ice_hw *hw, u16 lport, u8 bus_addr,
199 u16 mem_addr, u8 page, u8 set_page, u8 *data, u8 length,
200 bool write, struct ice_sq_cd *cd);
203 ice_aq_prog_topo_dev_nvm(struct ice_hw *hw,
204 struct ice_aqc_link_topo_params *topo_params,
205 struct ice_sq_cd *cd);
207 ice_aq_read_topo_dev_nvm(struct ice_hw *hw,
208 struct ice_aqc_link_topo_params *topo_params,
209 u32 start_address, u8 *buf, u8 buf_size,
210 struct ice_sq_cd *cd);
213 ice_get_ctx(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info);
215 ice_dis_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u8 num_queues,
216 u16 *q_handle, u16 *q_ids, u32 *q_teids,
217 enum ice_disq_rst_src rst_src, u16 vmvf_num,
218 struct ice_sq_cd *cd);
220 ice_cfg_vsi_lan(struct ice_port_info *pi, u16 vsi_handle, u16 tc_bitmap,
223 ice_ena_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u16 q_handle,
224 u8 num_qgrps, struct ice_aqc_add_tx_qgrp *buf, u16 buf_size,
225 struct ice_sq_cd *cd);
227 ice_replay_pre_init(struct ice_hw *hw, struct ice_switch_info *sw);
228 enum ice_status ice_replay_vsi(struct ice_hw *hw, u16 vsi_handle);
229 void ice_replay_post(struct ice_hw *hw);
231 ice_get_lan_q_ctx(struct ice_hw *hw, u16 vsi_handle, u8 tc, u16 q_handle);
232 enum ice_status ice_sbq_rw_reg_lp(struct ice_hw *hw,
233 struct ice_sbq_msg_input *in, bool lock);
234 void ice_sbq_lock(struct ice_hw *hw);
235 void ice_sbq_unlock(struct ice_hw *hw);
236 enum ice_status ice_sbq_rw_reg(struct ice_hw *hw, struct ice_sbq_msg_input *in);
238 ice_stat_update40(struct ice_hw *hw, u32 reg, bool prev_stat_loaded,
239 u64 *prev_stat, u64 *cur_stat);
241 ice_stat_update32(struct ice_hw *hw, u32 reg, bool prev_stat_loaded,
242 u64 *prev_stat, u64 *cur_stat);
244 ice_stat_update_repc(struct ice_hw *hw, u16 vsi_handle, bool prev_stat_loaded,
245 struct ice_eth_stats *cur_stats);
246 enum ice_fw_modes ice_get_fw_mode(struct ice_hw *hw);
247 void ice_print_rollback_msg(struct ice_hw *hw);
248 bool ice_is_generic_mac(struct ice_hw *hw);
249 bool ice_is_e810(struct ice_hw *hw);
250 bool ice_is_e810t(struct ice_hw *hw);
252 ice_sched_query_elem(struct ice_hw *hw, u32 node_teid,
253 struct ice_aqc_txsched_elem_data *buf);
255 ice_aq_set_driver_param(struct ice_hw *hw, enum ice_aqc_driver_params idx,
256 u32 value, struct ice_sq_cd *cd);
258 ice_aq_get_driver_param(struct ice_hw *hw, enum ice_aqc_driver_params idx,
259 u32 *value, struct ice_sq_cd *cd);
261 ice_aq_set_gpio(struct ice_hw *hw, u16 gpio_ctrl_handle, u8 pin_idx, bool value,
262 struct ice_sq_cd *cd);
264 ice_aq_get_gpio(struct ice_hw *hw, u16 gpio_ctrl_handle, u8 pin_idx,
265 bool *value, struct ice_sq_cd *cd);
266 bool ice_is_100m_speed_supported(struct ice_hw *hw);
268 ice_aq_set_lldp_mib(struct ice_hw *hw, u8 mib_type, void *buf, u16 buf_size,
269 struct ice_sq_cd *cd);
270 bool ice_fw_supports_lldp_fltr_ctrl(struct ice_hw *hw);
272 ice_lldp_fltr_add_remove(struct ice_hw *hw, u16 vsi_num, bool add);
274 ice_aq_read_i2c(struct ice_hw *hw, struct ice_aqc_link_topo_addr topo_addr,
275 u16 bus_addr, __le16 addr, u8 params, u8 *data,
276 struct ice_sq_cd *cd);
278 ice_aq_write_i2c(struct ice_hw *hw, struct ice_aqc_link_topo_addr topo_addr,
279 u16 bus_addr, __le16 addr, u8 params, u8 *data,
280 struct ice_sq_cd *cd);
281 bool ice_fw_supports_report_dflt_cfg(struct ice_hw *hw);
282 #endif /* _ICE_COMMON_H_ */