drivers/net/ice/base/ice_common.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2001-2021 Intel Corporation
   3  */
   4
   5 #ifndef _ICE_COMMON_H_
   6 #define _ICE_COMMON_H_
   7
   8 #include "ice_type.h"
   9 #include "ice_nvm.h"
  10 #include "ice_flex_pipe.h"
  11 #include "ice_switch.h"
  12 #include "ice_fdir.h"
  13
  14 #define ICE_SQ_SEND_DELAY_TIME_MS       10
  15 #define ICE_SQ_SEND_MAX_EXECUTE         3
  16
  17 enum ice_fw_modes {
  18         ICE_FW_MODE_NORMAL,
  19         ICE_FW_MODE_DBG,
  20         ICE_FW_MODE_REC,
  21         ICE_FW_MODE_ROLLBACK
  22 };
  23
  24 enum ice_status ice_init_fltr_mgmt_struct(struct ice_hw *hw);
  25 void ice_cleanup_fltr_mgmt_struct(struct ice_hw *hw);
  26 void ice_set_umac_shared(struct ice_hw *hw);
  27 enum ice_status ice_init_hw(struct ice_hw *hw);
  28 void ice_deinit_hw(struct ice_hw *hw);
  29 enum ice_status ice_check_reset(struct ice_hw *hw);
  30 enum ice_status ice_reset(struct ice_hw *hw, enum ice_reset_req req);
  31
  32 enum ice_status ice_create_all_ctrlq(struct ice_hw *hw);
  33 enum ice_status ice_init_all_ctrlq(struct ice_hw *hw);
  34 void ice_shutdown_all_ctrlq(struct ice_hw *hw);
  35 void ice_destroy_all_ctrlq(struct ice_hw *hw);
  36 enum ice_status
  37 ice_clean_rq_elem(struct ice_hw *hw, struct ice_ctl_q_info *cq,
  38                   struct ice_rq_event_info *e, u16 *pending);
  39 enum ice_status
  40 ice_get_link_status(struct ice_port_info *pi, bool *link_up);
  41 enum ice_status ice_update_link_info(struct ice_port_info *pi);
  42 enum ice_status
  43 ice_acquire_res(struct ice_hw *hw, enum ice_aq_res_ids res,
  44                 enum ice_aq_res_access_type access, u32 timeout);
  45 void ice_release_res(struct ice_hw *hw, enum ice_aq_res_ids res);
  46 enum ice_status
  47 ice_alloc_hw_res(struct ice_hw *hw, u16 type, u16 num, bool btm, u16 *res);
  48 enum ice_status
  49 ice_free_hw_res(struct ice_hw *hw, u16 type, u16 num, u16 *res);
  50 enum ice_status
  51 ice_aq_alloc_free_res(struct ice_hw *hw, u16 num_entries,
  52                       struct ice_aqc_alloc_free_res_elem *buf, u16 buf_size,
  53                       enum ice_adminq_opc opc, struct ice_sq_cd *cd);
  54 enum ice_status
  55 ice_sq_send_cmd_nolock(struct ice_hw *hw, struct ice_ctl_q_info *cq,
  56                        struct ice_aq_desc *desc, void *buf, u16 buf_size,
  57                        struct ice_sq_cd *cd);
  58 enum ice_status
  59 ice_sq_send_cmd(struct ice_hw *hw, struct ice_ctl_q_info *cq,
  60                 struct ice_aq_desc *desc, void *buf, u16 buf_size,
  61                 struct ice_sq_cd *cd);
  62 void ice_clear_pxe_mode(struct ice_hw *hw);
  63
  64 enum ice_status ice_get_caps(struct ice_hw *hw);
  65
  66 void ice_set_safe_mode_caps(struct ice_hw *hw);
  67
  68 enum ice_status
  69 ice_aq_get_internal_data(struct ice_hw *hw, u8 cluster_id, u16 table_id,
  70                          u32 start, void *buf, u16 buf_size, u16 *ret_buf_size,
  71                          u16 *ret_next_table, u32 *ret_next_index,
  72                          struct ice_sq_cd *cd);
  73
  74 /* Define a macro that will align a pointer to point to the next memory address
  75  * that falls on the given power of 2 (i.e., 2, 4, 8, 16, 32, 64...). For
  76  * example, given the variable pointer = 0x1006, then after the following call:
  77  *
  78  *      pointer = ICE_ALIGN(pointer, 4)
  79  *
  80  * ... the value of pointer would equal 0x1008, since 0x1008 is the next
  81  * address after 0x1006 which is divisible by 4.
  82  */
  83 #define ICE_ALIGN(ptr, align)   (((ptr) + ((align) - 1)) & ~((align) - 1))
  84
  85 enum ice_status
  86 ice_write_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx,
  87                   u32 rxq_index);
  88 enum ice_status ice_clear_rxq_ctx(struct ice_hw *hw, u32 rxq_index);
  89 enum ice_status
  90 ice_clear_tx_cmpltnq_ctx(struct ice_hw *hw, u32 tx_cmpltnq_index);
  91 enum ice_status
  92 ice_write_tx_cmpltnq_ctx(struct ice_hw *hw,
  93                          struct ice_tx_cmpltnq_ctx *tx_cmpltnq_ctx,
  94                          u32 tx_cmpltnq_index);
  95 enum ice_status
  96 ice_clear_tx_drbell_q_ctx(struct ice_hw *hw, u32 tx_drbell_q_index);
  97 enum ice_status
  98 ice_write_tx_drbell_q_ctx(struct ice_hw *hw,
  99                           struct ice_tx_drbell_q_ctx *tx_drbell_q_ctx,
 100                           u32 tx_drbell_q_index);
 101
 102 enum ice_status
 103 ice_aq_get_rss_lut(struct ice_hw *hw, struct ice_aq_get_set_rss_lut_params *get_params);
 104 enum ice_status
 105 ice_aq_set_rss_lut(struct ice_hw *hw, struct ice_aq_get_set_rss_lut_params *set_params);
 106 enum ice_status
 107 ice_aq_get_rss_key(struct ice_hw *hw, u16 vsi_handle,
 108                    struct ice_aqc_get_set_rss_keys *keys);
 109 enum ice_status
 110 ice_aq_set_rss_key(struct ice_hw *hw, u16 vsi_handle,
 111                    struct ice_aqc_get_set_rss_keys *keys);
 112 enum ice_status
 113 ice_aq_add_lan_txq(struct ice_hw *hw, u8 count,
 114                    struct ice_aqc_add_tx_qgrp *qg_list, u16 buf_size,
 115                    struct ice_sq_cd *cd);
 116 enum ice_status
 117 ice_aq_move_recfg_lan_txq(struct ice_hw *hw, u8 num_qs, bool is_move,
 118                           bool is_tc_change, bool subseq_call, bool flush_pipe,
 119                           u8 timeout, u32 *blocked_cgds,
 120                           struct ice_aqc_move_txqs_data *buf, u16 buf_size,
 121                           u8 *txqs_moved, struct ice_sq_cd *cd);
 122
 123 bool ice_check_sq_alive(struct ice_hw *hw, struct ice_ctl_q_info *cq);
 124 enum ice_status ice_aq_q_shutdown(struct ice_hw *hw, bool unloading);
 125 void ice_fill_dflt_direct_cmd_desc(struct ice_aq_desc *desc, u16 opcode);
 126 extern const struct ice_ctx_ele ice_tlan_ctx_info[];
 127 enum ice_status
 128 ice_set_ctx(struct ice_hw *hw, u8 *src_ctx, u8 *dest_ctx,
 129             const struct ice_ctx_ele *ce_info);
 130
 131 enum ice_status
 132 ice_aq_send_cmd(struct ice_hw *hw, struct ice_aq_desc *desc,
 133                 void *buf, u16 buf_size, struct ice_sq_cd *cd);
 134 enum ice_status ice_aq_get_fw_ver(struct ice_hw *hw, struct ice_sq_cd *cd);
 135
 136 enum ice_status
 137 ice_aq_send_driver_ver(struct ice_hw *hw, struct ice_driver_ver *dv,
 138                        struct ice_sq_cd *cd);
 139 enum ice_status
 140 ice_aq_set_port_params(struct ice_port_info *pi, u16 bad_frame_vsi,
 141                        bool save_bad_pac, bool pad_short_pac, bool double_vlan,
 142                        struct ice_sq_cd *cd);
 143 enum ice_status
 144 ice_aq_get_phy_caps(struct ice_port_info *pi, bool qual_mods, u8 report_mode,
 145                     struct ice_aqc_get_phy_caps_data *caps,
 146                     struct ice_sq_cd *cd);
 147 void
 148 ice_update_phy_type(u64 *phy_type_low, u64 *phy_type_high,
 149                     u16 link_speeds_bitmap);
 150 enum ice_status
 151 ice_aq_manage_mac_write(struct ice_hw *hw, const u8 *mac_addr, u8 flags,
 152                         struct ice_sq_cd *cd);
 153
 154 enum ice_status ice_clear_pf_cfg(struct ice_hw *hw);
 155 enum ice_status
 156 ice_aq_set_phy_cfg(struct ice_hw *hw, struct ice_port_info *pi,
 157                    struct ice_aqc_set_phy_cfg_data *cfg, struct ice_sq_cd *cd);
 158 bool ice_fw_supports_link_override(struct ice_hw *hw);
 159 enum ice_status
 160 ice_get_link_default_override(struct ice_link_default_override_tlv *ldo,
 161                               struct ice_port_info *pi);
 162 bool ice_is_phy_caps_an_enabled(struct ice_aqc_get_phy_caps_data *caps);
 163
 164 enum ice_fc_mode ice_caps_to_fc_mode(u8 caps);
 165 enum ice_fec_mode ice_caps_to_fec_mode(u8 caps, u8 fec_options);
 166 enum ice_status
 167 ice_set_fc(struct ice_port_info *pi, u8 *aq_failures,
 168            bool ena_auto_link_update);
 169 bool
 170 ice_phy_caps_equals_cfg(struct ice_aqc_get_phy_caps_data *caps,
 171                         struct ice_aqc_set_phy_cfg_data *cfg);
 172 void
 173 ice_copy_phy_caps_to_cfg(struct ice_port_info *pi,
 174                          struct ice_aqc_get_phy_caps_data *caps,
 175                          struct ice_aqc_set_phy_cfg_data *cfg);
 176 enum ice_status
 177 ice_cfg_phy_fec(struct ice_port_info *pi, struct ice_aqc_set_phy_cfg_data *cfg,
 178                 enum ice_fec_mode fec);
 179 enum ice_status
 180 ice_aq_set_link_restart_an(struct ice_port_info *pi, bool ena_link,
 181                            struct ice_sq_cd *cd);
 182 enum ice_status
 183 ice_aq_set_mac_cfg(struct ice_hw *hw, u16 max_frame_size, struct ice_sq_cd *cd);
 184 enum ice_status
 185 ice_aq_get_link_info(struct ice_port_info *pi, bool ena_lse,
 186                      struct ice_link_status *link, struct ice_sq_cd *cd);
 187 enum ice_status
 188 ice_aq_set_event_mask(struct ice_hw *hw, u8 port_num, u16 mask,
 189                       struct ice_sq_cd *cd);
 190 enum ice_status
 191 ice_aq_set_mac_loopback(struct ice_hw *hw, bool ena_lpbk, struct ice_sq_cd *cd);
 192
 193 enum ice_status
 194 ice_aq_set_port_id_led(struct ice_port_info *pi, bool is_orig_mode,
 195                        struct ice_sq_cd *cd);
 196 enum ice_status
 197 ice_aq_sff_eeprom(struct ice_hw *hw, u16 lport, u8 bus_addr,
 198                   u16 mem_addr, u8 page, u8 set_page, u8 *data, u8 length,
 199                   bool write, struct ice_sq_cd *cd);
 200
 201 enum ice_status
 202 ice_aq_prog_topo_dev_nvm(struct ice_hw *hw,
 203                          struct ice_aqc_link_topo_params *topo_params,
 204                          struct ice_sq_cd *cd);
 205 enum ice_status
 206 ice_aq_read_topo_dev_nvm(struct ice_hw *hw,
 207                          struct ice_aqc_link_topo_params *topo_params,
 208                          u32 start_address, u8 *buf, u8 buf_size,
 209                          struct ice_sq_cd *cd);
 210
 211 enum ice_status
 212 ice_get_ctx(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info);
 213 enum ice_status
 214 ice_dis_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u8 num_queues,
 215                 u16 *q_handle, u16 *q_ids, u32 *q_teids,
 216                 enum ice_disq_rst_src rst_src, u16 vmvf_num,
 217                 struct ice_sq_cd *cd);
 218 enum ice_status
 219 ice_cfg_vsi_lan(struct ice_port_info *pi, u16 vsi_handle, u16 tc_bitmap,
 220                 u16 *max_lanqs);
 221 enum ice_status
 222 ice_ena_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u16 q_handle,
 223                 u8 num_qgrps, struct ice_aqc_add_tx_qgrp *buf, u16 buf_size,
 224                 struct ice_sq_cd *cd);
 225 enum ice_status
 226 ice_replay_pre_init(struct ice_hw *hw, struct ice_switch_info *sw);
 227 enum ice_status ice_replay_vsi(struct ice_hw *hw, u16 vsi_handle);
 228 void ice_replay_post(struct ice_hw *hw);
 229 struct ice_q_ctx *
 230 ice_get_lan_q_ctx(struct ice_hw *hw, u16 vsi_handle, u8 tc, u16 q_handle);
 231 enum ice_status ice_sbq_rw_reg_lp(struct ice_hw *hw,
 232                                   struct ice_sbq_msg_input *in, bool lock);
 233 void ice_sbq_lock(struct ice_hw *hw);
 234 void ice_sbq_unlock(struct ice_hw *hw);
 235 enum ice_status ice_sbq_rw_reg(struct ice_hw *hw, struct ice_sbq_msg_input *in);
 236 void
 237 ice_stat_update40(struct ice_hw *hw, u32 reg, bool prev_stat_loaded,
 238                   u64 *prev_stat, u64 *cur_stat);
 239 void
 240 ice_stat_update32(struct ice_hw *hw, u32 reg, bool prev_stat_loaded,
 241                   u64 *prev_stat, u64 *cur_stat);
 242 void
 243 ice_stat_update_repc(struct ice_hw *hw, u16 vsi_handle, bool prev_stat_loaded,
 244                      struct ice_eth_stats *cur_stats);
 245 enum ice_fw_modes ice_get_fw_mode(struct ice_hw *hw);
 246 void ice_print_rollback_msg(struct ice_hw *hw);
 247 bool ice_is_generic_mac(struct ice_hw *hw);
 248 bool ice_is_e810(struct ice_hw *hw);
 249 bool ice_is_e810t(struct ice_hw *hw);
 250 enum ice_status
 251 ice_sched_query_elem(struct ice_hw *hw, u32 node_teid,
 252                      struct ice_aqc_txsched_elem_data *buf);
 253 enum ice_status
 254 ice_aq_set_gpio(struct ice_hw *hw, u16 gpio_ctrl_handle, u8 pin_idx, bool value,
 255                 struct ice_sq_cd *cd);
 256 enum ice_status
 257 ice_aq_get_gpio(struct ice_hw *hw, u16 gpio_ctrl_handle, u8 pin_idx,
 258                 bool *value, struct ice_sq_cd *cd);
 259 bool ice_is_100m_speed_supported(struct ice_hw *hw);
 260 enum ice_status
 261 ice_aq_set_lldp_mib(struct ice_hw *hw, u8 mib_type, void *buf, u16 buf_size,
 262                     struct ice_sq_cd *cd);
 263 bool ice_fw_supports_lldp_fltr_ctrl(struct ice_hw *hw);
 264 enum ice_status
 265 ice_lldp_fltr_add_remove(struct ice_hw *hw, u16 vsi_num, bool add);
 266 enum ice_status
 267 ice_aq_read_i2c(struct ice_hw *hw, struct ice_aqc_link_topo_addr topo_addr,
 268                 u16 bus_addr, __le16 addr, u8 params, u8 *data,
 269                 struct ice_sq_cd *cd);
 270 enum ice_status
 271 ice_aq_write_i2c(struct ice_hw *hw, struct ice_aqc_link_topo_addr topo_addr,
 272                  u16 bus_addr, __le16 addr, u8 params, u8 *data,
 273                  struct ice_sq_cd *cd);
 274 bool ice_fw_supports_report_dflt_cfg(struct ice_hw *hw);
 275 #endif /* _ICE_COMMON_H_ */