drivers/net/ice/base/ice_common.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2001-2021 Intel Corporation
   3  */
   4
   5 #ifndef _ICE_COMMON_H_
   6 #define _ICE_COMMON_H_
   7
   8 #include "ice_type.h"
   9 #include "ice_nvm.h"
  10 #include "ice_flex_pipe.h"
  11 #include "ice_switch.h"
  12 #include "ice_fdir.h"
  13
  14 #define ICE_SQ_SEND_DELAY_TIME_MS       10
  15 #define ICE_SQ_SEND_MAX_EXECUTE         3
  16
  17 enum ice_fw_modes {
  18         ICE_FW_MODE_NORMAL,
  19         ICE_FW_MODE_DBG,
  20         ICE_FW_MODE_REC,
  21         ICE_FW_MODE_ROLLBACK
  22 };
  23
  24 enum ice_status ice_init_fltr_mgmt_struct(struct ice_hw *hw);
  25 void ice_cleanup_fltr_mgmt_struct(struct ice_hw *hw);
  26 enum ice_status ice_init_hw(struct ice_hw *hw);
  27 void ice_deinit_hw(struct ice_hw *hw);
  28 enum ice_status ice_check_reset(struct ice_hw *hw);
  29 enum ice_status ice_reset(struct ice_hw *hw, enum ice_reset_req req);
  30
  31 enum ice_status ice_create_all_ctrlq(struct ice_hw *hw);
  32 enum ice_status ice_init_all_ctrlq(struct ice_hw *hw);
  33 void ice_shutdown_all_ctrlq(struct ice_hw *hw);
  34 void ice_destroy_all_ctrlq(struct ice_hw *hw);
  35 enum ice_status
  36 ice_clean_rq_elem(struct ice_hw *hw, struct ice_ctl_q_info *cq,
  37                   struct ice_rq_event_info *e, u16 *pending);
  38 enum ice_status
  39 ice_get_link_status(struct ice_port_info *pi, bool *link_up);
  40 enum ice_status ice_update_link_info(struct ice_port_info *pi);
  41 enum ice_status
  42 ice_acquire_res(struct ice_hw *hw, enum ice_aq_res_ids res,
  43                 enum ice_aq_res_access_type access, u32 timeout);
  44 void ice_release_res(struct ice_hw *hw, enum ice_aq_res_ids res);
  45 enum ice_status
  46 ice_alloc_hw_res(struct ice_hw *hw, u16 type, u16 num, bool btm, u16 *res);
  47 enum ice_status
  48 ice_free_hw_res(struct ice_hw *hw, u16 type, u16 num, u16 *res);
  49 enum ice_status
  50 ice_aq_alloc_free_res(struct ice_hw *hw, u16 num_entries,
  51                       struct ice_aqc_alloc_free_res_elem *buf, u16 buf_size,
  52                       enum ice_adminq_opc opc, struct ice_sq_cd *cd);
  53 enum ice_status
  54 ice_sq_send_cmd_nolock(struct ice_hw *hw, struct ice_ctl_q_info *cq,
  55                        struct ice_aq_desc *desc, void *buf, u16 buf_size,
  56                        struct ice_sq_cd *cd);
  57 enum ice_status
  58 ice_sq_send_cmd(struct ice_hw *hw, struct ice_ctl_q_info *cq,
  59                 struct ice_aq_desc *desc, void *buf, u16 buf_size,
  60                 struct ice_sq_cd *cd);
  61 void ice_clear_pxe_mode(struct ice_hw *hw);
  62
  63 enum ice_status ice_get_caps(struct ice_hw *hw);
  64
  65 void ice_set_safe_mode_caps(struct ice_hw *hw);
  66
  67 enum ice_status
  68 ice_aq_get_internal_data(struct ice_hw *hw, u8 cluster_id, u16 table_id,
  69                          u32 start, void *buf, u16 buf_size, u16 *ret_buf_size,
  70                          u16 *ret_next_table, u32 *ret_next_index,
  71                          struct ice_sq_cd *cd);
  72
  73 /* Define a macro that will align a pointer to point to the next memory address
  74  * that falls on the given power of 2 (i.e., 2, 4, 8, 16, 32, 64...). For
  75  * example, given the variable pointer = 0x1006, then after the following call:
  76  *
  77  *      pointer = ICE_ALIGN(pointer, 4)
  78  *
  79  * ... the value of pointer would equal 0x1008, since 0x1008 is the next
  80  * address after 0x1006 which is divisible by 4.
  81  */
  82 #define ICE_ALIGN(ptr, align)   (((ptr) + ((align) - 1)) & ~((align) - 1))
  83
  84 enum ice_status
  85 ice_write_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx,
  86                   u32 rxq_index);
  87 enum ice_status ice_clear_rxq_ctx(struct ice_hw *hw, u32 rxq_index);
  88 enum ice_status
  89 ice_clear_tx_cmpltnq_ctx(struct ice_hw *hw, u32 tx_cmpltnq_index);
  90 enum ice_status
  91 ice_write_tx_cmpltnq_ctx(struct ice_hw *hw,
  92                          struct ice_tx_cmpltnq_ctx *tx_cmpltnq_ctx,
  93                          u32 tx_cmpltnq_index);
  94 enum ice_status
  95 ice_clear_tx_drbell_q_ctx(struct ice_hw *hw, u32 tx_drbell_q_index);
  96 enum ice_status
  97 ice_write_tx_drbell_q_ctx(struct ice_hw *hw,
  98                           struct ice_tx_drbell_q_ctx *tx_drbell_q_ctx,
  99                           u32 tx_drbell_q_index);
 100
 101 enum ice_status
 102 ice_aq_get_rss_lut(struct ice_hw *hw, struct ice_aq_get_set_rss_lut_params *get_params);
 103 enum ice_status
 104 ice_aq_set_rss_lut(struct ice_hw *hw, struct ice_aq_get_set_rss_lut_params *set_params);
 105 enum ice_status
 106 ice_aq_get_rss_key(struct ice_hw *hw, u16 vsi_handle,
 107                    struct ice_aqc_get_set_rss_keys *keys);
 108 enum ice_status
 109 ice_aq_set_rss_key(struct ice_hw *hw, u16 vsi_handle,
 110                    struct ice_aqc_get_set_rss_keys *keys);
 111 enum ice_status
 112 ice_aq_add_lan_txq(struct ice_hw *hw, u8 count,
 113                    struct ice_aqc_add_tx_qgrp *qg_list, u16 buf_size,
 114                    struct ice_sq_cd *cd);
 115 enum ice_status
 116 ice_aq_move_recfg_lan_txq(struct ice_hw *hw, u8 num_qs, bool is_move,
 117                           bool is_tc_change, bool subseq_call, bool flush_pipe,
 118                           u8 timeout, u32 *blocked_cgds,
 119                           struct ice_aqc_move_txqs_data *buf, u16 buf_size,
 120                           u8 *txqs_moved, struct ice_sq_cd *cd);
 121
 122 bool ice_check_sq_alive(struct ice_hw *hw, struct ice_ctl_q_info *cq);
 123 enum ice_status ice_aq_q_shutdown(struct ice_hw *hw, bool unloading);
 124 void ice_fill_dflt_direct_cmd_desc(struct ice_aq_desc *desc, u16 opcode);
 125 extern const struct ice_ctx_ele ice_tlan_ctx_info[];
 126 enum ice_status
 127 ice_set_ctx(struct ice_hw *hw, u8 *src_ctx, u8 *dest_ctx,
 128             const struct ice_ctx_ele *ce_info);
 129
 130 enum ice_status
 131 ice_aq_send_cmd(struct ice_hw *hw, struct ice_aq_desc *desc,
 132                 void *buf, u16 buf_size, struct ice_sq_cd *cd);
 133 enum ice_status ice_aq_get_fw_ver(struct ice_hw *hw, struct ice_sq_cd *cd);
 134
 135 enum ice_status
 136 ice_aq_send_driver_ver(struct ice_hw *hw, struct ice_driver_ver *dv,
 137                        struct ice_sq_cd *cd);
 138 enum ice_status
 139 ice_aq_set_port_params(struct ice_port_info *pi, u16 bad_frame_vsi,
 140                        bool save_bad_pac, bool pad_short_pac, bool double_vlan,
 141                        struct ice_sq_cd *cd);
 142 enum ice_status
 143 ice_aq_get_phy_caps(struct ice_port_info *pi, bool qual_mods, u8 report_mode,
 144                     struct ice_aqc_get_phy_caps_data *caps,
 145                     struct ice_sq_cd *cd);
 146 void
 147 ice_update_phy_type(u64 *phy_type_low, u64 *phy_type_high,
 148                     u16 link_speeds_bitmap);
 149 enum ice_status
 150 ice_aq_manage_mac_write(struct ice_hw *hw, const u8 *mac_addr, u8 flags,
 151                         struct ice_sq_cd *cd);
 152
 153 enum ice_status ice_clear_pf_cfg(struct ice_hw *hw);
 154 enum ice_status
 155 ice_aq_set_phy_cfg(struct ice_hw *hw, struct ice_port_info *pi,
 156                    struct ice_aqc_set_phy_cfg_data *cfg, struct ice_sq_cd *cd);
 157 bool ice_fw_supports_link_override(struct ice_hw *hw);
 158 enum ice_status
 159 ice_get_link_default_override(struct ice_link_default_override_tlv *ldo,
 160                               struct ice_port_info *pi);
 161 bool ice_is_phy_caps_an_enabled(struct ice_aqc_get_phy_caps_data *caps);
 162
 163 enum ice_fc_mode ice_caps_to_fc_mode(u8 caps);
 164 enum ice_fec_mode ice_caps_to_fec_mode(u8 caps, u8 fec_options);
 165 enum ice_status
 166 ice_set_fc(struct ice_port_info *pi, u8 *aq_failures,
 167            bool ena_auto_link_update);
 168 bool
 169 ice_phy_caps_equals_cfg(struct ice_aqc_get_phy_caps_data *caps,
 170                         struct ice_aqc_set_phy_cfg_data *cfg);
 171 void
 172 ice_copy_phy_caps_to_cfg(struct ice_port_info *pi,
 173                          struct ice_aqc_get_phy_caps_data *caps,
 174                          struct ice_aqc_set_phy_cfg_data *cfg);
 175 enum ice_status
 176 ice_cfg_phy_fec(struct ice_port_info *pi, struct ice_aqc_set_phy_cfg_data *cfg,
 177                 enum ice_fec_mode fec);
 178 enum ice_status
 179 ice_aq_set_link_restart_an(struct ice_port_info *pi, bool ena_link,
 180                            struct ice_sq_cd *cd);
 181 enum ice_status
 182 ice_aq_set_mac_cfg(struct ice_hw *hw, u16 max_frame_size, struct ice_sq_cd *cd);
 183 enum ice_status
 184 ice_aq_get_link_info(struct ice_port_info *pi, bool ena_lse,
 185                      struct ice_link_status *link, struct ice_sq_cd *cd);
 186 enum ice_status
 187 ice_aq_set_event_mask(struct ice_hw *hw, u8 port_num, u16 mask,
 188                       struct ice_sq_cd *cd);
 189 enum ice_status
 190 ice_aq_set_mac_loopback(struct ice_hw *hw, bool ena_lpbk, struct ice_sq_cd *cd);
 191
 192 enum ice_status
 193 ice_aq_set_port_id_led(struct ice_port_info *pi, bool is_orig_mode,
 194                        struct ice_sq_cd *cd);
 195 enum ice_status
 196 ice_aq_sff_eeprom(struct ice_hw *hw, u16 lport, u8 bus_addr,
 197                   u16 mem_addr, u8 page, u8 set_page, u8 *data, u8 length,
 198                   bool write, struct ice_sq_cd *cd);
 199
 200 enum ice_status
 201 ice_aq_prog_topo_dev_nvm(struct ice_hw *hw,
 202                          struct ice_aqc_link_topo_params *topo_params,
 203                          struct ice_sq_cd *cd);
 204 enum ice_status
 205 ice_aq_read_topo_dev_nvm(struct ice_hw *hw,
 206                          struct ice_aqc_link_topo_params *topo_params,
 207                          u32 start_address, u8 *buf, u8 buf_size,
 208                          struct ice_sq_cd *cd);
 209
 210 enum ice_status
 211 ice_get_ctx(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info);
 212 enum ice_status
 213 ice_dis_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u8 num_queues,
 214                 u16 *q_handle, u16 *q_ids, u32 *q_teids,
 215                 enum ice_disq_rst_src rst_src, u16 vmvf_num,
 216                 struct ice_sq_cd *cd);
 217 enum ice_status
 218 ice_cfg_vsi_lan(struct ice_port_info *pi, u16 vsi_handle, u16 tc_bitmap,
 219                 u16 *max_lanqs);
 220 enum ice_status
 221 ice_ena_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u16 q_handle,
 222                 u8 num_qgrps, struct ice_aqc_add_tx_qgrp *buf, u16 buf_size,
 223                 struct ice_sq_cd *cd);
 224 enum ice_status
 225 ice_replay_pre_init(struct ice_hw *hw, struct ice_switch_info *sw);
 226 enum ice_status ice_replay_vsi(struct ice_hw *hw, u16 vsi_handle);
 227 void ice_replay_post(struct ice_hw *hw);
 228 struct ice_q_ctx *
 229 ice_get_lan_q_ctx(struct ice_hw *hw, u16 vsi_handle, u8 tc, u16 q_handle);
 230 enum ice_status ice_sbq_rw_reg_lp(struct ice_hw *hw,
 231                                   struct ice_sbq_msg_input *in, bool lock);
 232 void ice_sbq_lock(struct ice_hw *hw);
 233 void ice_sbq_unlock(struct ice_hw *hw);
 234 enum ice_status ice_sbq_rw_reg(struct ice_hw *hw, struct ice_sbq_msg_input *in);
 235 void
 236 ice_stat_update40(struct ice_hw *hw, u32 reg, bool prev_stat_loaded,
 237                   u64 *prev_stat, u64 *cur_stat);
 238 void
 239 ice_stat_update32(struct ice_hw *hw, u32 reg, bool prev_stat_loaded,
 240                   u64 *prev_stat, u64 *cur_stat);
 241 void
 242 ice_stat_update_repc(struct ice_hw *hw, u16 vsi_handle, bool prev_stat_loaded,
 243                      struct ice_eth_stats *cur_stats);
 244 enum ice_fw_modes ice_get_fw_mode(struct ice_hw *hw);
 245 void ice_print_rollback_msg(struct ice_hw *hw);
 246 bool ice_is_generic_mac(struct ice_hw *hw);
 247 bool ice_is_e810(struct ice_hw *hw);
 248 bool ice_is_e810t(struct ice_hw *hw);
 249 enum ice_status
 250 ice_sched_query_elem(struct ice_hw *hw, u32 node_teid,
 251                      struct ice_aqc_txsched_elem_data *buf);
 252 enum ice_status
 253 ice_aq_set_gpio(struct ice_hw *hw, u16 gpio_ctrl_handle, u8 pin_idx, bool value,
 254                 struct ice_sq_cd *cd);
 255 enum ice_status
 256 ice_aq_get_gpio(struct ice_hw *hw, u16 gpio_ctrl_handle, u8 pin_idx,
 257                 bool *value, struct ice_sq_cd *cd);
 258 enum ice_status
 259 ice_aq_set_lldp_mib(struct ice_hw *hw, u8 mib_type, void *buf, u16 buf_size,
 260                     struct ice_sq_cd *cd);
 261 bool ice_fw_supports_lldp_fltr_ctrl(struct ice_hw *hw);
 262 enum ice_status
 263 ice_lldp_fltr_add_remove(struct ice_hw *hw, u16 vsi_num, bool add);
 264 enum ice_status
 265 ice_aq_read_i2c(struct ice_hw *hw, struct ice_aqc_link_topo_addr topo_addr,
 266                 u16 bus_addr, __le16 addr, u8 params, u8 *data,
 267                 struct ice_sq_cd *cd);
 268 enum ice_status
 269 ice_aq_write_i2c(struct ice_hw *hw, struct ice_aqc_link_topo_addr topo_addr,
 270                  u16 bus_addr, __le16 addr, u8 params, u8 *data,
 271                  struct ice_sq_cd *cd);
 272 bool ice_fw_supports_report_dflt_cfg(struct ice_hw *hw);
 273 #endif /* _ICE_COMMON_H_ */