1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2001-2021 Intel Corporation
5 #include "ice_common.h"
7 #define ICE_CQ_INIT_REGS(qinfo, prefix) \
9 (qinfo)->sq.head = prefix##_ATQH; \
10 (qinfo)->sq.tail = prefix##_ATQT; \
11 (qinfo)->sq.len = prefix##_ATQLEN; \
12 (qinfo)->sq.bah = prefix##_ATQBAH; \
13 (qinfo)->sq.bal = prefix##_ATQBAL; \
14 (qinfo)->sq.len_mask = prefix##_ATQLEN_ATQLEN_M; \
15 (qinfo)->sq.len_ena_mask = prefix##_ATQLEN_ATQENABLE_M; \
16 (qinfo)->sq.len_crit_mask = prefix##_ATQLEN_ATQCRIT_M; \
17 (qinfo)->sq.head_mask = prefix##_ATQH_ATQH_M; \
18 (qinfo)->rq.head = prefix##_ARQH; \
19 (qinfo)->rq.tail = prefix##_ARQT; \
20 (qinfo)->rq.len = prefix##_ARQLEN; \
21 (qinfo)->rq.bah = prefix##_ARQBAH; \
22 (qinfo)->rq.bal = prefix##_ARQBAL; \
23 (qinfo)->rq.len_mask = prefix##_ARQLEN_ARQLEN_M; \
24 (qinfo)->rq.len_ena_mask = prefix##_ARQLEN_ARQENABLE_M; \
25 (qinfo)->rq.len_crit_mask = prefix##_ARQLEN_ARQCRIT_M; \
26 (qinfo)->rq.head_mask = prefix##_ARQH_ARQH_M; \
30 * ice_adminq_init_regs - Initialize AdminQ registers
31 * @hw: pointer to the hardware structure
33 * This assumes the alloc_sq and alloc_rq functions have already been called
35 static void ice_adminq_init_regs(struct ice_hw *hw)
37 struct ice_ctl_q_info *cq = &hw->adminq;
39 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
41 ICE_CQ_INIT_REGS(cq, PF_FW);
45 * ice_mailbox_init_regs - Initialize Mailbox registers
46 * @hw: pointer to the hardware structure
48 * This assumes the alloc_sq and alloc_rq functions have already been called
50 static void ice_mailbox_init_regs(struct ice_hw *hw)
52 struct ice_ctl_q_info *cq = &hw->mailboxq;
54 ICE_CQ_INIT_REGS(cq, PF_MBX);
58 * ice_sb_init_regs - Initialize Sideband registers
59 * @hw: pointer to the hardware structure
61 * This assumes the alloc_sq and alloc_rq functions have already been called
63 static void ice_sb_init_regs(struct ice_hw *hw)
65 struct ice_ctl_q_info *cq = &hw->sbq;
67 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
69 ICE_CQ_INIT_REGS(cq, PF_SB);
74 * @hw: pointer to the HW struct
75 * @cq: pointer to the specific Control queue
77 * Returns true if Queue is enabled else false.
79 bool ice_check_sq_alive(struct ice_hw *hw, struct ice_ctl_q_info *cq)
81 /* check both queue-length and queue-enable fields */
82 if (cq->sq.len && cq->sq.len_mask && cq->sq.len_ena_mask)
83 return (rd32(hw, cq->sq.len) & (cq->sq.len_mask |
84 cq->sq.len_ena_mask)) ==
85 (cq->num_sq_entries | cq->sq.len_ena_mask);
91 * ice_alloc_ctrlq_sq_ring - Allocate Control Transmit Queue (ATQ) rings
92 * @hw: pointer to the hardware structure
93 * @cq: pointer to the specific Control queue
95 static enum ice_status
96 ice_alloc_ctrlq_sq_ring(struct ice_hw *hw, struct ice_ctl_q_info *cq)
98 size_t size = cq->num_sq_entries * sizeof(struct ice_aq_desc);
100 cq->sq.desc_buf.va = ice_alloc_dma_mem(hw, &cq->sq.desc_buf, size);
101 if (!cq->sq.desc_buf.va)
102 return ICE_ERR_NO_MEMORY;
104 cq->sq.cmd_buf = ice_calloc(hw, cq->num_sq_entries,
105 sizeof(struct ice_sq_cd));
106 if (!cq->sq.cmd_buf) {
107 ice_free_dma_mem(hw, &cq->sq.desc_buf);
108 return ICE_ERR_NO_MEMORY;
115 * ice_alloc_ctrlq_rq_ring - Allocate Control Receive Queue (ARQ) rings
116 * @hw: pointer to the hardware structure
117 * @cq: pointer to the specific Control queue
119 static enum ice_status
120 ice_alloc_ctrlq_rq_ring(struct ice_hw *hw, struct ice_ctl_q_info *cq)
122 size_t size = cq->num_rq_entries * sizeof(struct ice_aq_desc);
124 cq->rq.desc_buf.va = ice_alloc_dma_mem(hw, &cq->rq.desc_buf, size);
125 if (!cq->rq.desc_buf.va)
126 return ICE_ERR_NO_MEMORY;
131 * ice_free_cq_ring - Free control queue ring
132 * @hw: pointer to the hardware structure
133 * @ring: pointer to the specific control queue ring
135 * This assumes the posted buffers have already been cleaned
138 static void ice_free_cq_ring(struct ice_hw *hw, struct ice_ctl_q_ring *ring)
140 ice_free_dma_mem(hw, &ring->desc_buf);
144 * ice_alloc_rq_bufs - Allocate pre-posted buffers for the ARQ
145 * @hw: pointer to the hardware structure
146 * @cq: pointer to the specific Control queue
148 static enum ice_status
149 ice_alloc_rq_bufs(struct ice_hw *hw, struct ice_ctl_q_info *cq)
153 /* We'll be allocating the buffer info memory first, then we can
154 * allocate the mapped buffers for the event processing
156 cq->rq.dma_head = ice_calloc(hw, cq->num_rq_entries,
157 sizeof(cq->rq.desc_buf));
158 if (!cq->rq.dma_head)
159 return ICE_ERR_NO_MEMORY;
160 cq->rq.r.rq_bi = (struct ice_dma_mem *)cq->rq.dma_head;
162 /* allocate the mapped buffers */
163 for (i = 0; i < cq->num_rq_entries; i++) {
164 struct ice_aq_desc *desc;
165 struct ice_dma_mem *bi;
167 bi = &cq->rq.r.rq_bi[i];
168 bi->va = ice_alloc_dma_mem(hw, bi, cq->rq_buf_size);
170 goto unwind_alloc_rq_bufs;
172 /* now configure the descriptors for use */
173 desc = ICE_CTL_Q_DESC(cq->rq, i);
175 desc->flags = CPU_TO_LE16(ICE_AQ_FLAG_BUF);
176 if (cq->rq_buf_size > ICE_AQ_LG_BUF)
177 desc->flags |= CPU_TO_LE16(ICE_AQ_FLAG_LB);
179 /* This is in accordance with Admin queue design, there is no
180 * register for buffer size configuration
182 desc->datalen = CPU_TO_LE16(bi->size);
184 desc->cookie_high = 0;
185 desc->cookie_low = 0;
186 desc->params.generic.addr_high =
187 CPU_TO_LE32(ICE_HI_DWORD(bi->pa));
188 desc->params.generic.addr_low =
189 CPU_TO_LE32(ICE_LO_DWORD(bi->pa));
190 desc->params.generic.param0 = 0;
191 desc->params.generic.param1 = 0;
195 unwind_alloc_rq_bufs:
196 /* don't try to free the one that failed... */
199 ice_free_dma_mem(hw, &cq->rq.r.rq_bi[i]);
200 cq->rq.r.rq_bi = NULL;
201 ice_free(hw, cq->rq.dma_head);
202 cq->rq.dma_head = NULL;
204 return ICE_ERR_NO_MEMORY;
208 * ice_alloc_sq_bufs - Allocate empty buffer structs for the ATQ
209 * @hw: pointer to the hardware structure
210 * @cq: pointer to the specific Control queue
212 static enum ice_status
213 ice_alloc_sq_bufs(struct ice_hw *hw, struct ice_ctl_q_info *cq)
217 /* No mapped memory needed yet, just the buffer info structures */
218 cq->sq.dma_head = ice_calloc(hw, cq->num_sq_entries,
219 sizeof(cq->sq.desc_buf));
220 if (!cq->sq.dma_head)
221 return ICE_ERR_NO_MEMORY;
222 cq->sq.r.sq_bi = (struct ice_dma_mem *)cq->sq.dma_head;
224 /* allocate the mapped buffers */
225 for (i = 0; i < cq->num_sq_entries; i++) {
226 struct ice_dma_mem *bi;
228 bi = &cq->sq.r.sq_bi[i];
229 bi->va = ice_alloc_dma_mem(hw, bi, cq->sq_buf_size);
231 goto unwind_alloc_sq_bufs;
235 unwind_alloc_sq_bufs:
236 /* don't try to free the one that failed... */
239 ice_free_dma_mem(hw, &cq->sq.r.sq_bi[i]);
240 cq->sq.r.sq_bi = NULL;
241 ice_free(hw, cq->sq.dma_head);
242 cq->sq.dma_head = NULL;
244 return ICE_ERR_NO_MEMORY;
247 static enum ice_status
248 ice_cfg_cq_regs(struct ice_hw *hw, struct ice_ctl_q_ring *ring, u16 num_entries)
250 /* Clear Head and Tail */
251 wr32(hw, ring->head, 0);
252 wr32(hw, ring->tail, 0);
254 /* set starting point */
255 wr32(hw, ring->len, (num_entries | ring->len_ena_mask));
256 wr32(hw, ring->bal, ICE_LO_DWORD(ring->desc_buf.pa));
257 wr32(hw, ring->bah, ICE_HI_DWORD(ring->desc_buf.pa));
259 /* Check one register to verify that config was applied */
260 if (rd32(hw, ring->bal) != ICE_LO_DWORD(ring->desc_buf.pa))
261 return ICE_ERR_AQ_ERROR;
267 * ice_cfg_sq_regs - configure Control ATQ registers
268 * @hw: pointer to the hardware structure
269 * @cq: pointer to the specific Control queue
271 * Configure base address and length registers for the transmit queue
273 static enum ice_status
274 ice_cfg_sq_regs(struct ice_hw *hw, struct ice_ctl_q_info *cq)
276 return ice_cfg_cq_regs(hw, &cq->sq, cq->num_sq_entries);
280 * ice_cfg_rq_regs - configure Control ARQ register
281 * @hw: pointer to the hardware structure
282 * @cq: pointer to the specific Control queue
284 * Configure base address and length registers for the receive (event queue)
286 static enum ice_status
287 ice_cfg_rq_regs(struct ice_hw *hw, struct ice_ctl_q_info *cq)
289 enum ice_status status;
291 status = ice_cfg_cq_regs(hw, &cq->rq, cq->num_rq_entries);
295 /* Update tail in the HW to post pre-allocated buffers */
296 wr32(hw, cq->rq.tail, (u32)(cq->num_rq_entries - 1));
301 #define ICE_FREE_CQ_BUFS(hw, qi, ring) \
303 /* free descriptors */ \
304 if ((qi)->ring.r.ring##_bi) { \
307 for (i = 0; i < (qi)->num_##ring##_entries; i++) \
308 if ((qi)->ring.r.ring##_bi[i].pa) \
309 ice_free_dma_mem((hw), \
310 &(qi)->ring.r.ring##_bi[i]); \
312 /* free the buffer info list */ \
313 if ((qi)->ring.cmd_buf) \
314 ice_free(hw, (qi)->ring.cmd_buf); \
315 /* free DMA head */ \
316 ice_free(hw, (qi)->ring.dma_head); \
320 * ice_init_sq - main initialization routine for Control ATQ
321 * @hw: pointer to the hardware structure
322 * @cq: pointer to the specific Control queue
324 * This is the main initialization routine for the Control Send Queue
325 * Prior to calling this function, the driver *MUST* set the following fields
326 * in the cq->structure:
327 * - cq->num_sq_entries
330 * Do *NOT* hold the lock when calling this as the memory allocation routines
331 * called are not going to be atomic context safe
333 static enum ice_status ice_init_sq(struct ice_hw *hw, struct ice_ctl_q_info *cq)
335 enum ice_status ret_code;
337 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
339 if (cq->sq.count > 0) {
340 /* queue already initialized */
341 ret_code = ICE_ERR_NOT_READY;
342 goto init_ctrlq_exit;
345 /* verify input for valid configuration */
346 if (!cq->num_sq_entries || !cq->sq_buf_size) {
347 ret_code = ICE_ERR_CFG;
348 goto init_ctrlq_exit;
351 cq->sq.next_to_use = 0;
352 cq->sq.next_to_clean = 0;
354 /* allocate the ring memory */
355 ret_code = ice_alloc_ctrlq_sq_ring(hw, cq);
357 goto init_ctrlq_exit;
359 /* allocate buffers in the rings */
360 ret_code = ice_alloc_sq_bufs(hw, cq);
362 goto init_ctrlq_free_rings;
364 /* initialize base registers */
365 ret_code = ice_cfg_sq_regs(hw, cq);
367 goto init_ctrlq_free_rings;
370 cq->sq.count = cq->num_sq_entries;
371 goto init_ctrlq_exit;
373 init_ctrlq_free_rings:
374 ICE_FREE_CQ_BUFS(hw, cq, sq);
375 ice_free_cq_ring(hw, &cq->sq);
382 * ice_init_rq - initialize ARQ
383 * @hw: pointer to the hardware structure
384 * @cq: pointer to the specific Control queue
386 * The main initialization routine for the Admin Receive (Event) Queue.
387 * Prior to calling this function, the driver *MUST* set the following fields
388 * in the cq->structure:
389 * - cq->num_rq_entries
392 * Do *NOT* hold the lock when calling this as the memory allocation routines
393 * called are not going to be atomic context safe
395 static enum ice_status ice_init_rq(struct ice_hw *hw, struct ice_ctl_q_info *cq)
397 enum ice_status ret_code;
399 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
401 if (cq->rq.count > 0) {
402 /* queue already initialized */
403 ret_code = ICE_ERR_NOT_READY;
404 goto init_ctrlq_exit;
407 /* verify input for valid configuration */
408 if (!cq->num_rq_entries || !cq->rq_buf_size) {
409 ret_code = ICE_ERR_CFG;
410 goto init_ctrlq_exit;
413 cq->rq.next_to_use = 0;
414 cq->rq.next_to_clean = 0;
416 /* allocate the ring memory */
417 ret_code = ice_alloc_ctrlq_rq_ring(hw, cq);
419 goto init_ctrlq_exit;
421 /* allocate buffers in the rings */
422 ret_code = ice_alloc_rq_bufs(hw, cq);
424 goto init_ctrlq_free_rings;
426 /* initialize base registers */
427 ret_code = ice_cfg_rq_regs(hw, cq);
429 goto init_ctrlq_free_rings;
432 cq->rq.count = cq->num_rq_entries;
433 goto init_ctrlq_exit;
435 init_ctrlq_free_rings:
436 ICE_FREE_CQ_BUFS(hw, cq, rq);
437 ice_free_cq_ring(hw, &cq->rq);
444 * ice_shutdown_sq - shutdown the Control ATQ
445 * @hw: pointer to the hardware structure
446 * @cq: pointer to the specific Control queue
448 * The main shutdown routine for the Control Transmit Queue
450 static enum ice_status
451 ice_shutdown_sq(struct ice_hw *hw, struct ice_ctl_q_info *cq)
453 enum ice_status ret_code = ICE_SUCCESS;
455 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
457 ice_acquire_lock(&cq->sq_lock);
460 ret_code = ICE_ERR_NOT_READY;
461 goto shutdown_sq_out;
464 /* Stop firmware AdminQ processing */
465 wr32(hw, cq->sq.head, 0);
466 wr32(hw, cq->sq.tail, 0);
467 wr32(hw, cq->sq.len, 0);
468 wr32(hw, cq->sq.bal, 0);
469 wr32(hw, cq->sq.bah, 0);
471 cq->sq.count = 0; /* to indicate uninitialized queue */
473 /* free ring buffers and the ring itself */
474 ICE_FREE_CQ_BUFS(hw, cq, sq);
475 ice_free_cq_ring(hw, &cq->sq);
478 ice_release_lock(&cq->sq_lock);
483 * ice_aq_ver_check - Check the reported AQ API version.
484 * @hw: pointer to the hardware structure
486 * Checks if the driver should load on a given AQ API version.
488 * Return: 'true' iff the driver should attempt to load. 'false' otherwise.
490 static bool ice_aq_ver_check(struct ice_hw *hw)
492 if (hw->api_maj_ver > EXP_FW_API_VER_MAJOR) {
493 /* Major API version is newer than expected, don't load */
494 ice_warn(hw, "The driver for the device stopped because the NVM image is newer than expected. You must install the most recent version of the network driver.\n");
496 } else if (hw->api_maj_ver == EXP_FW_API_VER_MAJOR) {
497 if (hw->api_min_ver > (EXP_FW_API_VER_MINOR + 2))
498 ice_info(hw, "The driver for the device detected a newer version of the NVM image than expected. Please install the most recent version of the network driver.\n");
499 else if ((hw->api_min_ver + 2) < EXP_FW_API_VER_MINOR)
500 ice_info(hw, "The driver for the device detected an older version of the NVM image than expected. Please update the NVM image.\n");
502 /* Major API version is older than expected, log a warning */
503 ice_info(hw, "The driver for the device detected an older version of the NVM image than expected. Please update the NVM image.\n");
509 * ice_shutdown_rq - shutdown Control ARQ
510 * @hw: pointer to the hardware structure
511 * @cq: pointer to the specific Control queue
513 * The main shutdown routine for the Control Receive Queue
515 static enum ice_status
516 ice_shutdown_rq(struct ice_hw *hw, struct ice_ctl_q_info *cq)
518 enum ice_status ret_code = ICE_SUCCESS;
520 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
522 ice_acquire_lock(&cq->rq_lock);
525 ret_code = ICE_ERR_NOT_READY;
526 goto shutdown_rq_out;
529 /* Stop Control Queue processing */
530 wr32(hw, cq->rq.head, 0);
531 wr32(hw, cq->rq.tail, 0);
532 wr32(hw, cq->rq.len, 0);
533 wr32(hw, cq->rq.bal, 0);
534 wr32(hw, cq->rq.bah, 0);
536 /* set rq.count to 0 to indicate uninitialized queue */
539 /* free ring buffers and the ring itself */
540 ICE_FREE_CQ_BUFS(hw, cq, rq);
541 ice_free_cq_ring(hw, &cq->rq);
544 ice_release_lock(&cq->rq_lock);
549 * ice_init_check_adminq - Check version for Admin Queue to know if its alive
550 * @hw: pointer to the hardware structure
552 static enum ice_status ice_init_check_adminq(struct ice_hw *hw)
554 struct ice_ctl_q_info *cq = &hw->adminq;
555 enum ice_status status;
557 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
559 status = ice_aq_get_fw_ver(hw, NULL);
561 goto init_ctrlq_free_rq;
563 if (!ice_aq_ver_check(hw)) {
564 status = ICE_ERR_FW_API_VER;
565 goto init_ctrlq_free_rq;
571 ice_shutdown_rq(hw, cq);
572 ice_shutdown_sq(hw, cq);
577 * ice_init_ctrlq - main initialization routine for any control Queue
578 * @hw: pointer to the hardware structure
579 * @q_type: specific Control queue type
581 * Prior to calling this function, the driver *MUST* set the following fields
582 * in the cq->structure:
583 * - cq->num_sq_entries
584 * - cq->num_rq_entries
588 * NOTE: this function does not initialize the controlq locks
590 static enum ice_status ice_init_ctrlq(struct ice_hw *hw, enum ice_ctl_q q_type)
592 struct ice_ctl_q_info *cq;
593 enum ice_status ret_code;
595 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
598 case ICE_CTL_Q_ADMIN:
599 ice_adminq_init_regs(hw);
603 ice_sb_init_regs(hw);
606 case ICE_CTL_Q_MAILBOX:
607 ice_mailbox_init_regs(hw);
611 return ICE_ERR_PARAM;
615 /* verify input for valid configuration */
616 if (!cq->num_rq_entries || !cq->num_sq_entries ||
617 !cq->rq_buf_size || !cq->sq_buf_size) {
621 /* setup SQ command write back timeout */
622 cq->sq_cmd_timeout = ICE_CTL_Q_SQ_CMD_TIMEOUT;
624 /* allocate the ATQ */
625 ret_code = ice_init_sq(hw, cq);
629 /* allocate the ARQ */
630 ret_code = ice_init_rq(hw, cq);
632 goto init_ctrlq_free_sq;
638 ice_shutdown_sq(hw, cq);
643 * ice_is_sbq_supported - is the sideband queue supported
644 * @hw: pointer to the hardware structure
646 * Returns true if the sideband control queue interface is
647 * supported for the device, false otherwise
649 static bool ice_is_sbq_supported(struct ice_hw *hw)
651 return ice_is_generic_mac(hw);
655 * ice_shutdown_ctrlq - shutdown routine for any control queue
656 * @hw: pointer to the hardware structure
657 * @q_type: specific Control queue type
659 * NOTE: this function does not destroy the control queue locks.
661 static void ice_shutdown_ctrlq(struct ice_hw *hw, enum ice_ctl_q q_type)
663 struct ice_ctl_q_info *cq;
665 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
668 case ICE_CTL_Q_ADMIN:
670 if (ice_check_sq_alive(hw, cq))
671 ice_aq_q_shutdown(hw, true);
676 case ICE_CTL_Q_MAILBOX:
683 ice_shutdown_sq(hw, cq);
684 ice_shutdown_rq(hw, cq);
688 * ice_shutdown_all_ctrlq - shutdown routine for all control queues
689 * @hw: pointer to the hardware structure
691 * NOTE: this function does not destroy the control queue locks. The driver
692 * may call this at runtime to shutdown and later restart control queues, such
693 * as in response to a reset event.
695 void ice_shutdown_all_ctrlq(struct ice_hw *hw)
697 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
698 /* Shutdown FW admin queue */
699 ice_shutdown_ctrlq(hw, ICE_CTL_Q_ADMIN);
700 /* Shutdown PHY Sideband */
701 if (ice_is_sbq_supported(hw))
702 ice_shutdown_ctrlq(hw, ICE_CTL_Q_SB);
703 /* Shutdown PF-VF Mailbox */
704 ice_shutdown_ctrlq(hw, ICE_CTL_Q_MAILBOX);
708 * ice_init_all_ctrlq - main initialization routine for all control queues
709 * @hw: pointer to the hardware structure
711 * Prior to calling this function, the driver MUST* set the following fields
712 * in the cq->structure for all control queues:
713 * - cq->num_sq_entries
714 * - cq->num_rq_entries
718 * NOTE: this function does not initialize the controlq locks.
720 enum ice_status ice_init_all_ctrlq(struct ice_hw *hw)
722 enum ice_status status;
725 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
727 /* Init FW admin queue */
729 status = ice_init_ctrlq(hw, ICE_CTL_Q_ADMIN);
733 status = ice_init_check_adminq(hw);
734 if (status != ICE_ERR_AQ_FW_CRITICAL)
737 ice_debug(hw, ICE_DBG_AQ_MSG, "Retry Admin Queue init due to FW critical error\n");
738 ice_shutdown_ctrlq(hw, ICE_CTL_Q_ADMIN);
739 ice_msec_delay(ICE_CTL_Q_ADMIN_INIT_MSEC, true);
740 } while (retry++ < ICE_CTL_Q_ADMIN_INIT_TIMEOUT);
744 /* sideband control queue (SBQ) interface is not supported on some
745 * devices. Initialize if supported, else fallback to the admin queue
748 if (ice_is_sbq_supported(hw)) {
749 status = ice_init_ctrlq(hw, ICE_CTL_Q_SB);
753 /* Init Mailbox queue */
754 return ice_init_ctrlq(hw, ICE_CTL_Q_MAILBOX);
758 * ice_init_ctrlq_locks - Initialize locks for a control queue
759 * @cq: pointer to the control queue
761 * Initializes the send and receive queue locks for a given control queue.
763 static void ice_init_ctrlq_locks(struct ice_ctl_q_info *cq)
765 ice_init_lock(&cq->sq_lock);
766 ice_init_lock(&cq->rq_lock);
770 * ice_create_all_ctrlq - main initialization routine for all control queues
771 * @hw: pointer to the hardware structure
773 * Prior to calling this function, the driver *MUST* set the following fields
774 * in the cq->structure for all control queues:
775 * - cq->num_sq_entries
776 * - cq->num_rq_entries
780 * This function creates all the control queue locks and then calls
781 * ice_init_all_ctrlq. It should be called once during driver load. If the
782 * driver needs to re-initialize control queues at run time it should call
783 * ice_init_all_ctrlq instead.
785 enum ice_status ice_create_all_ctrlq(struct ice_hw *hw)
787 ice_init_ctrlq_locks(&hw->adminq);
788 if (ice_is_sbq_supported(hw))
789 ice_init_ctrlq_locks(&hw->sbq);
790 ice_init_ctrlq_locks(&hw->mailboxq);
792 return ice_init_all_ctrlq(hw);
796 * ice_destroy_ctrlq_locks - Destroy locks for a control queue
797 * @cq: pointer to the control queue
799 * Destroys the send and receive queue locks for a given control queue.
801 static void ice_destroy_ctrlq_locks(struct ice_ctl_q_info *cq)
803 ice_destroy_lock(&cq->sq_lock);
804 ice_destroy_lock(&cq->rq_lock);
808 * ice_destroy_all_ctrlq - exit routine for all control queues
809 * @hw: pointer to the hardware structure
811 * This function shuts down all the control queues and then destroys the
812 * control queue locks. It should be called once during driver unload. The
813 * driver should call ice_shutdown_all_ctrlq if it needs to shut down and
814 * reinitialize control queues, such as in response to a reset event.
816 void ice_destroy_all_ctrlq(struct ice_hw *hw)
818 /* shut down all the control queues first */
819 ice_shutdown_all_ctrlq(hw);
821 ice_destroy_ctrlq_locks(&hw->adminq);
822 if (ice_is_sbq_supported(hw))
823 ice_destroy_ctrlq_locks(&hw->sbq);
824 ice_destroy_ctrlq_locks(&hw->mailboxq);
828 * ice_clean_sq - cleans Admin send queue (ATQ)
829 * @hw: pointer to the hardware structure
830 * @cq: pointer to the specific Control queue
832 * returns the number of free desc
834 static u16 ice_clean_sq(struct ice_hw *hw, struct ice_ctl_q_info *cq)
836 struct ice_ctl_q_ring *sq = &cq->sq;
837 u16 ntc = sq->next_to_clean;
838 struct ice_sq_cd *details;
839 struct ice_aq_desc *desc;
841 desc = ICE_CTL_Q_DESC(*sq, ntc);
842 details = ICE_CTL_Q_DETAILS(*sq, ntc);
844 while (rd32(hw, cq->sq.head) != ntc) {
845 ice_debug(hw, ICE_DBG_AQ_MSG, "ntc %d head %d.\n", ntc, rd32(hw, cq->sq.head));
846 ice_memset(desc, 0, sizeof(*desc), ICE_DMA_MEM);
847 ice_memset(details, 0, sizeof(*details), ICE_NONDMA_MEM);
849 if (ntc == sq->count)
851 desc = ICE_CTL_Q_DESC(*sq, ntc);
852 details = ICE_CTL_Q_DETAILS(*sq, ntc);
855 sq->next_to_clean = ntc;
857 return ICE_CTL_Q_DESC_UNUSED(sq);
862 * @hw: pointer to the hardware structure
863 * @desc: pointer to control queue descriptor
864 * @buf: pointer to command buffer
865 * @buf_len: max length of buf
867 * Dumps debug log about control command with descriptor contents.
869 static void ice_debug_cq(struct ice_hw *hw, void *desc, void *buf, u16 buf_len)
871 struct ice_aq_desc *cq_desc = (struct ice_aq_desc *)desc;
874 if (!((ICE_DBG_AQ_DESC | ICE_DBG_AQ_DESC_BUF) & hw->debug_mask))
880 datalen = LE16_TO_CPU(cq_desc->datalen);
881 flags = LE16_TO_CPU(cq_desc->flags);
883 ice_debug(hw, ICE_DBG_AQ_DESC, "CQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
884 LE16_TO_CPU(cq_desc->opcode), flags, datalen,
885 LE16_TO_CPU(cq_desc->retval));
886 ice_debug(hw, ICE_DBG_AQ_DESC, "\tcookie (h,l) 0x%08X 0x%08X\n",
887 LE32_TO_CPU(cq_desc->cookie_high),
888 LE32_TO_CPU(cq_desc->cookie_low));
889 ice_debug(hw, ICE_DBG_AQ_DESC, "\tparam (0,1) 0x%08X 0x%08X\n",
890 LE32_TO_CPU(cq_desc->params.generic.param0),
891 LE32_TO_CPU(cq_desc->params.generic.param1));
892 ice_debug(hw, ICE_DBG_AQ_DESC, "\taddr (h,l) 0x%08X 0x%08X\n",
893 LE32_TO_CPU(cq_desc->params.generic.addr_high),
894 LE32_TO_CPU(cq_desc->params.generic.addr_low));
895 /* Dump buffer iff 1) one exists and 2) is either a response indicated
896 * by the DD and/or CMP flag set or a command with the RD flag set.
898 if (buf && cq_desc->datalen != 0 &&
899 (flags & (ICE_AQ_FLAG_DD | ICE_AQ_FLAG_CMP) ||
900 flags & ICE_AQ_FLAG_RD)) {
901 ice_debug(hw, ICE_DBG_AQ_DESC_BUF, "Buffer:\n");
902 ice_debug_array(hw, ICE_DBG_AQ_DESC_BUF, 16, 1, (u8 *)buf,
903 MIN_T(u16, buf_len, datalen));
908 * ice_sq_done - check if FW has processed the Admin Send Queue (ATQ)
909 * @hw: pointer to the HW struct
910 * @cq: pointer to the specific Control queue
912 * Returns true if the firmware has processed all descriptors on the
913 * admin send queue. Returns false if there are still requests pending.
915 static bool ice_sq_done(struct ice_hw *hw, struct ice_ctl_q_info *cq)
917 /* AQ designers suggest use of head for better
918 * timing reliability than DD bit
920 return rd32(hw, cq->sq.head) == cq->sq.next_to_use;
924 * ice_sq_send_cmd_nolock - send command to Control Queue (ATQ)
925 * @hw: pointer to the HW struct
926 * @cq: pointer to the specific Control queue
927 * @desc: prefilled descriptor describing the command (non DMA mem)
928 * @buf: buffer to use for indirect commands (or NULL for direct commands)
929 * @buf_size: size of buffer for indirect commands (or 0 for direct commands)
930 * @cd: pointer to command details structure
932 * This is the main send command routine for the ATQ. It runs the queue,
933 * cleans the queue, etc.
936 ice_sq_send_cmd_nolock(struct ice_hw *hw, struct ice_ctl_q_info *cq,
937 struct ice_aq_desc *desc, void *buf, u16 buf_size,
938 struct ice_sq_cd *cd)
940 struct ice_dma_mem *dma_buf = NULL;
941 struct ice_aq_desc *desc_on_ring;
942 bool cmd_completed = false;
943 enum ice_status status = ICE_SUCCESS;
944 struct ice_sq_cd *details;
949 /* if reset is in progress return a soft error */
950 if (hw->reset_ongoing)
951 return ICE_ERR_RESET_ONGOING;
953 cq->sq_last_status = ICE_AQ_RC_OK;
956 ice_debug(hw, ICE_DBG_AQ_MSG, "Control Send queue not initialized.\n");
957 status = ICE_ERR_AQ_EMPTY;
958 goto sq_send_command_error;
961 if ((buf && !buf_size) || (!buf && buf_size)) {
962 status = ICE_ERR_PARAM;
963 goto sq_send_command_error;
967 if (buf_size > cq->sq_buf_size) {
968 ice_debug(hw, ICE_DBG_AQ_MSG, "Invalid buffer size for Control Send queue: %d.\n",
970 status = ICE_ERR_INVAL_SIZE;
971 goto sq_send_command_error;
974 desc->flags |= CPU_TO_LE16(ICE_AQ_FLAG_BUF);
975 if (buf_size > ICE_AQ_LG_BUF)
976 desc->flags |= CPU_TO_LE16(ICE_AQ_FLAG_LB);
979 val = rd32(hw, cq->sq.head);
980 if (val >= cq->num_sq_entries) {
981 ice_debug(hw, ICE_DBG_AQ_MSG, "head overrun at %d in the Control Send Queue ring\n",
983 status = ICE_ERR_AQ_EMPTY;
984 goto sq_send_command_error;
987 details = ICE_CTL_Q_DETAILS(cq->sq, cq->sq.next_to_use);
991 ice_memset(details, 0, sizeof(*details), ICE_NONDMA_MEM);
993 /* Call clean and check queue available function to reclaim the
994 * descriptors that were processed by FW/MBX; the function returns the
995 * number of desc available. The clean function called here could be
996 * called in a separate thread in case of asynchronous completions.
998 if (ice_clean_sq(hw, cq) == 0) {
999 ice_debug(hw, ICE_DBG_AQ_MSG, "Error: Control Send Queue is full.\n");
1000 status = ICE_ERR_AQ_FULL;
1001 goto sq_send_command_error;
1004 /* initialize the temp desc pointer with the right desc */
1005 desc_on_ring = ICE_CTL_Q_DESC(cq->sq, cq->sq.next_to_use);
1007 /* if the desc is available copy the temp desc to the right place */
1008 ice_memcpy(desc_on_ring, desc, sizeof(*desc_on_ring),
1011 /* if buf is not NULL assume indirect command */
1013 dma_buf = &cq->sq.r.sq_bi[cq->sq.next_to_use];
1014 /* copy the user buf into the respective DMA buf */
1015 ice_memcpy(dma_buf->va, buf, buf_size, ICE_NONDMA_TO_DMA);
1016 desc_on_ring->datalen = CPU_TO_LE16(buf_size);
1018 /* Update the address values in the desc with the pa value
1019 * for respective buffer
1021 desc_on_ring->params.generic.addr_high =
1022 CPU_TO_LE32(ICE_HI_DWORD(dma_buf->pa));
1023 desc_on_ring->params.generic.addr_low =
1024 CPU_TO_LE32(ICE_LO_DWORD(dma_buf->pa));
1027 /* Debug desc and buffer */
1028 ice_debug(hw, ICE_DBG_AQ_DESC, "ATQ: Control Send queue desc and buffer:\n");
1030 ice_debug_cq(hw, (void *)desc_on_ring, buf, buf_size);
1032 (cq->sq.next_to_use)++;
1033 if (cq->sq.next_to_use == cq->sq.count)
1034 cq->sq.next_to_use = 0;
1035 wr32(hw, cq->sq.tail, cq->sq.next_to_use);
1038 if (ice_sq_done(hw, cq))
1041 ice_usec_delay(ICE_CTL_Q_SQ_CMD_USEC, false);
1043 } while (total_delay < cq->sq_cmd_timeout);
1045 /* if ready, copy the desc back to temp */
1046 if (ice_sq_done(hw, cq)) {
1047 ice_memcpy(desc, desc_on_ring, sizeof(*desc),
1050 /* get returned length to copy */
1051 u16 copy_size = LE16_TO_CPU(desc->datalen);
1053 if (copy_size > buf_size) {
1054 ice_debug(hw, ICE_DBG_AQ_MSG, "Return len %d > than buf len %d\n",
1055 copy_size, buf_size);
1056 status = ICE_ERR_AQ_ERROR;
1058 ice_memcpy(buf, dma_buf->va, copy_size,
1062 retval = LE16_TO_CPU(desc->retval);
1064 ice_debug(hw, ICE_DBG_AQ_MSG, "Control Send Queue command 0x%04X completed with error 0x%X\n",
1065 LE16_TO_CPU(desc->opcode),
1068 /* strip off FW internal code */
1071 cmd_completed = true;
1072 if (!status && retval != ICE_AQ_RC_OK)
1073 status = ICE_ERR_AQ_ERROR;
1074 cq->sq_last_status = (enum ice_aq_err)retval;
1077 ice_debug(hw, ICE_DBG_AQ_MSG, "ATQ: desc and buffer writeback:\n");
1079 ice_debug_cq(hw, (void *)desc, buf, buf_size);
1081 /* save writeback AQ if requested */
1082 if (details->wb_desc)
1083 ice_memcpy(details->wb_desc, desc_on_ring,
1084 sizeof(*details->wb_desc), ICE_DMA_TO_NONDMA);
1086 /* update the error if time out occurred */
1087 if (!cmd_completed) {
1088 if (rd32(hw, cq->rq.len) & cq->rq.len_crit_mask ||
1089 rd32(hw, cq->sq.len) & cq->sq.len_crit_mask) {
1090 ice_debug(hw, ICE_DBG_AQ_MSG, "Critical FW error.\n");
1091 status = ICE_ERR_AQ_FW_CRITICAL;
1093 ice_debug(hw, ICE_DBG_AQ_MSG, "Control Send Queue Writeback timeout.\n");
1094 status = ICE_ERR_AQ_TIMEOUT;
1098 sq_send_command_error:
1103 * ice_sq_send_cmd - send command to Control Queue (ATQ)
1104 * @hw: pointer to the HW struct
1105 * @cq: pointer to the specific Control queue
1106 * @desc: prefilled descriptor describing the command
1107 * @buf: buffer to use for indirect commands (or NULL for direct commands)
1108 * @buf_size: size of buffer for indirect commands (or 0 for direct commands)
1109 * @cd: pointer to command details structure
1111 * This is the main send command routine for the ATQ. It runs the queue,
1112 * cleans the queue, etc.
1115 ice_sq_send_cmd(struct ice_hw *hw, struct ice_ctl_q_info *cq,
1116 struct ice_aq_desc *desc, void *buf, u16 buf_size,
1117 struct ice_sq_cd *cd)
1119 enum ice_status status = ICE_SUCCESS;
1121 /* if reset is in progress return a soft error */
1122 if (hw->reset_ongoing)
1123 return ICE_ERR_RESET_ONGOING;
1125 ice_acquire_lock(&cq->sq_lock);
1126 status = ice_sq_send_cmd_nolock(hw, cq, desc, buf, buf_size, cd);
1127 ice_release_lock(&cq->sq_lock);
1133 * ice_fill_dflt_direct_cmd_desc - AQ descriptor helper function
1134 * @desc: pointer to the temp descriptor (non DMA mem)
1135 * @opcode: the opcode can be used to decide which flags to turn off or on
1137 * Fill the desc with default values
1139 void ice_fill_dflt_direct_cmd_desc(struct ice_aq_desc *desc, u16 opcode)
1141 /* zero out the desc */
1142 ice_memset(desc, 0, sizeof(*desc), ICE_NONDMA_MEM);
1143 desc->opcode = CPU_TO_LE16(opcode);
1144 desc->flags = CPU_TO_LE16(ICE_AQ_FLAG_SI);
1149 * @hw: pointer to the HW struct
1150 * @cq: pointer to the specific Control queue
1151 * @e: event info from the receive descriptor, includes any buffers
1152 * @pending: number of events that could be left to process
1154 * This function cleans one Admin Receive Queue element and returns
1155 * the contents through e. It can also return how many events are
1156 * left to process through 'pending'.
1159 ice_clean_rq_elem(struct ice_hw *hw, struct ice_ctl_q_info *cq,
1160 struct ice_rq_event_info *e, u16 *pending)
1162 u16 ntc = cq->rq.next_to_clean;
1163 enum ice_aq_err rq_last_status;
1164 enum ice_status ret_code = ICE_SUCCESS;
1165 struct ice_aq_desc *desc;
1166 struct ice_dma_mem *bi;
1172 /* pre-clean the event info */
1173 ice_memset(&e->desc, 0, sizeof(e->desc), ICE_NONDMA_MEM);
1175 /* take the lock before we start messing with the ring */
1176 ice_acquire_lock(&cq->rq_lock);
1178 if (!cq->rq.count) {
1179 ice_debug(hw, ICE_DBG_AQ_MSG, "Control Receive queue not initialized.\n");
1180 ret_code = ICE_ERR_AQ_EMPTY;
1181 goto clean_rq_elem_err;
1184 /* set next_to_use to head */
1185 ntu = (u16)(rd32(hw, cq->rq.head) & cq->rq.head_mask);
1188 /* nothing to do - shouldn't need to update ring's values */
1189 ret_code = ICE_ERR_AQ_NO_WORK;
1190 goto clean_rq_elem_out;
1193 /* now clean the next descriptor */
1194 desc = ICE_CTL_Q_DESC(cq->rq, ntc);
1197 rq_last_status = (enum ice_aq_err)LE16_TO_CPU(desc->retval);
1198 flags = LE16_TO_CPU(desc->flags);
1199 if (flags & ICE_AQ_FLAG_ERR) {
1200 ret_code = ICE_ERR_AQ_ERROR;
1201 ice_debug(hw, ICE_DBG_AQ_MSG, "Control Receive Queue Event 0x%04X received with error 0x%X\n",
1202 LE16_TO_CPU(desc->opcode), rq_last_status);
1204 ice_memcpy(&e->desc, desc, sizeof(e->desc), ICE_DMA_TO_NONDMA);
1205 datalen = LE16_TO_CPU(desc->datalen);
1206 e->msg_len = MIN_T(u16, datalen, e->buf_len);
1207 if (e->msg_buf && e->msg_len)
1208 ice_memcpy(e->msg_buf, cq->rq.r.rq_bi[desc_idx].va,
1209 e->msg_len, ICE_DMA_TO_NONDMA);
1211 ice_debug(hw, ICE_DBG_AQ_DESC, "ARQ: desc and buffer:\n");
1213 ice_debug_cq(hw, (void *)desc, e->msg_buf, cq->rq_buf_size);
1215 /* Restore the original datalen and buffer address in the desc,
1216 * FW updates datalen to indicate the event message size
1218 bi = &cq->rq.r.rq_bi[ntc];
1219 ice_memset(desc, 0, sizeof(*desc), ICE_DMA_MEM);
1221 desc->flags = CPU_TO_LE16(ICE_AQ_FLAG_BUF);
1222 if (cq->rq_buf_size > ICE_AQ_LG_BUF)
1223 desc->flags |= CPU_TO_LE16(ICE_AQ_FLAG_LB);
1224 desc->datalen = CPU_TO_LE16(bi->size);
1225 desc->params.generic.addr_high = CPU_TO_LE32(ICE_HI_DWORD(bi->pa));
1226 desc->params.generic.addr_low = CPU_TO_LE32(ICE_LO_DWORD(bi->pa));
1228 /* set tail = the last cleaned desc index. */
1229 wr32(hw, cq->rq.tail, ntc);
1230 /* ntc is updated to tail + 1 */
1232 if (ntc == cq->num_rq_entries)
1234 cq->rq.next_to_clean = ntc;
1235 cq->rq.next_to_use = ntu;
1238 /* Set pending if needed, unlock and return */
1240 /* re-read HW head to calculate actual pending messages */
1241 ntu = (u16)(rd32(hw, cq->rq.head) & cq->rq.head_mask);
1242 *pending = (u16)((ntc > ntu ? cq->rq.count : 0) + (ntu - ntc));
1245 ice_release_lock(&cq->rq_lock);