1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2001-2021 Intel Corporation
5 #ifndef _ICE_CONTROLQ_H_
6 #define _ICE_CONTROLQ_H_
8 #include "ice_adminq_cmd.h"
10 /* Maximum buffer lengths for all control queue types */
11 #define ICE_AQ_MAX_BUF_LEN 4096
12 #define ICE_MBXQ_MAX_BUF_LEN 4096
13 #define ICE_SBQ_MAX_BUF_LEN 512
15 #define ICE_CTL_Q_DESC(R, i) \
16 (&(((struct ice_aq_desc *)((R).desc_buf.va))[i]))
18 #define ICE_CTL_Q_DESC_UNUSED(R) \
19 ((u16)((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
20 (R)->next_to_clean - (R)->next_to_use - 1))
22 /* Defines that help manage the driver vs FW API checks.
23 * Take a look at ice_aq_ver_check in ice_controlq.c for actual usage.
25 #define EXP_FW_API_VER_BRANCH 0x00
26 #define EXP_FW_API_VER_MAJOR 0x01
27 #define EXP_FW_API_VER_MINOR 0x05
29 /* Different control queue types: These are mainly for SW consumption. */
31 ICE_CTL_Q_UNKNOWN = 0,
37 /* Control Queue timeout settings - max delay 1s */
38 #define ICE_CTL_Q_SQ_CMD_TIMEOUT 10000 /* Count 10000 times */
39 #define ICE_CTL_Q_SQ_CMD_USEC 100 /* Check every 100usec */
40 #define ICE_CTL_Q_ADMIN_INIT_TIMEOUT 10 /* Count 10 times */
41 #define ICE_CTL_Q_ADMIN_INIT_MSEC 100 /* Check every 100msec */
43 struct ice_ctl_q_ring {
44 void *dma_head; /* Virtual address to DMA head */
45 struct ice_dma_mem desc_buf; /* descriptor ring memory */
46 void *cmd_buf; /* command buffer memory */
49 struct ice_dma_mem *sq_bi;
50 struct ice_dma_mem *rq_bi;
53 u16 count; /* Number of descriptors */
55 /* used for interrupt processing */
59 /* used for queue tracking */
71 /* sq transaction details */
73 struct ice_aq_desc *wb_desc;
76 #define ICE_CTL_Q_DETAILS(R, i) (&(((struct ice_sq_cd *)((R).cmd_buf))[i]))
78 /* rq event information */
79 struct ice_rq_event_info {
80 struct ice_aq_desc desc;
86 /* Control Queue information */
87 struct ice_ctl_q_info {
89 struct ice_ctl_q_ring rq; /* receive queue */
90 struct ice_ctl_q_ring sq; /* send queue */
91 u32 sq_cmd_timeout; /* send queue cmd write back timeout */
92 u16 num_rq_entries; /* receive queue depth */
93 u16 num_sq_entries; /* send queue depth */
94 u16 rq_buf_size; /* receive queue buffer size */
95 u16 sq_buf_size; /* send queue buffer size */
96 enum ice_aq_err sq_last_status; /* last status on send queue */
97 struct ice_lock sq_lock; /* Send queue lock */
98 struct ice_lock rq_lock; /* Receive queue lock */
101 #endif /* _ICE_CONTROLQ_H_ */