1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2001-2020 Intel Corporation
5 #ifndef _ICE_CONTROLQ_H_
6 #define _ICE_CONTROLQ_H_
8 #include "ice_adminq_cmd.h"
10 /* Maximum buffer lengths for all control queue types */
11 #define ICE_AQ_MAX_BUF_LEN 4096
12 #define ICE_MBXQ_MAX_BUF_LEN 4096
14 #define ICE_CTL_Q_DESC(R, i) \
15 (&(((struct ice_aq_desc *)((R).desc_buf.va))[i]))
17 #define ICE_CTL_Q_DESC_UNUSED(R) \
18 (u16)((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
19 (R)->next_to_clean - (R)->next_to_use - 1)
21 /* Defines that help manage the driver vs FW API checks.
22 * Take a look at ice_aq_ver_check in ice_controlq.c for actual usage.
24 #define EXP_FW_API_VER_BRANCH 0x00
25 #define EXP_FW_API_VER_MAJOR 0x01
26 #define EXP_FW_API_VER_MINOR 0x05
28 /* Different control queue types: These are mainly for SW consumption. */
30 ICE_CTL_Q_UNKNOWN = 0,
35 /* Control Queue timeout settings - max delay 1s */
36 #define ICE_CTL_Q_SQ_CMD_TIMEOUT 10000 /* Count 10000 times */
37 #define ICE_CTL_Q_SQ_CMD_USEC 100 /* Check every 100usec */
38 #define ICE_CTL_Q_ADMIN_INIT_TIMEOUT 10 /* Count 10 times */
39 #define ICE_CTL_Q_ADMIN_INIT_MSEC 100 /* Check every 100msec */
41 struct ice_ctl_q_ring {
42 void *dma_head; /* Virtual address to DMA head */
43 struct ice_dma_mem desc_buf; /* descriptor ring memory */
44 void *cmd_buf; /* command buffer memory */
47 struct ice_dma_mem *sq_bi;
48 struct ice_dma_mem *rq_bi;
51 u16 count; /* Number of descriptors */
53 /* used for interrupt processing */
57 /* used for queue tracking */
69 /* sq transaction details */
71 struct ice_aq_desc *wb_desc;
74 #define ICE_CTL_Q_DETAILS(R, i) (&(((struct ice_sq_cd *)((R).cmd_buf))[i]))
76 /* rq event information */
77 struct ice_rq_event_info {
78 struct ice_aq_desc desc;
84 /* Control Queue information */
85 struct ice_ctl_q_info {
87 enum ice_aq_err rq_last_status; /* last status on receive queue */
88 struct ice_ctl_q_ring rq; /* receive queue */
89 struct ice_ctl_q_ring sq; /* send queue */
90 u32 sq_cmd_timeout; /* send queue cmd write back timeout */
91 u16 num_rq_entries; /* receive queue depth */
92 u16 num_sq_entries; /* send queue depth */
93 u16 rq_buf_size; /* receive queue buffer size */
94 u16 sq_buf_size; /* send queue buffer size */
95 enum ice_aq_err sq_last_status; /* last status on send queue */
96 struct ice_lock sq_lock; /* Send queue lock */
97 struct ice_lock rq_lock; /* Receive queue lock */
100 #endif /* _ICE_CONTROLQ_H_ */