1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2001-2020 Intel Corporation
5 /* Machine-generated file; do not edit */
6 #ifndef _ICE_HW_AUTOGEN_H_
7 #define _ICE_HW_AUTOGEN_H_
9 #define GL_RDPU_CNTRL 0x00052054 /* Reset Source: CORER */
10 #define GL_RDPU_CNTRL_RX_PAD_EN_S 0
11 #define GL_RDPU_CNTRL_RX_PAD_EN_M BIT(0)
12 #define GL_RDPU_CNTRL_UDP_ZERO_EN_S 1
13 #define GL_RDPU_CNTRL_UDP_ZERO_EN_M BIT(1)
14 #define GL_RDPU_CNTRL_BLNC_EN_S 2
15 #define GL_RDPU_CNTRL_BLNC_EN_M BIT(2)
16 #define GL_RDPU_CNTRL_RECIPE_BYPASS_S 3
17 #define GL_RDPU_CNTRL_RECIPE_BYPASS_M BIT(3)
18 #define GL_RDPU_CNTRL_RLAN_ACK_REQ_PM_TH_S 4
19 #define GL_RDPU_CNTRL_RLAN_ACK_REQ_PM_TH_M MAKEMASK(0x3F, 4)
20 #define GL_RDPU_CNTRL_PE_ACK_REQ_PM_TH_S 10
21 #define GL_RDPU_CNTRL_PE_ACK_REQ_PM_TH_M MAKEMASK(0x3F, 10)
22 #define GL_RDPU_CNTRL_REQ_WB_PM_TH_S 16
23 #define GL_RDPU_CNTRL_REQ_WB_PM_TH_M MAKEMASK(0x1F, 16)
24 #define GL_RDPU_CNTRL_ECO_S 21
25 #define GL_RDPU_CNTRL_ECO_M MAKEMASK(0x7FF, 21)
26 #define MSIX_PBA(_i) (0x00008000 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: FLR */
27 #define MSIX_PBA_MAX_INDEX 2
28 #define MSIX_PBA_PENBIT_S 0
29 #define MSIX_PBA_PENBIT_M MAKEMASK(0xFFFFFFFF, 0)
30 #define MSIX_TADD(_i) (0x00000000 + ((_i) * 16)) /* _i=0...64 */ /* Reset Source: FLR */
31 #define MSIX_TADD_MAX_INDEX 64
32 #define MSIX_TADD_MSIXTADD10_S 0
33 #define MSIX_TADD_MSIXTADD10_M MAKEMASK(0x3, 0)
34 #define MSIX_TADD_MSIXTADD_S 2
35 #define MSIX_TADD_MSIXTADD_M MAKEMASK(0x3FFFFFFF, 2)
36 #define MSIX_TUADD(_i) (0x00000004 + ((_i) * 16)) /* _i=0...64 */ /* Reset Source: FLR */
37 #define MSIX_TUADD_MAX_INDEX 64
38 #define MSIX_TUADD_MSIXTUADD_S 0
39 #define MSIX_TUADD_MSIXTUADD_M MAKEMASK(0xFFFFFFFF, 0)
40 #define MSIX_TVCTRL(_i) (0x0000000C + ((_i) * 16)) /* _i=0...64 */ /* Reset Source: FLR */
41 #define MSIX_TVCTRL_MAX_INDEX 64
42 #define MSIX_TVCTRL_MASK_S 0
43 #define MSIX_TVCTRL_MASK_M BIT(0)
44 #define PF0_FW_HLP_ARQBAH_PAGE 0x02D00180 /* Reset Source: EMPR */
45 #define PF0_FW_HLP_ARQBAH_PAGE_ARQBAH_S 0
46 #define PF0_FW_HLP_ARQBAH_PAGE_ARQBAH_M MAKEMASK(0xFFFFFFFF, 0)
47 #define PF0_FW_HLP_ARQBAL_PAGE 0x02D00080 /* Reset Source: EMPR */
48 #define PF0_FW_HLP_ARQBAL_PAGE_ARQBAL_LSB_S 0
49 #define PF0_FW_HLP_ARQBAL_PAGE_ARQBAL_LSB_M MAKEMASK(0x3F, 0)
50 #define PF0_FW_HLP_ARQBAL_PAGE_ARQBAL_S 6
51 #define PF0_FW_HLP_ARQBAL_PAGE_ARQBAL_M MAKEMASK(0x3FFFFFF, 6)
52 #define PF0_FW_HLP_ARQH_PAGE 0x02D00380 /* Reset Source: EMPR */
53 #define PF0_FW_HLP_ARQH_PAGE_ARQH_S 0
54 #define PF0_FW_HLP_ARQH_PAGE_ARQH_M MAKEMASK(0x3FF, 0)
55 #define PF0_FW_HLP_ARQLEN_PAGE 0x02D00280 /* Reset Source: EMPR */
56 #define PF0_FW_HLP_ARQLEN_PAGE_ARQLEN_S 0
57 #define PF0_FW_HLP_ARQLEN_PAGE_ARQLEN_M MAKEMASK(0x3FF, 0)
58 #define PF0_FW_HLP_ARQLEN_PAGE_ARQVFE_S 28
59 #define PF0_FW_HLP_ARQLEN_PAGE_ARQVFE_M BIT(28)
60 #define PF0_FW_HLP_ARQLEN_PAGE_ARQOVFL_S 29
61 #define PF0_FW_HLP_ARQLEN_PAGE_ARQOVFL_M BIT(29)
62 #define PF0_FW_HLP_ARQLEN_PAGE_ARQCRIT_S 30
63 #define PF0_FW_HLP_ARQLEN_PAGE_ARQCRIT_M BIT(30)
64 #define PF0_FW_HLP_ARQLEN_PAGE_ARQENABLE_S 31
65 #define PF0_FW_HLP_ARQLEN_PAGE_ARQENABLE_M BIT(31)
66 #define PF0_FW_HLP_ARQT_PAGE 0x02D00480 /* Reset Source: EMPR */
67 #define PF0_FW_HLP_ARQT_PAGE_ARQT_S 0
68 #define PF0_FW_HLP_ARQT_PAGE_ARQT_M MAKEMASK(0x3FF, 0)
69 #define PF0_FW_HLP_ATQBAH_PAGE 0x02D00100 /* Reset Source: EMPR */
70 #define PF0_FW_HLP_ATQBAH_PAGE_ATQBAH_S 0
71 #define PF0_FW_HLP_ATQBAH_PAGE_ATQBAH_M MAKEMASK(0xFFFFFFFF, 0)
72 #define PF0_FW_HLP_ATQBAL_PAGE 0x02D00000 /* Reset Source: EMPR */
73 #define PF0_FW_HLP_ATQBAL_PAGE_ATQBAL_LSB_S 0
74 #define PF0_FW_HLP_ATQBAL_PAGE_ATQBAL_LSB_M MAKEMASK(0x3F, 0)
75 #define PF0_FW_HLP_ATQBAL_PAGE_ATQBAL_S 6
76 #define PF0_FW_HLP_ATQBAL_PAGE_ATQBAL_M MAKEMASK(0x3FFFFFF, 6)
77 #define PF0_FW_HLP_ATQH_PAGE 0x02D00300 /* Reset Source: EMPR */
78 #define PF0_FW_HLP_ATQH_PAGE_ATQH_S 0
79 #define PF0_FW_HLP_ATQH_PAGE_ATQH_M MAKEMASK(0x3FF, 0)
80 #define PF0_FW_HLP_ATQLEN_PAGE 0x02D00200 /* Reset Source: EMPR */
81 #define PF0_FW_HLP_ATQLEN_PAGE_ATQLEN_S 0
82 #define PF0_FW_HLP_ATQLEN_PAGE_ATQLEN_M MAKEMASK(0x3FF, 0)
83 #define PF0_FW_HLP_ATQLEN_PAGE_ATQVFE_S 28
84 #define PF0_FW_HLP_ATQLEN_PAGE_ATQVFE_M BIT(28)
85 #define PF0_FW_HLP_ATQLEN_PAGE_ATQOVFL_S 29
86 #define PF0_FW_HLP_ATQLEN_PAGE_ATQOVFL_M BIT(29)
87 #define PF0_FW_HLP_ATQLEN_PAGE_ATQCRIT_S 30
88 #define PF0_FW_HLP_ATQLEN_PAGE_ATQCRIT_M BIT(30)
89 #define PF0_FW_HLP_ATQLEN_PAGE_ATQENABLE_S 31
90 #define PF0_FW_HLP_ATQLEN_PAGE_ATQENABLE_M BIT(31)
91 #define PF0_FW_HLP_ATQT_PAGE 0x02D00400 /* Reset Source: EMPR */
92 #define PF0_FW_HLP_ATQT_PAGE_ATQT_S 0
93 #define PF0_FW_HLP_ATQT_PAGE_ATQT_M MAKEMASK(0x3FF, 0)
94 #define PF0_FW_PSM_ARQBAH_PAGE 0x02D40180 /* Reset Source: EMPR */
95 #define PF0_FW_PSM_ARQBAH_PAGE_ARQBAH_S 0
96 #define PF0_FW_PSM_ARQBAH_PAGE_ARQBAH_M MAKEMASK(0xFFFFFFFF, 0)
97 #define PF0_FW_PSM_ARQBAL_PAGE 0x02D40080 /* Reset Source: EMPR */
98 #define PF0_FW_PSM_ARQBAL_PAGE_ARQBAL_LSB_S 0
99 #define PF0_FW_PSM_ARQBAL_PAGE_ARQBAL_LSB_M MAKEMASK(0x3F, 0)
100 #define PF0_FW_PSM_ARQBAL_PAGE_ARQBAL_S 6
101 #define PF0_FW_PSM_ARQBAL_PAGE_ARQBAL_M MAKEMASK(0x3FFFFFF, 6)
102 #define PF0_FW_PSM_ARQH_PAGE 0x02D40380 /* Reset Source: EMPR */
103 #define PF0_FW_PSM_ARQH_PAGE_ARQH_S 0
104 #define PF0_FW_PSM_ARQH_PAGE_ARQH_M MAKEMASK(0x3FF, 0)
105 #define PF0_FW_PSM_ARQLEN_PAGE 0x02D40280 /* Reset Source: EMPR */
106 #define PF0_FW_PSM_ARQLEN_PAGE_ARQLEN_S 0
107 #define PF0_FW_PSM_ARQLEN_PAGE_ARQLEN_M MAKEMASK(0x3FF, 0)
108 #define PF0_FW_PSM_ARQLEN_PAGE_ARQVFE_S 28
109 #define PF0_FW_PSM_ARQLEN_PAGE_ARQVFE_M BIT(28)
110 #define PF0_FW_PSM_ARQLEN_PAGE_ARQOVFL_S 29
111 #define PF0_FW_PSM_ARQLEN_PAGE_ARQOVFL_M BIT(29)
112 #define PF0_FW_PSM_ARQLEN_PAGE_ARQCRIT_S 30
113 #define PF0_FW_PSM_ARQLEN_PAGE_ARQCRIT_M BIT(30)
114 #define PF0_FW_PSM_ARQLEN_PAGE_ARQENABLE_S 31
115 #define PF0_FW_PSM_ARQLEN_PAGE_ARQENABLE_M BIT(31)
116 #define PF0_FW_PSM_ARQT_PAGE 0x02D40480 /* Reset Source: EMPR */
117 #define PF0_FW_PSM_ARQT_PAGE_ARQT_S 0
118 #define PF0_FW_PSM_ARQT_PAGE_ARQT_M MAKEMASK(0x3FF, 0)
119 #define PF0_FW_PSM_ATQBAH_PAGE 0x02D40100 /* Reset Source: EMPR */
120 #define PF0_FW_PSM_ATQBAH_PAGE_ATQBAH_S 0
121 #define PF0_FW_PSM_ATQBAH_PAGE_ATQBAH_M MAKEMASK(0xFFFFFFFF, 0)
122 #define PF0_FW_PSM_ATQBAL_PAGE 0x02D40000 /* Reset Source: EMPR */
123 #define PF0_FW_PSM_ATQBAL_PAGE_ATQBAL_LSB_S 0
124 #define PF0_FW_PSM_ATQBAL_PAGE_ATQBAL_LSB_M MAKEMASK(0x3F, 0)
125 #define PF0_FW_PSM_ATQBAL_PAGE_ATQBAL_S 6
126 #define PF0_FW_PSM_ATQBAL_PAGE_ATQBAL_M MAKEMASK(0x3FFFFFF, 6)
127 #define PF0_FW_PSM_ATQH_PAGE 0x02D40300 /* Reset Source: EMPR */
128 #define PF0_FW_PSM_ATQH_PAGE_ATQH_S 0
129 #define PF0_FW_PSM_ATQH_PAGE_ATQH_M MAKEMASK(0x3FF, 0)
130 #define PF0_FW_PSM_ATQLEN_PAGE 0x02D40200 /* Reset Source: EMPR */
131 #define PF0_FW_PSM_ATQLEN_PAGE_ATQLEN_S 0
132 #define PF0_FW_PSM_ATQLEN_PAGE_ATQLEN_M MAKEMASK(0x3FF, 0)
133 #define PF0_FW_PSM_ATQLEN_PAGE_ATQVFE_S 28
134 #define PF0_FW_PSM_ATQLEN_PAGE_ATQVFE_M BIT(28)
135 #define PF0_FW_PSM_ATQLEN_PAGE_ATQOVFL_S 29
136 #define PF0_FW_PSM_ATQLEN_PAGE_ATQOVFL_M BIT(29)
137 #define PF0_FW_PSM_ATQLEN_PAGE_ATQCRIT_S 30
138 #define PF0_FW_PSM_ATQLEN_PAGE_ATQCRIT_M BIT(30)
139 #define PF0_FW_PSM_ATQLEN_PAGE_ATQENABLE_S 31
140 #define PF0_FW_PSM_ATQLEN_PAGE_ATQENABLE_M BIT(31)
141 #define PF0_FW_PSM_ATQT_PAGE 0x02D40400 /* Reset Source: EMPR */
142 #define PF0_FW_PSM_ATQT_PAGE_ATQT_S 0
143 #define PF0_FW_PSM_ATQT_PAGE_ATQT_M MAKEMASK(0x3FF, 0)
144 #define PF0_MBX_CPM_ARQBAH_PAGE 0x02D80190 /* Reset Source: CORER */
145 #define PF0_MBX_CPM_ARQBAH_PAGE_ARQBAH_S 0
146 #define PF0_MBX_CPM_ARQBAH_PAGE_ARQBAH_M MAKEMASK(0xFFFFFFFF, 0)
147 #define PF0_MBX_CPM_ARQBAL_PAGE 0x02D80090 /* Reset Source: CORER */
148 #define PF0_MBX_CPM_ARQBAL_PAGE_ARQBAL_LSB_S 0
149 #define PF0_MBX_CPM_ARQBAL_PAGE_ARQBAL_LSB_M MAKEMASK(0x3F, 0)
150 #define PF0_MBX_CPM_ARQBAL_PAGE_ARQBAL_S 6
151 #define PF0_MBX_CPM_ARQBAL_PAGE_ARQBAL_M MAKEMASK(0x3FFFFFF, 6)
152 #define PF0_MBX_CPM_ARQH_PAGE 0x02D80390 /* Reset Source: CORER */
153 #define PF0_MBX_CPM_ARQH_PAGE_ARQH_S 0
154 #define PF0_MBX_CPM_ARQH_PAGE_ARQH_M MAKEMASK(0x3FF, 0)
155 #define PF0_MBX_CPM_ARQLEN_PAGE 0x02D80290 /* Reset Source: PFR */
156 #define PF0_MBX_CPM_ARQLEN_PAGE_ARQLEN_S 0
157 #define PF0_MBX_CPM_ARQLEN_PAGE_ARQLEN_M MAKEMASK(0x3FF, 0)
158 #define PF0_MBX_CPM_ARQLEN_PAGE_ARQVFE_S 28
159 #define PF0_MBX_CPM_ARQLEN_PAGE_ARQVFE_M BIT(28)
160 #define PF0_MBX_CPM_ARQLEN_PAGE_ARQOVFL_S 29
161 #define PF0_MBX_CPM_ARQLEN_PAGE_ARQOVFL_M BIT(29)
162 #define PF0_MBX_CPM_ARQLEN_PAGE_ARQCRIT_S 30
163 #define PF0_MBX_CPM_ARQLEN_PAGE_ARQCRIT_M BIT(30)
164 #define PF0_MBX_CPM_ARQLEN_PAGE_ARQENABLE_S 31
165 #define PF0_MBX_CPM_ARQLEN_PAGE_ARQENABLE_M BIT(31)
166 #define PF0_MBX_CPM_ARQT_PAGE 0x02D80490 /* Reset Source: CORER */
167 #define PF0_MBX_CPM_ARQT_PAGE_ARQT_S 0
168 #define PF0_MBX_CPM_ARQT_PAGE_ARQT_M MAKEMASK(0x3FF, 0)
169 #define PF0_MBX_CPM_ATQBAH_PAGE 0x02D80110 /* Reset Source: CORER */
170 #define PF0_MBX_CPM_ATQBAH_PAGE_ATQBAH_S 0
171 #define PF0_MBX_CPM_ATQBAH_PAGE_ATQBAH_M MAKEMASK(0xFFFFFFFF, 0)
172 #define PF0_MBX_CPM_ATQBAL_PAGE 0x02D80010 /* Reset Source: CORER */
173 #define PF0_MBX_CPM_ATQBAL_PAGE_ATQBAL_S 6
174 #define PF0_MBX_CPM_ATQBAL_PAGE_ATQBAL_M MAKEMASK(0x3FFFFFF, 6)
175 #define PF0_MBX_CPM_ATQH_PAGE 0x02D80310 /* Reset Source: CORER */
176 #define PF0_MBX_CPM_ATQH_PAGE_ATQH_S 0
177 #define PF0_MBX_CPM_ATQH_PAGE_ATQH_M MAKEMASK(0x3FF, 0)
178 #define PF0_MBX_CPM_ATQLEN_PAGE 0x02D80210 /* Reset Source: PFR */
179 #define PF0_MBX_CPM_ATQLEN_PAGE_ATQLEN_S 0
180 #define PF0_MBX_CPM_ATQLEN_PAGE_ATQLEN_M MAKEMASK(0x3FF, 0)
181 #define PF0_MBX_CPM_ATQLEN_PAGE_ATQVFE_S 28
182 #define PF0_MBX_CPM_ATQLEN_PAGE_ATQVFE_M BIT(28)
183 #define PF0_MBX_CPM_ATQLEN_PAGE_ATQOVFL_S 29
184 #define PF0_MBX_CPM_ATQLEN_PAGE_ATQOVFL_M BIT(29)
185 #define PF0_MBX_CPM_ATQLEN_PAGE_ATQCRIT_S 30
186 #define PF0_MBX_CPM_ATQLEN_PAGE_ATQCRIT_M BIT(30)
187 #define PF0_MBX_CPM_ATQLEN_PAGE_ATQENABLE_S 31
188 #define PF0_MBX_CPM_ATQLEN_PAGE_ATQENABLE_M BIT(31)
189 #define PF0_MBX_CPM_ATQT_PAGE 0x02D80410 /* Reset Source: CORER */
190 #define PF0_MBX_CPM_ATQT_PAGE_ATQT_S 0
191 #define PF0_MBX_CPM_ATQT_PAGE_ATQT_M MAKEMASK(0x3FF, 0)
192 #define PF0_MBX_HLP_ARQBAH_PAGE 0x02D00190 /* Reset Source: CORER */
193 #define PF0_MBX_HLP_ARQBAH_PAGE_ARQBAH_S 0
194 #define PF0_MBX_HLP_ARQBAH_PAGE_ARQBAH_M MAKEMASK(0xFFFFFFFF, 0)
195 #define PF0_MBX_HLP_ARQBAL_PAGE 0x02D00090 /* Reset Source: CORER */
196 #define PF0_MBX_HLP_ARQBAL_PAGE_ARQBAL_LSB_S 0
197 #define PF0_MBX_HLP_ARQBAL_PAGE_ARQBAL_LSB_M MAKEMASK(0x3F, 0)
198 #define PF0_MBX_HLP_ARQBAL_PAGE_ARQBAL_S 6
199 #define PF0_MBX_HLP_ARQBAL_PAGE_ARQBAL_M MAKEMASK(0x3FFFFFF, 6)
200 #define PF0_MBX_HLP_ARQH_PAGE 0x02D00390 /* Reset Source: CORER */
201 #define PF0_MBX_HLP_ARQH_PAGE_ARQH_S 0
202 #define PF0_MBX_HLP_ARQH_PAGE_ARQH_M MAKEMASK(0x3FF, 0)
203 #define PF0_MBX_HLP_ARQLEN_PAGE 0x02D00290 /* Reset Source: PFR */
204 #define PF0_MBX_HLP_ARQLEN_PAGE_ARQLEN_S 0
205 #define PF0_MBX_HLP_ARQLEN_PAGE_ARQLEN_M MAKEMASK(0x3FF, 0)
206 #define PF0_MBX_HLP_ARQLEN_PAGE_ARQVFE_S 28
207 #define PF0_MBX_HLP_ARQLEN_PAGE_ARQVFE_M BIT(28)
208 #define PF0_MBX_HLP_ARQLEN_PAGE_ARQOVFL_S 29
209 #define PF0_MBX_HLP_ARQLEN_PAGE_ARQOVFL_M BIT(29)
210 #define PF0_MBX_HLP_ARQLEN_PAGE_ARQCRIT_S 30
211 #define PF0_MBX_HLP_ARQLEN_PAGE_ARQCRIT_M BIT(30)
212 #define PF0_MBX_HLP_ARQLEN_PAGE_ARQENABLE_S 31
213 #define PF0_MBX_HLP_ARQLEN_PAGE_ARQENABLE_M BIT(31)
214 #define PF0_MBX_HLP_ARQT_PAGE 0x02D00490 /* Reset Source: CORER */
215 #define PF0_MBX_HLP_ARQT_PAGE_ARQT_S 0
216 #define PF0_MBX_HLP_ARQT_PAGE_ARQT_M MAKEMASK(0x3FF, 0)
217 #define PF0_MBX_HLP_ATQBAH_PAGE 0x02D00110 /* Reset Source: CORER */
218 #define PF0_MBX_HLP_ATQBAH_PAGE_ATQBAH_S 0
219 #define PF0_MBX_HLP_ATQBAH_PAGE_ATQBAH_M MAKEMASK(0xFFFFFFFF, 0)
220 #define PF0_MBX_HLP_ATQBAL_PAGE 0x02D00010 /* Reset Source: CORER */
221 #define PF0_MBX_HLP_ATQBAL_PAGE_ATQBAL_S 6
222 #define PF0_MBX_HLP_ATQBAL_PAGE_ATQBAL_M MAKEMASK(0x3FFFFFF, 6)
223 #define PF0_MBX_HLP_ATQH_PAGE 0x02D00310 /* Reset Source: CORER */
224 #define PF0_MBX_HLP_ATQH_PAGE_ATQH_S 0
225 #define PF0_MBX_HLP_ATQH_PAGE_ATQH_M MAKEMASK(0x3FF, 0)
226 #define PF0_MBX_HLP_ATQLEN_PAGE 0x02D00210 /* Reset Source: PFR */
227 #define PF0_MBX_HLP_ATQLEN_PAGE_ATQLEN_S 0
228 #define PF0_MBX_HLP_ATQLEN_PAGE_ATQLEN_M MAKEMASK(0x3FF, 0)
229 #define PF0_MBX_HLP_ATQLEN_PAGE_ATQVFE_S 28
230 #define PF0_MBX_HLP_ATQLEN_PAGE_ATQVFE_M BIT(28)
231 #define PF0_MBX_HLP_ATQLEN_PAGE_ATQOVFL_S 29
232 #define PF0_MBX_HLP_ATQLEN_PAGE_ATQOVFL_M BIT(29)
233 #define PF0_MBX_HLP_ATQLEN_PAGE_ATQCRIT_S 30
234 #define PF0_MBX_HLP_ATQLEN_PAGE_ATQCRIT_M BIT(30)
235 #define PF0_MBX_HLP_ATQLEN_PAGE_ATQENABLE_S 31
236 #define PF0_MBX_HLP_ATQLEN_PAGE_ATQENABLE_M BIT(31)
237 #define PF0_MBX_HLP_ATQT_PAGE 0x02D00410 /* Reset Source: CORER */
238 #define PF0_MBX_HLP_ATQT_PAGE_ATQT_S 0
239 #define PF0_MBX_HLP_ATQT_PAGE_ATQT_M MAKEMASK(0x3FF, 0)
240 #define PF0_MBX_PSM_ARQBAH_PAGE 0x02D40190 /* Reset Source: CORER */
241 #define PF0_MBX_PSM_ARQBAH_PAGE_ARQBAH_S 0
242 #define PF0_MBX_PSM_ARQBAH_PAGE_ARQBAH_M MAKEMASK(0xFFFFFFFF, 0)
243 #define PF0_MBX_PSM_ARQBAL_PAGE 0x02D40090 /* Reset Source: CORER */
244 #define PF0_MBX_PSM_ARQBAL_PAGE_ARQBAL_LSB_S 0
245 #define PF0_MBX_PSM_ARQBAL_PAGE_ARQBAL_LSB_M MAKEMASK(0x3F, 0)
246 #define PF0_MBX_PSM_ARQBAL_PAGE_ARQBAL_S 6
247 #define PF0_MBX_PSM_ARQBAL_PAGE_ARQBAL_M MAKEMASK(0x3FFFFFF, 6)
248 #define PF0_MBX_PSM_ARQH_PAGE 0x02D40390 /* Reset Source: CORER */
249 #define PF0_MBX_PSM_ARQH_PAGE_ARQH_S 0
250 #define PF0_MBX_PSM_ARQH_PAGE_ARQH_M MAKEMASK(0x3FF, 0)
251 #define PF0_MBX_PSM_ARQLEN_PAGE 0x02D40290 /* Reset Source: PFR */
252 #define PF0_MBX_PSM_ARQLEN_PAGE_ARQLEN_S 0
253 #define PF0_MBX_PSM_ARQLEN_PAGE_ARQLEN_M MAKEMASK(0x3FF, 0)
254 #define PF0_MBX_PSM_ARQLEN_PAGE_ARQVFE_S 28
255 #define PF0_MBX_PSM_ARQLEN_PAGE_ARQVFE_M BIT(28)
256 #define PF0_MBX_PSM_ARQLEN_PAGE_ARQOVFL_S 29
257 #define PF0_MBX_PSM_ARQLEN_PAGE_ARQOVFL_M BIT(29)
258 #define PF0_MBX_PSM_ARQLEN_PAGE_ARQCRIT_S 30
259 #define PF0_MBX_PSM_ARQLEN_PAGE_ARQCRIT_M BIT(30)
260 #define PF0_MBX_PSM_ARQLEN_PAGE_ARQENABLE_S 31
261 #define PF0_MBX_PSM_ARQLEN_PAGE_ARQENABLE_M BIT(31)
262 #define PF0_MBX_PSM_ARQT_PAGE 0x02D40490 /* Reset Source: CORER */
263 #define PF0_MBX_PSM_ARQT_PAGE_ARQT_S 0
264 #define PF0_MBX_PSM_ARQT_PAGE_ARQT_M MAKEMASK(0x3FF, 0)
265 #define PF0_MBX_PSM_ATQBAH_PAGE 0x02D40110 /* Reset Source: CORER */
266 #define PF0_MBX_PSM_ATQBAH_PAGE_ATQBAH_S 0
267 #define PF0_MBX_PSM_ATQBAH_PAGE_ATQBAH_M MAKEMASK(0xFFFFFFFF, 0)
268 #define PF0_MBX_PSM_ATQBAL_PAGE 0x02D40010 /* Reset Source: CORER */
269 #define PF0_MBX_PSM_ATQBAL_PAGE_ATQBAL_S 6
270 #define PF0_MBX_PSM_ATQBAL_PAGE_ATQBAL_M MAKEMASK(0x3FFFFFF, 6)
271 #define PF0_MBX_PSM_ATQH_PAGE 0x02D40310 /* Reset Source: CORER */
272 #define PF0_MBX_PSM_ATQH_PAGE_ATQH_S 0
273 #define PF0_MBX_PSM_ATQH_PAGE_ATQH_M MAKEMASK(0x3FF, 0)
274 #define PF0_MBX_PSM_ATQLEN_PAGE 0x02D40210 /* Reset Source: PFR */
275 #define PF0_MBX_PSM_ATQLEN_PAGE_ATQLEN_S 0
276 #define PF0_MBX_PSM_ATQLEN_PAGE_ATQLEN_M MAKEMASK(0x3FF, 0)
277 #define PF0_MBX_PSM_ATQLEN_PAGE_ATQVFE_S 28
278 #define PF0_MBX_PSM_ATQLEN_PAGE_ATQVFE_M BIT(28)
279 #define PF0_MBX_PSM_ATQLEN_PAGE_ATQOVFL_S 29
280 #define PF0_MBX_PSM_ATQLEN_PAGE_ATQOVFL_M BIT(29)
281 #define PF0_MBX_PSM_ATQLEN_PAGE_ATQCRIT_S 30
282 #define PF0_MBX_PSM_ATQLEN_PAGE_ATQCRIT_M BIT(30)
283 #define PF0_MBX_PSM_ATQLEN_PAGE_ATQENABLE_S 31
284 #define PF0_MBX_PSM_ATQLEN_PAGE_ATQENABLE_M BIT(31)
285 #define PF0_MBX_PSM_ATQT_PAGE 0x02D40410 /* Reset Source: CORER */
286 #define PF0_MBX_PSM_ATQT_PAGE_ATQT_S 0
287 #define PF0_MBX_PSM_ATQT_PAGE_ATQT_M MAKEMASK(0x3FF, 0)
288 #define PF0_SB_CPM_ARQBAH_PAGE 0x02D801A0 /* Reset Source: CORER */
289 #define PF0_SB_CPM_ARQBAH_PAGE_ARQBAH_S 0
290 #define PF0_SB_CPM_ARQBAH_PAGE_ARQBAH_M MAKEMASK(0xFFFFFFFF, 0)
291 #define PF0_SB_CPM_ARQBAL_PAGE 0x02D800A0 /* Reset Source: CORER */
292 #define PF0_SB_CPM_ARQBAL_PAGE_ARQBAL_LSB_S 0
293 #define PF0_SB_CPM_ARQBAL_PAGE_ARQBAL_LSB_M MAKEMASK(0x3F, 0)
294 #define PF0_SB_CPM_ARQBAL_PAGE_ARQBAL_S 6
295 #define PF0_SB_CPM_ARQBAL_PAGE_ARQBAL_M MAKEMASK(0x3FFFFFF, 6)
296 #define PF0_SB_CPM_ARQH_PAGE 0x02D803A0 /* Reset Source: CORER */
297 #define PF0_SB_CPM_ARQH_PAGE_ARQH_S 0
298 #define PF0_SB_CPM_ARQH_PAGE_ARQH_M MAKEMASK(0x3FF, 0)
299 #define PF0_SB_CPM_ARQLEN_PAGE 0x02D802A0 /* Reset Source: PFR */
300 #define PF0_SB_CPM_ARQLEN_PAGE_ARQLEN_S 0
301 #define PF0_SB_CPM_ARQLEN_PAGE_ARQLEN_M MAKEMASK(0x3FF, 0)
302 #define PF0_SB_CPM_ARQLEN_PAGE_ARQVFE_S 28
303 #define PF0_SB_CPM_ARQLEN_PAGE_ARQVFE_M BIT(28)
304 #define PF0_SB_CPM_ARQLEN_PAGE_ARQOVFL_S 29
305 #define PF0_SB_CPM_ARQLEN_PAGE_ARQOVFL_M BIT(29)
306 #define PF0_SB_CPM_ARQLEN_PAGE_ARQCRIT_S 30
307 #define PF0_SB_CPM_ARQLEN_PAGE_ARQCRIT_M BIT(30)
308 #define PF0_SB_CPM_ARQLEN_PAGE_ARQENABLE_S 31
309 #define PF0_SB_CPM_ARQLEN_PAGE_ARQENABLE_M BIT(31)
310 #define PF0_SB_CPM_ARQT_PAGE 0x02D804A0 /* Reset Source: CORER */
311 #define PF0_SB_CPM_ARQT_PAGE_ARQT_S 0
312 #define PF0_SB_CPM_ARQT_PAGE_ARQT_M MAKEMASK(0x3FF, 0)
313 #define PF0_SB_CPM_ATQBAH_PAGE 0x02D80120 /* Reset Source: CORER */
314 #define PF0_SB_CPM_ATQBAH_PAGE_ATQBAH_S 0
315 #define PF0_SB_CPM_ATQBAH_PAGE_ATQBAH_M MAKEMASK(0xFFFFFFFF, 0)
316 #define PF0_SB_CPM_ATQBAL_PAGE 0x02D80020 /* Reset Source: CORER */
317 #define PF0_SB_CPM_ATQBAL_PAGE_ATQBAL_S 6
318 #define PF0_SB_CPM_ATQBAL_PAGE_ATQBAL_M MAKEMASK(0x3FFFFFF, 6)
319 #define PF0_SB_CPM_ATQH_PAGE 0x02D80320 /* Reset Source: CORER */
320 #define PF0_SB_CPM_ATQH_PAGE_ATQH_S 0
321 #define PF0_SB_CPM_ATQH_PAGE_ATQH_M MAKEMASK(0x3FF, 0)
322 #define PF0_SB_CPM_ATQLEN_PAGE 0x02D80220 /* Reset Source: PFR */
323 #define PF0_SB_CPM_ATQLEN_PAGE_ATQLEN_S 0
324 #define PF0_SB_CPM_ATQLEN_PAGE_ATQLEN_M MAKEMASK(0x3FF, 0)
325 #define PF0_SB_CPM_ATQLEN_PAGE_ATQVFE_S 28
326 #define PF0_SB_CPM_ATQLEN_PAGE_ATQVFE_M BIT(28)
327 #define PF0_SB_CPM_ATQLEN_PAGE_ATQOVFL_S 29
328 #define PF0_SB_CPM_ATQLEN_PAGE_ATQOVFL_M BIT(29)
329 #define PF0_SB_CPM_ATQLEN_PAGE_ATQCRIT_S 30
330 #define PF0_SB_CPM_ATQLEN_PAGE_ATQCRIT_M BIT(30)
331 #define PF0_SB_CPM_ATQLEN_PAGE_ATQENABLE_S 31
332 #define PF0_SB_CPM_ATQLEN_PAGE_ATQENABLE_M BIT(31)
333 #define PF0_SB_CPM_ATQT_PAGE 0x02D80420 /* Reset Source: CORER */
334 #define PF0_SB_CPM_ATQT_PAGE_ATQT_S 0
335 #define PF0_SB_CPM_ATQT_PAGE_ATQT_M MAKEMASK(0x3FF, 0)
336 #define PF0_SB_HLP_ARQBAH_PAGE 0x02D001A0 /* Reset Source: CORER */
337 #define PF0_SB_HLP_ARQBAH_PAGE_ARQBAH_S 0
338 #define PF0_SB_HLP_ARQBAH_PAGE_ARQBAH_M MAKEMASK(0xFFFFFFFF, 0)
339 #define PF0_SB_HLP_ARQBAL_PAGE 0x02D000A0 /* Reset Source: CORER */
340 #define PF0_SB_HLP_ARQBAL_PAGE_ARQBAL_LSB_S 0
341 #define PF0_SB_HLP_ARQBAL_PAGE_ARQBAL_LSB_M MAKEMASK(0x3F, 0)
342 #define PF0_SB_HLP_ARQBAL_PAGE_ARQBAL_S 6
343 #define PF0_SB_HLP_ARQBAL_PAGE_ARQBAL_M MAKEMASK(0x3FFFFFF, 6)
344 #define PF0_SB_HLP_ARQH_PAGE 0x02D003A0 /* Reset Source: CORER */
345 #define PF0_SB_HLP_ARQH_PAGE_ARQH_S 0
346 #define PF0_SB_HLP_ARQH_PAGE_ARQH_M MAKEMASK(0x3FF, 0)
347 #define PF0_SB_HLP_ARQLEN_PAGE 0x02D002A0 /* Reset Source: PFR */
348 #define PF0_SB_HLP_ARQLEN_PAGE_ARQLEN_S 0
349 #define PF0_SB_HLP_ARQLEN_PAGE_ARQLEN_M MAKEMASK(0x3FF, 0)
350 #define PF0_SB_HLP_ARQLEN_PAGE_ARQVFE_S 28
351 #define PF0_SB_HLP_ARQLEN_PAGE_ARQVFE_M BIT(28)
352 #define PF0_SB_HLP_ARQLEN_PAGE_ARQOVFL_S 29
353 #define PF0_SB_HLP_ARQLEN_PAGE_ARQOVFL_M BIT(29)
354 #define PF0_SB_HLP_ARQLEN_PAGE_ARQCRIT_S 30
355 #define PF0_SB_HLP_ARQLEN_PAGE_ARQCRIT_M BIT(30)
356 #define PF0_SB_HLP_ARQLEN_PAGE_ARQENABLE_S 31
357 #define PF0_SB_HLP_ARQLEN_PAGE_ARQENABLE_M BIT(31)
358 #define PF0_SB_HLP_ARQT_PAGE 0x02D004A0 /* Reset Source: CORER */
359 #define PF0_SB_HLP_ARQT_PAGE_ARQT_S 0
360 #define PF0_SB_HLP_ARQT_PAGE_ARQT_M MAKEMASK(0x3FF, 0)
361 #define PF0_SB_HLP_ATQBAH_PAGE 0x02D00120 /* Reset Source: CORER */
362 #define PF0_SB_HLP_ATQBAH_PAGE_ATQBAH_S 0
363 #define PF0_SB_HLP_ATQBAH_PAGE_ATQBAH_M MAKEMASK(0xFFFFFFFF, 0)
364 #define PF0_SB_HLP_ATQBAL_PAGE 0x02D00020 /* Reset Source: CORER */
365 #define PF0_SB_HLP_ATQBAL_PAGE_ATQBAL_S 6
366 #define PF0_SB_HLP_ATQBAL_PAGE_ATQBAL_M MAKEMASK(0x3FFFFFF, 6)
367 #define PF0_SB_HLP_ATQH_PAGE 0x02D00320 /* Reset Source: CORER */
368 #define PF0_SB_HLP_ATQH_PAGE_ATQH_S 0
369 #define PF0_SB_HLP_ATQH_PAGE_ATQH_M MAKEMASK(0x3FF, 0)
370 #define PF0_SB_HLP_ATQLEN_PAGE 0x02D00220 /* Reset Source: PFR */
371 #define PF0_SB_HLP_ATQLEN_PAGE_ATQLEN_S 0
372 #define PF0_SB_HLP_ATQLEN_PAGE_ATQLEN_M MAKEMASK(0x3FF, 0)
373 #define PF0_SB_HLP_ATQLEN_PAGE_ATQVFE_S 28
374 #define PF0_SB_HLP_ATQLEN_PAGE_ATQVFE_M BIT(28)
375 #define PF0_SB_HLP_ATQLEN_PAGE_ATQOVFL_S 29
376 #define PF0_SB_HLP_ATQLEN_PAGE_ATQOVFL_M BIT(29)
377 #define PF0_SB_HLP_ATQLEN_PAGE_ATQCRIT_S 30
378 #define PF0_SB_HLP_ATQLEN_PAGE_ATQCRIT_M BIT(30)
379 #define PF0_SB_HLP_ATQLEN_PAGE_ATQENABLE_S 31
380 #define PF0_SB_HLP_ATQLEN_PAGE_ATQENABLE_M BIT(31)
381 #define PF0_SB_HLP_ATQT_PAGE 0x02D00420 /* Reset Source: CORER */
382 #define PF0_SB_HLP_ATQT_PAGE_ATQT_S 0
383 #define PF0_SB_HLP_ATQT_PAGE_ATQT_M MAKEMASK(0x3FF, 0)
384 #define PF0INT_DYN_CTL(_i) (0x03000000 + ((_i) * 4096)) /* _i=0...2047 */ /* Reset Source: CORER */
385 #define PF0INT_DYN_CTL_MAX_INDEX 2047
386 #define PF0INT_DYN_CTL_INTENA_S 0
387 #define PF0INT_DYN_CTL_INTENA_M BIT(0)
388 #define PF0INT_DYN_CTL_CLEARPBA_S 1
389 #define PF0INT_DYN_CTL_CLEARPBA_M BIT(1)
390 #define PF0INT_DYN_CTL_SWINT_TRIG_S 2
391 #define PF0INT_DYN_CTL_SWINT_TRIG_M BIT(2)
392 #define PF0INT_DYN_CTL_ITR_INDX_S 3
393 #define PF0INT_DYN_CTL_ITR_INDX_M MAKEMASK(0x3, 3)
394 #define PF0INT_DYN_CTL_INTERVAL_S 5
395 #define PF0INT_DYN_CTL_INTERVAL_M MAKEMASK(0xFFF, 5)
396 #define PF0INT_DYN_CTL_SW_ITR_INDX_ENA_S 24
397 #define PF0INT_DYN_CTL_SW_ITR_INDX_ENA_M BIT(24)
398 #define PF0INT_DYN_CTL_SW_ITR_INDX_S 25
399 #define PF0INT_DYN_CTL_SW_ITR_INDX_M MAKEMASK(0x3, 25)
400 #define PF0INT_DYN_CTL_WB_ON_ITR_S 30
401 #define PF0INT_DYN_CTL_WB_ON_ITR_M BIT(30)
402 #define PF0INT_DYN_CTL_INTENA_MSK_S 31
403 #define PF0INT_DYN_CTL_INTENA_MSK_M BIT(31)
404 #define PF0INT_ITR_0(_i) (0x03000004 + ((_i) * 4096)) /* _i=0...2047 */ /* Reset Source: CORER */
405 #define PF0INT_ITR_0_MAX_INDEX 2047
406 #define PF0INT_ITR_0_INTERVAL_S 0
407 #define PF0INT_ITR_0_INTERVAL_M MAKEMASK(0xFFF, 0)
408 #define PF0INT_ITR_1(_i) (0x03000008 + ((_i) * 4096)) /* _i=0...2047 */ /* Reset Source: CORER */
409 #define PF0INT_ITR_1_MAX_INDEX 2047
410 #define PF0INT_ITR_1_INTERVAL_S 0
411 #define PF0INT_ITR_1_INTERVAL_M MAKEMASK(0xFFF, 0)
412 #define PF0INT_ITR_2(_i) (0x0300000C + ((_i) * 4096)) /* _i=0...2047 */ /* Reset Source: CORER */
413 #define PF0INT_ITR_2_MAX_INDEX 2047
414 #define PF0INT_ITR_2_INTERVAL_S 0
415 #define PF0INT_ITR_2_INTERVAL_M MAKEMASK(0xFFF, 0)
416 #define PF0INT_OICR_CPM_PAGE 0x02D03000 /* Reset Source: CORER */
417 #define PF0INT_OICR_CPM_PAGE_INTEVENT_S 0
418 #define PF0INT_OICR_CPM_PAGE_INTEVENT_M BIT(0)
419 #define PF0INT_OICR_CPM_PAGE_QUEUE_S 1
420 #define PF0INT_OICR_CPM_PAGE_QUEUE_M BIT(1)
421 #define PF0INT_OICR_CPM_PAGE_RSV1_S 2
422 #define PF0INT_OICR_CPM_PAGE_RSV1_M MAKEMASK(0xFF, 2)
423 #define PF0INT_OICR_CPM_PAGE_HH_COMP_S 10
424 #define PF0INT_OICR_CPM_PAGE_HH_COMP_M BIT(10)
425 #define PF0INT_OICR_CPM_PAGE_TSYN_TX_S 11
426 #define PF0INT_OICR_CPM_PAGE_TSYN_TX_M BIT(11)
427 #define PF0INT_OICR_CPM_PAGE_TSYN_EVNT_S 12
428 #define PF0INT_OICR_CPM_PAGE_TSYN_EVNT_M BIT(12)
429 #define PF0INT_OICR_CPM_PAGE_TSYN_TGT_S 13
430 #define PF0INT_OICR_CPM_PAGE_TSYN_TGT_M BIT(13)
431 #define PF0INT_OICR_CPM_PAGE_HLP_RDY_S 14
432 #define PF0INT_OICR_CPM_PAGE_HLP_RDY_M BIT(14)
433 #define PF0INT_OICR_CPM_PAGE_CPM_RDY_S 15
434 #define PF0INT_OICR_CPM_PAGE_CPM_RDY_M BIT(15)
435 #define PF0INT_OICR_CPM_PAGE_ECC_ERR_S 16
436 #define PF0INT_OICR_CPM_PAGE_ECC_ERR_M BIT(16)
437 #define PF0INT_OICR_CPM_PAGE_RSV2_S 17
438 #define PF0INT_OICR_CPM_PAGE_RSV2_M MAKEMASK(0x3, 17)
439 #define PF0INT_OICR_CPM_PAGE_MAL_DETECT_S 19
440 #define PF0INT_OICR_CPM_PAGE_MAL_DETECT_M BIT(19)
441 #define PF0INT_OICR_CPM_PAGE_GRST_S 20
442 #define PF0INT_OICR_CPM_PAGE_GRST_M BIT(20)
443 #define PF0INT_OICR_CPM_PAGE_PCI_EXCEPTION_S 21
444 #define PF0INT_OICR_CPM_PAGE_PCI_EXCEPTION_M BIT(21)
445 #define PF0INT_OICR_CPM_PAGE_GPIO_S 22
446 #define PF0INT_OICR_CPM_PAGE_GPIO_M BIT(22)
447 #define PF0INT_OICR_CPM_PAGE_RSV3_S 23
448 #define PF0INT_OICR_CPM_PAGE_RSV3_M BIT(23)
449 #define PF0INT_OICR_CPM_PAGE_STORM_DETECT_S 24
450 #define PF0INT_OICR_CPM_PAGE_STORM_DETECT_M BIT(24)
451 #define PF0INT_OICR_CPM_PAGE_LINK_STAT_CHANGE_S 25
452 #define PF0INT_OICR_CPM_PAGE_LINK_STAT_CHANGE_M BIT(25)
453 #define PF0INT_OICR_CPM_PAGE_HMC_ERR_S 26
454 #define PF0INT_OICR_CPM_PAGE_HMC_ERR_M BIT(26)
455 #define PF0INT_OICR_CPM_PAGE_PE_PUSH_S 27
456 #define PF0INT_OICR_CPM_PAGE_PE_PUSH_M BIT(27)
457 #define PF0INT_OICR_CPM_PAGE_PE_CRITERR_S 28
458 #define PF0INT_OICR_CPM_PAGE_PE_CRITERR_M BIT(28)
459 #define PF0INT_OICR_CPM_PAGE_VFLR_S 29
460 #define PF0INT_OICR_CPM_PAGE_VFLR_M BIT(29)
461 #define PF0INT_OICR_CPM_PAGE_XLR_HW_DONE_S 30
462 #define PF0INT_OICR_CPM_PAGE_XLR_HW_DONE_M BIT(30)
463 #define PF0INT_OICR_CPM_PAGE_SWINT_S 31
464 #define PF0INT_OICR_CPM_PAGE_SWINT_M BIT(31)
465 #define PF0INT_OICR_ENA_CPM_PAGE 0x02D03100 /* Reset Source: CORER */
466 #define PF0INT_OICR_ENA_CPM_PAGE_RSV0_S 0
467 #define PF0INT_OICR_ENA_CPM_PAGE_RSV0_M BIT(0)
468 #define PF0INT_OICR_ENA_CPM_PAGE_INT_ENA_S 1
469 #define PF0INT_OICR_ENA_CPM_PAGE_INT_ENA_M MAKEMASK(0x7FFFFFFF, 1)
470 #define PF0INT_OICR_ENA_HLP_PAGE 0x02D01100 /* Reset Source: CORER */
471 #define PF0INT_OICR_ENA_HLP_PAGE_RSV0_S 0
472 #define PF0INT_OICR_ENA_HLP_PAGE_RSV0_M BIT(0)
473 #define PF0INT_OICR_ENA_HLP_PAGE_INT_ENA_S 1
474 #define PF0INT_OICR_ENA_HLP_PAGE_INT_ENA_M MAKEMASK(0x7FFFFFFF, 1)
475 #define PF0INT_OICR_ENA_PSM_PAGE 0x02D02100 /* Reset Source: CORER */
476 #define PF0INT_OICR_ENA_PSM_PAGE_RSV0_S 0
477 #define PF0INT_OICR_ENA_PSM_PAGE_RSV0_M BIT(0)
478 #define PF0INT_OICR_ENA_PSM_PAGE_INT_ENA_S 1
479 #define PF0INT_OICR_ENA_PSM_PAGE_INT_ENA_M MAKEMASK(0x7FFFFFFF, 1)
480 #define PF0INT_OICR_HLP_PAGE 0x02D01000 /* Reset Source: CORER */
481 #define PF0INT_OICR_HLP_PAGE_INTEVENT_S 0
482 #define PF0INT_OICR_HLP_PAGE_INTEVENT_M BIT(0)
483 #define PF0INT_OICR_HLP_PAGE_QUEUE_S 1
484 #define PF0INT_OICR_HLP_PAGE_QUEUE_M BIT(1)
485 #define PF0INT_OICR_HLP_PAGE_RSV1_S 2
486 #define PF0INT_OICR_HLP_PAGE_RSV1_M MAKEMASK(0xFF, 2)
487 #define PF0INT_OICR_HLP_PAGE_HH_COMP_S 10
488 #define PF0INT_OICR_HLP_PAGE_HH_COMP_M BIT(10)
489 #define PF0INT_OICR_HLP_PAGE_TSYN_TX_S 11
490 #define PF0INT_OICR_HLP_PAGE_TSYN_TX_M BIT(11)
491 #define PF0INT_OICR_HLP_PAGE_TSYN_EVNT_S 12
492 #define PF0INT_OICR_HLP_PAGE_TSYN_EVNT_M BIT(12)
493 #define PF0INT_OICR_HLP_PAGE_TSYN_TGT_S 13
494 #define PF0INT_OICR_HLP_PAGE_TSYN_TGT_M BIT(13)
495 #define PF0INT_OICR_HLP_PAGE_HLP_RDY_S 14
496 #define PF0INT_OICR_HLP_PAGE_HLP_RDY_M BIT(14)
497 #define PF0INT_OICR_HLP_PAGE_CPM_RDY_S 15
498 #define PF0INT_OICR_HLP_PAGE_CPM_RDY_M BIT(15)
499 #define PF0INT_OICR_HLP_PAGE_ECC_ERR_S 16
500 #define PF0INT_OICR_HLP_PAGE_ECC_ERR_M BIT(16)
501 #define PF0INT_OICR_HLP_PAGE_RSV2_S 17
502 #define PF0INT_OICR_HLP_PAGE_RSV2_M MAKEMASK(0x3, 17)
503 #define PF0INT_OICR_HLP_PAGE_MAL_DETECT_S 19
504 #define PF0INT_OICR_HLP_PAGE_MAL_DETECT_M BIT(19)
505 #define PF0INT_OICR_HLP_PAGE_GRST_S 20
506 #define PF0INT_OICR_HLP_PAGE_GRST_M BIT(20)
507 #define PF0INT_OICR_HLP_PAGE_PCI_EXCEPTION_S 21
508 #define PF0INT_OICR_HLP_PAGE_PCI_EXCEPTION_M BIT(21)
509 #define PF0INT_OICR_HLP_PAGE_GPIO_S 22
510 #define PF0INT_OICR_HLP_PAGE_GPIO_M BIT(22)
511 #define PF0INT_OICR_HLP_PAGE_RSV3_S 23
512 #define PF0INT_OICR_HLP_PAGE_RSV3_M BIT(23)
513 #define PF0INT_OICR_HLP_PAGE_STORM_DETECT_S 24
514 #define PF0INT_OICR_HLP_PAGE_STORM_DETECT_M BIT(24)
515 #define PF0INT_OICR_HLP_PAGE_LINK_STAT_CHANGE_S 25
516 #define PF0INT_OICR_HLP_PAGE_LINK_STAT_CHANGE_M BIT(25)
517 #define PF0INT_OICR_HLP_PAGE_HMC_ERR_S 26
518 #define PF0INT_OICR_HLP_PAGE_HMC_ERR_M BIT(26)
519 #define PF0INT_OICR_HLP_PAGE_PE_PUSH_S 27
520 #define PF0INT_OICR_HLP_PAGE_PE_PUSH_M BIT(27)
521 #define PF0INT_OICR_HLP_PAGE_PE_CRITERR_S 28
522 #define PF0INT_OICR_HLP_PAGE_PE_CRITERR_M BIT(28)
523 #define PF0INT_OICR_HLP_PAGE_VFLR_S 29
524 #define PF0INT_OICR_HLP_PAGE_VFLR_M BIT(29)
525 #define PF0INT_OICR_HLP_PAGE_XLR_HW_DONE_S 30
526 #define PF0INT_OICR_HLP_PAGE_XLR_HW_DONE_M BIT(30)
527 #define PF0INT_OICR_HLP_PAGE_SWINT_S 31
528 #define PF0INT_OICR_HLP_PAGE_SWINT_M BIT(31)
529 #define PF0INT_OICR_PSM_PAGE 0x02D02000 /* Reset Source: CORER */
530 #define PF0INT_OICR_PSM_PAGE_INTEVENT_S 0
531 #define PF0INT_OICR_PSM_PAGE_INTEVENT_M BIT(0)
532 #define PF0INT_OICR_PSM_PAGE_QUEUE_S 1
533 #define PF0INT_OICR_PSM_PAGE_QUEUE_M BIT(1)
534 #define PF0INT_OICR_PSM_PAGE_RSV1_S 2
535 #define PF0INT_OICR_PSM_PAGE_RSV1_M MAKEMASK(0xFF, 2)
536 #define PF0INT_OICR_PSM_PAGE_HH_COMP_S 10
537 #define PF0INT_OICR_PSM_PAGE_HH_COMP_M BIT(10)
538 #define PF0INT_OICR_PSM_PAGE_TSYN_TX_S 11
539 #define PF0INT_OICR_PSM_PAGE_TSYN_TX_M BIT(11)
540 #define PF0INT_OICR_PSM_PAGE_TSYN_EVNT_S 12
541 #define PF0INT_OICR_PSM_PAGE_TSYN_EVNT_M BIT(12)
542 #define PF0INT_OICR_PSM_PAGE_TSYN_TGT_S 13
543 #define PF0INT_OICR_PSM_PAGE_TSYN_TGT_M BIT(13)
544 #define PF0INT_OICR_PSM_PAGE_HLP_RDY_S 14
545 #define PF0INT_OICR_PSM_PAGE_HLP_RDY_M BIT(14)
546 #define PF0INT_OICR_PSM_PAGE_CPM_RDY_S 15
547 #define PF0INT_OICR_PSM_PAGE_CPM_RDY_M BIT(15)
548 #define PF0INT_OICR_PSM_PAGE_ECC_ERR_S 16
549 #define PF0INT_OICR_PSM_PAGE_ECC_ERR_M BIT(16)
550 #define PF0INT_OICR_PSM_PAGE_RSV2_S 17
551 #define PF0INT_OICR_PSM_PAGE_RSV2_M MAKEMASK(0x3, 17)
552 #define PF0INT_OICR_PSM_PAGE_MAL_DETECT_S 19
553 #define PF0INT_OICR_PSM_PAGE_MAL_DETECT_M BIT(19)
554 #define PF0INT_OICR_PSM_PAGE_GRST_S 20
555 #define PF0INT_OICR_PSM_PAGE_GRST_M BIT(20)
556 #define PF0INT_OICR_PSM_PAGE_PCI_EXCEPTION_S 21
557 #define PF0INT_OICR_PSM_PAGE_PCI_EXCEPTION_M BIT(21)
558 #define PF0INT_OICR_PSM_PAGE_GPIO_S 22
559 #define PF0INT_OICR_PSM_PAGE_GPIO_M BIT(22)
560 #define PF0INT_OICR_PSM_PAGE_RSV3_S 23
561 #define PF0INT_OICR_PSM_PAGE_RSV3_M BIT(23)
562 #define PF0INT_OICR_PSM_PAGE_STORM_DETECT_S 24
563 #define PF0INT_OICR_PSM_PAGE_STORM_DETECT_M BIT(24)
564 #define PF0INT_OICR_PSM_PAGE_LINK_STAT_CHANGE_S 25
565 #define PF0INT_OICR_PSM_PAGE_LINK_STAT_CHANGE_M BIT(25)
566 #define PF0INT_OICR_PSM_PAGE_HMC_ERR_S 26
567 #define PF0INT_OICR_PSM_PAGE_HMC_ERR_M BIT(26)
568 #define PF0INT_OICR_PSM_PAGE_PE_PUSH_S 27
569 #define PF0INT_OICR_PSM_PAGE_PE_PUSH_M BIT(27)
570 #define PF0INT_OICR_PSM_PAGE_PE_CRITERR_S 28
571 #define PF0INT_OICR_PSM_PAGE_PE_CRITERR_M BIT(28)
572 #define PF0INT_OICR_PSM_PAGE_VFLR_S 29
573 #define PF0INT_OICR_PSM_PAGE_VFLR_M BIT(29)
574 #define PF0INT_OICR_PSM_PAGE_XLR_HW_DONE_S 30
575 #define PF0INT_OICR_PSM_PAGE_XLR_HW_DONE_M BIT(30)
576 #define PF0INT_OICR_PSM_PAGE_SWINT_S 31
577 #define PF0INT_OICR_PSM_PAGE_SWINT_M BIT(31)
578 #define QRX_TAIL_PAGE(_QRX) (0x03800000 + ((_QRX) * 4096)) /* _i=0...2047 */ /* Reset Source: CORER */
579 #define QRX_TAIL_PAGE_MAX_INDEX 2047
580 #define QRX_TAIL_PAGE_TAIL_S 0
581 #define QRX_TAIL_PAGE_TAIL_M MAKEMASK(0x1FFF, 0)
582 #define QTX_COMM_DBELL_PAGE(_DBQM) (0x04000000 + ((_DBQM) * 4096)) /* _i=0...16383 */ /* Reset Source: CORER */
583 #define QTX_COMM_DBELL_PAGE_MAX_INDEX 16383
584 #define QTX_COMM_DBELL_PAGE_QTX_COMM_DBELL_S 0
585 #define QTX_COMM_DBELL_PAGE_QTX_COMM_DBELL_M MAKEMASK(0xFFFFFFFF, 0)
586 #define QTX_COMM_DBLQ_DBELL_PAGE(_DBLQ) (0x02F00000 + ((_DBLQ) * 4096)) /* _i=0...255 */ /* Reset Source: CORER */
587 #define QTX_COMM_DBLQ_DBELL_PAGE_MAX_INDEX 255
588 #define QTX_COMM_DBLQ_DBELL_PAGE_TAIL_S 0
589 #define QTX_COMM_DBLQ_DBELL_PAGE_TAIL_M MAKEMASK(0x1FFF, 0)
590 #define VSI_MBX_ARQBAH(_VSI) (0x02000018 + ((_VSI) * 4096)) /* _i=0...767 */ /* Reset Source: CORER */
591 #define VSI_MBX_ARQBAH_MAX_INDEX 767
592 #define VSI_MBX_ARQBAH_ARQBAH_S 0
593 #define VSI_MBX_ARQBAH_ARQBAH_M MAKEMASK(0xFFFFFFFF, 0)
594 #define VSI_MBX_ARQBAL(_VSI) (0x02000014 + ((_VSI) * 4096)) /* _i=0...767 */ /* Reset Source: CORER */
595 #define VSI_MBX_ARQBAL_MAX_INDEX 767
596 #define VSI_MBX_ARQBAL_ARQBAL_LSB_S 0
597 #define VSI_MBX_ARQBAL_ARQBAL_LSB_M MAKEMASK(0x3F, 0)
598 #define VSI_MBX_ARQBAL_ARQBAL_S 6
599 #define VSI_MBX_ARQBAL_ARQBAL_M MAKEMASK(0x3FFFFFF, 6)
600 #define VSI_MBX_ARQH(_VSI) (0x02000020 + ((_VSI) * 4096)) /* _i=0...767 */ /* Reset Source: CORER */
601 #define VSI_MBX_ARQH_MAX_INDEX 767
602 #define VSI_MBX_ARQH_ARQH_S 0
603 #define VSI_MBX_ARQH_ARQH_M MAKEMASK(0x3FF, 0)
604 #define VSI_MBX_ARQLEN(_VSI) (0x0200001C + ((_VSI) * 4096)) /* _i=0...767 */ /* Reset Source: PFR */
605 #define VSI_MBX_ARQLEN_MAX_INDEX 767
606 #define VSI_MBX_ARQLEN_ARQLEN_S 0
607 #define VSI_MBX_ARQLEN_ARQLEN_M MAKEMASK(0x3FF, 0)
608 #define VSI_MBX_ARQLEN_ARQVFE_S 28
609 #define VSI_MBX_ARQLEN_ARQVFE_M BIT(28)
610 #define VSI_MBX_ARQLEN_ARQOVFL_S 29
611 #define VSI_MBX_ARQLEN_ARQOVFL_M BIT(29)
612 #define VSI_MBX_ARQLEN_ARQCRIT_S 30
613 #define VSI_MBX_ARQLEN_ARQCRIT_M BIT(30)
614 #define VSI_MBX_ARQLEN_ARQENABLE_S 31
615 #define VSI_MBX_ARQLEN_ARQENABLE_M BIT(31)
616 #define VSI_MBX_ARQT(_VSI) (0x02000024 + ((_VSI) * 4096)) /* _i=0...767 */ /* Reset Source: CORER */
617 #define VSI_MBX_ARQT_MAX_INDEX 767
618 #define VSI_MBX_ARQT_ARQT_S 0
619 #define VSI_MBX_ARQT_ARQT_M MAKEMASK(0x3FF, 0)
620 #define VSI_MBX_ATQBAH(_VSI) (0x02000004 + ((_VSI) * 4096)) /* _i=0...767 */ /* Reset Source: CORER */
621 #define VSI_MBX_ATQBAH_MAX_INDEX 767
622 #define VSI_MBX_ATQBAH_ATQBAH_S 0
623 #define VSI_MBX_ATQBAH_ATQBAH_M MAKEMASK(0xFFFFFFFF, 0)
624 #define VSI_MBX_ATQBAL(_VSI) (0x02000000 + ((_VSI) * 4096)) /* _i=0...767 */ /* Reset Source: CORER */
625 #define VSI_MBX_ATQBAL_MAX_INDEX 767
626 #define VSI_MBX_ATQBAL_ATQBAL_S 6
627 #define VSI_MBX_ATQBAL_ATQBAL_M MAKEMASK(0x3FFFFFF, 6)
628 #define VSI_MBX_ATQH(_VSI) (0x0200000C + ((_VSI) * 4096)) /* _i=0...767 */ /* Reset Source: CORER */
629 #define VSI_MBX_ATQH_MAX_INDEX 767
630 #define VSI_MBX_ATQH_ATQH_S 0
631 #define VSI_MBX_ATQH_ATQH_M MAKEMASK(0x3FF, 0)
632 #define VSI_MBX_ATQLEN(_VSI) (0x02000008 + ((_VSI) * 4096)) /* _i=0...767 */ /* Reset Source: PFR */
633 #define VSI_MBX_ATQLEN_MAX_INDEX 767
634 #define VSI_MBX_ATQLEN_ATQLEN_S 0
635 #define VSI_MBX_ATQLEN_ATQLEN_M MAKEMASK(0x3FF, 0)
636 #define VSI_MBX_ATQLEN_ATQVFE_S 28
637 #define VSI_MBX_ATQLEN_ATQVFE_M BIT(28)
638 #define VSI_MBX_ATQLEN_ATQOVFL_S 29
639 #define VSI_MBX_ATQLEN_ATQOVFL_M BIT(29)
640 #define VSI_MBX_ATQLEN_ATQCRIT_S 30
641 #define VSI_MBX_ATQLEN_ATQCRIT_M BIT(30)
642 #define VSI_MBX_ATQLEN_ATQENABLE_S 31
643 #define VSI_MBX_ATQLEN_ATQENABLE_M BIT(31)
644 #define VSI_MBX_ATQT(_VSI) (0x02000010 + ((_VSI) * 4096)) /* _i=0...767 */ /* Reset Source: CORER */
645 #define VSI_MBX_ATQT_MAX_INDEX 767
646 #define VSI_MBX_ATQT_ATQT_S 0
647 #define VSI_MBX_ATQT_ATQT_M MAKEMASK(0x3FF, 0)
648 #define GL_ACL_ACCESS_CMD 0x00391000 /* Reset Source: CORER */
649 #define GL_ACL_ACCESS_CMD_TABLE_ID_S 0
650 #define GL_ACL_ACCESS_CMD_TABLE_ID_M MAKEMASK(0xFF, 0)
651 #define GL_ACL_ACCESS_CMD_ENTRY_INDEX_S 8
652 #define GL_ACL_ACCESS_CMD_ENTRY_INDEX_M MAKEMASK(0xFFF, 8)
653 #define GL_ACL_ACCESS_CMD_OPERATION_S 20
654 #define GL_ACL_ACCESS_CMD_OPERATION_M BIT(20)
655 #define GL_ACL_ACCESS_CMD_OBJ_TYPE_S 24
656 #define GL_ACL_ACCESS_CMD_OBJ_TYPE_M MAKEMASK(0xF, 24)
657 #define GL_ACL_ACCESS_CMD_EXECUTE_S 31
658 #define GL_ACL_ACCESS_CMD_EXECUTE_M BIT(31)
659 #define GL_ACL_ACCESS_STATUS 0x00391004 /* Reset Source: CORER */
660 #define GL_ACL_ACCESS_STATUS_BUSY_S 0
661 #define GL_ACL_ACCESS_STATUS_BUSY_M BIT(0)
662 #define GL_ACL_ACCESS_STATUS_DONE_S 1
663 #define GL_ACL_ACCESS_STATUS_DONE_M BIT(1)
664 #define GL_ACL_ACCESS_STATUS_ERROR_S 2
665 #define GL_ACL_ACCESS_STATUS_ERROR_M BIT(2)
666 #define GL_ACL_ACCESS_STATUS_OPERATION_S 3
667 #define GL_ACL_ACCESS_STATUS_OPERATION_M BIT(3)
668 #define GL_ACL_ACCESS_STATUS_ERROR_CODE_S 4
669 #define GL_ACL_ACCESS_STATUS_ERROR_CODE_M MAKEMASK(0xF, 4)
670 #define GL_ACL_ACCESS_STATUS_TABLE_ID_S 8
671 #define GL_ACL_ACCESS_STATUS_TABLE_ID_M MAKEMASK(0xFF, 8)
672 #define GL_ACL_ACCESS_STATUS_ENTRY_INDEX_S 16
673 #define GL_ACL_ACCESS_STATUS_ENTRY_INDEX_M MAKEMASK(0xFFF, 16)
674 #define GL_ACL_ACCESS_STATUS_OBJ_TYPE_S 28
675 #define GL_ACL_ACCESS_STATUS_OBJ_TYPE_M MAKEMASK(0xF, 28)
676 #define GL_ACL_ACTMEM_ACT(_i) (0x00393824 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */
677 #define GL_ACL_ACTMEM_ACT_MAX_INDEX 1
678 #define GL_ACL_ACTMEM_ACT_VALUE_S 0
679 #define GL_ACL_ACTMEM_ACT_VALUE_M MAKEMASK(0xFFFF, 0)
680 #define GL_ACL_ACTMEM_ACT_MDID_S 20
681 #define GL_ACL_ACTMEM_ACT_MDID_M MAKEMASK(0x3F, 20)
682 #define GL_ACL_ACTMEM_ACT_PRIORITY_S 28
683 #define GL_ACL_ACTMEM_ACT_PRIORITY_M MAKEMASK(0x7, 28)
684 #define GL_ACL_CHICKEN_REGISTER 0x00393810 /* Reset Source: CORER */
685 #define GL_ACL_CHICKEN_REGISTER_TCAM_DATA_POL_CH_S 0
686 #define GL_ACL_CHICKEN_REGISTER_TCAM_DATA_POL_CH_M BIT(0)
687 #define GL_ACL_CHICKEN_REGISTER_TCAM_ADDR_POL_CH_S 1
688 #define GL_ACL_CHICKEN_REGISTER_TCAM_ADDR_POL_CH_M BIT(1)
689 #define GL_ACL_DEFAULT_ACT(_i) (0x00391168 + ((_i) * 4)) /* _i=0...15 */ /* Reset Source: CORER */
690 #define GL_ACL_DEFAULT_ACT_MAX_INDEX 15
691 #define GL_ACL_DEFAULT_ACT_VALUE_S 0
692 #define GL_ACL_DEFAULT_ACT_VALUE_M MAKEMASK(0xFFFF, 0)
693 #define GL_ACL_DEFAULT_ACT_MDID_S 20
694 #define GL_ACL_DEFAULT_ACT_MDID_M MAKEMASK(0x3F, 20)
695 #define GL_ACL_DEFAULT_ACT_PRIORITY_S 28
696 #define GL_ACL_DEFAULT_ACT_PRIORITY_M MAKEMASK(0x7, 28)
697 #define GL_ACL_PROFILE_BWSB_SEL(_i) (0x00391008 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
698 #define GL_ACL_PROFILE_BWSB_SEL_MAX_INDEX 31
699 #define GL_ACL_PROFILE_BWSB_SEL_BSB_SRC_OFF_S 0
700 #define GL_ACL_PROFILE_BWSB_SEL_BSB_SRC_OFF_M MAKEMASK(0x3F, 0)
701 #define GL_ACL_PROFILE_BWSB_SEL_WSB_SRC_OFF_S 8
702 #define GL_ACL_PROFILE_BWSB_SEL_WSB_SRC_OFF_M MAKEMASK(0x1F, 8)
703 #define GL_ACL_PROFILE_DWSB_SEL(_i) (0x00391088 + ((_i) * 4)) /* _i=0...15 */ /* Reset Source: CORER */
704 #define GL_ACL_PROFILE_DWSB_SEL_MAX_INDEX 15
705 #define GL_ACL_PROFILE_DWSB_SEL_DWORD_SEL_OFF_S 0
706 #define GL_ACL_PROFILE_DWSB_SEL_DWORD_SEL_OFF_M MAKEMASK(0xF, 0)
707 #define GL_ACL_PROFILE_PF_CFG(_i) (0x003910C8 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
708 #define GL_ACL_PROFILE_PF_CFG_MAX_INDEX 7
709 #define GL_ACL_PROFILE_PF_CFG_SCEN_SEL_S 0
710 #define GL_ACL_PROFILE_PF_CFG_SCEN_SEL_M MAKEMASK(0x3F, 0)
711 #define GL_ACL_PROFILE_RC_CFG(_i) (0x003910E8 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
712 #define GL_ACL_PROFILE_RC_CFG_MAX_INDEX 7
713 #define GL_ACL_PROFILE_RC_CFG_LOW_BOUND_S 0
714 #define GL_ACL_PROFILE_RC_CFG_LOW_BOUND_M MAKEMASK(0xFFFF, 0)
715 #define GL_ACL_PROFILE_RC_CFG_HIGH_BOUND_S 16
716 #define GL_ACL_PROFILE_RC_CFG_HIGH_BOUND_M MAKEMASK(0xFFFF, 16)
717 #define GL_ACL_PROFILE_RCF_MASK(_i) (0x00391108 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
718 #define GL_ACL_PROFILE_RCF_MASK_MAX_INDEX 7
719 #define GL_ACL_PROFILE_RCF_MASK_MASK_S 0
720 #define GL_ACL_PROFILE_RCF_MASK_MASK_M MAKEMASK(0xFFFF, 0)
721 #define GL_ACL_SCENARIO_ACT_CFG(_i) (0x003938AC + ((_i) * 4)) /* _i=0...19 */ /* Reset Source: CORER */
722 #define GL_ACL_SCENARIO_ACT_CFG_MAX_INDEX 19
723 #define GL_ACL_SCENARIO_ACT_CFG_ACTMEM_SEL_S 0
724 #define GL_ACL_SCENARIO_ACT_CFG_ACTMEM_SEL_M MAKEMASK(0xF, 0)
725 #define GL_ACL_SCENARIO_ACT_CFG_ACTMEM_EN_S 8
726 #define GL_ACL_SCENARIO_ACT_CFG_ACTMEM_EN_M BIT(8)
727 #define GL_ACL_SCENARIO_CFG_H(_i) (0x0039386C + ((_i) * 4)) /* _i=0...15 */ /* Reset Source: CORER */
728 #define GL_ACL_SCENARIO_CFG_H_MAX_INDEX 15
729 #define GL_ACL_SCENARIO_CFG_H_SELECT4_S 0
730 #define GL_ACL_SCENARIO_CFG_H_SELECT4_M MAKEMASK(0x1F, 0)
731 #define GL_ACL_SCENARIO_CFG_H_CHUNKMASK_S 8
732 #define GL_ACL_SCENARIO_CFG_H_CHUNKMASK_M MAKEMASK(0xFF, 8)
733 #define GL_ACL_SCENARIO_CFG_H_START_COMPARE_S 24
734 #define GL_ACL_SCENARIO_CFG_H_START_COMPARE_M BIT(24)
735 #define GL_ACL_SCENARIO_CFG_H_START_SET_S 28
736 #define GL_ACL_SCENARIO_CFG_H_START_SET_M BIT(28)
737 #define GL_ACL_SCENARIO_CFG_L(_i) (0x0039382C + ((_i) * 4)) /* _i=0...15 */ /* Reset Source: CORER */
738 #define GL_ACL_SCENARIO_CFG_L_MAX_INDEX 15
739 #define GL_ACL_SCENARIO_CFG_L_SELECT0_S 0
740 #define GL_ACL_SCENARIO_CFG_L_SELECT0_M MAKEMASK(0x7F, 0)
741 #define GL_ACL_SCENARIO_CFG_L_SELECT1_S 8
742 #define GL_ACL_SCENARIO_CFG_L_SELECT1_M MAKEMASK(0x7F, 8)
743 #define GL_ACL_SCENARIO_CFG_L_SELECT2_S 16
744 #define GL_ACL_SCENARIO_CFG_L_SELECT2_M MAKEMASK(0x7F, 16)
745 #define GL_ACL_SCENARIO_CFG_L_SELECT3_S 24
746 #define GL_ACL_SCENARIO_CFG_L_SELECT3_M MAKEMASK(0x7F, 24)
747 #define GL_ACL_TCAM_KEY_H 0x00393818 /* Reset Source: CORER */
748 #define GL_ACL_TCAM_KEY_H_GL_ACL_FFU_TCAM_KEY_H_S 0
749 #define GL_ACL_TCAM_KEY_H_GL_ACL_FFU_TCAM_KEY_H_M MAKEMASK(0xFF, 0)
750 #define GL_ACL_TCAM_KEY_INV_H 0x00393820 /* Reset Source: CORER */
751 #define GL_ACL_TCAM_KEY_INV_H_GL_ACL_FFU_TCAM_KEY_INV_H_S 0
752 #define GL_ACL_TCAM_KEY_INV_H_GL_ACL_FFU_TCAM_KEY_INV_H_M MAKEMASK(0xFF, 0)
753 #define GL_ACL_TCAM_KEY_INV_L 0x0039381C /* Reset Source: CORER */
754 #define GL_ACL_TCAM_KEY_INV_L_GL_ACL_FFU_TCAM_KEY_INV_L_S 0
755 #define GL_ACL_TCAM_KEY_INV_L_GL_ACL_FFU_TCAM_KEY_INV_L_M MAKEMASK(0xFFFFFFFF, 0)
756 #define GL_ACL_TCAM_KEY_L 0x00393814 /* Reset Source: CORER */
757 #define GL_ACL_TCAM_KEY_L_GL_ACL_FFU_TCAM_KEY_L_S 0
758 #define GL_ACL_TCAM_KEY_L_GL_ACL_FFU_TCAM_KEY_L_M MAKEMASK(0xFFFFFFFF, 0)
759 #define VSI_ACL_DEF_SEL(_VSI) (0x00391800 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: CORER */
760 #define VSI_ACL_DEF_SEL_MAX_INDEX 767
761 #define VSI_ACL_DEF_SEL_RX_PROFILE_MISS_SEL_S 0
762 #define VSI_ACL_DEF_SEL_RX_PROFILE_MISS_SEL_M MAKEMASK(0x3, 0)
763 #define VSI_ACL_DEF_SEL_RX_TABLES_MISS_SEL_S 4
764 #define VSI_ACL_DEF_SEL_RX_TABLES_MISS_SEL_M MAKEMASK(0x3, 4)
765 #define VSI_ACL_DEF_SEL_TX_PROFILE_MISS_SEL_S 8
766 #define VSI_ACL_DEF_SEL_TX_PROFILE_MISS_SEL_M MAKEMASK(0x3, 8)
767 #define VSI_ACL_DEF_SEL_TX_TABLES_MISS_SEL_S 12
768 #define VSI_ACL_DEF_SEL_TX_TABLES_MISS_SEL_M MAKEMASK(0x3, 12)
769 #define GL_SWT_L2TAG0(_i) (0x000492A8 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
770 #define GL_SWT_L2TAG0_MAX_INDEX 7
771 #define GL_SWT_L2TAG0_DATA_S 0
772 #define GL_SWT_L2TAG0_DATA_M MAKEMASK(0xFFFFFFFF, 0)
773 #define GL_SWT_L2TAG1(_i) (0x000492C8 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
774 #define GL_SWT_L2TAG1_MAX_INDEX 7
775 #define GL_SWT_L2TAG1_DATA_S 0
776 #define GL_SWT_L2TAG1_DATA_M MAKEMASK(0xFFFFFFFF, 0)
777 #define GL_SWT_L2TAGCTRL(_i) (0x001D2660 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
778 #define GL_SWT_L2TAGCTRL_MAX_INDEX 7
779 #define GL_SWT_L2TAGCTRL_LENGTH_S 0
780 #define GL_SWT_L2TAGCTRL_LENGTH_M MAKEMASK(0x7F, 0)
781 #define GL_SWT_L2TAGCTRL_HAS_UP_S 7
782 #define GL_SWT_L2TAGCTRL_HAS_UP_M BIT(7)
783 #define GL_SWT_L2TAGCTRL_ISVLAN_S 9
784 #define GL_SWT_L2TAGCTRL_ISVLAN_M BIT(9)
785 #define GL_SWT_L2TAGCTRL_INNERUP_S 10
786 #define GL_SWT_L2TAGCTRL_INNERUP_M BIT(10)
787 #define GL_SWT_L2TAGCTRL_OUTERUP_S 11
788 #define GL_SWT_L2TAGCTRL_OUTERUP_M BIT(11)
789 #define GL_SWT_L2TAGCTRL_LONG_S 12
790 #define GL_SWT_L2TAGCTRL_LONG_M BIT(12)
791 #define GL_SWT_L2TAGCTRL_ISMPLS_S 13
792 #define GL_SWT_L2TAGCTRL_ISMPLS_M BIT(13)
793 #define GL_SWT_L2TAGCTRL_ISNSH_S 14
794 #define GL_SWT_L2TAGCTRL_ISNSH_M BIT(14)
795 #define GL_SWT_L2TAGCTRL_ETHERTYPE_S 16
796 #define GL_SWT_L2TAGCTRL_ETHERTYPE_M MAKEMASK(0xFFFF, 16)
797 #define GL_SWT_L2TAGRXEB(_i) (0x00052000 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
798 #define GL_SWT_L2TAGRXEB_MAX_INDEX 7
799 #define GL_SWT_L2TAGRXEB_OFFSET_S 0
800 #define GL_SWT_L2TAGRXEB_OFFSET_M MAKEMASK(0xFF, 0)
801 #define GL_SWT_L2TAGRXEB_LENGTH_S 8
802 #define GL_SWT_L2TAGRXEB_LENGTH_M MAKEMASK(0x3, 8)
803 #define GL_SWT_L2TAGTXIB(_i) (0x000492E8 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
804 #define GL_SWT_L2TAGTXIB_MAX_INDEX 7
805 #define GL_SWT_L2TAGTXIB_OFFSET_S 0
806 #define GL_SWT_L2TAGTXIB_OFFSET_M MAKEMASK(0xFF, 0)
807 #define GL_SWT_L2TAGTXIB_LENGTH_S 8
808 #define GL_SWT_L2TAGTXIB_LENGTH_M MAKEMASK(0x3, 8)
809 #define GLCM_PE_CACHESIZE 0x005046B4 /* Reset Source: CORER */
810 #define GLCM_PE_CACHESIZE_WORD_SIZE_S 0
811 #define GLCM_PE_CACHESIZE_WORD_SIZE_M MAKEMASK(0xFFF, 0)
812 #define GLCM_PE_CACHESIZE_SETS_S 12
813 #define GLCM_PE_CACHESIZE_SETS_M MAKEMASK(0xF, 12)
814 #define GLCM_PE_CACHESIZE_WAYS_S 16
815 #define GLCM_PE_CACHESIZE_WAYS_M MAKEMASK(0x1FF, 16)
816 #define GLCOMM_CQ_CTL(_CQ) (0x000F0000 + ((_CQ) * 4)) /* _i=0...511 */ /* Reset Source: CORER */
817 #define GLCOMM_CQ_CTL_MAX_INDEX 511
818 #define GLCOMM_CQ_CTL_COMP_TYPE_S 0
819 #define GLCOMM_CQ_CTL_COMP_TYPE_M MAKEMASK(0x7, 0)
820 #define GLCOMM_CQ_CTL_CMD_S 4
821 #define GLCOMM_CQ_CTL_CMD_M MAKEMASK(0x7, 4)
822 #define GLCOMM_CQ_CTL_ID_S 16
823 #define GLCOMM_CQ_CTL_ID_M MAKEMASK(0x3FFF, 16)
824 #define GLCOMM_MIN_MAX_PKT 0x000FC064 /* Reset Source: CORER */
825 #define GLCOMM_MIN_MAX_PKT_MAHDL_S 0
826 #define GLCOMM_MIN_MAX_PKT_MAHDL_M MAKEMASK(0x3FFF, 0)
827 #define GLCOMM_MIN_MAX_PKT_MIHDL_S 16
828 #define GLCOMM_MIN_MAX_PKT_MIHDL_M MAKEMASK(0x3F, 16)
829 #define GLCOMM_MIN_MAX_PKT_LSO_COMS_MIHDL_S 22
830 #define GLCOMM_MIN_MAX_PKT_LSO_COMS_MIHDL_M MAKEMASK(0x3FF, 22)
831 #define GLCOMM_PKT_SHAPER_PROF(_i) (0x002D2DA8 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
832 #define GLCOMM_PKT_SHAPER_PROF_MAX_INDEX 7
833 #define GLCOMM_PKT_SHAPER_PROF_PKTCNT_S 0
834 #define GLCOMM_PKT_SHAPER_PROF_PKTCNT_M MAKEMASK(0x3F, 0)
835 #define GLCOMM_QTX_CNTX_CTL 0x002D2DC8 /* Reset Source: CORER */
836 #define GLCOMM_QTX_CNTX_CTL_QUEUE_ID_S 0
837 #define GLCOMM_QTX_CNTX_CTL_QUEUE_ID_M MAKEMASK(0x3FFF, 0)
838 #define GLCOMM_QTX_CNTX_CTL_CMD_S 16
839 #define GLCOMM_QTX_CNTX_CTL_CMD_M MAKEMASK(0x7, 16)
840 #define GLCOMM_QTX_CNTX_CTL_CMD_EXEC_S 19
841 #define GLCOMM_QTX_CNTX_CTL_CMD_EXEC_M BIT(19)
842 #define GLCOMM_QTX_CNTX_DATA(_i) (0x002D2D40 + ((_i) * 4)) /* _i=0...9 */ /* Reset Source: CORER */
843 #define GLCOMM_QTX_CNTX_DATA_MAX_INDEX 9
844 #define GLCOMM_QTX_CNTX_DATA_DATA_S 0
845 #define GLCOMM_QTX_CNTX_DATA_DATA_M MAKEMASK(0xFFFFFFFF, 0)
846 #define GLCOMM_QTX_CNTX_STAT 0x002D2DCC /* Reset Source: CORER */
847 #define GLCOMM_QTX_CNTX_STAT_CMD_IN_PROG_S 0
848 #define GLCOMM_QTX_CNTX_STAT_CMD_IN_PROG_M BIT(0)
849 #define GLCOMM_QUANTA_PROF(_i) (0x002D2D68 + ((_i) * 4)) /* _i=0...15 */ /* Reset Source: CORER */
850 #define GLCOMM_QUANTA_PROF_MAX_INDEX 15
851 #define GLCOMM_QUANTA_PROF_QUANTA_SIZE_S 0
852 #define GLCOMM_QUANTA_PROF_QUANTA_SIZE_M MAKEMASK(0x3FFF, 0)
853 #define GLCOMM_QUANTA_PROF_MAX_CMD_S 16
854 #define GLCOMM_QUANTA_PROF_MAX_CMD_M MAKEMASK(0xFF, 16)
855 #define GLCOMM_QUANTA_PROF_MAX_DESC_S 24
856 #define GLCOMM_QUANTA_PROF_MAX_DESC_M MAKEMASK(0x3F, 24)
857 #define GLLAN_TCLAN_CACHE_CTL 0x000FC0B8 /* Reset Source: CORER */
858 #define GLLAN_TCLAN_CACHE_CTL_MIN_FETCH_THRESH_S 0
859 #define GLLAN_TCLAN_CACHE_CTL_MIN_FETCH_THRESH_M MAKEMASK(0x3F, 0)
860 #define GLLAN_TCLAN_CACHE_CTL_FETCH_CL_ALIGN_S 6
861 #define GLLAN_TCLAN_CACHE_CTL_FETCH_CL_ALIGN_M BIT(6)
862 #define GLLAN_TCLAN_CACHE_CTL_MIN_ALLOC_THRESH_S 7
863 #define GLLAN_TCLAN_CACHE_CTL_MIN_ALLOC_THRESH_M MAKEMASK(0x7F, 7)
864 #define GLLAN_TCLAN_CACHE_CTL_CACHE_ENTRY_CNT_S 14
865 #define GLLAN_TCLAN_CACHE_CTL_CACHE_ENTRY_CNT_M MAKEMASK(0xFF, 14)
866 #define GLLAN_TCLAN_CACHE_CTL_CACHE_DESC_LIM_S 22
867 #define GLLAN_TCLAN_CACHE_CTL_CACHE_DESC_LIM_M MAKEMASK(0x3FF, 22)
868 #define GLTCLAN_CQ_CNTX0(_CQ) (0x000F0800 + ((_CQ) * 4)) /* _i=0...511 */ /* Reset Source: CORER */
869 #define GLTCLAN_CQ_CNTX0_MAX_INDEX 511
870 #define GLTCLAN_CQ_CNTX0_RING_ADDR_LSB_S 0
871 #define GLTCLAN_CQ_CNTX0_RING_ADDR_LSB_M MAKEMASK(0xFFFFFFFF, 0)
872 #define GLTCLAN_CQ_CNTX1(_CQ) (0x000F1000 + ((_CQ) * 4)) /* _i=0...511 */ /* Reset Source: CORER */
873 #define GLTCLAN_CQ_CNTX1_MAX_INDEX 511
874 #define GLTCLAN_CQ_CNTX1_RING_ADDR_MSB_S 0
875 #define GLTCLAN_CQ_CNTX1_RING_ADDR_MSB_M MAKEMASK(0x1FFFFFF, 0)
876 #define GLTCLAN_CQ_CNTX10(_CQ) (0x000F5800 + ((_CQ) * 4)) /* _i=0...511 */ /* Reset Source: CORER */
877 #define GLTCLAN_CQ_CNTX10_MAX_INDEX 511
878 #define GLTCLAN_CQ_CNTX10_CQ_CACHLINE_S 0
879 #define GLTCLAN_CQ_CNTX10_CQ_CACHLINE_M MAKEMASK(0xFFFFFFFF, 0)
880 #define GLTCLAN_CQ_CNTX11(_CQ) (0x000F6000 + ((_CQ) * 4)) /* _i=0...511 */ /* Reset Source: CORER */
881 #define GLTCLAN_CQ_CNTX11_MAX_INDEX 511
882 #define GLTCLAN_CQ_CNTX11_CQ_CACHLINE_S 0
883 #define GLTCLAN_CQ_CNTX11_CQ_CACHLINE_M MAKEMASK(0xFFFFFFFF, 0)
884 #define GLTCLAN_CQ_CNTX12(_CQ) (0x000F6800 + ((_CQ) * 4)) /* _i=0...511 */ /* Reset Source: CORER */
885 #define GLTCLAN_CQ_CNTX12_MAX_INDEX 511
886 #define GLTCLAN_CQ_CNTX12_CQ_CACHLINE_S 0
887 #define GLTCLAN_CQ_CNTX12_CQ_CACHLINE_M MAKEMASK(0xFFFFFFFF, 0)
888 #define GLTCLAN_CQ_CNTX13(_CQ) (0x000F7000 + ((_CQ) * 4)) /* _i=0...511 */ /* Reset Source: CORER */
889 #define GLTCLAN_CQ_CNTX13_MAX_INDEX 511
890 #define GLTCLAN_CQ_CNTX13_CQ_CACHLINE_S 0
891 #define GLTCLAN_CQ_CNTX13_CQ_CACHLINE_M MAKEMASK(0xFFFFFFFF, 0)
892 #define GLTCLAN_CQ_CNTX14(_CQ) (0x000F7800 + ((_CQ) * 4)) /* _i=0...511 */ /* Reset Source: CORER */
893 #define GLTCLAN_CQ_CNTX14_MAX_INDEX 511
894 #define GLTCLAN_CQ_CNTX14_CQ_CACHLINE_S 0
895 #define GLTCLAN_CQ_CNTX14_CQ_CACHLINE_M MAKEMASK(0xFFFFFFFF, 0)
896 #define GLTCLAN_CQ_CNTX15(_CQ) (0x000F8000 + ((_CQ) * 4)) /* _i=0...511 */ /* Reset Source: CORER */
897 #define GLTCLAN_CQ_CNTX15_MAX_INDEX 511
898 #define GLTCLAN_CQ_CNTX15_CQ_CACHLINE_S 0
899 #define GLTCLAN_CQ_CNTX15_CQ_CACHLINE_M MAKEMASK(0xFFFFFFFF, 0)
900 #define GLTCLAN_CQ_CNTX16(_CQ) (0x000F8800 + ((_CQ) * 4)) /* _i=0...511 */ /* Reset Source: CORER */
901 #define GLTCLAN_CQ_CNTX16_MAX_INDEX 511
902 #define GLTCLAN_CQ_CNTX16_CQ_CACHLINE_S 0
903 #define GLTCLAN_CQ_CNTX16_CQ_CACHLINE_M MAKEMASK(0xFFFFFFFF, 0)
904 #define GLTCLAN_CQ_CNTX17(_CQ) (0x000F9000 + ((_CQ) * 4)) /* _i=0...511 */ /* Reset Source: CORER */
905 #define GLTCLAN_CQ_CNTX17_MAX_INDEX 511
906 #define GLTCLAN_CQ_CNTX17_CQ_CACHLINE_S 0
907 #define GLTCLAN_CQ_CNTX17_CQ_CACHLINE_M MAKEMASK(0xFFFFFFFF, 0)
908 #define GLTCLAN_CQ_CNTX18(_CQ) (0x000F9800 + ((_CQ) * 4)) /* _i=0...511 */ /* Reset Source: CORER */
909 #define GLTCLAN_CQ_CNTX18_MAX_INDEX 511
910 #define GLTCLAN_CQ_CNTX18_CQ_CACHLINE_S 0
911 #define GLTCLAN_CQ_CNTX18_CQ_CACHLINE_M MAKEMASK(0xFFFFFFFF, 0)
912 #define GLTCLAN_CQ_CNTX19(_CQ) (0x000FA000 + ((_CQ) * 4)) /* _i=0...511 */ /* Reset Source: CORER */
913 #define GLTCLAN_CQ_CNTX19_MAX_INDEX 511
914 #define GLTCLAN_CQ_CNTX19_CQ_CACHLINE_S 0
915 #define GLTCLAN_CQ_CNTX19_CQ_CACHLINE_M MAKEMASK(0xFFFFFFFF, 0)
916 #define GLTCLAN_CQ_CNTX2(_CQ) (0x000F1800 + ((_CQ) * 4)) /* _i=0...511 */ /* Reset Source: CORER */
917 #define GLTCLAN_CQ_CNTX2_MAX_INDEX 511
918 #define GLTCLAN_CQ_CNTX2_RING_LEN_S 0
919 #define GLTCLAN_CQ_CNTX2_RING_LEN_M MAKEMASK(0x3FFFF, 0)
920 #define GLTCLAN_CQ_CNTX20(_CQ) (0x000FA800 + ((_CQ) * 4)) /* _i=0...511 */ /* Reset Source: CORER */
921 #define GLTCLAN_CQ_CNTX20_MAX_INDEX 511
922 #define GLTCLAN_CQ_CNTX20_CQ_CACHLINE_S 0
923 #define GLTCLAN_CQ_CNTX20_CQ_CACHLINE_M MAKEMASK(0xFFFFFFFF, 0)
924 #define GLTCLAN_CQ_CNTX21(_CQ) (0x000FB000 + ((_CQ) * 4)) /* _i=0...511 */ /* Reset Source: CORER */
925 #define GLTCLAN_CQ_CNTX21_MAX_INDEX 511
926 #define GLTCLAN_CQ_CNTX21_CQ_CACHLINE_S 0
927 #define GLTCLAN_CQ_CNTX21_CQ_CACHLINE_M MAKEMASK(0xFFFFFFFF, 0)
928 #define GLTCLAN_CQ_CNTX3(_CQ) (0x000F2000 + ((_CQ) * 4)) /* _i=0...511 */ /* Reset Source: CORER */
929 #define GLTCLAN_CQ_CNTX3_MAX_INDEX 511
930 #define GLTCLAN_CQ_CNTX3_GENERATION_S 0
931 #define GLTCLAN_CQ_CNTX3_GENERATION_M BIT(0)
932 #define GLTCLAN_CQ_CNTX3_CQ_WR_PTR_S 1
933 #define GLTCLAN_CQ_CNTX3_CQ_WR_PTR_M MAKEMASK(0x3FFFFF, 1)
934 #define GLTCLAN_CQ_CNTX4(_CQ) (0x000F2800 + ((_CQ) * 4)) /* _i=0...511 */ /* Reset Source: CORER */
935 #define GLTCLAN_CQ_CNTX4_MAX_INDEX 511
936 #define GLTCLAN_CQ_CNTX4_PF_NUM_S 0
937 #define GLTCLAN_CQ_CNTX4_PF_NUM_M MAKEMASK(0x7, 0)
938 #define GLTCLAN_CQ_CNTX4_VMVF_NUM_S 3
939 #define GLTCLAN_CQ_CNTX4_VMVF_NUM_M MAKEMASK(0x3FF, 3)
940 #define GLTCLAN_CQ_CNTX4_VMVF_TYPE_S 13
941 #define GLTCLAN_CQ_CNTX4_VMVF_TYPE_M MAKEMASK(0x3, 13)
942 #define GLTCLAN_CQ_CNTX5(_CQ) (0x000F3000 + ((_CQ) * 4)) /* _i=0...511 */ /* Reset Source: CORER */
943 #define GLTCLAN_CQ_CNTX5_MAX_INDEX 511
944 #define GLTCLAN_CQ_CNTX5_TPH_EN_S 0
945 #define GLTCLAN_CQ_CNTX5_TPH_EN_M BIT(0)
946 #define GLTCLAN_CQ_CNTX5_CPU_ID_S 1
947 #define GLTCLAN_CQ_CNTX5_CPU_ID_M MAKEMASK(0xFF, 1)
948 #define GLTCLAN_CQ_CNTX5_FLUSH_ON_ITR_DIS_S 9
949 #define GLTCLAN_CQ_CNTX5_FLUSH_ON_ITR_DIS_M BIT(9)
950 #define GLTCLAN_CQ_CNTX6(_CQ) (0x000F3800 + ((_CQ) * 4)) /* _i=0...511 */ /* Reset Source: CORER */
951 #define GLTCLAN_CQ_CNTX6_MAX_INDEX 511
952 #define GLTCLAN_CQ_CNTX6_CQ_CACHLINE_S 0
953 #define GLTCLAN_CQ_CNTX6_CQ_CACHLINE_M MAKEMASK(0xFFFFFFFF, 0)
954 #define GLTCLAN_CQ_CNTX7(_CQ) (0x000F4000 + ((_CQ) * 4)) /* _i=0...511 */ /* Reset Source: CORER */
955 #define GLTCLAN_CQ_CNTX7_MAX_INDEX 511
956 #define GLTCLAN_CQ_CNTX7_CQ_CACHLINE_S 0
957 #define GLTCLAN_CQ_CNTX7_CQ_CACHLINE_M MAKEMASK(0xFFFFFFFF, 0)
958 #define GLTCLAN_CQ_CNTX8(_CQ) (0x000F4800 + ((_CQ) * 4)) /* _i=0...511 */ /* Reset Source: CORER */
959 #define GLTCLAN_CQ_CNTX8_MAX_INDEX 511
960 #define GLTCLAN_CQ_CNTX8_CQ_CACHLINE_S 0
961 #define GLTCLAN_CQ_CNTX8_CQ_CACHLINE_M MAKEMASK(0xFFFFFFFF, 0)
962 #define GLTCLAN_CQ_CNTX9(_CQ) (0x000F5000 + ((_CQ) * 4)) /* _i=0...511 */ /* Reset Source: CORER */
963 #define GLTCLAN_CQ_CNTX9_MAX_INDEX 511
964 #define GLTCLAN_CQ_CNTX9_CQ_CACHLINE_S 0
965 #define GLTCLAN_CQ_CNTX9_CQ_CACHLINE_M MAKEMASK(0xFFFFFFFF, 0)
966 #define QTX_COMM_DBELL(_DBQM) (0x002C0000 + ((_DBQM) * 4)) /* _i=0...16383 */ /* Reset Source: CORER */
967 #define QTX_COMM_DBELL_MAX_INDEX 16383
968 #define QTX_COMM_DBELL_QTX_COMM_DBELL_S 0
969 #define QTX_COMM_DBELL_QTX_COMM_DBELL_M MAKEMASK(0xFFFFFFFF, 0)
970 #define QTX_COMM_DBLQ_CNTX(_i, _DBLQ) (0x002D0000 + ((_i) * 1024 + (_DBLQ) * 4)) /* _i=0...4, _DBLQ=0...255 */ /* Reset Source: CORER */
971 #define QTX_COMM_DBLQ_CNTX_MAX_INDEX 4
972 #define QTX_COMM_DBLQ_CNTX_DATA_S 0
973 #define QTX_COMM_DBLQ_CNTX_DATA_M MAKEMASK(0xFFFFFFFF, 0)
974 #define QTX_COMM_DBLQ_DBELL(_DBLQ) (0x002D1400 + ((_DBLQ) * 4)) /* _i=0...255 */ /* Reset Source: CORER */
975 #define QTX_COMM_DBLQ_DBELL_MAX_INDEX 255
976 #define QTX_COMM_DBLQ_DBELL_TAIL_S 0
977 #define QTX_COMM_DBLQ_DBELL_TAIL_M MAKEMASK(0x1FFF, 0)
978 #define QTX_COMM_HEAD(_DBQM) (0x000E0000 + ((_DBQM) * 4)) /* _i=0...16383 */ /* Reset Source: CORER */
979 #define QTX_COMM_HEAD_MAX_INDEX 16383
980 #define QTX_COMM_HEAD_HEAD_S 0
981 #define QTX_COMM_HEAD_HEAD_M MAKEMASK(0x1FFF, 0)
982 #define QTX_COMM_HEAD_RS_PENDING_S 16
983 #define QTX_COMM_HEAD_RS_PENDING_M BIT(16)
984 #define GL_FW_TOOL_ARQBAH 0x000801C0 /* Reset Source: EMPR */
985 #define GL_FW_TOOL_ARQBAH_ARQBAH_S 0
986 #define GL_FW_TOOL_ARQBAH_ARQBAH_M MAKEMASK(0xFFFFFFFF, 0)
987 #define GL_FW_TOOL_ARQBAL 0x000800C0 /* Reset Source: EMPR */
988 #define GL_FW_TOOL_ARQBAL_ARQBAL_LSB_S 0
989 #define GL_FW_TOOL_ARQBAL_ARQBAL_LSB_M MAKEMASK(0x3F, 0)
990 #define GL_FW_TOOL_ARQBAL_ARQBAL_S 6
991 #define GL_FW_TOOL_ARQBAL_ARQBAL_M MAKEMASK(0x3FFFFFF, 6)
992 #define GL_FW_TOOL_ARQH 0x000803C0 /* Reset Source: EMPR */
993 #define GL_FW_TOOL_ARQH_ARQH_S 0
994 #define GL_FW_TOOL_ARQH_ARQH_M MAKEMASK(0x3FF, 0)
995 #define GL_FW_TOOL_ARQLEN 0x000802C0 /* Reset Source: EMPR */
996 #define GL_FW_TOOL_ARQLEN_ARQLEN_S 0
997 #define GL_FW_TOOL_ARQLEN_ARQLEN_M MAKEMASK(0x3FF, 0)
998 #define GL_FW_TOOL_ARQLEN_ARQVFE_S 28
999 #define GL_FW_TOOL_ARQLEN_ARQVFE_M BIT(28)
1000 #define GL_FW_TOOL_ARQLEN_ARQOVFL_S 29
1001 #define GL_FW_TOOL_ARQLEN_ARQOVFL_M BIT(29)
1002 #define GL_FW_TOOL_ARQLEN_ARQCRIT_S 30
1003 #define GL_FW_TOOL_ARQLEN_ARQCRIT_M BIT(30)
1004 #define GL_FW_TOOL_ARQLEN_ARQENABLE_S 31
1005 #define GL_FW_TOOL_ARQLEN_ARQENABLE_M BIT(31)
1006 #define GL_FW_TOOL_ARQT 0x000804C0 /* Reset Source: EMPR */
1007 #define GL_FW_TOOL_ARQT_ARQT_S 0
1008 #define GL_FW_TOOL_ARQT_ARQT_M MAKEMASK(0x3FF, 0)
1009 #define GL_FW_TOOL_ATQBAH 0x00080140 /* Reset Source: EMPR */
1010 #define GL_FW_TOOL_ATQBAH_ATQBAH_S 0
1011 #define GL_FW_TOOL_ATQBAH_ATQBAH_M MAKEMASK(0xFFFFFFFF, 0)
1012 #define GL_FW_TOOL_ATQBAL 0x00080040 /* Reset Source: EMPR */
1013 #define GL_FW_TOOL_ATQBAL_ATQBAL_LSB_S 0
1014 #define GL_FW_TOOL_ATQBAL_ATQBAL_LSB_M MAKEMASK(0x3F, 0)
1015 #define GL_FW_TOOL_ATQBAL_ATQBAL_S 6
1016 #define GL_FW_TOOL_ATQBAL_ATQBAL_M MAKEMASK(0x3FFFFFF, 6)
1017 #define GL_FW_TOOL_ATQH 0x00080340 /* Reset Source: EMPR */
1018 #define GL_FW_TOOL_ATQH_ATQH_S 0
1019 #define GL_FW_TOOL_ATQH_ATQH_M MAKEMASK(0x3FF, 0)
1020 #define GL_FW_TOOL_ATQLEN 0x00080240 /* Reset Source: EMPR */
1021 #define GL_FW_TOOL_ATQLEN_ATQLEN_S 0
1022 #define GL_FW_TOOL_ATQLEN_ATQLEN_M MAKEMASK(0x3FF, 0)
1023 #define GL_FW_TOOL_ATQLEN_ATQVFE_S 28
1024 #define GL_FW_TOOL_ATQLEN_ATQVFE_M BIT(28)
1025 #define GL_FW_TOOL_ATQLEN_ATQOVFL_S 29
1026 #define GL_FW_TOOL_ATQLEN_ATQOVFL_M BIT(29)
1027 #define GL_FW_TOOL_ATQLEN_ATQCRIT_S 30
1028 #define GL_FW_TOOL_ATQLEN_ATQCRIT_M BIT(30)
1029 #define GL_FW_TOOL_ATQLEN_ATQENABLE_S 31
1030 #define GL_FW_TOOL_ATQLEN_ATQENABLE_M BIT(31)
1031 #define GL_FW_TOOL_ATQT 0x00080440 /* Reset Source: EMPR */
1032 #define GL_FW_TOOL_ATQT_ATQT_S 0
1033 #define GL_FW_TOOL_ATQT_ATQT_M MAKEMASK(0x3FF, 0)
1034 #define GL_MBX_PASID 0x00231EC0 /* Reset Source: CORER */
1035 #define GL_MBX_PASID_PASID_MODE_S 0
1036 #define GL_MBX_PASID_PASID_MODE_M BIT(0)
1037 #define GL_MBX_PASID_PASID_MODE_VALID_S 1
1038 #define GL_MBX_PASID_PASID_MODE_VALID_M BIT(1)
1039 #define PF_FW_ARQBAH 0x00080180 /* Reset Source: EMPR */
1040 #define PF_FW_ARQBAH_ARQBAH_S 0
1041 #define PF_FW_ARQBAH_ARQBAH_M MAKEMASK(0xFFFFFFFF, 0)
1042 #define PF_FW_ARQBAL 0x00080080 /* Reset Source: EMPR */
1043 #define PF_FW_ARQBAL_ARQBAL_LSB_S 0
1044 #define PF_FW_ARQBAL_ARQBAL_LSB_M MAKEMASK(0x3F, 0)
1045 #define PF_FW_ARQBAL_ARQBAL_S 6
1046 #define PF_FW_ARQBAL_ARQBAL_M MAKEMASK(0x3FFFFFF, 6)
1047 #define PF_FW_ARQH 0x00080380 /* Reset Source: EMPR */
1048 #define PF_FW_ARQH_ARQH_S 0
1049 #define PF_FW_ARQH_ARQH_M MAKEMASK(0x3FF, 0)
1050 #define PF_FW_ARQLEN 0x00080280 /* Reset Source: EMPR */
1051 #define PF_FW_ARQLEN_ARQLEN_S 0
1052 #define PF_FW_ARQLEN_ARQLEN_M MAKEMASK(0x3FF, 0)
1053 #define PF_FW_ARQLEN_ARQVFE_S 28
1054 #define PF_FW_ARQLEN_ARQVFE_M BIT(28)
1055 #define PF_FW_ARQLEN_ARQOVFL_S 29
1056 #define PF_FW_ARQLEN_ARQOVFL_M BIT(29)
1057 #define PF_FW_ARQLEN_ARQCRIT_S 30
1058 #define PF_FW_ARQLEN_ARQCRIT_M BIT(30)
1059 #define PF_FW_ARQLEN_ARQENABLE_S 31
1060 #define PF_FW_ARQLEN_ARQENABLE_M BIT(31)
1061 #define PF_FW_ARQT 0x00080480 /* Reset Source: EMPR */
1062 #define PF_FW_ARQT_ARQT_S 0
1063 #define PF_FW_ARQT_ARQT_M MAKEMASK(0x3FF, 0)
1064 #define PF_FW_ATQBAH 0x00080100 /* Reset Source: EMPR */
1065 #define PF_FW_ATQBAH_ATQBAH_S 0
1066 #define PF_FW_ATQBAH_ATQBAH_M MAKEMASK(0xFFFFFFFF, 0)
1067 #define PF_FW_ATQBAL 0x00080000 /* Reset Source: EMPR */
1068 #define PF_FW_ATQBAL_ATQBAL_LSB_S 0
1069 #define PF_FW_ATQBAL_ATQBAL_LSB_M MAKEMASK(0x3F, 0)
1070 #define PF_FW_ATQBAL_ATQBAL_S 6
1071 #define PF_FW_ATQBAL_ATQBAL_M MAKEMASK(0x3FFFFFF, 6)
1072 #define PF_FW_ATQH 0x00080300 /* Reset Source: EMPR */
1073 #define PF_FW_ATQH_ATQH_S 0
1074 #define PF_FW_ATQH_ATQH_M MAKEMASK(0x3FF, 0)
1075 #define PF_FW_ATQLEN 0x00080200 /* Reset Source: EMPR */
1076 #define PF_FW_ATQLEN_ATQLEN_S 0
1077 #define PF_FW_ATQLEN_ATQLEN_M MAKEMASK(0x3FF, 0)
1078 #define PF_FW_ATQLEN_ATQVFE_S 28
1079 #define PF_FW_ATQLEN_ATQVFE_M BIT(28)
1080 #define PF_FW_ATQLEN_ATQOVFL_S 29
1081 #define PF_FW_ATQLEN_ATQOVFL_M BIT(29)
1082 #define PF_FW_ATQLEN_ATQCRIT_S 30
1083 #define PF_FW_ATQLEN_ATQCRIT_M BIT(30)
1084 #define PF_FW_ATQLEN_ATQENABLE_S 31
1085 #define PF_FW_ATQLEN_ATQENABLE_M BIT(31)
1086 #define PF_FW_ATQT 0x00080400 /* Reset Source: EMPR */
1087 #define PF_FW_ATQT_ATQT_S 0
1088 #define PF_FW_ATQT_ATQT_M MAKEMASK(0x3FF, 0)
1089 #define PF_MBX_ARQBAH 0x0022E400 /* Reset Source: CORER */
1090 #define PF_MBX_ARQBAH_ARQBAH_S 0
1091 #define PF_MBX_ARQBAH_ARQBAH_M MAKEMASK(0xFFFFFFFF, 0)
1092 #define PF_MBX_ARQBAL 0x0022E380 /* Reset Source: CORER */
1093 #define PF_MBX_ARQBAL_ARQBAL_LSB_S 0
1094 #define PF_MBX_ARQBAL_ARQBAL_LSB_M MAKEMASK(0x3F, 0)
1095 #define PF_MBX_ARQBAL_ARQBAL_S 6
1096 #define PF_MBX_ARQBAL_ARQBAL_M MAKEMASK(0x3FFFFFF, 6)
1097 #define PF_MBX_ARQH 0x0022E500 /* Reset Source: CORER */
1098 #define PF_MBX_ARQH_ARQH_S 0
1099 #define PF_MBX_ARQH_ARQH_M MAKEMASK(0x3FF, 0)
1100 #define PF_MBX_ARQLEN 0x0022E480 /* Reset Source: PFR */
1101 #define PF_MBX_ARQLEN_ARQLEN_S 0
1102 #define PF_MBX_ARQLEN_ARQLEN_M MAKEMASK(0x3FF, 0)
1103 #define PF_MBX_ARQLEN_ARQVFE_S 28
1104 #define PF_MBX_ARQLEN_ARQVFE_M BIT(28)
1105 #define PF_MBX_ARQLEN_ARQOVFL_S 29
1106 #define PF_MBX_ARQLEN_ARQOVFL_M BIT(29)
1107 #define PF_MBX_ARQLEN_ARQCRIT_S 30
1108 #define PF_MBX_ARQLEN_ARQCRIT_M BIT(30)
1109 #define PF_MBX_ARQLEN_ARQENABLE_S 31
1110 #define PF_MBX_ARQLEN_ARQENABLE_M BIT(31)
1111 #define PF_MBX_ARQT 0x0022E580 /* Reset Source: CORER */
1112 #define PF_MBX_ARQT_ARQT_S 0
1113 #define PF_MBX_ARQT_ARQT_M MAKEMASK(0x3FF, 0)
1114 #define PF_MBX_ATQBAH 0x0022E180 /* Reset Source: CORER */
1115 #define PF_MBX_ATQBAH_ATQBAH_S 0
1116 #define PF_MBX_ATQBAH_ATQBAH_M MAKEMASK(0xFFFFFFFF, 0)
1117 #define PF_MBX_ATQBAL 0x0022E100 /* Reset Source: CORER */
1118 #define PF_MBX_ATQBAL_ATQBAL_S 6
1119 #define PF_MBX_ATQBAL_ATQBAL_M MAKEMASK(0x3FFFFFF, 6)
1120 #define PF_MBX_ATQH 0x0022E280 /* Reset Source: CORER */
1121 #define PF_MBX_ATQH_ATQH_S 0
1122 #define PF_MBX_ATQH_ATQH_M MAKEMASK(0x3FF, 0)
1123 #define PF_MBX_ATQLEN 0x0022E200 /* Reset Source: PFR */
1124 #define PF_MBX_ATQLEN_ATQLEN_S 0
1125 #define PF_MBX_ATQLEN_ATQLEN_M MAKEMASK(0x3FF, 0)
1126 #define PF_MBX_ATQLEN_ATQVFE_S 28
1127 #define PF_MBX_ATQLEN_ATQVFE_M BIT(28)
1128 #define PF_MBX_ATQLEN_ATQOVFL_S 29
1129 #define PF_MBX_ATQLEN_ATQOVFL_M BIT(29)
1130 #define PF_MBX_ATQLEN_ATQCRIT_S 30
1131 #define PF_MBX_ATQLEN_ATQCRIT_M BIT(30)
1132 #define PF_MBX_ATQLEN_ATQENABLE_S 31
1133 #define PF_MBX_ATQLEN_ATQENABLE_M BIT(31)
1134 #define PF_MBX_ATQT 0x0022E300 /* Reset Source: CORER */
1135 #define PF_MBX_ATQT_ATQT_S 0
1136 #define PF_MBX_ATQT_ATQT_M MAKEMASK(0x3FF, 0)
1137 #define PF_SB_ARQBAH 0x0022FF00 /* Reset Source: CORER */
1138 #define PF_SB_ARQBAH_ARQBAH_S 0
1139 #define PF_SB_ARQBAH_ARQBAH_M MAKEMASK(0xFFFFFFFF, 0)
1140 #define PF_SB_ARQBAL 0x0022FE80 /* Reset Source: CORER */
1141 #define PF_SB_ARQBAL_ARQBAL_LSB_S 0
1142 #define PF_SB_ARQBAL_ARQBAL_LSB_M MAKEMASK(0x3F, 0)
1143 #define PF_SB_ARQBAL_ARQBAL_S 6
1144 #define PF_SB_ARQBAL_ARQBAL_M MAKEMASK(0x3FFFFFF, 6)
1145 #define PF_SB_ARQH 0x00230000 /* Reset Source: CORER */
1146 #define PF_SB_ARQH_ARQH_S 0
1147 #define PF_SB_ARQH_ARQH_M MAKEMASK(0x3FF, 0)
1148 #define PF_SB_ARQLEN 0x0022FF80 /* Reset Source: PFR */
1149 #define PF_SB_ARQLEN_ARQLEN_S 0
1150 #define PF_SB_ARQLEN_ARQLEN_M MAKEMASK(0x3FF, 0)
1151 #define PF_SB_ARQLEN_ARQVFE_S 28
1152 #define PF_SB_ARQLEN_ARQVFE_M BIT(28)
1153 #define PF_SB_ARQLEN_ARQOVFL_S 29
1154 #define PF_SB_ARQLEN_ARQOVFL_M BIT(29)
1155 #define PF_SB_ARQLEN_ARQCRIT_S 30
1156 #define PF_SB_ARQLEN_ARQCRIT_M BIT(30)
1157 #define PF_SB_ARQLEN_ARQENABLE_S 31
1158 #define PF_SB_ARQLEN_ARQENABLE_M BIT(31)
1159 #define PF_SB_ARQT 0x00230080 /* Reset Source: CORER */
1160 #define PF_SB_ARQT_ARQT_S 0
1161 #define PF_SB_ARQT_ARQT_M MAKEMASK(0x3FF, 0)
1162 #define PF_SB_ATQBAH 0x0022FC80 /* Reset Source: CORER */
1163 #define PF_SB_ATQBAH_ATQBAH_S 0
1164 #define PF_SB_ATQBAH_ATQBAH_M MAKEMASK(0xFFFFFFFF, 0)
1165 #define PF_SB_ATQBAL 0x0022FC00 /* Reset Source: CORER */
1166 #define PF_SB_ATQBAL_ATQBAL_S 6
1167 #define PF_SB_ATQBAL_ATQBAL_M MAKEMASK(0x3FFFFFF, 6)
1168 #define PF_SB_ATQH 0x0022FD80 /* Reset Source: CORER */
1169 #define PF_SB_ATQH_ATQH_S 0
1170 #define PF_SB_ATQH_ATQH_M MAKEMASK(0x3FF, 0)
1171 #define PF_SB_ATQLEN 0x0022FD00 /* Reset Source: PFR */
1172 #define PF_SB_ATQLEN_ATQLEN_S 0
1173 #define PF_SB_ATQLEN_ATQLEN_M MAKEMASK(0x3FF, 0)
1174 #define PF_SB_ATQLEN_ATQVFE_S 28
1175 #define PF_SB_ATQLEN_ATQVFE_M BIT(28)
1176 #define PF_SB_ATQLEN_ATQOVFL_S 29
1177 #define PF_SB_ATQLEN_ATQOVFL_M BIT(29)
1178 #define PF_SB_ATQLEN_ATQCRIT_S 30
1179 #define PF_SB_ATQLEN_ATQCRIT_M BIT(30)
1180 #define PF_SB_ATQLEN_ATQENABLE_S 31
1181 #define PF_SB_ATQLEN_ATQENABLE_M BIT(31)
1182 #define PF_SB_ATQT 0x0022FE00 /* Reset Source: CORER */
1183 #define PF_SB_ATQT_ATQT_S 0
1184 #define PF_SB_ATQT_ATQT_M MAKEMASK(0x3FF, 0)
1185 #define PF_SB_REM_DEV_CTL 0x002300F0 /* Reset Source: CORER */
1186 #define PF_SB_REM_DEV_CTL_DEST_EN_S 0
1187 #define PF_SB_REM_DEV_CTL_DEST_EN_M MAKEMASK(0xFFFF, 0)
1188 #define PF0_FW_HLP_ARQBAH 0x000801C8 /* Reset Source: EMPR */
1189 #define PF0_FW_HLP_ARQBAH_ARQBAH_S 0
1190 #define PF0_FW_HLP_ARQBAH_ARQBAH_M MAKEMASK(0xFFFFFFFF, 0)
1191 #define PF0_FW_HLP_ARQBAL 0x000800C8 /* Reset Source: EMPR */
1192 #define PF0_FW_HLP_ARQBAL_ARQBAL_LSB_S 0
1193 #define PF0_FW_HLP_ARQBAL_ARQBAL_LSB_M MAKEMASK(0x3F, 0)
1194 #define PF0_FW_HLP_ARQBAL_ARQBAL_S 6
1195 #define PF0_FW_HLP_ARQBAL_ARQBAL_M MAKEMASK(0x3FFFFFF, 6)
1196 #define PF0_FW_HLP_ARQH 0x000803C8 /* Reset Source: EMPR */
1197 #define PF0_FW_HLP_ARQH_ARQH_S 0
1198 #define PF0_FW_HLP_ARQH_ARQH_M MAKEMASK(0x3FF, 0)
1199 #define PF0_FW_HLP_ARQLEN 0x000802C8 /* Reset Source: EMPR */
1200 #define PF0_FW_HLP_ARQLEN_ARQLEN_S 0
1201 #define PF0_FW_HLP_ARQLEN_ARQLEN_M MAKEMASK(0x3FF, 0)
1202 #define PF0_FW_HLP_ARQLEN_ARQVFE_S 28
1203 #define PF0_FW_HLP_ARQLEN_ARQVFE_M BIT(28)
1204 #define PF0_FW_HLP_ARQLEN_ARQOVFL_S 29
1205 #define PF0_FW_HLP_ARQLEN_ARQOVFL_M BIT(29)
1206 #define PF0_FW_HLP_ARQLEN_ARQCRIT_S 30
1207 #define PF0_FW_HLP_ARQLEN_ARQCRIT_M BIT(30)
1208 #define PF0_FW_HLP_ARQLEN_ARQENABLE_S 31
1209 #define PF0_FW_HLP_ARQLEN_ARQENABLE_M BIT(31)
1210 #define PF0_FW_HLP_ARQT 0x000804C8 /* Reset Source: EMPR */
1211 #define PF0_FW_HLP_ARQT_ARQT_S 0
1212 #define PF0_FW_HLP_ARQT_ARQT_M MAKEMASK(0x3FF, 0)
1213 #define PF0_FW_HLP_ATQBAH 0x00080148 /* Reset Source: EMPR */
1214 #define PF0_FW_HLP_ATQBAH_ATQBAH_S 0
1215 #define PF0_FW_HLP_ATQBAH_ATQBAH_M MAKEMASK(0xFFFFFFFF, 0)
1216 #define PF0_FW_HLP_ATQBAL 0x00080048 /* Reset Source: EMPR */
1217 #define PF0_FW_HLP_ATQBAL_ATQBAL_LSB_S 0
1218 #define PF0_FW_HLP_ATQBAL_ATQBAL_LSB_M MAKEMASK(0x3F, 0)
1219 #define PF0_FW_HLP_ATQBAL_ATQBAL_S 6
1220 #define PF0_FW_HLP_ATQBAL_ATQBAL_M MAKEMASK(0x3FFFFFF, 6)
1221 #define PF0_FW_HLP_ATQH 0x00080348 /* Reset Source: EMPR */
1222 #define PF0_FW_HLP_ATQH_ATQH_S 0
1223 #define PF0_FW_HLP_ATQH_ATQH_M MAKEMASK(0x3FF, 0)
1224 #define PF0_FW_HLP_ATQLEN 0x00080248 /* Reset Source: EMPR */
1225 #define PF0_FW_HLP_ATQLEN_ATQLEN_S 0
1226 #define PF0_FW_HLP_ATQLEN_ATQLEN_M MAKEMASK(0x3FF, 0)
1227 #define PF0_FW_HLP_ATQLEN_ATQVFE_S 28
1228 #define PF0_FW_HLP_ATQLEN_ATQVFE_M BIT(28)
1229 #define PF0_FW_HLP_ATQLEN_ATQOVFL_S 29
1230 #define PF0_FW_HLP_ATQLEN_ATQOVFL_M BIT(29)
1231 #define PF0_FW_HLP_ATQLEN_ATQCRIT_S 30
1232 #define PF0_FW_HLP_ATQLEN_ATQCRIT_M BIT(30)
1233 #define PF0_FW_HLP_ATQLEN_ATQENABLE_S 31
1234 #define PF0_FW_HLP_ATQLEN_ATQENABLE_M BIT(31)
1235 #define PF0_FW_HLP_ATQT 0x00080448 /* Reset Source: EMPR */
1236 #define PF0_FW_HLP_ATQT_ATQT_S 0
1237 #define PF0_FW_HLP_ATQT_ATQT_M MAKEMASK(0x3FF, 0)
1238 #define PF0_FW_PSM_ARQBAH 0x000801C4 /* Reset Source: EMPR */
1239 #define PF0_FW_PSM_ARQBAH_ARQBAH_S 0
1240 #define PF0_FW_PSM_ARQBAH_ARQBAH_M MAKEMASK(0xFFFFFFFF, 0)
1241 #define PF0_FW_PSM_ARQBAL 0x000800C4 /* Reset Source: EMPR */
1242 #define PF0_FW_PSM_ARQBAL_ARQBAL_LSB_S 0
1243 #define PF0_FW_PSM_ARQBAL_ARQBAL_LSB_M MAKEMASK(0x3F, 0)
1244 #define PF0_FW_PSM_ARQBAL_ARQBAL_S 6
1245 #define PF0_FW_PSM_ARQBAL_ARQBAL_M MAKEMASK(0x3FFFFFF, 6)
1246 #define PF0_FW_PSM_ARQH 0x000803C4 /* Reset Source: EMPR */
1247 #define PF0_FW_PSM_ARQH_ARQH_S 0
1248 #define PF0_FW_PSM_ARQH_ARQH_M MAKEMASK(0x3FF, 0)
1249 #define PF0_FW_PSM_ARQLEN 0x000802C4 /* Reset Source: EMPR */
1250 #define PF0_FW_PSM_ARQLEN_ARQLEN_S 0
1251 #define PF0_FW_PSM_ARQLEN_ARQLEN_M MAKEMASK(0x3FF, 0)
1252 #define PF0_FW_PSM_ARQLEN_ARQVFE_S 28
1253 #define PF0_FW_PSM_ARQLEN_ARQVFE_M BIT(28)
1254 #define PF0_FW_PSM_ARQLEN_ARQOVFL_S 29
1255 #define PF0_FW_PSM_ARQLEN_ARQOVFL_M BIT(29)
1256 #define PF0_FW_PSM_ARQLEN_ARQCRIT_S 30
1257 #define PF0_FW_PSM_ARQLEN_ARQCRIT_M BIT(30)
1258 #define PF0_FW_PSM_ARQLEN_ARQENABLE_S 31
1259 #define PF0_FW_PSM_ARQLEN_ARQENABLE_M BIT(31)
1260 #define PF0_FW_PSM_ARQT 0x000804C4 /* Reset Source: EMPR */
1261 #define PF0_FW_PSM_ARQT_ARQT_S 0
1262 #define PF0_FW_PSM_ARQT_ARQT_M MAKEMASK(0x3FF, 0)
1263 #define PF0_FW_PSM_ATQBAH 0x00080144 /* Reset Source: EMPR */
1264 #define PF0_FW_PSM_ATQBAH_ATQBAH_S 0
1265 #define PF0_FW_PSM_ATQBAH_ATQBAH_M MAKEMASK(0xFFFFFFFF, 0)
1266 #define PF0_FW_PSM_ATQBAL 0x00080044 /* Reset Source: EMPR */
1267 #define PF0_FW_PSM_ATQBAL_ATQBAL_LSB_S 0
1268 #define PF0_FW_PSM_ATQBAL_ATQBAL_LSB_M MAKEMASK(0x3F, 0)
1269 #define PF0_FW_PSM_ATQBAL_ATQBAL_S 6
1270 #define PF0_FW_PSM_ATQBAL_ATQBAL_M MAKEMASK(0x3FFFFFF, 6)
1271 #define PF0_FW_PSM_ATQH 0x00080344 /* Reset Source: EMPR */
1272 #define PF0_FW_PSM_ATQH_ATQH_S 0
1273 #define PF0_FW_PSM_ATQH_ATQH_M MAKEMASK(0x3FF, 0)
1274 #define PF0_FW_PSM_ATQLEN 0x00080244 /* Reset Source: EMPR */
1275 #define PF0_FW_PSM_ATQLEN_ATQLEN_S 0
1276 #define PF0_FW_PSM_ATQLEN_ATQLEN_M MAKEMASK(0x3FF, 0)
1277 #define PF0_FW_PSM_ATQLEN_ATQVFE_S 28
1278 #define PF0_FW_PSM_ATQLEN_ATQVFE_M BIT(28)
1279 #define PF0_FW_PSM_ATQLEN_ATQOVFL_S 29
1280 #define PF0_FW_PSM_ATQLEN_ATQOVFL_M BIT(29)
1281 #define PF0_FW_PSM_ATQLEN_ATQCRIT_S 30
1282 #define PF0_FW_PSM_ATQLEN_ATQCRIT_M BIT(30)
1283 #define PF0_FW_PSM_ATQLEN_ATQENABLE_S 31
1284 #define PF0_FW_PSM_ATQLEN_ATQENABLE_M BIT(31)
1285 #define PF0_FW_PSM_ATQT 0x00080444 /* Reset Source: EMPR */
1286 #define PF0_FW_PSM_ATQT_ATQT_S 0
1287 #define PF0_FW_PSM_ATQT_ATQT_M MAKEMASK(0x3FF, 0)
1288 #define PF0_MBX_CPM_ARQBAH 0x0022E5D8 /* Reset Source: CORER */
1289 #define PF0_MBX_CPM_ARQBAH_ARQBAH_S 0
1290 #define PF0_MBX_CPM_ARQBAH_ARQBAH_M MAKEMASK(0xFFFFFFFF, 0)
1291 #define PF0_MBX_CPM_ARQBAL 0x0022E5D4 /* Reset Source: CORER */
1292 #define PF0_MBX_CPM_ARQBAL_ARQBAL_LSB_S 0
1293 #define PF0_MBX_CPM_ARQBAL_ARQBAL_LSB_M MAKEMASK(0x3F, 0)
1294 #define PF0_MBX_CPM_ARQBAL_ARQBAL_S 6
1295 #define PF0_MBX_CPM_ARQBAL_ARQBAL_M MAKEMASK(0x3FFFFFF, 6)
1296 #define PF0_MBX_CPM_ARQH 0x0022E5E0 /* Reset Source: CORER */
1297 #define PF0_MBX_CPM_ARQH_ARQH_S 0
1298 #define PF0_MBX_CPM_ARQH_ARQH_M MAKEMASK(0x3FF, 0)
1299 #define PF0_MBX_CPM_ARQLEN 0x0022E5DC /* Reset Source: PFR */
1300 #define PF0_MBX_CPM_ARQLEN_ARQLEN_S 0
1301 #define PF0_MBX_CPM_ARQLEN_ARQLEN_M MAKEMASK(0x3FF, 0)
1302 #define PF0_MBX_CPM_ARQLEN_ARQVFE_S 28
1303 #define PF0_MBX_CPM_ARQLEN_ARQVFE_M BIT(28)
1304 #define PF0_MBX_CPM_ARQLEN_ARQOVFL_S 29
1305 #define PF0_MBX_CPM_ARQLEN_ARQOVFL_M BIT(29)
1306 #define PF0_MBX_CPM_ARQLEN_ARQCRIT_S 30
1307 #define PF0_MBX_CPM_ARQLEN_ARQCRIT_M BIT(30)
1308 #define PF0_MBX_CPM_ARQLEN_ARQENABLE_S 31
1309 #define PF0_MBX_CPM_ARQLEN_ARQENABLE_M BIT(31)
1310 #define PF0_MBX_CPM_ARQT 0x0022E5E4 /* Reset Source: CORER */
1311 #define PF0_MBX_CPM_ARQT_ARQT_S 0
1312 #define PF0_MBX_CPM_ARQT_ARQT_M MAKEMASK(0x3FF, 0)
1313 #define PF0_MBX_CPM_ATQBAH 0x0022E5C4 /* Reset Source: CORER */
1314 #define PF0_MBX_CPM_ATQBAH_ATQBAH_S 0
1315 #define PF0_MBX_CPM_ATQBAH_ATQBAH_M MAKEMASK(0xFFFFFFFF, 0)
1316 #define PF0_MBX_CPM_ATQBAL 0x0022E5C0 /* Reset Source: CORER */
1317 #define PF0_MBX_CPM_ATQBAL_ATQBAL_S 6
1318 #define PF0_MBX_CPM_ATQBAL_ATQBAL_M MAKEMASK(0x3FFFFFF, 6)
1319 #define PF0_MBX_CPM_ATQH 0x0022E5CC /* Reset Source: CORER */
1320 #define PF0_MBX_CPM_ATQH_ATQH_S 0
1321 #define PF0_MBX_CPM_ATQH_ATQH_M MAKEMASK(0x3FF, 0)
1322 #define PF0_MBX_CPM_ATQLEN 0x0022E5C8 /* Reset Source: PFR */
1323 #define PF0_MBX_CPM_ATQLEN_ATQLEN_S 0
1324 #define PF0_MBX_CPM_ATQLEN_ATQLEN_M MAKEMASK(0x3FF, 0)
1325 #define PF0_MBX_CPM_ATQLEN_ATQVFE_S 28
1326 #define PF0_MBX_CPM_ATQLEN_ATQVFE_M BIT(28)
1327 #define PF0_MBX_CPM_ATQLEN_ATQOVFL_S 29
1328 #define PF0_MBX_CPM_ATQLEN_ATQOVFL_M BIT(29)
1329 #define PF0_MBX_CPM_ATQLEN_ATQCRIT_S 30
1330 #define PF0_MBX_CPM_ATQLEN_ATQCRIT_M BIT(30)
1331 #define PF0_MBX_CPM_ATQLEN_ATQENABLE_S 31
1332 #define PF0_MBX_CPM_ATQLEN_ATQENABLE_M BIT(31)
1333 #define PF0_MBX_CPM_ATQT 0x0022E5D0 /* Reset Source: CORER */
1334 #define PF0_MBX_CPM_ATQT_ATQT_S 0
1335 #define PF0_MBX_CPM_ATQT_ATQT_M MAKEMASK(0x3FF, 0)
1336 #define PF0_MBX_HLP_ARQBAH 0x0022E600 /* Reset Source: CORER */
1337 #define PF0_MBX_HLP_ARQBAH_ARQBAH_S 0
1338 #define PF0_MBX_HLP_ARQBAH_ARQBAH_M MAKEMASK(0xFFFFFFFF, 0)
1339 #define PF0_MBX_HLP_ARQBAL 0x0022E5FC /* Reset Source: CORER */
1340 #define PF0_MBX_HLP_ARQBAL_ARQBAL_LSB_S 0
1341 #define PF0_MBX_HLP_ARQBAL_ARQBAL_LSB_M MAKEMASK(0x3F, 0)
1342 #define PF0_MBX_HLP_ARQBAL_ARQBAL_S 6
1343 #define PF0_MBX_HLP_ARQBAL_ARQBAL_M MAKEMASK(0x3FFFFFF, 6)
1344 #define PF0_MBX_HLP_ARQH 0x0022E608 /* Reset Source: CORER */
1345 #define PF0_MBX_HLP_ARQH_ARQH_S 0
1346 #define PF0_MBX_HLP_ARQH_ARQH_M MAKEMASK(0x3FF, 0)
1347 #define PF0_MBX_HLP_ARQLEN 0x0022E604 /* Reset Source: PFR */
1348 #define PF0_MBX_HLP_ARQLEN_ARQLEN_S 0
1349 #define PF0_MBX_HLP_ARQLEN_ARQLEN_M MAKEMASK(0x3FF, 0)
1350 #define PF0_MBX_HLP_ARQLEN_ARQVFE_S 28
1351 #define PF0_MBX_HLP_ARQLEN_ARQVFE_M BIT(28)
1352 #define PF0_MBX_HLP_ARQLEN_ARQOVFL_S 29
1353 #define PF0_MBX_HLP_ARQLEN_ARQOVFL_M BIT(29)
1354 #define PF0_MBX_HLP_ARQLEN_ARQCRIT_S 30
1355 #define PF0_MBX_HLP_ARQLEN_ARQCRIT_M BIT(30)
1356 #define PF0_MBX_HLP_ARQLEN_ARQENABLE_S 31
1357 #define PF0_MBX_HLP_ARQLEN_ARQENABLE_M BIT(31)
1358 #define PF0_MBX_HLP_ARQT 0x0022E60C /* Reset Source: CORER */
1359 #define PF0_MBX_HLP_ARQT_ARQT_S 0
1360 #define PF0_MBX_HLP_ARQT_ARQT_M MAKEMASK(0x3FF, 0)
1361 #define PF0_MBX_HLP_ATQBAH 0x0022E5EC /* Reset Source: CORER */
1362 #define PF0_MBX_HLP_ATQBAH_ATQBAH_S 0
1363 #define PF0_MBX_HLP_ATQBAH_ATQBAH_M MAKEMASK(0xFFFFFFFF, 0)
1364 #define PF0_MBX_HLP_ATQBAL 0x0022E5E8 /* Reset Source: CORER */
1365 #define PF0_MBX_HLP_ATQBAL_ATQBAL_S 6
1366 #define PF0_MBX_HLP_ATQBAL_ATQBAL_M MAKEMASK(0x3FFFFFF, 6)
1367 #define PF0_MBX_HLP_ATQH 0x0022E5F4 /* Reset Source: CORER */
1368 #define PF0_MBX_HLP_ATQH_ATQH_S 0
1369 #define PF0_MBX_HLP_ATQH_ATQH_M MAKEMASK(0x3FF, 0)
1370 #define PF0_MBX_HLP_ATQLEN 0x0022E5F0 /* Reset Source: PFR */
1371 #define PF0_MBX_HLP_ATQLEN_ATQLEN_S 0
1372 #define PF0_MBX_HLP_ATQLEN_ATQLEN_M MAKEMASK(0x3FF, 0)
1373 #define PF0_MBX_HLP_ATQLEN_ATQVFE_S 28
1374 #define PF0_MBX_HLP_ATQLEN_ATQVFE_M BIT(28)
1375 #define PF0_MBX_HLP_ATQLEN_ATQOVFL_S 29
1376 #define PF0_MBX_HLP_ATQLEN_ATQOVFL_M BIT(29)
1377 #define PF0_MBX_HLP_ATQLEN_ATQCRIT_S 30
1378 #define PF0_MBX_HLP_ATQLEN_ATQCRIT_M BIT(30)
1379 #define PF0_MBX_HLP_ATQLEN_ATQENABLE_S 31
1380 #define PF0_MBX_HLP_ATQLEN_ATQENABLE_M BIT(31)
1381 #define PF0_MBX_HLP_ATQT 0x0022E5F8 /* Reset Source: CORER */
1382 #define PF0_MBX_HLP_ATQT_ATQT_S 0
1383 #define PF0_MBX_HLP_ATQT_ATQT_M MAKEMASK(0x3FF, 0)
1384 #define PF0_MBX_PSM_ARQBAH 0x0022E628 /* Reset Source: CORER */
1385 #define PF0_MBX_PSM_ARQBAH_ARQBAH_S 0
1386 #define PF0_MBX_PSM_ARQBAH_ARQBAH_M MAKEMASK(0xFFFFFFFF, 0)
1387 #define PF0_MBX_PSM_ARQBAL 0x0022E624 /* Reset Source: CORER */
1388 #define PF0_MBX_PSM_ARQBAL_ARQBAL_LSB_S 0
1389 #define PF0_MBX_PSM_ARQBAL_ARQBAL_LSB_M MAKEMASK(0x3F, 0)
1390 #define PF0_MBX_PSM_ARQBAL_ARQBAL_S 6
1391 #define PF0_MBX_PSM_ARQBAL_ARQBAL_M MAKEMASK(0x3FFFFFF, 6)
1392 #define PF0_MBX_PSM_ARQH 0x0022E630 /* Reset Source: CORER */
1393 #define PF0_MBX_PSM_ARQH_ARQH_S 0
1394 #define PF0_MBX_PSM_ARQH_ARQH_M MAKEMASK(0x3FF, 0)
1395 #define PF0_MBX_PSM_ARQLEN 0x0022E62C /* Reset Source: PFR */
1396 #define PF0_MBX_PSM_ARQLEN_ARQLEN_S 0
1397 #define PF0_MBX_PSM_ARQLEN_ARQLEN_M MAKEMASK(0x3FF, 0)
1398 #define PF0_MBX_PSM_ARQLEN_ARQVFE_S 28
1399 #define PF0_MBX_PSM_ARQLEN_ARQVFE_M BIT(28)
1400 #define PF0_MBX_PSM_ARQLEN_ARQOVFL_S 29
1401 #define PF0_MBX_PSM_ARQLEN_ARQOVFL_M BIT(29)
1402 #define PF0_MBX_PSM_ARQLEN_ARQCRIT_S 30
1403 #define PF0_MBX_PSM_ARQLEN_ARQCRIT_M BIT(30)
1404 #define PF0_MBX_PSM_ARQLEN_ARQENABLE_S 31
1405 #define PF0_MBX_PSM_ARQLEN_ARQENABLE_M BIT(31)
1406 #define PF0_MBX_PSM_ARQT 0x0022E634 /* Reset Source: CORER */
1407 #define PF0_MBX_PSM_ARQT_ARQT_S 0
1408 #define PF0_MBX_PSM_ARQT_ARQT_M MAKEMASK(0x3FF, 0)
1409 #define PF0_MBX_PSM_ATQBAH 0x0022E614 /* Reset Source: CORER */
1410 #define PF0_MBX_PSM_ATQBAH_ATQBAH_S 0
1411 #define PF0_MBX_PSM_ATQBAH_ATQBAH_M MAKEMASK(0xFFFFFFFF, 0)
1412 #define PF0_MBX_PSM_ATQBAL 0x0022E610 /* Reset Source: CORER */
1413 #define PF0_MBX_PSM_ATQBAL_ATQBAL_S 6
1414 #define PF0_MBX_PSM_ATQBAL_ATQBAL_M MAKEMASK(0x3FFFFFF, 6)
1415 #define PF0_MBX_PSM_ATQH 0x0022E61C /* Reset Source: CORER */
1416 #define PF0_MBX_PSM_ATQH_ATQH_S 0
1417 #define PF0_MBX_PSM_ATQH_ATQH_M MAKEMASK(0x3FF, 0)
1418 #define PF0_MBX_PSM_ATQLEN 0x0022E618 /* Reset Source: PFR */
1419 #define PF0_MBX_PSM_ATQLEN_ATQLEN_S 0
1420 #define PF0_MBX_PSM_ATQLEN_ATQLEN_M MAKEMASK(0x3FF, 0)
1421 #define PF0_MBX_PSM_ATQLEN_ATQVFE_S 28
1422 #define PF0_MBX_PSM_ATQLEN_ATQVFE_M BIT(28)
1423 #define PF0_MBX_PSM_ATQLEN_ATQOVFL_S 29
1424 #define PF0_MBX_PSM_ATQLEN_ATQOVFL_M BIT(29)
1425 #define PF0_MBX_PSM_ATQLEN_ATQCRIT_S 30
1426 #define PF0_MBX_PSM_ATQLEN_ATQCRIT_M BIT(30)
1427 #define PF0_MBX_PSM_ATQLEN_ATQENABLE_S 31
1428 #define PF0_MBX_PSM_ATQLEN_ATQENABLE_M BIT(31)
1429 #define PF0_MBX_PSM_ATQT 0x0022E620 /* Reset Source: CORER */
1430 #define PF0_MBX_PSM_ATQT_ATQT_S 0
1431 #define PF0_MBX_PSM_ATQT_ATQT_M MAKEMASK(0x3FF, 0)
1432 #define PF0_SB_CPM_ARQBAH 0x0022E650 /* Reset Source: CORER */
1433 #define PF0_SB_CPM_ARQBAH_ARQBAH_S 0
1434 #define PF0_SB_CPM_ARQBAH_ARQBAH_M MAKEMASK(0xFFFFFFFF, 0)
1435 #define PF0_SB_CPM_ARQBAL 0x0022E64C /* Reset Source: CORER */
1436 #define PF0_SB_CPM_ARQBAL_ARQBAL_LSB_S 0
1437 #define PF0_SB_CPM_ARQBAL_ARQBAL_LSB_M MAKEMASK(0x3F, 0)
1438 #define PF0_SB_CPM_ARQBAL_ARQBAL_S 6
1439 #define PF0_SB_CPM_ARQBAL_ARQBAL_M MAKEMASK(0x3FFFFFF, 6)
1440 #define PF0_SB_CPM_ARQH 0x0022E658 /* Reset Source: CORER */
1441 #define PF0_SB_CPM_ARQH_ARQH_S 0
1442 #define PF0_SB_CPM_ARQH_ARQH_M MAKEMASK(0x3FF, 0)
1443 #define PF0_SB_CPM_ARQLEN 0x0022E654 /* Reset Source: PFR */
1444 #define PF0_SB_CPM_ARQLEN_ARQLEN_S 0
1445 #define PF0_SB_CPM_ARQLEN_ARQLEN_M MAKEMASK(0x3FF, 0)
1446 #define PF0_SB_CPM_ARQLEN_ARQVFE_S 28
1447 #define PF0_SB_CPM_ARQLEN_ARQVFE_M BIT(28)
1448 #define PF0_SB_CPM_ARQLEN_ARQOVFL_S 29
1449 #define PF0_SB_CPM_ARQLEN_ARQOVFL_M BIT(29)
1450 #define PF0_SB_CPM_ARQLEN_ARQCRIT_S 30
1451 #define PF0_SB_CPM_ARQLEN_ARQCRIT_M BIT(30)
1452 #define PF0_SB_CPM_ARQLEN_ARQENABLE_S 31
1453 #define PF0_SB_CPM_ARQLEN_ARQENABLE_M BIT(31)
1454 #define PF0_SB_CPM_ARQT 0x0022E65C /* Reset Source: CORER */
1455 #define PF0_SB_CPM_ARQT_ARQT_S 0
1456 #define PF0_SB_CPM_ARQT_ARQT_M MAKEMASK(0x3FF, 0)
1457 #define PF0_SB_CPM_ATQBAH 0x0022E63C /* Reset Source: CORER */
1458 #define PF0_SB_CPM_ATQBAH_ATQBAH_S 0
1459 #define PF0_SB_CPM_ATQBAH_ATQBAH_M MAKEMASK(0xFFFFFFFF, 0)
1460 #define PF0_SB_CPM_ATQBAL 0x0022E638 /* Reset Source: CORER */
1461 #define PF0_SB_CPM_ATQBAL_ATQBAL_S 6
1462 #define PF0_SB_CPM_ATQBAL_ATQBAL_M MAKEMASK(0x3FFFFFF, 6)
1463 #define PF0_SB_CPM_ATQH 0x0022E644 /* Reset Source: CORER */
1464 #define PF0_SB_CPM_ATQH_ATQH_S 0
1465 #define PF0_SB_CPM_ATQH_ATQH_M MAKEMASK(0x3FF, 0)
1466 #define PF0_SB_CPM_ATQLEN 0x0022E640 /* Reset Source: PFR */
1467 #define PF0_SB_CPM_ATQLEN_ATQLEN_S 0
1468 #define PF0_SB_CPM_ATQLEN_ATQLEN_M MAKEMASK(0x3FF, 0)
1469 #define PF0_SB_CPM_ATQLEN_ATQVFE_S 28
1470 #define PF0_SB_CPM_ATQLEN_ATQVFE_M BIT(28)
1471 #define PF0_SB_CPM_ATQLEN_ATQOVFL_S 29
1472 #define PF0_SB_CPM_ATQLEN_ATQOVFL_M BIT(29)
1473 #define PF0_SB_CPM_ATQLEN_ATQCRIT_S 30
1474 #define PF0_SB_CPM_ATQLEN_ATQCRIT_M BIT(30)
1475 #define PF0_SB_CPM_ATQLEN_ATQENABLE_S 31
1476 #define PF0_SB_CPM_ATQLEN_ATQENABLE_M BIT(31)
1477 #define PF0_SB_CPM_ATQT 0x0022E648 /* Reset Source: CORER */
1478 #define PF0_SB_CPM_ATQT_ATQT_S 0
1479 #define PF0_SB_CPM_ATQT_ATQT_M MAKEMASK(0x3FF, 0)
1480 #define PF0_SB_CPM_REM_DEV_CTL 0x002300F4 /* Reset Source: CORER */
1481 #define PF0_SB_CPM_REM_DEV_CTL_DEST_EN_S 0
1482 #define PF0_SB_CPM_REM_DEV_CTL_DEST_EN_M MAKEMASK(0xFFFF, 0)
1483 #define PF0_SB_HLP_ARQBAH 0x002300D8 /* Reset Source: CORER */
1484 #define PF0_SB_HLP_ARQBAH_ARQBAH_S 0
1485 #define PF0_SB_HLP_ARQBAH_ARQBAH_M MAKEMASK(0xFFFFFFFF, 0)
1486 #define PF0_SB_HLP_ARQBAL 0x002300D4 /* Reset Source: CORER */
1487 #define PF0_SB_HLP_ARQBAL_ARQBAL_LSB_S 0
1488 #define PF0_SB_HLP_ARQBAL_ARQBAL_LSB_M MAKEMASK(0x3F, 0)
1489 #define PF0_SB_HLP_ARQBAL_ARQBAL_S 6
1490 #define PF0_SB_HLP_ARQBAL_ARQBAL_M MAKEMASK(0x3FFFFFF, 6)
1491 #define PF0_SB_HLP_ARQH 0x002300E0 /* Reset Source: CORER */
1492 #define PF0_SB_HLP_ARQH_ARQH_S 0
1493 #define PF0_SB_HLP_ARQH_ARQH_M MAKEMASK(0x3FF, 0)
1494 #define PF0_SB_HLP_ARQLEN 0x002300DC /* Reset Source: PFR */
1495 #define PF0_SB_HLP_ARQLEN_ARQLEN_S 0
1496 #define PF0_SB_HLP_ARQLEN_ARQLEN_M MAKEMASK(0x3FF, 0)
1497 #define PF0_SB_HLP_ARQLEN_ARQVFE_S 28
1498 #define PF0_SB_HLP_ARQLEN_ARQVFE_M BIT(28)
1499 #define PF0_SB_HLP_ARQLEN_ARQOVFL_S 29
1500 #define PF0_SB_HLP_ARQLEN_ARQOVFL_M BIT(29)
1501 #define PF0_SB_HLP_ARQLEN_ARQCRIT_S 30
1502 #define PF0_SB_HLP_ARQLEN_ARQCRIT_M BIT(30)
1503 #define PF0_SB_HLP_ARQLEN_ARQENABLE_S 31
1504 #define PF0_SB_HLP_ARQLEN_ARQENABLE_M BIT(31)
1505 #define PF0_SB_HLP_ARQT 0x002300E4 /* Reset Source: CORER */
1506 #define PF0_SB_HLP_ARQT_ARQT_S 0
1507 #define PF0_SB_HLP_ARQT_ARQT_M MAKEMASK(0x3FF, 0)
1508 #define PF0_SB_HLP_ATQBAH 0x002300C4 /* Reset Source: CORER */
1509 #define PF0_SB_HLP_ATQBAH_ATQBAH_S 0
1510 #define PF0_SB_HLP_ATQBAH_ATQBAH_M MAKEMASK(0xFFFFFFFF, 0)
1511 #define PF0_SB_HLP_ATQBAL 0x002300C0 /* Reset Source: CORER */
1512 #define PF0_SB_HLP_ATQBAL_ATQBAL_S 6
1513 #define PF0_SB_HLP_ATQBAL_ATQBAL_M MAKEMASK(0x3FFFFFF, 6)
1514 #define PF0_SB_HLP_ATQH 0x002300CC /* Reset Source: CORER */
1515 #define PF0_SB_HLP_ATQH_ATQH_S 0
1516 #define PF0_SB_HLP_ATQH_ATQH_M MAKEMASK(0x3FF, 0)
1517 #define PF0_SB_HLP_ATQLEN 0x002300C8 /* Reset Source: PFR */
1518 #define PF0_SB_HLP_ATQLEN_ATQLEN_S 0
1519 #define PF0_SB_HLP_ATQLEN_ATQLEN_M MAKEMASK(0x3FF, 0)
1520 #define PF0_SB_HLP_ATQLEN_ATQVFE_S 28
1521 #define PF0_SB_HLP_ATQLEN_ATQVFE_M BIT(28)
1522 #define PF0_SB_HLP_ATQLEN_ATQOVFL_S 29
1523 #define PF0_SB_HLP_ATQLEN_ATQOVFL_M BIT(29)
1524 #define PF0_SB_HLP_ATQLEN_ATQCRIT_S 30
1525 #define PF0_SB_HLP_ATQLEN_ATQCRIT_M BIT(30)
1526 #define PF0_SB_HLP_ATQLEN_ATQENABLE_S 31
1527 #define PF0_SB_HLP_ATQLEN_ATQENABLE_M BIT(31)
1528 #define PF0_SB_HLP_ATQT 0x002300D0 /* Reset Source: CORER */
1529 #define PF0_SB_HLP_ATQT_ATQT_S 0
1530 #define PF0_SB_HLP_ATQT_ATQT_M MAKEMASK(0x3FF, 0)
1531 #define PF0_SB_HLP_REM_DEV_CTL 0x002300E8 /* Reset Source: CORER */
1532 #define PF0_SB_HLP_REM_DEV_CTL_DEST_EN_S 0
1533 #define PF0_SB_HLP_REM_DEV_CTL_DEST_EN_M MAKEMASK(0xFFFF, 0)
1534 #define SB_REM_DEV_DEST(_i) (0x002300F8 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
1535 #define SB_REM_DEV_DEST_MAX_INDEX 7
1536 #define SB_REM_DEV_DEST_DEST_S 0
1537 #define SB_REM_DEV_DEST_DEST_M MAKEMASK(0xF, 0)
1538 #define SB_REM_DEV_DEST_DEST_VALID_S 31
1539 #define SB_REM_DEV_DEST_DEST_VALID_M BIT(31)
1540 #define VF_MBX_ARQBAH(_VF) (0x0022B800 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: CORER */
1541 #define VF_MBX_ARQBAH_MAX_INDEX 255
1542 #define VF_MBX_ARQBAH_ARQBAH_S 0
1543 #define VF_MBX_ARQBAH_ARQBAH_M MAKEMASK(0xFFFFFFFF, 0)
1544 #define VF_MBX_ARQBAL(_VF) (0x0022B400 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: CORER */
1545 #define VF_MBX_ARQBAL_MAX_INDEX 255
1546 #define VF_MBX_ARQBAL_ARQBAL_LSB_S 0
1547 #define VF_MBX_ARQBAL_ARQBAL_LSB_M MAKEMASK(0x3F, 0)
1548 #define VF_MBX_ARQBAL_ARQBAL_S 6
1549 #define VF_MBX_ARQBAL_ARQBAL_M MAKEMASK(0x3FFFFFF, 6)
1550 #define VF_MBX_ARQH(_VF) (0x0022C000 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: CORER */
1551 #define VF_MBX_ARQH_MAX_INDEX 255
1552 #define VF_MBX_ARQH_ARQH_S 0
1553 #define VF_MBX_ARQH_ARQH_M MAKEMASK(0x3FF, 0)
1554 #define VF_MBX_ARQLEN(_VF) (0x0022BC00 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: PFR */
1555 #define VF_MBX_ARQLEN_MAX_INDEX 255
1556 #define VF_MBX_ARQLEN_ARQLEN_S 0
1557 #define VF_MBX_ARQLEN_ARQLEN_M MAKEMASK(0x3FF, 0)
1558 #define VF_MBX_ARQLEN_ARQVFE_S 28
1559 #define VF_MBX_ARQLEN_ARQVFE_M BIT(28)
1560 #define VF_MBX_ARQLEN_ARQOVFL_S 29
1561 #define VF_MBX_ARQLEN_ARQOVFL_M BIT(29)
1562 #define VF_MBX_ARQLEN_ARQCRIT_S 30
1563 #define VF_MBX_ARQLEN_ARQCRIT_M BIT(30)
1564 #define VF_MBX_ARQLEN_ARQENABLE_S 31
1565 #define VF_MBX_ARQLEN_ARQENABLE_M BIT(31)
1566 #define VF_MBX_ARQT(_VF) (0x0022C400 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: CORER */
1567 #define VF_MBX_ARQT_MAX_INDEX 255
1568 #define VF_MBX_ARQT_ARQT_S 0
1569 #define VF_MBX_ARQT_ARQT_M MAKEMASK(0x3FF, 0)
1570 #define VF_MBX_ATQBAH(_VF) (0x0022A400 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: CORER */
1571 #define VF_MBX_ATQBAH_MAX_INDEX 255
1572 #define VF_MBX_ATQBAH_ATQBAH_S 0
1573 #define VF_MBX_ATQBAH_ATQBAH_M MAKEMASK(0xFFFFFFFF, 0)
1574 #define VF_MBX_ATQBAL(_VF) (0x0022A000 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: CORER */
1575 #define VF_MBX_ATQBAL_MAX_INDEX 255
1576 #define VF_MBX_ATQBAL_ATQBAL_S 6
1577 #define VF_MBX_ATQBAL_ATQBAL_M MAKEMASK(0x3FFFFFF, 6)
1578 #define VF_MBX_ATQH(_VF) (0x0022AC00 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: CORER */
1579 #define VF_MBX_ATQH_MAX_INDEX 255
1580 #define VF_MBX_ATQH_ATQH_S 0
1581 #define VF_MBX_ATQH_ATQH_M MAKEMASK(0x3FF, 0)
1582 #define VF_MBX_ATQLEN(_VF) (0x0022A800 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: PFR */
1583 #define VF_MBX_ATQLEN_MAX_INDEX 255
1584 #define VF_MBX_ATQLEN_ATQLEN_S 0
1585 #define VF_MBX_ATQLEN_ATQLEN_M MAKEMASK(0x3FF, 0)
1586 #define VF_MBX_ATQLEN_ATQVFE_S 28
1587 #define VF_MBX_ATQLEN_ATQVFE_M BIT(28)
1588 #define VF_MBX_ATQLEN_ATQOVFL_S 29
1589 #define VF_MBX_ATQLEN_ATQOVFL_M BIT(29)
1590 #define VF_MBX_ATQLEN_ATQCRIT_S 30
1591 #define VF_MBX_ATQLEN_ATQCRIT_M BIT(30)
1592 #define VF_MBX_ATQLEN_ATQENABLE_S 31
1593 #define VF_MBX_ATQLEN_ATQENABLE_M BIT(31)
1594 #define VF_MBX_ATQT(_VF) (0x0022B000 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: CORER */
1595 #define VF_MBX_ATQT_MAX_INDEX 255
1596 #define VF_MBX_ATQT_ATQT_S 0
1597 #define VF_MBX_ATQT_ATQT_M MAKEMASK(0x3FF, 0)
1598 #define VF_MBX_CPM_ARQBAH(_VF128) (0x0022D400 + ((_VF128) * 4)) /* _i=0...127 */ /* Reset Source: CORER */
1599 #define VF_MBX_CPM_ARQBAH_MAX_INDEX 127
1600 #define VF_MBX_CPM_ARQBAH_ARQBAH_S 0
1601 #define VF_MBX_CPM_ARQBAH_ARQBAH_M MAKEMASK(0xFFFFFFFF, 0)
1602 #define VF_MBX_CPM_ARQBAL(_VF128) (0x0022D200 + ((_VF128) * 4)) /* _i=0...127 */ /* Reset Source: CORER */
1603 #define VF_MBX_CPM_ARQBAL_MAX_INDEX 127
1604 #define VF_MBX_CPM_ARQBAL_ARQBAL_LSB_S 0
1605 #define VF_MBX_CPM_ARQBAL_ARQBAL_LSB_M MAKEMASK(0x3F, 0)
1606 #define VF_MBX_CPM_ARQBAL_ARQBAL_S 6
1607 #define VF_MBX_CPM_ARQBAL_ARQBAL_M MAKEMASK(0x3FFFFFF, 6)
1608 #define VF_MBX_CPM_ARQH(_VF128) (0x0022D800 + ((_VF128) * 4)) /* _i=0...127 */ /* Reset Source: CORER */
1609 #define VF_MBX_CPM_ARQH_MAX_INDEX 127
1610 #define VF_MBX_CPM_ARQH_ARQH_S 0
1611 #define VF_MBX_CPM_ARQH_ARQH_M MAKEMASK(0x3FF, 0)
1612 #define VF_MBX_CPM_ARQLEN(_VF128) (0x0022D600 + ((_VF128) * 4)) /* _i=0...127 */ /* Reset Source: PFR */
1613 #define VF_MBX_CPM_ARQLEN_MAX_INDEX 127
1614 #define VF_MBX_CPM_ARQLEN_ARQLEN_S 0
1615 #define VF_MBX_CPM_ARQLEN_ARQLEN_M MAKEMASK(0x3FF, 0)
1616 #define VF_MBX_CPM_ARQLEN_ARQVFE_S 28
1617 #define VF_MBX_CPM_ARQLEN_ARQVFE_M BIT(28)
1618 #define VF_MBX_CPM_ARQLEN_ARQOVFL_S 29
1619 #define VF_MBX_CPM_ARQLEN_ARQOVFL_M BIT(29)
1620 #define VF_MBX_CPM_ARQLEN_ARQCRIT_S 30
1621 #define VF_MBX_CPM_ARQLEN_ARQCRIT_M BIT(30)
1622 #define VF_MBX_CPM_ARQLEN_ARQENABLE_S 31
1623 #define VF_MBX_CPM_ARQLEN_ARQENABLE_M BIT(31)
1624 #define VF_MBX_CPM_ARQT(_VF128) (0x0022DA00 + ((_VF128) * 4)) /* _i=0...127 */ /* Reset Source: CORER */
1625 #define VF_MBX_CPM_ARQT_MAX_INDEX 127
1626 #define VF_MBX_CPM_ARQT_ARQT_S 0
1627 #define VF_MBX_CPM_ARQT_ARQT_M MAKEMASK(0x3FF, 0)
1628 #define VF_MBX_CPM_ATQBAH(_VF128) (0x0022CA00 + ((_VF128) * 4)) /* _i=0...127 */ /* Reset Source: CORER */
1629 #define VF_MBX_CPM_ATQBAH_MAX_INDEX 127
1630 #define VF_MBX_CPM_ATQBAH_ATQBAH_S 0
1631 #define VF_MBX_CPM_ATQBAH_ATQBAH_M MAKEMASK(0xFFFFFFFF, 0)
1632 #define VF_MBX_CPM_ATQBAL(_VF128) (0x0022C800 + ((_VF128) * 4)) /* _i=0...127 */ /* Reset Source: CORER */
1633 #define VF_MBX_CPM_ATQBAL_MAX_INDEX 127
1634 #define VF_MBX_CPM_ATQBAL_ATQBAL_S 6
1635 #define VF_MBX_CPM_ATQBAL_ATQBAL_M MAKEMASK(0x3FFFFFF, 6)
1636 #define VF_MBX_CPM_ATQH(_VF128) (0x0022CE00 + ((_VF128) * 4)) /* _i=0...127 */ /* Reset Source: CORER */
1637 #define VF_MBX_CPM_ATQH_MAX_INDEX 127
1638 #define VF_MBX_CPM_ATQH_ATQH_S 0
1639 #define VF_MBX_CPM_ATQH_ATQH_M MAKEMASK(0x3FF, 0)
1640 #define VF_MBX_CPM_ATQLEN(_VF128) (0x0022CC00 + ((_VF128) * 4)) /* _i=0...127 */ /* Reset Source: PFR */
1641 #define VF_MBX_CPM_ATQLEN_MAX_INDEX 127
1642 #define VF_MBX_CPM_ATQLEN_ATQLEN_S 0
1643 #define VF_MBX_CPM_ATQLEN_ATQLEN_M MAKEMASK(0x3FF, 0)
1644 #define VF_MBX_CPM_ATQLEN_ATQVFE_S 28
1645 #define VF_MBX_CPM_ATQLEN_ATQVFE_M BIT(28)
1646 #define VF_MBX_CPM_ATQLEN_ATQOVFL_S 29
1647 #define VF_MBX_CPM_ATQLEN_ATQOVFL_M BIT(29)
1648 #define VF_MBX_CPM_ATQLEN_ATQCRIT_S 30
1649 #define VF_MBX_CPM_ATQLEN_ATQCRIT_M BIT(30)
1650 #define VF_MBX_CPM_ATQLEN_ATQENABLE_S 31
1651 #define VF_MBX_CPM_ATQLEN_ATQENABLE_M BIT(31)
1652 #define VF_MBX_CPM_ATQT(_VF128) (0x0022D000 + ((_VF128) * 4)) /* _i=0...127 */ /* Reset Source: CORER */
1653 #define VF_MBX_CPM_ATQT_MAX_INDEX 127
1654 #define VF_MBX_CPM_ATQT_ATQT_S 0
1655 #define VF_MBX_CPM_ATQT_ATQT_M MAKEMASK(0x3FF, 0)
1656 #define VF_MBX_HLP_ARQBAH(_VF16) (0x0022DD80 + ((_VF16) * 4)) /* _i=0...15 */ /* Reset Source: CORER */
1657 #define VF_MBX_HLP_ARQBAH_MAX_INDEX 15
1658 #define VF_MBX_HLP_ARQBAH_ARQBAH_S 0
1659 #define VF_MBX_HLP_ARQBAH_ARQBAH_M MAKEMASK(0xFFFFFFFF, 0)
1660 #define VF_MBX_HLP_ARQBAL(_VF16) (0x0022DD40 + ((_VF16) * 4)) /* _i=0...15 */ /* Reset Source: CORER */
1661 #define VF_MBX_HLP_ARQBAL_MAX_INDEX 15
1662 #define VF_MBX_HLP_ARQBAL_ARQBAL_LSB_S 0
1663 #define VF_MBX_HLP_ARQBAL_ARQBAL_LSB_M MAKEMASK(0x3F, 0)
1664 #define VF_MBX_HLP_ARQBAL_ARQBAL_S 6
1665 #define VF_MBX_HLP_ARQBAL_ARQBAL_M MAKEMASK(0x3FFFFFF, 6)
1666 #define VF_MBX_HLP_ARQH(_VF16) (0x0022DE00 + ((_VF16) * 4)) /* _i=0...15 */ /* Reset Source: CORER */
1667 #define VF_MBX_HLP_ARQH_MAX_INDEX 15
1668 #define VF_MBX_HLP_ARQH_ARQH_S 0
1669 #define VF_MBX_HLP_ARQH_ARQH_M MAKEMASK(0x3FF, 0)
1670 #define VF_MBX_HLP_ARQLEN(_VF16) (0x0022DDC0 + ((_VF16) * 4)) /* _i=0...15 */ /* Reset Source: PFR */
1671 #define VF_MBX_HLP_ARQLEN_MAX_INDEX 15
1672 #define VF_MBX_HLP_ARQLEN_ARQLEN_S 0
1673 #define VF_MBX_HLP_ARQLEN_ARQLEN_M MAKEMASK(0x3FF, 0)
1674 #define VF_MBX_HLP_ARQLEN_ARQVFE_S 28
1675 #define VF_MBX_HLP_ARQLEN_ARQVFE_M BIT(28)
1676 #define VF_MBX_HLP_ARQLEN_ARQOVFL_S 29
1677 #define VF_MBX_HLP_ARQLEN_ARQOVFL_M BIT(29)
1678 #define VF_MBX_HLP_ARQLEN_ARQCRIT_S 30
1679 #define VF_MBX_HLP_ARQLEN_ARQCRIT_M BIT(30)
1680 #define VF_MBX_HLP_ARQLEN_ARQENABLE_S 31
1681 #define VF_MBX_HLP_ARQLEN_ARQENABLE_M BIT(31)
1682 #define VF_MBX_HLP_ARQT(_VF16) (0x0022DE40 + ((_VF16) * 4)) /* _i=0...15 */ /* Reset Source: CORER */
1683 #define VF_MBX_HLP_ARQT_MAX_INDEX 15
1684 #define VF_MBX_HLP_ARQT_ARQT_S 0
1685 #define VF_MBX_HLP_ARQT_ARQT_M MAKEMASK(0x3FF, 0)
1686 #define VF_MBX_HLP_ATQBAH(_VF16) (0x0022DC40 + ((_VF16) * 4)) /* _i=0...15 */ /* Reset Source: CORER */
1687 #define VF_MBX_HLP_ATQBAH_MAX_INDEX 15
1688 #define VF_MBX_HLP_ATQBAH_ATQBAH_S 0
1689 #define VF_MBX_HLP_ATQBAH_ATQBAH_M MAKEMASK(0xFFFFFFFF, 0)
1690 #define VF_MBX_HLP_ATQBAL(_VF16) (0x0022DC00 + ((_VF16) * 4)) /* _i=0...15 */ /* Reset Source: CORER */
1691 #define VF_MBX_HLP_ATQBAL_MAX_INDEX 15
1692 #define VF_MBX_HLP_ATQBAL_ATQBAL_S 6
1693 #define VF_MBX_HLP_ATQBAL_ATQBAL_M MAKEMASK(0x3FFFFFF, 6)
1694 #define VF_MBX_HLP_ATQH(_VF16) (0x0022DCC0 + ((_VF16) * 4)) /* _i=0...15 */ /* Reset Source: CORER */
1695 #define VF_MBX_HLP_ATQH_MAX_INDEX 15
1696 #define VF_MBX_HLP_ATQH_ATQH_S 0
1697 #define VF_MBX_HLP_ATQH_ATQH_M MAKEMASK(0x3FF, 0)
1698 #define VF_MBX_HLP_ATQLEN(_VF16) (0x0022DC80 + ((_VF16) * 4)) /* _i=0...15 */ /* Reset Source: PFR */
1699 #define VF_MBX_HLP_ATQLEN_MAX_INDEX 15
1700 #define VF_MBX_HLP_ATQLEN_ATQLEN_S 0
1701 #define VF_MBX_HLP_ATQLEN_ATQLEN_M MAKEMASK(0x3FF, 0)
1702 #define VF_MBX_HLP_ATQLEN_ATQVFE_S 28
1703 #define VF_MBX_HLP_ATQLEN_ATQVFE_M BIT(28)
1704 #define VF_MBX_HLP_ATQLEN_ATQOVFL_S 29
1705 #define VF_MBX_HLP_ATQLEN_ATQOVFL_M BIT(29)
1706 #define VF_MBX_HLP_ATQLEN_ATQCRIT_S 30
1707 #define VF_MBX_HLP_ATQLEN_ATQCRIT_M BIT(30)
1708 #define VF_MBX_HLP_ATQLEN_ATQENABLE_S 31
1709 #define VF_MBX_HLP_ATQLEN_ATQENABLE_M BIT(31)
1710 #define VF_MBX_HLP_ATQT(_VF16) (0x0022DD00 + ((_VF16) * 4)) /* _i=0...15 */ /* Reset Source: CORER */
1711 #define VF_MBX_HLP_ATQT_MAX_INDEX 15
1712 #define VF_MBX_HLP_ATQT_ATQT_S 0
1713 #define VF_MBX_HLP_ATQT_ATQT_M MAKEMASK(0x3FF, 0)
1714 #define VF_MBX_PSM_ARQBAH(_VF16) (0x0022E000 + ((_VF16) * 4)) /* _i=0...15 */ /* Reset Source: CORER */
1715 #define VF_MBX_PSM_ARQBAH_MAX_INDEX 15
1716 #define VF_MBX_PSM_ARQBAH_ARQBAH_S 0
1717 #define VF_MBX_PSM_ARQBAH_ARQBAH_M MAKEMASK(0xFFFFFFFF, 0)
1718 #define VF_MBX_PSM_ARQBAL(_VF16) (0x0022DFC0 + ((_VF16) * 4)) /* _i=0...15 */ /* Reset Source: CORER */
1719 #define VF_MBX_PSM_ARQBAL_MAX_INDEX 15
1720 #define VF_MBX_PSM_ARQBAL_ARQBAL_LSB_S 0
1721 #define VF_MBX_PSM_ARQBAL_ARQBAL_LSB_M MAKEMASK(0x3F, 0)
1722 #define VF_MBX_PSM_ARQBAL_ARQBAL_S 6
1723 #define VF_MBX_PSM_ARQBAL_ARQBAL_M MAKEMASK(0x3FFFFFF, 6)
1724 #define VF_MBX_PSM_ARQH(_VF16) (0x0022E080 + ((_VF16) * 4)) /* _i=0...15 */ /* Reset Source: CORER */
1725 #define VF_MBX_PSM_ARQH_MAX_INDEX 15
1726 #define VF_MBX_PSM_ARQH_ARQH_S 0
1727 #define VF_MBX_PSM_ARQH_ARQH_M MAKEMASK(0x3FF, 0)
1728 #define VF_MBX_PSM_ARQLEN(_VF16) (0x0022E040 + ((_VF16) * 4)) /* _i=0...15 */ /* Reset Source: PFR */
1729 #define VF_MBX_PSM_ARQLEN_MAX_INDEX 15
1730 #define VF_MBX_PSM_ARQLEN_ARQLEN_S 0
1731 #define VF_MBX_PSM_ARQLEN_ARQLEN_M MAKEMASK(0x3FF, 0)
1732 #define VF_MBX_PSM_ARQLEN_ARQVFE_S 28
1733 #define VF_MBX_PSM_ARQLEN_ARQVFE_M BIT(28)
1734 #define VF_MBX_PSM_ARQLEN_ARQOVFL_S 29
1735 #define VF_MBX_PSM_ARQLEN_ARQOVFL_M BIT(29)
1736 #define VF_MBX_PSM_ARQLEN_ARQCRIT_S 30
1737 #define VF_MBX_PSM_ARQLEN_ARQCRIT_M BIT(30)
1738 #define VF_MBX_PSM_ARQLEN_ARQENABLE_S 31
1739 #define VF_MBX_PSM_ARQLEN_ARQENABLE_M BIT(31)
1740 #define VF_MBX_PSM_ARQT(_VF16) (0x0022E0C0 + ((_VF16) * 4)) /* _i=0...15 */ /* Reset Source: CORER */
1741 #define VF_MBX_PSM_ARQT_MAX_INDEX 15
1742 #define VF_MBX_PSM_ARQT_ARQT_S 0
1743 #define VF_MBX_PSM_ARQT_ARQT_M MAKEMASK(0x3FF, 0)
1744 #define VF_MBX_PSM_ATQBAH(_VF16) (0x0022DEC0 + ((_VF16) * 4)) /* _i=0...15 */ /* Reset Source: CORER */
1745 #define VF_MBX_PSM_ATQBAH_MAX_INDEX 15
1746 #define VF_MBX_PSM_ATQBAH_ATQBAH_S 0
1747 #define VF_MBX_PSM_ATQBAH_ATQBAH_M MAKEMASK(0xFFFFFFFF, 0)
1748 #define VF_MBX_PSM_ATQBAL(_VF16) (0x0022DE80 + ((_VF16) * 4)) /* _i=0...15 */ /* Reset Source: CORER */
1749 #define VF_MBX_PSM_ATQBAL_MAX_INDEX 15
1750 #define VF_MBX_PSM_ATQBAL_ATQBAL_S 6
1751 #define VF_MBX_PSM_ATQBAL_ATQBAL_M MAKEMASK(0x3FFFFFF, 6)
1752 #define VF_MBX_PSM_ATQH(_VF16) (0x0022DF40 + ((_VF16) * 4)) /* _i=0...15 */ /* Reset Source: CORER */
1753 #define VF_MBX_PSM_ATQH_MAX_INDEX 15
1754 #define VF_MBX_PSM_ATQH_ATQH_S 0
1755 #define VF_MBX_PSM_ATQH_ATQH_M MAKEMASK(0x3FF, 0)
1756 #define VF_MBX_PSM_ATQLEN(_VF16) (0x0022DF00 + ((_VF16) * 4)) /* _i=0...15 */ /* Reset Source: PFR */
1757 #define VF_MBX_PSM_ATQLEN_MAX_INDEX 15
1758 #define VF_MBX_PSM_ATQLEN_ATQLEN_S 0
1759 #define VF_MBX_PSM_ATQLEN_ATQLEN_M MAKEMASK(0x3FF, 0)
1760 #define VF_MBX_PSM_ATQLEN_ATQVFE_S 28
1761 #define VF_MBX_PSM_ATQLEN_ATQVFE_M BIT(28)
1762 #define VF_MBX_PSM_ATQLEN_ATQOVFL_S 29
1763 #define VF_MBX_PSM_ATQLEN_ATQOVFL_M BIT(29)
1764 #define VF_MBX_PSM_ATQLEN_ATQCRIT_S 30
1765 #define VF_MBX_PSM_ATQLEN_ATQCRIT_M BIT(30)
1766 #define VF_MBX_PSM_ATQLEN_ATQENABLE_S 31
1767 #define VF_MBX_PSM_ATQLEN_ATQENABLE_M BIT(31)
1768 #define VF_MBX_PSM_ATQT(_VF16) (0x0022DF80 + ((_VF16) * 4)) /* _i=0...15 */ /* Reset Source: CORER */
1769 #define VF_MBX_PSM_ATQT_MAX_INDEX 15
1770 #define VF_MBX_PSM_ATQT_ATQT_S 0
1771 #define VF_MBX_PSM_ATQT_ATQT_M MAKEMASK(0x3FF, 0)
1772 #define VF_SB_CPM_ARQBAH(_VF128) (0x0022F400 + ((_VF128) * 4)) /* _i=0...127 */ /* Reset Source: CORER */
1773 #define VF_SB_CPM_ARQBAH_MAX_INDEX 127
1774 #define VF_SB_CPM_ARQBAH_ARQBAH_S 0
1775 #define VF_SB_CPM_ARQBAH_ARQBAH_M MAKEMASK(0xFFFFFFFF, 0)
1776 #define VF_SB_CPM_ARQBAL(_VF128) (0x0022F200 + ((_VF128) * 4)) /* _i=0...127 */ /* Reset Source: CORER */
1777 #define VF_SB_CPM_ARQBAL_MAX_INDEX 127
1778 #define VF_SB_CPM_ARQBAL_ARQBAL_LSB_S 0
1779 #define VF_SB_CPM_ARQBAL_ARQBAL_LSB_M MAKEMASK(0x3F, 0)
1780 #define VF_SB_CPM_ARQBAL_ARQBAL_S 6
1781 #define VF_SB_CPM_ARQBAL_ARQBAL_M MAKEMASK(0x3FFFFFF, 6)
1782 #define VF_SB_CPM_ARQH(_VF128) (0x0022F800 + ((_VF128) * 4)) /* _i=0...127 */ /* Reset Source: CORER */
1783 #define VF_SB_CPM_ARQH_MAX_INDEX 127
1784 #define VF_SB_CPM_ARQH_ARQH_S 0
1785 #define VF_SB_CPM_ARQH_ARQH_M MAKEMASK(0x3FF, 0)
1786 #define VF_SB_CPM_ARQLEN(_VF128) (0x0022F600 + ((_VF128) * 4)) /* _i=0...127 */ /* Reset Source: PFR */
1787 #define VF_SB_CPM_ARQLEN_MAX_INDEX 127
1788 #define VF_SB_CPM_ARQLEN_ARQLEN_S 0
1789 #define VF_SB_CPM_ARQLEN_ARQLEN_M MAKEMASK(0x3FF, 0)
1790 #define VF_SB_CPM_ARQLEN_ARQVFE_S 28
1791 #define VF_SB_CPM_ARQLEN_ARQVFE_M BIT(28)
1792 #define VF_SB_CPM_ARQLEN_ARQOVFL_S 29
1793 #define VF_SB_CPM_ARQLEN_ARQOVFL_M BIT(29)
1794 #define VF_SB_CPM_ARQLEN_ARQCRIT_S 30
1795 #define VF_SB_CPM_ARQLEN_ARQCRIT_M BIT(30)
1796 #define VF_SB_CPM_ARQLEN_ARQENABLE_S 31
1797 #define VF_SB_CPM_ARQLEN_ARQENABLE_M BIT(31)
1798 #define VF_SB_CPM_ARQT(_VF128) (0x0022FA00 + ((_VF128) * 4)) /* _i=0...127 */ /* Reset Source: CORER */
1799 #define VF_SB_CPM_ARQT_MAX_INDEX 127
1800 #define VF_SB_CPM_ARQT_ARQT_S 0
1801 #define VF_SB_CPM_ARQT_ARQT_M MAKEMASK(0x3FF, 0)
1802 #define VF_SB_CPM_ATQBAH(_VF128) (0x0022EA00 + ((_VF128) * 4)) /* _i=0...127 */ /* Reset Source: CORER */
1803 #define VF_SB_CPM_ATQBAH_MAX_INDEX 127
1804 #define VF_SB_CPM_ATQBAH_ATQBAH_S 0
1805 #define VF_SB_CPM_ATQBAH_ATQBAH_M MAKEMASK(0xFFFFFFFF, 0)
1806 #define VF_SB_CPM_ATQBAL(_VF128) (0x0022E800 + ((_VF128) * 4)) /* _i=0...127 */ /* Reset Source: CORER */
1807 #define VF_SB_CPM_ATQBAL_MAX_INDEX 127
1808 #define VF_SB_CPM_ATQBAL_ATQBAL_S 6
1809 #define VF_SB_CPM_ATQBAL_ATQBAL_M MAKEMASK(0x3FFFFFF, 6)
1810 #define VF_SB_CPM_ATQH(_VF128) (0x0022EE00 + ((_VF128) * 4)) /* _i=0...127 */ /* Reset Source: CORER */
1811 #define VF_SB_CPM_ATQH_MAX_INDEX 127
1812 #define VF_SB_CPM_ATQH_ATQH_S 0
1813 #define VF_SB_CPM_ATQH_ATQH_M MAKEMASK(0x3FF, 0)
1814 #define VF_SB_CPM_ATQLEN(_VF128) (0x0022EC00 + ((_VF128) * 4)) /* _i=0...127 */ /* Reset Source: PFR */
1815 #define VF_SB_CPM_ATQLEN_MAX_INDEX 127
1816 #define VF_SB_CPM_ATQLEN_ATQLEN_S 0
1817 #define VF_SB_CPM_ATQLEN_ATQLEN_M MAKEMASK(0x3FF, 0)
1818 #define VF_SB_CPM_ATQLEN_ATQVFE_S 28
1819 #define VF_SB_CPM_ATQLEN_ATQVFE_M BIT(28)
1820 #define VF_SB_CPM_ATQLEN_ATQOVFL_S 29
1821 #define VF_SB_CPM_ATQLEN_ATQOVFL_M BIT(29)
1822 #define VF_SB_CPM_ATQLEN_ATQCRIT_S 30
1823 #define VF_SB_CPM_ATQLEN_ATQCRIT_M BIT(30)
1824 #define VF_SB_CPM_ATQLEN_ATQENABLE_S 31
1825 #define VF_SB_CPM_ATQLEN_ATQENABLE_M BIT(31)
1826 #define VF_SB_CPM_ATQT(_VF128) (0x0022F000 + ((_VF128) * 4)) /* _i=0...127 */ /* Reset Source: CORER */
1827 #define VF_SB_CPM_ATQT_MAX_INDEX 127
1828 #define VF_SB_CPM_ATQT_ATQT_S 0
1829 #define VF_SB_CPM_ATQT_ATQT_M MAKEMASK(0x3FF, 0)
1830 #define VF_SB_CPM_REM_DEV_CTL 0x002300EC /* Reset Source: CORER */
1831 #define VF_SB_CPM_REM_DEV_CTL_DEST_EN_S 0
1832 #define VF_SB_CPM_REM_DEV_CTL_DEST_EN_M MAKEMASK(0xFFFF, 0)
1833 #define VP_MBX_CPM_PF_VF_CTRL(_VP128) (0x00231800 + ((_VP128) * 4)) /* _i=0...127 */ /* Reset Source: CORER */
1834 #define VP_MBX_CPM_PF_VF_CTRL_MAX_INDEX 127
1835 #define VP_MBX_CPM_PF_VF_CTRL_QUEUE_EN_S 0
1836 #define VP_MBX_CPM_PF_VF_CTRL_QUEUE_EN_M BIT(0)
1837 #define VP_MBX_HLP_PF_VF_CTRL(_VP16) (0x00231A00 + ((_VP16) * 4)) /* _i=0...15 */ /* Reset Source: CORER */
1838 #define VP_MBX_HLP_PF_VF_CTRL_MAX_INDEX 15
1839 #define VP_MBX_HLP_PF_VF_CTRL_QUEUE_EN_S 0
1840 #define VP_MBX_HLP_PF_VF_CTRL_QUEUE_EN_M BIT(0)
1841 #define VP_MBX_PF_VF_CTRL(_VSI) (0x00230800 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: CORER */
1842 #define VP_MBX_PF_VF_CTRL_MAX_INDEX 767
1843 #define VP_MBX_PF_VF_CTRL_QUEUE_EN_S 0
1844 #define VP_MBX_PF_VF_CTRL_QUEUE_EN_M BIT(0)
1845 #define VP_MBX_PSM_PF_VF_CTRL(_VP16) (0x00231A40 + ((_VP16) * 4)) /* _i=0...15 */ /* Reset Source: CORER */
1846 #define VP_MBX_PSM_PF_VF_CTRL_MAX_INDEX 15
1847 #define VP_MBX_PSM_PF_VF_CTRL_QUEUE_EN_S 0
1848 #define VP_MBX_PSM_PF_VF_CTRL_QUEUE_EN_M BIT(0)
1849 #define VP_SB_CPM_PF_VF_CTRL(_VP128) (0x00231C00 + ((_VP128) * 4)) /* _i=0...127 */ /* Reset Source: CORER */
1850 #define VP_SB_CPM_PF_VF_CTRL_MAX_INDEX 127
1851 #define VP_SB_CPM_PF_VF_CTRL_QUEUE_EN_S 0
1852 #define VP_SB_CPM_PF_VF_CTRL_QUEUE_EN_M BIT(0)
1853 #define GL_DCB_TDSCP2TC_BLOCK_DIS 0x00049218 /* Reset Source: CORER */
1854 #define GL_DCB_TDSCP2TC_BLOCK_DIS_DSCP2TC_BLOCK_DIS_S 0
1855 #define GL_DCB_TDSCP2TC_BLOCK_DIS_DSCP2TC_BLOCK_DIS_M BIT(0)
1856 #define GL_DCB_TDSCP2TC_BLOCK_IPV4(_i) (0x00049018 + ((_i) * 4)) /* _i=0...63 */ /* Reset Source: CORER */
1857 #define GL_DCB_TDSCP2TC_BLOCK_IPV4_MAX_INDEX 63
1858 #define GL_DCB_TDSCP2TC_BLOCK_IPV4_TC_BLOCK_LUT_S 0
1859 #define GL_DCB_TDSCP2TC_BLOCK_IPV4_TC_BLOCK_LUT_M MAKEMASK(0xFFFFFFFF, 0)
1860 #define GL_DCB_TDSCP2TC_BLOCK_IPV6(_i) (0x00049118 + ((_i) * 4)) /* _i=0...63 */ /* Reset Source: CORER */
1861 #define GL_DCB_TDSCP2TC_BLOCK_IPV6_MAX_INDEX 63
1862 #define GL_DCB_TDSCP2TC_BLOCK_IPV6_TC_BLOCK_LUT_S 0
1863 #define GL_DCB_TDSCP2TC_BLOCK_IPV6_TC_BLOCK_LUT_M MAKEMASK(0xFFFFFFFF, 0)
1864 #define GLDCB_GENC 0x00083044 /* Reset Source: CORER */
1865 #define GLDCB_GENC_PCIRTT_S 0
1866 #define GLDCB_GENC_PCIRTT_M MAKEMASK(0xFFFF, 0)
1867 #define GLDCB_PRS_RETSTCC(_i) (0x002000B0 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
1868 #define GLDCB_PRS_RETSTCC_MAX_INDEX 31
1869 #define GLDCB_PRS_RETSTCC_BWSHARE_S 0
1870 #define GLDCB_PRS_RETSTCC_BWSHARE_M MAKEMASK(0x7F, 0)
1871 #define GLDCB_PRS_RETSTCC_ETSTC_S 31
1872 #define GLDCB_PRS_RETSTCC_ETSTC_M BIT(31)
1873 #define GLDCB_PRS_RSPMC 0x00200160 /* Reset Source: CORER */
1874 #define GLDCB_PRS_RSPMC_RSPM_S 0
1875 #define GLDCB_PRS_RSPMC_RSPM_M MAKEMASK(0xFF, 0)
1876 #define GLDCB_PRS_RSPMC_RPM_MODE_S 8
1877 #define GLDCB_PRS_RSPMC_RPM_MODE_M MAKEMASK(0x3, 8)
1878 #define GLDCB_PRS_RSPMC_PRR_MAX_EXP_S 10
1879 #define GLDCB_PRS_RSPMC_PRR_MAX_EXP_M MAKEMASK(0xF, 10)
1880 #define GLDCB_PRS_RSPMC_PFCTIMER_S 14
1881 #define GLDCB_PRS_RSPMC_PFCTIMER_M MAKEMASK(0x3FFF, 14)
1882 #define GLDCB_PRS_RSPMC_RPM_DIS_S 31
1883 #define GLDCB_PRS_RSPMC_RPM_DIS_M BIT(31)
1884 #define GLDCB_RETSTCC(_i) (0x00122140 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
1885 #define GLDCB_RETSTCC_MAX_INDEX 31
1886 #define GLDCB_RETSTCC_BWSHARE_S 0
1887 #define GLDCB_RETSTCC_BWSHARE_M MAKEMASK(0x7F, 0)
1888 #define GLDCB_RETSTCC_ETSTC_S 31
1889 #define GLDCB_RETSTCC_ETSTC_M BIT(31)
1890 #define GLDCB_RETSTCS(_i) (0x001221C0 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
1891 #define GLDCB_RETSTCS_MAX_INDEX 31
1892 #define GLDCB_RETSTCS_CREDITS_S 0
1893 #define GLDCB_RETSTCS_CREDITS_M MAKEMASK(0xFFFFFFFF, 0)
1894 #define GLDCB_RTC2PFC_RCB 0x00122100 /* Reset Source: CORER */
1895 #define GLDCB_RTC2PFC_RCB_TC2PFC_S 0
1896 #define GLDCB_RTC2PFC_RCB_TC2PFC_M MAKEMASK(0xFFFFFFFF, 0)
1897 #define GLDCB_SWT_RETSTCC(_i) (0x0020A040 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
1898 #define GLDCB_SWT_RETSTCC_MAX_INDEX 31
1899 #define GLDCB_SWT_RETSTCC_BWSHARE_S 0
1900 #define GLDCB_SWT_RETSTCC_BWSHARE_M MAKEMASK(0x7F, 0)
1901 #define GLDCB_SWT_RETSTCC_ETSTC_S 31
1902 #define GLDCB_SWT_RETSTCC_ETSTC_M BIT(31)
1903 #define GLDCB_TC2PFC 0x001D2694 /* Reset Source: CORER */
1904 #define GLDCB_TC2PFC_TC2PFC_S 0
1905 #define GLDCB_TC2PFC_TC2PFC_M MAKEMASK(0xFFFFFFFF, 0)
1906 #define GLDCB_TCB_MNG_SP 0x000AE12C /* Reset Source: CORER */
1907 #define GLDCB_TCB_MNG_SP_MNG_SP_S 0
1908 #define GLDCB_TCB_MNG_SP_MNG_SP_M BIT(0)
1909 #define GLDCB_TCB_TCLL_CFG 0x000AE134 /* Reset Source: CORER */
1910 #define GLDCB_TCB_TCLL_CFG_LLTC_S 0
1911 #define GLDCB_TCB_TCLL_CFG_LLTC_M MAKEMASK(0xFFFFFFFF, 0)
1912 #define GLDCB_TCB_WB_SP 0x000AE310 /* Reset Source: CORER */
1913 #define GLDCB_TCB_WB_SP_WB_SP_S 0
1914 #define GLDCB_TCB_WB_SP_WB_SP_M BIT(0)
1915 #define GLDCB_TCUPM_IMM_EN 0x000BC824 /* Reset Source: CORER */
1916 #define GLDCB_TCUPM_IMM_EN_IMM_EN_S 0
1917 #define GLDCB_TCUPM_IMM_EN_IMM_EN_M MAKEMASK(0xFFFFFFFF, 0)
1918 #define GLDCB_TCUPM_LEGACY_TC 0x000BC828 /* Reset Source: CORER */
1919 #define GLDCB_TCUPM_LEGACY_TC_LEGTC_S 0
1920 #define GLDCB_TCUPM_LEGACY_TC_LEGTC_M MAKEMASK(0xFFFFFFFF, 0)
1921 #define GLDCB_TCUPM_NO_EXCEED_DIS 0x000BC830 /* Reset Source: CORER */
1922 #define GLDCB_TCUPM_NO_EXCEED_DIS_NON_EXCEED_DIS_S 0
1923 #define GLDCB_TCUPM_NO_EXCEED_DIS_NON_EXCEED_DIS_M BIT(0)
1924 #define GLDCB_TCUPM_WB_DIS 0x000BC834 /* Reset Source: CORER */
1925 #define GLDCB_TCUPM_WB_DIS_PORT_DISABLE_S 0
1926 #define GLDCB_TCUPM_WB_DIS_PORT_DISABLE_M BIT(0)
1927 #define GLDCB_TCUPM_WB_DIS_TC_DISABLE_S 1
1928 #define GLDCB_TCUPM_WB_DIS_TC_DISABLE_M BIT(1)
1929 #define GLDCB_TFPFCI 0x0009949C /* Reset Source: CORER */
1930 #define GLDCB_TFPFCI_GLDCB_TFPFCI_S 0
1931 #define GLDCB_TFPFCI_GLDCB_TFPFCI_M MAKEMASK(0xFFFFFFFF, 0)
1932 #define GLDCB_TLPM_IMM_TCB 0x000A0190 /* Reset Source: CORER */
1933 #define GLDCB_TLPM_IMM_TCB_IMM_EN_S 0
1934 #define GLDCB_TLPM_IMM_TCB_IMM_EN_M MAKEMASK(0xFFFFFFFF, 0)
1935 #define GLDCB_TLPM_IMM_TCUPM 0x000A018C /* Reset Source: CORER */
1936 #define GLDCB_TLPM_IMM_TCUPM_IMM_EN_S 0
1937 #define GLDCB_TLPM_IMM_TCUPM_IMM_EN_M MAKEMASK(0xFFFFFFFF, 0)
1938 #define GLDCB_TLPM_PCI_DM 0x000A0180 /* Reset Source: CORER */
1939 #define GLDCB_TLPM_PCI_DM_MONITOR_S 0
1940 #define GLDCB_TLPM_PCI_DM_MONITOR_M MAKEMASK(0x7FFFF, 0)
1941 #define GLDCB_TLPM_PCI_DTHR 0x000A0184 /* Reset Source: CORER */
1942 #define GLDCB_TLPM_PCI_DTHR_PCI_TDATA_S 0
1943 #define GLDCB_TLPM_PCI_DTHR_PCI_TDATA_M MAKEMASK(0xFFF, 0)
1944 #define GLDCB_TPB_IMM_TLPM 0x00099468 /* Reset Source: CORER */
1945 #define GLDCB_TPB_IMM_TLPM_IMM_EN_S 0
1946 #define GLDCB_TPB_IMM_TLPM_IMM_EN_M MAKEMASK(0xFFFFFFFF, 0)
1947 #define GLDCB_TPB_IMM_TPB 0x0009946C /* Reset Source: CORER */
1948 #define GLDCB_TPB_IMM_TPB_IMM_EN_S 0
1949 #define GLDCB_TPB_IMM_TPB_IMM_EN_M MAKEMASK(0xFFFFFFFF, 0)
1950 #define GLDCB_TPB_TCLL_CFG 0x00099464 /* Reset Source: CORER */
1951 #define GLDCB_TPB_TCLL_CFG_LLTC_S 0
1952 #define GLDCB_TPB_TCLL_CFG_LLTC_M MAKEMASK(0xFFFFFFFF, 0)
1953 #define GLTCB_BULK_DWRR_REG_QUANTA 0x000AE0E0 /* Reset Source: CORER */
1954 #define GLTCB_BULK_DWRR_REG_QUANTA_QUANTA_S 0
1955 #define GLTCB_BULK_DWRR_REG_QUANTA_QUANTA_M MAKEMASK(0x7FF, 0)
1956 #define GLTCB_BULK_DWRR_REG_SAT 0x000AE0F0 /* Reset Source: CORER */
1957 #define GLTCB_BULK_DWRR_REG_SAT_SATURATION_S 0
1958 #define GLTCB_BULK_DWRR_REG_SAT_SATURATION_M MAKEMASK(0x1FFFF, 0)
1959 #define GLTCB_BULK_DWRR_WB_QUANTA 0x000AE0E4 /* Reset Source: CORER */
1960 #define GLTCB_BULK_DWRR_WB_QUANTA_QUANTA_S 0
1961 #define GLTCB_BULK_DWRR_WB_QUANTA_QUANTA_M MAKEMASK(0x7FF, 0)
1962 #define GLTCB_BULK_DWRR_WB_SAT 0x000AE0F4 /* Reset Source: CORER */
1963 #define GLTCB_BULK_DWRR_WB_SAT_SATURATION_S 0
1964 #define GLTCB_BULK_DWRR_WB_SAT_SATURATION_M MAKEMASK(0x1FFFF, 0)
1965 #define GLTCB_CREDIT_EXP_CTL 0x000AE120 /* Reset Source: CORER */
1966 #define GLTCB_CREDIT_EXP_CTL_EN_S 0
1967 #define GLTCB_CREDIT_EXP_CTL_EN_M BIT(0)
1968 #define GLTCB_CREDIT_EXP_CTL_MIN_PKT_S 1
1969 #define GLTCB_CREDIT_EXP_CTL_MIN_PKT_M MAKEMASK(0x1FF, 1)
1970 #define GLTCB_LL_DWRR_REG_QUANTA 0x000AE0E8 /* Reset Source: CORER */
1971 #define GLTCB_LL_DWRR_REG_QUANTA_QUANTA_S 0
1972 #define GLTCB_LL_DWRR_REG_QUANTA_QUANTA_M MAKEMASK(0x7FF, 0)
1973 #define GLTCB_LL_DWRR_REG_SAT 0x000AE0F8 /* Reset Source: CORER */
1974 #define GLTCB_LL_DWRR_REG_SAT_SATURATION_S 0
1975 #define GLTCB_LL_DWRR_REG_SAT_SATURATION_M MAKEMASK(0x1FFFF, 0)
1976 #define GLTCB_LL_DWRR_WB_QUANTA 0x000AE0EC /* Reset Source: CORER */
1977 #define GLTCB_LL_DWRR_WB_QUANTA_QUANTA_S 0
1978 #define GLTCB_LL_DWRR_WB_QUANTA_QUANTA_M MAKEMASK(0x7FF, 0)
1979 #define GLTCB_LL_DWRR_WB_SAT 0x000AE0FC /* Reset Source: CORER */
1980 #define GLTCB_LL_DWRR_WB_SAT_SATURATION_S 0
1981 #define GLTCB_LL_DWRR_WB_SAT_SATURATION_M MAKEMASK(0x1FFFF, 0)
1982 #define GLTCB_WB_RL 0x000AE238 /* Reset Source: CORER */
1983 #define GLTCB_WB_RL_PERIOD_S 0
1984 #define GLTCB_WB_RL_PERIOD_M MAKEMASK(0xFFFF, 0)
1985 #define GLTCB_WB_RL_EN_S 16
1986 #define GLTCB_WB_RL_EN_M BIT(16)
1987 #define GLTPB_WB_RL 0x00099460 /* Reset Source: CORER */
1988 #define GLTPB_WB_RL_PERIOD_S 0
1989 #define GLTPB_WB_RL_PERIOD_M MAKEMASK(0xFFFF, 0)
1990 #define GLTPB_WB_RL_EN_S 16
1991 #define GLTPB_WB_RL_EN_M BIT(16)
1992 #define PRTDCB_FCCFG 0x001E4640 /* Reset Source: GLOBR */
1993 #define PRTDCB_FCCFG_TFCE_S 3
1994 #define PRTDCB_FCCFG_TFCE_M MAKEMASK(0x3, 3)
1995 #define PRTDCB_FCRTV 0x001E4600 /* Reset Source: GLOBR */
1996 #define PRTDCB_FCRTV_FC_REFRESH_TH_S 0
1997 #define PRTDCB_FCRTV_FC_REFRESH_TH_M MAKEMASK(0xFFFF, 0)
1998 #define PRTDCB_FCTTVN(_i) (0x001E4580 + ((_i) * 32)) /* _i=0...3 */ /* Reset Source: GLOBR */
1999 #define PRTDCB_FCTTVN_MAX_INDEX 3
2000 #define PRTDCB_FCTTVN_TTV_2N_S 0
2001 #define PRTDCB_FCTTVN_TTV_2N_M MAKEMASK(0xFFFF, 0)
2002 #define PRTDCB_FCTTVN_TTV_2N_P1_S 16
2003 #define PRTDCB_FCTTVN_TTV_2N_P1_M MAKEMASK(0xFFFF, 16)
2004 #define PRTDCB_GENC 0x00083000 /* Reset Source: CORER */
2005 #define PRTDCB_GENC_NUMTC_S 2
2006 #define PRTDCB_GENC_NUMTC_M MAKEMASK(0xF, 2)
2007 #define PRTDCB_GENC_FCOEUP_S 6
2008 #define PRTDCB_GENC_FCOEUP_M MAKEMASK(0x7, 6)
2009 #define PRTDCB_GENC_FCOEUP_VALID_S 9
2010 #define PRTDCB_GENC_FCOEUP_VALID_M BIT(9)
2011 #define PRTDCB_GENC_PFCLDA_S 16
2012 #define PRTDCB_GENC_PFCLDA_M MAKEMASK(0xFFFF, 16)
2013 #define PRTDCB_GENS 0x00083020 /* Reset Source: CORER */
2014 #define PRTDCB_GENS_DCBX_STATUS_S 0
2015 #define PRTDCB_GENS_DCBX_STATUS_M MAKEMASK(0x7, 0)
2016 #define PRTDCB_PRS_RETSC 0x002001A0 /* Reset Source: CORER */
2017 #define PRTDCB_PRS_RETSC_ETS_MODE_S 0
2018 #define PRTDCB_PRS_RETSC_ETS_MODE_M BIT(0)
2019 #define PRTDCB_PRS_RETSC_NON_ETS_MODE_S 1
2020 #define PRTDCB_PRS_RETSC_NON_ETS_MODE_M BIT(1)
2021 #define PRTDCB_PRS_RETSC_ETS_MAX_EXP_S 2
2022 #define PRTDCB_PRS_RETSC_ETS_MAX_EXP_M MAKEMASK(0xF, 2)
2023 #define PRTDCB_PRS_RPRRC 0x00200180 /* Reset Source: CORER */
2024 #define PRTDCB_PRS_RPRRC_BWSHARE_S 0
2025 #define PRTDCB_PRS_RPRRC_BWSHARE_M MAKEMASK(0x3FF, 0)
2026 #define PRTDCB_PRS_RPRRC_BWSHARE_DIS_S 31
2027 #define PRTDCB_PRS_RPRRC_BWSHARE_DIS_M BIT(31)
2028 #define PRTDCB_RETSC 0x001222A0 /* Reset Source: CORER */
2029 #define PRTDCB_RETSC_ETS_MODE_S 0
2030 #define PRTDCB_RETSC_ETS_MODE_M BIT(0)
2031 #define PRTDCB_RETSC_NON_ETS_MODE_S 1
2032 #define PRTDCB_RETSC_NON_ETS_MODE_M BIT(1)
2033 #define PRTDCB_RETSC_ETS_MAX_EXP_S 2
2034 #define PRTDCB_RETSC_ETS_MAX_EXP_M MAKEMASK(0xF, 2)
2035 #define PRTDCB_RPRRC 0x001220C0 /* Reset Source: CORER */
2036 #define PRTDCB_RPRRC_BWSHARE_S 0
2037 #define PRTDCB_RPRRC_BWSHARE_M MAKEMASK(0x3FF, 0)
2038 #define PRTDCB_RPRRC_BWSHARE_DIS_S 31
2039 #define PRTDCB_RPRRC_BWSHARE_DIS_M BIT(31)
2040 #define PRTDCB_RPRRS 0x001220E0 /* Reset Source: CORER */
2041 #define PRTDCB_RPRRS_CREDITS_S 0
2042 #define PRTDCB_RPRRS_CREDITS_M MAKEMASK(0xFFFFFFFF, 0)
2043 #define PRTDCB_RUP_TDPU 0x00040960 /* Reset Source: CORER */
2044 #define PRTDCB_RUP_TDPU_NOVLANUP_S 0
2045 #define PRTDCB_RUP_TDPU_NOVLANUP_M MAKEMASK(0x7, 0)
2046 #define PRTDCB_RUP2TC 0x001D2640 /* Reset Source: CORER */
2047 #define PRTDCB_RUP2TC_UP0TC_S 0
2048 #define PRTDCB_RUP2TC_UP0TC_M MAKEMASK(0x7, 0)
2049 #define PRTDCB_RUP2TC_UP1TC_S 3
2050 #define PRTDCB_RUP2TC_UP1TC_M MAKEMASK(0x7, 3)
2051 #define PRTDCB_RUP2TC_UP2TC_S 6
2052 #define PRTDCB_RUP2TC_UP2TC_M MAKEMASK(0x7, 6)
2053 #define PRTDCB_RUP2TC_UP3TC_S 9
2054 #define PRTDCB_RUP2TC_UP3TC_M MAKEMASK(0x7, 9)
2055 #define PRTDCB_RUP2TC_UP4TC_S 12
2056 #define PRTDCB_RUP2TC_UP4TC_M MAKEMASK(0x7, 12)
2057 #define PRTDCB_RUP2TC_UP5TC_S 15
2058 #define PRTDCB_RUP2TC_UP5TC_M MAKEMASK(0x7, 15)
2059 #define PRTDCB_RUP2TC_UP6TC_S 18
2060 #define PRTDCB_RUP2TC_UP6TC_M MAKEMASK(0x7, 18)
2061 #define PRTDCB_RUP2TC_UP7TC_S 21
2062 #define PRTDCB_RUP2TC_UP7TC_M MAKEMASK(0x7, 21)
2063 #define PRTDCB_SWT_RETSC 0x0020A140 /* Reset Source: CORER */
2064 #define PRTDCB_SWT_RETSC_ETS_MODE_S 0
2065 #define PRTDCB_SWT_RETSC_ETS_MODE_M BIT(0)
2066 #define PRTDCB_SWT_RETSC_NON_ETS_MODE_S 1
2067 #define PRTDCB_SWT_RETSC_NON_ETS_MODE_M BIT(1)
2068 #define PRTDCB_SWT_RETSC_ETS_MAX_EXP_S 2
2069 #define PRTDCB_SWT_RETSC_ETS_MAX_EXP_M MAKEMASK(0xF, 2)
2070 #define PRTDCB_TCB_DWRR_CREDITS 0x000AE000 /* Reset Source: CORER */
2071 #define PRTDCB_TCB_DWRR_CREDITS_CREDITS_S 0
2072 #define PRTDCB_TCB_DWRR_CREDITS_CREDITS_M MAKEMASK(0x3FFFF, 0)
2073 #define PRTDCB_TCB_DWRR_QUANTA 0x000AE020 /* Reset Source: CORER */
2074 #define PRTDCB_TCB_DWRR_QUANTA_QUANTA_S 0
2075 #define PRTDCB_TCB_DWRR_QUANTA_QUANTA_M MAKEMASK(0x7FF, 0)
2076 #define PRTDCB_TCB_DWRR_SAT 0x000AE040 /* Reset Source: CORER */
2077 #define PRTDCB_TCB_DWRR_SAT_SATURATION_S 0
2078 #define PRTDCB_TCB_DWRR_SAT_SATURATION_M MAKEMASK(0x1FFFF, 0)
2079 #define PRTDCB_TCUPM_NO_EXCEED_DM 0x000BC3C0 /* Reset Source: CORER */
2080 #define PRTDCB_TCUPM_NO_EXCEED_DM_MONITOR_S 0
2081 #define PRTDCB_TCUPM_NO_EXCEED_DM_MONITOR_M MAKEMASK(0x7FFFF, 0)
2082 #define PRTDCB_TCUPM_REG_CM 0x000BC360 /* Reset Source: CORER */
2083 #define PRTDCB_TCUPM_REG_CM_MONITOR_S 0
2084 #define PRTDCB_TCUPM_REG_CM_MONITOR_M MAKEMASK(0x7FFF, 0)
2085 #define PRTDCB_TCUPM_REG_CTHR 0x000BC380 /* Reset Source: CORER */
2086 #define PRTDCB_TCUPM_REG_CTHR_PORTOFFTH_H_S 0
2087 #define PRTDCB_TCUPM_REG_CTHR_PORTOFFTH_H_M MAKEMASK(0x7FFF, 0)
2088 #define PRTDCB_TCUPM_REG_CTHR_PORTOFFTH_L_S 15
2089 #define PRTDCB_TCUPM_REG_CTHR_PORTOFFTH_L_M MAKEMASK(0x7FFF, 15)
2090 #define PRTDCB_TCUPM_REG_DM 0x000BC3A0 /* Reset Source: CORER */
2091 #define PRTDCB_TCUPM_REG_DM_MONITOR_S 0
2092 #define PRTDCB_TCUPM_REG_DM_MONITOR_M MAKEMASK(0x7FFFF, 0)
2093 #define PRTDCB_TCUPM_REG_DTHR 0x000BC3E0 /* Reset Source: CORER */
2094 #define PRTDCB_TCUPM_REG_DTHR_PORTOFFTH_H_S 0
2095 #define PRTDCB_TCUPM_REG_DTHR_PORTOFFTH_H_M MAKEMASK(0xFFF, 0)
2096 #define PRTDCB_TCUPM_REG_DTHR_PORTOFFTH_L_S 12
2097 #define PRTDCB_TCUPM_REG_DTHR_PORTOFFTH_L_M MAKEMASK(0xFFF, 12)
2098 #define PRTDCB_TCUPM_REG_PE_HB_DM 0x000BC400 /* Reset Source: CORER */
2099 #define PRTDCB_TCUPM_REG_PE_HB_DM_MONITOR_S 0
2100 #define PRTDCB_TCUPM_REG_PE_HB_DM_MONITOR_M MAKEMASK(0xFFF, 0)
2101 #define PRTDCB_TCUPM_REG_PE_HB_DTHR 0x000BC420 /* Reset Source: CORER */
2102 #define PRTDCB_TCUPM_REG_PE_HB_DTHR_PORTOFFTH_H_S 0
2103 #define PRTDCB_TCUPM_REG_PE_HB_DTHR_PORTOFFTH_H_M MAKEMASK(0xFFF, 0)
2104 #define PRTDCB_TCUPM_REG_PE_HB_DTHR_PORTOFFTH_L_S 12
2105 #define PRTDCB_TCUPM_REG_PE_HB_DTHR_PORTOFFTH_L_M MAKEMASK(0xFFF, 12)
2106 #define PRTDCB_TCUPM_WAIT_PFC_CM 0x000BC440 /* Reset Source: CORER */
2107 #define PRTDCB_TCUPM_WAIT_PFC_CM_MONITOR_S 0
2108 #define PRTDCB_TCUPM_WAIT_PFC_CM_MONITOR_M MAKEMASK(0x7FFF, 0)
2109 #define PRTDCB_TCUPM_WAIT_PFC_CTHR 0x000BC460 /* Reset Source: CORER */
2110 #define PRTDCB_TCUPM_WAIT_PFC_CTHR_PORTOFFTH_S 0
2111 #define PRTDCB_TCUPM_WAIT_PFC_CTHR_PORTOFFTH_M MAKEMASK(0x7FFF, 0)
2112 #define PRTDCB_TCUPM_WAIT_PFC_DM 0x000BC480 /* Reset Source: CORER */
2113 #define PRTDCB_TCUPM_WAIT_PFC_DM_MONITOR_S 0
2114 #define PRTDCB_TCUPM_WAIT_PFC_DM_MONITOR_M MAKEMASK(0x7FFFF, 0)
2115 #define PRTDCB_TCUPM_WAIT_PFC_DTHR 0x000BC4A0 /* Reset Source: CORER */
2116 #define PRTDCB_TCUPM_WAIT_PFC_DTHR_PORTOFFTH_S 0
2117 #define PRTDCB_TCUPM_WAIT_PFC_DTHR_PORTOFFTH_M MAKEMASK(0xFFF, 0)
2118 #define PRTDCB_TCUPM_WAIT_PFC_PE_HB_DM 0x000BC4C0 /* Reset Source: CORER */
2119 #define PRTDCB_TCUPM_WAIT_PFC_PE_HB_DM_MONITOR_S 0
2120 #define PRTDCB_TCUPM_WAIT_PFC_PE_HB_DM_MONITOR_M MAKEMASK(0xFFF, 0)
2121 #define PRTDCB_TCUPM_WAIT_PFC_PE_HB_DTHR 0x000BC4E0 /* Reset Source: CORER */
2122 #define PRTDCB_TCUPM_WAIT_PFC_PE_HB_DTHR_PORTOFFTH_S 0
2123 #define PRTDCB_TCUPM_WAIT_PFC_PE_HB_DTHR_PORTOFFTH_M MAKEMASK(0xFFF, 0)
2124 #define PRTDCB_TDPUC 0x00040940 /* Reset Source: CORER */
2125 #define PRTDCB_TDPUC_MAX_TXFRAME_S 0
2126 #define PRTDCB_TDPUC_MAX_TXFRAME_M MAKEMASK(0xFFFF, 0)
2127 #define PRTDCB_TDPUC_MAL_LENGTH_S 16
2128 #define PRTDCB_TDPUC_MAL_LENGTH_M BIT(16)
2129 #define PRTDCB_TDPUC_MAL_CMD_S 17
2130 #define PRTDCB_TDPUC_MAL_CMD_M BIT(17)
2131 #define PRTDCB_TDPUC_TTL_DROP_S 18
2132 #define PRTDCB_TDPUC_TTL_DROP_M BIT(18)
2133 #define PRTDCB_TDPUC_UR_DROP_S 19
2134 #define PRTDCB_TDPUC_UR_DROP_M BIT(19)
2135 #define PRTDCB_TDPUC_DUMMY_S 20
2136 #define PRTDCB_TDPUC_DUMMY_M BIT(20)
2137 #define PRTDCB_TDPUC_BIG_PKT_SIZE_S 21
2138 #define PRTDCB_TDPUC_BIG_PKT_SIZE_M BIT(21)
2139 #define PRTDCB_TDPUC_L2_ACCEPT_FAIL_S 22
2140 #define PRTDCB_TDPUC_L2_ACCEPT_FAIL_M BIT(22)
2141 #define PRTDCB_TDPUC_DSCP_CHECK_FAIL_S 23
2142 #define PRTDCB_TDPUC_DSCP_CHECK_FAIL_M BIT(23)
2143 #define PRTDCB_TDPUC_RCU_ANTISPOOF_S 24
2144 #define PRTDCB_TDPUC_RCU_ANTISPOOF_M BIT(24)
2145 #define PRTDCB_TDPUC_NIC_DSI_S 25
2146 #define PRTDCB_TDPUC_NIC_DSI_M BIT(25)
2147 #define PRTDCB_TDPUC_NIC_IPSEC_S 26
2148 #define PRTDCB_TDPUC_NIC_IPSEC_M BIT(26)
2149 #define PRTDCB_TDPUC_CLEAR_DROP_S 31
2150 #define PRTDCB_TDPUC_CLEAR_DROP_M BIT(31)
2151 #define PRTDCB_TFCS 0x001E4560 /* Reset Source: GLOBR */
2152 #define PRTDCB_TFCS_TXOFF_S 0
2153 #define PRTDCB_TFCS_TXOFF_M BIT(0)
2154 #define PRTDCB_TFCS_TXOFF0_S 8
2155 #define PRTDCB_TFCS_TXOFF0_M BIT(8)
2156 #define PRTDCB_TFCS_TXOFF1_S 9
2157 #define PRTDCB_TFCS_TXOFF1_M BIT(9)
2158 #define PRTDCB_TFCS_TXOFF2_S 10
2159 #define PRTDCB_TFCS_TXOFF2_M BIT(10)
2160 #define PRTDCB_TFCS_TXOFF3_S 11
2161 #define PRTDCB_TFCS_TXOFF3_M BIT(11)
2162 #define PRTDCB_TFCS_TXOFF4_S 12
2163 #define PRTDCB_TFCS_TXOFF4_M BIT(12)
2164 #define PRTDCB_TFCS_TXOFF5_S 13
2165 #define PRTDCB_TFCS_TXOFF5_M BIT(13)
2166 #define PRTDCB_TFCS_TXOFF6_S 14
2167 #define PRTDCB_TFCS_TXOFF6_M BIT(14)
2168 #define PRTDCB_TFCS_TXOFF7_S 15
2169 #define PRTDCB_TFCS_TXOFF7_M BIT(15)
2170 #define PRTDCB_TLPM_REG_DM 0x000A0000 /* Reset Source: CORER */
2171 #define PRTDCB_TLPM_REG_DM_MONITOR_S 0
2172 #define PRTDCB_TLPM_REG_DM_MONITOR_M MAKEMASK(0x7FFFF, 0)
2173 #define PRTDCB_TLPM_REG_DTHR 0x000A0020 /* Reset Source: CORER */
2174 #define PRTDCB_TLPM_REG_DTHR_PORTOFFTH_H_S 0
2175 #define PRTDCB_TLPM_REG_DTHR_PORTOFFTH_H_M MAKEMASK(0xFFF, 0)
2176 #define PRTDCB_TLPM_REG_DTHR_PORTOFFTH_L_S 12
2177 #define PRTDCB_TLPM_REG_DTHR_PORTOFFTH_L_M MAKEMASK(0xFFF, 12)
2178 #define PRTDCB_TLPM_WAIT_PFC_DM 0x000A0040 /* Reset Source: CORER */
2179 #define PRTDCB_TLPM_WAIT_PFC_DM_MONITOR_S 0
2180 #define PRTDCB_TLPM_WAIT_PFC_DM_MONITOR_M MAKEMASK(0x7FFFF, 0)
2181 #define PRTDCB_TLPM_WAIT_PFC_DTHR 0x000A0060 /* Reset Source: CORER */
2182 #define PRTDCB_TLPM_WAIT_PFC_DTHR_PORTOFFTH_S 0
2183 #define PRTDCB_TLPM_WAIT_PFC_DTHR_PORTOFFTH_M MAKEMASK(0xFFF, 0)
2184 #define PRTDCB_TPFCTS(_i) (0x001E4660 + ((_i) * 32)) /* _i=0...7 */ /* Reset Source: GLOBR */
2185 #define PRTDCB_TPFCTS_MAX_INDEX 7
2186 #define PRTDCB_TPFCTS_PFCTIMER_S 0
2187 #define PRTDCB_TPFCTS_PFCTIMER_M MAKEMASK(0x3FFF, 0)
2188 #define PRTDCB_TUP2TC 0x001D26C0 /* Reset Source: CORER */
2189 #define PRTDCB_TUP2TC_UP0TC_S 0
2190 #define PRTDCB_TUP2TC_UP0TC_M MAKEMASK(0x7, 0)
2191 #define PRTDCB_TUP2TC_UP1TC_S 3
2192 #define PRTDCB_TUP2TC_UP1TC_M MAKEMASK(0x7, 3)
2193 #define PRTDCB_TUP2TC_UP2TC_S 6
2194 #define PRTDCB_TUP2TC_UP2TC_M MAKEMASK(0x7, 6)
2195 #define PRTDCB_TUP2TC_UP3TC_S 9
2196 #define PRTDCB_TUP2TC_UP3TC_M MAKEMASK(0x7, 9)
2197 #define PRTDCB_TUP2TC_UP4TC_S 12
2198 #define PRTDCB_TUP2TC_UP4TC_M MAKEMASK(0x7, 12)
2199 #define PRTDCB_TUP2TC_UP5TC_S 15
2200 #define PRTDCB_TUP2TC_UP5TC_M MAKEMASK(0x7, 15)
2201 #define PRTDCB_TUP2TC_UP6TC_S 18
2202 #define PRTDCB_TUP2TC_UP6TC_M MAKEMASK(0x7, 18)
2203 #define PRTDCB_TUP2TC_UP7TC_S 21
2204 #define PRTDCB_TUP2TC_UP7TC_M MAKEMASK(0x7, 21)
2205 #define PRTDCB_TX_DSCP2UP_CTL 0x00040980 /* Reset Source: CORER */
2206 #define PRTDCB_TX_DSCP2UP_CTL_DSCP2UP_ENA_S 0
2207 #define PRTDCB_TX_DSCP2UP_CTL_DSCP2UP_ENA_M BIT(0)
2208 #define PRTDCB_TX_DSCP2UP_CTL_DSCP_DEFAULT_UP_S 1
2209 #define PRTDCB_TX_DSCP2UP_CTL_DSCP_DEFAULT_UP_M MAKEMASK(0x7, 1)
2210 #define PRTDCB_TX_DSCP2UP_IPV4_LUT(_i) (0x000409A0 + ((_i) * 32)) /* _i=0...7 */ /* Reset Source: CORER */
2211 #define PRTDCB_TX_DSCP2UP_IPV4_LUT_MAX_INDEX 7
2212 #define PRTDCB_TX_DSCP2UP_IPV4_LUT_DSCP2UP_LUT_0_S 0
2213 #define PRTDCB_TX_DSCP2UP_IPV4_LUT_DSCP2UP_LUT_0_M MAKEMASK(0x7, 0)
2214 #define PRTDCB_TX_DSCP2UP_IPV4_LUT_DSCP2UP_LUT_1_S 4
2215 #define PRTDCB_TX_DSCP2UP_IPV4_LUT_DSCP2UP_LUT_1_M MAKEMASK(0x7, 4)
2216 #define PRTDCB_TX_DSCP2UP_IPV4_LUT_DSCP2UP_LUT_2_S 8
2217 #define PRTDCB_TX_DSCP2UP_IPV4_LUT_DSCP2UP_LUT_2_M MAKEMASK(0x7, 8)
2218 #define PRTDCB_TX_DSCP2UP_IPV4_LUT_DSCP2UP_LUT_3_S 12
2219 #define PRTDCB_TX_DSCP2UP_IPV4_LUT_DSCP2UP_LUT_3_M MAKEMASK(0x7, 12)
2220 #define PRTDCB_TX_DSCP2UP_IPV4_LUT_DSCP2UP_LUT_4_S 16
2221 #define PRTDCB_TX_DSCP2UP_IPV4_LUT_DSCP2UP_LUT_4_M MAKEMASK(0x7, 16)
2222 #define PRTDCB_TX_DSCP2UP_IPV4_LUT_DSCP2UP_LUT_5_S 20
2223 #define PRTDCB_TX_DSCP2UP_IPV4_LUT_DSCP2UP_LUT_5_M MAKEMASK(0x7, 20)
2224 #define PRTDCB_TX_DSCP2UP_IPV4_LUT_DSCP2UP_LUT_6_S 24
2225 #define PRTDCB_TX_DSCP2UP_IPV4_LUT_DSCP2UP_LUT_6_M MAKEMASK(0x7, 24)
2226 #define PRTDCB_TX_DSCP2UP_IPV4_LUT_DSCP2UP_LUT_7_S 28
2227 #define PRTDCB_TX_DSCP2UP_IPV4_LUT_DSCP2UP_LUT_7_M MAKEMASK(0x7, 28)
2228 #define PRTDCB_TX_DSCP2UP_IPV6_LUT(_i) (0x00040AA0 + ((_i) * 32)) /* _i=0...7 */ /* Reset Source: CORER */
2229 #define PRTDCB_TX_DSCP2UP_IPV6_LUT_MAX_INDEX 7
2230 #define PRTDCB_TX_DSCP2UP_IPV6_LUT_DSCP2UP_LUT_0_S 0
2231 #define PRTDCB_TX_DSCP2UP_IPV6_LUT_DSCP2UP_LUT_0_M MAKEMASK(0x7, 0)
2232 #define PRTDCB_TX_DSCP2UP_IPV6_LUT_DSCP2UP_LUT_1_S 4
2233 #define PRTDCB_TX_DSCP2UP_IPV6_LUT_DSCP2UP_LUT_1_M MAKEMASK(0x7, 4)
2234 #define PRTDCB_TX_DSCP2UP_IPV6_LUT_DSCP2UP_LUT_2_S 8
2235 #define PRTDCB_TX_DSCP2UP_IPV6_LUT_DSCP2UP_LUT_2_M MAKEMASK(0x7, 8)
2236 #define PRTDCB_TX_DSCP2UP_IPV6_LUT_DSCP2UP_LUT_3_S 12
2237 #define PRTDCB_TX_DSCP2UP_IPV6_LUT_DSCP2UP_LUT_3_M MAKEMASK(0x7, 12)
2238 #define PRTDCB_TX_DSCP2UP_IPV6_LUT_DSCP2UP_LUT_4_S 16
2239 #define PRTDCB_TX_DSCP2UP_IPV6_LUT_DSCP2UP_LUT_4_M MAKEMASK(0x7, 16)
2240 #define PRTDCB_TX_DSCP2UP_IPV6_LUT_DSCP2UP_LUT_5_S 20
2241 #define PRTDCB_TX_DSCP2UP_IPV6_LUT_DSCP2UP_LUT_5_M MAKEMASK(0x7, 20)
2242 #define PRTDCB_TX_DSCP2UP_IPV6_LUT_DSCP2UP_LUT_6_S 24
2243 #define PRTDCB_TX_DSCP2UP_IPV6_LUT_DSCP2UP_LUT_6_M MAKEMASK(0x7, 24)
2244 #define PRTDCB_TX_DSCP2UP_IPV6_LUT_DSCP2UP_LUT_7_S 28
2245 #define PRTDCB_TX_DSCP2UP_IPV6_LUT_DSCP2UP_LUT_7_M MAKEMASK(0x7, 28)
2246 #define PRTTCB_BULK_DWRR_REG_CREDITS 0x000AE060 /* Reset Source: CORER */
2247 #define PRTTCB_BULK_DWRR_REG_CREDITS_CREDITS_S 0
2248 #define PRTTCB_BULK_DWRR_REG_CREDITS_CREDITS_M MAKEMASK(0x3FFFF, 0)
2249 #define PRTTCB_BULK_DWRR_WB_CREDITS 0x000AE080 /* Reset Source: CORER */
2250 #define PRTTCB_BULK_DWRR_WB_CREDITS_CREDITS_S 0
2251 #define PRTTCB_BULK_DWRR_WB_CREDITS_CREDITS_M MAKEMASK(0x3FFFF, 0)
2252 #define PRTTCB_CREDIT_EXP 0x000AE100 /* Reset Source: CORER */
2253 #define PRTTCB_CREDIT_EXP_EXPANSION_S 0
2254 #define PRTTCB_CREDIT_EXP_EXPANSION_M MAKEMASK(0xFF, 0)
2255 #define PRTTCB_LL_DWRR_REG_CREDITS 0x000AE0A0 /* Reset Source: CORER */
2256 #define PRTTCB_LL_DWRR_REG_CREDITS_CREDITS_S 0
2257 #define PRTTCB_LL_DWRR_REG_CREDITS_CREDITS_M MAKEMASK(0x3FFFF, 0)
2258 #define PRTTCB_LL_DWRR_WB_CREDITS 0x000AE0C0 /* Reset Source: CORER */
2259 #define PRTTCB_LL_DWRR_WB_CREDITS_CREDITS_S 0
2260 #define PRTTCB_LL_DWRR_WB_CREDITS_CREDITS_M MAKEMASK(0x3FFFF, 0)
2261 #define TCDCB_TCUPM_WAIT_CM(_i) (0x000BC520 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
2262 #define TCDCB_TCUPM_WAIT_CM_MAX_INDEX 31
2263 #define TCDCB_TCUPM_WAIT_CM_MONITOR_S 0
2264 #define TCDCB_TCUPM_WAIT_CM_MONITOR_M MAKEMASK(0x7FFF, 0)
2265 #define TCDCB_TCUPM_WAIT_CTHR(_i) (0x000BC5A0 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
2266 #define TCDCB_TCUPM_WAIT_CTHR_MAX_INDEX 31
2267 #define TCDCB_TCUPM_WAIT_CTHR_TCOFFTH_S 0
2268 #define TCDCB_TCUPM_WAIT_CTHR_TCOFFTH_M MAKEMASK(0x7FFF, 0)
2269 #define TCDCB_TCUPM_WAIT_DM(_i) (0x000BC620 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
2270 #define TCDCB_TCUPM_WAIT_DM_MAX_INDEX 31
2271 #define TCDCB_TCUPM_WAIT_DM_MONITOR_S 0
2272 #define TCDCB_TCUPM_WAIT_DM_MONITOR_M MAKEMASK(0x7FFFF, 0)
2273 #define TCDCB_TCUPM_WAIT_DTHR(_i) (0x000BC6A0 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
2274 #define TCDCB_TCUPM_WAIT_DTHR_MAX_INDEX 31
2275 #define TCDCB_TCUPM_WAIT_DTHR_TCOFFTH_S 0
2276 #define TCDCB_TCUPM_WAIT_DTHR_TCOFFTH_M MAKEMASK(0xFFF, 0)
2277 #define TCDCB_TCUPM_WAIT_PE_HB_DM(_i) (0x000BC720 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
2278 #define TCDCB_TCUPM_WAIT_PE_HB_DM_MAX_INDEX 31
2279 #define TCDCB_TCUPM_WAIT_PE_HB_DM_MONITOR_S 0
2280 #define TCDCB_TCUPM_WAIT_PE_HB_DM_MONITOR_M MAKEMASK(0xFFF, 0)
2281 #define TCDCB_TCUPM_WAIT_PE_HB_DTHR(_i) (0x000BC7A0 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
2282 #define TCDCB_TCUPM_WAIT_PE_HB_DTHR_MAX_INDEX 31
2283 #define TCDCB_TCUPM_WAIT_PE_HB_DTHR_TCOFFTH_S 0
2284 #define TCDCB_TCUPM_WAIT_PE_HB_DTHR_TCOFFTH_M MAKEMASK(0xFFF, 0)
2285 #define TCDCB_TLPM_WAIT_DM(_i) (0x000A0080 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
2286 #define TCDCB_TLPM_WAIT_DM_MAX_INDEX 31
2287 #define TCDCB_TLPM_WAIT_DM_MONITOR_S 0
2288 #define TCDCB_TLPM_WAIT_DM_MONITOR_M MAKEMASK(0x7FFFF, 0)
2289 #define TCDCB_TLPM_WAIT_DTHR(_i) (0x000A0100 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
2290 #define TCDCB_TLPM_WAIT_DTHR_MAX_INDEX 31
2291 #define TCDCB_TLPM_WAIT_DTHR_TCOFFTH_S 0
2292 #define TCDCB_TLPM_WAIT_DTHR_TCOFFTH_M MAKEMASK(0xFFF, 0)
2293 #define TCTCB_WB_RL_TC_CFG(_i) (0x000AE138 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
2294 #define TCTCB_WB_RL_TC_CFG_MAX_INDEX 31
2295 #define TCTCB_WB_RL_TC_CFG_TOKENS_S 0
2296 #define TCTCB_WB_RL_TC_CFG_TOKENS_M MAKEMASK(0xFFF, 0)
2297 #define TCTCB_WB_RL_TC_CFG_BURST_SIZE_S 12
2298 #define TCTCB_WB_RL_TC_CFG_BURST_SIZE_M MAKEMASK(0x3FF, 12)
2299 #define TCTCB_WB_RL_TC_STAT(_i) (0x000AE1B8 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
2300 #define TCTCB_WB_RL_TC_STAT_MAX_INDEX 31
2301 #define TCTCB_WB_RL_TC_STAT_BUCKET_S 0
2302 #define TCTCB_WB_RL_TC_STAT_BUCKET_M MAKEMASK(0x1FFFF, 0)
2303 #define TPB_BULK_DWRR_REG_QUANTA 0x00099340 /* Reset Source: CORER */
2304 #define TPB_BULK_DWRR_REG_QUANTA_QUANTA_S 0
2305 #define TPB_BULK_DWRR_REG_QUANTA_QUANTA_M MAKEMASK(0x7FF, 0)
2306 #define TPB_BULK_DWRR_REG_SAT 0x00099350 /* Reset Source: CORER */
2307 #define TPB_BULK_DWRR_REG_SAT_SATURATION_S 0
2308 #define TPB_BULK_DWRR_REG_SAT_SATURATION_M MAKEMASK(0x1FFFF, 0)
2309 #define TPB_BULK_DWRR_WB_QUANTA 0x00099344 /* Reset Source: CORER */
2310 #define TPB_BULK_DWRR_WB_QUANTA_QUANTA_S 0
2311 #define TPB_BULK_DWRR_WB_QUANTA_QUANTA_M MAKEMASK(0x7FF, 0)
2312 #define TPB_BULK_DWRR_WB_SAT 0x00099354 /* Reset Source: CORER */
2313 #define TPB_BULK_DWRR_WB_SAT_SATURATION_S 0
2314 #define TPB_BULK_DWRR_WB_SAT_SATURATION_M MAKEMASK(0x1FFFF, 0)
2315 #define TPB_GLDCB_TCB_WB_SP 0x0009966C /* Reset Source: CORER */
2316 #define TPB_GLDCB_TCB_WB_SP_WB_SP_S 0
2317 #define TPB_GLDCB_TCB_WB_SP_WB_SP_M BIT(0)
2318 #define TPB_GLTCB_CREDIT_EXP_CTL 0x00099664 /* Reset Source: CORER */
2319 #define TPB_GLTCB_CREDIT_EXP_CTL_EN_S 0
2320 #define TPB_GLTCB_CREDIT_EXP_CTL_EN_M BIT(0)
2321 #define TPB_GLTCB_CREDIT_EXP_CTL_MIN_PKT_S 1
2322 #define TPB_GLTCB_CREDIT_EXP_CTL_MIN_PKT_M MAKEMASK(0x1FF, 1)
2323 #define TPB_LL_DWRR_REG_QUANTA 0x00099348 /* Reset Source: CORER */
2324 #define TPB_LL_DWRR_REG_QUANTA_QUANTA_S 0
2325 #define TPB_LL_DWRR_REG_QUANTA_QUANTA_M MAKEMASK(0x7FF, 0)
2326 #define TPB_LL_DWRR_REG_SAT 0x00099358 /* Reset Source: CORER */
2327 #define TPB_LL_DWRR_REG_SAT_SATURATION_S 0
2328 #define TPB_LL_DWRR_REG_SAT_SATURATION_M MAKEMASK(0x1FFFF, 0)
2329 #define TPB_LL_DWRR_WB_QUANTA 0x0009934C /* Reset Source: CORER */
2330 #define TPB_LL_DWRR_WB_QUANTA_QUANTA_S 0
2331 #define TPB_LL_DWRR_WB_QUANTA_QUANTA_M MAKEMASK(0x7FF, 0)
2332 #define TPB_LL_DWRR_WB_SAT 0x0009935C /* Reset Source: CORER */
2333 #define TPB_LL_DWRR_WB_SAT_SATURATION_S 0
2334 #define TPB_LL_DWRR_WB_SAT_SATURATION_M MAKEMASK(0x1FFFF, 0)
2335 #define TPB_PRTDCB_TCB_DWRR_CREDITS 0x000991C0 /* Reset Source: CORER */
2336 #define TPB_PRTDCB_TCB_DWRR_CREDITS_CREDITS_S 0
2337 #define TPB_PRTDCB_TCB_DWRR_CREDITS_CREDITS_M MAKEMASK(0x3FFFF, 0)
2338 #define TPB_PRTDCB_TCB_DWRR_QUANTA 0x00099220 /* Reset Source: CORER */
2339 #define TPB_PRTDCB_TCB_DWRR_QUANTA_QUANTA_S 0
2340 #define TPB_PRTDCB_TCB_DWRR_QUANTA_QUANTA_M MAKEMASK(0x7FF, 0)
2341 #define TPB_PRTDCB_TCB_DWRR_SAT 0x00099260 /* Reset Source: CORER */
2342 #define TPB_PRTDCB_TCB_DWRR_SAT_SATURATION_S 0
2343 #define TPB_PRTDCB_TCB_DWRR_SAT_SATURATION_M MAKEMASK(0x1FFFF, 0)
2344 #define TPB_PRTTCB_BULK_DWRR_REG_CREDITS 0x000992A0 /* Reset Source: CORER */
2345 #define TPB_PRTTCB_BULK_DWRR_REG_CREDITS_CREDITS_S 0
2346 #define TPB_PRTTCB_BULK_DWRR_REG_CREDITS_CREDITS_M MAKEMASK(0x3FFFF, 0)
2347 #define TPB_PRTTCB_BULK_DWRR_WB_CREDITS 0x000992C0 /* Reset Source: CORER */
2348 #define TPB_PRTTCB_BULK_DWRR_WB_CREDITS_CREDITS_S 0
2349 #define TPB_PRTTCB_BULK_DWRR_WB_CREDITS_CREDITS_M MAKEMASK(0x3FFFF, 0)
2350 #define TPB_PRTTCB_CREDIT_EXP 0x00099644 /* Reset Source: CORER */
2351 #define TPB_PRTTCB_CREDIT_EXP_EXPANSION_S 0
2352 #define TPB_PRTTCB_CREDIT_EXP_EXPANSION_M MAKEMASK(0xFF, 0)
2353 #define TPB_PRTTCB_LL_DWRR_REG_CREDITS 0x00099300 /* Reset Source: CORER */
2354 #define TPB_PRTTCB_LL_DWRR_REG_CREDITS_CREDITS_S 0
2355 #define TPB_PRTTCB_LL_DWRR_REG_CREDITS_CREDITS_M MAKEMASK(0x3FFFF, 0)
2356 #define TPB_PRTTCB_LL_DWRR_WB_CREDITS 0x00099320 /* Reset Source: CORER */
2357 #define TPB_PRTTCB_LL_DWRR_WB_CREDITS_CREDITS_S 0
2358 #define TPB_PRTTCB_LL_DWRR_WB_CREDITS_CREDITS_M MAKEMASK(0x3FFFF, 0)
2359 #define TPB_WB_RL_TC_CFG(_i) (0x00099360 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
2360 #define TPB_WB_RL_TC_CFG_MAX_INDEX 31
2361 #define TPB_WB_RL_TC_CFG_TOKENS_S 0
2362 #define TPB_WB_RL_TC_CFG_TOKENS_M MAKEMASK(0xFFF, 0)
2363 #define TPB_WB_RL_TC_CFG_BURST_SIZE_S 12
2364 #define TPB_WB_RL_TC_CFG_BURST_SIZE_M MAKEMASK(0x3FF, 12)
2365 #define TPB_WB_RL_TC_STAT(_i) (0x000993E0 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
2366 #define TPB_WB_RL_TC_STAT_MAX_INDEX 31
2367 #define TPB_WB_RL_TC_STAT_BUCKET_S 0
2368 #define TPB_WB_RL_TC_STAT_BUCKET_M MAKEMASK(0x1FFFF, 0)
2369 #define GL_ACLEXT_CDMD_L1SEL(_i) (0x00210054 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2370 #define GL_ACLEXT_CDMD_L1SEL_MAX_INDEX 2
2371 #define GL_ACLEXT_CDMD_L1SEL_RX_SEL_S 0
2372 #define GL_ACLEXT_CDMD_L1SEL_RX_SEL_M MAKEMASK(0x1F, 0)
2373 #define GL_ACLEXT_CDMD_L1SEL_TX_SEL_S 8
2374 #define GL_ACLEXT_CDMD_L1SEL_TX_SEL_M MAKEMASK(0x1F, 8)
2375 #define GL_ACLEXT_CDMD_L1SEL_AUX0_SEL_S 16
2376 #define GL_ACLEXT_CDMD_L1SEL_AUX0_SEL_M MAKEMASK(0x1F, 16)
2377 #define GL_ACLEXT_CDMD_L1SEL_AUX1_SEL_S 24
2378 #define GL_ACLEXT_CDMD_L1SEL_AUX1_SEL_M MAKEMASK(0x1F, 24)
2379 #define GL_ACLEXT_CDMD_L1SEL_BIDIR_ENA_S 30
2380 #define GL_ACLEXT_CDMD_L1SEL_BIDIR_ENA_M MAKEMASK(0x3, 30)
2381 #define GL_ACLEXT_CTLTBL_L2ADDR(_i) (0x00210084 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2382 #define GL_ACLEXT_CTLTBL_L2ADDR_MAX_INDEX 2
2383 #define GL_ACLEXT_CTLTBL_L2ADDR_LINE_OFF_S 0
2384 #define GL_ACLEXT_CTLTBL_L2ADDR_LINE_OFF_M MAKEMASK(0x7, 0)
2385 #define GL_ACLEXT_CTLTBL_L2ADDR_LINE_IDX_S 8
2386 #define GL_ACLEXT_CTLTBL_L2ADDR_LINE_IDX_M MAKEMASK(0x7, 8)
2387 #define GL_ACLEXT_CTLTBL_L2ADDR_AUTO_INC_S 31
2388 #define GL_ACLEXT_CTLTBL_L2ADDR_AUTO_INC_M BIT(31)
2389 #define GL_ACLEXT_CTLTBL_L2DATA(_i) (0x00210090 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2390 #define GL_ACLEXT_CTLTBL_L2DATA_MAX_INDEX 2
2391 #define GL_ACLEXT_CTLTBL_L2DATA_DATA_S 0
2392 #define GL_ACLEXT_CTLTBL_L2DATA_DATA_M MAKEMASK(0xFFFFFFFF, 0)
2393 #define GL_ACLEXT_DFLT_L2PRFL(_i) (0x00210138 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2394 #define GL_ACLEXT_DFLT_L2PRFL_MAX_INDEX 2
2395 #define GL_ACLEXT_DFLT_L2PRFL_DFLT_PRFL_S 0
2396 #define GL_ACLEXT_DFLT_L2PRFL_DFLT_PRFL_M MAKEMASK(0xFFFF, 0)
2397 #define GL_ACLEXT_DFLT_L2PRFL_ACL(_i) (0x00393800 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2398 #define GL_ACLEXT_DFLT_L2PRFL_ACL_MAX_INDEX 2
2399 #define GL_ACLEXT_DFLT_L2PRFL_ACL_DFLT_PRFL_S 0
2400 #define GL_ACLEXT_DFLT_L2PRFL_ACL_DFLT_PRFL_M MAKEMASK(0xFFFF, 0)
2401 #define GL_ACLEXT_FLGS_L1SEL0_1(_i) (0x0021006C + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2402 #define GL_ACLEXT_FLGS_L1SEL0_1_MAX_INDEX 2
2403 #define GL_ACLEXT_FLGS_L1SEL0_1_FLS0_S 0
2404 #define GL_ACLEXT_FLGS_L1SEL0_1_FLS0_M MAKEMASK(0x1FF, 0)
2405 #define GL_ACLEXT_FLGS_L1SEL0_1_FLS1_S 16
2406 #define GL_ACLEXT_FLGS_L1SEL0_1_FLS1_M MAKEMASK(0x1FF, 16)
2407 #define GL_ACLEXT_FLGS_L1SEL2_3(_i) (0x00210078 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2408 #define GL_ACLEXT_FLGS_L1SEL2_3_MAX_INDEX 2
2409 #define GL_ACLEXT_FLGS_L1SEL2_3_FLS2_S 0
2410 #define GL_ACLEXT_FLGS_L1SEL2_3_FLS2_M MAKEMASK(0x1FF, 0)
2411 #define GL_ACLEXT_FLGS_L1SEL2_3_FLS3_S 16
2412 #define GL_ACLEXT_FLGS_L1SEL2_3_FLS3_M MAKEMASK(0x1FF, 16)
2413 #define GL_ACLEXT_FLGS_L1TBL(_i) (0x00210060 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2414 #define GL_ACLEXT_FLGS_L1TBL_MAX_INDEX 2
2415 #define GL_ACLEXT_FLGS_L1TBL_LSB_S 0
2416 #define GL_ACLEXT_FLGS_L1TBL_LSB_M MAKEMASK(0xFFFF, 0)
2417 #define GL_ACLEXT_FLGS_L1TBL_MSB_S 16
2418 #define GL_ACLEXT_FLGS_L1TBL_MSB_M MAKEMASK(0xFFFF, 16)
2419 #define GL_ACLEXT_FORCE_L1CDID(_i) (0x00210018 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2420 #define GL_ACLEXT_FORCE_L1CDID_MAX_INDEX 2
2421 #define GL_ACLEXT_FORCE_L1CDID_STATIC_CDID_S 0
2422 #define GL_ACLEXT_FORCE_L1CDID_STATIC_CDID_M MAKEMASK(0xF, 0)
2423 #define GL_ACLEXT_FORCE_L1CDID_STATIC_CDID_EN_S 31
2424 #define GL_ACLEXT_FORCE_L1CDID_STATIC_CDID_EN_M BIT(31)
2425 #define GL_ACLEXT_FORCE_PID(_i) (0x00210000 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2426 #define GL_ACLEXT_FORCE_PID_MAX_INDEX 2
2427 #define GL_ACLEXT_FORCE_PID_STATIC_PID_S 0
2428 #define GL_ACLEXT_FORCE_PID_STATIC_PID_M MAKEMASK(0xFFFF, 0)
2429 #define GL_ACLEXT_FORCE_PID_STATIC_PID_EN_S 31
2430 #define GL_ACLEXT_FORCE_PID_STATIC_PID_EN_M BIT(31)
2431 #define GL_ACLEXT_K2N_L2ADDR(_i) (0x00210144 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2432 #define GL_ACLEXT_K2N_L2ADDR_MAX_INDEX 2
2433 #define GL_ACLEXT_K2N_L2ADDR_LINE_IDX_S 0
2434 #define GL_ACLEXT_K2N_L2ADDR_LINE_IDX_M MAKEMASK(0x7F, 0)
2435 #define GL_ACLEXT_K2N_L2ADDR_AUTO_INC_S 31
2436 #define GL_ACLEXT_K2N_L2ADDR_AUTO_INC_M BIT(31)
2437 #define GL_ACLEXT_K2N_L2DATA(_i) (0x00210150 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2438 #define GL_ACLEXT_K2N_L2DATA_MAX_INDEX 2
2439 #define GL_ACLEXT_K2N_L2DATA_DATA0_S 0
2440 #define GL_ACLEXT_K2N_L2DATA_DATA0_M MAKEMASK(0xFF, 0)
2441 #define GL_ACLEXT_K2N_L2DATA_DATA1_S 8
2442 #define GL_ACLEXT_K2N_L2DATA_DATA1_M MAKEMASK(0xFF, 8)
2443 #define GL_ACLEXT_K2N_L2DATA_DATA2_S 16
2444 #define GL_ACLEXT_K2N_L2DATA_DATA2_M MAKEMASK(0xFF, 16)
2445 #define GL_ACLEXT_K2N_L2DATA_DATA3_S 24
2446 #define GL_ACLEXT_K2N_L2DATA_DATA3_M MAKEMASK(0xFF, 24)
2447 #define GL_ACLEXT_L2_PMASK0(_i) (0x002100FC + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2448 #define GL_ACLEXT_L2_PMASK0_MAX_INDEX 2
2449 #define GL_ACLEXT_L2_PMASK0_BITMASK_S 0
2450 #define GL_ACLEXT_L2_PMASK0_BITMASK_M MAKEMASK(0xFFFFFFFF, 0)
2451 #define GL_ACLEXT_L2_PMASK1(_i) (0x00210108 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2452 #define GL_ACLEXT_L2_PMASK1_MAX_INDEX 2
2453 #define GL_ACLEXT_L2_PMASK1_BITMASK_S 0
2454 #define GL_ACLEXT_L2_PMASK1_BITMASK_M MAKEMASK(0xFFFF, 0)
2455 #define GL_ACLEXT_L2_TMASK0(_i) (0x00210498 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2456 #define GL_ACLEXT_L2_TMASK0_MAX_INDEX 2
2457 #define GL_ACLEXT_L2_TMASK0_BITMASK_S 0
2458 #define GL_ACLEXT_L2_TMASK0_BITMASK_M MAKEMASK(0xFFFFFFFF, 0)
2459 #define GL_ACLEXT_L2_TMASK1(_i) (0x002104A4 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2460 #define GL_ACLEXT_L2_TMASK1_MAX_INDEX 2
2461 #define GL_ACLEXT_L2_TMASK1_BITMASK_S 0
2462 #define GL_ACLEXT_L2_TMASK1_BITMASK_M MAKEMASK(0xFF, 0)
2463 #define GL_ACLEXT_L2BMP0_3(_i) (0x002100A8 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2464 #define GL_ACLEXT_L2BMP0_3_MAX_INDEX 2
2465 #define GL_ACLEXT_L2BMP0_3_BMP0_S 0
2466 #define GL_ACLEXT_L2BMP0_3_BMP0_M MAKEMASK(0xFF, 0)
2467 #define GL_ACLEXT_L2BMP0_3_BMP1_S 8
2468 #define GL_ACLEXT_L2BMP0_3_BMP1_M MAKEMASK(0xFF, 8)
2469 #define GL_ACLEXT_L2BMP0_3_BMP2_S 16
2470 #define GL_ACLEXT_L2BMP0_3_BMP2_M MAKEMASK(0xFF, 16)
2471 #define GL_ACLEXT_L2BMP0_3_BMP3_S 24
2472 #define GL_ACLEXT_L2BMP0_3_BMP3_M MAKEMASK(0xFF, 24)
2473 #define GL_ACLEXT_L2BMP4_7(_i) (0x002100B4 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2474 #define GL_ACLEXT_L2BMP4_7_MAX_INDEX 2
2475 #define GL_ACLEXT_L2BMP4_7_BMP4_S 0
2476 #define GL_ACLEXT_L2BMP4_7_BMP4_M MAKEMASK(0xFF, 0)
2477 #define GL_ACLEXT_L2BMP4_7_BMP5_S 8
2478 #define GL_ACLEXT_L2BMP4_7_BMP5_M MAKEMASK(0xFF, 8)
2479 #define GL_ACLEXT_L2BMP4_7_BMP6_S 16
2480 #define GL_ACLEXT_L2BMP4_7_BMP6_M MAKEMASK(0xFF, 16)
2481 #define GL_ACLEXT_L2BMP4_7_BMP7_S 24
2482 #define GL_ACLEXT_L2BMP4_7_BMP7_M MAKEMASK(0xFF, 24)
2483 #define GL_ACLEXT_L2PRTMOD(_i) (0x0021009C + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2484 #define GL_ACLEXT_L2PRTMOD_MAX_INDEX 2
2485 #define GL_ACLEXT_L2PRTMOD_XLT1_S 0
2486 #define GL_ACLEXT_L2PRTMOD_XLT1_M MAKEMASK(0x3, 0)
2487 #define GL_ACLEXT_L2PRTMOD_XLT2_S 8
2488 #define GL_ACLEXT_L2PRTMOD_XLT2_M MAKEMASK(0x3, 8)
2489 #define GL_ACLEXT_N2N_L2ADDR(_i) (0x0021015C + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2490 #define GL_ACLEXT_N2N_L2ADDR_MAX_INDEX 2
2491 #define GL_ACLEXT_N2N_L2ADDR_LINE_IDX_S 0
2492 #define GL_ACLEXT_N2N_L2ADDR_LINE_IDX_M MAKEMASK(0x3F, 0)
2493 #define GL_ACLEXT_N2N_L2ADDR_AUTO_INC_S 31
2494 #define GL_ACLEXT_N2N_L2ADDR_AUTO_INC_M BIT(31)
2495 #define GL_ACLEXT_N2N_L2DATA(_i) (0x00210168 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2496 #define GL_ACLEXT_N2N_L2DATA_MAX_INDEX 2
2497 #define GL_ACLEXT_N2N_L2DATA_DATA0_S 0
2498 #define GL_ACLEXT_N2N_L2DATA_DATA0_M MAKEMASK(0xFF, 0)
2499 #define GL_ACLEXT_N2N_L2DATA_DATA1_S 8
2500 #define GL_ACLEXT_N2N_L2DATA_DATA1_M MAKEMASK(0xFF, 8)
2501 #define GL_ACLEXT_N2N_L2DATA_DATA2_S 16
2502 #define GL_ACLEXT_N2N_L2DATA_DATA2_M MAKEMASK(0xFF, 16)
2503 #define GL_ACLEXT_N2N_L2DATA_DATA3_S 24
2504 #define GL_ACLEXT_N2N_L2DATA_DATA3_M MAKEMASK(0xFF, 24)
2505 #define GL_ACLEXT_P2P_L1ADDR(_i) (0x00210024 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2506 #define GL_ACLEXT_P2P_L1ADDR_MAX_INDEX 2
2507 #define GL_ACLEXT_P2P_L1ADDR_LINE_IDX_S 0
2508 #define GL_ACLEXT_P2P_L1ADDR_LINE_IDX_M BIT(0)
2509 #define GL_ACLEXT_P2P_L1ADDR_AUTO_INC_S 31
2510 #define GL_ACLEXT_P2P_L1ADDR_AUTO_INC_M BIT(31)
2511 #define GL_ACLEXT_P2P_L1DATA(_i) (0x00210030 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2512 #define GL_ACLEXT_P2P_L1DATA_MAX_INDEX 2
2513 #define GL_ACLEXT_P2P_L1DATA_DATA_S 0
2514 #define GL_ACLEXT_P2P_L1DATA_DATA_M MAKEMASK(0xFFFFFFFF, 0)
2515 #define GL_ACLEXT_PID_L2GKTYPE(_i) (0x002100F0 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2516 #define GL_ACLEXT_PID_L2GKTYPE_MAX_INDEX 2
2517 #define GL_ACLEXT_PID_L2GKTYPE_PID_GKTYPE_S 0
2518 #define GL_ACLEXT_PID_L2GKTYPE_PID_GKTYPE_M MAKEMASK(0x3, 0)
2519 #define GL_ACLEXT_PLVL_SEL(_i) (0x0021000C + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2520 #define GL_ACLEXT_PLVL_SEL_MAX_INDEX 2
2521 #define GL_ACLEXT_PLVL_SEL_PLVL_SEL_S 0
2522 #define GL_ACLEXT_PLVL_SEL_PLVL_SEL_M BIT(0)
2523 #define GL_ACLEXT_TCAM_L2ADDR(_i) (0x00210114 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2524 #define GL_ACLEXT_TCAM_L2ADDR_MAX_INDEX 2
2525 #define GL_ACLEXT_TCAM_L2ADDR_LINE_IDX_S 0
2526 #define GL_ACLEXT_TCAM_L2ADDR_LINE_IDX_M MAKEMASK(0x3FF, 0)
2527 #define GL_ACLEXT_TCAM_L2ADDR_AUTO_INC_S 31
2528 #define GL_ACLEXT_TCAM_L2ADDR_AUTO_INC_M BIT(31)
2529 #define GL_ACLEXT_TCAM_L2DATALSB(_i) (0x00210120 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2530 #define GL_ACLEXT_TCAM_L2DATALSB_MAX_INDEX 2
2531 #define GL_ACLEXT_TCAM_L2DATALSB_DATALSB_S 0
2532 #define GL_ACLEXT_TCAM_L2DATALSB_DATALSB_M MAKEMASK(0xFFFFFFFF, 0)
2533 #define GL_ACLEXT_TCAM_L2DATAMSB(_i) (0x0021012C + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2534 #define GL_ACLEXT_TCAM_L2DATAMSB_MAX_INDEX 2
2535 #define GL_ACLEXT_TCAM_L2DATAMSB_DATAMSB_S 0
2536 #define GL_ACLEXT_TCAM_L2DATAMSB_DATAMSB_M MAKEMASK(0xFF, 0)
2537 #define GL_ACLEXT_XLT0_L1ADDR(_i) (0x0021003C + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2538 #define GL_ACLEXT_XLT0_L1ADDR_MAX_INDEX 2
2539 #define GL_ACLEXT_XLT0_L1ADDR_LINE_IDX_S 0
2540 #define GL_ACLEXT_XLT0_L1ADDR_LINE_IDX_M MAKEMASK(0xFF, 0)
2541 #define GL_ACLEXT_XLT0_L1ADDR_AUTO_INC_S 31
2542 #define GL_ACLEXT_XLT0_L1ADDR_AUTO_INC_M BIT(31)
2543 #define GL_ACLEXT_XLT0_L1DATA(_i) (0x00210048 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2544 #define GL_ACLEXT_XLT0_L1DATA_MAX_INDEX 2
2545 #define GL_ACLEXT_XLT0_L1DATA_DATA_S 0
2546 #define GL_ACLEXT_XLT0_L1DATA_DATA_M MAKEMASK(0xFFFFFFFF, 0)
2547 #define GL_ACLEXT_XLT1_L2ADDR(_i) (0x002100C0 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2548 #define GL_ACLEXT_XLT1_L2ADDR_MAX_INDEX 2
2549 #define GL_ACLEXT_XLT1_L2ADDR_LINE_IDX_S 0
2550 #define GL_ACLEXT_XLT1_L2ADDR_LINE_IDX_M MAKEMASK(0x7FF, 0)
2551 #define GL_ACLEXT_XLT1_L2ADDR_AUTO_INC_S 31
2552 #define GL_ACLEXT_XLT1_L2ADDR_AUTO_INC_M BIT(31)
2553 #define GL_ACLEXT_XLT1_L2DATA(_i) (0x002100CC + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2554 #define GL_ACLEXT_XLT1_L2DATA_MAX_INDEX 2
2555 #define GL_ACLEXT_XLT1_L2DATA_DATA_S 0
2556 #define GL_ACLEXT_XLT1_L2DATA_DATA_M MAKEMASK(0xFFFFFFFF, 0)
2557 #define GL_ACLEXT_XLT2_L2ADDR(_i) (0x002100D8 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2558 #define GL_ACLEXT_XLT2_L2ADDR_MAX_INDEX 2
2559 #define GL_ACLEXT_XLT2_L2ADDR_LINE_IDX_S 0
2560 #define GL_ACLEXT_XLT2_L2ADDR_LINE_IDX_M MAKEMASK(0x1FF, 0)
2561 #define GL_ACLEXT_XLT2_L2ADDR_AUTO_INC_S 31
2562 #define GL_ACLEXT_XLT2_L2ADDR_AUTO_INC_M BIT(31)
2563 #define GL_ACLEXT_XLT2_L2DATA(_i) (0x002100E4 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2564 #define GL_ACLEXT_XLT2_L2DATA_MAX_INDEX 2
2565 #define GL_ACLEXT_XLT2_L2DATA_DATA_S 0
2566 #define GL_ACLEXT_XLT2_L2DATA_DATA_M MAKEMASK(0xFFFFFFFF, 0)
2567 #define GL_PREEXT_CDMD_L1SEL(_i) (0x0020F054 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2568 #define GL_PREEXT_CDMD_L1SEL_MAX_INDEX 2
2569 #define GL_PREEXT_CDMD_L1SEL_RX_SEL_S 0
2570 #define GL_PREEXT_CDMD_L1SEL_RX_SEL_M MAKEMASK(0x1F, 0)
2571 #define GL_PREEXT_CDMD_L1SEL_TX_SEL_S 8
2572 #define GL_PREEXT_CDMD_L1SEL_TX_SEL_M MAKEMASK(0x1F, 8)
2573 #define GL_PREEXT_CDMD_L1SEL_AUX0_SEL_S 16
2574 #define GL_PREEXT_CDMD_L1SEL_AUX0_SEL_M MAKEMASK(0x1F, 16)
2575 #define GL_PREEXT_CDMD_L1SEL_AUX1_SEL_S 24
2576 #define GL_PREEXT_CDMD_L1SEL_AUX1_SEL_M MAKEMASK(0x1F, 24)
2577 #define GL_PREEXT_CDMD_L1SEL_BIDIR_ENA_S 30
2578 #define GL_PREEXT_CDMD_L1SEL_BIDIR_ENA_M MAKEMASK(0x3, 30)
2579 #define GL_PREEXT_CTLTBL_L2ADDR(_i) (0x0020F084 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2580 #define GL_PREEXT_CTLTBL_L2ADDR_MAX_INDEX 2
2581 #define GL_PREEXT_CTLTBL_L2ADDR_LINE_OFF_S 0
2582 #define GL_PREEXT_CTLTBL_L2ADDR_LINE_OFF_M MAKEMASK(0x7, 0)
2583 #define GL_PREEXT_CTLTBL_L2ADDR_LINE_IDX_S 8
2584 #define GL_PREEXT_CTLTBL_L2ADDR_LINE_IDX_M MAKEMASK(0x7, 8)
2585 #define GL_PREEXT_CTLTBL_L2ADDR_AUTO_INC_S 31
2586 #define GL_PREEXT_CTLTBL_L2ADDR_AUTO_INC_M BIT(31)
2587 #define GL_PREEXT_CTLTBL_L2DATA(_i) (0x0020F090 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2588 #define GL_PREEXT_CTLTBL_L2DATA_MAX_INDEX 2
2589 #define GL_PREEXT_CTLTBL_L2DATA_DATA_S 0
2590 #define GL_PREEXT_CTLTBL_L2DATA_DATA_M MAKEMASK(0xFFFFFFFF, 0)
2591 #define GL_PREEXT_DFLT_L2PRFL(_i) (0x0020F138 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2592 #define GL_PREEXT_DFLT_L2PRFL_MAX_INDEX 2
2593 #define GL_PREEXT_DFLT_L2PRFL_DFLT_PRFL_S 0
2594 #define GL_PREEXT_DFLT_L2PRFL_DFLT_PRFL_M MAKEMASK(0xFFFF, 0)
2595 #define GL_PREEXT_FLGS_L1SEL0_1(_i) (0x0020F06C + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2596 #define GL_PREEXT_FLGS_L1SEL0_1_MAX_INDEX 2
2597 #define GL_PREEXT_FLGS_L1SEL0_1_FLS0_S 0
2598 #define GL_PREEXT_FLGS_L1SEL0_1_FLS0_M MAKEMASK(0x1FF, 0)
2599 #define GL_PREEXT_FLGS_L1SEL0_1_FLS1_S 16
2600 #define GL_PREEXT_FLGS_L1SEL0_1_FLS1_M MAKEMASK(0x1FF, 16)
2601 #define GL_PREEXT_FLGS_L1SEL2_3(_i) (0x0020F078 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2602 #define GL_PREEXT_FLGS_L1SEL2_3_MAX_INDEX 2
2603 #define GL_PREEXT_FLGS_L1SEL2_3_FLS2_S 0
2604 #define GL_PREEXT_FLGS_L1SEL2_3_FLS2_M MAKEMASK(0x1FF, 0)
2605 #define GL_PREEXT_FLGS_L1SEL2_3_FLS3_S 16
2606 #define GL_PREEXT_FLGS_L1SEL2_3_FLS3_M MAKEMASK(0x1FF, 16)
2607 #define GL_PREEXT_FLGS_L1TBL(_i) (0x0020F060 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2608 #define GL_PREEXT_FLGS_L1TBL_MAX_INDEX 2
2609 #define GL_PREEXT_FLGS_L1TBL_LSB_S 0
2610 #define GL_PREEXT_FLGS_L1TBL_LSB_M MAKEMASK(0xFFFF, 0)
2611 #define GL_PREEXT_FLGS_L1TBL_MSB_S 16
2612 #define GL_PREEXT_FLGS_L1TBL_MSB_M MAKEMASK(0xFFFF, 16)
2613 #define GL_PREEXT_FORCE_L1CDID(_i) (0x0020F018 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2614 #define GL_PREEXT_FORCE_L1CDID_MAX_INDEX 2
2615 #define GL_PREEXT_FORCE_L1CDID_STATIC_CDID_S 0
2616 #define GL_PREEXT_FORCE_L1CDID_STATIC_CDID_M MAKEMASK(0xF, 0)
2617 #define GL_PREEXT_FORCE_L1CDID_STATIC_CDID_EN_S 31
2618 #define GL_PREEXT_FORCE_L1CDID_STATIC_CDID_EN_M BIT(31)
2619 #define GL_PREEXT_FORCE_PID(_i) (0x0020F000 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2620 #define GL_PREEXT_FORCE_PID_MAX_INDEX 2
2621 #define GL_PREEXT_FORCE_PID_STATIC_PID_S 0
2622 #define GL_PREEXT_FORCE_PID_STATIC_PID_M MAKEMASK(0xFFFF, 0)
2623 #define GL_PREEXT_FORCE_PID_STATIC_PID_EN_S 31
2624 #define GL_PREEXT_FORCE_PID_STATIC_PID_EN_M BIT(31)
2625 #define GL_PREEXT_K2N_L2ADDR(_i) (0x0020F144 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2626 #define GL_PREEXT_K2N_L2ADDR_MAX_INDEX 2
2627 #define GL_PREEXT_K2N_L2ADDR_LINE_IDX_S 0
2628 #define GL_PREEXT_K2N_L2ADDR_LINE_IDX_M MAKEMASK(0x7F, 0)
2629 #define GL_PREEXT_K2N_L2ADDR_AUTO_INC_S 31
2630 #define GL_PREEXT_K2N_L2ADDR_AUTO_INC_M BIT(31)
2631 #define GL_PREEXT_K2N_L2DATA(_i) (0x0020F150 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2632 #define GL_PREEXT_K2N_L2DATA_MAX_INDEX 2
2633 #define GL_PREEXT_K2N_L2DATA_DATA0_S 0
2634 #define GL_PREEXT_K2N_L2DATA_DATA0_M MAKEMASK(0xFF, 0)
2635 #define GL_PREEXT_K2N_L2DATA_DATA1_S 8
2636 #define GL_PREEXT_K2N_L2DATA_DATA1_M MAKEMASK(0xFF, 8)
2637 #define GL_PREEXT_K2N_L2DATA_DATA2_S 16
2638 #define GL_PREEXT_K2N_L2DATA_DATA2_M MAKEMASK(0xFF, 16)
2639 #define GL_PREEXT_K2N_L2DATA_DATA3_S 24
2640 #define GL_PREEXT_K2N_L2DATA_DATA3_M MAKEMASK(0xFF, 24)
2641 #define GL_PREEXT_L2_PMASK0(_i) (0x0020F0FC + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2642 #define GL_PREEXT_L2_PMASK0_MAX_INDEX 2
2643 #define GL_PREEXT_L2_PMASK0_BITMASK_S 0
2644 #define GL_PREEXT_L2_PMASK0_BITMASK_M MAKEMASK(0xFFFFFFFF, 0)
2645 #define GL_PREEXT_L2_PMASK1(_i) (0x0020F108 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2646 #define GL_PREEXT_L2_PMASK1_MAX_INDEX 2
2647 #define GL_PREEXT_L2_PMASK1_BITMASK_S 0
2648 #define GL_PREEXT_L2_PMASK1_BITMASK_M MAKEMASK(0xFFFF, 0)
2649 #define GL_PREEXT_L2_TMASK0(_i) (0x0020F498 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2650 #define GL_PREEXT_L2_TMASK0_MAX_INDEX 2
2651 #define GL_PREEXT_L2_TMASK0_BITMASK_S 0
2652 #define GL_PREEXT_L2_TMASK0_BITMASK_M MAKEMASK(0xFFFFFFFF, 0)
2653 #define GL_PREEXT_L2_TMASK1(_i) (0x0020F4A4 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2654 #define GL_PREEXT_L2_TMASK1_MAX_INDEX 2
2655 #define GL_PREEXT_L2_TMASK1_BITMASK_S 0
2656 #define GL_PREEXT_L2_TMASK1_BITMASK_M MAKEMASK(0xFF, 0)
2657 #define GL_PREEXT_L2BMP0_3(_i) (0x0020F0A8 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2658 #define GL_PREEXT_L2BMP0_3_MAX_INDEX 2
2659 #define GL_PREEXT_L2BMP0_3_BMP0_S 0
2660 #define GL_PREEXT_L2BMP0_3_BMP0_M MAKEMASK(0xFF, 0)
2661 #define GL_PREEXT_L2BMP0_3_BMP1_S 8
2662 #define GL_PREEXT_L2BMP0_3_BMP1_M MAKEMASK(0xFF, 8)
2663 #define GL_PREEXT_L2BMP0_3_BMP2_S 16
2664 #define GL_PREEXT_L2BMP0_3_BMP2_M MAKEMASK(0xFF, 16)
2665 #define GL_PREEXT_L2BMP0_3_BMP3_S 24
2666 #define GL_PREEXT_L2BMP0_3_BMP3_M MAKEMASK(0xFF, 24)
2667 #define GL_PREEXT_L2BMP4_7(_i) (0x0020F0B4 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2668 #define GL_PREEXT_L2BMP4_7_MAX_INDEX 2
2669 #define GL_PREEXT_L2BMP4_7_BMP4_S 0
2670 #define GL_PREEXT_L2BMP4_7_BMP4_M MAKEMASK(0xFF, 0)
2671 #define GL_PREEXT_L2BMP4_7_BMP5_S 8
2672 #define GL_PREEXT_L2BMP4_7_BMP5_M MAKEMASK(0xFF, 8)
2673 #define GL_PREEXT_L2BMP4_7_BMP6_S 16
2674 #define GL_PREEXT_L2BMP4_7_BMP6_M MAKEMASK(0xFF, 16)
2675 #define GL_PREEXT_L2BMP4_7_BMP7_S 24
2676 #define GL_PREEXT_L2BMP4_7_BMP7_M MAKEMASK(0xFF, 24)
2677 #define GL_PREEXT_L2PRTMOD(_i) (0x0020F09C + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2678 #define GL_PREEXT_L2PRTMOD_MAX_INDEX 2
2679 #define GL_PREEXT_L2PRTMOD_XLT1_S 0
2680 #define GL_PREEXT_L2PRTMOD_XLT1_M MAKEMASK(0x3, 0)
2681 #define GL_PREEXT_L2PRTMOD_XLT2_S 8
2682 #define GL_PREEXT_L2PRTMOD_XLT2_M MAKEMASK(0x3, 8)
2683 #define GL_PREEXT_N2N_L2ADDR(_i) (0x0020F15C + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2684 #define GL_PREEXT_N2N_L2ADDR_MAX_INDEX 2
2685 #define GL_PREEXT_N2N_L2ADDR_LINE_IDX_S 0
2686 #define GL_PREEXT_N2N_L2ADDR_LINE_IDX_M MAKEMASK(0x3F, 0)
2687 #define GL_PREEXT_N2N_L2ADDR_AUTO_INC_S 31
2688 #define GL_PREEXT_N2N_L2ADDR_AUTO_INC_M BIT(31)
2689 #define GL_PREEXT_N2N_L2DATA(_i) (0x0020F168 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2690 #define GL_PREEXT_N2N_L2DATA_MAX_INDEX 2
2691 #define GL_PREEXT_N2N_L2DATA_DATA0_S 0
2692 #define GL_PREEXT_N2N_L2DATA_DATA0_M MAKEMASK(0xFF, 0)
2693 #define GL_PREEXT_N2N_L2DATA_DATA1_S 8
2694 #define GL_PREEXT_N2N_L2DATA_DATA1_M MAKEMASK(0xFF, 8)
2695 #define GL_PREEXT_N2N_L2DATA_DATA2_S 16
2696 #define GL_PREEXT_N2N_L2DATA_DATA2_M MAKEMASK(0xFF, 16)
2697 #define GL_PREEXT_N2N_L2DATA_DATA3_S 24
2698 #define GL_PREEXT_N2N_L2DATA_DATA3_M MAKEMASK(0xFF, 24)
2699 #define GL_PREEXT_P2P_L1ADDR(_i) (0x0020F024 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2700 #define GL_PREEXT_P2P_L1ADDR_MAX_INDEX 2
2701 #define GL_PREEXT_P2P_L1ADDR_LINE_IDX_S 0
2702 #define GL_PREEXT_P2P_L1ADDR_LINE_IDX_M BIT(0)
2703 #define GL_PREEXT_P2P_L1ADDR_AUTO_INC_S 31
2704 #define GL_PREEXT_P2P_L1ADDR_AUTO_INC_M BIT(31)
2705 #define GL_PREEXT_P2P_L1DATA(_i) (0x0020F030 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2706 #define GL_PREEXT_P2P_L1DATA_MAX_INDEX 2
2707 #define GL_PREEXT_P2P_L1DATA_DATA_S 0
2708 #define GL_PREEXT_P2P_L1DATA_DATA_M MAKEMASK(0xFFFFFFFF, 0)
2709 #define GL_PREEXT_PID_L2GKTYPE(_i) (0x0020F0F0 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2710 #define GL_PREEXT_PID_L2GKTYPE_MAX_INDEX 2
2711 #define GL_PREEXT_PID_L2GKTYPE_PID_GKTYPE_S 0
2712 #define GL_PREEXT_PID_L2GKTYPE_PID_GKTYPE_M MAKEMASK(0x3, 0)
2713 #define GL_PREEXT_PLVL_SEL(_i) (0x0020F00C + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2714 #define GL_PREEXT_PLVL_SEL_MAX_INDEX 2
2715 #define GL_PREEXT_PLVL_SEL_PLVL_SEL_S 0
2716 #define GL_PREEXT_PLVL_SEL_PLVL_SEL_M BIT(0)
2717 #define GL_PREEXT_TCAM_L2ADDR(_i) (0x0020F114 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2718 #define GL_PREEXT_TCAM_L2ADDR_MAX_INDEX 2
2719 #define GL_PREEXT_TCAM_L2ADDR_LINE_IDX_S 0
2720 #define GL_PREEXT_TCAM_L2ADDR_LINE_IDX_M MAKEMASK(0x3FF, 0)
2721 #define GL_PREEXT_TCAM_L2ADDR_AUTO_INC_S 31
2722 #define GL_PREEXT_TCAM_L2ADDR_AUTO_INC_M BIT(31)
2723 #define GL_PREEXT_TCAM_L2DATALSB(_i) (0x0020F120 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2724 #define GL_PREEXT_TCAM_L2DATALSB_MAX_INDEX 2
2725 #define GL_PREEXT_TCAM_L2DATALSB_DATALSB_S 0
2726 #define GL_PREEXT_TCAM_L2DATALSB_DATALSB_M MAKEMASK(0xFFFFFFFF, 0)
2727 #define GL_PREEXT_TCAM_L2DATAMSB(_i) (0x0020F12C + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2728 #define GL_PREEXT_TCAM_L2DATAMSB_MAX_INDEX 2
2729 #define GL_PREEXT_TCAM_L2DATAMSB_DATAMSB_S 0
2730 #define GL_PREEXT_TCAM_L2DATAMSB_DATAMSB_M MAKEMASK(0xFF, 0)
2731 #define GL_PREEXT_XLT0_L1ADDR(_i) (0x0020F03C + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2732 #define GL_PREEXT_XLT0_L1ADDR_MAX_INDEX 2
2733 #define GL_PREEXT_XLT0_L1ADDR_LINE_IDX_S 0
2734 #define GL_PREEXT_XLT0_L1ADDR_LINE_IDX_M MAKEMASK(0xFF, 0)
2735 #define GL_PREEXT_XLT0_L1ADDR_AUTO_INC_S 31
2736 #define GL_PREEXT_XLT0_L1ADDR_AUTO_INC_M BIT(31)
2737 #define GL_PREEXT_XLT0_L1DATA(_i) (0x0020F048 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2738 #define GL_PREEXT_XLT0_L1DATA_MAX_INDEX 2
2739 #define GL_PREEXT_XLT0_L1DATA_DATA_S 0
2740 #define GL_PREEXT_XLT0_L1DATA_DATA_M MAKEMASK(0xFFFFFFFF, 0)
2741 #define GL_PREEXT_XLT1_L2ADDR(_i) (0x0020F0C0 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2742 #define GL_PREEXT_XLT1_L2ADDR_MAX_INDEX 2
2743 #define GL_PREEXT_XLT1_L2ADDR_LINE_IDX_S 0
2744 #define GL_PREEXT_XLT1_L2ADDR_LINE_IDX_M MAKEMASK(0x7FF, 0)
2745 #define GL_PREEXT_XLT1_L2ADDR_AUTO_INC_S 31
2746 #define GL_PREEXT_XLT1_L2ADDR_AUTO_INC_M BIT(31)
2747 #define GL_PREEXT_XLT1_L2DATA(_i) (0x0020F0CC + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2748 #define GL_PREEXT_XLT1_L2DATA_MAX_INDEX 2
2749 #define GL_PREEXT_XLT1_L2DATA_DATA_S 0
2750 #define GL_PREEXT_XLT1_L2DATA_DATA_M MAKEMASK(0xFFFFFFFF, 0)
2751 #define GL_PREEXT_XLT2_L2ADDR(_i) (0x0020F0D8 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2752 #define GL_PREEXT_XLT2_L2ADDR_MAX_INDEX 2
2753 #define GL_PREEXT_XLT2_L2ADDR_LINE_IDX_S 0
2754 #define GL_PREEXT_XLT2_L2ADDR_LINE_IDX_M MAKEMASK(0x1FF, 0)
2755 #define GL_PREEXT_XLT2_L2ADDR_AUTO_INC_S 31
2756 #define GL_PREEXT_XLT2_L2ADDR_AUTO_INC_M BIT(31)
2757 #define GL_PREEXT_XLT2_L2DATA(_i) (0x0020F0E4 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2758 #define GL_PREEXT_XLT2_L2DATA_MAX_INDEX 2
2759 #define GL_PREEXT_XLT2_L2DATA_DATA_S 0
2760 #define GL_PREEXT_XLT2_L2DATA_DATA_M MAKEMASK(0xFFFFFFFF, 0)
2761 #define GL_PSTEXT_CDMD_L1SEL(_i) (0x0020E054 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2762 #define GL_PSTEXT_CDMD_L1SEL_MAX_INDEX 2
2763 #define GL_PSTEXT_CDMD_L1SEL_RX_SEL_S 0
2764 #define GL_PSTEXT_CDMD_L1SEL_RX_SEL_M MAKEMASK(0x1F, 0)
2765 #define GL_PSTEXT_CDMD_L1SEL_TX_SEL_S 8
2766 #define GL_PSTEXT_CDMD_L1SEL_TX_SEL_M MAKEMASK(0x1F, 8)
2767 #define GL_PSTEXT_CDMD_L1SEL_AUX0_SEL_S 16
2768 #define GL_PSTEXT_CDMD_L1SEL_AUX0_SEL_M MAKEMASK(0x1F, 16)
2769 #define GL_PSTEXT_CDMD_L1SEL_AUX1_SEL_S 24
2770 #define GL_PSTEXT_CDMD_L1SEL_AUX1_SEL_M MAKEMASK(0x1F, 24)
2771 #define GL_PSTEXT_CDMD_L1SEL_BIDIR_ENA_S 30
2772 #define GL_PSTEXT_CDMD_L1SEL_BIDIR_ENA_M MAKEMASK(0x3, 30)
2773 #define GL_PSTEXT_CTLTBL_L2ADDR(_i) (0x0020E084 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2774 #define GL_PSTEXT_CTLTBL_L2ADDR_MAX_INDEX 2
2775 #define GL_PSTEXT_CTLTBL_L2ADDR_LINE_OFF_S 0
2776 #define GL_PSTEXT_CTLTBL_L2ADDR_LINE_OFF_M MAKEMASK(0x7, 0)
2777 #define GL_PSTEXT_CTLTBL_L2ADDR_LINE_IDX_S 8
2778 #define GL_PSTEXT_CTLTBL_L2ADDR_LINE_IDX_M MAKEMASK(0x7, 8)
2779 #define GL_PSTEXT_CTLTBL_L2ADDR_AUTO_INC_S 31
2780 #define GL_PSTEXT_CTLTBL_L2ADDR_AUTO_INC_M BIT(31)
2781 #define GL_PSTEXT_CTLTBL_L2DATA(_i) (0x0020E090 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2782 #define GL_PSTEXT_CTLTBL_L2DATA_MAX_INDEX 2
2783 #define GL_PSTEXT_CTLTBL_L2DATA_DATA_S 0
2784 #define GL_PSTEXT_CTLTBL_L2DATA_DATA_M MAKEMASK(0xFFFFFFFF, 0)
2785 #define GL_PSTEXT_DFLT_L2PRFL(_i) (0x0020E138 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2786 #define GL_PSTEXT_DFLT_L2PRFL_MAX_INDEX 2
2787 #define GL_PSTEXT_DFLT_L2PRFL_DFLT_PRFL_S 0
2788 #define GL_PSTEXT_DFLT_L2PRFL_DFLT_PRFL_M MAKEMASK(0xFFFF, 0)
2789 #define GL_PSTEXT_FL15_BMPLSB(_i) (0x0020E480 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2790 #define GL_PSTEXT_FL15_BMPLSB_MAX_INDEX 2
2791 #define GL_PSTEXT_FL15_BMPLSB_BMPLSB_S 0
2792 #define GL_PSTEXT_FL15_BMPLSB_BMPLSB_M MAKEMASK(0xFFFFFFFF, 0)
2793 #define GL_PSTEXT_FL15_BMPMSB(_i) (0x0020E48C + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2794 #define GL_PSTEXT_FL15_BMPMSB_MAX_INDEX 2
2795 #define GL_PSTEXT_FL15_BMPMSB_BMPMSB_S 0
2796 #define GL_PSTEXT_FL15_BMPMSB_BMPMSB_M MAKEMASK(0xFFFFFFFF, 0)
2797 #define GL_PSTEXT_FLGS_L1SEL0_1(_i) (0x0020E06C + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2798 #define GL_PSTEXT_FLGS_L1SEL0_1_MAX_INDEX 2
2799 #define GL_PSTEXT_FLGS_L1SEL0_1_FLS0_S 0
2800 #define GL_PSTEXT_FLGS_L1SEL0_1_FLS0_M MAKEMASK(0x1FF, 0)
2801 #define GL_PSTEXT_FLGS_L1SEL0_1_FLS1_S 16
2802 #define GL_PSTEXT_FLGS_L1SEL0_1_FLS1_M MAKEMASK(0x1FF, 16)
2803 #define GL_PSTEXT_FLGS_L1SEL2_3(_i) (0x0020E078 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2804 #define GL_PSTEXT_FLGS_L1SEL2_3_MAX_INDEX 2
2805 #define GL_PSTEXT_FLGS_L1SEL2_3_FLS2_S 0
2806 #define GL_PSTEXT_FLGS_L1SEL2_3_FLS2_M MAKEMASK(0x1FF, 0)
2807 #define GL_PSTEXT_FLGS_L1SEL2_3_FLS3_S 16
2808 #define GL_PSTEXT_FLGS_L1SEL2_3_FLS3_M MAKEMASK(0x1FF, 16)
2809 #define GL_PSTEXT_FLGS_L1TBL(_i) (0x0020E060 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2810 #define GL_PSTEXT_FLGS_L1TBL_MAX_INDEX 2
2811 #define GL_PSTEXT_FLGS_L1TBL_LSB_S 0
2812 #define GL_PSTEXT_FLGS_L1TBL_LSB_M MAKEMASK(0xFFFF, 0)
2813 #define GL_PSTEXT_FLGS_L1TBL_MSB_S 16
2814 #define GL_PSTEXT_FLGS_L1TBL_MSB_M MAKEMASK(0xFFFF, 16)
2815 #define GL_PSTEXT_FORCE_L1CDID(_i) (0x0020E018 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2816 #define GL_PSTEXT_FORCE_L1CDID_MAX_INDEX 2
2817 #define GL_PSTEXT_FORCE_L1CDID_STATIC_CDID_S 0
2818 #define GL_PSTEXT_FORCE_L1CDID_STATIC_CDID_M MAKEMASK(0xF, 0)
2819 #define GL_PSTEXT_FORCE_L1CDID_STATIC_CDID_EN_S 31
2820 #define GL_PSTEXT_FORCE_L1CDID_STATIC_CDID_EN_M BIT(31)
2821 #define GL_PSTEXT_FORCE_PID(_i) (0x0020E000 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2822 #define GL_PSTEXT_FORCE_PID_MAX_INDEX 2
2823 #define GL_PSTEXT_FORCE_PID_STATIC_PID_S 0
2824 #define GL_PSTEXT_FORCE_PID_STATIC_PID_M MAKEMASK(0xFFFF, 0)
2825 #define GL_PSTEXT_FORCE_PID_STATIC_PID_EN_S 31
2826 #define GL_PSTEXT_FORCE_PID_STATIC_PID_EN_M BIT(31)
2827 #define GL_PSTEXT_K2N_L2ADDR(_i) (0x0020E144 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2828 #define GL_PSTEXT_K2N_L2ADDR_MAX_INDEX 2
2829 #define GL_PSTEXT_K2N_L2ADDR_LINE_IDX_S 0
2830 #define GL_PSTEXT_K2N_L2ADDR_LINE_IDX_M MAKEMASK(0x7F, 0)
2831 #define GL_PSTEXT_K2N_L2ADDR_AUTO_INC_S 31
2832 #define GL_PSTEXT_K2N_L2ADDR_AUTO_INC_M BIT(31)
2833 #define GL_PSTEXT_K2N_L2DATA(_i) (0x0020E150 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2834 #define GL_PSTEXT_K2N_L2DATA_MAX_INDEX 2
2835 #define GL_PSTEXT_K2N_L2DATA_DATA0_S 0
2836 #define GL_PSTEXT_K2N_L2DATA_DATA0_M MAKEMASK(0xFF, 0)
2837 #define GL_PSTEXT_K2N_L2DATA_DATA1_S 8
2838 #define GL_PSTEXT_K2N_L2DATA_DATA1_M MAKEMASK(0xFF, 8)
2839 #define GL_PSTEXT_K2N_L2DATA_DATA2_S 16
2840 #define GL_PSTEXT_K2N_L2DATA_DATA2_M MAKEMASK(0xFF, 16)
2841 #define GL_PSTEXT_K2N_L2DATA_DATA3_S 24
2842 #define GL_PSTEXT_K2N_L2DATA_DATA3_M MAKEMASK(0xFF, 24)
2843 #define GL_PSTEXT_L2_PMASK0(_i) (0x0020E0FC + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2844 #define GL_PSTEXT_L2_PMASK0_MAX_INDEX 2
2845 #define GL_PSTEXT_L2_PMASK0_BITMASK_S 0
2846 #define GL_PSTEXT_L2_PMASK0_BITMASK_M MAKEMASK(0xFFFFFFFF, 0)
2847 #define GL_PSTEXT_L2_PMASK1(_i) (0x0020E108 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2848 #define GL_PSTEXT_L2_PMASK1_MAX_INDEX 2
2849 #define GL_PSTEXT_L2_PMASK1_BITMASK_S 0
2850 #define GL_PSTEXT_L2_PMASK1_BITMASK_M MAKEMASK(0xFFFF, 0)
2851 #define GL_PSTEXT_L2_TMASK0(_i) (0x0020E498 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2852 #define GL_PSTEXT_L2_TMASK0_MAX_INDEX 2
2853 #define GL_PSTEXT_L2_TMASK0_BITMASK_S 0
2854 #define GL_PSTEXT_L2_TMASK0_BITMASK_M MAKEMASK(0xFFFFFFFF, 0)
2855 #define GL_PSTEXT_L2_TMASK1(_i) (0x0020E4A4 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2856 #define GL_PSTEXT_L2_TMASK1_MAX_INDEX 2
2857 #define GL_PSTEXT_L2_TMASK1_BITMASK_S 0
2858 #define GL_PSTEXT_L2_TMASK1_BITMASK_M MAKEMASK(0xFF, 0)
2859 #define GL_PSTEXT_L2PRTMOD(_i) (0x0020E09C + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2860 #define GL_PSTEXT_L2PRTMOD_MAX_INDEX 2
2861 #define GL_PSTEXT_L2PRTMOD_XLT1_S 0
2862 #define GL_PSTEXT_L2PRTMOD_XLT1_M MAKEMASK(0x3, 0)
2863 #define GL_PSTEXT_L2PRTMOD_XLT2_S 8
2864 #define GL_PSTEXT_L2PRTMOD_XLT2_M MAKEMASK(0x3, 8)
2865 #define GL_PSTEXT_N2N_L2ADDR(_i) (0x0020E15C + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2866 #define GL_PSTEXT_N2N_L2ADDR_MAX_INDEX 2
2867 #define GL_PSTEXT_N2N_L2ADDR_LINE_IDX_S 0
2868 #define GL_PSTEXT_N2N_L2ADDR_LINE_IDX_M MAKEMASK(0x3F, 0)
2869 #define GL_PSTEXT_N2N_L2ADDR_AUTO_INC_S 31
2870 #define GL_PSTEXT_N2N_L2ADDR_AUTO_INC_M BIT(31)
2871 #define GL_PSTEXT_N2N_L2DATA(_i) (0x0020E168 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2872 #define GL_PSTEXT_N2N_L2DATA_MAX_INDEX 2
2873 #define GL_PSTEXT_N2N_L2DATA_DATA0_S 0
2874 #define GL_PSTEXT_N2N_L2DATA_DATA0_M MAKEMASK(0xFF, 0)
2875 #define GL_PSTEXT_N2N_L2DATA_DATA1_S 8
2876 #define GL_PSTEXT_N2N_L2DATA_DATA1_M MAKEMASK(0xFF, 8)
2877 #define GL_PSTEXT_N2N_L2DATA_DATA2_S 16
2878 #define GL_PSTEXT_N2N_L2DATA_DATA2_M MAKEMASK(0xFF, 16)
2879 #define GL_PSTEXT_N2N_L2DATA_DATA3_S 24
2880 #define GL_PSTEXT_N2N_L2DATA_DATA3_M MAKEMASK(0xFF, 24)
2881 #define GL_PSTEXT_P2P_L1ADDR(_i) (0x0020E024 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2882 #define GL_PSTEXT_P2P_L1ADDR_MAX_INDEX 2
2883 #define GL_PSTEXT_P2P_L1ADDR_LINE_IDX_S 0
2884 #define GL_PSTEXT_P2P_L1ADDR_LINE_IDX_M BIT(0)
2885 #define GL_PSTEXT_P2P_L1ADDR_AUTO_INC_S 31
2886 #define GL_PSTEXT_P2P_L1ADDR_AUTO_INC_M BIT(31)
2887 #define GL_PSTEXT_P2P_L1DATA(_i) (0x0020E030 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2888 #define GL_PSTEXT_P2P_L1DATA_MAX_INDEX 2
2889 #define GL_PSTEXT_P2P_L1DATA_DATA_S 0
2890 #define GL_PSTEXT_P2P_L1DATA_DATA_M MAKEMASK(0xFFFFFFFF, 0)
2891 #define GL_PSTEXT_PID_L2GKTYPE(_i) (0x0020E0F0 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2892 #define GL_PSTEXT_PID_L2GKTYPE_MAX_INDEX 2
2893 #define GL_PSTEXT_PID_L2GKTYPE_PID_GKTYPE_S 0
2894 #define GL_PSTEXT_PID_L2GKTYPE_PID_GKTYPE_M MAKEMASK(0x3, 0)
2895 #define GL_PSTEXT_PLVL_SEL(_i) (0x0020E00C + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2896 #define GL_PSTEXT_PLVL_SEL_MAX_INDEX 2
2897 #define GL_PSTEXT_PLVL_SEL_PLVL_SEL_S 0
2898 #define GL_PSTEXT_PLVL_SEL_PLVL_SEL_M BIT(0)
2899 #define GL_PSTEXT_PRFLM_CTRL(_i) (0x0020E474 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2900 #define GL_PSTEXT_PRFLM_CTRL_MAX_INDEX 2
2901 #define GL_PSTEXT_PRFLM_CTRL_PRFL_IDX_S 0
2902 #define GL_PSTEXT_PRFLM_CTRL_PRFL_IDX_M MAKEMASK(0xFF, 0)
2903 #define GL_PSTEXT_PRFLM_CTRL_RD_REQ_S 30
2904 #define GL_PSTEXT_PRFLM_CTRL_RD_REQ_M BIT(30)
2905 #define GL_PSTEXT_PRFLM_CTRL_WR_REQ_S 31
2906 #define GL_PSTEXT_PRFLM_CTRL_WR_REQ_M BIT(31)
2907 #define GL_PSTEXT_PRFLM_DATA_0(_i) (0x0020E174 + ((_i) * 4)) /* _i=0...63 */ /* Reset Source: CORER */
2908 #define GL_PSTEXT_PRFLM_DATA_0_MAX_INDEX 63
2909 #define GL_PSTEXT_PRFLM_DATA_0_PROT_S 0
2910 #define GL_PSTEXT_PRFLM_DATA_0_PROT_M MAKEMASK(0xFF, 0)
2911 #define GL_PSTEXT_PRFLM_DATA_0_OFF_S 16
2912 #define GL_PSTEXT_PRFLM_DATA_0_OFF_M MAKEMASK(0x1FF, 16)
2913 #define GL_PSTEXT_PRFLM_DATA_1(_i) (0x0020E274 + ((_i) * 4)) /* _i=0...63 */ /* Reset Source: CORER */
2914 #define GL_PSTEXT_PRFLM_DATA_1_MAX_INDEX 63
2915 #define GL_PSTEXT_PRFLM_DATA_1_PROT_S 0
2916 #define GL_PSTEXT_PRFLM_DATA_1_PROT_M MAKEMASK(0xFF, 0)
2917 #define GL_PSTEXT_PRFLM_DATA_1_OFF_S 16
2918 #define GL_PSTEXT_PRFLM_DATA_1_OFF_M MAKEMASK(0x1FF, 16)
2919 #define GL_PSTEXT_PRFLM_DATA_2(_i) (0x0020E374 + ((_i) * 4)) /* _i=0...63 */ /* Reset Source: CORER */
2920 #define GL_PSTEXT_PRFLM_DATA_2_MAX_INDEX 63
2921 #define GL_PSTEXT_PRFLM_DATA_2_PROT_S 0
2922 #define GL_PSTEXT_PRFLM_DATA_2_PROT_M MAKEMASK(0xFF, 0)
2923 #define GL_PSTEXT_PRFLM_DATA_2_OFF_S 16
2924 #define GL_PSTEXT_PRFLM_DATA_2_OFF_M MAKEMASK(0x1FF, 16)
2925 #define GL_PSTEXT_TCAM_L2ADDR(_i) (0x0020E114 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2926 #define GL_PSTEXT_TCAM_L2ADDR_MAX_INDEX 2
2927 #define GL_PSTEXT_TCAM_L2ADDR_LINE_IDX_S 0
2928 #define GL_PSTEXT_TCAM_L2ADDR_LINE_IDX_M MAKEMASK(0x3FF, 0)
2929 #define GL_PSTEXT_TCAM_L2ADDR_AUTO_INC_S 31
2930 #define GL_PSTEXT_TCAM_L2ADDR_AUTO_INC_M BIT(31)
2931 #define GL_PSTEXT_TCAM_L2DATALSB(_i) (0x0020E120 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2932 #define GL_PSTEXT_TCAM_L2DATALSB_MAX_INDEX 2
2933 #define GL_PSTEXT_TCAM_L2DATALSB_DATALSB_S 0
2934 #define GL_PSTEXT_TCAM_L2DATALSB_DATALSB_M MAKEMASK(0xFFFFFFFF, 0)
2935 #define GL_PSTEXT_TCAM_L2DATAMSB(_i) (0x0020E12C + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2936 #define GL_PSTEXT_TCAM_L2DATAMSB_MAX_INDEX 2
2937 #define GL_PSTEXT_TCAM_L2DATAMSB_DATAMSB_S 0
2938 #define GL_PSTEXT_TCAM_L2DATAMSB_DATAMSB_M MAKEMASK(0xFF, 0)
2939 #define GL_PSTEXT_XLT0_L1ADDR(_i) (0x0020E03C + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2940 #define GL_PSTEXT_XLT0_L1ADDR_MAX_INDEX 2
2941 #define GL_PSTEXT_XLT0_L1ADDR_LINE_IDX_S 0
2942 #define GL_PSTEXT_XLT0_L1ADDR_LINE_IDX_M MAKEMASK(0xFF, 0)
2943 #define GL_PSTEXT_XLT0_L1ADDR_AUTO_INC_S 31
2944 #define GL_PSTEXT_XLT0_L1ADDR_AUTO_INC_M BIT(31)
2945 #define GL_PSTEXT_XLT0_L1DATA(_i) (0x0020E048 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2946 #define GL_PSTEXT_XLT0_L1DATA_MAX_INDEX 2
2947 #define GL_PSTEXT_XLT0_L1DATA_DATA_S 0
2948 #define GL_PSTEXT_XLT0_L1DATA_DATA_M MAKEMASK(0xFFFFFFFF, 0)
2949 #define GL_PSTEXT_XLT1_L2ADDR(_i) (0x0020E0C0 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2950 #define GL_PSTEXT_XLT1_L2ADDR_MAX_INDEX 2
2951 #define GL_PSTEXT_XLT1_L2ADDR_LINE_IDX_S 0
2952 #define GL_PSTEXT_XLT1_L2ADDR_LINE_IDX_M MAKEMASK(0x7FF, 0)
2953 #define GL_PSTEXT_XLT1_L2ADDR_AUTO_INC_S 31
2954 #define GL_PSTEXT_XLT1_L2ADDR_AUTO_INC_M BIT(31)
2955 #define GL_PSTEXT_XLT1_L2DATA(_i) (0x0020E0CC + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2956 #define GL_PSTEXT_XLT1_L2DATA_MAX_INDEX 2
2957 #define GL_PSTEXT_XLT1_L2DATA_DATA_S 0
2958 #define GL_PSTEXT_XLT1_L2DATA_DATA_M MAKEMASK(0xFFFFFFFF, 0)
2959 #define GL_PSTEXT_XLT2_L2ADDR(_i) (0x0020E0D8 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2960 #define GL_PSTEXT_XLT2_L2ADDR_MAX_INDEX 2
2961 #define GL_PSTEXT_XLT2_L2ADDR_LINE_IDX_S 0
2962 #define GL_PSTEXT_XLT2_L2ADDR_LINE_IDX_M MAKEMASK(0x1FF, 0)
2963 #define GL_PSTEXT_XLT2_L2ADDR_AUTO_INC_S 31
2964 #define GL_PSTEXT_XLT2_L2ADDR_AUTO_INC_M BIT(31)
2965 #define GL_PSTEXT_XLT2_L2DATA(_i) (0x0020E0E4 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2966 #define GL_PSTEXT_XLT2_L2DATA_MAX_INDEX 2
2967 #define GL_PSTEXT_XLT2_L2DATA_DATA_S 0
2968 #define GL_PSTEXT_XLT2_L2DATA_DATA_M MAKEMASK(0xFFFFFFFF, 0)
2969 #define GLFLXP_PTYPE_TRANSLATION(_i) (0x0045C000 + ((_i) * 4)) /* _i=0...255 */ /* Reset Source: CORER */
2970 #define GLFLXP_PTYPE_TRANSLATION_MAX_INDEX 255
2971 #define GLFLXP_PTYPE_TRANSLATION_PTYPE_4N_S 0
2972 #define GLFLXP_PTYPE_TRANSLATION_PTYPE_4N_M MAKEMASK(0xFF, 0)
2973 #define GLFLXP_PTYPE_TRANSLATION_PTYPE_4N_1_S 8
2974 #define GLFLXP_PTYPE_TRANSLATION_PTYPE_4N_1_M MAKEMASK(0xFF, 8)
2975 #define GLFLXP_PTYPE_TRANSLATION_PTYPE_4N_2_S 16
2976 #define GLFLXP_PTYPE_TRANSLATION_PTYPE_4N_2_M MAKEMASK(0xFF, 16)
2977 #define GLFLXP_PTYPE_TRANSLATION_PTYPE_4N_3_S 24
2978 #define GLFLXP_PTYPE_TRANSLATION_PTYPE_4N_3_M MAKEMASK(0xFF, 24)
2979 #define GLFLXP_RX_CMD_LX_PROT_IDX(_i) (0x0045C400 + ((_i) * 4)) /* _i=0...255 */ /* Reset Source: CORER */
2980 #define GLFLXP_RX_CMD_LX_PROT_IDX_MAX_INDEX 255
2981 #define GLFLXP_RX_CMD_LX_PROT_IDX_INNER_CLOUD_OFFSET_INDEX_S 0
2982 #define GLFLXP_RX_CMD_LX_PROT_IDX_INNER_CLOUD_OFFSET_INDEX_M MAKEMASK(0x7, 0)
2983 #define GLFLXP_RX_CMD_LX_PROT_IDX_L4_OFFSET_INDEX_S 4
2984 #define GLFLXP_RX_CMD_LX_PROT_IDX_L4_OFFSET_INDEX_M MAKEMASK(0x7, 4)
2985 #define GLFLXP_RX_CMD_LX_PROT_IDX_PAYLOAD_OFFSET_INDEX_S 8
2986 #define GLFLXP_RX_CMD_LX_PROT_IDX_PAYLOAD_OFFSET_INDEX_M MAKEMASK(0x7, 8)
2987 #define GLFLXP_RX_CMD_LX_PROT_IDX_L3_PROTOCOL_S 12
2988 #define GLFLXP_RX_CMD_LX_PROT_IDX_L3_PROTOCOL_M MAKEMASK(0x3, 12)
2989 #define GLFLXP_RX_CMD_LX_PROT_IDX_L4_PROTOCOL_S 14
2990 #define GLFLXP_RX_CMD_LX_PROT_IDX_L4_PROTOCOL_M MAKEMASK(0x3, 14)
2991 #define GLFLXP_RX_CMD_PROTIDS(_i, _j) (0x0045A000 + ((_i) * 4 + (_j) * 1024)) /* _i=0...255, _j=0...5 */ /* Reset Source: CORER */
2992 #define GLFLXP_RX_CMD_PROTIDS_MAX_INDEX 255
2993 #define GLFLXP_RX_CMD_PROTIDS_PROTID_4N_S 0
2994 #define GLFLXP_RX_CMD_PROTIDS_PROTID_4N_M MAKEMASK(0xFF, 0)
2995 #define GLFLXP_RX_CMD_PROTIDS_PROTID_4N_1_S 8
2996 #define GLFLXP_RX_CMD_PROTIDS_PROTID_4N_1_M MAKEMASK(0xFF, 8)
2997 #define GLFLXP_RX_CMD_PROTIDS_PROTID_4N_2_S 16
2998 #define GLFLXP_RX_CMD_PROTIDS_PROTID_4N_2_M MAKEMASK(0xFF, 16)
2999 #define GLFLXP_RX_CMD_PROTIDS_PROTID_4N_3_S 24
3000 #define GLFLXP_RX_CMD_PROTIDS_PROTID_4N_3_M MAKEMASK(0xFF, 24)
3001 #define GLFLXP_RXDID_FLAGS(_i, _j) (0x0045D000 + ((_i) * 4 + (_j) * 256)) /* _i=0...63, _j=0...4 */ /* Reset Source: CORER */
3002 #define GLFLXP_RXDID_FLAGS_MAX_INDEX 63
3003 #define GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_S 0
3004 #define GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_M MAKEMASK(0x3F, 0)
3005 #define GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_1_S 8
3006 #define GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_1_M MAKEMASK(0x3F, 8)
3007 #define GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_2_S 16
3008 #define GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_2_M MAKEMASK(0x3F, 16)
3009 #define GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_3_S 24
3010 #define GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_3_M MAKEMASK(0x3F, 24)
3011 #define GLFLXP_RXDID_FLAGS1_OVERRIDE(_i) (0x0045D600 + ((_i) * 4)) /* _i=0...63 */ /* Reset Source: CORER */
3012 #define GLFLXP_RXDID_FLAGS1_OVERRIDE_MAX_INDEX 63
3013 #define GLFLXP_RXDID_FLAGS1_OVERRIDE_FLEXIFLAGS1_OVERRIDE_S 0
3014 #define GLFLXP_RXDID_FLAGS1_OVERRIDE_FLEXIFLAGS1_OVERRIDE_M MAKEMASK(0xF, 0)
3015 #define GLFLXP_RXDID_FLX_WRD_0(_i) (0x0045C800 + ((_i) * 4)) /* _i=0...63 */ /* Reset Source: CORER */
3016 #define GLFLXP_RXDID_FLX_WRD_0_MAX_INDEX 63
3017 #define GLFLXP_RXDID_FLX_WRD_0_PROT_MDID_S 0
3018 #define GLFLXP_RXDID_FLX_WRD_0_PROT_MDID_M MAKEMASK(0xFF, 0)
3019 #define GLFLXP_RXDID_FLX_WRD_0_EXTRACTION_OFFSET_S 8
3020 #define GLFLXP_RXDID_FLX_WRD_0_EXTRACTION_OFFSET_M MAKEMASK(0x3FF, 8)
3021 #define GLFLXP_RXDID_FLX_WRD_0_RXDID_OPCODE_S 30
3022 #define GLFLXP_RXDID_FLX_WRD_0_RXDID_OPCODE_M MAKEMASK(0x3, 30)
3023 #define GLFLXP_RXDID_FLX_WRD_1(_i) (0x0045C900 + ((_i) * 4)) /* _i=0...63 */ /* Reset Source: CORER */
3024 #define GLFLXP_RXDID_FLX_WRD_1_MAX_INDEX 63
3025 #define GLFLXP_RXDID_FLX_WRD_1_PROT_MDID_S 0
3026 #define GLFLXP_RXDID_FLX_WRD_1_PROT_MDID_M MAKEMASK(0xFF, 0)
3027 #define GLFLXP_RXDID_FLX_WRD_1_EXTRACTION_OFFSET_S 8
3028 #define GLFLXP_RXDID_FLX_WRD_1_EXTRACTION_OFFSET_M MAKEMASK(0x3FF, 8)
3029 #define GLFLXP_RXDID_FLX_WRD_1_RXDID_OPCODE_S 30
3030 #define GLFLXP_RXDID_FLX_WRD_1_RXDID_OPCODE_M MAKEMASK(0x3, 30)
3031 #define GLFLXP_RXDID_FLX_WRD_2(_i) (0x0045CA00 + ((_i) * 4)) /* _i=0...63 */ /* Reset Source: CORER */
3032 #define GLFLXP_RXDID_FLX_WRD_2_MAX_INDEX 63
3033 #define GLFLXP_RXDID_FLX_WRD_2_PROT_MDID_S 0
3034 #define GLFLXP_RXDID_FLX_WRD_2_PROT_MDID_M MAKEMASK(0xFF, 0)
3035 #define GLFLXP_RXDID_FLX_WRD_2_EXTRACTION_OFFSET_S 8
3036 #define GLFLXP_RXDID_FLX_WRD_2_EXTRACTION_OFFSET_M MAKEMASK(0x3FF, 8)
3037 #define GLFLXP_RXDID_FLX_WRD_2_RXDID_OPCODE_S 30
3038 #define GLFLXP_RXDID_FLX_WRD_2_RXDID_OPCODE_M MAKEMASK(0x3, 30)
3039 #define GLFLXP_RXDID_FLX_WRD_3(_i) (0x0045CB00 + ((_i) * 4)) /* _i=0...63 */ /* Reset Source: CORER */
3040 #define GLFLXP_RXDID_FLX_WRD_3_MAX_INDEX 63
3041 #define GLFLXP_RXDID_FLX_WRD_3_PROT_MDID_S 0
3042 #define GLFLXP_RXDID_FLX_WRD_3_PROT_MDID_M MAKEMASK(0xFF, 0)
3043 #define GLFLXP_RXDID_FLX_WRD_3_EXTRACTION_OFFSET_S 8
3044 #define GLFLXP_RXDID_FLX_WRD_3_EXTRACTION_OFFSET_M MAKEMASK(0x3FF, 8)
3045 #define GLFLXP_RXDID_FLX_WRD_3_RXDID_OPCODE_S 30
3046 #define GLFLXP_RXDID_FLX_WRD_3_RXDID_OPCODE_M MAKEMASK(0x3, 30)
3047 #define GLFLXP_RXDID_FLX_WRD_4(_i) (0x0045CC00 + ((_i) * 4)) /* _i=0...63 */ /* Reset Source: CORER */
3048 #define GLFLXP_RXDID_FLX_WRD_4_MAX_INDEX 63
3049 #define GLFLXP_RXDID_FLX_WRD_4_PROT_MDID_S 0
3050 #define GLFLXP_RXDID_FLX_WRD_4_PROT_MDID_M MAKEMASK(0xFF, 0)
3051 #define GLFLXP_RXDID_FLX_WRD_4_EXTRACTION_OFFSET_S 8
3052 #define GLFLXP_RXDID_FLX_WRD_4_EXTRACTION_OFFSET_M MAKEMASK(0x3FF, 8)
3053 #define GLFLXP_RXDID_FLX_WRD_4_RXDID_OPCODE_S 30
3054 #define GLFLXP_RXDID_FLX_WRD_4_RXDID_OPCODE_M MAKEMASK(0x3, 30)
3055 #define GLFLXP_RXDID_FLX_WRD_5(_i) (0x0045CD00 + ((_i) * 4)) /* _i=0...63 */ /* Reset Source: CORER */
3056 #define GLFLXP_RXDID_FLX_WRD_5_MAX_INDEX 63
3057 #define GLFLXP_RXDID_FLX_WRD_5_PROT_MDID_S 0
3058 #define GLFLXP_RXDID_FLX_WRD_5_PROT_MDID_M MAKEMASK(0xFF, 0)
3059 #define GLFLXP_RXDID_FLX_WRD_5_EXTRACTION_OFFSET_S 8
3060 #define GLFLXP_RXDID_FLX_WRD_5_EXTRACTION_OFFSET_M MAKEMASK(0x3FF, 8)
3061 #define GLFLXP_RXDID_FLX_WRD_5_RXDID_OPCODE_S 30
3062 #define GLFLXP_RXDID_FLX_WRD_5_RXDID_OPCODE_M MAKEMASK(0x3, 30)
3063 #define GLFLXP_TX_SCHED_CORRECT(_i, _j) (0x00458000 + ((_i) * 4 + (_j) * 256)) /* _i=0...63, _j=0...31 */ /* Reset Source: CORER */
3064 #define GLFLXP_TX_SCHED_CORRECT_MAX_INDEX 63
3065 #define GLFLXP_TX_SCHED_CORRECT_PROTD_ID_2N_S 0
3066 #define GLFLXP_TX_SCHED_CORRECT_PROTD_ID_2N_M MAKEMASK(0xFF, 0)
3067 #define GLFLXP_TX_SCHED_CORRECT_RECIPE_2N_S 8
3068 #define GLFLXP_TX_SCHED_CORRECT_RECIPE_2N_M MAKEMASK(0x1F, 8)
3069 #define GLFLXP_TX_SCHED_CORRECT_PROTD_ID_2N_1_S 16
3070 #define GLFLXP_TX_SCHED_CORRECT_PROTD_ID_2N_1_M MAKEMASK(0xFF, 16)
3071 #define GLFLXP_TX_SCHED_CORRECT_RECIPE_2N_1_S 24
3072 #define GLFLXP_TX_SCHED_CORRECT_RECIPE_2N_1_M MAKEMASK(0x1F, 24)
3073 #define QRXFLXP_CNTXT(_QRX) (0x00480000 + ((_QRX) * 4)) /* _i=0...2047 */ /* Reset Source: CORER */
3074 #define QRXFLXP_CNTXT_MAX_INDEX 2047
3075 #define QRXFLXP_CNTXT_RXDID_IDX_S 0
3076 #define QRXFLXP_CNTXT_RXDID_IDX_M MAKEMASK(0x3F, 0)
3077 #define QRXFLXP_CNTXT_RXDID_PRIO_S 8
3078 #define QRXFLXP_CNTXT_RXDID_PRIO_M MAKEMASK(0x7, 8)
3079 #define QRXFLXP_CNTXT_TS_S 11
3080 #define QRXFLXP_CNTXT_TS_M BIT(11)
3081 #define GL_FWSTS 0x00083048 /* Reset Source: POR */
3082 #define GL_FWSTS_FWS0B_S 0
3083 #define GL_FWSTS_FWS0B_M MAKEMASK(0xFF, 0)
3084 #define GL_FWSTS_FWROWD_S 8
3085 #define GL_FWSTS_FWROWD_M BIT(8)
3086 #define GL_FWSTS_FWRI_S 9
3087 #define GL_FWSTS_FWRI_M BIT(9)
3088 #define GL_FWSTS_FWS1B_S 16
3089 #define GL_FWSTS_FWS1B_M MAKEMASK(0xFF, 16)
3090 #define GL_TCVMLR_DRAIN_CNTR_CTL 0x000A21E0 /* Reset Source: CORER */
3091 #define GL_TCVMLR_DRAIN_CNTR_CTL_OP_S 0
3092 #define GL_TCVMLR_DRAIN_CNTR_CTL_OP_M BIT(0)
3093 #define GL_TCVMLR_DRAIN_CNTR_CTL_PORT_S 1
3094 #define GL_TCVMLR_DRAIN_CNTR_CTL_PORT_M MAKEMASK(0x7, 1)
3095 #define GL_TCVMLR_DRAIN_CNTR_CTL_VALUE_S 4
3096 #define GL_TCVMLR_DRAIN_CNTR_CTL_VALUE_M MAKEMASK(0x3FFF, 4)
3097 #define GL_TCVMLR_DRAIN_DONE_DEC 0x000A21A8 /* Reset Source: CORER */
3098 #define GL_TCVMLR_DRAIN_DONE_DEC_TARGET_S 0
3099 #define GL_TCVMLR_DRAIN_DONE_DEC_TARGET_M BIT(0)
3100 #define GL_TCVMLR_DRAIN_DONE_DEC_INDEX_S 1
3101 #define GL_TCVMLR_DRAIN_DONE_DEC_INDEX_M MAKEMASK(0x1F, 1)
3102 #define GL_TCVMLR_DRAIN_DONE_DEC_VALUE_S 6
3103 #define GL_TCVMLR_DRAIN_DONE_DEC_VALUE_M MAKEMASK(0xFF, 6)
3104 #define GL_TCVMLR_DRAIN_DONE_TCLAN(_i) (0x000A20A8 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
3105 #define GL_TCVMLR_DRAIN_DONE_TCLAN_MAX_INDEX 31
3106 #define GL_TCVMLR_DRAIN_DONE_TCLAN_COUNT_S 0
3107 #define GL_TCVMLR_DRAIN_DONE_TCLAN_COUNT_M MAKEMASK(0xFF, 0)
3108 #define GL_TCVMLR_DRAIN_DONE_TPB(_i) (0x000A2128 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
3109 #define GL_TCVMLR_DRAIN_DONE_TPB_MAX_INDEX 31
3110 #define GL_TCVMLR_DRAIN_DONE_TPB_COUNT_S 0
3111 #define GL_TCVMLR_DRAIN_DONE_TPB_COUNT_M MAKEMASK(0xFF, 0)
3112 #define GL_TCVMLR_DRAIN_MARKER 0x000A2008 /* Reset Source: CORER */
3113 #define GL_TCVMLR_DRAIN_MARKER_PORT_S 0
3114 #define GL_TCVMLR_DRAIN_MARKER_PORT_M MAKEMASK(0x7, 0)
3115 #define GL_TCVMLR_DRAIN_MARKER_TC_S 3
3116 #define GL_TCVMLR_DRAIN_MARKER_TC_M MAKEMASK(0x1F, 3)
3117 #define GL_TCVMLR_ERR_STAT 0x000A2024 /* Reset Source: CORER */
3118 #define GL_TCVMLR_ERR_STAT_ERROR_S 0
3119 #define GL_TCVMLR_ERR_STAT_ERROR_M BIT(0)
3120 #define GL_TCVMLR_ERR_STAT_FW_REQ_S 1
3121 #define GL_TCVMLR_ERR_STAT_FW_REQ_M BIT(1)
3122 #define GL_TCVMLR_ERR_STAT_STAT_S 2
3123 #define GL_TCVMLR_ERR_STAT_STAT_M MAKEMASK(0x7, 2)
3124 #define GL_TCVMLR_ERR_STAT_ENT_TYPE_S 5
3125 #define GL_TCVMLR_ERR_STAT_ENT_TYPE_M MAKEMASK(0x7, 5)
3126 #define GL_TCVMLR_ERR_STAT_ENT_ID_S 8
3127 #define GL_TCVMLR_ERR_STAT_ENT_ID_M MAKEMASK(0x3FFF, 8)
3128 #define GL_TCVMLR_QCFG 0x000A2010 /* Reset Source: CORER */
3129 #define GL_TCVMLR_QCFG_QID_S 0
3130 #define GL_TCVMLR_QCFG_QID_M MAKEMASK(0x3FFF, 0)
3131 #define GL_TCVMLR_QCFG_OP_S 14
3132 #define GL_TCVMLR_QCFG_OP_M BIT(14)
3133 #define GL_TCVMLR_QCFG_PORT_S 15
3134 #define GL_TCVMLR_QCFG_PORT_M MAKEMASK(0x7, 15)
3135 #define GL_TCVMLR_QCFG_TC_S 18
3136 #define GL_TCVMLR_QCFG_TC_M MAKEMASK(0x1F, 18)
3137 #define GL_TCVMLR_QCFG_RD 0x000A2014 /* Reset Source: CORER */
3138 #define GL_TCVMLR_QCFG_RD_QID_S 0
3139 #define GL_TCVMLR_QCFG_RD_QID_M MAKEMASK(0x3FFF, 0)
3140 #define GL_TCVMLR_QCFG_RD_PORT_S 14
3141 #define GL_TCVMLR_QCFG_RD_PORT_M MAKEMASK(0x7, 14)
3142 #define GL_TCVMLR_QCFG_RD_TC_S 17
3143 #define GL_TCVMLR_QCFG_RD_TC_M MAKEMASK(0x1F, 17)
3144 #define GL_TCVMLR_QCNTR 0x000A200C /* Reset Source: CORER */
3145 #define GL_TCVMLR_QCNTR_CNTR_S 0
3146 #define GL_TCVMLR_QCNTR_CNTR_M MAKEMASK(0x7FFF, 0)
3147 #define GL_TCVMLR_QCTL 0x000A2004 /* Reset Source: CORER */
3148 #define GL_TCVMLR_QCTL_QID_S 0
3149 #define GL_TCVMLR_QCTL_QID_M MAKEMASK(0x3FFF, 0)
3150 #define GL_TCVMLR_QCTL_OP_S 14
3151 #define GL_TCVMLR_QCTL_OP_M BIT(14)
3152 #define GL_TCVMLR_REQ_STAT 0x000A2018 /* Reset Source: CORER */
3153 #define GL_TCVMLR_REQ_STAT_ENT_TYPE_S 0
3154 #define GL_TCVMLR_REQ_STAT_ENT_TYPE_M MAKEMASK(0x7, 0)
3155 #define GL_TCVMLR_REQ_STAT_ENT_ID_S 3
3156 #define GL_TCVMLR_REQ_STAT_ENT_ID_M MAKEMASK(0x3FFF, 3)
3157 #define GL_TCVMLR_REQ_STAT_OP_S 17
3158 #define GL_TCVMLR_REQ_STAT_OP_M BIT(17)
3159 #define GL_TCVMLR_REQ_STAT_WRITE_STATUS_S 18
3160 #define GL_TCVMLR_REQ_STAT_WRITE_STATUS_M MAKEMASK(0x7, 18)
3161 #define GL_TCVMLR_STAT 0x000A201C /* Reset Source: CORER */
3162 #define GL_TCVMLR_STAT_ENT_TYPE_S 0
3163 #define GL_TCVMLR_STAT_ENT_TYPE_M MAKEMASK(0x7, 0)
3164 #define GL_TCVMLR_STAT_ENT_ID_S 3
3165 #define GL_TCVMLR_STAT_ENT_ID_M MAKEMASK(0x3FFF, 3)
3166 #define GL_TCVMLR_STAT_STATUS_S 17
3167 #define GL_TCVMLR_STAT_STATUS_M MAKEMASK(0x7, 17)
3168 #define GL_XLR_MARKER_TRIG_TCVMLR 0x000A2000 /* Reset Source: CORER */
3169 #define GL_XLR_MARKER_TRIG_TCVMLR_VM_VF_NUM_S 0
3170 #define GL_XLR_MARKER_TRIG_TCVMLR_VM_VF_NUM_M MAKEMASK(0x3FF, 0)
3171 #define GL_XLR_MARKER_TRIG_TCVMLR_VM_VF_TYPE_S 10
3172 #define GL_XLR_MARKER_TRIG_TCVMLR_VM_VF_TYPE_M MAKEMASK(0x3, 10)
3173 #define GL_XLR_MARKER_TRIG_TCVMLR_PF_NUM_S 12
3174 #define GL_XLR_MARKER_TRIG_TCVMLR_PF_NUM_M MAKEMASK(0x7, 12)
3175 #define GL_XLR_MARKER_TRIG_TCVMLR_PORT_NUM_S 16
3176 #define GL_XLR_MARKER_TRIG_TCVMLR_PORT_NUM_M MAKEMASK(0x7, 16)
3177 #define GL_XLR_MARKER_TRIG_VMLR 0x00093804 /* Reset Source: CORER */
3178 #define GL_XLR_MARKER_TRIG_VMLR_VM_VF_NUM_S 0
3179 #define GL_XLR_MARKER_TRIG_VMLR_VM_VF_NUM_M MAKEMASK(0x3FF, 0)
3180 #define GL_XLR_MARKER_TRIG_VMLR_VM_VF_TYPE_S 10
3181 #define GL_XLR_MARKER_TRIG_VMLR_VM_VF_TYPE_M MAKEMASK(0x3, 10)
3182 #define GL_XLR_MARKER_TRIG_VMLR_PF_NUM_S 12
3183 #define GL_XLR_MARKER_TRIG_VMLR_PF_NUM_M MAKEMASK(0x7, 12)
3184 #define GL_XLR_MARKER_TRIG_VMLR_PORT_NUM_S 16
3185 #define GL_XLR_MARKER_TRIG_VMLR_PORT_NUM_M MAKEMASK(0x7, 16)
3186 #define GLGEN_ANA_ABORT_PTYPE 0x0020C21C /* Reset Source: CORER */
3187 #define GLGEN_ANA_ABORT_PTYPE_ABORT_S 0
3188 #define GLGEN_ANA_ABORT_PTYPE_ABORT_M MAKEMASK(0x3FF, 0)
3189 #define GLGEN_ANA_ALU_ACCSS_OUT_OF_PKT 0x0020C208 /* Reset Source: CORER */
3190 #define GLGEN_ANA_ALU_ACCSS_OUT_OF_PKT_NPC_S 0
3191 #define GLGEN_ANA_ALU_ACCSS_OUT_OF_PKT_NPC_M MAKEMASK(0xFF, 0)
3192 #define GLGEN_ANA_CFG_CTRL 0x0020C104 /* Reset Source: CORER */
3193 #define GLGEN_ANA_CFG_CTRL_LINE_IDX_S 0
3194 #define GLGEN_ANA_CFG_CTRL_LINE_IDX_M MAKEMASK(0x3FFFF, 0)
3195 #define GLGEN_ANA_CFG_CTRL_TABLE_ID_S 18
3196 #define GLGEN_ANA_CFG_CTRL_TABLE_ID_M MAKEMASK(0xFF, 18)
3197 #define GLGEN_ANA_CFG_CTRL_RESRVED_S 26
3198 #define GLGEN_ANA_CFG_CTRL_RESRVED_M MAKEMASK(0x7, 26)
3199 #define GLGEN_ANA_CFG_CTRL_OPERATION_ID_S 29
3200 #define GLGEN_ANA_CFG_CTRL_OPERATION_ID_M MAKEMASK(0x7, 29)
3201 #define GLGEN_ANA_CFG_HTBL_LU_RESULT 0x0020C158 /* Reset Source: CORER */
3202 #define GLGEN_ANA_CFG_HTBL_LU_RESULT_HIT_S 0
3203 #define GLGEN_ANA_CFG_HTBL_LU_RESULT_HIT_M BIT(0)
3204 #define GLGEN_ANA_CFG_HTBL_LU_RESULT_PG_MEM_IDX_S 1
3205 #define GLGEN_ANA_CFG_HTBL_LU_RESULT_PG_MEM_IDX_M MAKEMASK(0x7, 1)
3206 #define GLGEN_ANA_CFG_HTBL_LU_RESULT_ADDR_S 4
3207 #define GLGEN_ANA_CFG_HTBL_LU_RESULT_ADDR_M MAKEMASK(0x1FF, 4)
3208 #define GLGEN_ANA_CFG_LU_KEY(_i) (0x0020C14C + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
3209 #define GLGEN_ANA_CFG_LU_KEY_MAX_INDEX 2
3210 #define GLGEN_ANA_CFG_LU_KEY_LU_KEY_S 0
3211 #define GLGEN_ANA_CFG_LU_KEY_LU_KEY_M MAKEMASK(0xFFFFFFFF, 0)
3212 #define GLGEN_ANA_CFG_RDDATA(_i) (0x0020C10C + ((_i) * 4)) /* _i=0...15 */ /* Reset Source: CORER */
3213 #define GLGEN_ANA_CFG_RDDATA_MAX_INDEX 15
3214 #define GLGEN_ANA_CFG_RDDATA_RD_DATA_S 0
3215 #define GLGEN_ANA_CFG_RDDATA_RD_DATA_M MAKEMASK(0xFFFFFFFF, 0)
3216 #define GLGEN_ANA_CFG_SPLBUF_LU_RESULT 0x0020C15C /* Reset Source: CORER */
3217 #define GLGEN_ANA_CFG_SPLBUF_LU_RESULT_HIT_S 0
3218 #define GLGEN_ANA_CFG_SPLBUF_LU_RESULT_HIT_M BIT(0)
3219 #define GLGEN_ANA_CFG_SPLBUF_LU_RESULT_RSV_S 1
3220 #define GLGEN_ANA_CFG_SPLBUF_LU_RESULT_RSV_M MAKEMASK(0x7, 1)
3221 #define GLGEN_ANA_CFG_SPLBUF_LU_RESULT_ADDR_S 4
3222 #define GLGEN_ANA_CFG_SPLBUF_LU_RESULT_ADDR_M MAKEMASK(0x1FF, 4)
3223 #define GLGEN_ANA_CFG_WRDATA 0x0020C108 /* Reset Source: CORER */
3224 #define GLGEN_ANA_CFG_WRDATA_WR_DATA_S 0
3225 #define GLGEN_ANA_CFG_WRDATA_WR_DATA_M MAKEMASK(0xFFFFFFFF, 0)
3226 #define GLGEN_ANA_DEF_PTYPE 0x0020C100 /* Reset Source: CORER */
3227 #define GLGEN_ANA_DEF_PTYPE_DEF_PTYPE_S 0
3228 #define GLGEN_ANA_DEF_PTYPE_DEF_PTYPE_M MAKEMASK(0x3FF, 0)
3229 #define GLGEN_ANA_ERR_CTRL 0x0020C220 /* Reset Source: CORER */
3230 #define GLGEN_ANA_ERR_CTRL_ERR_MASK_EN_S 0
3231 #define GLGEN_ANA_ERR_CTRL_ERR_MASK_EN_M MAKEMASK(0xFFFFFFFF, 0)
3232 #define GLGEN_ANA_FLAG_MAP(_i) (0x0020C000 + ((_i) * 4)) /* _i=0...63 */ /* Reset Source: CORER */
3233 #define GLGEN_ANA_FLAG_MAP_MAX_INDEX 63
3234 #define GLGEN_ANA_FLAG_MAP_FLAG_EN_S 0
3235 #define GLGEN_ANA_FLAG_MAP_FLAG_EN_M BIT(0)
3236 #define GLGEN_ANA_FLAG_MAP_EXT_FLAG_ID_S 1
3237 #define GLGEN_ANA_FLAG_MAP_EXT_FLAG_ID_M MAKEMASK(0x3F, 1)
3238 #define GLGEN_ANA_INV_NODE_PTYPE 0x0020C210 /* Reset Source: CORER */
3239 #define GLGEN_ANA_INV_NODE_PTYPE_INV_NODE_PTYPE_S 0
3240 #define GLGEN_ANA_INV_NODE_PTYPE_INV_NODE_PTYPE_M MAKEMASK(0x7FF, 0)
3241 #define GLGEN_ANA_INV_PTYPE_MARKER 0x0020C218 /* Reset Source: CORER */
3242 #define GLGEN_ANA_INV_PTYPE_MARKER_INV_PTYPE_MARKER_S 0
3243 #define GLGEN_ANA_INV_PTYPE_MARKER_INV_PTYPE_MARKER_M MAKEMASK(0x7F, 0)
3244 #define GLGEN_ANA_LAST_PROT_ID(_i) (0x0020C1E4 + ((_i) * 4)) /* _i=0...5 */ /* Reset Source: CORER */
3245 #define GLGEN_ANA_LAST_PROT_ID_MAX_INDEX 5
3246 #define GLGEN_ANA_LAST_PROT_ID_EN_S 0
3247 #define GLGEN_ANA_LAST_PROT_ID_EN_M BIT(0)
3248 #define GLGEN_ANA_LAST_PROT_ID_PROT_ID_S 1
3249 #define GLGEN_ANA_LAST_PROT_ID_PROT_ID_M MAKEMASK(0xFF, 1)
3250 #define GLGEN_ANA_NMPG_KEYMASK(_i) (0x0020C1D0 + ((_i) * 4)) /* _i=0...3 */ /* Reset Source: CORER */
3251 #define GLGEN_ANA_NMPG_KEYMASK_MAX_INDEX 3
3252 #define GLGEN_ANA_NMPG_KEYMASK_HASH_KEY_S 0
3253 #define GLGEN_ANA_NMPG_KEYMASK_HASH_KEY_M MAKEMASK(0xFFFFFFFF, 0)
3254 #define GLGEN_ANA_NMPG0_HASHKEY(_i) (0x0020C1B0 + ((_i) * 4)) /* _i=0...3 */ /* Reset Source: CORER */
3255 #define GLGEN_ANA_NMPG0_HASHKEY_MAX_INDEX 3
3256 #define GLGEN_ANA_NMPG0_HASHKEY_HASH_KEY_S 0
3257 #define GLGEN_ANA_NMPG0_HASHKEY_HASH_KEY_M MAKEMASK(0xFFFFFFFF, 0)
3258 #define GLGEN_ANA_NO_HIT_PG_NM_PG 0x0020C204 /* Reset Source: CORER */
3259 #define GLGEN_ANA_NO_HIT_PG_NM_PG_NPC_S 0
3260 #define GLGEN_ANA_NO_HIT_PG_NM_PG_NPC_M MAKEMASK(0xFF, 0)
3261 #define GLGEN_ANA_OUT_OF_PKT 0x0020C200 /* Reset Source: CORER */
3262 #define GLGEN_ANA_OUT_OF_PKT_NPC_S 0
3263 #define GLGEN_ANA_OUT_OF_PKT_NPC_M MAKEMASK(0xFF, 0)
3264 #define GLGEN_ANA_P2P(_i) (0x0020C160 + ((_i) * 4)) /* _i=0...15 */ /* Reset Source: CORER */
3265 #define GLGEN_ANA_P2P_MAX_INDEX 15
3266 #define GLGEN_ANA_P2P_TARGET_PROF_S 0
3267 #define GLGEN_ANA_P2P_TARGET_PROF_M MAKEMASK(0xF, 0)
3268 #define GLGEN_ANA_PG_KEYMASK(_i) (0x0020C1C0 + ((_i) * 4)) /* _i=0...3 */ /* Reset Source: CORER */
3269 #define GLGEN_ANA_PG_KEYMASK_MAX_INDEX 3
3270 #define GLGEN_ANA_PG_KEYMASK_HASH_KEY_S 0
3271 #define GLGEN_ANA_PG_KEYMASK_HASH_KEY_M MAKEMASK(0xFFFFFFFF, 0)
3272 #define GLGEN_ANA_PG0_HASHKEY(_i) (0x0020C1A0 + ((_i) * 4)) /* _i=0...3 */ /* Reset Source: CORER */
3273 #define GLGEN_ANA_PG0_HASHKEY_MAX_INDEX 3
3274 #define GLGEN_ANA_PG0_HASHKEY_HASH_KEY_S 0
3275 #define GLGEN_ANA_PG0_HASHKEY_HASH_KEY_M MAKEMASK(0xFFFFFFFF, 0)
3276 #define GLGEN_ANA_PROFIL_CTRL 0x0020C1FC /* Reset Source: CORER */
3277 #define GLGEN_ANA_PROFIL_CTRL_PROFILE_SELECT_MDID_S 0
3278 #define GLGEN_ANA_PROFIL_CTRL_PROFILE_SELECT_MDID_M MAKEMASK(0x1F, 0)
3279 #define GLGEN_ANA_PROFIL_CTRL_PROFILE_SELECT_MDSTART_S 5
3280 #define GLGEN_ANA_PROFIL_CTRL_PROFILE_SELECT_MDSTART_M MAKEMASK(0xF, 5)
3281 #define GLGEN_ANA_PROFIL_CTRL_PROFILE_SELECT_MD_LEN_S 9
3282 #define GLGEN_ANA_PROFIL_CTRL_PROFILE_SELECT_MD_LEN_M MAKEMASK(0x1F, 9)
3283 #define GLGEN_ANA_PROFIL_CTRL_NUM_CTRL_DOMAIN_S 14
3284 #define GLGEN_ANA_PROFIL_CTRL_NUM_CTRL_DOMAIN_M MAKEMASK(0x3, 14)
3285 #define GLGEN_ANA_PROFIL_CTRL_DEF_PROF_ID_S 16
3286 #define GLGEN_ANA_PROFIL_CTRL_DEF_PROF_ID_M MAKEMASK(0xF, 16)
3287 #define GLGEN_ANA_PROFIL_CTRL_SEL_DEF_PROF_ID_S 20
3288 #define GLGEN_ANA_PROFIL_CTRL_SEL_DEF_PROF_ID_M BIT(20)
3289 #define GLGEN_ANA_TX_ABORT_PTYPE 0x0020D21C /* Reset Source: CORER */
3290 #define GLGEN_ANA_TX_ABORT_PTYPE_ABORT_S 0
3291 #define GLGEN_ANA_TX_ABORT_PTYPE_ABORT_M MAKEMASK(0x3FF, 0)
3292 #define GLGEN_ANA_TX_ALU_ACCSS_OUT_OF_PKT 0x0020D208 /* Reset Source: CORER */
3293 #define GLGEN_ANA_TX_ALU_ACCSS_OUT_OF_PKT_NPC_S 0
3294 #define GLGEN_ANA_TX_ALU_ACCSS_OUT_OF_PKT_NPC_M MAKEMASK(0xFF, 0)
3295 #define GLGEN_ANA_TX_CFG_CTRL 0x0020D104 /* Reset Source: CORER */
3296 #define GLGEN_ANA_TX_CFG_CTRL_LINE_IDX_S 0
3297 #define GLGEN_ANA_TX_CFG_CTRL_LINE_IDX_M MAKEMASK(0x3FFFF, 0)
3298 #define GLGEN_ANA_TX_CFG_CTRL_TABLE_ID_S 18
3299 #define GLGEN_ANA_TX_CFG_CTRL_TABLE_ID_M MAKEMASK(0xFF, 18)
3300 #define GLGEN_ANA_TX_CFG_CTRL_RESRVED_S 26
3301 #define GLGEN_ANA_TX_CFG_CTRL_RESRVED_M MAKEMASK(0x7, 26)
3302 #define GLGEN_ANA_TX_CFG_CTRL_OPERATION_ID_S 29
3303 #define GLGEN_ANA_TX_CFG_CTRL_OPERATION_ID_M MAKEMASK(0x7, 29)
3304 #define GLGEN_ANA_TX_CFG_HTBL_LU_RESULT 0x0020D158 /* Reset Source: CORER */
3305 #define GLGEN_ANA_TX_CFG_HTBL_LU_RESULT_HIT_S 0
3306 #define GLGEN_ANA_TX_CFG_HTBL_LU_RESULT_HIT_M BIT(0)
3307 #define GLGEN_ANA_TX_CFG_HTBL_LU_RESULT_PG_MEM_IDX_S 1
3308 #define GLGEN_ANA_TX_CFG_HTBL_LU_RESULT_PG_MEM_IDX_M MAKEMASK(0x7, 1)
3309 #define GLGEN_ANA_TX_CFG_HTBL_LU_RESULT_ADDR_S 4
3310 #define GLGEN_ANA_TX_CFG_HTBL_LU_RESULT_ADDR_M MAKEMASK(0x1FF, 4)
3311 #define GLGEN_ANA_TX_CFG_LU_KEY(_i) (0x0020D14C + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
3312 #define GLGEN_ANA_TX_CFG_LU_KEY_MAX_INDEX 2
3313 #define GLGEN_ANA_TX_CFG_LU_KEY_LU_KEY_S 0
3314 #define GLGEN_ANA_TX_CFG_LU_KEY_LU_KEY_M MAKEMASK(0xFFFFFFFF, 0)
3315 #define GLGEN_ANA_TX_CFG_RDDATA(_i) (0x0020D10C + ((_i) * 4)) /* _i=0...15 */ /* Reset Source: CORER */
3316 #define GLGEN_ANA_TX_CFG_RDDATA_MAX_INDEX 15
3317 #define GLGEN_ANA_TX_CFG_RDDATA_RD_DATA_S 0
3318 #define GLGEN_ANA_TX_CFG_RDDATA_RD_DATA_M MAKEMASK(0xFFFFFFFF, 0)
3319 #define GLGEN_ANA_TX_CFG_SPLBUF_LU_RESULT 0x0020D15C /* Reset Source: CORER */
3320 #define GLGEN_ANA_TX_CFG_SPLBUF_LU_RESULT_HIT_S 0
3321 #define GLGEN_ANA_TX_CFG_SPLBUF_LU_RESULT_HIT_M BIT(0)
3322 #define GLGEN_ANA_TX_CFG_SPLBUF_LU_RESULT_RSV_S 1
3323 #define GLGEN_ANA_TX_CFG_SPLBUF_LU_RESULT_RSV_M MAKEMASK(0x7, 1)
3324 #define GLGEN_ANA_TX_CFG_SPLBUF_LU_RESULT_ADDR_S 4
3325 #define GLGEN_ANA_TX_CFG_SPLBUF_LU_RESULT_ADDR_M MAKEMASK(0x1FF, 4)
3326 #define GLGEN_ANA_TX_CFG_WRDATA 0x0020D108 /* Reset Source: CORER */
3327 #define GLGEN_ANA_TX_CFG_WRDATA_WR_DATA_S 0
3328 #define GLGEN_ANA_TX_CFG_WRDATA_WR_DATA_M MAKEMASK(0xFFFFFFFF, 0)
3329 #define GLGEN_ANA_TX_DEF_PTYPE 0x0020D100 /* Reset Source: CORER */
3330 #define GLGEN_ANA_TX_DEF_PTYPE_DEF_PTYPE_S 0
3331 #define GLGEN_ANA_TX_DEF_PTYPE_DEF_PTYPE_M MAKEMASK(0x3FF, 0)
3332 #define GLGEN_ANA_TX_DFD_PACE_OUT 0x0020D4CC /* Reset Source: CORER */
3333 #define GLGEN_ANA_TX_DFD_PACE_OUT_PUSH_S 0
3334 #define GLGEN_ANA_TX_DFD_PACE_OUT_PUSH_M BIT(0)
3335 #define GLGEN_ANA_TX_ERR_CTRL 0x0020D220 /* Reset Source: CORER */
3336 #define GLGEN_ANA_TX_ERR_CTRL_ERR_MASK_EN_S 0
3337 #define GLGEN_ANA_TX_ERR_CTRL_ERR_MASK_EN_M MAKEMASK(0xFFFFFFFF, 0)
3338 #define GLGEN_ANA_TX_FLAG_MAP(_i) (0x0020D000 + ((_i) * 4)) /* _i=0...63 */ /* Reset Source: CORER */
3339 #define GLGEN_ANA_TX_FLAG_MAP_MAX_INDEX 63
3340 #define GLGEN_ANA_TX_FLAG_MAP_FLAG_EN_S 0
3341 #define GLGEN_ANA_TX_FLAG_MAP_FLAG_EN_M BIT(0)
3342 #define GLGEN_ANA_TX_FLAG_MAP_EXT_FLAG_ID_S 1
3343 #define GLGEN_ANA_TX_FLAG_MAP_EXT_FLAG_ID_M MAKEMASK(0x3F, 1)
3344 #define GLGEN_ANA_TX_INV_NODE_PTYPE 0x0020D210 /* Reset Source: CORER */
3345 #define GLGEN_ANA_TX_INV_NODE_PTYPE_INV_NODE_PTYPE_S 0
3346 #define GLGEN_ANA_TX_INV_NODE_PTYPE_INV_NODE_PTYPE_M MAKEMASK(0x7FF, 0)
3347 #define GLGEN_ANA_TX_INV_PROT_ID 0x0020D214 /* Reset Source: CORER */
3348 #define GLGEN_ANA_TX_INV_PROT_ID_INV_PROT_ID_S 0
3349 #define GLGEN_ANA_TX_INV_PROT_ID_INV_PROT_ID_M MAKEMASK(0xFF, 0)
3350 #define GLGEN_ANA_TX_INV_PTYPE_MARKER 0x0020D218 /* Reset Source: CORER */
3351 #define GLGEN_ANA_TX_INV_PTYPE_MARKER_INV_PTYPE_MARKER_S 0
3352 #define GLGEN_ANA_TX_INV_PTYPE_MARKER_INV_PTYPE_MARKER_M MAKEMASK(0x7F, 0)
3353 #define GLGEN_ANA_TX_NMPG_KEYMASK(_i) (0x0020D1D0 + ((_i) * 4)) /* _i=0...3 */ /* Reset Source: CORER */
3354 #define GLGEN_ANA_TX_NMPG_KEYMASK_MAX_INDEX 3
3355 #define GLGEN_ANA_TX_NMPG_KEYMASK_HASH_KEY_S 0
3356 #define GLGEN_ANA_TX_NMPG_KEYMASK_HASH_KEY_M MAKEMASK(0xFFFFFFFF, 0)
3357 #define GLGEN_ANA_TX_NMPG0_HASHKEY(_i) (0x0020D1B0 + ((_i) * 4)) /* _i=0...3 */ /* Reset Source: CORER */
3358 #define GLGEN_ANA_TX_NMPG0_HASHKEY_MAX_INDEX 3
3359 #define GLGEN_ANA_TX_NMPG0_HASHKEY_HASH_KEY_S 0
3360 #define GLGEN_ANA_TX_NMPG0_HASHKEY_HASH_KEY_M MAKEMASK(0xFFFFFFFF, 0)
3361 #define GLGEN_ANA_TX_NO_HIT_PG_NM_PG 0x0020D204 /* Reset Source: CORER */
3362 #define GLGEN_ANA_TX_NO_HIT_PG_NM_PG_NPC_S 0
3363 #define GLGEN_ANA_TX_NO_HIT_PG_NM_PG_NPC_M MAKEMASK(0xFF, 0)
3364 #define GLGEN_ANA_TX_P2P(_i) (0x0020D160 + ((_i) * 4)) /* _i=0...15 */ /* Reset Source: CORER */
3365 #define GLGEN_ANA_TX_P2P_MAX_INDEX 15
3366 #define GLGEN_ANA_TX_P2P_TARGET_PROF_S 0
3367 #define GLGEN_ANA_TX_P2P_TARGET_PROF_M MAKEMASK(0xF, 0)
3368 #define GLGEN_ANA_TX_PG_KEYMASK(_i) (0x0020D1C0 + ((_i) * 4)) /* _i=0...3 */ /* Reset Source: CORER */
3369 #define GLGEN_ANA_TX_PG_KEYMASK_MAX_INDEX 3
3370 #define GLGEN_ANA_TX_PG_KEYMASK_HASH_KEY_S 0
3371 #define GLGEN_ANA_TX_PG_KEYMASK_HASH_KEY_M MAKEMASK(0xFFFFFFFF, 0)
3372 #define GLGEN_ANA_TX_PG0_HASHKEY(_i) (0x0020D1A0 + ((_i) * 4)) /* _i=0...3 */ /* Reset Source: CORER */
3373 #define GLGEN_ANA_TX_PG0_HASHKEY_MAX_INDEX 3
3374 #define GLGEN_ANA_TX_PG0_HASHKEY_HASH_KEY_S 0
3375 #define GLGEN_ANA_TX_PG0_HASHKEY_HASH_KEY_M MAKEMASK(0xFFFFFFFF, 0)
3376 #define GLGEN_ANA_TX_PROFIL_CTRL 0x0020D1FC /* Reset Source: CORER */
3377 #define GLGEN_ANA_TX_PROFIL_CTRL_PROFILE_SELECT_MDID_S 0
3378 #define GLGEN_ANA_TX_PROFIL_CTRL_PROFILE_SELECT_MDID_M MAKEMASK(0x1F, 0)
3379 #define GLGEN_ANA_TX_PROFIL_CTRL_PROFILE_SELECT_MDSTART_S 5
3380 #define GLGEN_ANA_TX_PROFIL_CTRL_PROFILE_SELECT_MDSTART_M MAKEMASK(0xF, 5)
3381 #define GLGEN_ANA_TX_PROFIL_CTRL_PROFILE_SELECT_MD_LEN_S 9
3382 #define GLGEN_ANA_TX_PROFIL_CTRL_PROFILE_SELECT_MD_LEN_M MAKEMASK(0x1F, 9)
3383 #define GLGEN_ANA_TX_PROFIL_CTRL_NUM_CTRL_DOMAIN_S 14
3384 #define GLGEN_ANA_TX_PROFIL_CTRL_NUM_CTRL_DOMAIN_M MAKEMASK(0x3, 14)
3385 #define GLGEN_ANA_TX_PROFIL_CTRL_DEF_PROF_ID_S 16
3386 #define GLGEN_ANA_TX_PROFIL_CTRL_DEF_PROF_ID_M MAKEMASK(0xF, 16)
3387 #define GLGEN_ANA_TX_PROFIL_CTRL_SEL_DEF_PROF_ID_S 20
3388 #define GLGEN_ANA_TX_PROFIL_CTRL_SEL_DEF_PROF_ID_M BIT(20)
3389 #define GLGEN_ASSERT_HLP 0x000B81E4 /* Reset Source: POR */
3390 #define GLGEN_ASSERT_HLP_CORE_ON_RST_S 0
3391 #define GLGEN_ASSERT_HLP_CORE_ON_RST_M BIT(0)
3392 #define GLGEN_ASSERT_HLP_FULL_ON_RST_S 1
3393 #define GLGEN_ASSERT_HLP_FULL_ON_RST_M BIT(1)
3394 #define GLGEN_CLKSTAT 0x000B8184 /* Reset Source: POR */
3395 #define GLGEN_CLKSTAT_U_CLK_SPEED_S 0
3396 #define GLGEN_CLKSTAT_U_CLK_SPEED_M MAKEMASK(0x7, 0)
3397 #define GLGEN_CLKSTAT_L_CLK_SPEED_S 3
3398 #define GLGEN_CLKSTAT_L_CLK_SPEED_M MAKEMASK(0x7, 3)
3399 #define GLGEN_CLKSTAT_PSM_CLK_SPEED_S 6
3400 #define GLGEN_CLKSTAT_PSM_CLK_SPEED_M MAKEMASK(0x7, 6)
3401 #define GLGEN_CLKSTAT_RXCTL_CLK_SPEED_S 9
3402 #define GLGEN_CLKSTAT_RXCTL_CLK_SPEED_M MAKEMASK(0x7, 9)
3403 #define GLGEN_CLKSTAT_UANA_CLK_SPEED_S 12
3404 #define GLGEN_CLKSTAT_UANA_CLK_SPEED_M MAKEMASK(0x7, 12)
3405 #define GLGEN_CLKSTAT_PE_CLK_SPEED_S 18
3406 #define GLGEN_CLKSTAT_PE_CLK_SPEED_M MAKEMASK(0x7, 18)
3407 #define GLGEN_CLKSTAT_SRC 0x000B826C /* Reset Source: POR */
3408 #define GLGEN_CLKSTAT_SRC_U_CLK_SRC_S 0
3409 #define GLGEN_CLKSTAT_SRC_U_CLK_SRC_M MAKEMASK(0x3, 0)
3410 #define GLGEN_CLKSTAT_SRC_L_CLK_SRC_S 2
3411 #define GLGEN_CLKSTAT_SRC_L_CLK_SRC_M MAKEMASK(0x3, 2)
3412 #define GLGEN_CLKSTAT_SRC_PSM_CLK_SRC_S 4
3413 #define GLGEN_CLKSTAT_SRC_PSM_CLK_SRC_M MAKEMASK(0x3, 4)
3414 #define GLGEN_CLKSTAT_SRC_RXCTL_CLK_SRC_S 6
3415 #define GLGEN_CLKSTAT_SRC_RXCTL_CLK_SRC_M MAKEMASK(0x3, 6)
3416 #define GLGEN_CLKSTAT_SRC_UANA_CLK_SRC_S 8
3417 #define GLGEN_CLKSTAT_SRC_UANA_CLK_SRC_M MAKEMASK(0xF, 8)
3418 #define GLGEN_ECC_ERR_INT_TOG_MASK_H 0x00093A00 /* Reset Source: CORER */
3419 #define GLGEN_ECC_ERR_INT_TOG_MASK_H_CLIENT_NUM_S 0
3420 #define GLGEN_ECC_ERR_INT_TOG_MASK_H_CLIENT_NUM_M MAKEMASK(0x7F, 0)
3421 #define GLGEN_ECC_ERR_INT_TOG_MASK_L 0x000939FC /* Reset Source: CORER */
3422 #define GLGEN_ECC_ERR_INT_TOG_MASK_L_CLIENT_NUM_S 0
3423 #define GLGEN_ECC_ERR_INT_TOG_MASK_L_CLIENT_NUM_M MAKEMASK(0xFFFFFFFF, 0)
3424 #define GLGEN_ECC_ERR_RST_MASK_H 0x000939F8 /* Reset Source: CORER */
3425 #define GLGEN_ECC_ERR_RST_MASK_H_CLIENT_NUM_S 0
3426 #define GLGEN_ECC_ERR_RST_MASK_H_CLIENT_NUM_M MAKEMASK(0x7F, 0)
3427 #define GLGEN_ECC_ERR_RST_MASK_L 0x000939F4 /* Reset Source: CORER */
3428 #define GLGEN_ECC_ERR_RST_MASK_L_CLIENT_NUM_S 0
3429 #define GLGEN_ECC_ERR_RST_MASK_L_CLIENT_NUM_M MAKEMASK(0xFFFFFFFF, 0)
3430 #define GLGEN_GPIO_CTL(_i) (0x000880C8 + ((_i) * 4)) /* _i=0...6 */ /* Reset Source: POR */
3431 #define GLGEN_GPIO_CTL_MAX_INDEX 6
3432 #define GLGEN_GPIO_CTL_IN_VALUE_S 0
3433 #define GLGEN_GPIO_CTL_IN_VALUE_M BIT(0)
3434 #define GLGEN_GPIO_CTL_IN_TRANSIT_S 1
3435 #define GLGEN_GPIO_CTL_IN_TRANSIT_M BIT(1)
3436 #define GLGEN_GPIO_CTL_OUT_VALUE_S 2
3437 #define GLGEN_GPIO_CTL_OUT_VALUE_M BIT(2)
3438 #define GLGEN_GPIO_CTL_NO_P_UP_S 3
3439 #define GLGEN_GPIO_CTL_NO_P_UP_M BIT(3)
3440 #define GLGEN_GPIO_CTL_PIN_DIR_S 4
3441 #define GLGEN_GPIO_CTL_PIN_DIR_M BIT(4)
3442 #define GLGEN_GPIO_CTL_TRI_CTL_S 5
3443 #define GLGEN_GPIO_CTL_TRI_CTL_M BIT(5)
3444 #define GLGEN_GPIO_CTL_PIN_FUNC_S 8
3445 #define GLGEN_GPIO_CTL_PIN_FUNC_M MAKEMASK(0xF, 8)
3446 #define GLGEN_GPIO_CTL_INT_MODE_S 12
3447 #define GLGEN_GPIO_CTL_INT_MODE_M MAKEMASK(0x3, 12)
3448 #define GLGEN_MARKER_COUNT 0x000939E8 /* Reset Source: CORER */
3449 #define GLGEN_MARKER_COUNT_MARKER_COUNT_S 0
3450 #define GLGEN_MARKER_COUNT_MARKER_COUNT_M MAKEMASK(0xFF, 0)
3451 #define GLGEN_MARKER_COUNT_MARKER_COUNT_EN_S 31
3452 #define GLGEN_MARKER_COUNT_MARKER_COUNT_EN_M BIT(31)
3453 #define GLGEN_RSTAT 0x000B8188 /* Reset Source: POR */
3454 #define GLGEN_RSTAT_DEVSTATE_S 0
3455 #define GLGEN_RSTAT_DEVSTATE_M MAKEMASK(0x3, 0)
3456 #define GLGEN_RSTAT_RESET_TYPE_S 2
3457 #define GLGEN_RSTAT_RESET_TYPE_M MAKEMASK(0x3, 2)
3458 #define GLGEN_RSTAT_CORERCNT_S 4
3459 #define GLGEN_RSTAT_CORERCNT_M MAKEMASK(0x3, 4)
3460 #define GLGEN_RSTAT_GLOBRCNT_S 6
3461 #define GLGEN_RSTAT_GLOBRCNT_M MAKEMASK(0x3, 6)
3462 #define GLGEN_RSTAT_EMPRCNT_S 8
3463 #define GLGEN_RSTAT_EMPRCNT_M MAKEMASK(0x3, 8)
3464 #define GLGEN_RSTAT_TIME_TO_RST_S 10
3465 #define GLGEN_RSTAT_TIME_TO_RST_M MAKEMASK(0x3F, 10)
3466 #define GLGEN_RSTAT_RTRIG_FLR_S 16
3467 #define GLGEN_RSTAT_RTRIG_FLR_M BIT(16)
3468 #define GLGEN_RSTAT_RTRIG_ECC_S 17
3469 #define GLGEN_RSTAT_RTRIG_ECC_M BIT(17)
3470 #define GLGEN_RSTAT_RTRIG_FW_AUX_S 18
3471 #define GLGEN_RSTAT_RTRIG_FW_AUX_M BIT(18)
3472 #define GLGEN_RSTCTL 0x000B8180 /* Reset Source: POR */
3473 #define GLGEN_RSTCTL_GRSTDEL_S 0
3474 #define GLGEN_RSTCTL_GRSTDEL_M MAKEMASK(0x3F, 0)
3475 #define GLGEN_RSTCTL_ECC_RST_ENA_S 8
3476 #define GLGEN_RSTCTL_ECC_RST_ENA_M BIT(8)
3477 #define GLGEN_RSTCTL_ECC_RT_EN_S 30
3478 #define GLGEN_RSTCTL_ECC_RT_EN_M BIT(30)
3479 #define GLGEN_RSTCTL_FLR_RT_EN_S 31
3480 #define GLGEN_RSTCTL_FLR_RT_EN_M BIT(31)
3481 #define GLGEN_RTRIG 0x000B8190 /* Reset Source: CORER */
3482 #define GLGEN_RTRIG_CORER_S 0
3483 #define GLGEN_RTRIG_CORER_M BIT(0)
3484 #define GLGEN_RTRIG_GLOBR_S 1
3485 #define GLGEN_RTRIG_GLOBR_M BIT(1)
3486 #define GLGEN_RTRIG_EMPFWR_S 2
3487 #define GLGEN_RTRIG_EMPFWR_M BIT(2)
3488 #define GLGEN_STAT 0x000B612C /* Reset Source: POR */
3489 #define GLGEN_STAT_RSVD4FW_S 0
3490 #define GLGEN_STAT_RSVD4FW_M MAKEMASK(0xFF, 0)
3491 #define GLGEN_VFLRSTAT(_i) (0x00093A04 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
3492 #define GLGEN_VFLRSTAT_MAX_INDEX 7
3493 #define GLGEN_VFLRSTAT_VFLRS_S 0
3494 #define GLGEN_VFLRSTAT_VFLRS_M MAKEMASK(0xFFFFFFFF, 0)
3495 #define GLGEN_XLR_MSK2HLP_RDY 0x000939F0 /* Reset Source: CORER */
3496 #define GLGEN_XLR_MSK2HLP_RDY_GLGEN_XLR_MSK2HLP_RDY_S 0
3497 #define GLGEN_XLR_MSK2HLP_RDY_GLGEN_XLR_MSK2HLP_RDY_M BIT(0)
3498 #define GLGEN_XLR_TRNS_WAIT_COUNT 0x000939EC /* Reset Source: CORER */
3499 #define GLGEN_XLR_TRNS_WAIT_COUNT_W_BTWN_TRNS_COUNT_S 0
3500 #define GLGEN_XLR_TRNS_WAIT_COUNT_W_BTWN_TRNS_COUNT_M MAKEMASK(0x1F, 0)
3501 #define GLGEN_XLR_TRNS_WAIT_COUNT_W_PEND_TRNS_COUNT_S 8
3502 #define GLGEN_XLR_TRNS_WAIT_COUNT_W_PEND_TRNS_COUNT_M MAKEMASK(0xFF, 8)
3503 #define GLVFGEN_TIMER 0x000B8214 /* Reset Source: POR */
3504 #define GLVFGEN_TIMER_GTIME_S 0
3505 #define GLVFGEN_TIMER_GTIME_M MAKEMASK(0xFFFFFFFF, 0)
3506 #define PFGEN_CTRL 0x00091000 /* Reset Source: CORER */
3507 #define PFGEN_CTRL_PFSWR_S 0
3508 #define PFGEN_CTRL_PFSWR_M BIT(0)
3509 #define PFGEN_DRUN 0x00091180 /* Reset Source: CORER */
3510 #define PFGEN_DRUN_DRVUNLD_S 0
3511 #define PFGEN_DRUN_DRVUNLD_M BIT(0)
3512 #define PFGEN_PFRSTAT 0x00091080 /* Reset Source: CORER */
3513 #define PFGEN_PFRSTAT_PFRD_S 0
3514 #define PFGEN_PFRSTAT_PFRD_M BIT(0)
3515 #define PFGEN_PORTNUM 0x001D2400 /* Reset Source: CORER */
3516 #define PFGEN_PORTNUM_PORT_NUM_S 0
3517 #define PFGEN_PORTNUM_PORT_NUM_M MAKEMASK(0x7, 0)
3518 #define PFGEN_STATE 0x00088000 /* Reset Source: CORER */
3519 #define PFGEN_STATE_PFPEEN_S 0
3520 #define PFGEN_STATE_PFPEEN_M BIT(0)
3521 #define PFGEN_STATE_RSVD_S 1
3522 #define PFGEN_STATE_RSVD_M BIT(1)
3523 #define PFGEN_STATE_PFLINKEN_S 2
3524 #define PFGEN_STATE_PFLINKEN_M BIT(2)
3525 #define PFGEN_STATE_PFSCEN_S 3
3526 #define PFGEN_STATE_PFSCEN_M BIT(3)
3527 #define PRT_TCVMLR_DRAIN_CNTR 0x000A21C0 /* Reset Source: CORER */
3528 #define PRT_TCVMLR_DRAIN_CNTR_CNTR_S 0
3529 #define PRT_TCVMLR_DRAIN_CNTR_CNTR_M MAKEMASK(0x3FFF, 0)
3530 #define PRTGEN_CNF 0x000B8120 /* Reset Source: POR */
3531 #define PRTGEN_CNF_PORT_DIS_S 0
3532 #define PRTGEN_CNF_PORT_DIS_M BIT(0)
3533 #define PRTGEN_CNF_ALLOW_PORT_DIS_S 1
3534 #define PRTGEN_CNF_ALLOW_PORT_DIS_M BIT(1)
3535 #define PRTGEN_CNF_EMP_PORT_DIS_S 2
3536 #define PRTGEN_CNF_EMP_PORT_DIS_M BIT(2)
3537 #define PRTGEN_CNF2 0x000B8160 /* Reset Source: POR */
3538 #define PRTGEN_CNF2_ACTIVATE_PORT_LINK_S 0
3539 #define PRTGEN_CNF2_ACTIVATE_PORT_LINK_M BIT(0)
3540 #define PRTGEN_CNF3 0x000B8280 /* Reset Source: POR */
3541 #define PRTGEN_CNF3_PORT_STAGERING_EN_S 0
3542 #define PRTGEN_CNF3_PORT_STAGERING_EN_M BIT(0)
3543 #define PRTGEN_STATUS 0x000B8100 /* Reset Source: POR */
3544 #define PRTGEN_STATUS_PORT_VALID_S 0
3545 #define PRTGEN_STATUS_PORT_VALID_M BIT(0)
3546 #define PRTGEN_STATUS_PORT_ACTIVE_S 1
3547 #define PRTGEN_STATUS_PORT_ACTIVE_M BIT(1)
3548 #define VFGEN_RSTAT(_VF) (0x00074000 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: VFR */
3549 #define VFGEN_RSTAT_MAX_INDEX 255
3550 #define VFGEN_RSTAT_VFR_STATE_S 0
3551 #define VFGEN_RSTAT_VFR_STATE_M MAKEMASK(0x3, 0)
3552 #define VPGEN_VFRSTAT(_VF) (0x00090800 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: CORER */
3553 #define VPGEN_VFRSTAT_MAX_INDEX 255
3554 #define VPGEN_VFRSTAT_VFRD_S 0
3555 #define VPGEN_VFRSTAT_VFRD_M BIT(0)
3556 #define VPGEN_VFRTRIG(_VF) (0x00090000 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: CORER */
3557 #define VPGEN_VFRTRIG_MAX_INDEX 255
3558 #define VPGEN_VFRTRIG_VFSWR_S 0
3559 #define VPGEN_VFRTRIG_VFSWR_M BIT(0)
3560 #define VSIGEN_RSTAT(_VSI) (0x00092800 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: CORER */
3561 #define VSIGEN_RSTAT_MAX_INDEX 767
3562 #define VSIGEN_RSTAT_VMRD_S 0
3563 #define VSIGEN_RSTAT_VMRD_M BIT(0)
3564 #define VSIGEN_RTRIG(_VSI) (0x00091800 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: CORER */
3565 #define VSIGEN_RTRIG_MAX_INDEX 767
3566 #define VSIGEN_RTRIG_VMSWR_S 0
3567 #define VSIGEN_RTRIG_VMSWR_M BIT(0)
3568 #define GLHMC_APBVTINUSEBASE(_i) (0x00524A00 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
3569 #define GLHMC_APBVTINUSEBASE_MAX_INDEX 7
3570 #define GLHMC_APBVTINUSEBASE_FPMAPBINUSEBASE_S 0
3571 #define GLHMC_APBVTINUSEBASE_FPMAPBINUSEBASE_M MAKEMASK(0xFFFFFF, 0)
3572 #define GLHMC_CEQPART(_i) (0x005031C0 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
3573 #define GLHMC_CEQPART_MAX_INDEX 7
3574 #define GLHMC_CEQPART_PMCEQBASE_S 0
3575 #define GLHMC_CEQPART_PMCEQBASE_M MAKEMASK(0x3FF, 0)
3576 #define GLHMC_CEQPART_PMCEQSIZE_S 16
3577 #define GLHMC_CEQPART_PMCEQSIZE_M MAKEMASK(0x3FF, 16)
3578 #define GLHMC_DBCQMAX 0x005220F0 /* Reset Source: CORER */
3579 #define GLHMC_DBCQMAX_GLHMC_DBCQMAX_S 0
3580 #define GLHMC_DBCQMAX_GLHMC_DBCQMAX_M MAKEMASK(0xFFFFF, 0)
3581 #define GLHMC_DBCQPART(_i) (0x00503180 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
3582 #define GLHMC_DBCQPART_MAX_INDEX 7
3583 #define GLHMC_DBCQPART_PMDBCQBASE_S 0
3584 #define GLHMC_DBCQPART_PMDBCQBASE_M MAKEMASK(0x3FFF, 0)
3585 #define GLHMC_DBCQPART_PMDBCQSIZE_S 16
3586 #define GLHMC_DBCQPART_PMDBCQSIZE_M MAKEMASK(0x7FFF, 16)
3587 #define GLHMC_DBQPMAX 0x005220EC /* Reset Source: CORER */
3588 #define GLHMC_DBQPMAX_GLHMC_DBQPMAX_S 0
3589 #define GLHMC_DBQPMAX_GLHMC_DBQPMAX_M MAKEMASK(0x7FFFF, 0)
3590 #define GLHMC_DBQPPART(_i) (0x005044C0 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
3591 #define GLHMC_DBQPPART_MAX_INDEX 7
3592 #define GLHMC_DBQPPART_PMDBQPBASE_S 0
3593 #define GLHMC_DBQPPART_PMDBQPBASE_M MAKEMASK(0x3FFF, 0)
3594 #define GLHMC_DBQPPART_PMDBQPSIZE_S 16
3595 #define GLHMC_DBQPPART_PMDBQPSIZE_M MAKEMASK(0x7FFF, 16)
3596 #define GLHMC_FSIAVBASE(_i) (0x00525600 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
3597 #define GLHMC_FSIAVBASE_MAX_INDEX 7
3598 #define GLHMC_FSIAVBASE_FPMFSIAVBASE_S 0
3599 #define GLHMC_FSIAVBASE_FPMFSIAVBASE_M MAKEMASK(0xFFFFFF, 0)
3600 #define GLHMC_FSIAVCNT(_i) (0x00525700 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
3601 #define GLHMC_FSIAVCNT_MAX_INDEX 7
3602 #define GLHMC_FSIAVCNT_FPMFSIAVCNT_S 0
3603 #define GLHMC_FSIAVCNT_FPMFSIAVCNT_M MAKEMASK(0x1FFFFFFF, 0)
3604 #define GLHMC_FSIAVMAX 0x00522068 /* Reset Source: CORER */
3605 #define GLHMC_FSIAVMAX_PMFSIAVMAX_S 0
3606 #define GLHMC_FSIAVMAX_PMFSIAVMAX_M MAKEMASK(0x3FFFF, 0)
3607 #define GLHMC_FSIAVOBJSZ 0x00522064 /* Reset Source: CORER */
3608 #define GLHMC_FSIAVOBJSZ_PMFSIAVOBJSZ_S 0
3609 #define GLHMC_FSIAVOBJSZ_PMFSIAVOBJSZ_M MAKEMASK(0xF, 0)
3610 #define GLHMC_FSIMCBASE(_i) (0x00526000 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
3611 #define GLHMC_FSIMCBASE_MAX_INDEX 7
3612 #define GLHMC_FSIMCBASE_FPMFSIMCBASE_S 0
3613 #define GLHMC_FSIMCBASE_FPMFSIMCBASE_M MAKEMASK(0xFFFFFF, 0)
3614 #define GLHMC_FSIMCCNT(_i) (0x00526100 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
3615 #define GLHMC_FSIMCCNT_MAX_INDEX 7
3616 #define GLHMC_FSIMCCNT_FPMFSIMCSZ_S 0
3617 #define GLHMC_FSIMCCNT_FPMFSIMCSZ_M MAKEMASK(0x1FFFFFFF, 0)
3618 #define GLHMC_FSIMCMAX 0x00522060 /* Reset Source: CORER */
3619 #define GLHMC_FSIMCMAX_PMFSIMCMAX_S 0
3620 #define GLHMC_FSIMCMAX_PMFSIMCMAX_M MAKEMASK(0x3FFF, 0)
3621 #define GLHMC_FSIMCOBJSZ 0x0052205C /* Reset Source: CORER */
3622 #define GLHMC_FSIMCOBJSZ_PMFSIMCOBJSZ_S 0
3623 #define GLHMC_FSIMCOBJSZ_PMFSIMCOBJSZ_M MAKEMASK(0xF, 0)
3624 #define GLHMC_FWPDINV 0x0052207C /* Reset Source: CORER */
3625 #define GLHMC_FWPDINV_PMSDIDX_S 0
3626 #define GLHMC_FWPDINV_PMSDIDX_M MAKEMASK(0xFFF, 0)
3627 #define GLHMC_FWPDINV_PMSDPARTSEL_S 15
3628 #define GLHMC_FWPDINV_PMSDPARTSEL_M BIT(15)
3629 #define GLHMC_FWPDINV_PMPDIDX_S 16
3630 #define GLHMC_FWPDINV_PMPDIDX_M MAKEMASK(0x1FF, 16)
3631 #define GLHMC_FWPDINV_FPMAT 0x0010207C /* Reset Source: CORER */
3632 #define GLHMC_FWPDINV_FPMAT_PMSDIDX_S 0
3633 #define GLHMC_FWPDINV_FPMAT_PMSDIDX_M MAKEMASK(0xFFF, 0)
3634 #define GLHMC_FWPDINV_FPMAT_PMSDPARTSEL_S 15
3635 #define GLHMC_FWPDINV_FPMAT_PMSDPARTSEL_M BIT(15)
3636 #define GLHMC_FWPDINV_FPMAT_PMPDIDX_S 16
3637 #define GLHMC_FWPDINV_FPMAT_PMPDIDX_M MAKEMASK(0x1FF, 16)
3638 #define GLHMC_FWSDDATAHIGH 0x00522078 /* Reset Source: CORER */
3639 #define GLHMC_FWSDDATAHIGH_PMSDDATAHIGH_S 0
3640 #define GLHMC_FWSDDATAHIGH_PMSDDATAHIGH_M MAKEMASK(0xFFFFFFFF, 0)
3641 #define GLHMC_FWSDDATAHIGH_FPMAT 0x00102078 /* Reset Source: CORER */
3642 #define GLHMC_FWSDDATAHIGH_FPMAT_PMSDDATAHIGH_S 0
3643 #define GLHMC_FWSDDATAHIGH_FPMAT_PMSDDATAHIGH_M MAKEMASK(0xFFFFFFFF, 0)
3644 #define GLHMC_FWSDDATALOW 0x00522074 /* Reset Source: CORER */
3645 #define GLHMC_FWSDDATALOW_PMSDVALID_S 0
3646 #define GLHMC_FWSDDATALOW_PMSDVALID_M BIT(0)
3647 #define GLHMC_FWSDDATALOW_PMSDTYPE_S 1
3648 #define GLHMC_FWSDDATALOW_PMSDTYPE_M BIT(1)
3649 #define GLHMC_FWSDDATALOW_PMSDBPCOUNT_S 2
3650 #define GLHMC_FWSDDATALOW_PMSDBPCOUNT_M MAKEMASK(0x3FF, 2)
3651 #define GLHMC_FWSDDATALOW_PMSDDATALOW_S 12
3652 #define GLHMC_FWSDDATALOW_PMSDDATALOW_M MAKEMASK(0xFFFFF, 12)
3653 #define GLHMC_FWSDDATALOW_FPMAT 0x00102074 /* Reset Source: CORER */
3654 #define GLHMC_FWSDDATALOW_FPMAT_PMSDVALID_S 0
3655 #define GLHMC_FWSDDATALOW_FPMAT_PMSDVALID_M BIT(0)
3656 #define GLHMC_FWSDDATALOW_FPMAT_PMSDTYPE_S 1
3657 #define GLHMC_FWSDDATALOW_FPMAT_PMSDTYPE_M BIT(1)
3658 #define GLHMC_FWSDDATALOW_FPMAT_PMSDBPCOUNT_S 2
3659 #define GLHMC_FWSDDATALOW_FPMAT_PMSDBPCOUNT_M MAKEMASK(0x3FF, 2)
3660 #define GLHMC_FWSDDATALOW_FPMAT_PMSDDATALOW_S 12
3661 #define GLHMC_FWSDDATALOW_FPMAT_PMSDDATALOW_M MAKEMASK(0xFFFFF, 12)
3662 #define GLHMC_PEARPBASE(_i) (0x00524800 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
3663 #define GLHMC_PEARPBASE_MAX_INDEX 7
3664 #define GLHMC_PEARPBASE_FPMPEARPBASE_S 0
3665 #define GLHMC_PEARPBASE_FPMPEARPBASE_M MAKEMASK(0xFFFFFF, 0)
3666 #define GLHMC_PEARPCNT(_i) (0x00524900 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
3667 #define GLHMC_PEARPCNT_MAX_INDEX 7
3668 #define GLHMC_PEARPCNT_FPMPEARPCNT_S 0
3669 #define GLHMC_PEARPCNT_FPMPEARPCNT_M MAKEMASK(0x1FFFFFFF, 0)
3670 #define GLHMC_PEARPMAX 0x00522038 /* Reset Source: CORER */
3671 #define GLHMC_PEARPMAX_PMPEARPMAX_S 0
3672 #define GLHMC_PEARPMAX_PMPEARPMAX_M MAKEMASK(0x1FFFF, 0)
3673 #define GLHMC_PEARPOBJSZ 0x00522034 /* Reset Source: CORER */
3674 #define GLHMC_PEARPOBJSZ_PMPEARPOBJSZ_S 0
3675 #define GLHMC_PEARPOBJSZ_PMPEARPOBJSZ_M MAKEMASK(0x7, 0)
3676 #define GLHMC_PECQBASE(_i) (0x00524200 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
3677 #define GLHMC_PECQBASE_MAX_INDEX 7
3678 #define GLHMC_PECQBASE_FPMPECQBASE_S 0
3679 #define GLHMC_PECQBASE_FPMPECQBASE_M MAKEMASK(0xFFFFFF, 0)
3680 #define GLHMC_PECQCNT(_i) (0x00524300 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
3681 #define GLHMC_PECQCNT_MAX_INDEX 7
3682 #define GLHMC_PECQCNT_FPMPECQCNT_S 0
3683 #define GLHMC_PECQCNT_FPMPECQCNT_M MAKEMASK(0x1FFFFFFF, 0)
3684 #define GLHMC_PECQOBJSZ 0x00522020 /* Reset Source: CORER */
3685 #define GLHMC_PECQOBJSZ_PMPECQOBJSZ_S 0
3686 #define GLHMC_PECQOBJSZ_PMPECQOBJSZ_M MAKEMASK(0xF, 0)
3687 #define GLHMC_PEHDRBASE(_i) (0x00526200 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
3688 #define GLHMC_PEHDRBASE_MAX_INDEX 7
3689 #define GLHMC_PEHDRBASE_GLHMC_PEHDRBASE_S 0
3690 #define GLHMC_PEHDRBASE_GLHMC_PEHDRBASE_M MAKEMASK(0xFFFFFFFF, 0)
3691 #define GLHMC_PEHDRCNT(_i) (0x00526300 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
3692 #define GLHMC_PEHDRCNT_MAX_INDEX 7
3693 #define GLHMC_PEHDRCNT_GLHMC_PEHDRCNT_S 0
3694 #define GLHMC_PEHDRCNT_GLHMC_PEHDRCNT_M MAKEMASK(0xFFFFFFFF, 0)
3695 #define GLHMC_PEHDRMAX 0x00522008 /* Reset Source: CORER */
3696 #define GLHMC_PEHDRMAX_PMPEHDRMAX_S 0
3697 #define GLHMC_PEHDRMAX_PMPEHDRMAX_M MAKEMASK(0x7FFFF, 0)
3698 #define GLHMC_PEHDRMAX_RSVD_S 19
3699 #define GLHMC_PEHDRMAX_RSVD_M MAKEMASK(0x1FFF, 19)
3700 #define GLHMC_PEHDROBJSZ 0x00522004 /* Reset Source: CORER */
3701 #define GLHMC_PEHDROBJSZ_PMPEHDROBJSZ_S 0
3702 #define GLHMC_PEHDROBJSZ_PMPEHDROBJSZ_M MAKEMASK(0xF, 0)
3703 #define GLHMC_PEHDROBJSZ_RSVD_S 4
3704 #define GLHMC_PEHDROBJSZ_RSVD_M MAKEMASK(0xFFFFFFF, 4)
3705 #define GLHMC_PEHTCNT(_i) (0x00524700 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
3706 #define GLHMC_PEHTCNT_MAX_INDEX 7
3707 #define GLHMC_PEHTCNT_FPMPEHTCNT_S 0
3708 #define GLHMC_PEHTCNT_FPMPEHTCNT_M MAKEMASK(0x1FFFFFFF, 0)
3709 #define GLHMC_PEHTCNT_FPMAT(_i) (0x00104700 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
3710 #define GLHMC_PEHTCNT_FPMAT_MAX_INDEX 7
3711 #define GLHMC_PEHTCNT_FPMAT_FPMPEHTCNT_S 0
3712 #define GLHMC_PEHTCNT_FPMAT_FPMPEHTCNT_M MAKEMASK(0x1FFFFFFF, 0)
3713 #define GLHMC_PEHTEBASE(_i) (0x00524600 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
3714 #define GLHMC_PEHTEBASE_MAX_INDEX 7
3715 #define GLHMC_PEHTEBASE_FPMPEHTEBASE_S 0
3716 #define GLHMC_PEHTEBASE_FPMPEHTEBASE_M MAKEMASK(0xFFFFFF, 0)
3717 #define GLHMC_PEHTEBASE_FPMAT(_i) (0x00104600 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
3718 #define GLHMC_PEHTEBASE_FPMAT_MAX_INDEX 7
3719 #define GLHMC_PEHTEBASE_FPMAT_FPMPEHTEBASE_S 0
3720 #define GLHMC_PEHTEBASE_FPMAT_FPMPEHTEBASE_M MAKEMASK(0xFFFFFF, 0)
3721 #define GLHMC_PEHTEOBJSZ 0x0052202C /* Reset Source: CORER */
3722 #define GLHMC_PEHTEOBJSZ_PMPEHTEOBJSZ_S 0
3723 #define GLHMC_PEHTEOBJSZ_PMPEHTEOBJSZ_M MAKEMASK(0xF, 0)
3724 #define GLHMC_PEHTEOBJSZ_FPMAT 0x0010202C /* Reset Source: CORER */
3725 #define GLHMC_PEHTEOBJSZ_FPMAT_PMPEHTEOBJSZ_S 0
3726 #define GLHMC_PEHTEOBJSZ_FPMAT_PMPEHTEOBJSZ_M MAKEMASK(0xF, 0)
3727 #define GLHMC_PEHTMAX 0x00522030 /* Reset Source: CORER */
3728 #define GLHMC_PEHTMAX_PMPEHTMAX_S 0
3729 #define GLHMC_PEHTMAX_PMPEHTMAX_M MAKEMASK(0x1FFFFF, 0)
3730 #define GLHMC_PEHTMAX_FPMAT 0x00102030 /* Reset Source: CORER */
3731 #define GLHMC_PEHTMAX_FPMAT_PMPEHTMAX_S 0
3732 #define GLHMC_PEHTMAX_FPMAT_PMPEHTMAX_M MAKEMASK(0x1FFFFF, 0)
3733 #define GLHMC_PEMDBASE(_i) (0x00526400 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
3734 #define GLHMC_PEMDBASE_MAX_INDEX 7
3735 #define GLHMC_PEMDBASE_GLHMC_PEMDBASE_S 0
3736 #define GLHMC_PEMDBASE_GLHMC_PEMDBASE_M MAKEMASK(0xFFFFFFFF, 0)
3737 #define GLHMC_PEMDCNT(_i) (0x00526500 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
3738 #define GLHMC_PEMDCNT_MAX_INDEX 7
3739 #define GLHMC_PEMDCNT_GLHMC_PEMDCNT_S 0
3740 #define GLHMC_PEMDCNT_GLHMC_PEMDCNT_M MAKEMASK(0xFFFFFFFF, 0)
3741 #define GLHMC_PEMDMAX 0x00522010 /* Reset Source: CORER */
3742 #define GLHMC_PEMDMAX_PMPEMDMAX_S 0
3743 #define GLHMC_PEMDMAX_PMPEMDMAX_M MAKEMASK(0xFFFFFF, 0)
3744 #define GLHMC_PEMDMAX_RSVD_S 24
3745 #define GLHMC_PEMDMAX_RSVD_M MAKEMASK(0xFF, 24)
3746 #define GLHMC_PEMDOBJSZ 0x0052200C /* Reset Source: CORER */
3747 #define GLHMC_PEMDOBJSZ_PMPEMDOBJSZ_S 0
3748 #define GLHMC_PEMDOBJSZ_PMPEMDOBJSZ_M MAKEMASK(0xF, 0)
3749 #define GLHMC_PEMDOBJSZ_RSVD_S 4
3750 #define GLHMC_PEMDOBJSZ_RSVD_M MAKEMASK(0xFFFFFFF, 4)
3751 #define GLHMC_PEMRBASE(_i) (0x00524C00 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
3752 #define GLHMC_PEMRBASE_MAX_INDEX 7
3753 #define GLHMC_PEMRBASE_FPMPEMRBASE_S 0
3754 #define GLHMC_PEMRBASE_FPMPEMRBASE_M MAKEMASK(0xFFFFFF, 0)
3755 #define GLHMC_PEMRCNT(_i) (0x00524D00 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
3756 #define GLHMC_PEMRCNT_MAX_INDEX 7
3757 #define GLHMC_PEMRCNT_FPMPEMRSZ_S 0
3758 #define GLHMC_PEMRCNT_FPMPEMRSZ_M MAKEMASK(0x1FFFFFFF, 0)
3759 #define GLHMC_PEMRMAX 0x00522040 /* Reset Source: CORER */
3760 #define GLHMC_PEMRMAX_PMPEMRMAX_S 0
3761 #define GLHMC_PEMRMAX_PMPEMRMAX_M MAKEMASK(0x7FFFFF, 0)
3762 #define GLHMC_PEMROBJSZ 0x0052203C /* Reset Source: CORER */
3763 #define GLHMC_PEMROBJSZ_PMPEMROBJSZ_S 0
3764 #define GLHMC_PEMROBJSZ_PMPEMROBJSZ_M MAKEMASK(0xF, 0)
3765 #define GLHMC_PEOOISCBASE(_i) (0x00526600 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
3766 #define GLHMC_PEOOISCBASE_MAX_INDEX 7
3767 #define GLHMC_PEOOISCBASE_GLHMC_PEOOISCBASE_S 0
3768 #define GLHMC_PEOOISCBASE_GLHMC_PEOOISCBASE_M MAKEMASK(0xFFFFFFFF, 0)
3769 #define GLHMC_PEOOISCCNT(_i) (0x00526700 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
3770 #define GLHMC_PEOOISCCNT_MAX_INDEX 7
3771 #define GLHMC_PEOOISCCNT_GLHMC_PEOOISCCNT_S 0
3772 #define GLHMC_PEOOISCCNT_GLHMC_PEOOISCCNT_M MAKEMASK(0xFFFFFFFF, 0)
3773 #define GLHMC_PEOOISCFFLBASE(_i) (0x00526C00 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
3774 #define GLHMC_PEOOISCFFLBASE_MAX_INDEX 7
3775 #define GLHMC_PEOOISCFFLBASE_GLHMC_PEOOISCFFLBASE_S 0
3776 #define GLHMC_PEOOISCFFLBASE_GLHMC_PEOOISCFFLBASE_M MAKEMASK(0xFFFFFFFF, 0)
3777 #define GLHMC_PEOOISCFFLCNT_PMAT(_i) (0x00526D00 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
3778 #define GLHMC_PEOOISCFFLCNT_PMAT_MAX_INDEX 7
3779 #define GLHMC_PEOOISCFFLCNT_PMAT_FPMPEOOISCFLCNT_S 0
3780 #define GLHMC_PEOOISCFFLCNT_PMAT_FPMPEOOISCFLCNT_M MAKEMASK(0x1FFFFFFF, 0)
3781 #define GLHMC_PEOOISCFFLMAX 0x005220A4 /* Reset Source: CORER */
3782 #define GLHMC_PEOOISCFFLMAX_PMPEOOISCFFLMAX_S 0
3783 #define GLHMC_PEOOISCFFLMAX_PMPEOOISCFFLMAX_M MAKEMASK(0x7FFFF, 0)
3784 #define GLHMC_PEOOISCFFLMAX_RSVD_S 19
3785 #define GLHMC_PEOOISCFFLMAX_RSVD_M MAKEMASK(0x1FFF, 19)
3786 #define GLHMC_PEOOISCMAX 0x00522018 /* Reset Source: CORER */
3787 #define GLHMC_PEOOISCMAX_PMPEOOISCMAX_S 0
3788 #define GLHMC_PEOOISCMAX_PMPEOOISCMAX_M MAKEMASK(0x7FFFF, 0)
3789 #define GLHMC_PEOOISCMAX_RSVD_S 19
3790 #define GLHMC_PEOOISCMAX_RSVD_M MAKEMASK(0x1FFF, 19)
3791 #define GLHMC_PEOOISCOBJSZ 0x00522014 /* Reset Source: CORER */
3792 #define GLHMC_PEOOISCOBJSZ_PMPEOOISCOBJSZ_S 0
3793 #define GLHMC_PEOOISCOBJSZ_PMPEOOISCOBJSZ_M MAKEMASK(0xF, 0)
3794 #define GLHMC_PEOOISCOBJSZ_RSVD_S 4
3795 #define GLHMC_PEOOISCOBJSZ_RSVD_M MAKEMASK(0xFFFFFFF, 4)
3796 #define GLHMC_PEPBLBASE(_i) (0x00525800 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
3797 #define GLHMC_PEPBLBASE_MAX_INDEX 7
3798 #define GLHMC_PEPBLBASE_FPMPEPBLBASE_S 0
3799 #define GLHMC_PEPBLBASE_FPMPEPBLBASE_M MAKEMASK(0xFFFFFF, 0)
3800 #define GLHMC_PEPBLCNT(_i) (0x00525900 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
3801 #define GLHMC_PEPBLCNT_MAX_INDEX 7
3802 #define GLHMC_PEPBLCNT_FPMPEPBLCNT_S 0
3803 #define GLHMC_PEPBLCNT_FPMPEPBLCNT_M MAKEMASK(0x1FFFFFFF, 0)
3804 #define GLHMC_PEPBLMAX 0x0052206C /* Reset Source: CORER */
3805 #define GLHMC_PEPBLMAX_PMPEPBLMAX_S 0
3806 #define GLHMC_PEPBLMAX_PMPEPBLMAX_M MAKEMASK(0x1FFFFFFF, 0)
3807 #define GLHMC_PEQ1BASE(_i) (0x00525200 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
3808 #define GLHMC_PEQ1BASE_MAX_INDEX 7
3809 #define GLHMC_PEQ1BASE_FPMPEQ1BASE_S 0
3810 #define GLHMC_PEQ1BASE_FPMPEQ1BASE_M MAKEMASK(0xFFFFFF, 0)
3811 #define GLHMC_PEQ1CNT(_i) (0x00525300 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
3812 #define GLHMC_PEQ1CNT_MAX_INDEX 7
3813 #define GLHMC_PEQ1CNT_FPMPEQ1CNT_S 0
3814 #define GLHMC_PEQ1CNT_FPMPEQ1CNT_M MAKEMASK(0x1FFFFFFF, 0)
3815 #define GLHMC_PEQ1FLBASE(_i) (0x00525400 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
3816 #define GLHMC_PEQ1FLBASE_MAX_INDEX 7
3817 #define GLHMC_PEQ1FLBASE_FPMPEQ1FLBASE_S 0
3818 #define GLHMC_PEQ1FLBASE_FPMPEQ1FLBASE_M MAKEMASK(0xFFFFFF, 0)
3819 #define GLHMC_PEQ1FLMAX 0x00522058 /* Reset Source: CORER */
3820 #define GLHMC_PEQ1FLMAX_PMPEQ1FLMAX_S 0
3821 #define GLHMC_PEQ1FLMAX_PMPEQ1FLMAX_M MAKEMASK(0x3FFFFFF, 0)
3822 #define GLHMC_PEQ1MAX 0x00522054 /* Reset Source: CORER */
3823 #define GLHMC_PEQ1MAX_PMPEQ1MAX_S 0
3824 #define GLHMC_PEQ1MAX_PMPEQ1MAX_M MAKEMASK(0xFFFFFFF, 0)
3825 #define GLHMC_PEQ1OBJSZ 0x00522050 /* Reset Source: CORER */
3826 #define GLHMC_PEQ1OBJSZ_PMPEQ1OBJSZ_S 0
3827 #define GLHMC_PEQ1OBJSZ_PMPEQ1OBJSZ_M MAKEMASK(0xF, 0)
3828 #define GLHMC_PEQPBASE(_i) (0x00524000 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
3829 #define GLHMC_PEQPBASE_MAX_INDEX 7
3830 #define GLHMC_PEQPBASE_FPMPEQPBASE_S 0
3831 #define GLHMC_PEQPBASE_FPMPEQPBASE_M MAKEMASK(0xFFFFFF, 0)
3832 #define GLHMC_PEQPCNT(_i) (0x00524100 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
3833 #define GLHMC_PEQPCNT_MAX_INDEX 7
3834 #define GLHMC_PEQPCNT_FPMPEQPCNT_S 0
3835 #define GLHMC_PEQPCNT_FPMPEQPCNT_M MAKEMASK(0x1FFFFFFF, 0)
3836 #define GLHMC_PEQPOBJSZ 0x0052201C /* Reset Source: CORER */
3837 #define GLHMC_PEQPOBJSZ_PMPEQPOBJSZ_S 0
3838 #define GLHMC_PEQPOBJSZ_PMPEQPOBJSZ_M MAKEMASK(0xF, 0)
3839 #define GLHMC_PERRFBASE(_i) (0x00526800 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
3840 #define GLHMC_PERRFBASE_MAX_INDEX 7
3841 #define GLHMC_PERRFBASE_GLHMC_PERRFBASE_S 0
3842 #define GLHMC_PERRFBASE_GLHMC_PERRFBASE_M MAKEMASK(0xFFFFFFFF, 0)
3843 #define GLHMC_PERRFCNT(_i) (0x00526900 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
3844 #define GLHMC_PERRFCNT_MAX_INDEX 7
3845 #define GLHMC_PERRFCNT_GLHMC_PERRFCNT_S 0
3846 #define GLHMC_PERRFCNT_GLHMC_PERRFCNT_M MAKEMASK(0xFFFFFFFF, 0)
3847 #define GLHMC_PERRFFLBASE(_i) (0x00526A00 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
3848 #define GLHMC_PERRFFLBASE_MAX_INDEX 7
3849 #define GLHMC_PERRFFLBASE_GLHMC_PERRFFLBASE_S 0
3850 #define GLHMC_PERRFFLBASE_GLHMC_PERRFFLBASE_M MAKEMASK(0xFFFFFFFF, 0)
3851 #define GLHMC_PERRFFLCNT_PMAT(_i) (0x00526B00 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
3852 #define GLHMC_PERRFFLCNT_PMAT_MAX_INDEX 7
3853 #define GLHMC_PERRFFLCNT_PMAT_FPMPERRFFLCNT_S 0
3854 #define GLHMC_PERRFFLCNT_PMAT_FPMPERRFFLCNT_M MAKEMASK(0x1FFFFFFF, 0)
3855 #define GLHMC_PERRFFLMAX 0x005220A0 /* Reset Source: CORER */
3856 #define GLHMC_PERRFFLMAX_PMPERRFFLMAX_S 0
3857 #define GLHMC_PERRFFLMAX_PMPERRFFLMAX_M MAKEMASK(0x3FFFFFF, 0)
3858 #define GLHMC_PERRFFLMAX_RSVD_S 26
3859 #define GLHMC_PERRFFLMAX_RSVD_M MAKEMASK(0x3F, 26)
3860 #define GLHMC_PERRFMAX 0x0052209C /* Reset Source: CORER */
3861 #define GLHMC_PERRFMAX_PMPERRFMAX_S 0
3862 #define GLHMC_PERRFMAX_PMPERRFMAX_M MAKEMASK(0xFFFFFFF, 0)
3863 #define GLHMC_PERRFMAX_RSVD_S 28
3864 #define GLHMC_PERRFMAX_RSVD_M MAKEMASK(0xF, 28)
3865 #define GLHMC_PERRFOBJSZ 0x00522098 /* Reset Source: CORER */
3866 #define GLHMC_PERRFOBJSZ_PMPERRFOBJSZ_S 0
3867 #define GLHMC_PERRFOBJSZ_PMPERRFOBJSZ_M MAKEMASK(0xF, 0)
3868 #define GLHMC_PERRFOBJSZ_RSVD_S 4
3869 #define GLHMC_PERRFOBJSZ_RSVD_M MAKEMASK(0xFFFFFFF, 4)
3870 #define GLHMC_PETIMERBASE(_i) (0x00525A00 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
3871 #define GLHMC_PETIMERBASE_MAX_INDEX 7
3872 #define GLHMC_PETIMERBASE_FPMPETIMERBASE_S 0
3873 #define GLHMC_PETIMERBASE_FPMPETIMERBASE_M MAKEMASK(0xFFFFFF, 0)
3874 #define GLHMC_PETIMERCNT(_i) (0x00525B00 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
3875 #define GLHMC_PETIMERCNT_MAX_INDEX 7
3876 #define GLHMC_PETIMERCNT_FPMPETIMERCNT_S 0
3877 #define GLHMC_PETIMERCNT_FPMPETIMERCNT_M MAKEMASK(0x1FFFFFFF, 0)
3878 #define GLHMC_PETIMERMAX 0x00522084 /* Reset Source: CORER */
3879 #define GLHMC_PETIMERMAX_PMPETIMERMAX_S 0
3880 #define GLHMC_PETIMERMAX_PMPETIMERMAX_M MAKEMASK(0x1FFFFFFF, 0)
3881 #define GLHMC_PETIMEROBJSZ 0x00522080 /* Reset Source: CORER */
3882 #define GLHMC_PETIMEROBJSZ_PMPETIMEROBJSZ_S 0
3883 #define GLHMC_PETIMEROBJSZ_PMPETIMEROBJSZ_M MAKEMASK(0xF, 0)
3884 #define GLHMC_PEXFBASE(_i) (0x00524E00 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
3885 #define GLHMC_PEXFBASE_MAX_INDEX 7
3886 #define GLHMC_PEXFBASE_FPMPEXFBASE_S 0
3887 #define GLHMC_PEXFBASE_FPMPEXFBASE_M MAKEMASK(0xFFFFFF, 0)
3888 #define GLHMC_PEXFCNT(_i) (0x00524F00 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
3889 #define GLHMC_PEXFCNT_MAX_INDEX 7
3890 #define GLHMC_PEXFCNT_FPMPEXFCNT_S 0
3891 #define GLHMC_PEXFCNT_FPMPEXFCNT_M MAKEMASK(0x1FFFFFFF, 0)
3892 #define GLHMC_PEXFFLBASE(_i) (0x00525000 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
3893 #define GLHMC_PEXFFLBASE_MAX_INDEX 7
3894 #define GLHMC_PEXFFLBASE_FPMPEXFFLBASE_S 0
3895 #define GLHMC_PEXFFLBASE_FPMPEXFFLBASE_M MAKEMASK(0xFFFFFF, 0)
3896 #define GLHMC_PEXFFLMAX 0x0052204C /* Reset Source: CORER */
3897 #define GLHMC_PEXFFLMAX_PMPEXFFLMAX_S 0
3898 #define GLHMC_PEXFFLMAX_PMPEXFFLMAX_M MAKEMASK(0xFFFFFFF, 0)
3899 #define GLHMC_PEXFMAX 0x00522048 /* Reset Source: CORER */
3900 #define GLHMC_PEXFMAX_PMPEXFMAX_S 0
3901 #define GLHMC_PEXFMAX_PMPEXFMAX_M MAKEMASK(0xFFFFFFF, 0)
3902 #define GLHMC_PEXFOBJSZ 0x00522044 /* Reset Source: CORER */
3903 #define GLHMC_PEXFOBJSZ_PMPEXFOBJSZ_S 0
3904 #define GLHMC_PEXFOBJSZ_PMPEXFOBJSZ_M MAKEMASK(0xF, 0)
3905 #define GLHMC_PFPESDPART(_i) (0x00520880 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
3906 #define GLHMC_PFPESDPART_MAX_INDEX 7
3907 #define GLHMC_PFPESDPART_PMSDBASE_S 0
3908 #define GLHMC_PFPESDPART_PMSDBASE_M MAKEMASK(0xFFF, 0)
3909 #define GLHMC_PFPESDPART_PMSDSIZE_S 16
3910 #define GLHMC_PFPESDPART_PMSDSIZE_M MAKEMASK(0x1FFF, 16)
3911 #define GLHMC_PFPESDPART_FPMAT(_i) (0x00100880 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
3912 #define GLHMC_PFPESDPART_FPMAT_MAX_INDEX 7
3913 #define GLHMC_PFPESDPART_FPMAT_PMSDBASE_S 0
3914 #define GLHMC_PFPESDPART_FPMAT_PMSDBASE_M MAKEMASK(0xFFF, 0)
3915 #define GLHMC_PFPESDPART_FPMAT_PMSDSIZE_S 16
3916 #define GLHMC_PFPESDPART_FPMAT_PMSDSIZE_M MAKEMASK(0x1FFF, 16)
3917 #define GLHMC_SDPART(_i) (0x00520800 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
3918 #define GLHMC_SDPART_MAX_INDEX 7
3919 #define GLHMC_SDPART_PMSDBASE_S 0
3920 #define GLHMC_SDPART_PMSDBASE_M MAKEMASK(0xFFF, 0)
3921 #define GLHMC_SDPART_PMSDSIZE_S 16
3922 #define GLHMC_SDPART_PMSDSIZE_M MAKEMASK(0x1FFF, 16)
3923 #define GLHMC_SDPART_FPMAT(_i) (0x00100800 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
3924 #define GLHMC_SDPART_FPMAT_MAX_INDEX 7
3925 #define GLHMC_SDPART_FPMAT_PMSDBASE_S 0
3926 #define GLHMC_SDPART_FPMAT_PMSDBASE_M MAKEMASK(0xFFF, 0)
3927 #define GLHMC_SDPART_FPMAT_PMSDSIZE_S 16
3928 #define GLHMC_SDPART_FPMAT_PMSDSIZE_M MAKEMASK(0x1FFF, 16)
3929 #define GLHMC_VFAPBVTINUSEBASE(_i) (0x0052CA00 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
3930 #define GLHMC_VFAPBVTINUSEBASE_MAX_INDEX 31
3931 #define GLHMC_VFAPBVTINUSEBASE_FPMAPBINUSEBASE_S 0
3932 #define GLHMC_VFAPBVTINUSEBASE_FPMAPBINUSEBASE_M MAKEMASK(0xFFFFFF, 0)
3933 #define GLHMC_VFCEQPART(_i) (0x00502F00 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
3934 #define GLHMC_VFCEQPART_MAX_INDEX 31
3935 #define GLHMC_VFCEQPART_PMCEQBASE_S 0
3936 #define GLHMC_VFCEQPART_PMCEQBASE_M MAKEMASK(0x3FF, 0)
3937 #define GLHMC_VFCEQPART_PMCEQSIZE_S 16
3938 #define GLHMC_VFCEQPART_PMCEQSIZE_M MAKEMASK(0x3FF, 16)
3939 #define GLHMC_VFDBCQPART(_i) (0x00502E00 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
3940 #define GLHMC_VFDBCQPART_MAX_INDEX 31
3941 #define GLHMC_VFDBCQPART_PMDBCQBASE_S 0
3942 #define GLHMC_VFDBCQPART_PMDBCQBASE_M MAKEMASK(0x3FFF, 0)
3943 #define GLHMC_VFDBCQPART_PMDBCQSIZE_S 16
3944 #define GLHMC_VFDBCQPART_PMDBCQSIZE_M MAKEMASK(0x7FFF, 16)
3945 #define GLHMC_VFDBQPPART(_i) (0x00504520 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
3946 #define GLHMC_VFDBQPPART_MAX_INDEX 31
3947 #define GLHMC_VFDBQPPART_PMDBQPBASE_S 0
3948 #define GLHMC_VFDBQPPART_PMDBQPBASE_M MAKEMASK(0x3FFF, 0)
3949 #define GLHMC_VFDBQPPART_PMDBQPSIZE_S 16
3950 #define GLHMC_VFDBQPPART_PMDBQPSIZE_M MAKEMASK(0x7FFF, 16)
3951 #define GLHMC_VFFSIAVBASE(_i) (0x0052D600 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
3952 #define GLHMC_VFFSIAVBASE_MAX_INDEX 31
3953 #define GLHMC_VFFSIAVBASE_FPMFSIAVBASE_S 0
3954 #define GLHMC_VFFSIAVBASE_FPMFSIAVBASE_M MAKEMASK(0xFFFFFF, 0)
3955 #define GLHMC_VFFSIAVCNT(_i) (0x0052D700 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
3956 #define GLHMC_VFFSIAVCNT_MAX_INDEX 31
3957 #define GLHMC_VFFSIAVCNT_FPMFSIAVCNT_S 0
3958 #define GLHMC_VFFSIAVCNT_FPMFSIAVCNT_M MAKEMASK(0x1FFFFFFF, 0)
3959 #define GLHMC_VFFSIMCBASE(_i) (0x0052E000 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
3960 #define GLHMC_VFFSIMCBASE_MAX_INDEX 31
3961 #define GLHMC_VFFSIMCBASE_FPMFSIMCBASE_S 0
3962 #define GLHMC_VFFSIMCBASE_FPMFSIMCBASE_M MAKEMASK(0xFFFFFF, 0)
3963 #define GLHMC_VFFSIMCCNT(_i) (0x0052E100 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
3964 #define GLHMC_VFFSIMCCNT_MAX_INDEX 31
3965 #define GLHMC_VFFSIMCCNT_FPMFSIMCSZ_S 0
3966 #define GLHMC_VFFSIMCCNT_FPMFSIMCSZ_M MAKEMASK(0x1FFFFFFF, 0)
3967 #define GLHMC_VFPDINV(_i) (0x00528300 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
3968 #define GLHMC_VFPDINV_MAX_INDEX 31
3969 #define GLHMC_VFPDINV_PMSDIDX_S 0
3970 #define GLHMC_VFPDINV_PMSDIDX_M MAKEMASK(0xFFF, 0)
3971 #define GLHMC_VFPDINV_PMSDPARTSEL_S 15
3972 #define GLHMC_VFPDINV_PMSDPARTSEL_M BIT(15)
3973 #define GLHMC_VFPDINV_PMPDIDX_S 16
3974 #define GLHMC_VFPDINV_PMPDIDX_M MAKEMASK(0x1FF, 16)
3975 #define GLHMC_VFPDINV_FPMAT(_i) (0x00108300 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
3976 #define GLHMC_VFPDINV_FPMAT_MAX_INDEX 31
3977 #define GLHMC_VFPDINV_FPMAT_PMSDIDX_S 0
3978 #define GLHMC_VFPDINV_FPMAT_PMSDIDX_M MAKEMASK(0xFFF, 0)
3979 #define GLHMC_VFPDINV_FPMAT_PMSDPARTSEL_S 15
3980 #define GLHMC_VFPDINV_FPMAT_PMSDPARTSEL_M BIT(15)
3981 #define GLHMC_VFPDINV_FPMAT_PMPDIDX_S 16
3982 #define GLHMC_VFPDINV_FPMAT_PMPDIDX_M MAKEMASK(0x1FF, 16)
3983 #define GLHMC_VFPEARPBASE(_i) (0x0052C800 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
3984 #define GLHMC_VFPEARPBASE_MAX_INDEX 31
3985 #define GLHMC_VFPEARPBASE_FPMPEARPBASE_S 0
3986 #define GLHMC_VFPEARPBASE_FPMPEARPBASE_M MAKEMASK(0xFFFFFF, 0)
3987 #define GLHMC_VFPEARPCNT(_i) (0x0052C900 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
3988 #define GLHMC_VFPEARPCNT_MAX_INDEX 31
3989 #define GLHMC_VFPEARPCNT_FPMPEARPCNT_S 0
3990 #define GLHMC_VFPEARPCNT_FPMPEARPCNT_M MAKEMASK(0x1FFFFFFF, 0)
3991 #define GLHMC_VFPECQBASE(_i) (0x0052C200 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
3992 #define GLHMC_VFPECQBASE_MAX_INDEX 31
3993 #define GLHMC_VFPECQBASE_FPMPECQBASE_S 0
3994 #define GLHMC_VFPECQBASE_FPMPECQBASE_M MAKEMASK(0xFFFFFF, 0)
3995 #define GLHMC_VFPECQCNT(_i) (0x0052C300 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
3996 #define GLHMC_VFPECQCNT_MAX_INDEX 31
3997 #define GLHMC_VFPECQCNT_FPMPECQCNT_S 0
3998 #define GLHMC_VFPECQCNT_FPMPECQCNT_M MAKEMASK(0x1FFFFFFF, 0)
3999 #define GLHMC_VFPEHDRBASE(_i) (0x0052E200 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
4000 #define GLHMC_VFPEHDRBASE_MAX_INDEX 31
4001 #define GLHMC_VFPEHDRBASE_GLHMC_PEHDRBASE_S 0
4002 #define GLHMC_VFPEHDRBASE_GLHMC_PEHDRBASE_M MAKEMASK(0xFFFFFFFF, 0)
4003 #define GLHMC_VFPEHDRCNT(_i) (0x0052E300 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
4004 #define GLHMC_VFPEHDRCNT_MAX_INDEX 31
4005 #define GLHMC_VFPEHDRCNT_GLHMC_PEHDRCNT_S 0
4006 #define GLHMC_VFPEHDRCNT_GLHMC_PEHDRCNT_M MAKEMASK(0xFFFFFFFF, 0)
4007 #define GLHMC_VFPEHTCNT(_i) (0x0052C700 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
4008 #define GLHMC_VFPEHTCNT_MAX_INDEX 31
4009 #define GLHMC_VFPEHTCNT_FPMPEHTCNT_S 0
4010 #define GLHMC_VFPEHTCNT_FPMPEHTCNT_M MAKEMASK(0x1FFFFFFF, 0)
4011 #define GLHMC_VFPEHTCNT_FPMAT(_i) (0x0010C700 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
4012 #define GLHMC_VFPEHTCNT_FPMAT_MAX_INDEX 31
4013 #define GLHMC_VFPEHTCNT_FPMAT_FPMPEHTCNT_S 0
4014 #define GLHMC_VFPEHTCNT_FPMAT_FPMPEHTCNT_M MAKEMASK(0x1FFFFFFF, 0)
4015 #define GLHMC_VFPEHTEBASE(_i) (0x0052C600 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
4016 #define GLHMC_VFPEHTEBASE_MAX_INDEX 31
4017 #define GLHMC_VFPEHTEBASE_FPMPEHTEBASE_S 0
4018 #define GLHMC_VFPEHTEBASE_FPMPEHTEBASE_M MAKEMASK(0xFFFFFF, 0)
4019 #define GLHMC_VFPEHTEBASE_FPMAT(_i) (0x0010C600 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
4020 #define GLHMC_VFPEHTEBASE_FPMAT_MAX_INDEX 31
4021 #define GLHMC_VFPEHTEBASE_FPMAT_FPMPEHTEBASE_S 0
4022 #define GLHMC_VFPEHTEBASE_FPMAT_FPMPEHTEBASE_M MAKEMASK(0xFFFFFF, 0)
4023 #define GLHMC_VFPEMDBASE(_i) (0x0052E400 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
4024 #define GLHMC_VFPEMDBASE_MAX_INDEX 31
4025 #define GLHMC_VFPEMDBASE_GLHMC_PEMDBASE_S 0
4026 #define GLHMC_VFPEMDBASE_GLHMC_PEMDBASE_M MAKEMASK(0xFFFFFFFF, 0)
4027 #define GLHMC_VFPEMDCNT(_i) (0x0052E500 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
4028 #define GLHMC_VFPEMDCNT_MAX_INDEX 31
4029 #define GLHMC_VFPEMDCNT_GLHMC_PEMDCNT_S 0
4030 #define GLHMC_VFPEMDCNT_GLHMC_PEMDCNT_M MAKEMASK(0xFFFFFFFF, 0)
4031 #define GLHMC_VFPEMRBASE(_i) (0x0052CC00 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
4032 #define GLHMC_VFPEMRBASE_MAX_INDEX 31
4033 #define GLHMC_VFPEMRBASE_FPMPEMRBASE_S 0
4034 #define GLHMC_VFPEMRBASE_FPMPEMRBASE_M MAKEMASK(0xFFFFFF, 0)
4035 #define GLHMC_VFPEMRCNT(_i) (0x0052CD00 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
4036 #define GLHMC_VFPEMRCNT_MAX_INDEX 31
4037 #define GLHMC_VFPEMRCNT_FPMPEMRSZ_S 0
4038 #define GLHMC_VFPEMRCNT_FPMPEMRSZ_M MAKEMASK(0x1FFFFFFF, 0)
4039 #define GLHMC_VFPEOOISCBASE(_i) (0x0052E600 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
4040 #define GLHMC_VFPEOOISCBASE_MAX_INDEX 31
4041 #define GLHMC_VFPEOOISCBASE_GLHMC_PEOOISCBASE_S 0
4042 #define GLHMC_VFPEOOISCBASE_GLHMC_PEOOISCBASE_M MAKEMASK(0xFFFFFFFF, 0)
4043 #define GLHMC_VFPEOOISCCNT(_i) (0x0052E700 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
4044 #define GLHMC_VFPEOOISCCNT_MAX_INDEX 31
4045 #define GLHMC_VFPEOOISCCNT_GLHMC_PEOOISCCNT_S 0
4046 #define GLHMC_VFPEOOISCCNT_GLHMC_PEOOISCCNT_M MAKEMASK(0xFFFFFFFF, 0)
4047 #define GLHMC_VFPEOOISCFFLBASE(_i) (0x0052EC00 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
4048 #define GLHMC_VFPEOOISCFFLBASE_MAX_INDEX 31
4049 #define GLHMC_VFPEOOISCFFLBASE_GLHMC_PEOOISCFFLBASE_S 0
4050 #define GLHMC_VFPEOOISCFFLBASE_GLHMC_PEOOISCFFLBASE_M MAKEMASK(0xFFFFFFFF, 0)
4051 #define GLHMC_VFPEPBLBASE(_i) (0x0052D800 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
4052 #define GLHMC_VFPEPBLBASE_MAX_INDEX 31
4053 #define GLHMC_VFPEPBLBASE_FPMPEPBLBASE_S 0
4054 #define GLHMC_VFPEPBLBASE_FPMPEPBLBASE_M MAKEMASK(0xFFFFFF, 0)
4055 #define GLHMC_VFPEPBLCNT(_i) (0x0052D900 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
4056 #define GLHMC_VFPEPBLCNT_MAX_INDEX 31
4057 #define GLHMC_VFPEPBLCNT_FPMPEPBLCNT_S 0
4058 #define GLHMC_VFPEPBLCNT_FPMPEPBLCNT_M MAKEMASK(0x1FFFFFFF, 0)
4059 #define GLHMC_VFPEQ1BASE(_i) (0x0052D200 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
4060 #define GLHMC_VFPEQ1BASE_MAX_INDEX 31
4061 #define GLHMC_VFPEQ1BASE_FPMPEQ1BASE_S 0
4062 #define GLHMC_VFPEQ1BASE_FPMPEQ1BASE_M MAKEMASK(0xFFFFFF, 0)
4063 #define GLHMC_VFPEQ1CNT(_i) (0x0052D300 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
4064 #define GLHMC_VFPEQ1CNT_MAX_INDEX 31
4065 #define GLHMC_VFPEQ1CNT_FPMPEQ1CNT_S 0
4066 #define GLHMC_VFPEQ1CNT_FPMPEQ1CNT_M MAKEMASK(0x1FFFFFFF, 0)
4067 #define GLHMC_VFPEQ1FLBASE(_i) (0x0052D400 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
4068 #define GLHMC_VFPEQ1FLBASE_MAX_INDEX 31
4069 #define GLHMC_VFPEQ1FLBASE_FPMPEQ1FLBASE_S 0
4070 #define GLHMC_VFPEQ1FLBASE_FPMPEQ1FLBASE_M MAKEMASK(0xFFFFFF, 0)
4071 #define GLHMC_VFPEQPBASE(_i) (0x0052C000 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
4072 #define GLHMC_VFPEQPBASE_MAX_INDEX 31
4073 #define GLHMC_VFPEQPBASE_FPMPEQPBASE_S 0
4074 #define GLHMC_VFPEQPBASE_FPMPEQPBASE_M MAKEMASK(0xFFFFFF, 0)
4075 #define GLHMC_VFPEQPCNT(_i) (0x0052C100 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
4076 #define GLHMC_VFPEQPCNT_MAX_INDEX 31
4077 #define GLHMC_VFPEQPCNT_FPMPEQPCNT_S 0
4078 #define GLHMC_VFPEQPCNT_FPMPEQPCNT_M MAKEMASK(0x1FFFFFFF, 0)
4079 #define GLHMC_VFPERRFBASE(_i) (0x0052E800 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
4080 #define GLHMC_VFPERRFBASE_MAX_INDEX 31
4081 #define GLHMC_VFPERRFBASE_GLHMC_PERRFBASE_S 0
4082 #define GLHMC_VFPERRFBASE_GLHMC_PERRFBASE_M MAKEMASK(0xFFFFFFFF, 0)
4083 #define GLHMC_VFPERRFCNT(_i) (0x0052E900 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
4084 #define GLHMC_VFPERRFCNT_MAX_INDEX 31
4085 #define GLHMC_VFPERRFCNT_GLHMC_PERRFCNT_S 0
4086 #define GLHMC_VFPERRFCNT_GLHMC_PERRFCNT_M MAKEMASK(0xFFFFFFFF, 0)
4087 #define GLHMC_VFPERRFFLBASE(_i) (0x0052EA00 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
4088 #define GLHMC_VFPERRFFLBASE_MAX_INDEX 31
4089 #define GLHMC_VFPERRFFLBASE_GLHMC_PERRFFLBASE_S 0
4090 #define GLHMC_VFPERRFFLBASE_GLHMC_PERRFFLBASE_M MAKEMASK(0xFFFFFFFF, 0)
4091 #define GLHMC_VFPETIMERBASE(_i) (0x0052DA00 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
4092 #define GLHMC_VFPETIMERBASE_MAX_INDEX 31
4093 #define GLHMC_VFPETIMERBASE_FPMPETIMERBASE_S 0
4094 #define GLHMC_VFPETIMERBASE_FPMPETIMERBASE_M MAKEMASK(0xFFFFFF, 0)
4095 #define GLHMC_VFPETIMERCNT(_i) (0x0052DB00 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
4096 #define GLHMC_VFPETIMERCNT_MAX_INDEX 31
4097 #define GLHMC_VFPETIMERCNT_FPMPETIMERCNT_S 0
4098 #define GLHMC_VFPETIMERCNT_FPMPETIMERCNT_M MAKEMASK(0x1FFFFFFF, 0)
4099 #define GLHMC_VFPEXFBASE(_i) (0x0052CE00 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
4100 #define GLHMC_VFPEXFBASE_MAX_INDEX 31
4101 #define GLHMC_VFPEXFBASE_FPMPEXFBASE_S 0
4102 #define GLHMC_VFPEXFBASE_FPMPEXFBASE_M MAKEMASK(0xFFFFFF, 0)
4103 #define GLHMC_VFPEXFCNT(_i) (0x0052CF00 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
4104 #define GLHMC_VFPEXFCNT_MAX_INDEX 31
4105 #define GLHMC_VFPEXFCNT_FPMPEXFCNT_S 0
4106 #define GLHMC_VFPEXFCNT_FPMPEXFCNT_M MAKEMASK(0x1FFFFFFF, 0)
4107 #define GLHMC_VFPEXFFLBASE(_i) (0x0052D000 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
4108 #define GLHMC_VFPEXFFLBASE_MAX_INDEX 31
4109 #define GLHMC_VFPEXFFLBASE_FPMPEXFFLBASE_S 0
4110 #define GLHMC_VFPEXFFLBASE_FPMPEXFFLBASE_M MAKEMASK(0xFFFFFF, 0)
4111 #define GLHMC_VFSDDATAHIGH(_i) (0x00528200 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
4112 #define GLHMC_VFSDDATAHIGH_MAX_INDEX 31
4113 #define GLHMC_VFSDDATAHIGH_PMSDDATAHIGH_S 0
4114 #define GLHMC_VFSDDATAHIGH_PMSDDATAHIGH_M MAKEMASK(0xFFFFFFFF, 0)
4115 #define GLHMC_VFSDDATAHIGH_FPMAT(_i) (0x00108200 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
4116 #define GLHMC_VFSDDATAHIGH_FPMAT_MAX_INDEX 31
4117 #define GLHMC_VFSDDATAHIGH_FPMAT_PMSDDATAHIGH_S 0
4118 #define GLHMC_VFSDDATAHIGH_FPMAT_PMSDDATAHIGH_M MAKEMASK(0xFFFFFFFF, 0)
4119 #define GLHMC_VFSDDATALOW(_i) (0x00528100 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
4120 #define GLHMC_VFSDDATALOW_MAX_INDEX 31
4121 #define GLHMC_VFSDDATALOW_PMSDVALID_S 0
4122 #define GLHMC_VFSDDATALOW_PMSDVALID_M BIT(0)
4123 #define GLHMC_VFSDDATALOW_PMSDTYPE_S 1
4124 #define GLHMC_VFSDDATALOW_PMSDTYPE_M BIT(1)
4125 #define GLHMC_VFSDDATALOW_PMSDBPCOUNT_S 2
4126 #define GLHMC_VFSDDATALOW_PMSDBPCOUNT_M MAKEMASK(0x3FF, 2)
4127 #define GLHMC_VFSDDATALOW_PMSDDATALOW_S 12
4128 #define GLHMC_VFSDDATALOW_PMSDDATALOW_M MAKEMASK(0xFFFFF, 12)
4129 #define GLHMC_VFSDDATALOW_FPMAT(_i) (0x00108100 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
4130 #define GLHMC_VFSDDATALOW_FPMAT_MAX_INDEX 31
4131 #define GLHMC_VFSDDATALOW_FPMAT_PMSDVALID_S 0
4132 #define GLHMC_VFSDDATALOW_FPMAT_PMSDVALID_M BIT(0)
4133 #define GLHMC_VFSDDATALOW_FPMAT_PMSDTYPE_S 1
4134 #define GLHMC_VFSDDATALOW_FPMAT_PMSDTYPE_M BIT(1)
4135 #define GLHMC_VFSDDATALOW_FPMAT_PMSDBPCOUNT_S 2
4136 #define GLHMC_VFSDDATALOW_FPMAT_PMSDBPCOUNT_M MAKEMASK(0x3FF, 2)
4137 #define GLHMC_VFSDDATALOW_FPMAT_PMSDDATALOW_S 12
4138 #define GLHMC_VFSDDATALOW_FPMAT_PMSDDATALOW_M MAKEMASK(0xFFFFF, 12)
4139 #define GLHMC_VFSDPART(_i) (0x00528800 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
4140 #define GLHMC_VFSDPART_MAX_INDEX 31
4141 #define GLHMC_VFSDPART_PMSDBASE_S 0
4142 #define GLHMC_VFSDPART_PMSDBASE_M MAKEMASK(0xFFF, 0)
4143 #define GLHMC_VFSDPART_PMSDSIZE_S 16
4144 #define GLHMC_VFSDPART_PMSDSIZE_M MAKEMASK(0x1FFF, 16)
4145 #define GLHMC_VFSDPART_FPMAT(_i) (0x00108800 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
4146 #define GLHMC_VFSDPART_FPMAT_MAX_INDEX 31
4147 #define GLHMC_VFSDPART_FPMAT_PMSDBASE_S 0
4148 #define GLHMC_VFSDPART_FPMAT_PMSDBASE_M MAKEMASK(0xFFF, 0)
4149 #define GLHMC_VFSDPART_FPMAT_PMSDSIZE_S 16
4150 #define GLHMC_VFSDPART_FPMAT_PMSDSIZE_M MAKEMASK(0x1FFF, 16)
4151 #define GLMDOC_CACHESIZE 0x0051C06C /* Reset Source: CORER */
4152 #define GLMDOC_CACHESIZE_WORD_SIZE_S 0
4153 #define GLMDOC_CACHESIZE_WORD_SIZE_M MAKEMASK(0xFF, 0)
4154 #define GLMDOC_CACHESIZE_SETS_S 8
4155 #define GLMDOC_CACHESIZE_SETS_M MAKEMASK(0xFFF, 8)
4156 #define GLMDOC_CACHESIZE_WAYS_S 20
4157 #define GLMDOC_CACHESIZE_WAYS_M MAKEMASK(0xF, 20)
4158 #define GLPBLOC0_CACHESIZE 0x00518074 /* Reset Source: CORER */
4159 #define GLPBLOC0_CACHESIZE_WORD_SIZE_S 0
4160 #define GLPBLOC0_CACHESIZE_WORD_SIZE_M MAKEMASK(0xFF, 0)
4161 #define GLPBLOC0_CACHESIZE_SETS_S 8
4162 #define GLPBLOC0_CACHESIZE_SETS_M MAKEMASK(0xFFF, 8)
4163 #define GLPBLOC0_CACHESIZE_WAYS_S 20
4164 #define GLPBLOC0_CACHESIZE_WAYS_M MAKEMASK(0xF, 20)
4165 #define GLPBLOC1_CACHESIZE 0x0051A074 /* Reset Source: CORER */
4166 #define GLPBLOC1_CACHESIZE_WORD_SIZE_S 0
4167 #define GLPBLOC1_CACHESIZE_WORD_SIZE_M MAKEMASK(0xFF, 0)
4168 #define GLPBLOC1_CACHESIZE_SETS_S 8
4169 #define GLPBLOC1_CACHESIZE_SETS_M MAKEMASK(0xFFF, 8)
4170 #define GLPBLOC1_CACHESIZE_WAYS_S 20
4171 #define GLPBLOC1_CACHESIZE_WAYS_M MAKEMASK(0xF, 20)
4172 #define GLPDOC_CACHESIZE 0x00530048 /* Reset Source: CORER */
4173 #define GLPDOC_CACHESIZE_WORD_SIZE_S 0
4174 #define GLPDOC_CACHESIZE_WORD_SIZE_M MAKEMASK(0xFF, 0)
4175 #define GLPDOC_CACHESIZE_SETS_S 8
4176 #define GLPDOC_CACHESIZE_SETS_M MAKEMASK(0xFFF, 8)
4177 #define GLPDOC_CACHESIZE_WAYS_S 20
4178 #define GLPDOC_CACHESIZE_WAYS_M MAKEMASK(0xF, 20)
4179 #define GLPDOC_CACHESIZE_FPMAT 0x00110088 /* Reset Source: CORER */
4180 #define GLPDOC_CACHESIZE_FPMAT_WORD_SIZE_S 0
4181 #define GLPDOC_CACHESIZE_FPMAT_WORD_SIZE_M MAKEMASK(0xFF, 0)
4182 #define GLPDOC_CACHESIZE_FPMAT_SETS_S 8
4183 #define GLPDOC_CACHESIZE_FPMAT_SETS_M MAKEMASK(0xFFF, 8)
4184 #define GLPDOC_CACHESIZE_FPMAT_WAYS_S 20
4185 #define GLPDOC_CACHESIZE_FPMAT_WAYS_M MAKEMASK(0xF, 20)
4186 #define GLPEOC0_CACHESIZE 0x005140A8 /* Reset Source: CORER */
4187 #define GLPEOC0_CACHESIZE_WORD_SIZE_S 0
4188 #define GLPEOC0_CACHESIZE_WORD_SIZE_M MAKEMASK(0xFF, 0)
4189 #define GLPEOC0_CACHESIZE_SETS_S 8
4190 #define GLPEOC0_CACHESIZE_SETS_M MAKEMASK(0xFFF, 8)
4191 #define GLPEOC0_CACHESIZE_WAYS_S 20
4192 #define GLPEOC0_CACHESIZE_WAYS_M MAKEMASK(0xF, 20)
4193 #define GLPEOC1_CACHESIZE 0x005160A8 /* Reset Source: CORER */
4194 #define GLPEOC1_CACHESIZE_WORD_SIZE_S 0
4195 #define GLPEOC1_CACHESIZE_WORD_SIZE_M MAKEMASK(0xFF, 0)
4196 #define GLPEOC1_CACHESIZE_SETS_S 8
4197 #define GLPEOC1_CACHESIZE_SETS_M MAKEMASK(0xFFF, 8)
4198 #define GLPEOC1_CACHESIZE_WAYS_S 20
4199 #define GLPEOC1_CACHESIZE_WAYS_M MAKEMASK(0xF, 20)
4200 #define PFHMC_ERRORDATA 0x00520500 /* Reset Source: PFR */
4201 #define PFHMC_ERRORDATA_HMC_ERROR_DATA_S 0
4202 #define PFHMC_ERRORDATA_HMC_ERROR_DATA_M MAKEMASK(0x3FFFFFFF, 0)
4203 #define PFHMC_ERRORDATA_FPMAT 0x00100500 /* Reset Source: PFR */
4204 #define PFHMC_ERRORDATA_FPMAT_HMC_ERROR_DATA_S 0
4205 #define PFHMC_ERRORDATA_FPMAT_HMC_ERROR_DATA_M MAKEMASK(0x3FFFFFFF, 0)
4206 #define PFHMC_ERRORINFO 0x00520400 /* Reset Source: PFR */
4207 #define PFHMC_ERRORINFO_PMF_INDEX_S 0
4208 #define PFHMC_ERRORINFO_PMF_INDEX_M MAKEMASK(0x1F, 0)
4209 #define PFHMC_ERRORINFO_PMF_ISVF_S 7
4210 #define PFHMC_ERRORINFO_PMF_ISVF_M BIT(7)
4211 #define PFHMC_ERRORINFO_HMC_ERROR_TYPE_S 8
4212 #define PFHMC_ERRORINFO_HMC_ERROR_TYPE_M MAKEMASK(0xF, 8)
4213 #define PFHMC_ERRORINFO_HMC_OBJECT_TYPE_S 16
4214 #define PFHMC_ERRORINFO_HMC_OBJECT_TYPE_M MAKEMASK(0x1F, 16)
4215 #define PFHMC_ERRORINFO_ERROR_DETECTED_S 31
4216 #define PFHMC_ERRORINFO_ERROR_DETECTED_M BIT(31)
4217 #define PFHMC_ERRORINFO_FPMAT 0x00100400 /* Reset Source: PFR */
4218 #define PFHMC_ERRORINFO_FPMAT_PMF_INDEX_S 0
4219 #define PFHMC_ERRORINFO_FPMAT_PMF_INDEX_M MAKEMASK(0x1F, 0)
4220 #define PFHMC_ERRORINFO_FPMAT_PMF_ISVF_S 7
4221 #define PFHMC_ERRORINFO_FPMAT_PMF_ISVF_M BIT(7)
4222 #define PFHMC_ERRORINFO_FPMAT_HMC_ERROR_TYPE_S 8
4223 #define PFHMC_ERRORINFO_FPMAT_HMC_ERROR_TYPE_M MAKEMASK(0xF, 8)
4224 #define PFHMC_ERRORINFO_FPMAT_HMC_OBJECT_TYPE_S 16
4225 #define PFHMC_ERRORINFO_FPMAT_HMC_OBJECT_TYPE_M MAKEMASK(0x1F, 16)
4226 #define PFHMC_ERRORINFO_FPMAT_ERROR_DETECTED_S 31
4227 #define PFHMC_ERRORINFO_FPMAT_ERROR_DETECTED_M BIT(31)
4228 #define PFHMC_PDINV 0x00520300 /* Reset Source: PFR */
4229 #define PFHMC_PDINV_PMSDIDX_S 0
4230 #define PFHMC_PDINV_PMSDIDX_M MAKEMASK(0xFFF, 0)
4231 #define PFHMC_PDINV_PMSDPARTSEL_S 15
4232 #define PFHMC_PDINV_PMSDPARTSEL_M BIT(15)
4233 #define PFHMC_PDINV_PMPDIDX_S 16
4234 #define PFHMC_PDINV_PMPDIDX_M MAKEMASK(0x1FF, 16)
4235 #define PFHMC_PDINV_FPMAT 0x00100300 /* Reset Source: PFR */
4236 #define PFHMC_PDINV_FPMAT_PMSDIDX_S 0
4237 #define PFHMC_PDINV_FPMAT_PMSDIDX_M MAKEMASK(0xFFF, 0)
4238 #define PFHMC_PDINV_FPMAT_PMSDPARTSEL_S 15
4239 #define PFHMC_PDINV_FPMAT_PMSDPARTSEL_M BIT(15)
4240 #define PFHMC_PDINV_FPMAT_PMPDIDX_S 16
4241 #define PFHMC_PDINV_FPMAT_PMPDIDX_M MAKEMASK(0x1FF, 16)
4242 #define PFHMC_SDCMD 0x00520000 /* Reset Source: PFR */
4243 #define PFHMC_SDCMD_PMSDIDX_S 0
4244 #define PFHMC_SDCMD_PMSDIDX_M MAKEMASK(0xFFF, 0)
4245 #define PFHMC_SDCMD_PMSDPARTSEL_S 15
4246 #define PFHMC_SDCMD_PMSDPARTSEL_M BIT(15)
4247 #define PFHMC_SDCMD_PMSDWR_S 31
4248 #define PFHMC_SDCMD_PMSDWR_M BIT(31)
4249 #define PFHMC_SDCMD_FPMAT 0x00100000 /* Reset Source: PFR */
4250 #define PFHMC_SDCMD_FPMAT_PMSDIDX_S 0
4251 #define PFHMC_SDCMD_FPMAT_PMSDIDX_M MAKEMASK(0xFFF, 0)
4252 #define PFHMC_SDCMD_FPMAT_PMSDPARTSEL_S 15
4253 #define PFHMC_SDCMD_FPMAT_PMSDPARTSEL_M BIT(15)
4254 #define PFHMC_SDCMD_FPMAT_PMSDWR_S 31
4255 #define PFHMC_SDCMD_FPMAT_PMSDWR_M BIT(31)
4256 #define PFHMC_SDDATAHIGH 0x00520200 /* Reset Source: PFR */
4257 #define PFHMC_SDDATAHIGH_PMSDDATAHIGH_S 0
4258 #define PFHMC_SDDATAHIGH_PMSDDATAHIGH_M MAKEMASK(0xFFFFFFFF, 0)
4259 #define PFHMC_SDDATAHIGH_FPMAT 0x00100200 /* Reset Source: PFR */
4260 #define PFHMC_SDDATAHIGH_FPMAT_PMSDDATAHIGH_S 0
4261 #define PFHMC_SDDATAHIGH_FPMAT_PMSDDATAHIGH_M MAKEMASK(0xFFFFFFFF, 0)
4262 #define PFHMC_SDDATALOW 0x00520100 /* Reset Source: PFR */
4263 #define PFHMC_SDDATALOW_PMSDVALID_S 0
4264 #define PFHMC_SDDATALOW_PMSDVALID_M BIT(0)
4265 #define PFHMC_SDDATALOW_PMSDTYPE_S 1
4266 #define PFHMC_SDDATALOW_PMSDTYPE_M BIT(1)
4267 #define PFHMC_SDDATALOW_PMSDBPCOUNT_S 2
4268 #define PFHMC_SDDATALOW_PMSDBPCOUNT_M MAKEMASK(0x3FF, 2)
4269 #define PFHMC_SDDATALOW_PMSDDATALOW_S 12
4270 #define PFHMC_SDDATALOW_PMSDDATALOW_M MAKEMASK(0xFFFFF, 12)
4271 #define PFHMC_SDDATALOW_FPMAT 0x00100100 /* Reset Source: PFR */
4272 #define PFHMC_SDDATALOW_FPMAT_PMSDVALID_S 0
4273 #define PFHMC_SDDATALOW_FPMAT_PMSDVALID_M BIT(0)
4274 #define PFHMC_SDDATALOW_FPMAT_PMSDTYPE_S 1
4275 #define PFHMC_SDDATALOW_FPMAT_PMSDTYPE_M BIT(1)
4276 #define PFHMC_SDDATALOW_FPMAT_PMSDBPCOUNT_S 2
4277 #define PFHMC_SDDATALOW_FPMAT_PMSDBPCOUNT_M MAKEMASK(0x3FF, 2)
4278 #define PFHMC_SDDATALOW_FPMAT_PMSDDATALOW_S 12
4279 #define PFHMC_SDDATALOW_FPMAT_PMSDDATALOW_M MAKEMASK(0xFFFFF, 12)
4280 #define GL_DSI_REPC 0x00294208 /* Reset Source: CORER */
4281 #define GL_DSI_REPC_NO_DESC_CNT_S 0
4282 #define GL_DSI_REPC_NO_DESC_CNT_M MAKEMASK(0xFFFF, 0)
4283 #define GL_DSI_REPC_ERROR_CNT_S 16
4284 #define GL_DSI_REPC_ERROR_CNT_M MAKEMASK(0xFFFF, 16)
4285 #define GL_MDCK_TDAT_TCLAN 0x000FC0DC /* Reset Source: CORER */
4286 #define GL_MDCK_TDAT_TCLAN_WRONG_ORDER_FORMAT_DESC_S 0
4287 #define GL_MDCK_TDAT_TCLAN_WRONG_ORDER_FORMAT_DESC_M BIT(0)
4288 #define GL_MDCK_TDAT_TCLAN_UR_S 1
4289 #define GL_MDCK_TDAT_TCLAN_UR_M BIT(1)
4290 #define GL_MDCK_TDAT_TCLAN_TAIL_DESC_NOT_DDESC_EOP_NOP_S 2
4291 #define GL_MDCK_TDAT_TCLAN_TAIL_DESC_NOT_DDESC_EOP_NOP_M BIT(2)
4292 #define GL_MDCK_TDAT_TCLAN_FALSE_SCHEDULING_S 3
4293 #define GL_MDCK_TDAT_TCLAN_FALSE_SCHEDULING_M BIT(3)
4294 #define GL_MDCK_TDAT_TCLAN_TAIL_VALUE_BIGGER_THAN_RING_LEN_S 4
4295 #define GL_MDCK_TDAT_TCLAN_TAIL_VALUE_BIGGER_THAN_RING_LEN_M BIT(4)
4296 #define GL_MDCK_TDAT_TCLAN_MORE_THAN_8_DCMDS_IN_PKT_S 5
4297 #define GL_MDCK_TDAT_TCLAN_MORE_THAN_8_DCMDS_IN_PKT_M BIT(5)
4298 #define GL_MDCK_TDAT_TCLAN_NO_HEAD_UPDATE_IN_QUANTA_S 6
4299 #define GL_MDCK_TDAT_TCLAN_NO_HEAD_UPDATE_IN_QUANTA_M BIT(6)
4300 #define GL_MDCK_TDAT_TCLAN_PKT_LEN_NOT_LEGAL_S 7
4301 #define GL_MDCK_TDAT_TCLAN_PKT_LEN_NOT_LEGAL_M BIT(7)
4302 #define GL_MDCK_TDAT_TCLAN_TSO_TLEN_NOT_COHERENT_WITH_SUM_BUFS_S 8
4303 #define GL_MDCK_TDAT_TCLAN_TSO_TLEN_NOT_COHERENT_WITH_SUM_BUFS_M BIT(8)
4304 #define GL_MDCK_TDAT_TCLAN_TSO_TAIL_REACHED_BEFORE_TLEN_END_S 9
4305 #define GL_MDCK_TDAT_TCLAN_TSO_TAIL_REACHED_BEFORE_TLEN_END_M BIT(9)
4306 #define GL_MDCK_TDAT_TCLAN_TSO_MORE_THAN_3_HDRS_S 10
4307 #define GL_MDCK_TDAT_TCLAN_TSO_MORE_THAN_3_HDRS_M BIT(10)
4308 #define GL_MDCK_TDAT_TCLAN_TSO_SUM_BUFFS_LT_SUM_HDRS_S 11
4309 #define GL_MDCK_TDAT_TCLAN_TSO_SUM_BUFFS_LT_SUM_HDRS_M BIT(11)
4310 #define GL_MDCK_TDAT_TCLAN_TSO_ZERO_MSS_TLEN_HDRS_S 12
4311 #define GL_MDCK_TDAT_TCLAN_TSO_ZERO_MSS_TLEN_HDRS_M BIT(12)
4312 #define GL_MDCK_TDAT_TCLAN_TSO_CTX_DESC_IPSEC_S 13
4313 #define GL_MDCK_TDAT_TCLAN_TSO_CTX_DESC_IPSEC_M BIT(13)
4314 #define GL_MDCK_TDAT_TCLAN_SSO_COMS_NOT_WHOLE_PKT_NUM_IN_QUANTA_S 14
4315 #define GL_MDCK_TDAT_TCLAN_SSO_COMS_NOT_WHOLE_PKT_NUM_IN_QUANTA_M BIT(14)
4316 #define GL_MDCK_TDAT_TCLAN_COMS_QUANTA_BYTES_EXCEED_PKTLEN_X_64_S 15
4317 #define GL_MDCK_TDAT_TCLAN_COMS_QUANTA_BYTES_EXCEED_PKTLEN_X_64_M BIT(15)
4318 #define GL_MDCK_TDAT_TCLAN_COMS_QUANTA_CMDS_EXCEED_S 16
4319 #define GL_MDCK_TDAT_TCLAN_COMS_QUANTA_CMDS_EXCEED_M BIT(16)
4320 #define GL_MDCK_TDAT_TCLAN_TSO_COMS_TSO_DESCS_LAST_LSO_QUANTA_S 17
4321 #define GL_MDCK_TDAT_TCLAN_TSO_COMS_TSO_DESCS_LAST_LSO_QUANTA_M BIT(17)
4322 #define GL_MDCK_TDAT_TCLAN_TSO_COMS_TSO_DESCS_TLEN_S 18
4323 #define GL_MDCK_TDAT_TCLAN_TSO_COMS_TSO_DESCS_TLEN_M BIT(18)
4324 #define GL_MDCK_TDAT_TCLAN_TSO_COMS_QUANTA_FINISHED_TOO_EARLY_S 19
4325 #define GL_MDCK_TDAT_TCLAN_TSO_COMS_QUANTA_FINISHED_TOO_EARLY_M BIT(19)
4326 #define GL_MDCK_TDAT_TCLAN_COMS_NUM_PKTS_IN_QUANTA_S 20
4327 #define GL_MDCK_TDAT_TCLAN_COMS_NUM_PKTS_IN_QUANTA_M BIT(20)
4328 #define GLCORE_CLKCTL_H 0x000B81E8 /* Reset Source: POR */
4329 #define GLCORE_CLKCTL_H_UPPER_CLK_SRC_H_S 0
4330 #define GLCORE_CLKCTL_H_UPPER_CLK_SRC_H_M MAKEMASK(0x3, 0)
4331 #define GLCORE_CLKCTL_H_LOWER_CLK_SRC_H_S 2
4332 #define GLCORE_CLKCTL_H_LOWER_CLK_SRC_H_M MAKEMASK(0x3, 2)
4333 #define GLCORE_CLKCTL_H_PSM_CLK_SRC_H_S 4
4334 #define GLCORE_CLKCTL_H_PSM_CLK_SRC_H_M MAKEMASK(0x3, 4)
4335 #define GLCORE_CLKCTL_H_RXCTL_CLK_SRC_H_S 6
4336 #define GLCORE_CLKCTL_H_RXCTL_CLK_SRC_H_M MAKEMASK(0x3, 6)
4337 #define GLCORE_CLKCTL_H_UANA_CLK_SRC_H_S 8
4338 #define GLCORE_CLKCTL_H_UANA_CLK_SRC_H_M MAKEMASK(0x7, 8)
4339 #define GLCORE_CLKCTL_L 0x000B8254 /* Reset Source: POR */
4340 #define GLCORE_CLKCTL_L_UPPER_CLK_SRC_L_S 0
4341 #define GLCORE_CLKCTL_L_UPPER_CLK_SRC_L_M MAKEMASK(0x3, 0)
4342 #define GLCORE_CLKCTL_L_LOWER_CLK_SRC_L_S 2
4343 #define GLCORE_CLKCTL_L_LOWER_CLK_SRC_L_M MAKEMASK(0x3, 2)
4344 #define GLCORE_CLKCTL_L_PSM_CLK_SRC_L_S 4
4345 #define GLCORE_CLKCTL_L_PSM_CLK_SRC_L_M MAKEMASK(0x3, 4)
4346 #define GLCORE_CLKCTL_L_RXCTL_CLK_SRC_L_S 6
4347 #define GLCORE_CLKCTL_L_RXCTL_CLK_SRC_L_M MAKEMASK(0x3, 6)
4348 #define GLCORE_CLKCTL_L_UANA_CLK_SRC_L_S 8
4349 #define GLCORE_CLKCTL_L_UANA_CLK_SRC_L_M MAKEMASK(0x7, 8)
4350 #define GLCORE_CLKCTL_M 0x000B8258 /* Reset Source: POR */
4351 #define GLCORE_CLKCTL_M_UPPER_CLK_SRC_M_S 0
4352 #define GLCORE_CLKCTL_M_UPPER_CLK_SRC_M_M MAKEMASK(0x3, 0)
4353 #define GLCORE_CLKCTL_M_LOWER_CLK_SRC_M_S 2
4354 #define GLCORE_CLKCTL_M_LOWER_CLK_SRC_M_M MAKEMASK(0x3, 2)
4355 #define GLCORE_CLKCTL_M_PSM_CLK_SRC_M_S 4
4356 #define GLCORE_CLKCTL_M_PSM_CLK_SRC_M_M MAKEMASK(0x3, 4)
4357 #define GLCORE_CLKCTL_M_RXCTL_CLK_SRC_M_S 6
4358 #define GLCORE_CLKCTL_M_RXCTL_CLK_SRC_M_M MAKEMASK(0x3, 6)
4359 #define GLCORE_CLKCTL_M_UANA_CLK_SRC_M_S 8
4360 #define GLCORE_CLKCTL_M_UANA_CLK_SRC_M_M MAKEMASK(0x7, 8)
4361 #define GLFOC_CACHESIZE 0x000AA074 /* Reset Source: CORER */
4362 #define GLFOC_CACHESIZE_WORD_SIZE_S 0
4363 #define GLFOC_CACHESIZE_WORD_SIZE_M MAKEMASK(0xFF, 0)
4364 #define GLFOC_CACHESIZE_SETS_S 8
4365 #define GLFOC_CACHESIZE_SETS_M MAKEMASK(0xFFF, 8)
4366 #define GLFOC_CACHESIZE_WAYS_S 20
4367 #define GLFOC_CACHESIZE_WAYS_M MAKEMASK(0xF, 20)
4368 #define GLMAC_CLKSTAT 0x000B8210 /* Reset Source: POR */
4369 #define GLMAC_CLKSTAT_P0_CLK_SPEED_S 0
4370 #define GLMAC_CLKSTAT_P0_CLK_SPEED_M MAKEMASK(0xF, 0)
4371 #define GLMAC_CLKSTAT_P1_CLK_SPEED_S 4
4372 #define GLMAC_CLKSTAT_P1_CLK_SPEED_M MAKEMASK(0xF, 4)
4373 #define GLMAC_CLKSTAT_P2_CLK_SPEED_S 8
4374 #define GLMAC_CLKSTAT_P2_CLK_SPEED_M MAKEMASK(0xF, 8)
4375 #define GLMAC_CLKSTAT_P3_CLK_SPEED_S 12
4376 #define GLMAC_CLKSTAT_P3_CLK_SPEED_M MAKEMASK(0xF, 12)
4377 #define GLMAC_CLKSTAT_P4_CLK_SPEED_S 16
4378 #define GLMAC_CLKSTAT_P4_CLK_SPEED_M MAKEMASK(0xF, 16)
4379 #define GLMAC_CLKSTAT_P5_CLK_SPEED_S 20
4380 #define GLMAC_CLKSTAT_P5_CLK_SPEED_M MAKEMASK(0xF, 20)
4381 #define GLMAC_CLKSTAT_P6_CLK_SPEED_S 24
4382 #define GLMAC_CLKSTAT_P6_CLK_SPEED_M MAKEMASK(0xF, 24)
4383 #define GLMAC_CLKSTAT_P7_CLK_SPEED_S 28
4384 #define GLMAC_CLKSTAT_P7_CLK_SPEED_M MAKEMASK(0xF, 28)
4385 #define GLTPB_100G_MAC_FC_THRESH 0x00099510 /* Reset Source: CORER */
4386 #define GLTPB_100G_MAC_FC_THRESH_PORT0_FC_THRESH_S 0
4387 #define GLTPB_100G_MAC_FC_THRESH_PORT0_FC_THRESH_M MAKEMASK(0xFFFF, 0)
4388 #define GLTPB_100G_MAC_FC_THRESH_PORT1_FC_THRESH_S 16
4389 #define GLTPB_100G_MAC_FC_THRESH_PORT1_FC_THRESH_M MAKEMASK(0xFFFF, 16)
4390 #define GLTPB_100G_RPB_FC_THRESH 0x0009963C /* Reset Source: CORER */
4391 #define GLTPB_100G_RPB_FC_THRESH_PORT0_FC_THRESH_S 0
4392 #define GLTPB_100G_RPB_FC_THRESH_PORT0_FC_THRESH_M MAKEMASK(0xFFFF, 0)
4393 #define GLTPB_100G_RPB_FC_THRESH_PORT1_FC_THRESH_S 16
4394 #define GLTPB_100G_RPB_FC_THRESH_PORT1_FC_THRESH_M MAKEMASK(0xFFFF, 16)
4395 #define GLTPB_PACING_10G 0x000994E4 /* Reset Source: CORER */
4396 #define GLTPB_PACING_10G_N_S 0
4397 #define GLTPB_PACING_10G_N_M MAKEMASK(0xFF, 0)
4398 #define GLTPB_PACING_10G_K_S 8
4399 #define GLTPB_PACING_10G_K_M MAKEMASK(0xFF, 8)
4400 #define GLTPB_PACING_10G_S_S 16
4401 #define GLTPB_PACING_10G_S_M MAKEMASK(0x1FF, 16)
4402 #define GLTPB_PACING_25G 0x000994E0 /* Reset Source: CORER */
4403 #define GLTPB_PACING_25G_N_S 0
4404 #define GLTPB_PACING_25G_N_M MAKEMASK(0xFF, 0)
4405 #define GLTPB_PACING_25G_K_S 8
4406 #define GLTPB_PACING_25G_K_M MAKEMASK(0xFF, 8)
4407 #define GLTPB_PACING_25G_S_S 16
4408 #define GLTPB_PACING_25G_S_M MAKEMASK(0x1FF, 16)
4409 #define GLTPB_PORT_PACING_SPEED 0x000994E8 /* Reset Source: CORER */
4410 #define GLTPB_PORT_PACING_SPEED_PORT0_SPEED_S 0
4411 #define GLTPB_PORT_PACING_SPEED_PORT0_SPEED_M BIT(0)
4412 #define GLTPB_PORT_PACING_SPEED_PORT1_SPEED_S 1
4413 #define GLTPB_PORT_PACING_SPEED_PORT1_SPEED_M BIT(1)
4414 #define GLTPB_PORT_PACING_SPEED_PORT2_SPEED_S 2
4415 #define GLTPB_PORT_PACING_SPEED_PORT2_SPEED_M BIT(2)
4416 #define GLTPB_PORT_PACING_SPEED_PORT3_SPEED_S 3
4417 #define GLTPB_PORT_PACING_SPEED_PORT3_SPEED_M BIT(3)
4418 #define GLTPB_PORT_PACING_SPEED_PORT4_SPEED_S 4
4419 #define GLTPB_PORT_PACING_SPEED_PORT4_SPEED_M BIT(4)
4420 #define GLTPB_PORT_PACING_SPEED_PORT5_SPEED_S 5
4421 #define GLTPB_PORT_PACING_SPEED_PORT5_SPEED_M BIT(5)
4422 #define GLTPB_PORT_PACING_SPEED_PORT6_SPEED_S 6
4423 #define GLTPB_PORT_PACING_SPEED_PORT6_SPEED_M BIT(6)
4424 #define GLTPB_PORT_PACING_SPEED_PORT7_SPEED_S 7
4425 #define GLTPB_PORT_PACING_SPEED_PORT7_SPEED_M BIT(7)
4426 #define TPB_CFG_SCHEDULED_BC_THRESHOLD 0x00099494 /* Reset Source: CORER */
4427 #define TPB_CFG_SCHEDULED_BC_THRESHOLD_THRESHOLD_S 0
4428 #define TPB_CFG_SCHEDULED_BC_THRESHOLD_THRESHOLD_M MAKEMASK(0x7FFF, 0)
4429 #define GL_UFUSE_SOC 0x000A400C /* Reset Source: POR */
4430 #define GL_UFUSE_SOC_PORT_MODE_S 0
4431 #define GL_UFUSE_SOC_PORT_MODE_M MAKEMASK(0x3, 0)
4432 #define GL_UFUSE_SOC_BANDWIDTH_S 2
4433 #define GL_UFUSE_SOC_BANDWIDTH_M MAKEMASK(0x3, 2)
4434 #define GL_UFUSE_SOC_PE_DISABLE_S 4
4435 #define GL_UFUSE_SOC_PE_DISABLE_M BIT(4)
4436 #define GL_UFUSE_SOC_SWITCH_MODE_S 5
4437 #define GL_UFUSE_SOC_SWITCH_MODE_M BIT(5)
4438 #define GL_UFUSE_SOC_CSR_PROTECTION_ENABLE_S 6
4439 #define GL_UFUSE_SOC_CSR_PROTECTION_ENABLE_M BIT(6)
4440 #define GL_UFUSE_SOC_SERIAL_50G_S 7
4441 #define GL_UFUSE_SOC_SERIAL_50G_M BIT(7)
4442 #define GL_UFUSE_SOC_NIC_ID_S 8
4443 #define GL_UFUSE_SOC_NIC_ID_M BIT(8)
4444 #define GL_UFUSE_SOC_BLOCK_BME_TO_FW_S 9
4445 #define GL_UFUSE_SOC_BLOCK_BME_TO_FW_M BIT(9)
4446 #define GL_UFUSE_SOC_SOC_TYPE_S 10
4447 #define GL_UFUSE_SOC_SOC_TYPE_M BIT(10)
4448 #define GL_UFUSE_SOC_BTS_MODE_S 11
4449 #define GL_UFUSE_SOC_BTS_MODE_M BIT(11)
4450 #define GL_UFUSE_SOC_SPARE_FUSES_S 12
4451 #define GL_UFUSE_SOC_SPARE_FUSES_M MAKEMASK(0xF, 12)
4452 #define EMPINT_GPIO_ENA 0x000880C0 /* Reset Source: POR */
4453 #define EMPINT_GPIO_ENA_GPIO0_ENA_S 0
4454 #define EMPINT_GPIO_ENA_GPIO0_ENA_M BIT(0)
4455 #define EMPINT_GPIO_ENA_GPIO1_ENA_S 1
4456 #define EMPINT_GPIO_ENA_GPIO1_ENA_M BIT(1)
4457 #define EMPINT_GPIO_ENA_GPIO2_ENA_S 2
4458 #define EMPINT_GPIO_ENA_GPIO2_ENA_M BIT(2)
4459 #define EMPINT_GPIO_ENA_GPIO3_ENA_S 3
4460 #define EMPINT_GPIO_ENA_GPIO3_ENA_M BIT(3)
4461 #define EMPINT_GPIO_ENA_GPIO4_ENA_S 4
4462 #define EMPINT_GPIO_ENA_GPIO4_ENA_M BIT(4)
4463 #define EMPINT_GPIO_ENA_GPIO5_ENA_S 5
4464 #define EMPINT_GPIO_ENA_GPIO5_ENA_M BIT(5)
4465 #define EMPINT_GPIO_ENA_GPIO6_ENA_S 6
4466 #define EMPINT_GPIO_ENA_GPIO6_ENA_M BIT(6)
4467 #define GLGEN_MAC_LINK_TOPO 0x000B81DC /* Reset Source: GLOBR */
4468 #define GLGEN_MAC_LINK_TOPO_LINK_TOPO_S 0
4469 #define GLGEN_MAC_LINK_TOPO_LINK_TOPO_M MAKEMASK(0x3, 0)
4470 #define GLINT_CEQCTL(_INT) (0x0015C000 + ((_INT) * 4)) /* _i=0...2047 */ /* Reset Source: CORER */
4471 #define GLINT_CEQCTL_MAX_INDEX 2047
4472 #define GLINT_CEQCTL_MSIX_INDX_S 0
4473 #define GLINT_CEQCTL_MSIX_INDX_M MAKEMASK(0x7FF, 0)
4474 #define GLINT_CEQCTL_ITR_INDX_S 11
4475 #define GLINT_CEQCTL_ITR_INDX_M MAKEMASK(0x3, 11)
4476 #define GLINT_CEQCTL_CAUSE_ENA_S 30
4477 #define GLINT_CEQCTL_CAUSE_ENA_M BIT(30)
4478 #define GLINT_CEQCTL_INTEVENT_S 31
4479 #define GLINT_CEQCTL_INTEVENT_M BIT(31)
4480 #define GLINT_CTL 0x0016CC54 /* Reset Source: CORER */
4481 #define GLINT_CTL_DIS_AUTOMASK_S 0
4482 #define GLINT_CTL_DIS_AUTOMASK_M BIT(0)
4483 #define GLINT_CTL_RSVD_S 1
4484 #define GLINT_CTL_RSVD_M MAKEMASK(0x7FFF, 1)
4485 #define GLINT_CTL_ITR_GRAN_200_S 16
4486 #define GLINT_CTL_ITR_GRAN_200_M MAKEMASK(0xF, 16)
4487 #define GLINT_CTL_ITR_GRAN_100_S 20
4488 #define GLINT_CTL_ITR_GRAN_100_M MAKEMASK(0xF, 20)
4489 #define GLINT_CTL_ITR_GRAN_50_S 24
4490 #define GLINT_CTL_ITR_GRAN_50_M MAKEMASK(0xF, 24)
4491 #define GLINT_CTL_ITR_GRAN_25_S 28
4492 #define GLINT_CTL_ITR_GRAN_25_M MAKEMASK(0xF, 28)
4493 #define GLINT_DYN_CTL(_INT) (0x00160000 + ((_INT) * 4)) /* _i=0...2047 */ /* Reset Source: CORER */
4494 #define GLINT_DYN_CTL_MAX_INDEX 2047
4495 #define GLINT_DYN_CTL_INTENA_S 0
4496 #define GLINT_DYN_CTL_INTENA_M BIT(0)
4497 #define GLINT_DYN_CTL_CLEARPBA_S 1
4498 #define GLINT_DYN_CTL_CLEARPBA_M BIT(1)
4499 #define GLINT_DYN_CTL_SWINT_TRIG_S 2
4500 #define GLINT_DYN_CTL_SWINT_TRIG_M BIT(2)
4501 #define GLINT_DYN_CTL_ITR_INDX_S 3
4502 #define GLINT_DYN_CTL_ITR_INDX_M MAKEMASK(0x3, 3)
4503 #define GLINT_DYN_CTL_INTERVAL_S 5
4504 #define GLINT_DYN_CTL_INTERVAL_M MAKEMASK(0xFFF, 5)
4505 #define GLINT_DYN_CTL_SW_ITR_INDX_ENA_S 24
4506 #define GLINT_DYN_CTL_SW_ITR_INDX_ENA_M BIT(24)
4507 #define GLINT_DYN_CTL_SW_ITR_INDX_S 25
4508 #define GLINT_DYN_CTL_SW_ITR_INDX_M MAKEMASK(0x3, 25)
4509 #define GLINT_DYN_CTL_WB_ON_ITR_S 30
4510 #define GLINT_DYN_CTL_WB_ON_ITR_M BIT(30)
4511 #define GLINT_DYN_CTL_INTENA_MSK_S 31
4512 #define GLINT_DYN_CTL_INTENA_MSK_M BIT(31)
4513 #define GLINT_FW_TOOL_CTL 0x0016C840 /* Reset Source: CORER */
4514 #define GLINT_FW_TOOL_CTL_MSIX_INDX_S 0
4515 #define GLINT_FW_TOOL_CTL_MSIX_INDX_M MAKEMASK(0x7FF, 0)
4516 #define GLINT_FW_TOOL_CTL_ITR_INDX_S 11
4517 #define GLINT_FW_TOOL_CTL_ITR_INDX_M MAKEMASK(0x3, 11)
4518 #define GLINT_FW_TOOL_CTL_CAUSE_ENA_S 30
4519 #define GLINT_FW_TOOL_CTL_CAUSE_ENA_M BIT(30)
4520 #define GLINT_FW_TOOL_CTL_INTEVENT_S 31
4521 #define GLINT_FW_TOOL_CTL_INTEVENT_M BIT(31)
4522 #define GLINT_ITR(_i, _INT) (0x00154000 + ((_i) * 8192 + (_INT) * 4)) /* _i=0...2, _INT=0...2047 */ /* Reset Source: CORER */
4523 #define GLINT_ITR_MAX_INDEX 2
4524 #define GLINT_ITR_INTERVAL_S 0
4525 #define GLINT_ITR_INTERVAL_M MAKEMASK(0xFFF, 0)
4526 #define GLINT_RATE(_INT) (0x0015A000 + ((_INT) * 4)) /* _i=0...2047 */ /* Reset Source: CORER */
4527 #define GLINT_RATE_MAX_INDEX 2047
4528 #define GLINT_RATE_INTERVAL_S 0
4529 #define GLINT_RATE_INTERVAL_M MAKEMASK(0x3F, 0)
4530 #define GLINT_RATE_INTRL_ENA_S 6
4531 #define GLINT_RATE_INTRL_ENA_M BIT(6)
4532 #define GLINT_TSYN_PFMSTR(_i) (0x0016CCC0 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */
4533 #define GLINT_TSYN_PFMSTR_MAX_INDEX 1
4534 #define GLINT_TSYN_PFMSTR_PF_MASTER_S 0
4535 #define GLINT_TSYN_PFMSTR_PF_MASTER_M MAKEMASK(0x7, 0)
4536 #define GLINT_TSYN_PHY 0x0016CC50 /* Reset Source: CORER */
4537 #define GLINT_TSYN_PHY_PHY_INDX_S 0
4538 #define GLINT_TSYN_PHY_PHY_INDX_M MAKEMASK(0x1F, 0)
4539 #define GLINT_VECT2FUNC(_INT) (0x00162000 + ((_INT) * 4)) /* _i=0...2047 */ /* Reset Source: CORER */
4540 #define GLINT_VECT2FUNC_MAX_INDEX 2047
4541 #define GLINT_VECT2FUNC_VF_NUM_S 0
4542 #define GLINT_VECT2FUNC_VF_NUM_M MAKEMASK(0xFF, 0)
4543 #define GLINT_VECT2FUNC_PF_NUM_S 12
4544 #define GLINT_VECT2FUNC_PF_NUM_M MAKEMASK(0x7, 12)
4545 #define GLINT_VECT2FUNC_IS_PF_S 16
4546 #define GLINT_VECT2FUNC_IS_PF_M BIT(16)
4547 #define PF0INT_FW_HLP_CTL 0x0016C844 /* Reset Source: CORER */
4548 #define PF0INT_FW_HLP_CTL_MSIX_INDX_S 0
4549 #define PF0INT_FW_HLP_CTL_MSIX_INDX_M MAKEMASK(0x7FF, 0)
4550 #define PF0INT_FW_HLP_CTL_ITR_INDX_S 11
4551 #define PF0INT_FW_HLP_CTL_ITR_INDX_M MAKEMASK(0x3, 11)
4552 #define PF0INT_FW_HLP_CTL_CAUSE_ENA_S 30
4553 #define PF0INT_FW_HLP_CTL_CAUSE_ENA_M BIT(30)
4554 #define PF0INT_FW_HLP_CTL_INTEVENT_S 31
4555 #define PF0INT_FW_HLP_CTL_INTEVENT_M BIT(31)
4556 #define PF0INT_FW_PSM_CTL 0x0016C848 /* Reset Source: CORER */
4557 #define PF0INT_FW_PSM_CTL_MSIX_INDX_S 0
4558 #define PF0INT_FW_PSM_CTL_MSIX_INDX_M MAKEMASK(0x7FF, 0)
4559 #define PF0INT_FW_PSM_CTL_ITR_INDX_S 11
4560 #define PF0INT_FW_PSM_CTL_ITR_INDX_M MAKEMASK(0x3, 11)
4561 #define PF0INT_FW_PSM_CTL_CAUSE_ENA_S 30
4562 #define PF0INT_FW_PSM_CTL_CAUSE_ENA_M BIT(30)
4563 #define PF0INT_FW_PSM_CTL_INTEVENT_S 31
4564 #define PF0INT_FW_PSM_CTL_INTEVENT_M BIT(31)
4565 #define PF0INT_MBX_CPM_CTL 0x0016B2C0 /* Reset Source: CORER */
4566 #define PF0INT_MBX_CPM_CTL_MSIX_INDX_S 0
4567 #define PF0INT_MBX_CPM_CTL_MSIX_INDX_M MAKEMASK(0x7FF, 0)
4568 #define PF0INT_MBX_CPM_CTL_ITR_INDX_S 11
4569 #define PF0INT_MBX_CPM_CTL_ITR_INDX_M MAKEMASK(0x3, 11)
4570 #define PF0INT_MBX_CPM_CTL_CAUSE_ENA_S 30
4571 #define PF0INT_MBX_CPM_CTL_CAUSE_ENA_M BIT(30)
4572 #define PF0INT_MBX_CPM_CTL_INTEVENT_S 31
4573 #define PF0INT_MBX_CPM_CTL_INTEVENT_M BIT(31)
4574 #define PF0INT_MBX_HLP_CTL 0x0016B2C4 /* Reset Source: CORER */
4575 #define PF0INT_MBX_HLP_CTL_MSIX_INDX_S 0
4576 #define PF0INT_MBX_HLP_CTL_MSIX_INDX_M MAKEMASK(0x7FF, 0)
4577 #define PF0INT_MBX_HLP_CTL_ITR_INDX_S 11
4578 #define PF0INT_MBX_HLP_CTL_ITR_INDX_M MAKEMASK(0x3, 11)
4579 #define PF0INT_MBX_HLP_CTL_CAUSE_ENA_S 30
4580 #define PF0INT_MBX_HLP_CTL_CAUSE_ENA_M BIT(30)
4581 #define PF0INT_MBX_HLP_CTL_INTEVENT_S 31
4582 #define PF0INT_MBX_HLP_CTL_INTEVENT_M BIT(31)
4583 #define PF0INT_MBX_PSM_CTL 0x0016B2C8 /* Reset Source: CORER */
4584 #define PF0INT_MBX_PSM_CTL_MSIX_INDX_S 0
4585 #define PF0INT_MBX_PSM_CTL_MSIX_INDX_M MAKEMASK(0x7FF, 0)
4586 #define PF0INT_MBX_PSM_CTL_ITR_INDX_S 11
4587 #define PF0INT_MBX_PSM_CTL_ITR_INDX_M MAKEMASK(0x3, 11)
4588 #define PF0INT_MBX_PSM_CTL_CAUSE_ENA_S 30
4589 #define PF0INT_MBX_PSM_CTL_CAUSE_ENA_M BIT(30)
4590 #define PF0INT_MBX_PSM_CTL_INTEVENT_S 31
4591 #define PF0INT_MBX_PSM_CTL_INTEVENT_M BIT(31)
4592 #define PF0INT_OICR_CPM 0x0016CC40 /* Reset Source: CORER */
4593 #define PF0INT_OICR_CPM_INTEVENT_S 0
4594 #define PF0INT_OICR_CPM_INTEVENT_M BIT(0)
4595 #define PF0INT_OICR_CPM_QUEUE_S 1
4596 #define PF0INT_OICR_CPM_QUEUE_M BIT(1)
4597 #define PF0INT_OICR_CPM_RSV1_S 2
4598 #define PF0INT_OICR_CPM_RSV1_M MAKEMASK(0xFF, 2)
4599 #define PF0INT_OICR_CPM_HH_COMP_S 10
4600 #define PF0INT_OICR_CPM_HH_COMP_M BIT(10)
4601 #define PF0INT_OICR_CPM_TSYN_TX_S 11
4602 #define PF0INT_OICR_CPM_TSYN_TX_M BIT(11)
4603 #define PF0INT_OICR_CPM_TSYN_EVNT_S 12
4604 #define PF0INT_OICR_CPM_TSYN_EVNT_M BIT(12)
4605 #define PF0INT_OICR_CPM_TSYN_TGT_S 13
4606 #define PF0INT_OICR_CPM_TSYN_TGT_M BIT(13)
4607 #define PF0INT_OICR_CPM_HLP_RDY_S 14
4608 #define PF0INT_OICR_CPM_HLP_RDY_M BIT(14)
4609 #define PF0INT_OICR_CPM_CPM_RDY_S 15
4610 #define PF0INT_OICR_CPM_CPM_RDY_M BIT(15)
4611 #define PF0INT_OICR_CPM_ECC_ERR_S 16
4612 #define PF0INT_OICR_CPM_ECC_ERR_M BIT(16)
4613 #define PF0INT_OICR_CPM_RSV2_S 17
4614 #define PF0INT_OICR_CPM_RSV2_M MAKEMASK(0x3, 17)
4615 #define PF0INT_OICR_CPM_MAL_DETECT_S 19
4616 #define PF0INT_OICR_CPM_MAL_DETECT_M BIT(19)
4617 #define PF0INT_OICR_CPM_GRST_S 20
4618 #define PF0INT_OICR_CPM_GRST_M BIT(20)
4619 #define PF0INT_OICR_CPM_PCI_EXCEPTION_S 21
4620 #define PF0INT_OICR_CPM_PCI_EXCEPTION_M BIT(21)
4621 #define PF0INT_OICR_CPM_GPIO_S 22
4622 #define PF0INT_OICR_CPM_GPIO_M BIT(22)
4623 #define PF0INT_OICR_CPM_RSV3_S 23
4624 #define PF0INT_OICR_CPM_RSV3_M BIT(23)
4625 #define PF0INT_OICR_CPM_STORM_DETECT_S 24
4626 #define PF0INT_OICR_CPM_STORM_DETECT_M BIT(24)
4627 #define PF0INT_OICR_CPM_LINK_STAT_CHANGE_S 25
4628 #define PF0INT_OICR_CPM_LINK_STAT_CHANGE_M BIT(25)
4629 #define PF0INT_OICR_CPM_HMC_ERR_S 26
4630 #define PF0INT_OICR_CPM_HMC_ERR_M BIT(26)
4631 #define PF0INT_OICR_CPM_PE_PUSH_S 27
4632 #define PF0INT_OICR_CPM_PE_PUSH_M BIT(27)
4633 #define PF0INT_OICR_CPM_PE_CRITERR_S 28
4634 #define PF0INT_OICR_CPM_PE_CRITERR_M BIT(28)
4635 #define PF0INT_OICR_CPM_VFLR_S 29
4636 #define PF0INT_OICR_CPM_VFLR_M BIT(29)
4637 #define PF0INT_OICR_CPM_XLR_HW_DONE_S 30
4638 #define PF0INT_OICR_CPM_XLR_HW_DONE_M BIT(30)
4639 #define PF0INT_OICR_CPM_SWINT_S 31
4640 #define PF0INT_OICR_CPM_SWINT_M BIT(31)
4641 #define PF0INT_OICR_CTL_CPM 0x0016CC48 /* Reset Source: CORER */
4642 #define PF0INT_OICR_CTL_CPM_MSIX_INDX_S 0
4643 #define PF0INT_OICR_CTL_CPM_MSIX_INDX_M MAKEMASK(0x7FF, 0)
4644 #define PF0INT_OICR_CTL_CPM_ITR_INDX_S 11
4645 #define PF0INT_OICR_CTL_CPM_ITR_INDX_M MAKEMASK(0x3, 11)
4646 #define PF0INT_OICR_CTL_CPM_CAUSE_ENA_S 30
4647 #define PF0INT_OICR_CTL_CPM_CAUSE_ENA_M BIT(30)
4648 #define PF0INT_OICR_CTL_CPM_INTEVENT_S 31
4649 #define PF0INT_OICR_CTL_CPM_INTEVENT_M BIT(31)
4650 #define PF0INT_OICR_CTL_HLP 0x0016CC5C /* Reset Source: CORER */
4651 #define PF0INT_OICR_CTL_HLP_MSIX_INDX_S 0
4652 #define PF0INT_OICR_CTL_HLP_MSIX_INDX_M MAKEMASK(0x7FF, 0)
4653 #define PF0INT_OICR_CTL_HLP_ITR_INDX_S 11
4654 #define PF0INT_OICR_CTL_HLP_ITR_INDX_M MAKEMASK(0x3, 11)
4655 #define PF0INT_OICR_CTL_HLP_CAUSE_ENA_S 30
4656 #define PF0INT_OICR_CTL_HLP_CAUSE_ENA_M BIT(30)
4657 #define PF0INT_OICR_CTL_HLP_INTEVENT_S 31
4658 #define PF0INT_OICR_CTL_HLP_INTEVENT_M BIT(31)
4659 #define PF0INT_OICR_CTL_PSM 0x0016CC64 /* Reset Source: CORER */
4660 #define PF0INT_OICR_CTL_PSM_MSIX_INDX_S 0
4661 #define PF0INT_OICR_CTL_PSM_MSIX_INDX_M MAKEMASK(0x7FF, 0)
4662 #define PF0INT_OICR_CTL_PSM_ITR_INDX_S 11
4663 #define PF0INT_OICR_CTL_PSM_ITR_INDX_M MAKEMASK(0x3, 11)
4664 #define PF0INT_OICR_CTL_PSM_CAUSE_ENA_S 30
4665 #define PF0INT_OICR_CTL_PSM_CAUSE_ENA_M BIT(30)
4666 #define PF0INT_OICR_CTL_PSM_INTEVENT_S 31
4667 #define PF0INT_OICR_CTL_PSM_INTEVENT_M BIT(31)
4668 #define PF0INT_OICR_ENA_CPM 0x0016CC60 /* Reset Source: CORER */
4669 #define PF0INT_OICR_ENA_CPM_RSV0_S 0
4670 #define PF0INT_OICR_ENA_CPM_RSV0_M BIT(0)
4671 #define PF0INT_OICR_ENA_CPM_INT_ENA_S 1
4672 #define PF0INT_OICR_ENA_CPM_INT_ENA_M MAKEMASK(0x7FFFFFFF, 1)
4673 #define PF0INT_OICR_ENA_HLP 0x0016CC4C /* Reset Source: CORER */
4674 #define PF0INT_OICR_ENA_HLP_RSV0_S 0
4675 #define PF0INT_OICR_ENA_HLP_RSV0_M BIT(0)
4676 #define PF0INT_OICR_ENA_HLP_INT_ENA_S 1
4677 #define PF0INT_OICR_ENA_HLP_INT_ENA_M MAKEMASK(0x7FFFFFFF, 1)
4678 #define PF0INT_OICR_ENA_PSM 0x0016CC58 /* Reset Source: CORER */
4679 #define PF0INT_OICR_ENA_PSM_RSV0_S 0
4680 #define PF0INT_OICR_ENA_PSM_RSV0_M BIT(0)
4681 #define PF0INT_OICR_ENA_PSM_INT_ENA_S 1
4682 #define PF0INT_OICR_ENA_PSM_INT_ENA_M MAKEMASK(0x7FFFFFFF, 1)
4683 #define PF0INT_OICR_HLP 0x0016CC68 /* Reset Source: CORER */
4684 #define PF0INT_OICR_HLP_INTEVENT_S 0
4685 #define PF0INT_OICR_HLP_INTEVENT_M BIT(0)
4686 #define PF0INT_OICR_HLP_QUEUE_S 1
4687 #define PF0INT_OICR_HLP_QUEUE_M BIT(1)
4688 #define PF0INT_OICR_HLP_RSV1_S 2
4689 #define PF0INT_OICR_HLP_RSV1_M MAKEMASK(0xFF, 2)
4690 #define PF0INT_OICR_HLP_HH_COMP_S 10
4691 #define PF0INT_OICR_HLP_HH_COMP_M BIT(10)
4692 #define PF0INT_OICR_HLP_TSYN_TX_S 11
4693 #define PF0INT_OICR_HLP_TSYN_TX_M BIT(11)
4694 #define PF0INT_OICR_HLP_TSYN_EVNT_S 12
4695 #define PF0INT_OICR_HLP_TSYN_EVNT_M BIT(12)
4696 #define PF0INT_OICR_HLP_TSYN_TGT_S 13
4697 #define PF0INT_OICR_HLP_TSYN_TGT_M BIT(13)
4698 #define PF0INT_OICR_HLP_HLP_RDY_S 14
4699 #define PF0INT_OICR_HLP_HLP_RDY_M BIT(14)
4700 #define PF0INT_OICR_HLP_CPM_RDY_S 15
4701 #define PF0INT_OICR_HLP_CPM_RDY_M BIT(15)
4702 #define PF0INT_OICR_HLP_ECC_ERR_S 16
4703 #define PF0INT_OICR_HLP_ECC_ERR_M BIT(16)
4704 #define PF0INT_OICR_HLP_RSV2_S 17
4705 #define PF0INT_OICR_HLP_RSV2_M MAKEMASK(0x3, 17)
4706 #define PF0INT_OICR_HLP_MAL_DETECT_S 19
4707 #define PF0INT_OICR_HLP_MAL_DETECT_M BIT(19)
4708 #define PF0INT_OICR_HLP_GRST_S 20
4709 #define PF0INT_OICR_HLP_GRST_M BIT(20)
4710 #define PF0INT_OICR_HLP_PCI_EXCEPTION_S 21
4711 #define PF0INT_OICR_HLP_PCI_EXCEPTION_M BIT(21)
4712 #define PF0INT_OICR_HLP_GPIO_S 22
4713 #define PF0INT_OICR_HLP_GPIO_M BIT(22)
4714 #define PF0INT_OICR_HLP_RSV3_S 23
4715 #define PF0INT_OICR_HLP_RSV3_M BIT(23)
4716 #define PF0INT_OICR_HLP_STORM_DETECT_S 24
4717 #define PF0INT_OICR_HLP_STORM_DETECT_M BIT(24)
4718 #define PF0INT_OICR_HLP_LINK_STAT_CHANGE_S 25
4719 #define PF0INT_OICR_HLP_LINK_STAT_CHANGE_M BIT(25)
4720 #define PF0INT_OICR_HLP_HMC_ERR_S 26
4721 #define PF0INT_OICR_HLP_HMC_ERR_M BIT(26)
4722 #define PF0INT_OICR_HLP_PE_PUSH_S 27
4723 #define PF0INT_OICR_HLP_PE_PUSH_M BIT(27)
4724 #define PF0INT_OICR_HLP_PE_CRITERR_S 28
4725 #define PF0INT_OICR_HLP_PE_CRITERR_M BIT(28)
4726 #define PF0INT_OICR_HLP_VFLR_S 29
4727 #define PF0INT_OICR_HLP_VFLR_M BIT(29)
4728 #define PF0INT_OICR_HLP_XLR_HW_DONE_S 30
4729 #define PF0INT_OICR_HLP_XLR_HW_DONE_M BIT(30)
4730 #define PF0INT_OICR_HLP_SWINT_S 31
4731 #define PF0INT_OICR_HLP_SWINT_M BIT(31)
4732 #define PF0INT_OICR_PSM 0x0016CC44 /* Reset Source: CORER */
4733 #define PF0INT_OICR_PSM_INTEVENT_S 0
4734 #define PF0INT_OICR_PSM_INTEVENT_M BIT(0)
4735 #define PF0INT_OICR_PSM_QUEUE_S 1
4736 #define PF0INT_OICR_PSM_QUEUE_M BIT(1)
4737 #define PF0INT_OICR_PSM_RSV1_S 2
4738 #define PF0INT_OICR_PSM_RSV1_M MAKEMASK(0xFF, 2)
4739 #define PF0INT_OICR_PSM_HH_COMP_S 10
4740 #define PF0INT_OICR_PSM_HH_COMP_M BIT(10)
4741 #define PF0INT_OICR_PSM_TSYN_TX_S 11
4742 #define PF0INT_OICR_PSM_TSYN_TX_M BIT(11)
4743 #define PF0INT_OICR_PSM_TSYN_EVNT_S 12
4744 #define PF0INT_OICR_PSM_TSYN_EVNT_M BIT(12)
4745 #define PF0INT_OICR_PSM_TSYN_TGT_S 13
4746 #define PF0INT_OICR_PSM_TSYN_TGT_M BIT(13)
4747 #define PF0INT_OICR_PSM_HLP_RDY_S 14
4748 #define PF0INT_OICR_PSM_HLP_RDY_M BIT(14)
4749 #define PF0INT_OICR_PSM_CPM_RDY_S 15
4750 #define PF0INT_OICR_PSM_CPM_RDY_M BIT(15)
4751 #define PF0INT_OICR_PSM_ECC_ERR_S 16
4752 #define PF0INT_OICR_PSM_ECC_ERR_M BIT(16)
4753 #define PF0INT_OICR_PSM_RSV2_S 17
4754 #define PF0INT_OICR_PSM_RSV2_M MAKEMASK(0x3, 17)
4755 #define PF0INT_OICR_PSM_MAL_DETECT_S 19
4756 #define PF0INT_OICR_PSM_MAL_DETECT_M BIT(19)
4757 #define PF0INT_OICR_PSM_GRST_S 20
4758 #define PF0INT_OICR_PSM_GRST_M BIT(20)
4759 #define PF0INT_OICR_PSM_PCI_EXCEPTION_S 21
4760 #define PF0INT_OICR_PSM_PCI_EXCEPTION_M BIT(21)
4761 #define PF0INT_OICR_PSM_GPIO_S 22
4762 #define PF0INT_OICR_PSM_GPIO_M BIT(22)
4763 #define PF0INT_OICR_PSM_RSV3_S 23
4764 #define PF0INT_OICR_PSM_RSV3_M BIT(23)
4765 #define PF0INT_OICR_PSM_STORM_DETECT_S 24
4766 #define PF0INT_OICR_PSM_STORM_DETECT_M BIT(24)
4767 #define PF0INT_OICR_PSM_LINK_STAT_CHANGE_S 25
4768 #define PF0INT_OICR_PSM_LINK_STAT_CHANGE_M BIT(25)
4769 #define PF0INT_OICR_PSM_HMC_ERR_S 26
4770 #define PF0INT_OICR_PSM_HMC_ERR_M BIT(26)
4771 #define PF0INT_OICR_PSM_PE_PUSH_S 27
4772 #define PF0INT_OICR_PSM_PE_PUSH_M BIT(27)
4773 #define PF0INT_OICR_PSM_PE_CRITERR_S 28
4774 #define PF0INT_OICR_PSM_PE_CRITERR_M BIT(28)
4775 #define PF0INT_OICR_PSM_VFLR_S 29
4776 #define PF0INT_OICR_PSM_VFLR_M BIT(29)
4777 #define PF0INT_OICR_PSM_XLR_HW_DONE_S 30
4778 #define PF0INT_OICR_PSM_XLR_HW_DONE_M BIT(30)
4779 #define PF0INT_OICR_PSM_SWINT_S 31
4780 #define PF0INT_OICR_PSM_SWINT_M BIT(31)
4781 #define PF0INT_SB_CPM_CTL 0x0016B2CC /* Reset Source: CORER */
4782 #define PF0INT_SB_CPM_CTL_MSIX_INDX_S 0
4783 #define PF0INT_SB_CPM_CTL_MSIX_INDX_M MAKEMASK(0x7FF, 0)
4784 #define PF0INT_SB_CPM_CTL_ITR_INDX_S 11
4785 #define PF0INT_SB_CPM_CTL_ITR_INDX_M MAKEMASK(0x3, 11)
4786 #define PF0INT_SB_CPM_CTL_CAUSE_ENA_S 30
4787 #define PF0INT_SB_CPM_CTL_CAUSE_ENA_M BIT(30)
4788 #define PF0INT_SB_CPM_CTL_INTEVENT_S 31
4789 #define PF0INT_SB_CPM_CTL_INTEVENT_M BIT(31)
4790 #define PF0INT_SB_HLP_CTL 0x0016B640 /* Reset Source: CORER */
4791 #define PF0INT_SB_HLP_CTL_MSIX_INDX_S 0
4792 #define PF0INT_SB_HLP_CTL_MSIX_INDX_M MAKEMASK(0x7FF, 0)
4793 #define PF0INT_SB_HLP_CTL_ITR_INDX_S 11
4794 #define PF0INT_SB_HLP_CTL_ITR_INDX_M MAKEMASK(0x3, 11)
4795 #define PF0INT_SB_HLP_CTL_CAUSE_ENA_S 30
4796 #define PF0INT_SB_HLP_CTL_CAUSE_ENA_M BIT(30)
4797 #define PF0INT_SB_HLP_CTL_INTEVENT_S 31
4798 #define PF0INT_SB_HLP_CTL_INTEVENT_M BIT(31)
4799 #define PFINT_AEQCTL 0x0016CB00 /* Reset Source: CORER */
4800 #define PFINT_AEQCTL_MSIX_INDX_S 0
4801 #define PFINT_AEQCTL_MSIX_INDX_M MAKEMASK(0x7FF, 0)
4802 #define PFINT_AEQCTL_ITR_INDX_S 11
4803 #define PFINT_AEQCTL_ITR_INDX_M MAKEMASK(0x3, 11)
4804 #define PFINT_AEQCTL_CAUSE_ENA_S 30
4805 #define PFINT_AEQCTL_CAUSE_ENA_M BIT(30)
4806 #define PFINT_AEQCTL_INTEVENT_S 31
4807 #define PFINT_AEQCTL_INTEVENT_M BIT(31)
4808 #define PFINT_ALLOC 0x001D2600 /* Reset Source: CORER */
4809 #define PFINT_ALLOC_FIRST_S 0
4810 #define PFINT_ALLOC_FIRST_M MAKEMASK(0x7FF, 0)
4811 #define PFINT_ALLOC_LAST_S 12
4812 #define PFINT_ALLOC_LAST_M MAKEMASK(0x7FF, 12)
4813 #define PFINT_ALLOC_VALID_S 31
4814 #define PFINT_ALLOC_VALID_M BIT(31)
4815 #define PFINT_ALLOC_PCI 0x0009D800 /* Reset Source: PCIR */
4816 #define PFINT_ALLOC_PCI_FIRST_S 0
4817 #define PFINT_ALLOC_PCI_FIRST_M MAKEMASK(0x7FF, 0)
4818 #define PFINT_ALLOC_PCI_LAST_S 12
4819 #define PFINT_ALLOC_PCI_LAST_M MAKEMASK(0x7FF, 12)
4820 #define PFINT_ALLOC_PCI_VALID_S 31
4821 #define PFINT_ALLOC_PCI_VALID_M BIT(31)
4822 #define PFINT_FW_CTL 0x0016C800 /* Reset Source: CORER */
4823 #define PFINT_FW_CTL_MSIX_INDX_S 0
4824 #define PFINT_FW_CTL_MSIX_INDX_M MAKEMASK(0x7FF, 0)
4825 #define PFINT_FW_CTL_ITR_INDX_S 11
4826 #define PFINT_FW_CTL_ITR_INDX_M MAKEMASK(0x3, 11)
4827 #define PFINT_FW_CTL_CAUSE_ENA_S 30
4828 #define PFINT_FW_CTL_CAUSE_ENA_M BIT(30)
4829 #define PFINT_FW_CTL_INTEVENT_S 31
4830 #define PFINT_FW_CTL_INTEVENT_M BIT(31)
4831 #define PFINT_GPIO_ENA 0x00088080 /* Reset Source: CORER */
4832 #define PFINT_GPIO_ENA_GPIO0_ENA_S 0
4833 #define PFINT_GPIO_ENA_GPIO0_ENA_M BIT(0)
4834 #define PFINT_GPIO_ENA_GPIO1_ENA_S 1
4835 #define PFINT_GPIO_ENA_GPIO1_ENA_M BIT(1)
4836 #define PFINT_GPIO_ENA_GPIO2_ENA_S 2
4837 #define PFINT_GPIO_ENA_GPIO2_ENA_M BIT(2)
4838 #define PFINT_GPIO_ENA_GPIO3_ENA_S 3
4839 #define PFINT_GPIO_ENA_GPIO3_ENA_M BIT(3)
4840 #define PFINT_GPIO_ENA_GPIO4_ENA_S 4
4841 #define PFINT_GPIO_ENA_GPIO4_ENA_M BIT(4)
4842 #define PFINT_GPIO_ENA_GPIO5_ENA_S 5
4843 #define PFINT_GPIO_ENA_GPIO5_ENA_M BIT(5)
4844 #define PFINT_GPIO_ENA_GPIO6_ENA_S 6
4845 #define PFINT_GPIO_ENA_GPIO6_ENA_M BIT(6)
4846 #define PFINT_MBX_CTL 0x0016B280 /* Reset Source: CORER */
4847 #define PFINT_MBX_CTL_MSIX_INDX_S 0
4848 #define PFINT_MBX_CTL_MSIX_INDX_M MAKEMASK(0x7FF, 0)
4849 #define PFINT_MBX_CTL_ITR_INDX_S 11
4850 #define PFINT_MBX_CTL_ITR_INDX_M MAKEMASK(0x3, 11)
4851 #define PFINT_MBX_CTL_CAUSE_ENA_S 30
4852 #define PFINT_MBX_CTL_CAUSE_ENA_M BIT(30)
4853 #define PFINT_MBX_CTL_INTEVENT_S 31
4854 #define PFINT_MBX_CTL_INTEVENT_M BIT(31)
4855 #define PFINT_OICR 0x0016CA00 /* Reset Source: CORER */
4856 #define PFINT_OICR_INTEVENT_S 0
4857 #define PFINT_OICR_INTEVENT_M BIT(0)
4858 #define PFINT_OICR_QUEUE_S 1
4859 #define PFINT_OICR_QUEUE_M BIT(1)
4860 #define PFINT_OICR_RSV1_S 2
4861 #define PFINT_OICR_RSV1_M MAKEMASK(0xFF, 2)
4862 #define PFINT_OICR_HH_COMP_S 10
4863 #define PFINT_OICR_HH_COMP_M BIT(10)
4864 #define PFINT_OICR_TSYN_TX_S 11
4865 #define PFINT_OICR_TSYN_TX_M BIT(11)
4866 #define PFINT_OICR_TSYN_EVNT_S 12
4867 #define PFINT_OICR_TSYN_EVNT_M BIT(12)
4868 #define PFINT_OICR_TSYN_TGT_S 13
4869 #define PFINT_OICR_TSYN_TGT_M BIT(13)
4870 #define PFINT_OICR_HLP_RDY_S 14
4871 #define PFINT_OICR_HLP_RDY_M BIT(14)
4872 #define PFINT_OICR_CPM_RDY_S 15
4873 #define PFINT_OICR_CPM_RDY_M BIT(15)
4874 #define PFINT_OICR_ECC_ERR_S 16
4875 #define PFINT_OICR_ECC_ERR_M BIT(16)
4876 #define PFINT_OICR_RSV2_S 17
4877 #define PFINT_OICR_RSV2_M MAKEMASK(0x3, 17)
4878 #define PFINT_OICR_MAL_DETECT_S 19
4879 #define PFINT_OICR_MAL_DETECT_M BIT(19)
4880 #define PFINT_OICR_GRST_S 20
4881 #define PFINT_OICR_GRST_M BIT(20)
4882 #define PFINT_OICR_PCI_EXCEPTION_S 21
4883 #define PFINT_OICR_PCI_EXCEPTION_M BIT(21)
4884 #define PFINT_OICR_GPIO_S 22
4885 #define PFINT_OICR_GPIO_M BIT(22)
4886 #define PFINT_OICR_RSV3_S 23
4887 #define PFINT_OICR_RSV3_M BIT(23)
4888 #define PFINT_OICR_STORM_DETECT_S 24
4889 #define PFINT_OICR_STORM_DETECT_M BIT(24)
4890 #define PFINT_OICR_LINK_STAT_CHANGE_S 25
4891 #define PFINT_OICR_LINK_STAT_CHANGE_M BIT(25)
4892 #define PFINT_OICR_HMC_ERR_S 26
4893 #define PFINT_OICR_HMC_ERR_M BIT(26)
4894 #define PFINT_OICR_PE_PUSH_S 27
4895 #define PFINT_OICR_PE_PUSH_M BIT(27)
4896 #define PFINT_OICR_PE_CRITERR_S 28
4897 #define PFINT_OICR_PE_CRITERR_M BIT(28)
4898 #define PFINT_OICR_VFLR_S 29
4899 #define PFINT_OICR_VFLR_M BIT(29)
4900 #define PFINT_OICR_XLR_HW_DONE_S 30
4901 #define PFINT_OICR_XLR_HW_DONE_M BIT(30)
4902 #define PFINT_OICR_SWINT_S 31
4903 #define PFINT_OICR_SWINT_M BIT(31)
4904 #define PFINT_OICR_CTL 0x0016CA80 /* Reset Source: CORER */
4905 #define PFINT_OICR_CTL_MSIX_INDX_S 0
4906 #define PFINT_OICR_CTL_MSIX_INDX_M MAKEMASK(0x7FF, 0)
4907 #define PFINT_OICR_CTL_ITR_INDX_S 11
4908 #define PFINT_OICR_CTL_ITR_INDX_M MAKEMASK(0x3, 11)
4909 #define PFINT_OICR_CTL_CAUSE_ENA_S 30
4910 #define PFINT_OICR_CTL_CAUSE_ENA_M BIT(30)
4911 #define PFINT_OICR_CTL_INTEVENT_S 31
4912 #define PFINT_OICR_CTL_INTEVENT_M BIT(31)
4913 #define PFINT_OICR_ENA 0x0016C900 /* Reset Source: CORER */
4914 #define PFINT_OICR_ENA_RSV0_S 0
4915 #define PFINT_OICR_ENA_RSV0_M BIT(0)
4916 #define PFINT_OICR_ENA_INT_ENA_S 1
4917 #define PFINT_OICR_ENA_INT_ENA_M MAKEMASK(0x7FFFFFFF, 1)
4918 #define PFINT_SB_CTL 0x0016B600 /* Reset Source: CORER */
4919 #define PFINT_SB_CTL_MSIX_INDX_S 0
4920 #define PFINT_SB_CTL_MSIX_INDX_M MAKEMASK(0x7FF, 0)
4921 #define PFINT_SB_CTL_ITR_INDX_S 11
4922 #define PFINT_SB_CTL_ITR_INDX_M MAKEMASK(0x3, 11)
4923 #define PFINT_SB_CTL_CAUSE_ENA_S 30
4924 #define PFINT_SB_CTL_CAUSE_ENA_M BIT(30)
4925 #define PFINT_SB_CTL_INTEVENT_S 31
4926 #define PFINT_SB_CTL_INTEVENT_M BIT(31)
4927 #define PFINT_TSYN_MSK 0x0016C980 /* Reset Source: CORER */
4928 #define PFINT_TSYN_MSK_PHY_INDX_S 0
4929 #define PFINT_TSYN_MSK_PHY_INDX_M MAKEMASK(0x1F, 0)
4930 #define QINT_RQCTL(_QRX) (0x00150000 + ((_QRX) * 4)) /* _i=0...2047 */ /* Reset Source: CORER */
4931 #define QINT_RQCTL_MAX_INDEX 2047
4932 #define QINT_RQCTL_MSIX_INDX_S 0
4933 #define QINT_RQCTL_MSIX_INDX_M MAKEMASK(0x7FF, 0)
4934 #define QINT_RQCTL_ITR_INDX_S 11
4935 #define QINT_RQCTL_ITR_INDX_M MAKEMASK(0x3, 11)
4936 #define QINT_RQCTL_CAUSE_ENA_S 30
4937 #define QINT_RQCTL_CAUSE_ENA_M BIT(30)
4938 #define QINT_RQCTL_INTEVENT_S 31
4939 #define QINT_RQCTL_INTEVENT_M BIT(31)
4940 #define QINT_TQCTL(_DBQM) (0x00140000 + ((_DBQM) * 4)) /* _i=0...16383 */ /* Reset Source: CORER */
4941 #define QINT_TQCTL_MAX_INDEX 16383
4942 #define QINT_TQCTL_MSIX_INDX_S 0
4943 #define QINT_TQCTL_MSIX_INDX_M MAKEMASK(0x7FF, 0)
4944 #define QINT_TQCTL_ITR_INDX_S 11
4945 #define QINT_TQCTL_ITR_INDX_M MAKEMASK(0x3, 11)
4946 #define QINT_TQCTL_CAUSE_ENA_S 30
4947 #define QINT_TQCTL_CAUSE_ENA_M BIT(30)
4948 #define QINT_TQCTL_INTEVENT_S 31
4949 #define QINT_TQCTL_INTEVENT_M BIT(31)
4950 #define VPINT_AEQCTL(_VF) (0x0016B800 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: CORER */
4951 #define VPINT_AEQCTL_MAX_INDEX 255
4952 #define VPINT_AEQCTL_MSIX_INDX_S 0
4953 #define VPINT_AEQCTL_MSIX_INDX_M MAKEMASK(0x7FF, 0)
4954 #define VPINT_AEQCTL_ITR_INDX_S 11
4955 #define VPINT_AEQCTL_ITR_INDX_M MAKEMASK(0x3, 11)
4956 #define VPINT_AEQCTL_CAUSE_ENA_S 30
4957 #define VPINT_AEQCTL_CAUSE_ENA_M BIT(30)
4958 #define VPINT_AEQCTL_INTEVENT_S 31
4959 #define VPINT_AEQCTL_INTEVENT_M BIT(31)
4960 #define VPINT_ALLOC(_VF) (0x001D1000 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: CORER */
4961 #define VPINT_ALLOC_MAX_INDEX 255
4962 #define VPINT_ALLOC_FIRST_S 0
4963 #define VPINT_ALLOC_FIRST_M MAKEMASK(0x7FF, 0)
4964 #define VPINT_ALLOC_LAST_S 12
4965 #define VPINT_ALLOC_LAST_M MAKEMASK(0x7FF, 12)
4966 #define VPINT_ALLOC_VALID_S 31
4967 #define VPINT_ALLOC_VALID_M BIT(31)
4968 #define VPINT_ALLOC_PCI(_VF) (0x0009D000 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: PCIR */
4969 #define VPINT_ALLOC_PCI_MAX_INDEX 255
4970 #define VPINT_ALLOC_PCI_FIRST_S 0
4971 #define VPINT_ALLOC_PCI_FIRST_M MAKEMASK(0x7FF, 0)
4972 #define VPINT_ALLOC_PCI_LAST_S 12
4973 #define VPINT_ALLOC_PCI_LAST_M MAKEMASK(0x7FF, 12)
4974 #define VPINT_ALLOC_PCI_VALID_S 31
4975 #define VPINT_ALLOC_PCI_VALID_M BIT(31)
4976 #define VPINT_MBX_CPM_CTL(_VP128) (0x0016B000 + ((_VP128) * 4)) /* _i=0...127 */ /* Reset Source: CORER */
4977 #define VPINT_MBX_CPM_CTL_MAX_INDEX 127
4978 #define VPINT_MBX_CPM_CTL_MSIX_INDX_S 0
4979 #define VPINT_MBX_CPM_CTL_MSIX_INDX_M MAKEMASK(0x7FF, 0)
4980 #define VPINT_MBX_CPM_CTL_ITR_INDX_S 11
4981 #define VPINT_MBX_CPM_CTL_ITR_INDX_M MAKEMASK(0x3, 11)
4982 #define VPINT_MBX_CPM_CTL_CAUSE_ENA_S 30
4983 #define VPINT_MBX_CPM_CTL_CAUSE_ENA_M BIT(30)
4984 #define VPINT_MBX_CPM_CTL_INTEVENT_S 31
4985 #define VPINT_MBX_CPM_CTL_INTEVENT_M BIT(31)
4986 #define VPINT_MBX_CTL(_VSI) (0x0016A000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: CORER */
4987 #define VPINT_MBX_CTL_MAX_INDEX 767
4988 #define VPINT_MBX_CTL_MSIX_INDX_S 0
4989 #define VPINT_MBX_CTL_MSIX_INDX_M MAKEMASK(0x7FF, 0)
4990 #define VPINT_MBX_CTL_ITR_INDX_S 11
4991 #define VPINT_MBX_CTL_ITR_INDX_M MAKEMASK(0x3, 11)
4992 #define VPINT_MBX_CTL_CAUSE_ENA_S 30
4993 #define VPINT_MBX_CTL_CAUSE_ENA_M BIT(30)
4994 #define VPINT_MBX_CTL_INTEVENT_S 31
4995 #define VPINT_MBX_CTL_INTEVENT_M BIT(31)
4996 #define VPINT_MBX_HLP_CTL(_VP16) (0x0016B200 + ((_VP16) * 4)) /* _i=0...15 */ /* Reset Source: CORER */
4997 #define VPINT_MBX_HLP_CTL_MAX_INDEX 15
4998 #define VPINT_MBX_HLP_CTL_MSIX_INDX_S 0
4999 #define VPINT_MBX_HLP_CTL_MSIX_INDX_M MAKEMASK(0x7FF, 0)
5000 #define VPINT_MBX_HLP_CTL_ITR_INDX_S 11
5001 #define VPINT_MBX_HLP_CTL_ITR_INDX_M MAKEMASK(0x3, 11)
5002 #define VPINT_MBX_HLP_CTL_CAUSE_ENA_S 30
5003 #define VPINT_MBX_HLP_CTL_CAUSE_ENA_M BIT(30)
5004 #define VPINT_MBX_HLP_CTL_INTEVENT_S 31
5005 #define VPINT_MBX_HLP_CTL_INTEVENT_M BIT(31)
5006 #define VPINT_MBX_PSM_CTL(_VP16) (0x0016B240 + ((_VP16) * 4)) /* _i=0...15 */ /* Reset Source: CORER */
5007 #define VPINT_MBX_PSM_CTL_MAX_INDEX 15
5008 #define VPINT_MBX_PSM_CTL_MSIX_INDX_S 0
5009 #define VPINT_MBX_PSM_CTL_MSIX_INDX_M MAKEMASK(0x7FF, 0)
5010 #define VPINT_MBX_PSM_CTL_ITR_INDX_S 11
5011 #define VPINT_MBX_PSM_CTL_ITR_INDX_M MAKEMASK(0x3, 11)
5012 #define VPINT_MBX_PSM_CTL_CAUSE_ENA_S 30
5013 #define VPINT_MBX_PSM_CTL_CAUSE_ENA_M BIT(30)
5014 #define VPINT_MBX_PSM_CTL_INTEVENT_S 31
5015 #define VPINT_MBX_PSM_CTL_INTEVENT_M BIT(31)
5016 #define VPINT_SB_CPM_CTL(_VP128) (0x0016B400 + ((_VP128) * 4)) /* _i=0...127 */ /* Reset Source: CORER */
5017 #define VPINT_SB_CPM_CTL_MAX_INDEX 127
5018 #define VPINT_SB_CPM_CTL_MSIX_INDX_S 0
5019 #define VPINT_SB_CPM_CTL_MSIX_INDX_M MAKEMASK(0x7FF, 0)
5020 #define VPINT_SB_CPM_CTL_ITR_INDX_S 11
5021 #define VPINT_SB_CPM_CTL_ITR_INDX_M MAKEMASK(0x3, 11)
5022 #define VPINT_SB_CPM_CTL_CAUSE_ENA_S 30
5023 #define VPINT_SB_CPM_CTL_CAUSE_ENA_M BIT(30)
5024 #define VPINT_SB_CPM_CTL_INTEVENT_S 31
5025 #define VPINT_SB_CPM_CTL_INTEVENT_M BIT(31)
5026 #define GL_HLP_PRT_IPG_PREAMBLE_SIZE(_i) (0x00049240 + ((_i) * 4)) /* _i=0...20 */ /* Reset Source: CORER */
5027 #define GL_HLP_PRT_IPG_PREAMBLE_SIZE_MAX_INDEX 20
5028 #define GL_HLP_PRT_IPG_PREAMBLE_SIZE_IPG_PREAMBLE_SIZE_S 0
5029 #define GL_HLP_PRT_IPG_PREAMBLE_SIZE_IPG_PREAMBLE_SIZE_M MAKEMASK(0xFF, 0)
5030 #define GL_TDPU_PSM_DEFAULT_RECIPE(_i) (0x00049294 + ((_i) * 4)) /* _i=0...3 */ /* Reset Source: CORER */
5031 #define GL_TDPU_PSM_DEFAULT_RECIPE_MAX_INDEX 3
5032 #define GL_TDPU_PSM_DEFAULT_RECIPE_ADD_IPG_S 0
5033 #define GL_TDPU_PSM_DEFAULT_RECIPE_ADD_IPG_M BIT(0)
5034 #define GL_TDPU_PSM_DEFAULT_RECIPE_SUB_CRC_S 1
5035 #define GL_TDPU_PSM_DEFAULT_RECIPE_SUB_CRC_M BIT(1)
5036 #define GL_TDPU_PSM_DEFAULT_RECIPE_SUB_ESP_TRAILER_S 2
5037 #define GL_TDPU_PSM_DEFAULT_RECIPE_SUB_ESP_TRAILER_M BIT(2)
5038 #define GL_TDPU_PSM_DEFAULT_RECIPE_INCLUDE_L2_PAD_S 3
5039 #define GL_TDPU_PSM_DEFAULT_RECIPE_INCLUDE_L2_PAD_M BIT(3)
5040 #define GL_TDPU_PSM_DEFAULT_RECIPE_DEFAULT_UPDATE_MODE_S 4
5041 #define GL_TDPU_PSM_DEFAULT_RECIPE_DEFAULT_UPDATE_MODE_M BIT(4)
5042 #define GLLAN_PF_RECIPE(_i) (0x0029420C + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
5043 #define GLLAN_PF_RECIPE_MAX_INDEX 7
5044 #define GLLAN_PF_RECIPE_RECIPE_S 0
5045 #define GLLAN_PF_RECIPE_RECIPE_M MAKEMASK(0x3, 0)
5046 #define GLLAN_RCTL_0 0x002941F8 /* Reset Source: CORER */
5047 #define GLLAN_RCTL_0_PXE_MODE_S 0
5048 #define GLLAN_RCTL_0_PXE_MODE_M BIT(0)
5049 #define GLLAN_RCTL_1 0x002941FC /* Reset Source: CORER */
5050 #define GLLAN_RCTL_1_RXMAX_EXPANSION_S 12
5051 #define GLLAN_RCTL_1_RXMAX_EXPANSION_M MAKEMASK(0xF, 12)
5052 #define GLLAN_RCTL_1_RXDRDCTL_S 17
5053 #define GLLAN_RCTL_1_RXDRDCTL_M BIT(17)
5054 #define GLLAN_RCTL_1_RXDESCRDROEN_S 18
5055 #define GLLAN_RCTL_1_RXDESCRDROEN_M BIT(18)
5056 #define GLLAN_RCTL_1_RXDATAWRROEN_S 19
5057 #define GLLAN_RCTL_1_RXDATAWRROEN_M BIT(19)
5058 #define GLLAN_TSOMSK_F 0x00049308 /* Reset Source: CORER */
5059 #define GLLAN_TSOMSK_F_TCPMSKF_S 0
5060 #define GLLAN_TSOMSK_F_TCPMSKF_M MAKEMASK(0xFFF, 0)
5061 #define GLLAN_TSOMSK_L 0x00049310 /* Reset Source: CORER */
5062 #define GLLAN_TSOMSK_L_TCPMSKL_S 0
5063 #define GLLAN_TSOMSK_L_TCPMSKL_M MAKEMASK(0xFFF, 0)
5064 #define GLLAN_TSOMSK_M 0x0004930C /* Reset Source: CORER */
5065 #define GLLAN_TSOMSK_M_TCPMSKM_S 0
5066 #define GLLAN_TSOMSK_M_TCPMSKM_M MAKEMASK(0xFFF, 0)
5067 #define PFLAN_CP_QALLOC 0x00075700 /* Reset Source: CORER */
5068 #define PFLAN_CP_QALLOC_FIRSTQ_S 0
5069 #define PFLAN_CP_QALLOC_FIRSTQ_M MAKEMASK(0x1FF, 0)
5070 #define PFLAN_CP_QALLOC_LASTQ_S 16
5071 #define PFLAN_CP_QALLOC_LASTQ_M MAKEMASK(0x1FF, 16)
5072 #define PFLAN_CP_QALLOC_VALID_S 31
5073 #define PFLAN_CP_QALLOC_VALID_M BIT(31)
5074 #define PFLAN_DB_QALLOC 0x00075680 /* Reset Source: CORER */
5075 #define PFLAN_DB_QALLOC_FIRSTQ_S 0
5076 #define PFLAN_DB_QALLOC_FIRSTQ_M MAKEMASK(0xFF, 0)
5077 #define PFLAN_DB_QALLOC_LASTQ_S 16
5078 #define PFLAN_DB_QALLOC_LASTQ_M MAKEMASK(0xFF, 16)
5079 #define PFLAN_DB_QALLOC_VALID_S 31
5080 #define PFLAN_DB_QALLOC_VALID_M BIT(31)
5081 #define PFLAN_RX_QALLOC 0x001D2500 /* Reset Source: CORER */
5082 #define PFLAN_RX_QALLOC_FIRSTQ_S 0
5083 #define PFLAN_RX_QALLOC_FIRSTQ_M MAKEMASK(0x7FF, 0)
5084 #define PFLAN_RX_QALLOC_LASTQ_S 16
5085 #define PFLAN_RX_QALLOC_LASTQ_M MAKEMASK(0x7FF, 16)
5086 #define PFLAN_RX_QALLOC_VALID_S 31
5087 #define PFLAN_RX_QALLOC_VALID_M BIT(31)
5088 #define PFLAN_TX_QALLOC 0x001D2580 /* Reset Source: CORER */
5089 #define PFLAN_TX_QALLOC_FIRSTQ_S 0
5090 #define PFLAN_TX_QALLOC_FIRSTQ_M MAKEMASK(0x3FFF, 0)
5091 #define PFLAN_TX_QALLOC_LASTQ_S 16
5092 #define PFLAN_TX_QALLOC_LASTQ_M MAKEMASK(0x3FFF, 16)
5093 #define PFLAN_TX_QALLOC_VALID_S 31
5094 #define PFLAN_TX_QALLOC_VALID_M BIT(31)
5095 #define PRT_TDPUL2TAGSEN 0x00040BA0 /* Reset Source: CORER */
5096 #define PRT_TDPUL2TAGSEN_ENABLE_S 0
5097 #define PRT_TDPUL2TAGSEN_ENABLE_M MAKEMASK(0xFF, 0)
5098 #define PRT_TDPUL2TAGSEN_NONLAST_TAG_S 8
5099 #define PRT_TDPUL2TAGSEN_NONLAST_TAG_M MAKEMASK(0xFF, 8)
5100 #define QRX_CONTEXT(_i, _QRX) (0x00280000 + ((_i) * 8192 + (_QRX) * 4)) /* _i=0...7, _QRX=0...2047 */ /* Reset Source: CORER */
5101 #define QRX_CONTEXT_MAX_INDEX 7
5102 #define QRX_CONTEXT_RXQ_CONTEXT_S 0
5103 #define QRX_CONTEXT_RXQ_CONTEXT_M MAKEMASK(0xFFFFFFFF, 0)
5104 #define QRX_CTRL(_QRX) (0x00120000 + ((_QRX) * 4)) /* _i=0...2047 */ /* Reset Source: PFR */
5105 #define QRX_CTRL_MAX_INDEX 2047
5106 #define QRX_CTRL_QENA_REQ_S 0
5107 #define QRX_CTRL_QENA_REQ_M BIT(0)
5108 #define QRX_CTRL_FAST_QDIS_S 1
5109 #define QRX_CTRL_FAST_QDIS_M BIT(1)
5110 #define QRX_CTRL_QENA_STAT_S 2
5111 #define QRX_CTRL_QENA_STAT_M BIT(2)
5112 #define QRX_CTRL_CDE_S 3
5113 #define QRX_CTRL_CDE_M BIT(3)
5114 #define QRX_CTRL_CDS_S 4
5115 #define QRX_CTRL_CDS_M BIT(4)
5116 #define QRX_ITR(_QRX) (0x00292000 + ((_QRX) * 4)) /* _i=0...2047 */ /* Reset Source: CORER */
5117 #define QRX_ITR_MAX_INDEX 2047
5118 #define QRX_ITR_NO_EXPR_S 0
5119 #define QRX_ITR_NO_EXPR_M BIT(0)
5120 #define QRX_TAIL(_QRX) (0x00290000 + ((_QRX) * 4)) /* _i=0...2047 */ /* Reset Source: CORER */
5121 #define QRX_TAIL_MAX_INDEX 2047
5122 #define QRX_TAIL_TAIL_S 0
5123 #define QRX_TAIL_TAIL_M MAKEMASK(0x1FFF, 0)
5124 #define VPDSI_RX_QTABLE(_i, _VP16) (0x00074C00 + ((_i) * 64 + (_VP16) * 4)) /* _i=0...15, _VP16=0...15 */ /* Reset Source: CORER */
5125 #define VPDSI_RX_QTABLE_MAX_INDEX 15
5126 #define VPDSI_RX_QTABLE_PAGE_INDEX0_S 0
5127 #define VPDSI_RX_QTABLE_PAGE_INDEX0_M MAKEMASK(0x7F, 0)
5128 #define VPDSI_RX_QTABLE_PAGE_INDEX1_S 8
5129 #define VPDSI_RX_QTABLE_PAGE_INDEX1_M MAKEMASK(0x7F, 8)
5130 #define VPDSI_RX_QTABLE_PAGE_INDEX2_S 16
5131 #define VPDSI_RX_QTABLE_PAGE_INDEX2_M MAKEMASK(0x7F, 16)
5132 #define VPDSI_RX_QTABLE_PAGE_INDEX3_S 24
5133 #define VPDSI_RX_QTABLE_PAGE_INDEX3_M MAKEMASK(0x7F, 24)
5134 #define VPDSI_TX_QTABLE(_i, _VP16) (0x001D2000 + ((_i) * 64 + (_VP16) * 4)) /* _i=0...15, _VP16=0...15 */ /* Reset Source: CORER */
5135 #define VPDSI_TX_QTABLE_MAX_INDEX 15
5136 #define VPDSI_TX_QTABLE_PAGE_INDEX0_S 0
5137 #define VPDSI_TX_QTABLE_PAGE_INDEX0_M MAKEMASK(0x7F, 0)
5138 #define VPDSI_TX_QTABLE_PAGE_INDEX1_S 8
5139 #define VPDSI_TX_QTABLE_PAGE_INDEX1_M MAKEMASK(0x7F, 8)
5140 #define VPDSI_TX_QTABLE_PAGE_INDEX2_S 16
5141 #define VPDSI_TX_QTABLE_PAGE_INDEX2_M MAKEMASK(0x7F, 16)
5142 #define VPDSI_TX_QTABLE_PAGE_INDEX3_S 24
5143 #define VPDSI_TX_QTABLE_PAGE_INDEX3_M MAKEMASK(0x7F, 24)
5144 #define VPLAN_DB_QTABLE(_i, _VF) (0x00070000 + ((_i) * 2048 + (_VF) * 4)) /* _i=0...3, _VF=0...255 */ /* Reset Source: CORER */
5145 #define VPLAN_DB_QTABLE_MAX_INDEX 3
5146 #define VPLAN_DB_QTABLE_QINDEX_S 0
5147 #define VPLAN_DB_QTABLE_QINDEX_M MAKEMASK(0x1FF, 0)
5148 #define VPLAN_DSI_VF_MODE(_VP16) (0x002D2C00 + ((_VP16) * 4)) /* _i=0...15 */ /* Reset Source: CORER */
5149 #define VPLAN_DSI_VF_MODE_MAX_INDEX 15
5150 #define VPLAN_DSI_VF_MODE_LAN_DSI_VF_MODE_S 0
5151 #define VPLAN_DSI_VF_MODE_LAN_DSI_VF_MODE_M BIT(0)
5152 #define VPLAN_RX_QBASE(_VF) (0x00072000 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: CORER */
5153 #define VPLAN_RX_QBASE_MAX_INDEX 255
5154 #define VPLAN_RX_QBASE_VFFIRSTQ_S 0
5155 #define VPLAN_RX_QBASE_VFFIRSTQ_M MAKEMASK(0x7FF, 0)
5156 #define VPLAN_RX_QBASE_VFNUMQ_S 16
5157 #define VPLAN_RX_QBASE_VFNUMQ_M MAKEMASK(0xFF, 16)
5158 #define VPLAN_RX_QBASE_VFQTABLE_ENA_S 31
5159 #define VPLAN_RX_QBASE_VFQTABLE_ENA_M BIT(31)
5160 #define VPLAN_RX_QTABLE(_i, _VF) (0x00060000 + ((_i) * 2048 + (_VF) * 4)) /* _i=0...15, _VF=0...255 */ /* Reset Source: CORER */
5161 #define VPLAN_RX_QTABLE_MAX_INDEX 15
5162 #define VPLAN_RX_QTABLE_QINDEX_S 0
5163 #define VPLAN_RX_QTABLE_QINDEX_M MAKEMASK(0xFFF, 0)
5164 #define VPLAN_RXQ_MAPENA(_VF) (0x00073000 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: CORER */
5165 #define VPLAN_RXQ_MAPENA_MAX_INDEX 255
5166 #define VPLAN_RXQ_MAPENA_RX_ENA_S 0
5167 #define VPLAN_RXQ_MAPENA_RX_ENA_M BIT(0)
5168 #define VPLAN_TX_QBASE(_VF) (0x001D1800 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: CORER */
5169 #define VPLAN_TX_QBASE_MAX_INDEX 255
5170 #define VPLAN_TX_QBASE_VFFIRSTQ_S 0
5171 #define VPLAN_TX_QBASE_VFFIRSTQ_M MAKEMASK(0x3FFF, 0)
5172 #define VPLAN_TX_QBASE_VFNUMQ_S 16
5173 #define VPLAN_TX_QBASE_VFNUMQ_M MAKEMASK(0xFF, 16)
5174 #define VPLAN_TX_QBASE_VFQTABLE_ENA_S 31
5175 #define VPLAN_TX_QBASE_VFQTABLE_ENA_M BIT(31)
5176 #define VPLAN_TX_QTABLE(_i, _VF) (0x001C0000 + ((_i) * 2048 + (_VF) * 4)) /* _i=0...15, _VF=0...255 */ /* Reset Source: CORER */
5177 #define VPLAN_TX_QTABLE_MAX_INDEX 15
5178 #define VPLAN_TX_QTABLE_QINDEX_S 0
5179 #define VPLAN_TX_QTABLE_QINDEX_M MAKEMASK(0x7FFF, 0)
5180 #define VPLAN_TXQ_MAPENA(_VF) (0x00073800 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: CORER */
5181 #define VPLAN_TXQ_MAPENA_MAX_INDEX 255
5182 #define VPLAN_TXQ_MAPENA_TX_ENA_S 0
5183 #define VPLAN_TXQ_MAPENA_TX_ENA_M BIT(0)
5184 #define VSILAN_QBASE(_VSI) (0x0044C000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: PFR */
5185 #define VSILAN_QBASE_MAX_INDEX 767
5186 #define VSILAN_QBASE_VSIBASE_S 0
5187 #define VSILAN_QBASE_VSIBASE_M MAKEMASK(0x7FF, 0)
5188 #define VSILAN_QBASE_VSIQTABLE_ENA_S 11
5189 #define VSILAN_QBASE_VSIQTABLE_ENA_M BIT(11)
5190 #define VSILAN_QTABLE(_i, _VSI) (0x00440000 + ((_i) * 4096 + (_VSI) * 4)) /* _i=0...7, _VSI=0...767 */ /* Reset Source: PFR */
5191 #define VSILAN_QTABLE_MAX_INDEX 7
5192 #define VSILAN_QTABLE_QINDEX_0_S 0
5193 #define VSILAN_QTABLE_QINDEX_0_M MAKEMASK(0x7FF, 0)
5194 #define VSILAN_QTABLE_QINDEX_1_S 16
5195 #define VSILAN_QTABLE_QINDEX_1_M MAKEMASK(0x7FF, 16)
5196 #define PRTMAC_HSEC_CTL_RX_ENABLE_GCP 0x001E31C0 /* Reset Source: GLOBR */
5197 #define PRTMAC_HSEC_CTL_RX_ENABLE_GCP_HSEC_CTL_RX_ENABLE_GCP_S 0
5198 #define PRTMAC_HSEC_CTL_RX_ENABLE_GCP_HSEC_CTL_RX_ENABLE_GCP_M BIT(0)
5199 #define PRTMAC_HSEC_CTL_RX_ENABLE_GPP 0x001E34C0 /* Reset Source: GLOBR */
5200 #define PRTMAC_HSEC_CTL_RX_ENABLE_GPP_HSEC_CTL_RX_ENABLE_GPP_S 0
5201 #define PRTMAC_HSEC_CTL_RX_ENABLE_GPP_HSEC_CTL_RX_ENABLE_GPP_M BIT(0)
5202 #define PRTMAC_HSEC_CTL_RX_ENABLE_PPP 0x001E35C0 /* Reset Source: GLOBR */
5203 #define PRTMAC_HSEC_CTL_RX_ENABLE_PPP_HSEC_CTL_RX_ENABLE_PPP_S 0
5204 #define PRTMAC_HSEC_CTL_RX_ENABLE_PPP_HSEC_CTL_RX_ENABLE_PPP_M BIT(0)
5205 #define PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL 0x001E36C0 /* Reset Source: GLOBR */
5206 #define PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL_HSEC_CTL_RX_FORWARD_CONTROL_S 0
5207 #define PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL_HSEC_CTL_RX_FORWARD_CONTROL_M BIT(0)
5208 #define PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART1 0x001E3220 /* Reset Source: GLOBR */
5209 #define PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART1_HSEC_CTL_RX_PAUSE_DA_UCAST_PART1_S 0
5210 #define PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART1_HSEC_CTL_RX_PAUSE_DA_UCAST_PART1_M MAKEMASK(0xFFFFFFFF, 0)
5211 #define PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART2 0x001E3240 /* Reset Source: GLOBR */
5212 #define PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART2_HSEC_CTL_RX_PAUSE_DA_UCAST_PART2_S 0
5213 #define PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART2_HSEC_CTL_RX_PAUSE_DA_UCAST_PART2_M MAKEMASK(0xFFFF, 0)
5214 #define PRTMAC_HSEC_CTL_RX_PAUSE_ENABLE 0x001E3180 /* Reset Source: GLOBR */
5215 #define PRTMAC_HSEC_CTL_RX_PAUSE_ENABLE_HSEC_CTL_RX_PAUSE_ENABLE_S 0
5216 #define PRTMAC_HSEC_CTL_RX_PAUSE_ENABLE_HSEC_CTL_RX_PAUSE_ENABLE_M MAKEMASK(0x1FF, 0)
5217 #define PRTMAC_HSEC_CTL_RX_PAUSE_SA_PART1 0x001E3280 /* Reset Source: GLOBR */
5218 #define PRTMAC_HSEC_CTL_RX_PAUSE_SA_PART1_HSEC_CTL_RX_PAUSE_SA_PART1_S 0
5219 #define PRTMAC_HSEC_CTL_RX_PAUSE_SA_PART1_HSEC_CTL_RX_PAUSE_SA_PART1_M MAKEMASK(0xFFFFFFFF, 0)
5220 #define PRTMAC_HSEC_CTL_RX_PAUSE_SA_PART2 0x001E32A0 /* Reset Source: GLOBR */
5221 #define PRTMAC_HSEC_CTL_RX_PAUSE_SA_PART2_HSEC_CTL_RX_PAUSE_SA_PART2_S 0
5222 #define PRTMAC_HSEC_CTL_RX_PAUSE_SA_PART2_HSEC_CTL_RX_PAUSE_SA_PART2_M MAKEMASK(0xFFFF, 0)
5223 #define PRTMAC_HSEC_CTL_RX_QUANTA_S 0x001E3C40 /* Reset Source: GLOBR */
5224 #define PRTMAC_HSEC_CTL_RX_QUANTA_SHIFT_PRTMAC_HSEC_CTL_RX_QUANTA_SHIFT_S 0
5225 #define PRTMAC_HSEC_CTL_RX_QUANTA_SHIFT_PRTMAC_HSEC_CTL_RX_QUANTA_SHIFT_M MAKEMASK(0xFFFF, 0)
5226 #define PRTMAC_HSEC_CTL_TX_PAUSE_ENABLE 0x001E31A0 /* Reset Source: GLOBR */
5227 #define PRTMAC_HSEC_CTL_TX_PAUSE_ENABLE_HSEC_CTL_TX_PAUSE_ENABLE_S 0
5228 #define PRTMAC_HSEC_CTL_TX_PAUSE_ENABLE_HSEC_CTL_TX_PAUSE_ENABLE_M MAKEMASK(0x1FF, 0)
5229 #define PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(_i) (0x001E36E0 + ((_i) * 32)) /* _i=0...8 */ /* Reset Source: GLOBR */
5230 #define PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX 8
5231 #define PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_HSEC_CTL_TX_PAUSE_QUANTA_S 0
5232 #define PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_HSEC_CTL_TX_PAUSE_QUANTA_M MAKEMASK(0xFFFF, 0)
5233 #define PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(_i) (0x001E3800 + ((_i) * 32)) /* _i=0...8 */ /* Reset Source: GLOBR */
5234 #define PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_MAX_INDEX 8
5235 #define PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_S 0
5236 #define PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_M MAKEMASK(0xFFFF, 0)
5237 #define PRTMAC_HSEC_CTL_TX_SA_PART1 0x001E3960 /* Reset Source: GLOBR */
5238 #define PRTMAC_HSEC_CTL_TX_SA_PART1_HSEC_CTL_TX_SA_PART1_S 0
5239 #define PRTMAC_HSEC_CTL_TX_SA_PART1_HSEC_CTL_TX_SA_PART1_M MAKEMASK(0xFFFFFFFF, 0)
5240 #define PRTMAC_HSEC_CTL_TX_SA_PART2 0x001E3980 /* Reset Source: GLOBR */
5241 #define PRTMAC_HSEC_CTL_TX_SA_PART2_HSEC_CTL_TX_SA_PART2_S 0
5242 #define PRTMAC_HSEC_CTL_TX_SA_PART2_HSEC_CTL_TX_SA_PART2_M MAKEMASK(0xFFFF, 0)
5243 #define PRTMAC_LINK_DOWN_COUNTER 0x001E47C0 /* Reset Source: GLOBR */
5244 #define PRTMAC_LINK_DOWN_COUNTER_LINK_DOWN_COUNTER_S 0
5245 #define PRTMAC_LINK_DOWN_COUNTER_LINK_DOWN_COUNTER_M MAKEMASK(0xFFFF, 0)
5246 #define PRTMAC_MD_OVRRIDE_ENABLE(_i) (0x001E3C60 + ((_i) * 32)) /* _i=0...7 */ /* Reset Source: GLOBR */
5247 #define PRTMAC_MD_OVRRIDE_ENABLE_MAX_INDEX 7
5248 #define PRTMAC_MD_OVRRIDE_ENABLE_PRTMAC_MD_OVRRIDE_ENABLE_S 0
5249 #define PRTMAC_MD_OVRRIDE_ENABLE_PRTMAC_MD_OVRRIDE_ENABLE_M MAKEMASK(0xFFFFFFFF, 0)
5250 #define PRTMAC_MD_OVRRIDE_VAL(_i) (0x001E3D60 + ((_i) * 32)) /* _i=0...7 */ /* Reset Source: GLOBR */
5251 #define PRTMAC_MD_OVRRIDE_VAL_MAX_INDEX 7
5252 #define PRTMAC_MD_OVRRIDE_VAL_PRTMAC_MD_OVRRIDE_ENABLE_S 0
5253 #define PRTMAC_MD_OVRRIDE_VAL_PRTMAC_MD_OVRRIDE_ENABLE_M MAKEMASK(0xFFFFFFFF, 0)
5254 #define PRTMAC_RX_CNT_MRKR 0x001E48E0 /* Reset Source: GLOBR */
5255 #define PRTMAC_RX_CNT_MRKR_RX_CNT_MRKR_S 0
5256 #define PRTMAC_RX_CNT_MRKR_RX_CNT_MRKR_M MAKEMASK(0xFFFF, 0)
5257 #define PRTMAC_RX_PKT_DRP_CNT 0x001E3C20 /* Reset Source: GLOBR */
5258 #define PRTMAC_RX_PKT_DRP_CNT_RX_PKT_DRP_CNT_S 0
5259 #define PRTMAC_RX_PKT_DRP_CNT_RX_PKT_DRP_CNT_M MAKEMASK(0xFFFF, 0)
5260 #define PRTMAC_RX_PKT_DRP_CNT_RX_MKR_PKT_DRP_CNT_S 16
5261 #define PRTMAC_RX_PKT_DRP_CNT_RX_MKR_PKT_DRP_CNT_M MAKEMASK(0xFFFF, 16)
5262 #define PRTMAC_TX_CNT_MRKR 0x001E48C0 /* Reset Source: GLOBR */
5263 #define PRTMAC_TX_CNT_MRKR_TX_CNT_MRKR_S 0
5264 #define PRTMAC_TX_CNT_MRKR_TX_CNT_MRKR_M MAKEMASK(0xFFFF, 0)
5265 #define PRTMAC_TX_LNK_UP_CNT 0x001E4840 /* Reset Source: GLOBR */
5266 #define PRTMAC_TX_LNK_UP_CNT_TX_LINK_UP_CNT_S 0
5267 #define PRTMAC_TX_LNK_UP_CNT_TX_LINK_UP_CNT_M MAKEMASK(0xFFFF, 0)
5268 #define GL_MDCK_CFG1_TX_PQM 0x002D2DF4 /* Reset Source: CORER */
5269 #define GL_MDCK_CFG1_TX_PQM_SSO_MAX_DATA_LEN_S 0
5270 #define GL_MDCK_CFG1_TX_PQM_SSO_MAX_DATA_LEN_M MAKEMASK(0xFF, 0)
5271 #define GL_MDCK_CFG1_TX_PQM_SSO_MAX_PKT_CNT_S 8
5272 #define GL_MDCK_CFG1_TX_PQM_SSO_MAX_PKT_CNT_M MAKEMASK(0x3F, 8)
5273 #define GL_MDCK_CFG1_TX_PQM_SSO_MAX_DESC_CNT_S 16
5274 #define GL_MDCK_CFG1_TX_PQM_SSO_MAX_DESC_CNT_M MAKEMASK(0x3F, 16)
5275 #define GL_MDCK_EN_TX_PQM 0x002D2DFC /* Reset Source: CORER */
5276 #define GL_MDCK_EN_TX_PQM_PCI_DUMMY_COMP_S 0
5277 #define GL_MDCK_EN_TX_PQM_PCI_DUMMY_COMP_M BIT(0)
5278 #define GL_MDCK_EN_TX_PQM_PCI_UR_COMP_S 1
5279 #define GL_MDCK_EN_TX_PQM_PCI_UR_COMP_M BIT(1)
5280 #define GL_MDCK_EN_TX_PQM_RCV_SH_BE_LSO_S 3
5281 #define GL_MDCK_EN_TX_PQM_RCV_SH_BE_LSO_M BIT(3)
5282 #define GL_MDCK_EN_TX_PQM_Q_FL_MNG_EPY_CH_S 4
5283 #define GL_MDCK_EN_TX_PQM_Q_FL_MNG_EPY_CH_M BIT(4)
5284 #define GL_MDCK_EN_TX_PQM_Q_EPY_MNG_FL_CH_S 5
5285 #define GL_MDCK_EN_TX_PQM_Q_EPY_MNG_FL_CH_M BIT(5)
5286 #define GL_MDCK_EN_TX_PQM_LSO_NUMDESCS_ZERO_S 6
5287 #define GL_MDCK_EN_TX_PQM_LSO_NUMDESCS_ZERO_M BIT(6)
5288 #define GL_MDCK_EN_TX_PQM_LSO_LENGTH_ZERO_S 7
5289 #define GL_MDCK_EN_TX_PQM_LSO_LENGTH_ZERO_M BIT(7)
5290 #define GL_MDCK_EN_TX_PQM_LSO_MSS_BELOW_MIN_S 8
5291 #define GL_MDCK_EN_TX_PQM_LSO_MSS_BELOW_MIN_M BIT(8)
5292 #define GL_MDCK_EN_TX_PQM_LSO_MSS_ABOVE_MAX_S 9
5293 #define GL_MDCK_EN_TX_PQM_LSO_MSS_ABOVE_MAX_M BIT(9)
5294 #define GL_MDCK_EN_TX_PQM_LSO_HDR_SIZE_ZERO_S 10
5295 #define GL_MDCK_EN_TX_PQM_LSO_HDR_SIZE_ZERO_M BIT(10)
5296 #define GL_MDCK_EN_TX_PQM_RCV_CNT_BE_LSO_S 11
5297 #define GL_MDCK_EN_TX_PQM_RCV_CNT_BE_LSO_M BIT(11)
5298 #define GL_MDCK_EN_TX_PQM_SKIP_ONE_QT_ONLY_S 12
5299 #define GL_MDCK_EN_TX_PQM_SKIP_ONE_QT_ONLY_M BIT(12)
5300 #define GL_MDCK_EN_TX_PQM_LSO_PKTCNT_ZERO_S 13
5301 #define GL_MDCK_EN_TX_PQM_LSO_PKTCNT_ZERO_M BIT(13)
5302 #define GL_MDCK_EN_TX_PQM_SSO_LENGTH_ZERO_S 14
5303 #define GL_MDCK_EN_TX_PQM_SSO_LENGTH_ZERO_M BIT(14)
5304 #define GL_MDCK_EN_TX_PQM_SSO_LENGTH_EXCEED_S 15
5305 #define GL_MDCK_EN_TX_PQM_SSO_LENGTH_EXCEED_M BIT(15)
5306 #define GL_MDCK_EN_TX_PQM_SSO_PKTCNT_ZERO_S 16
5307 #define GL_MDCK_EN_TX_PQM_SSO_PKTCNT_ZERO_M BIT(16)
5308 #define GL_MDCK_EN_TX_PQM_SSO_PKTCNT_EXCEED_S 17
5309 #define GL_MDCK_EN_TX_PQM_SSO_PKTCNT_EXCEED_M BIT(17)
5310 #define GL_MDCK_EN_TX_PQM_SSO_NUMDESCS_ZERO_S 18
5311 #define GL_MDCK_EN_TX_PQM_SSO_NUMDESCS_ZERO_M BIT(18)
5312 #define GL_MDCK_EN_TX_PQM_SSO_NUMDESCS_EXCEED_S 19
5313 #define GL_MDCK_EN_TX_PQM_SSO_NUMDESCS_EXCEED_M BIT(19)
5314 #define GL_MDCK_EN_TX_PQM_TAIL_GT_RING_LENGTH_S 20
5315 #define GL_MDCK_EN_TX_PQM_TAIL_GT_RING_LENGTH_M BIT(20)
5316 #define GL_MDCK_EN_TX_PQM_RESERVED_DBL_TYPE_S 21
5317 #define GL_MDCK_EN_TX_PQM_RESERVED_DBL_TYPE_M BIT(21)
5318 #define GL_MDCK_EN_TX_PQM_ILLEGAL_HEAD_DROP_DBL_S 22
5319 #define GL_MDCK_EN_TX_PQM_ILLEGAL_HEAD_DROP_DBL_M BIT(22)
5320 #define GL_MDCK_EN_TX_PQM_LSO_OVER_COMMS_Q_S 23
5321 #define GL_MDCK_EN_TX_PQM_LSO_OVER_COMMS_Q_M BIT(23)
5322 #define GL_MDCK_EN_TX_PQM_ILLEGAL_VF_QNUM_S 24
5323 #define GL_MDCK_EN_TX_PQM_ILLEGAL_VF_QNUM_M BIT(24)
5324 #define GL_MDCK_EN_TX_PQM_QTAIL_GT_RING_LENGTH_S 25
5325 #define GL_MDCK_EN_TX_PQM_QTAIL_GT_RING_LENGTH_M BIT(25)
5326 #define GL_MDCK_EN_TX_PQM_RSVD_S 26
5327 #define GL_MDCK_EN_TX_PQM_RSVD_M MAKEMASK(0x3F, 26)
5328 #define GL_MDCK_RX 0x0029422C /* Reset Source: CORER */
5329 #define GL_MDCK_RX_DESC_ADDR_S 0
5330 #define GL_MDCK_RX_DESC_ADDR_M BIT(0)
5331 #define GL_MDCK_TX_TDPU 0x00049348 /* Reset Source: CORER */
5332 #define GL_MDCK_TX_TDPU_TTL_ERR_ITR_DIS_S 0
5333 #define GL_MDCK_TX_TDPU_TTL_ERR_ITR_DIS_M BIT(0)
5334 #define GL_MDCK_TX_TDPU_RCU_ANTISPOOF_ITR_DIS_S 1
5335 #define GL_MDCK_TX_TDPU_RCU_ANTISPOOF_ITR_DIS_M BIT(1)
5336 #define GL_MDCK_TX_TDPU_PCIE_UR_ITR_DIS_S 2
5337 #define GL_MDCK_TX_TDPU_PCIE_UR_ITR_DIS_M BIT(2)
5338 #define GL_MDCK_TX_TDPU_MAL_OFFSET_ITR_DIS_S 3
5339 #define GL_MDCK_TX_TDPU_MAL_OFFSET_ITR_DIS_M BIT(3)
5340 #define GL_MDCK_TX_TDPU_MAL_CMD_ITR_DIS_S 4
5341 #define GL_MDCK_TX_TDPU_MAL_CMD_ITR_DIS_M BIT(4)
5342 #define GL_MDCK_TX_TDPU_BIG_PKT_SIZE_ITR_DIS_S 5
5343 #define GL_MDCK_TX_TDPU_BIG_PKT_SIZE_ITR_DIS_M BIT(5)
5344 #define GL_MDCK_TX_TDPU_L2_ACCEPT_FAIL_ITR_DIS_S 6
5345 #define GL_MDCK_TX_TDPU_L2_ACCEPT_FAIL_ITR_DIS_M BIT(6)
5346 #define GL_MDCK_TX_TDPU_NIC_DSI_ITR_DIS_S 7
5347 #define GL_MDCK_TX_TDPU_NIC_DSI_ITR_DIS_M BIT(7)
5348 #define GL_MDCK_TX_TDPU_MAL_IPSEC_CMD_ITR_DIS_S 8
5349 #define GL_MDCK_TX_TDPU_MAL_IPSEC_CMD_ITR_DIS_M BIT(8)
5350 #define GL_MDCK_TX_TDPU_DSCP_CHECK_FAIL_ITR_DIS_S 9
5351 #define GL_MDCK_TX_TDPU_DSCP_CHECK_FAIL_ITR_DIS_M BIT(9)
5352 #define GL_MDCK_TX_TDPU_NIC_IPSEC_ITR_DIS_S 10
5353 #define GL_MDCK_TX_TDPU_NIC_IPSEC_ITR_DIS_M BIT(10)
5354 #define GL_MDET_RX 0x00294C00 /* Reset Source: CORER */
5355 #define GL_MDET_RX_QNUM_S 0
5356 #define GL_MDET_RX_QNUM_M MAKEMASK(0x7FFF, 0)
5357 #define GL_MDET_RX_VF_NUM_S 15
5358 #define GL_MDET_RX_VF_NUM_M MAKEMASK(0xFF, 15)
5359 #define GL_MDET_RX_PF_NUM_S 23
5360 #define GL_MDET_RX_PF_NUM_M MAKEMASK(0x7, 23)
5361 #define GL_MDET_RX_MAL_TYPE_S 26
5362 #define GL_MDET_RX_MAL_TYPE_M MAKEMASK(0x1F, 26)
5363 #define GL_MDET_RX_VALID_S 31
5364 #define GL_MDET_RX_VALID_M BIT(31)
5365 #define GL_MDET_TX_PQM 0x002D2E00 /* Reset Source: CORER */
5366 #define GL_MDET_TX_PQM_PF_NUM_S 0
5367 #define GL_MDET_TX_PQM_PF_NUM_M MAKEMASK(0x7, 0)
5368 #define GL_MDET_TX_PQM_VF_NUM_S 4
5369 #define GL_MDET_TX_PQM_VF_NUM_M MAKEMASK(0xFF, 4)
5370 #define GL_MDET_TX_PQM_QNUM_S 12
5371 #define GL_MDET_TX_PQM_QNUM_M MAKEMASK(0x3FFF, 12)
5372 #define GL_MDET_TX_PQM_MAL_TYPE_S 26
5373 #define GL_MDET_TX_PQM_MAL_TYPE_M MAKEMASK(0x1F, 26)
5374 #define GL_MDET_TX_PQM_VALID_S 31
5375 #define GL_MDET_TX_PQM_VALID_M BIT(31)
5376 #define GL_MDET_TX_TCLAN 0x000FC068 /* Reset Source: CORER */
5377 #define GL_MDET_TX_TCLAN_QNUM_S 0
5378 #define GL_MDET_TX_TCLAN_QNUM_M MAKEMASK(0x7FFF, 0)
5379 #define GL_MDET_TX_TCLAN_VF_NUM_S 15
5380 #define GL_MDET_TX_TCLAN_VF_NUM_M MAKEMASK(0xFF, 15)
5381 #define GL_MDET_TX_TCLAN_PF_NUM_S 23
5382 #define GL_MDET_TX_TCLAN_PF_NUM_M MAKEMASK(0x7, 23)
5383 #define GL_MDET_TX_TCLAN_MAL_TYPE_S 26
5384 #define GL_MDET_TX_TCLAN_MAL_TYPE_M MAKEMASK(0x1F, 26)
5385 #define GL_MDET_TX_TCLAN_VALID_S 31
5386 #define GL_MDET_TX_TCLAN_VALID_M BIT(31)
5387 #define GL_MDET_TX_TDPU 0x00049350 /* Reset Source: CORER */
5388 #define GL_MDET_TX_TDPU_QNUM_S 0
5389 #define GL_MDET_TX_TDPU_QNUM_M MAKEMASK(0x7FFF, 0)
5390 #define GL_MDET_TX_TDPU_VF_NUM_S 15
5391 #define GL_MDET_TX_TDPU_VF_NUM_M MAKEMASK(0xFF, 15)
5392 #define GL_MDET_TX_TDPU_PF_NUM_S 23
5393 #define GL_MDET_TX_TDPU_PF_NUM_M MAKEMASK(0x7, 23)
5394 #define GL_MDET_TX_TDPU_MAL_TYPE_S 26
5395 #define GL_MDET_TX_TDPU_MAL_TYPE_M MAKEMASK(0x1F, 26)
5396 #define GL_MDET_TX_TDPU_VALID_S 31
5397 #define GL_MDET_TX_TDPU_VALID_M BIT(31)
5398 #define GLRLAN_MDET 0x00294200 /* Reset Source: CORER */
5399 #define GLRLAN_MDET_PCKT_EXTRCT_ERR_S 0
5400 #define GLRLAN_MDET_PCKT_EXTRCT_ERR_M BIT(0)
5401 #define PF_MDET_RX 0x00294280 /* Reset Source: CORER */
5402 #define PF_MDET_RX_VALID_S 0
5403 #define PF_MDET_RX_VALID_M BIT(0)
5404 #define PF_MDET_TX_PQM 0x002D2C80 /* Reset Source: CORER */
5405 #define PF_MDET_TX_PQM_VALID_S 0
5406 #define PF_MDET_TX_PQM_VALID_M BIT(0)
5407 #define PF_MDET_TX_TCLAN 0x000FC000 /* Reset Source: CORER */
5408 #define PF_MDET_TX_TCLAN_VALID_S 0
5409 #define PF_MDET_TX_TCLAN_VALID_M BIT(0)
5410 #define PF_MDET_TX_TDPU 0x00040800 /* Reset Source: CORER */
5411 #define PF_MDET_TX_TDPU_VALID_S 0
5412 #define PF_MDET_TX_TDPU_VALID_M BIT(0)
5413 #define VP_MDET_RX(_VF) (0x00294400 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: CORER */
5414 #define VP_MDET_RX_MAX_INDEX 255
5415 #define VP_MDET_RX_VALID_S 0
5416 #define VP_MDET_RX_VALID_M BIT(0)
5417 #define VP_MDET_TX_PQM(_VF) (0x002D2000 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: CORER */
5418 #define VP_MDET_TX_PQM_MAX_INDEX 255
5419 #define VP_MDET_TX_PQM_VALID_S 0
5420 #define VP_MDET_TX_PQM_VALID_M BIT(0)
5421 #define VP_MDET_TX_TCLAN(_VF) (0x000FB800 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: CORER */
5422 #define VP_MDET_TX_TCLAN_MAX_INDEX 255
5423 #define VP_MDET_TX_TCLAN_VALID_S 0
5424 #define VP_MDET_TX_TCLAN_VALID_M BIT(0)
5425 #define VP_MDET_TX_TDPU(_VF) (0x00040000 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: CORER */
5426 #define VP_MDET_TX_TDPU_MAX_INDEX 255
5427 #define VP_MDET_TX_TDPU_VALID_S 0
5428 #define VP_MDET_TX_TDPU_VALID_M BIT(0)
5429 #define GENERAL_MNG_FW_DBG_CSR(_i) (0x000B6180 + ((_i) * 4)) /* _i=0...9 */ /* Reset Source: POR */
5430 #define GENERAL_MNG_FW_DBG_CSR_MAX_INDEX 9
5431 #define GENERAL_MNG_FW_DBG_CSR_GENERAL_FW_DBG_S 0
5432 #define GENERAL_MNG_FW_DBG_CSR_GENERAL_FW_DBG_M MAKEMASK(0xFFFFFFFF, 0)
5433 #define GL_FWRESETCNT 0x00083100 /* Reset Source: POR */
5434 #define GL_FWRESETCNT_FWRESETCNT_S 0
5435 #define GL_FWRESETCNT_FWRESETCNT_M MAKEMASK(0xFFFFFFFF, 0)
5436 #define GL_MNG_FW_RAM_STAT 0x0008309C /* Reset Source: POR */
5437 #define GL_MNG_FW_RAM_STAT_FW_RAM_RST_STAT_S 0
5438 #define GL_MNG_FW_RAM_STAT_FW_RAM_RST_STAT_M BIT(0)
5439 #define GL_MNG_FW_RAM_STAT_MNG_MEM_ECC_ERR_S 1
5440 #define GL_MNG_FW_RAM_STAT_MNG_MEM_ECC_ERR_M BIT(1)
5441 #define GL_MNG_FWSM 0x000B6134 /* Reset Source: POR */
5442 #define GL_MNG_FWSM_FW_MODES_S 0
5443 #define GL_MNG_FWSM_FW_MODES_M MAKEMASK(0x7, 0)
5444 #define GL_MNG_FWSM_RSV0_S 3
5445 #define GL_MNG_FWSM_RSV0_M MAKEMASK(0x7F, 3)
5446 #define GL_MNG_FWSM_EEP_RELOAD_IND_S 10
5447 #define GL_MNG_FWSM_EEP_RELOAD_IND_M BIT(10)
5448 #define GL_MNG_FWSM_RSV1_S 11
5449 #define GL_MNG_FWSM_RSV1_M MAKEMASK(0xF, 11)
5450 #define GL_MNG_FWSM_RSV2_S 15
5451 #define GL_MNG_FWSM_RSV2_M BIT(15)
5452 #define GL_MNG_FWSM_PCIR_AL_FAILURE_S 16
5453 #define GL_MNG_FWSM_PCIR_AL_FAILURE_M BIT(16)
5454 #define GL_MNG_FWSM_POR_AL_FAILURE_S 17
5455 #define GL_MNG_FWSM_POR_AL_FAILURE_M BIT(17)
5456 #define GL_MNG_FWSM_RSV3_S 18
5457 #define GL_MNG_FWSM_RSV3_M BIT(18)
5458 #define GL_MNG_FWSM_EXT_ERR_IND_S 19
5459 #define GL_MNG_FWSM_EXT_ERR_IND_M MAKEMASK(0x3F, 19)
5460 #define GL_MNG_FWSM_RSV4_S 25
5461 #define GL_MNG_FWSM_RSV4_M BIT(25)
5462 #define GL_MNG_FWSM_RESERVED_11_S 26
5463 #define GL_MNG_FWSM_RESERVED_11_M MAKEMASK(0xF, 26)
5464 #define GL_MNG_FWSM_RSV5_S 30
5465 #define GL_MNG_FWSM_RSV5_M MAKEMASK(0x3, 30)
5466 #define GL_MNG_HWARB_CTRL 0x000B6130 /* Reset Source: POR */
5467 #define GL_MNG_HWARB_CTRL_NCSI_ARB_EN_S 0
5468 #define GL_MNG_HWARB_CTRL_NCSI_ARB_EN_M BIT(0)
5469 #define GL_MNG_SHA_EXTEND(_i) (0x00083120 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: EMPR */
5470 #define GL_MNG_SHA_EXTEND_MAX_INDEX 7
5471 #define GL_MNG_SHA_EXTEND_GL_MNG_SHA_EXTEND_S 0
5472 #define GL_MNG_SHA_EXTEND_GL_MNG_SHA_EXTEND_M MAKEMASK(0xFFFFFFFF, 0)
5473 #define GL_MNG_SHA_EXTEND_ROM(_i) (0x00083160 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: EMPR */
5474 #define GL_MNG_SHA_EXTEND_ROM_MAX_INDEX 7
5475 #define GL_MNG_SHA_EXTEND_ROM_GL_MNG_SHA_EXTEND_ROM_S 0
5476 #define GL_MNG_SHA_EXTEND_ROM_GL_MNG_SHA_EXTEND_ROM_M MAKEMASK(0xFFFFFFFF, 0)
5477 #define GL_MNG_SHA_EXTEND_STATUS 0x00083148 /* Reset Source: EMPR */
5478 #define GL_MNG_SHA_EXTEND_STATUS_STAGE_S 0
5479 #define GL_MNG_SHA_EXTEND_STATUS_STAGE_M MAKEMASK(0x7, 0)
5480 #define GL_MNG_SHA_EXTEND_STATUS_FW_HALTED_S 30
5481 #define GL_MNG_SHA_EXTEND_STATUS_FW_HALTED_M BIT(30)
5482 #define GL_MNG_SHA_EXTEND_STATUS_DONE_S 31
5483 #define GL_MNG_SHA_EXTEND_STATUS_DONE_M BIT(31)
5484 #define GL_SWT_PRT2MDEF(_i) (0x00216018 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: POR */
5485 #define GL_SWT_PRT2MDEF_MAX_INDEX 31
5486 #define GL_SWT_PRT2MDEF_MDEFIDX_S 0
5487 #define GL_SWT_PRT2MDEF_MDEFIDX_M MAKEMASK(0x7, 0)
5488 #define GL_SWT_PRT2MDEF_MDEFENA_S 31
5489 #define GL_SWT_PRT2MDEF_MDEFENA_M BIT(31)
5490 #define PRT_MNG_MANC 0x00214720 /* Reset Source: POR */
5491 #define PRT_MNG_MANC_FLOW_CONTROL_DISCARD_S 0
5492 #define PRT_MNG_MANC_FLOW_CONTROL_DISCARD_M BIT(0)
5493 #define PRT_MNG_MANC_NCSI_DISCARD_S 1
5494 #define PRT_MNG_MANC_NCSI_DISCARD_M BIT(1)
5495 #define PRT_MNG_MANC_RCV_TCO_EN_S 17
5496 #define PRT_MNG_MANC_RCV_TCO_EN_M BIT(17)
5497 #define PRT_MNG_MANC_RCV_ALL_S 19
5498 #define PRT_MNG_MANC_RCV_ALL_M BIT(19)
5499 #define PRT_MNG_MANC_FIXED_NET_TYPE_S 25
5500 #define PRT_MNG_MANC_FIXED_NET_TYPE_M BIT(25)
5501 #define PRT_MNG_MANC_NET_TYPE_S 26
5502 #define PRT_MNG_MANC_NET_TYPE_M BIT(26)
5503 #define PRT_MNG_MANC_EN_BMC2OS_S 28
5504 #define PRT_MNG_MANC_EN_BMC2OS_M BIT(28)
5505 #define PRT_MNG_MANC_EN_BMC2NET_S 29
5506 #define PRT_MNG_MANC_EN_BMC2NET_M BIT(29)
5507 #define PRT_MNG_MAVTV(_i) (0x00214780 + ((_i) * 32)) /* _i=0...7 */ /* Reset Source: POR */
5508 #define PRT_MNG_MAVTV_MAX_INDEX 7
5509 #define PRT_MNG_MAVTV_VID_S 0
5510 #define PRT_MNG_MAVTV_VID_M MAKEMASK(0xFFF, 0)
5511 #define PRT_MNG_MDEF(_i) (0x00214880 + ((_i) * 32)) /* _i=0...7 */ /* Reset Source: POR */
5512 #define PRT_MNG_MDEF_MAX_INDEX 7
5513 #define PRT_MNG_MDEF_MAC_EXACT_AND_S 0
5514 #define PRT_MNG_MDEF_MAC_EXACT_AND_M MAKEMASK(0xF, 0)
5515 #define PRT_MNG_MDEF_BROADCAST_AND_S 4
5516 #define PRT_MNG_MDEF_BROADCAST_AND_M BIT(4)
5517 #define PRT_MNG_MDEF_VLAN_AND_S 5
5518 #define PRT_MNG_MDEF_VLAN_AND_M MAKEMASK(0xFF, 5)
5519 #define PRT_MNG_MDEF_IPV4_ADDRESS_AND_S 13
5520 #define PRT_MNG_MDEF_IPV4_ADDRESS_AND_M MAKEMASK(0xF, 13)
5521 #define PRT_MNG_MDEF_IPV6_ADDRESS_AND_S 17
5522 #define PRT_MNG_MDEF_IPV6_ADDRESS_AND_M MAKEMASK(0xF, 17)
5523 #define PRT_MNG_MDEF_MAC_EXACT_OR_S 21
5524 #define PRT_MNG_MDEF_MAC_EXACT_OR_M MAKEMASK(0xF, 21)
5525 #define PRT_MNG_MDEF_BROADCAST_OR_S 25
5526 #define PRT_MNG_MDEF_BROADCAST_OR_M BIT(25)
5527 #define PRT_MNG_MDEF_MULTICAST_AND_S 26
5528 #define PRT_MNG_MDEF_MULTICAST_AND_M BIT(26)
5529 #define PRT_MNG_MDEF_ARP_REQUEST_OR_S 27
5530 #define PRT_MNG_MDEF_ARP_REQUEST_OR_M BIT(27)
5531 #define PRT_MNG_MDEF_ARP_RESPONSE_OR_S 28
5532 #define PRT_MNG_MDEF_ARP_RESPONSE_OR_M BIT(28)
5533 #define PRT_MNG_MDEF_NEIGHBOR_DISCOVERY_134_OR_S 29
5534 #define PRT_MNG_MDEF_NEIGHBOR_DISCOVERY_134_OR_M BIT(29)
5535 #define PRT_MNG_MDEF_PORT_0X298_OR_S 30
5536 #define PRT_MNG_MDEF_PORT_0X298_OR_M BIT(30)
5537 #define PRT_MNG_MDEF_PORT_0X26F_OR_S 31
5538 #define PRT_MNG_MDEF_PORT_0X26F_OR_M BIT(31)
5539 #define PRT_MNG_MDEF_EXT(_i) (0x00214A00 + ((_i) * 32)) /* _i=0...7 */ /* Reset Source: POR */
5540 #define PRT_MNG_MDEF_EXT_MAX_INDEX 7
5541 #define PRT_MNG_MDEF_EXT_L2_ETHERTYPE_AND_S 0
5542 #define PRT_MNG_MDEF_EXT_L2_ETHERTYPE_AND_M MAKEMASK(0xF, 0)
5543 #define PRT_MNG_MDEF_EXT_L2_ETHERTYPE_OR_S 4
5544 #define PRT_MNG_MDEF_EXT_L2_ETHERTYPE_OR_M MAKEMASK(0xF, 4)
5545 #define PRT_MNG_MDEF_EXT_FLEX_PORT_OR_S 8
5546 #define PRT_MNG_MDEF_EXT_FLEX_PORT_OR_M MAKEMASK(0xFFFF, 8)
5547 #define PRT_MNG_MDEF_EXT_FLEX_TCO_S 24
5548 #define PRT_MNG_MDEF_EXT_FLEX_TCO_M BIT(24)
5549 #define PRT_MNG_MDEF_EXT_NEIGHBOR_DISCOVERY_135_OR_S 25
5550 #define PRT_MNG_MDEF_EXT_NEIGHBOR_DISCOVERY_135_OR_M BIT(25)
5551 #define PRT_MNG_MDEF_EXT_NEIGHBOR_DISCOVERY_136_OR_S 26
5552 #define PRT_MNG_MDEF_EXT_NEIGHBOR_DISCOVERY_136_OR_M BIT(26)
5553 #define PRT_MNG_MDEF_EXT_NEIGHBOR_DISCOVERY_137_OR_S 27
5554 #define PRT_MNG_MDEF_EXT_NEIGHBOR_DISCOVERY_137_OR_M BIT(27)
5555 #define PRT_MNG_MDEF_EXT_ICMP_OR_S 28
5556 #define PRT_MNG_MDEF_EXT_ICMP_OR_M BIT(28)
5557 #define PRT_MNG_MDEF_EXT_MLD_S 29
5558 #define PRT_MNG_MDEF_EXT_MLD_M BIT(29)
5559 #define PRT_MNG_MDEF_EXT_APPLY_TO_NETWORK_TRAFFIC_S 30
5560 #define PRT_MNG_MDEF_EXT_APPLY_TO_NETWORK_TRAFFIC_M BIT(30)
5561 #define PRT_MNG_MDEF_EXT_APPLY_TO_HOST_TRAFFIC_S 31
5562 #define PRT_MNG_MDEF_EXT_APPLY_TO_HOST_TRAFFIC_M BIT(31)
5563 #define PRT_MNG_MDEFVSI(_i) (0x00214980 + ((_i) * 32)) /* _i=0...3 */ /* Reset Source: POR */
5564 #define PRT_MNG_MDEFVSI_MAX_INDEX 3
5565 #define PRT_MNG_MDEFVSI_MDEFVSI_2N_S 0
5566 #define PRT_MNG_MDEFVSI_MDEFVSI_2N_M MAKEMASK(0xFFFF, 0)
5567 #define PRT_MNG_MDEFVSI_MDEFVSI_2NP1_S 16
5568 #define PRT_MNG_MDEFVSI_MDEFVSI_2NP1_M MAKEMASK(0xFFFF, 16)
5569 #define PRT_MNG_METF(_i) (0x00214120 + ((_i) * 32)) /* _i=0...3 */ /* Reset Source: POR */
5570 #define PRT_MNG_METF_MAX_INDEX 3
5571 #define PRT_MNG_METF_ETYPE_S 0
5572 #define PRT_MNG_METF_ETYPE_M MAKEMASK(0xFFFF, 0)
5573 #define PRT_MNG_METF_POLARITY_S 30
5574 #define PRT_MNG_METF_POLARITY_M BIT(30)
5575 #define PRT_MNG_MFUTP(_i) (0x00214320 + ((_i) * 32)) /* _i=0...15 */ /* Reset Source: POR */
5576 #define PRT_MNG_MFUTP_MAX_INDEX 15
5577 #define PRT_MNG_MFUTP_MFUTP_N_S 0
5578 #define PRT_MNG_MFUTP_MFUTP_N_M MAKEMASK(0xFFFF, 0)
5579 #define PRT_MNG_MFUTP_UDP_S 16
5580 #define PRT_MNG_MFUTP_UDP_M BIT(16)
5581 #define PRT_MNG_MFUTP_TCP_S 17
5582 #define PRT_MNG_MFUTP_TCP_M BIT(17)
5583 #define PRT_MNG_MFUTP_SOURCE_DESTINATION_S 18
5584 #define PRT_MNG_MFUTP_SOURCE_DESTINATION_M BIT(18)
5585 #define PRT_MNG_MIPAF4(_i) (0x002141A0 + ((_i) * 32)) /* _i=0...3 */ /* Reset Source: POR */
5586 #define PRT_MNG_MIPAF4_MAX_INDEX 3
5587 #define PRT_MNG_MIPAF4_MIPAF_S 0
5588 #define PRT_MNG_MIPAF4_MIPAF_M MAKEMASK(0xFFFFFFFF, 0)
5589 #define PRT_MNG_MIPAF6(_i) (0x00214520 + ((_i) * 32)) /* _i=0...15 */ /* Reset Source: POR */
5590 #define PRT_MNG_MIPAF6_MAX_INDEX 15
5591 #define PRT_MNG_MIPAF6_MIPAF_S 0
5592 #define PRT_MNG_MIPAF6_MIPAF_M MAKEMASK(0xFFFFFFFF, 0)
5593 #define PRT_MNG_MMAH(_i) (0x00214220 + ((_i) * 32)) /* _i=0...3 */ /* Reset Source: POR */
5594 #define PRT_MNG_MMAH_MAX_INDEX 3
5595 #define PRT_MNG_MMAH_MMAH_S 0
5596 #define PRT_MNG_MMAH_MMAH_M MAKEMASK(0xFFFF, 0)
5597 #define PRT_MNG_MMAL(_i) (0x002142A0 + ((_i) * 32)) /* _i=0...3 */ /* Reset Source: POR */
5598 #define PRT_MNG_MMAL_MAX_INDEX 3
5599 #define PRT_MNG_MMAL_MMAL_S 0
5600 #define PRT_MNG_MMAL_MMAL_M MAKEMASK(0xFFFFFFFF, 0)
5601 #define PRT_MNG_MNGONLY 0x00214740 /* Reset Source: POR */
5602 #define PRT_MNG_MNGONLY_EXCLUSIVE_TO_MANAGEABILITY_S 0
5603 #define PRT_MNG_MNGONLY_EXCLUSIVE_TO_MANAGEABILITY_M MAKEMASK(0xFF, 0)
5604 #define PRT_MNG_MSFM 0x00214760 /* Reset Source: POR */
5605 #define PRT_MNG_MSFM_PORT_26F_UDP_S 0
5606 #define PRT_MNG_MSFM_PORT_26F_UDP_M BIT(0)
5607 #define PRT_MNG_MSFM_PORT_26F_TCP_S 1
5608 #define PRT_MNG_MSFM_PORT_26F_TCP_M BIT(1)
5609 #define PRT_MNG_MSFM_PORT_298_UDP_S 2
5610 #define PRT_MNG_MSFM_PORT_298_UDP_M BIT(2)
5611 #define PRT_MNG_MSFM_PORT_298_TCP_S 3
5612 #define PRT_MNG_MSFM_PORT_298_TCP_M BIT(3)
5613 #define PRT_MNG_MSFM_IPV6_0_MASK_S 4
5614 #define PRT_MNG_MSFM_IPV6_0_MASK_M BIT(4)
5615 #define PRT_MNG_MSFM_IPV6_1_MASK_S 5
5616 #define PRT_MNG_MSFM_IPV6_1_MASK_M BIT(5)
5617 #define PRT_MNG_MSFM_IPV6_2_MASK_S 6
5618 #define PRT_MNG_MSFM_IPV6_2_MASK_M BIT(6)
5619 #define PRT_MNG_MSFM_IPV6_3_MASK_S 7
5620 #define PRT_MNG_MSFM_IPV6_3_MASK_M BIT(7)
5621 #define MSIX_PBA_PAGE(_i) (0x02E08000 + ((_i) * 4)) /* _i=0...63 */ /* Reset Source: FLR */
5622 #define MSIX_PBA_PAGE_MAX_INDEX 63
5623 #define MSIX_PBA_PAGE_PENBIT_S 0
5624 #define MSIX_PBA_PAGE_PENBIT_M MAKEMASK(0xFFFFFFFF, 0)
5625 #define MSIX_PBA1(_i) (0x00008000 + ((_i) * 4)) /* _i=0...63 */ /* Reset Source: FLR */
5626 #define MSIX_PBA1_MAX_INDEX 63
5627 #define MSIX_PBA1_PENBIT_S 0
5628 #define MSIX_PBA1_PENBIT_M MAKEMASK(0xFFFFFFFF, 0)
5629 #define MSIX_TADD_PAGE(_i) (0x02E00000 + ((_i) * 16)) /* _i=0...2047 */ /* Reset Source: FLR */
5630 #define MSIX_TADD_PAGE_MAX_INDEX 2047
5631 #define MSIX_TADD_PAGE_MSIXTADD10_S 0
5632 #define MSIX_TADD_PAGE_MSIXTADD10_M MAKEMASK(0x3, 0)
5633 #define MSIX_TADD_PAGE_MSIXTADD_S 2
5634 #define MSIX_TADD_PAGE_MSIXTADD_M MAKEMASK(0x3FFFFFFF, 2)
5635 #define MSIX_TADD1(_i) (0x00000000 + ((_i) * 16)) /* _i=0...2047 */ /* Reset Source: FLR */
5636 #define MSIX_TADD1_MAX_INDEX 2047
5637 #define MSIX_TADD1_MSIXTADD10_S 0
5638 #define MSIX_TADD1_MSIXTADD10_M MAKEMASK(0x3, 0)
5639 #define MSIX_TADD1_MSIXTADD_S 2
5640 #define MSIX_TADD1_MSIXTADD_M MAKEMASK(0x3FFFFFFF, 2)
5641 #define MSIX_TMSG(_i) (0x00000008 + ((_i) * 16)) /* _i=0...2047 */ /* Reset Source: FLR */
5642 #define MSIX_TMSG_MAX_INDEX 2047
5643 #define MSIX_TMSG_MSIXTMSG_S 0
5644 #define MSIX_TMSG_MSIXTMSG_M MAKEMASK(0xFFFFFFFF, 0)
5645 #define MSIX_TMSG_PAGE(_i) (0x02E00008 + ((_i) * 16)) /* _i=0...2047 */ /* Reset Source: FLR */
5646 #define MSIX_TMSG_PAGE_MAX_INDEX 2047
5647 #define MSIX_TMSG_PAGE_MSIXTMSG_S 0
5648 #define MSIX_TMSG_PAGE_MSIXTMSG_M MAKEMASK(0xFFFFFFFF, 0)
5649 #define MSIX_TUADD_PAGE(_i) (0x02E00004 + ((_i) * 16)) /* _i=0...2047 */ /* Reset Source: FLR */
5650 #define MSIX_TUADD_PAGE_MAX_INDEX 2047
5651 #define MSIX_TUADD_PAGE_MSIXTUADD_S 0
5652 #define MSIX_TUADD_PAGE_MSIXTUADD_M MAKEMASK(0xFFFFFFFF, 0)
5653 #define MSIX_TUADD1(_i) (0x00000004 + ((_i) * 16)) /* _i=0...2047 */ /* Reset Source: FLR */
5654 #define MSIX_TUADD1_MAX_INDEX 2047
5655 #define MSIX_TUADD1_MSIXTUADD_S 0
5656 #define MSIX_TUADD1_MSIXTUADD_M MAKEMASK(0xFFFFFFFF, 0)
5657 #define MSIX_TVCTRL_PAGE(_i) (0x02E0000C + ((_i) * 16)) /* _i=0...2047 */ /* Reset Source: FLR */
5658 #define MSIX_TVCTRL_PAGE_MAX_INDEX 2047
5659 #define MSIX_TVCTRL_PAGE_MASK_S 0
5660 #define MSIX_TVCTRL_PAGE_MASK_M BIT(0)
5661 #define MSIX_TVCTRL1(_i) (0x0000000C + ((_i) * 16)) /* _i=0...2047 */ /* Reset Source: FLR */
5662 #define MSIX_TVCTRL1_MAX_INDEX 2047
5663 #define MSIX_TVCTRL1_MASK_S 0
5664 #define MSIX_TVCTRL1_MASK_M BIT(0)
5665 #define GLNVM_AL_DONE_HLP 0x000824C4 /* Reset Source: POR */
5666 #define GLNVM_AL_DONE_HLP_HLP_CORER_S 0
5667 #define GLNVM_AL_DONE_HLP_HLP_CORER_M BIT(0)
5668 #define GLNVM_AL_DONE_HLP_HLP_FULLR_S 1
5669 #define GLNVM_AL_DONE_HLP_HLP_FULLR_M BIT(1)
5670 #define GLNVM_ALTIMERS 0x000B6140 /* Reset Source: POR */
5671 #define GLNVM_ALTIMERS_PCI_ALTIMER_S 0
5672 #define GLNVM_ALTIMERS_PCI_ALTIMER_M MAKEMASK(0xFFF, 0)
5673 #define GLNVM_ALTIMERS_GEN_ALTIMER_S 12
5674 #define GLNVM_ALTIMERS_GEN_ALTIMER_M MAKEMASK(0xFFFFF, 12)
5675 #define GLNVM_FLA 0x000B6108 /* Reset Source: POR */
5676 #define GLNVM_FLA_LOCKED_S 6
5677 #define GLNVM_FLA_LOCKED_M BIT(6)
5678 #define GLNVM_GENS 0x000B6100 /* Reset Source: POR */
5679 #define GLNVM_GENS_NVM_PRES_S 0
5680 #define GLNVM_GENS_NVM_PRES_M BIT(0)
5681 #define GLNVM_GENS_SR_SIZE_S 5
5682 #define GLNVM_GENS_SR_SIZE_M MAKEMASK(0x7, 5)
5683 #define GLNVM_GENS_BANK1VAL_S 8
5684 #define GLNVM_GENS_BANK1VAL_M BIT(8)
5685 #define GLNVM_GENS_ALT_PRST_S 23
5686 #define GLNVM_GENS_ALT_PRST_M BIT(23)
5687 #define GLNVM_GENS_FL_AUTO_RD_S 25
5688 #define GLNVM_GENS_FL_AUTO_RD_M BIT(25)
5689 #define GLNVM_PROTCSR(_i) (0x000B6010 + ((_i) * 4)) /* _i=0...59 */ /* Reset Source: POR */
5690 #define GLNVM_PROTCSR_MAX_INDEX 59
5691 #define GLNVM_PROTCSR_ADDR_BLOCK_S 0
5692 #define GLNVM_PROTCSR_ADDR_BLOCK_M MAKEMASK(0xFFFFFF, 0)
5693 #define GLNVM_ULD 0x000B6008 /* Reset Source: POR */
5694 #define GLNVM_ULD_PCIER_DONE_S 0
5695 #define GLNVM_ULD_PCIER_DONE_M BIT(0)
5696 #define GLNVM_ULD_PCIER_DONE_1_S 1
5697 #define GLNVM_ULD_PCIER_DONE_1_M BIT(1)
5698 #define GLNVM_ULD_CORER_DONE_S 3
5699 #define GLNVM_ULD_CORER_DONE_M BIT(3)
5700 #define GLNVM_ULD_GLOBR_DONE_S 4
5701 #define GLNVM_ULD_GLOBR_DONE_M BIT(4)
5702 #define GLNVM_ULD_POR_DONE_S 5
5703 #define GLNVM_ULD_POR_DONE_M BIT(5)
5704 #define GLNVM_ULD_POR_DONE_1_S 8
5705 #define GLNVM_ULD_POR_DONE_1_M BIT(8)
5706 #define GLNVM_ULD_PCIER_DONE_2_S 9
5707 #define GLNVM_ULD_PCIER_DONE_2_M BIT(9)
5708 #define GLNVM_ULD_PE_DONE_S 10
5709 #define GLNVM_ULD_PE_DONE_M BIT(10)
5710 #define GLNVM_ULD_HLP_CORE_DONE_S 11
5711 #define GLNVM_ULD_HLP_CORE_DONE_M BIT(11)
5712 #define GLNVM_ULD_HLP_FULL_DONE_S 12
5713 #define GLNVM_ULD_HLP_FULL_DONE_M BIT(12)
5714 #define GLNVM_ULT 0x000B6154 /* Reset Source: POR */
5715 #define GLNVM_ULT_CONF_PCIR_AE_S 0
5716 #define GLNVM_ULT_CONF_PCIR_AE_M BIT(0)
5717 #define GLNVM_ULT_CONF_PCIRTL_AE_S 1
5718 #define GLNVM_ULT_CONF_PCIRTL_AE_M BIT(1)
5719 #define GLNVM_ULT_RESERVED_1_S 2
5720 #define GLNVM_ULT_RESERVED_1_M BIT(2)
5721 #define GLNVM_ULT_CONF_CORE_AE_S 3
5722 #define GLNVM_ULT_CONF_CORE_AE_M BIT(3)
5723 #define GLNVM_ULT_CONF_GLOBAL_AE_S 4
5724 #define GLNVM_ULT_CONF_GLOBAL_AE_M BIT(4)
5725 #define GLNVM_ULT_CONF_POR_AE_S 5
5726 #define GLNVM_ULT_CONF_POR_AE_M BIT(5)
5727 #define GLNVM_ULT_RESERVED_2_S 6
5728 #define GLNVM_ULT_RESERVED_2_M BIT(6)
5729 #define GLNVM_ULT_RESERVED_3_S 7
5730 #define GLNVM_ULT_RESERVED_3_M BIT(7)
5731 #define GLNVM_ULT_RESERVED_5_S 8
5732 #define GLNVM_ULT_RESERVED_5_M BIT(8)
5733 #define GLNVM_ULT_CONF_PCIALT_AE_S 9
5734 #define GLNVM_ULT_CONF_PCIALT_AE_M BIT(9)
5735 #define GLNVM_ULT_CONF_PE_AE_S 10
5736 #define GLNVM_ULT_CONF_PE_AE_M BIT(10)
5737 #define GLNVM_ULT_RESERVED_4_S 11
5738 #define GLNVM_ULT_RESERVED_4_M MAKEMASK(0x1FFFFF, 11)
5739 #define GL_COTF_MARKER_STATUS 0x00200200 /* Reset Source: CORER */
5740 #define GL_COTF_MARKER_STATUS_MRKR_BUSY_S 0
5741 #define GL_COTF_MARKER_STATUS_MRKR_BUSY_M MAKEMASK(0xFF, 0)
5742 #define GL_COTF_MARKER_TRIG_RCU_PRS(_i) (0x002001D4 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
5743 #define GL_COTF_MARKER_TRIG_RCU_PRS_MAX_INDEX 7
5744 #define GL_COTF_MARKER_TRIG_RCU_PRS_SET_RST_S 0
5745 #define GL_COTF_MARKER_TRIG_RCU_PRS_SET_RST_M BIT(0)
5746 #define GL_PRS_MARKER_ERROR 0x00200204 /* Reset Source: CORER */
5747 #define GL_PRS_MARKER_ERROR_XLR_CFG_ERR_S 0
5748 #define GL_PRS_MARKER_ERROR_XLR_CFG_ERR_M BIT(0)
5749 #define GL_PRS_MARKER_ERROR_QH_CFG_ERR_S 1
5750 #define GL_PRS_MARKER_ERROR_QH_CFG_ERR_M BIT(1)
5751 #define GL_PRS_MARKER_ERROR_COTF_CFG_ERR_S 2
5752 #define GL_PRS_MARKER_ERROR_COTF_CFG_ERR_M BIT(2)
5753 #define GL_PRS_RX_PIPE_INIT0(_i) (0x0020000C + ((_i) * 4)) /* _i=0...6 */ /* Reset Source: CORER */
5754 #define GL_PRS_RX_PIPE_INIT0_MAX_INDEX 6
5755 #define GL_PRS_RX_PIPE_INIT0_GPCSR_INIT_S 0
5756 #define GL_PRS_RX_PIPE_INIT0_GPCSR_INIT_M MAKEMASK(0xFFFF, 0)
5757 #define GL_PRS_RX_PIPE_INIT1 0x00200028 /* Reset Source: CORER */
5758 #define GL_PRS_RX_PIPE_INIT1_GPCSR_INIT_S 0
5759 #define GL_PRS_RX_PIPE_INIT1_GPCSR_INIT_M MAKEMASK(0xFFFF, 0)
5760 #define GL_PRS_RX_PIPE_INIT2 0x0020002C /* Reset Source: CORER */
5761 #define GL_PRS_RX_PIPE_INIT2_GPCSR_INIT_S 0
5762 #define GL_PRS_RX_PIPE_INIT2_GPCSR_INIT_M MAKEMASK(0xFFFF, 0)
5763 #define GL_PRS_RX_SIZE_CTRL 0x00200004 /* Reset Source: CORER */
5764 #define GL_PRS_RX_SIZE_CTRL_MIN_SIZE_S 0
5765 #define GL_PRS_RX_SIZE_CTRL_MIN_SIZE_M MAKEMASK(0x3FF, 0)
5766 #define GL_PRS_RX_SIZE_CTRL_MIN_SIZE_EN_S 15
5767 #define GL_PRS_RX_SIZE_CTRL_MIN_SIZE_EN_M BIT(15)
5768 #define GL_PRS_RX_SIZE_CTRL_MAX_SIZE_S 16
5769 #define GL_PRS_RX_SIZE_CTRL_MAX_SIZE_M MAKEMASK(0x3FF, 16)
5770 #define GL_PRS_RX_SIZE_CTRL_MAX_SIZE_EN_S 31
5771 #define GL_PRS_RX_SIZE_CTRL_MAX_SIZE_EN_M BIT(31)
5772 #define GL_PRS_TX_PIPE_INIT0(_i) (0x00202018 + ((_i) * 4)) /* _i=0...6 */ /* Reset Source: CORER */
5773 #define GL_PRS_TX_PIPE_INIT0_MAX_INDEX 6
5774 #define GL_PRS_TX_PIPE_INIT0_GPCSR_INIT_S 0
5775 #define GL_PRS_TX_PIPE_INIT0_GPCSR_INIT_M MAKEMASK(0xFFFF, 0)
5776 #define GL_PRS_TX_PIPE_INIT1 0x00202034 /* Reset Source: CORER */
5777 #define GL_PRS_TX_PIPE_INIT1_GPCSR_INIT_S 0
5778 #define GL_PRS_TX_PIPE_INIT1_GPCSR_INIT_M MAKEMASK(0xFFFF, 0)
5779 #define GL_PRS_TX_PIPE_INIT2 0x00202038 /* Reset Source: CORER */
5780 #define GL_PRS_TX_PIPE_INIT2_GPCSR_INIT_S 0
5781 #define GL_PRS_TX_PIPE_INIT2_GPCSR_INIT_M MAKEMASK(0xFFFF, 0)
5782 #define GL_PRS_TX_SIZE_CTRL 0x00202014 /* Reset Source: CORER */
5783 #define GL_PRS_TX_SIZE_CTRL_MIN_SIZE_S 0
5784 #define GL_PRS_TX_SIZE_CTRL_MIN_SIZE_M MAKEMASK(0x3FF, 0)
5785 #define GL_PRS_TX_SIZE_CTRL_MIN_SIZE_EN_S 15
5786 #define GL_PRS_TX_SIZE_CTRL_MIN_SIZE_EN_M BIT(15)
5787 #define GL_PRS_TX_SIZE_CTRL_MAX_SIZE_S 16
5788 #define GL_PRS_TX_SIZE_CTRL_MAX_SIZE_M MAKEMASK(0x3FF, 16)
5789 #define GL_PRS_TX_SIZE_CTRL_MAX_SIZE_EN_S 31
5790 #define GL_PRS_TX_SIZE_CTRL_MAX_SIZE_EN_M BIT(31)
5791 #define GL_QH_MARKER_STATUS 0x002001FC /* Reset Source: CORER */
5792 #define GL_QH_MARKER_STATUS_MRKR_BUSY_S 0
5793 #define GL_QH_MARKER_STATUS_MRKR_BUSY_M MAKEMASK(0xF, 0)
5794 #define GL_QH_MARKER_TRIG_RCU_PRS(_i) (0x002001C4 + ((_i) * 4)) /* _i=0...3 */ /* Reset Source: CORER */
5795 #define GL_QH_MARKER_TRIG_RCU_PRS_MAX_INDEX 3
5796 #define GL_QH_MARKER_TRIG_RCU_PRS_QPID_S 0
5797 #define GL_QH_MARKER_TRIG_RCU_PRS_QPID_M MAKEMASK(0x3FFFF, 0)
5798 #define GL_QH_MARKER_TRIG_RCU_PRS_PE_TAG_S 18
5799 #define GL_QH_MARKER_TRIG_RCU_PRS_PE_TAG_M MAKEMASK(0xFF, 18)
5800 #define GL_QH_MARKER_TRIG_RCU_PRS_PORT_NUM_S 26
5801 #define GL_QH_MARKER_TRIG_RCU_PRS_PORT_NUM_M MAKEMASK(0x7, 26)
5802 #define GL_QH_MARKER_TRIG_RCU_PRS_SET_RST_S 31
5803 #define GL_QH_MARKER_TRIG_RCU_PRS_SET_RST_M BIT(31)
5804 #define GL_RPRS_ANA_CSR_CTRL 0x00200708 /* Reset Source: CORER */
5805 #define GL_RPRS_ANA_CSR_CTRL_SELECT_EN_S 0
5806 #define GL_RPRS_ANA_CSR_CTRL_SELECT_EN_M BIT(0)
5807 #define GL_RPRS_ANA_CSR_CTRL_SELECTED_ANA_S 1
5808 #define GL_RPRS_ANA_CSR_CTRL_SELECTED_ANA_M BIT(1)
5809 #define GL_TPRS_ANA_CSR_CTRL 0x00202100 /* Reset Source: CORER */
5810 #define GL_TPRS_ANA_CSR_CTRL_SELECT_EN_S 0
5811 #define GL_TPRS_ANA_CSR_CTRL_SELECT_EN_M BIT(0)
5812 #define GL_TPRS_ANA_CSR_CTRL_SELECTED_ANA_S 1
5813 #define GL_TPRS_ANA_CSR_CTRL_SELECTED_ANA_M BIT(1)
5814 #define GL_TPRS_MNG_PM_THR 0x00202004 /* Reset Source: CORER */
5815 #define GL_TPRS_MNG_PM_THR_MNG_PM_THR_S 0
5816 #define GL_TPRS_MNG_PM_THR_MNG_PM_THR_M MAKEMASK(0x3FFF, 0)
5817 #define GL_TPRS_PM_CNT(_i) (0x00202008 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */
5818 #define GL_TPRS_PM_CNT_MAX_INDEX 1
5819 #define GL_TPRS_PM_CNT_GL_PRS_PM_CNT_S 0
5820 #define GL_TPRS_PM_CNT_GL_PRS_PM_CNT_M MAKEMASK(0x3FFF, 0)
5821 #define GL_TPRS_PM_THR 0x00202000 /* Reset Source: CORER */
5822 #define GL_TPRS_PM_THR_PM_THR_S 0
5823 #define GL_TPRS_PM_THR_PM_THR_M MAKEMASK(0x3FFF, 0)
5824 #define GL_XLR_MARKER_LOG_RCU_PRS(_i) (0x00200208 + ((_i) * 4)) /* _i=0...63 */ /* Reset Source: CORER */
5825 #define GL_XLR_MARKER_LOG_RCU_PRS_MAX_INDEX 63
5826 #define GL_XLR_MARKER_LOG_RCU_PRS_XLR_TRIG_S 0
5827 #define GL_XLR_MARKER_LOG_RCU_PRS_XLR_TRIG_M MAKEMASK(0xFFFFFFFF, 0)
5828 #define GL_XLR_MARKER_STATUS(_i) (0x002001F4 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */
5829 #define GL_XLR_MARKER_STATUS_MAX_INDEX 1
5830 #define GL_XLR_MARKER_STATUS_MRKR_BUSY_S 0
5831 #define GL_XLR_MARKER_STATUS_MRKR_BUSY_M MAKEMASK(0xFFFFFFFF, 0)
5832 #define GL_XLR_MARKER_TRIG_PE 0x005008C0 /* Reset Source: CORER */
5833 #define GL_XLR_MARKER_TRIG_PE_VM_VF_NUM_S 0
5834 #define GL_XLR_MARKER_TRIG_PE_VM_VF_NUM_M MAKEMASK(0x3FF, 0)
5835 #define GL_XLR_MARKER_TRIG_PE_VM_VF_TYPE_S 10
5836 #define GL_XLR_MARKER_TRIG_PE_VM_VF_TYPE_M MAKEMASK(0x3, 10)
5837 #define GL_XLR_MARKER_TRIG_PE_PF_NUM_S 12
5838 #define GL_XLR_MARKER_TRIG_PE_PF_NUM_M MAKEMASK(0x7, 12)
5839 #define GL_XLR_MARKER_TRIG_PE_PORT_NUM_S 16
5840 #define GL_XLR_MARKER_TRIG_PE_PORT_NUM_M MAKEMASK(0x7, 16)
5841 #define GL_XLR_MARKER_TRIG_RCU_PRS 0x002001C0 /* Reset Source: CORER */
5842 #define GL_XLR_MARKER_TRIG_RCU_PRS_VM_VF_NUM_S 0
5843 #define GL_XLR_MARKER_TRIG_RCU_PRS_VM_VF_NUM_M MAKEMASK(0x3FF, 0)
5844 #define GL_XLR_MARKER_TRIG_RCU_PRS_VM_VF_TYPE_S 10
5845 #define GL_XLR_MARKER_TRIG_RCU_PRS_VM_VF_TYPE_M MAKEMASK(0x3, 10)
5846 #define GL_XLR_MARKER_TRIG_RCU_PRS_PF_NUM_S 12
5847 #define GL_XLR_MARKER_TRIG_RCU_PRS_PF_NUM_M MAKEMASK(0x7, 12)
5848 #define GL_XLR_MARKER_TRIG_RCU_PRS_PORT_NUM_S 16
5849 #define GL_XLR_MARKER_TRIG_RCU_PRS_PORT_NUM_M MAKEMASK(0x7, 16)
5850 #define GL_CLKGATE_EVENTS 0x0009DE70 /* Reset Source: PERST */
5851 #define GL_CLKGATE_EVENTS_PRIMARY_CLKGATE_EVENTS_S 0
5852 #define GL_CLKGATE_EVENTS_PRIMARY_CLKGATE_EVENTS_M MAKEMASK(0xFFFF, 0)
5853 #define GL_CLKGATE_EVENTS_SIDEBAND_CLKGATE_EVENTS_S 16
5854 #define GL_CLKGATE_EVENTS_SIDEBAND_CLKGATE_EVENTS_M MAKEMASK(0xFFFF, 16)
5855 #define GLPCI_BYTCTH_NP_C 0x000BFDA8 /* Reset Source: PCIR */
5856 #define GLPCI_BYTCTH_NP_C_PCI_COUNT_BW_BCT_S 0
5857 #define GLPCI_BYTCTH_NP_C_PCI_COUNT_BW_BCT_M MAKEMASK(0xFFFFFFFF, 0)
5858 #define GLPCI_BYTCTH_P 0x0009E970 /* Reset Source: PCIR */
5859 #define GLPCI_BYTCTH_P_PCI_COUNT_BW_BCT_S 0
5860 #define GLPCI_BYTCTH_P_PCI_COUNT_BW_BCT_M MAKEMASK(0xFFFFFFFF, 0)
5861 #define GLPCI_BYTCTL_NP_C 0x000BFDAC /* Reset Source: PCIR */
5862 #define GLPCI_BYTCTL_NP_C_PCI_COUNT_BW_BCT_S 0
5863 #define GLPCI_BYTCTL_NP_C_PCI_COUNT_BW_BCT_M MAKEMASK(0xFFFFFFFF, 0)
5864 #define GLPCI_BYTCTL_P 0x0009E994 /* Reset Source: PCIR */
5865 #define GLPCI_BYTCTL_P_PCI_COUNT_BW_BCT_S 0
5866 #define GLPCI_BYTCTL_P_PCI_COUNT_BW_BCT_M MAKEMASK(0xFFFFFFFF, 0)
5867 #define GLPCI_CAPCTRL 0x0009DE88 /* Reset Source: PCIR */
5868 #define GLPCI_CAPCTRL_VPD_EN_S 0
5869 #define GLPCI_CAPCTRL_VPD_EN_M BIT(0)
5870 #define GLPCI_CAPSUP 0x0009DE8C /* Reset Source: PCIR */
5871 #define GLPCI_CAPSUP_PCIE_VER_S 0
5872 #define GLPCI_CAPSUP_PCIE_VER_M BIT(0)
5873 #define GLPCI_CAPSUP_RESERVED_2_S 1
5874 #define GLPCI_CAPSUP_RESERVED_2_M BIT(1)
5875 #define GLPCI_CAPSUP_LTR_EN_S 2
5876 #define GLPCI_CAPSUP_LTR_EN_M BIT(2)
5877 #define GLPCI_CAPSUP_TPH_EN_S 3
5878 #define GLPCI_CAPSUP_TPH_EN_M BIT(3)
5879 #define GLPCI_CAPSUP_ARI_EN_S 4
5880 #define GLPCI_CAPSUP_ARI_EN_M BIT(4)
5881 #define GLPCI_CAPSUP_IOV_EN_S 5
5882 #define GLPCI_CAPSUP_IOV_EN_M BIT(5)
5883 #define GLPCI_CAPSUP_ACS_EN_S 6
5884 #define GLPCI_CAPSUP_ACS_EN_M BIT(6)
5885 #define GLPCI_CAPSUP_SEC_EN_S 7
5886 #define GLPCI_CAPSUP_SEC_EN_M BIT(7)
5887 #define GLPCI_CAPSUP_PASID_EN_S 8
5888 #define GLPCI_CAPSUP_PASID_EN_M BIT(8)
5889 #define GLPCI_CAPSUP_DLFE_EN_S 9
5890 #define GLPCI_CAPSUP_DLFE_EN_M BIT(9)
5891 #define GLPCI_CAPSUP_GEN4_EXT_EN_S 10
5892 #define GLPCI_CAPSUP_GEN4_EXT_EN_M BIT(10)
5893 #define GLPCI_CAPSUP_GEN4_MARG_EN_S 11
5894 #define GLPCI_CAPSUP_GEN4_MARG_EN_M BIT(11)
5895 #define GLPCI_CAPSUP_ECRC_GEN_EN_S 16
5896 #define GLPCI_CAPSUP_ECRC_GEN_EN_M BIT(16)
5897 #define GLPCI_CAPSUP_ECRC_CHK_EN_S 17
5898 #define GLPCI_CAPSUP_ECRC_CHK_EN_M BIT(17)
5899 #define GLPCI_CAPSUP_IDO_EN_S 18
5900 #define GLPCI_CAPSUP_IDO_EN_M BIT(18)
5901 #define GLPCI_CAPSUP_MSI_MASK_S 19
5902 #define GLPCI_CAPSUP_MSI_MASK_M BIT(19)
5903 #define GLPCI_CAPSUP_CSR_CONF_EN_S 20
5904 #define GLPCI_CAPSUP_CSR_CONF_EN_M BIT(20)
5905 #define GLPCI_CAPSUP_WAKUP_EN_S 21
5906 #define GLPCI_CAPSUP_WAKUP_EN_M BIT(21)
5907 #define GLPCI_CAPSUP_LOAD_SUBSYS_ID_S 30
5908 #define GLPCI_CAPSUP_LOAD_SUBSYS_ID_M BIT(30)
5909 #define GLPCI_CAPSUP_LOAD_DEV_ID_S 31
5910 #define GLPCI_CAPSUP_LOAD_DEV_ID_M BIT(31)
5911 #define GLPCI_CNF 0x0009DEA0 /* Reset Source: POR */
5912 #define GLPCI_CNF_FLEX10_S 1
5913 #define GLPCI_CNF_FLEX10_M BIT(1)
5914 #define GLPCI_CNF_WAKE_PIN_EN_S 2
5915 #define GLPCI_CNF_WAKE_PIN_EN_M BIT(2)
5916 #define GLPCI_CNF_MSIX_ECC_BLOCK_DISABLE_S 3
5917 #define GLPCI_CNF_MSIX_ECC_BLOCK_DISABLE_M BIT(3)
5918 #define GLPCI_CNF2 0x000BE004 /* Reset Source: PCIR */
5919 #define GLPCI_CNF2_RO_DIS_S 0
5920 #define GLPCI_CNF2_RO_DIS_M BIT(0)
5921 #define GLPCI_CNF2_CACHELINE_SIZE_S 1
5922 #define GLPCI_CNF2_CACHELINE_SIZE_M BIT(1)
5923 #define GLPCI_DREVID 0x0009E9AC /* Reset Source: PCIR */
5924 #define GLPCI_DREVID_DEFAULT_REVID_S 0
5925 #define GLPCI_DREVID_DEFAULT_REVID_M MAKEMASK(0xFF, 0)
5926 #define GLPCI_GSCL_1_NP_C 0x000BFDA4 /* Reset Source: PCIR */
5927 #define GLPCI_GSCL_1_NP_C_RT_MODE_S 8
5928 #define GLPCI_GSCL_1_NP_C_RT_MODE_M BIT(8)
5929 #define GLPCI_GSCL_1_NP_C_RT_EVENT_S 9
5930 #define GLPCI_GSCL_1_NP_C_RT_EVENT_M MAKEMASK(0x1F, 9)
5931 #define GLPCI_GSCL_1_NP_C_PCI_COUNT_BW_EN_S 14
5932 #define GLPCI_GSCL_1_NP_C_PCI_COUNT_BW_EN_M BIT(14)
5933 #define GLPCI_GSCL_1_NP_C_PCI_COUNT_BW_EV_S 15
5934 #define GLPCI_GSCL_1_NP_C_PCI_COUNT_BW_EV_M MAKEMASK(0x1F, 15)
5935 #define GLPCI_GSCL_1_NP_C_GIO_COUNT_RESET_S 29
5936 #define GLPCI_GSCL_1_NP_C_GIO_COUNT_RESET_M BIT(29)
5937 #define GLPCI_GSCL_1_NP_C_GIO_COUNT_STOP_S 30
5938 #define GLPCI_GSCL_1_NP_C_GIO_COUNT_STOP_M BIT(30)
5939 #define GLPCI_GSCL_1_NP_C_GIO_COUNT_START_S 31
5940 #define GLPCI_GSCL_1_NP_C_GIO_COUNT_START_M BIT(31)
5941 #define GLPCI_GSCL_1_P 0x0009E9B4 /* Reset Source: PCIR */
5942 #define GLPCI_GSCL_1_P_GIO_COUNT_EN_0_S 0
5943 #define GLPCI_GSCL_1_P_GIO_COUNT_EN_0_M BIT(0)
5944 #define GLPCI_GSCL_1_P_GIO_COUNT_EN_1_S 1
5945 #define GLPCI_GSCL_1_P_GIO_COUNT_EN_1_M BIT(1)
5946 #define GLPCI_GSCL_1_P_GIO_COUNT_EN_2_S 2
5947 #define GLPCI_GSCL_1_P_GIO_COUNT_EN_2_M BIT(2)
5948 #define GLPCI_GSCL_1_P_GIO_COUNT_EN_3_S 3
5949 #define GLPCI_GSCL_1_P_GIO_COUNT_EN_3_M BIT(3)
5950 #define GLPCI_GSCL_1_P_LBC_ENABLE_0_S 4
5951 #define GLPCI_GSCL_1_P_LBC_ENABLE_0_M BIT(4)
5952 #define GLPCI_GSCL_1_P_LBC_ENABLE_1_S 5
5953 #define GLPCI_GSCL_1_P_LBC_ENABLE_1_M BIT(5)
5954 #define GLPCI_GSCL_1_P_LBC_ENABLE_2_S 6
5955 #define GLPCI_GSCL_1_P_LBC_ENABLE_2_M BIT(6)
5956 #define GLPCI_GSCL_1_P_LBC_ENABLE_3_S 7
5957 #define GLPCI_GSCL_1_P_LBC_ENABLE_3_M BIT(7)
5958 #define GLPCI_GSCL_1_P_PCI_COUNT_BW_EN_S 14
5959 #define GLPCI_GSCL_1_P_PCI_COUNT_BW_EN_M BIT(14)
5960 #define GLPCI_GSCL_1_P_GIO_64_BIT_EN_S 28
5961 #define GLPCI_GSCL_1_P_GIO_64_BIT_EN_M BIT(28)
5962 #define GLPCI_GSCL_1_P_GIO_COUNT_RESET_S 29
5963 #define GLPCI_GSCL_1_P_GIO_COUNT_RESET_M BIT(29)
5964 #define GLPCI_GSCL_1_P_GIO_COUNT_STOP_S 30
5965 #define GLPCI_GSCL_1_P_GIO_COUNT_STOP_M BIT(30)
5966 #define GLPCI_GSCL_1_P_GIO_COUNT_START_S 31
5967 #define GLPCI_GSCL_1_P_GIO_COUNT_START_M BIT(31)
5968 #define GLPCI_GSCL_2 0x0009E998 /* Reset Source: PCIR */
5969 #define GLPCI_GSCL_2_GIO_EVENT_NUM_0_S 0
5970 #define GLPCI_GSCL_2_GIO_EVENT_NUM_0_M MAKEMASK(0xFF, 0)
5971 #define GLPCI_GSCL_2_GIO_EVENT_NUM_1_S 8
5972 #define GLPCI_GSCL_2_GIO_EVENT_NUM_1_M MAKEMASK(0xFF, 8)
5973 #define GLPCI_GSCL_2_GIO_EVENT_NUM_2_S 16
5974 #define GLPCI_GSCL_2_GIO_EVENT_NUM_2_M MAKEMASK(0xFF, 16)
5975 #define GLPCI_GSCL_2_GIO_EVENT_NUM_3_S 24
5976 #define GLPCI_GSCL_2_GIO_EVENT_NUM_3_M MAKEMASK(0xFF, 24)
5977 #define GLPCI_GSCL_5_8(_i) (0x0009E954 + ((_i) * 4)) /* _i=0...3 */ /* Reset Source: PCIR */
5978 #define GLPCI_GSCL_5_8_MAX_INDEX 3
5979 #define GLPCI_GSCL_5_8_LBC_THRESHOLD_N_S 0
5980 #define GLPCI_GSCL_5_8_LBC_THRESHOLD_N_M MAKEMASK(0xFFFF, 0)
5981 #define GLPCI_GSCL_5_8_LBC_TIMER_N_S 16
5982 #define GLPCI_GSCL_5_8_LBC_TIMER_N_M MAKEMASK(0xFFFF, 16)
5983 #define GLPCI_GSCN_0_3(_i) (0x0009E99C + ((_i) * 4)) /* _i=0...3 */ /* Reset Source: PCIR */
5984 #define GLPCI_GSCN_0_3_MAX_INDEX 3
5985 #define GLPCI_GSCN_0_3_EVENT_COUNTER_S 0
5986 #define GLPCI_GSCN_0_3_EVENT_COUNTER_M MAKEMASK(0xFFFFFFFF, 0)
5987 #define GLPCI_LATCT_NP_C 0x000BFDA0 /* Reset Source: PCIR */
5988 #define GLPCI_LATCT_NP_C_PCI_LATENCY_COUNT_S 0
5989 #define GLPCI_LATCT_NP_C_PCI_LATENCY_COUNT_M MAKEMASK(0xFFFFFFFF, 0)
5990 #define GLPCI_LBARCTRL 0x0009DE74 /* Reset Source: POR */
5991 #define GLPCI_LBARCTRL_PREFBAR_S 0
5992 #define GLPCI_LBARCTRL_PREFBAR_M BIT(0)
5993 #define GLPCI_LBARCTRL_BAR32_S 1
5994 #define GLPCI_LBARCTRL_BAR32_M BIT(1)
5995 #define GLPCI_LBARCTRL_PAGES_SPACE_EN_PF_S 2
5996 #define GLPCI_LBARCTRL_PAGES_SPACE_EN_PF_M BIT(2)
5997 #define GLPCI_LBARCTRL_FLASH_EXPOSE_S 3
5998 #define GLPCI_LBARCTRL_FLASH_EXPOSE_M BIT(3)
5999 #define GLPCI_LBARCTRL_PE_DB_SIZE_S 4
6000 #define GLPCI_LBARCTRL_PE_DB_SIZE_M MAKEMASK(0x3, 4)
6001 #define GLPCI_LBARCTRL_PAGES_SPACE_EN_VF_S 9
6002 #define GLPCI_LBARCTRL_PAGES_SPACE_EN_VF_M BIT(9)
6003 #define GLPCI_LBARCTRL_EXROM_SIZE_S 11
6004 #define GLPCI_LBARCTRL_EXROM_SIZE_M MAKEMASK(0x7, 11)
6005 #define GLPCI_LBARCTRL_VF_PE_DB_SIZE_S 14
6006 #define GLPCI_LBARCTRL_VF_PE_DB_SIZE_M MAKEMASK(0x3, 14)
6007 #define GLPCI_LINKCAP 0x0009DE90 /* Reset Source: PCIR */
6008 #define GLPCI_LINKCAP_LINK_SPEEDS_VECTOR_S 0
6009 #define GLPCI_LINKCAP_LINK_SPEEDS_VECTOR_M MAKEMASK(0x3F, 0)
6010 #define GLPCI_LINKCAP_MAX_LINK_WIDTH_S 9
6011 #define GLPCI_LINKCAP_MAX_LINK_WIDTH_M MAKEMASK(0xF, 9)
6012 #define GLPCI_NPQ_CFG 0x000BFD80 /* Reset Source: PCIR */
6013 #define GLPCI_NPQ_CFG_EXTEND_TO_S 0
6014 #define GLPCI_NPQ_CFG_EXTEND_TO_M BIT(0)
6015 #define GLPCI_NPQ_CFG_SMALL_TO_S 1
6016 #define GLPCI_NPQ_CFG_SMALL_TO_M BIT(1)
6017 #define GLPCI_NPQ_CFG_WEIGHT_AVG_S 2
6018 #define GLPCI_NPQ_CFG_WEIGHT_AVG_M MAKEMASK(0xF, 2)
6019 #define GLPCI_NPQ_CFG_NPQ_SPARE_S 6
6020 #define GLPCI_NPQ_CFG_NPQ_SPARE_M MAKEMASK(0x3FF, 6)
6021 #define GLPCI_NPQ_CFG_NPQ_ERR_STAT_S 16
6022 #define GLPCI_NPQ_CFG_NPQ_ERR_STAT_M MAKEMASK(0xF, 16)
6023 #define GLPCI_PKTCT_NP_C 0x000BFD9C /* Reset Source: PCIR */
6024 #define GLPCI_PKTCT_NP_C_PCI_COUNT_BW_PCT_S 0
6025 #define GLPCI_PKTCT_NP_C_PCI_COUNT_BW_PCT_M MAKEMASK(0xFFFFFFFF, 0)
6026 #define GLPCI_PKTCT_P 0x0009E9B0 /* Reset Source: PCIR */
6027 #define GLPCI_PKTCT_P_PCI_COUNT_BW_PCT_S 0
6028 #define GLPCI_PKTCT_P_PCI_COUNT_BW_PCT_M MAKEMASK(0xFFFFFFFF, 0)
6029 #define GLPCI_PMSUP 0x0009DE94 /* Reset Source: PCIR */
6030 #define GLPCI_PMSUP_RESERVED_0_S 0
6031 #define GLPCI_PMSUP_RESERVED_0_M MAKEMASK(0x3, 0)
6032 #define GLPCI_PMSUP_RESERVED_1_S 2
6033 #define GLPCI_PMSUP_RESERVED_1_M MAKEMASK(0x7, 2)
6034 #define GLPCI_PMSUP_RESERVED_2_S 5
6035 #define GLPCI_PMSUP_RESERVED_2_M MAKEMASK(0x7, 5)
6036 #define GLPCI_PMSUP_L0S_ACC_LAT_S 8
6037 #define GLPCI_PMSUP_L0S_ACC_LAT_M MAKEMASK(0x7, 8)
6038 #define GLPCI_PMSUP_L1_ACC_LAT_S 11
6039 #define GLPCI_PMSUP_L1_ACC_LAT_M MAKEMASK(0x7, 11)
6040 #define GLPCI_PMSUP_RESERVED_3_S 14
6041 #define GLPCI_PMSUP_RESERVED_3_M BIT(14)
6042 #define GLPCI_PMSUP_OBFF_SUP_S 15
6043 #define GLPCI_PMSUP_OBFF_SUP_M MAKEMASK(0x3, 15)
6044 #define GLPCI_PUSH_PE_IF_TO_STATUS 0x0009DF44 /* Reset Source: PCIR */
6045 #define GLPCI_PUSH_PE_IF_TO_STATUS_GLPCI_PUSH_PE_IF_TO_STATUS_S 0
6046 #define GLPCI_PUSH_PE_IF_TO_STATUS_GLPCI_PUSH_PE_IF_TO_STATUS_M BIT(0)
6047 #define GLPCI_PWRDATA 0x0009DE7C /* Reset Source: PCIR */
6048 #define GLPCI_PWRDATA_D0_POWER_S 0
6049 #define GLPCI_PWRDATA_D0_POWER_M MAKEMASK(0xFF, 0)
6050 #define GLPCI_PWRDATA_COMM_POWER_S 8
6051 #define GLPCI_PWRDATA_COMM_POWER_M MAKEMASK(0xFF, 8)
6052 #define GLPCI_PWRDATA_D3_POWER_S 16
6053 #define GLPCI_PWRDATA_D3_POWER_M MAKEMASK(0xFF, 16)
6054 #define GLPCI_PWRDATA_DATA_SCALE_S 24
6055 #define GLPCI_PWRDATA_DATA_SCALE_M MAKEMASK(0x3, 24)
6056 #define GLPCI_REVID 0x0009DE98 /* Reset Source: PCIR */
6057 #define GLPCI_REVID_NVM_REVID_S 0
6058 #define GLPCI_REVID_NVM_REVID_M MAKEMASK(0xFF, 0)
6059 #define GLPCI_SERH 0x0009DE84 /* Reset Source: PCIR */
6060 #define GLPCI_SERH_SER_NUM_H_S 0
6061 #define GLPCI_SERH_SER_NUM_H_M MAKEMASK(0xFFFF, 0)
6062 #define GLPCI_SERL 0x0009DE80 /* Reset Source: PCIR */
6063 #define GLPCI_SERL_SER_NUM_L_S 0
6064 #define GLPCI_SERL_SER_NUM_L_M MAKEMASK(0xFFFFFFFF, 0)
6065 #define GLPCI_SUBVENID 0x0009DEE8 /* Reset Source: PCIR */
6066 #define GLPCI_SUBVENID_SUB_VEN_ID_S 0
6067 #define GLPCI_SUBVENID_SUB_VEN_ID_M MAKEMASK(0xFFFF, 0)
6068 #define GLPCI_UPADD 0x000BE0D4 /* Reset Source: PCIR */
6069 #define GLPCI_UPADD_ADDRESS_S 1
6070 #define GLPCI_UPADD_ADDRESS_M MAKEMASK(0x7FFFFFFF, 1)
6071 #define GLPCI_VENDORID 0x0009DEC8 /* Reset Source: PCIR */
6072 #define GLPCI_VENDORID_VENDORID_S 0
6073 #define GLPCI_VENDORID_VENDORID_M MAKEMASK(0xFFFF, 0)
6074 #define GLPCI_VFSUP 0x0009DE9C /* Reset Source: PCIR */
6075 #define GLPCI_VFSUP_VF_PREFETCH_S 0
6076 #define GLPCI_VFSUP_VF_PREFETCH_M BIT(0)
6077 #define GLPCI_VFSUP_VR_BAR_TYPE_S 1
6078 #define GLPCI_VFSUP_VR_BAR_TYPE_M BIT(1)
6079 #define GLPCI_WATMK_CLNT_PIPEMON 0x000BFD90 /* Reset Source: PCIR */
6080 #define GLPCI_WATMK_CLNT_PIPEMON_DATA_LINES_S 0
6081 #define GLPCI_WATMK_CLNT_PIPEMON_DATA_LINES_M MAKEMASK(0xFFFF, 0)
6082 #define PF_FUNC_RID 0x0009E880 /* Reset Source: PCIR */
6083 #define PF_FUNC_RID_FUNCTION_NUMBER_S 0
6084 #define PF_FUNC_RID_FUNCTION_NUMBER_M MAKEMASK(0x7, 0)
6085 #define PF_FUNC_RID_DEVICE_NUMBER_S 3
6086 #define PF_FUNC_RID_DEVICE_NUMBER_M MAKEMASK(0x1F, 3)
6087 #define PF_FUNC_RID_BUS_NUMBER_S 8
6088 #define PF_FUNC_RID_BUS_NUMBER_M MAKEMASK(0xFF, 8)
6089 #define PF_PCI_CIAA 0x0009E580 /* Reset Source: FLR */
6090 #define PF_PCI_CIAA_ADDRESS_S 0
6091 #define PF_PCI_CIAA_ADDRESS_M MAKEMASK(0xFFF, 0)
6092 #define PF_PCI_CIAA_VF_NUM_S 12
6093 #define PF_PCI_CIAA_VF_NUM_M MAKEMASK(0xFF, 12)
6094 #define PF_PCI_CIAD 0x0009E500 /* Reset Source: FLR */
6095 #define PF_PCI_CIAD_DATA_S 0
6096 #define PF_PCI_CIAD_DATA_M MAKEMASK(0xFFFFFFFF, 0)
6097 #define PFPCI_CLASS 0x0009DB00 /* Reset Source: PCIR */
6098 #define PFPCI_CLASS_STORAGE_CLASS_S 0
6099 #define PFPCI_CLASS_STORAGE_CLASS_M BIT(0)
6100 #define PFPCI_CLASS_PF_IS_LAN_S 2
6101 #define PFPCI_CLASS_PF_IS_LAN_M BIT(2)
6102 #define PFPCI_CNF 0x0009DF00 /* Reset Source: PCIR */
6103 #define PFPCI_CNF_MSI_EN_S 2
6104 #define PFPCI_CNF_MSI_EN_M BIT(2)
6105 #define PFPCI_CNF_EXROM_DIS_S 3
6106 #define PFPCI_CNF_EXROM_DIS_M BIT(3)
6107 #define PFPCI_CNF_IO_BAR_S 4
6108 #define PFPCI_CNF_IO_BAR_M BIT(4)
6109 #define PFPCI_CNF_INT_PIN_S 5
6110 #define PFPCI_CNF_INT_PIN_M MAKEMASK(0x3, 5)
6111 #define PFPCI_DEVID 0x0009DE00 /* Reset Source: PCIR */
6112 #define PFPCI_DEVID_PF_DEV_ID_S 0
6113 #define PFPCI_DEVID_PF_DEV_ID_M MAKEMASK(0xFFFF, 0)
6114 #define PFPCI_DEVID_VF_DEV_ID_S 16
6115 #define PFPCI_DEVID_VF_DEV_ID_M MAKEMASK(0xFFFF, 16)
6116 #define PFPCI_FACTPS 0x0009E900 /* Reset Source: FLR */
6117 #define PFPCI_FACTPS_FUNC_POWER_STATE_S 0
6118 #define PFPCI_FACTPS_FUNC_POWER_STATE_M MAKEMASK(0x3, 0)
6119 #define PFPCI_FACTPS_FUNC_AUX_EN_S 3
6120 #define PFPCI_FACTPS_FUNC_AUX_EN_M BIT(3)
6121 #define PFPCI_FUNC 0x0009D980 /* Reset Source: POR */
6122 #define PFPCI_FUNC_FUNC_DIS_S 0
6123 #define PFPCI_FUNC_FUNC_DIS_M BIT(0)
6124 #define PFPCI_FUNC_ALLOW_FUNC_DIS_S 1
6125 #define PFPCI_FUNC_ALLOW_FUNC_DIS_M BIT(1)
6126 #define PFPCI_FUNC_DIS_FUNC_ON_PORT_DIS_S 2
6127 #define PFPCI_FUNC_DIS_FUNC_ON_PORT_DIS_M BIT(2)
6128 #define PFPCI_PF_FLUSH_DONE 0x0009E400 /* Reset Source: PCIR */
6129 #define PFPCI_PF_FLUSH_DONE_FLUSH_DONE_S 0
6130 #define PFPCI_PF_FLUSH_DONE_FLUSH_DONE_M BIT(0)
6131 #define PFPCI_PM 0x0009DA80 /* Reset Source: POR */
6132 #define PFPCI_PM_PME_EN_S 0
6133 #define PFPCI_PM_PME_EN_M BIT(0)
6134 #define PFPCI_STATUS1 0x0009DA00 /* Reset Source: POR */
6135 #define PFPCI_STATUS1_FUNC_VALID_S 0
6136 #define PFPCI_STATUS1_FUNC_VALID_M BIT(0)
6137 #define PFPCI_SUBSYSID 0x0009D880 /* Reset Source: PCIR */
6138 #define PFPCI_SUBSYSID_PF_SUBSYS_ID_S 0
6139 #define PFPCI_SUBSYSID_PF_SUBSYS_ID_M MAKEMASK(0xFFFF, 0)
6140 #define PFPCI_SUBSYSID_VF_SUBSYS_ID_S 16
6141 #define PFPCI_SUBSYSID_VF_SUBSYS_ID_M MAKEMASK(0xFFFF, 16)
6142 #define PFPCI_VF_FLUSH_DONE(_VF) (0x0009E000 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: PCIR */
6143 #define PFPCI_VF_FLUSH_DONE_MAX_INDEX 255
6144 #define PFPCI_VF_FLUSH_DONE_FLUSH_DONE_S 0
6145 #define PFPCI_VF_FLUSH_DONE_FLUSH_DONE_M BIT(0)
6146 #define PFPCI_VM_FLUSH_DONE 0x0009E480 /* Reset Source: PCIR */
6147 #define PFPCI_VM_FLUSH_DONE_FLUSH_DONE_S 0
6148 #define PFPCI_VM_FLUSH_DONE_FLUSH_DONE_M BIT(0)
6149 #define PFPCI_VMINDEX 0x0009E600 /* Reset Source: PCIR */
6150 #define PFPCI_VMINDEX_VMINDEX_S 0
6151 #define PFPCI_VMINDEX_VMINDEX_M MAKEMASK(0x3FF, 0)
6152 #define PFPCI_VMPEND 0x0009E800 /* Reset Source: PCIR */
6153 #define PFPCI_VMPEND_PENDING_S 0
6154 #define PFPCI_VMPEND_PENDING_M BIT(0)
6155 #define PQ_FIFO_STATUS 0x0009DF40 /* Reset Source: PCIR */
6156 #define PQ_FIFO_STATUS_PQ_FIFO_COUNT_S 0
6157 #define PQ_FIFO_STATUS_PQ_FIFO_COUNT_M MAKEMASK(0x7FFFFFFF, 0)
6158 #define PQ_FIFO_STATUS_PQ_FIFO_EMPTY_S 31
6159 #define PQ_FIFO_STATUS_PQ_FIFO_EMPTY_M BIT(31)
6160 #define GLPE_CPUSTATUS0 0x0050BA5C /* Reset Source: CORER */
6161 #define GLPE_CPUSTATUS0_PECPUSTATUS0_S 0
6162 #define GLPE_CPUSTATUS0_PECPUSTATUS0_M MAKEMASK(0xFFFFFFFF, 0)
6163 #define GLPE_CPUSTATUS1 0x0050BA60 /* Reset Source: CORER */
6164 #define GLPE_CPUSTATUS1_PECPUSTATUS1_S 0
6165 #define GLPE_CPUSTATUS1_PECPUSTATUS1_M MAKEMASK(0xFFFFFFFF, 0)
6166 #define GLPE_CPUSTATUS2 0x0050BA64 /* Reset Source: CORER */
6167 #define GLPE_CPUSTATUS2_PECPUSTATUS2_S 0
6168 #define GLPE_CPUSTATUS2_PECPUSTATUS2_M MAKEMASK(0xFFFFFFFF, 0)
6169 #define GLPE_MDQ_BASE(_i) (0x00536000 + ((_i) * 4)) /* _i=0...511 */ /* Reset Source: CORER */
6170 #define GLPE_MDQ_BASE_MAX_INDEX 511
6171 #define GLPE_MDQ_BASE_MDOC_INDEX_S 0
6172 #define GLPE_MDQ_BASE_MDOC_INDEX_M MAKEMASK(0xFFFFFFF, 0)
6173 #define GLPE_MDQ_PTR(_i) (0x00537000 + ((_i) * 4)) /* _i=0...511 */ /* Reset Source: CORER */
6174 #define GLPE_MDQ_PTR_MAX_INDEX 511
6175 #define GLPE_MDQ_PTR_MDQ_HEAD_S 0
6176 #define GLPE_MDQ_PTR_MDQ_HEAD_M MAKEMASK(0x3FFF, 0)
6177 #define GLPE_MDQ_PTR_MDQ_TAIL_S 16
6178 #define GLPE_MDQ_PTR_MDQ_TAIL_M MAKEMASK(0x3FFF, 16)
6179 #define GLPE_MDQ_SIZE(_i) (0x00536800 + ((_i) * 4)) /* _i=0...511 */ /* Reset Source: CORER */
6180 #define GLPE_MDQ_SIZE_MAX_INDEX 511
6181 #define GLPE_MDQ_SIZE_MDQ_SIZE_S 0
6182 #define GLPE_MDQ_SIZE_MDQ_SIZE_M MAKEMASK(0x3FFF, 0)
6183 #define GLPE_PEPM_CTRL 0x0050C000 /* Reset Source: PERST */
6184 #define GLPE_PEPM_CTRL_PEPM_ENABLE_S 0
6185 #define GLPE_PEPM_CTRL_PEPM_ENABLE_M BIT(0)
6186 #define GLPE_PEPM_CTRL_PEPM_HALT_S 8
6187 #define GLPE_PEPM_CTRL_PEPM_HALT_M BIT(8)
6188 #define GLPE_PEPM_CTRL_PEPM_PUSH_MARGIN_S 16
6189 #define GLPE_PEPM_CTRL_PEPM_PUSH_MARGIN_M MAKEMASK(0xFF, 16)
6190 #define GLPE_PEPM_DEALLOC 0x0050C004 /* Reset Source: PERST */
6191 #define GLPE_PEPM_DEALLOC_MDQ_CREDITS_S 0
6192 #define GLPE_PEPM_DEALLOC_MDQ_CREDITS_M MAKEMASK(0x3FFF, 0)
6193 #define GLPE_PEPM_DEALLOC_PSQ_CREDITS_S 14
6194 #define GLPE_PEPM_DEALLOC_PSQ_CREDITS_M MAKEMASK(0x1F, 14)
6195 #define GLPE_PEPM_DEALLOC_PQID_S 19
6196 #define GLPE_PEPM_DEALLOC_PQID_M MAKEMASK(0x1FF, 19)
6197 #define GLPE_PEPM_DEALLOC_PORT_S 28
6198 #define GLPE_PEPM_DEALLOC_PORT_M MAKEMASK(0x7, 28)
6199 #define GLPE_PEPM_DEALLOC_DEALLOC_RDY_S 31
6200 #define GLPE_PEPM_DEALLOC_DEALLOC_RDY_M BIT(31)
6201 #define GLPE_PEPM_PSQ_COUNT 0x0050C020 /* Reset Source: PERST */
6202 #define GLPE_PEPM_PSQ_COUNT_PEPM_PSQ_COUNT_S 0
6203 #define GLPE_PEPM_PSQ_COUNT_PEPM_PSQ_COUNT_M MAKEMASK(0xFFFF, 0)
6204 #define GLPE_PEPM_THRESH(_i) (0x0050C840 + ((_i) * 4)) /* _i=0...511 */ /* Reset Source: PERST */
6205 #define GLPE_PEPM_THRESH_MAX_INDEX 511
6206 #define GLPE_PEPM_THRESH_PEPM_PSQ_THRESH_S 0
6207 #define GLPE_PEPM_THRESH_PEPM_PSQ_THRESH_M MAKEMASK(0x1F, 0)
6208 #define GLPE_PEPM_THRESH_PEPM_MDQ_THRESH_S 16
6209 #define GLPE_PEPM_THRESH_PEPM_MDQ_THRESH_M MAKEMASK(0x3FFF, 16)
6210 #define GLPE_PFAEQEDROPCNT(_i) (0x00503240 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
6211 #define GLPE_PFAEQEDROPCNT_MAX_INDEX 7
6212 #define GLPE_PFAEQEDROPCNT_AEQEDROPCNT_S 0
6213 #define GLPE_PFAEQEDROPCNT_AEQEDROPCNT_M MAKEMASK(0xFFFF, 0)
6214 #define GLPE_PFCEQEDROPCNT(_i) (0x00503220 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
6215 #define GLPE_PFCEQEDROPCNT_MAX_INDEX 7
6216 #define GLPE_PFCEQEDROPCNT_CEQEDROPCNT_S 0
6217 #define GLPE_PFCEQEDROPCNT_CEQEDROPCNT_M MAKEMASK(0xFFFF, 0)
6218 #define GLPE_PFCQEDROPCNT(_i) (0x00503200 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
6219 #define GLPE_PFCQEDROPCNT_MAX_INDEX 7
6220 #define GLPE_PFCQEDROPCNT_CQEDROPCNT_S 0
6221 #define GLPE_PFCQEDROPCNT_CQEDROPCNT_M MAKEMASK(0xFFFF, 0)
6222 #define GLPE_PFFLMOOISCALLOCERR(_i) (0x0050B960 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
6223 #define GLPE_PFFLMOOISCALLOCERR_MAX_INDEX 7
6224 #define GLPE_PFFLMOOISCALLOCERR_ERROR_COUNT_S 0
6225 #define GLPE_PFFLMOOISCALLOCERR_ERROR_COUNT_M MAKEMASK(0xFFFF, 0)
6226 #define GLPE_PFFLMQ1ALLOCERR(_i) (0x0050B920 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
6227 #define GLPE_PFFLMQ1ALLOCERR_MAX_INDEX 7
6228 #define GLPE_PFFLMQ1ALLOCERR_ERROR_COUNT_S 0
6229 #define GLPE_PFFLMQ1ALLOCERR_ERROR_COUNT_M MAKEMASK(0xFFFF, 0)
6230 #define GLPE_PFFLMRRFALLOCERR(_i) (0x0050B940 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
6231 #define GLPE_PFFLMRRFALLOCERR_MAX_INDEX 7
6232 #define GLPE_PFFLMRRFALLOCERR_ERROR_COUNT_S 0
6233 #define GLPE_PFFLMRRFALLOCERR_ERROR_COUNT_M MAKEMASK(0xFFFF, 0)
6234 #define GLPE_PFFLMXMITALLOCERR(_i) (0x0050B900 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
6235 #define GLPE_PFFLMXMITALLOCERR_MAX_INDEX 7
6236 #define GLPE_PFFLMXMITALLOCERR_ERROR_COUNT_S 0
6237 #define GLPE_PFFLMXMITALLOCERR_ERROR_COUNT_M MAKEMASK(0xFFFF, 0)
6238 #define GLPE_PFTCPNOW50USCNT(_i) (0x0050B8C0 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
6239 #define GLPE_PFTCPNOW50USCNT_MAX_INDEX 7
6240 #define GLPE_PFTCPNOW50USCNT_CNT_S 0
6241 #define GLPE_PFTCPNOW50USCNT_CNT_M MAKEMASK(0xFFFFFFFF, 0)
6242 #define GLPE_PUSH_PEPM 0x0053241C /* Reset Source: CORER */
6243 #define GLPE_PUSH_PEPM_MDQ_CREDITS_S 0
6244 #define GLPE_PUSH_PEPM_MDQ_CREDITS_M MAKEMASK(0xFF, 0)
6245 #define GLPE_VFAEQEDROPCNT(_i) (0x00503100 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
6246 #define GLPE_VFAEQEDROPCNT_MAX_INDEX 31
6247 #define GLPE_VFAEQEDROPCNT_AEQEDROPCNT_S 0
6248 #define GLPE_VFAEQEDROPCNT_AEQEDROPCNT_M MAKEMASK(0xFFFF, 0)
6249 #define GLPE_VFCEQEDROPCNT(_i) (0x00503080 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
6250 #define GLPE_VFCEQEDROPCNT_MAX_INDEX 31
6251 #define GLPE_VFCEQEDROPCNT_CEQEDROPCNT_S 0
6252 #define GLPE_VFCEQEDROPCNT_CEQEDROPCNT_M MAKEMASK(0xFFFF, 0)
6253 #define GLPE_VFCQEDROPCNT(_i) (0x00503000 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
6254 #define GLPE_VFCQEDROPCNT_MAX_INDEX 31
6255 #define GLPE_VFCQEDROPCNT_CQEDROPCNT_S 0
6256 #define GLPE_VFCQEDROPCNT_CQEDROPCNT_M MAKEMASK(0xFFFF, 0)
6257 #define GLPE_VFFLMOOISCALLOCERR(_i) (0x0050B580 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
6258 #define GLPE_VFFLMOOISCALLOCERR_MAX_INDEX 31
6259 #define GLPE_VFFLMOOISCALLOCERR_ERROR_COUNT_S 0
6260 #define GLPE_VFFLMOOISCALLOCERR_ERROR_COUNT_M MAKEMASK(0xFFFF, 0)
6261 #define GLPE_VFFLMQ1ALLOCERR(_i) (0x0050B480 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
6262 #define GLPE_VFFLMQ1ALLOCERR_MAX_INDEX 31
6263 #define GLPE_VFFLMQ1ALLOCERR_ERROR_COUNT_S 0
6264 #define GLPE_VFFLMQ1ALLOCERR_ERROR_COUNT_M MAKEMASK(0xFFFF, 0)
6265 #define GLPE_VFFLMRRFALLOCERR(_i) (0x0050B500 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
6266 #define GLPE_VFFLMRRFALLOCERR_MAX_INDEX 31
6267 #define GLPE_VFFLMRRFALLOCERR_ERROR_COUNT_S 0
6268 #define GLPE_VFFLMRRFALLOCERR_ERROR_COUNT_M MAKEMASK(0xFFFF, 0)
6269 #define GLPE_VFFLMXMITALLOCERR(_i) (0x0050B400 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
6270 #define GLPE_VFFLMXMITALLOCERR_MAX_INDEX 31
6271 #define GLPE_VFFLMXMITALLOCERR_ERROR_COUNT_S 0
6272 #define GLPE_VFFLMXMITALLOCERR_ERROR_COUNT_M MAKEMASK(0xFFFF, 0)
6273 #define GLPE_VFTCPNOW50USCNT(_i) (0x0050B300 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: PE_CORER */
6274 #define GLPE_VFTCPNOW50USCNT_MAX_INDEX 31
6275 #define GLPE_VFTCPNOW50USCNT_CNT_S 0
6276 #define GLPE_VFTCPNOW50USCNT_CNT_M MAKEMASK(0xFFFFFFFF, 0)
6277 #define PFPE_AEQALLOC 0x00502D00 /* Reset Source: PFR */
6278 #define PFPE_AEQALLOC_AECOUNT_S 0
6279 #define PFPE_AEQALLOC_AECOUNT_M MAKEMASK(0xFFFFFFFF, 0)
6280 #define PFPE_CCQPHIGH 0x0050A100 /* Reset Source: PFR */
6281 #define PFPE_CCQPHIGH_PECCQPHIGH_S 0
6282 #define PFPE_CCQPHIGH_PECCQPHIGH_M MAKEMASK(0xFFFFFFFF, 0)
6283 #define PFPE_CCQPLOW 0x0050A080 /* Reset Source: PFR */
6284 #define PFPE_CCQPLOW_PECCQPLOW_S 0
6285 #define PFPE_CCQPLOW_PECCQPLOW_M MAKEMASK(0xFFFFFFFF, 0)
6286 #define PFPE_CCQPSTATUS 0x0050A000 /* Reset Source: PFR */
6287 #define PFPE_CCQPSTATUS_CCQP_DONE_S 0
6288 #define PFPE_CCQPSTATUS_CCQP_DONE_M BIT(0)
6289 #define PFPE_CCQPSTATUS_HMC_PROFILE_S 4
6290 #define PFPE_CCQPSTATUS_HMC_PROFILE_M MAKEMASK(0x7, 4)
6291 #define PFPE_CCQPSTATUS_RDMA_EN_VFS_S 16
6292 #define PFPE_CCQPSTATUS_RDMA_EN_VFS_M MAKEMASK(0x3F, 16)
6293 #define PFPE_CCQPSTATUS_CCQP_ERR_S 31
6294 #define PFPE_CCQPSTATUS_CCQP_ERR_M BIT(31)
6295 #define PFPE_CQACK 0x00502C80 /* Reset Source: PFR */
6296 #define PFPE_CQACK_PECQID_S 0
6297 #define PFPE_CQACK_PECQID_M MAKEMASK(0x7FFFF, 0)
6298 #define PFPE_CQARM 0x00502C00 /* Reset Source: PFR */
6299 #define PFPE_CQARM_PECQID_S 0
6300 #define PFPE_CQARM_PECQID_M MAKEMASK(0x7FFFF, 0)
6301 #define PFPE_CQPDB 0x00500800 /* Reset Source: PFR */
6302 #define PFPE_CQPDB_WQHEAD_S 0
6303 #define PFPE_CQPDB_WQHEAD_M MAKEMASK(0x7FF, 0)
6304 #define PFPE_CQPERRCODES 0x0050A200 /* Reset Source: PFR */
6305 #define PFPE_CQPERRCODES_CQP_MINOR_CODE_S 0
6306 #define PFPE_CQPERRCODES_CQP_MINOR_CODE_M MAKEMASK(0xFFFF, 0)
6307 #define PFPE_CQPERRCODES_CQP_MAJOR_CODE_S 16
6308 #define PFPE_CQPERRCODES_CQP_MAJOR_CODE_M MAKEMASK(0xFFFF, 16)
6309 #define PFPE_CQPTAIL 0x00500880 /* Reset Source: PFR */
6310 #define PFPE_CQPTAIL_WQTAIL_S 0
6311 #define PFPE_CQPTAIL_WQTAIL_M MAKEMASK(0x7FF, 0)
6312 #define PFPE_CQPTAIL_CQP_OP_ERR_S 31
6313 #define PFPE_CQPTAIL_CQP_OP_ERR_M BIT(31)
6314 #define PFPE_IPCONFIG0 0x0050A180 /* Reset Source: PFR */
6315 #define PFPE_IPCONFIG0_PEIPID_S 0
6316 #define PFPE_IPCONFIG0_PEIPID_M MAKEMASK(0xFFFF, 0)
6317 #define PFPE_IPCONFIG0_USEENTIREIDRANGE_S 16
6318 #define PFPE_IPCONFIG0_USEENTIREIDRANGE_M BIT(16)
6319 #define PFPE_IPCONFIG0_UDP_SRC_PORT_MASK_EN_S 17
6320 #define PFPE_IPCONFIG0_UDP_SRC_PORT_MASK_EN_M BIT(17)
6321 #define PFPE_MRTEIDXMASK 0x0050A300 /* Reset Source: PFR */
6322 #define PFPE_MRTEIDXMASK_MRTEIDXMASKBITS_S 0
6323 #define PFPE_MRTEIDXMASK_MRTEIDXMASKBITS_M MAKEMASK(0x1F, 0)
6324 #define PFPE_RCVUNEXPECTEDERROR 0x0050A380 /* Reset Source: PFR */
6325 #define PFPE_RCVUNEXPECTEDERROR_TCP_RX_UNEXP_ERR_S 0
6326 #define PFPE_RCVUNEXPECTEDERROR_TCP_RX_UNEXP_ERR_M MAKEMASK(0xFFFFFF, 0)
6327 #define PFPE_TCPNOWTIMER 0x0050A280 /* Reset Source: PFR */
6328 #define PFPE_TCPNOWTIMER_TCP_NOW_S 0
6329 #define PFPE_TCPNOWTIMER_TCP_NOW_M MAKEMASK(0xFFFFFFFF, 0)
6330 #define PFPE_WQEALLOC 0x00504400 /* Reset Source: PFR */
6331 #define PFPE_WQEALLOC_PEQPID_S 0
6332 #define PFPE_WQEALLOC_PEQPID_M MAKEMASK(0x3FFFF, 0)
6333 #define PFPE_WQEALLOC_WQE_DESC_INDEX_S 20
6334 #define PFPE_WQEALLOC_WQE_DESC_INDEX_M MAKEMASK(0xFFF, 20)
6335 #define PRT_PEPM_COUNT(_i) (0x0050C040 + ((_i) * 4)) /* _i=0...511 */ /* Reset Source: PERST */
6336 #define PRT_PEPM_COUNT_MAX_INDEX 511
6337 #define PRT_PEPM_COUNT_PEPM_PSQ_COUNT_S 0
6338 #define PRT_PEPM_COUNT_PEPM_PSQ_COUNT_M MAKEMASK(0x1F, 0)
6339 #define PRT_PEPM_COUNT_PEPM_MDQ_COUNT_S 16
6340 #define PRT_PEPM_COUNT_PEPM_MDQ_COUNT_M MAKEMASK(0x3FFF, 16)
6341 #define VFPE_AEQALLOC(_VF) (0x00502800 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: PFR */
6342 #define VFPE_AEQALLOC_MAX_INDEX 255
6343 #define VFPE_AEQALLOC_AECOUNT_S 0
6344 #define VFPE_AEQALLOC_AECOUNT_M MAKEMASK(0xFFFFFFFF, 0)
6345 #define VFPE_CCQPHIGH(_VF) (0x00508800 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: PFR */
6346 #define VFPE_CCQPHIGH_MAX_INDEX 255
6347 #define VFPE_CCQPHIGH_PECCQPHIGH_S 0
6348 #define VFPE_CCQPHIGH_PECCQPHIGH_M MAKEMASK(0xFFFFFFFF, 0)
6349 #define VFPE_CCQPLOW(_VF) (0x00508400 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: PFR */
6350 #define VFPE_CCQPLOW_MAX_INDEX 255
6351 #define VFPE_CCQPLOW_PECCQPLOW_S 0
6352 #define VFPE_CCQPLOW_PECCQPLOW_M MAKEMASK(0xFFFFFFFF, 0)
6353 #define VFPE_CCQPSTATUS(_VF) (0x00508000 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: PFR */
6354 #define VFPE_CCQPSTATUS_MAX_INDEX 255
6355 #define VFPE_CCQPSTATUS_CCQP_DONE_S 0
6356 #define VFPE_CCQPSTATUS_CCQP_DONE_M BIT(0)
6357 #define VFPE_CCQPSTATUS_HMC_PROFILE_S 4
6358 #define VFPE_CCQPSTATUS_HMC_PROFILE_M MAKEMASK(0x7, 4)
6359 #define VFPE_CCQPSTATUS_RDMA_EN_VFS_S 16
6360 #define VFPE_CCQPSTATUS_RDMA_EN_VFS_M MAKEMASK(0x3F, 16)
6361 #define VFPE_CCQPSTATUS_CCQP_ERR_S 31
6362 #define VFPE_CCQPSTATUS_CCQP_ERR_M BIT(31)
6363 #define VFPE_CQACK(_VF) (0x00502400 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: PFR */
6364 #define VFPE_CQACK_MAX_INDEX 255
6365 #define VFPE_CQACK_PECQID_S 0
6366 #define VFPE_CQACK_PECQID_M MAKEMASK(0x7FFFF, 0)
6367 #define VFPE_CQARM(_VF) (0x00502000 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: PFR */
6368 #define VFPE_CQARM_MAX_INDEX 255
6369 #define VFPE_CQARM_PECQID_S 0
6370 #define VFPE_CQARM_PECQID_M MAKEMASK(0x7FFFF, 0)
6371 #define VFPE_CQPDB(_VF) (0x00500000 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: PFR */
6372 #define VFPE_CQPDB_MAX_INDEX 255
6373 #define VFPE_CQPDB_WQHEAD_S 0
6374 #define VFPE_CQPDB_WQHEAD_M MAKEMASK(0x7FF, 0)
6375 #define VFPE_CQPERRCODES(_VF) (0x00509000 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: PFR */
6376 #define VFPE_CQPERRCODES_MAX_INDEX 255
6377 #define VFPE_CQPERRCODES_CQP_MINOR_CODE_S 0
6378 #define VFPE_CQPERRCODES_CQP_MINOR_CODE_M MAKEMASK(0xFFFF, 0)
6379 #define VFPE_CQPERRCODES_CQP_MAJOR_CODE_S 16
6380 #define VFPE_CQPERRCODES_CQP_MAJOR_CODE_M MAKEMASK(0xFFFF, 16)
6381 #define VFPE_CQPTAIL(_VF) (0x00500400 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: PFR */
6382 #define VFPE_CQPTAIL_MAX_INDEX 255
6383 #define VFPE_CQPTAIL_WQTAIL_S 0
6384 #define VFPE_CQPTAIL_WQTAIL_M MAKEMASK(0x7FF, 0)
6385 #define VFPE_CQPTAIL_CQP_OP_ERR_S 31
6386 #define VFPE_CQPTAIL_CQP_OP_ERR_M BIT(31)
6387 #define VFPE_IPCONFIG0(_VF) (0x00508C00 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: PFR */
6388 #define VFPE_IPCONFIG0_MAX_INDEX 255
6389 #define VFPE_IPCONFIG0_PEIPID_S 0
6390 #define VFPE_IPCONFIG0_PEIPID_M MAKEMASK(0xFFFF, 0)
6391 #define VFPE_IPCONFIG0_USEENTIREIDRANGE_S 16
6392 #define VFPE_IPCONFIG0_USEENTIREIDRANGE_M BIT(16)
6393 #define VFPE_IPCONFIG0_UDP_SRC_PORT_MASK_EN_S 17
6394 #define VFPE_IPCONFIG0_UDP_SRC_PORT_MASK_EN_M BIT(17)
6395 #define VFPE_RCVUNEXPECTEDERROR(_VF) (0x00509C00 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: PFR */
6396 #define VFPE_RCVUNEXPECTEDERROR_MAX_INDEX 255
6397 #define VFPE_RCVUNEXPECTEDERROR_TCP_RX_UNEXP_ERR_S 0
6398 #define VFPE_RCVUNEXPECTEDERROR_TCP_RX_UNEXP_ERR_M MAKEMASK(0xFFFFFF, 0)
6399 #define VFPE_TCPNOWTIMER(_VF) (0x00509400 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: PFR */
6400 #define VFPE_TCPNOWTIMER_MAX_INDEX 255
6401 #define VFPE_TCPNOWTIMER_TCP_NOW_S 0
6402 #define VFPE_TCPNOWTIMER_TCP_NOW_M MAKEMASK(0xFFFFFFFF, 0)
6403 #define VFPE_WQEALLOC(_VF) (0x00504000 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: PFR */
6404 #define VFPE_WQEALLOC_MAX_INDEX 255
6405 #define VFPE_WQEALLOC_PEQPID_S 0
6406 #define VFPE_WQEALLOC_PEQPID_M MAKEMASK(0x3FFFF, 0)
6407 #define VFPE_WQEALLOC_WQE_DESC_INDEX_S 20
6408 #define VFPE_WQEALLOC_WQE_DESC_INDEX_M MAKEMASK(0xFFF, 20)
6409 #define GLPES_PFIP4RXDISCARD(_i) (0x00541400 + ((_i) * 4)) /* _i=0...127 */ /* Reset Source: CORER */
6410 #define GLPES_PFIP4RXDISCARD_MAX_INDEX 127
6411 #define GLPES_PFIP4RXDISCARD_IP4RXDISCARD_S 0
6412 #define GLPES_PFIP4RXDISCARD_IP4RXDISCARD_M MAKEMASK(0xFFFFFFFF, 0)
6413 #define GLPES_PFIP4RXFRAGSHI(_i) (0x00541C04 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6414 #define GLPES_PFIP4RXFRAGSHI_MAX_INDEX 127
6415 #define GLPES_PFIP4RXFRAGSHI_IP4RXFRAGSHI_S 0
6416 #define GLPES_PFIP4RXFRAGSHI_IP4RXFRAGSHI_M MAKEMASK(0xFFFF, 0)
6417 #define GLPES_PFIP4RXFRAGSLO(_i) (0x00541C00 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6418 #define GLPES_PFIP4RXFRAGSLO_MAX_INDEX 127
6419 #define GLPES_PFIP4RXFRAGSLO_IP4RXFRAGSLO_S 0
6420 #define GLPES_PFIP4RXFRAGSLO_IP4RXFRAGSLO_M MAKEMASK(0xFFFFFFFF, 0)
6421 #define GLPES_PFIP4RXMCOCTSHI(_i) (0x00542404 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6422 #define GLPES_PFIP4RXMCOCTSHI_MAX_INDEX 127
6423 #define GLPES_PFIP4RXMCOCTSHI_IP4RXMCOCTSHI_S 0
6424 #define GLPES_PFIP4RXMCOCTSHI_IP4RXMCOCTSHI_M MAKEMASK(0xFFFF, 0)
6425 #define GLPES_PFIP4RXMCOCTSLO(_i) (0x00542400 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6426 #define GLPES_PFIP4RXMCOCTSLO_MAX_INDEX 127
6427 #define GLPES_PFIP4RXMCOCTSLO_IP4RXMCOCTSLO_S 0
6428 #define GLPES_PFIP4RXMCOCTSLO_IP4RXMCOCTSLO_M MAKEMASK(0xFFFFFFFF, 0)
6429 #define GLPES_PFIP4RXMCPKTSHI(_i) (0x00542C04 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6430 #define GLPES_PFIP4RXMCPKTSHI_MAX_INDEX 127
6431 #define GLPES_PFIP4RXMCPKTSHI_IP4RXMCPKTSHI_S 0
6432 #define GLPES_PFIP4RXMCPKTSHI_IP4RXMCPKTSHI_M MAKEMASK(0xFFFF, 0)
6433 #define GLPES_PFIP4RXMCPKTSLO(_i) (0x00542C00 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6434 #define GLPES_PFIP4RXMCPKTSLO_MAX_INDEX 127
6435 #define GLPES_PFIP4RXMCPKTSLO_IP4RXMCPKTSLO_S 0
6436 #define GLPES_PFIP4RXMCPKTSLO_IP4RXMCPKTSLO_M MAKEMASK(0xFFFFFFFF, 0)
6437 #define GLPES_PFIP4RXOCTSHI(_i) (0x00540404 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6438 #define GLPES_PFIP4RXOCTSHI_MAX_INDEX 127
6439 #define GLPES_PFIP4RXOCTSHI_IP4RXOCTSHI_S 0
6440 #define GLPES_PFIP4RXOCTSHI_IP4RXOCTSHI_M MAKEMASK(0xFFFF, 0)
6441 #define GLPES_PFIP4RXOCTSLO(_i) (0x00540400 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6442 #define GLPES_PFIP4RXOCTSLO_MAX_INDEX 127
6443 #define GLPES_PFIP4RXOCTSLO_IP4RXOCTSLO_S 0
6444 #define GLPES_PFIP4RXOCTSLO_IP4RXOCTSLO_M MAKEMASK(0xFFFFFFFF, 0)
6445 #define GLPES_PFIP4RXPKTSHI(_i) (0x00540C04 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6446 #define GLPES_PFIP4RXPKTSHI_MAX_INDEX 127
6447 #define GLPES_PFIP4RXPKTSHI_IP4RXPKTSHI_S 0
6448 #define GLPES_PFIP4RXPKTSHI_IP4RXPKTSHI_M MAKEMASK(0xFFFF, 0)
6449 #define GLPES_PFIP4RXPKTSLO(_i) (0x00540C00 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6450 #define GLPES_PFIP4RXPKTSLO_MAX_INDEX 127
6451 #define GLPES_PFIP4RXPKTSLO_IP4RXPKTSLO_S 0
6452 #define GLPES_PFIP4RXPKTSLO_IP4RXPKTSLO_M MAKEMASK(0xFFFFFFFF, 0)
6453 #define GLPES_PFIP4RXTRUNC(_i) (0x00541800 + ((_i) * 4)) /* _i=0...127 */ /* Reset Source: CORER */
6454 #define GLPES_PFIP4RXTRUNC_MAX_INDEX 127
6455 #define GLPES_PFIP4RXTRUNC_IP4RXTRUNC_S 0
6456 #define GLPES_PFIP4RXTRUNC_IP4RXTRUNC_M MAKEMASK(0xFFFFFFFF, 0)
6457 #define GLPES_PFIP4TXFRAGSHI(_i) (0x00547404 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6458 #define GLPES_PFIP4TXFRAGSHI_MAX_INDEX 127
6459 #define GLPES_PFIP4TXFRAGSHI_IP4TXFRAGSHI_S 0
6460 #define GLPES_PFIP4TXFRAGSHI_IP4TXFRAGSHI_M MAKEMASK(0xFFFF, 0)
6461 #define GLPES_PFIP4TXFRAGSLO(_i) (0x00547400 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6462 #define GLPES_PFIP4TXFRAGSLO_MAX_INDEX 127
6463 #define GLPES_PFIP4TXFRAGSLO_IP4TXFRAGSLO_S 0
6464 #define GLPES_PFIP4TXFRAGSLO_IP4TXFRAGSLO_M MAKEMASK(0xFFFFFFFF, 0)
6465 #define GLPES_PFIP4TXMCOCTSHI(_i) (0x00547C04 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6466 #define GLPES_PFIP4TXMCOCTSHI_MAX_INDEX 127
6467 #define GLPES_PFIP4TXMCOCTSHI_IP4TXMCOCTSHI_S 0
6468 #define GLPES_PFIP4TXMCOCTSHI_IP4TXMCOCTSHI_M MAKEMASK(0xFFFF, 0)
6469 #define GLPES_PFIP4TXMCOCTSLO(_i) (0x00547C00 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6470 #define GLPES_PFIP4TXMCOCTSLO_MAX_INDEX 127
6471 #define GLPES_PFIP4TXMCOCTSLO_IP4TXMCOCTSLO_S 0
6472 #define GLPES_PFIP4TXMCOCTSLO_IP4TXMCOCTSLO_M MAKEMASK(0xFFFFFFFF, 0)
6473 #define GLPES_PFIP4TXMCPKTSHI(_i) (0x00548404 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6474 #define GLPES_PFIP4TXMCPKTSHI_MAX_INDEX 127
6475 #define GLPES_PFIP4TXMCPKTSHI_IP4TXMCPKTSHI_S 0
6476 #define GLPES_PFIP4TXMCPKTSHI_IP4TXMCPKTSHI_M MAKEMASK(0xFFFF, 0)
6477 #define GLPES_PFIP4TXMCPKTSLO(_i) (0x00548400 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6478 #define GLPES_PFIP4TXMCPKTSLO_MAX_INDEX 127
6479 #define GLPES_PFIP4TXMCPKTSLO_IP4TXMCPKTSLO_S 0
6480 #define GLPES_PFIP4TXMCPKTSLO_IP4TXMCPKTSLO_M MAKEMASK(0xFFFFFFFF, 0)
6481 #define GLPES_PFIP4TXNOROUTE(_i) (0x0054B400 + ((_i) * 4)) /* _i=0...127 */ /* Reset Source: CORER */
6482 #define GLPES_PFIP4TXNOROUTE_MAX_INDEX 127
6483 #define GLPES_PFIP4TXNOROUTE_IP4TXNOROUTE_S 0
6484 #define GLPES_PFIP4TXNOROUTE_IP4TXNOROUTE_M MAKEMASK(0xFFFFFF, 0)
6485 #define GLPES_PFIP4TXOCTSHI(_i) (0x00546404 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6486 #define GLPES_PFIP4TXOCTSHI_MAX_INDEX 127
6487 #define GLPES_PFIP4TXOCTSHI_IP4TXOCTSHI_S 0
6488 #define GLPES_PFIP4TXOCTSHI_IP4TXOCTSHI_M MAKEMASK(0xFFFF, 0)
6489 #define GLPES_PFIP4TXOCTSLO(_i) (0x00546400 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6490 #define GLPES_PFIP4TXOCTSLO_MAX_INDEX 127
6491 #define GLPES_PFIP4TXOCTSLO_IP4TXOCTSLO_S 0
6492 #define GLPES_PFIP4TXOCTSLO_IP4TXOCTSLO_M MAKEMASK(0xFFFFFFFF, 0)
6493 #define GLPES_PFIP4TXPKTSHI(_i) (0x00546C04 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6494 #define GLPES_PFIP4TXPKTSHI_MAX_INDEX 127
6495 #define GLPES_PFIP4TXPKTSHI_IP4TXPKTSHI_S 0
6496 #define GLPES_PFIP4TXPKTSHI_IP4TXPKTSHI_M MAKEMASK(0xFFFF, 0)
6497 #define GLPES_PFIP4TXPKTSLO(_i) (0x00546C00 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6498 #define GLPES_PFIP4TXPKTSLO_MAX_INDEX 127
6499 #define GLPES_PFIP4TXPKTSLO_IP4TXPKTSLO_S 0
6500 #define GLPES_PFIP4TXPKTSLO_IP4TXPKTSLO_M MAKEMASK(0xFFFFFFFF, 0)
6501 #define GLPES_PFIP6RXDISCARD(_i) (0x00544400 + ((_i) * 4)) /* _i=0...127 */ /* Reset Source: CORER */
6502 #define GLPES_PFIP6RXDISCARD_MAX_INDEX 127
6503 #define GLPES_PFIP6RXDISCARD_IP6RXDISCARD_S 0
6504 #define GLPES_PFIP6RXDISCARD_IP6RXDISCARD_M MAKEMASK(0xFFFFFFFF, 0)
6505 #define GLPES_PFIP6RXFRAGSHI(_i) (0x00544C04 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6506 #define GLPES_PFIP6RXFRAGSHI_MAX_INDEX 127
6507 #define GLPES_PFIP6RXFRAGSHI_IP6RXFRAGSHI_S 0
6508 #define GLPES_PFIP6RXFRAGSHI_IP6RXFRAGSHI_M MAKEMASK(0xFFFF, 0)
6509 #define GLPES_PFIP6RXFRAGSLO(_i) (0x00544C00 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6510 #define GLPES_PFIP6RXFRAGSLO_MAX_INDEX 127
6511 #define GLPES_PFIP6RXFRAGSLO_IP6RXFRAGSLO_S 0
6512 #define GLPES_PFIP6RXFRAGSLO_IP6RXFRAGSLO_M MAKEMASK(0xFFFFFFFF, 0)
6513 #define GLPES_PFIP6RXMCOCTSHI(_i) (0x00545404 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6514 #define GLPES_PFIP6RXMCOCTSHI_MAX_INDEX 127
6515 #define GLPES_PFIP6RXMCOCTSHI_IP6RXMCOCTSHI_S 0
6516 #define GLPES_PFIP6RXMCOCTSHI_IP6RXMCOCTSHI_M MAKEMASK(0xFFFF, 0)
6517 #define GLPES_PFIP6RXMCOCTSLO(_i) (0x00545400 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6518 #define GLPES_PFIP6RXMCOCTSLO_MAX_INDEX 127
6519 #define GLPES_PFIP6RXMCOCTSLO_IP6RXMCOCTSLO_S 0
6520 #define GLPES_PFIP6RXMCOCTSLO_IP6RXMCOCTSLO_M MAKEMASK(0xFFFFFFFF, 0)
6521 #define GLPES_PFIP6RXMCPKTSHI(_i) (0x00545C04 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6522 #define GLPES_PFIP6RXMCPKTSHI_MAX_INDEX 127
6523 #define GLPES_PFIP6RXMCPKTSHI_IP6RXMCPKTSHI_S 0
6524 #define GLPES_PFIP6RXMCPKTSHI_IP6RXMCPKTSHI_M MAKEMASK(0xFFFF, 0)
6525 #define GLPES_PFIP6RXMCPKTSLO(_i) (0x00545C00 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6526 #define GLPES_PFIP6RXMCPKTSLO_MAX_INDEX 127
6527 #define GLPES_PFIP6RXMCPKTSLO_IP6RXMCPKTSLO_S 0
6528 #define GLPES_PFIP6RXMCPKTSLO_IP6RXMCPKTSLO_M MAKEMASK(0xFFFFFFFF, 0)
6529 #define GLPES_PFIP6RXOCTSHI(_i) (0x00543404 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6530 #define GLPES_PFIP6RXOCTSHI_MAX_INDEX 127
6531 #define GLPES_PFIP6RXOCTSHI_IP6RXOCTSHI_S 0
6532 #define GLPES_PFIP6RXOCTSHI_IP6RXOCTSHI_M MAKEMASK(0xFFFF, 0)
6533 #define GLPES_PFIP6RXOCTSLO(_i) (0x00543400 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6534 #define GLPES_PFIP6RXOCTSLO_MAX_INDEX 127
6535 #define GLPES_PFIP6RXOCTSLO_IP6RXOCTSLO_S 0
6536 #define GLPES_PFIP6RXOCTSLO_IP6RXOCTSLO_M MAKEMASK(0xFFFFFFFF, 0)
6537 #define GLPES_PFIP6RXPKTSHI(_i) (0x00543C04 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6538 #define GLPES_PFIP6RXPKTSHI_MAX_INDEX 127
6539 #define GLPES_PFIP6RXPKTSHI_IP6RXPKTSHI_S 0
6540 #define GLPES_PFIP6RXPKTSHI_IP6RXPKTSHI_M MAKEMASK(0xFFFF, 0)
6541 #define GLPES_PFIP6RXPKTSLO(_i) (0x00543C00 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6542 #define GLPES_PFIP6RXPKTSLO_MAX_INDEX 127
6543 #define GLPES_PFIP6RXPKTSLO_IP6RXPKTSLO_S 0
6544 #define GLPES_PFIP6RXPKTSLO_IP6RXPKTSLO_M MAKEMASK(0xFFFFFFFF, 0)
6545 #define GLPES_PFIP6RXTRUNC(_i) (0x00544800 + ((_i) * 4)) /* _i=0...127 */ /* Reset Source: CORER */
6546 #define GLPES_PFIP6RXTRUNC_MAX_INDEX 127
6547 #define GLPES_PFIP6RXTRUNC_IP6RXTRUNC_S 0
6548 #define GLPES_PFIP6RXTRUNC_IP6RXTRUNC_M MAKEMASK(0xFFFFFFFF, 0)
6549 #define GLPES_PFIP6TXFRAGSHI(_i) (0x00549C04 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6550 #define GLPES_PFIP6TXFRAGSHI_MAX_INDEX 127
6551 #define GLPES_PFIP6TXFRAGSHI_IP6TXFRAGSHI_S 0
6552 #define GLPES_PFIP6TXFRAGSHI_IP6TXFRAGSHI_M MAKEMASK(0xFFFF, 0)
6553 #define GLPES_PFIP6TXFRAGSLO(_i) (0x00549C00 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6554 #define GLPES_PFIP6TXFRAGSLO_MAX_INDEX 127
6555 #define GLPES_PFIP6TXFRAGSLO_IP6TXFRAGSLO_S 0
6556 #define GLPES_PFIP6TXFRAGSLO_IP6TXFRAGSLO_M MAKEMASK(0xFFFFFFFF, 0)
6557 #define GLPES_PFIP6TXMCOCTSHI(_i) (0x0054A404 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6558 #define GLPES_PFIP6TXMCOCTSHI_MAX_INDEX 127
6559 #define GLPES_PFIP6TXMCOCTSHI_IP6TXMCOCTSHI_S 0
6560 #define GLPES_PFIP6TXMCOCTSHI_IP6TXMCOCTSHI_M MAKEMASK(0xFFFF, 0)
6561 #define GLPES_PFIP6TXMCOCTSLO(_i) (0x0054A400 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6562 #define GLPES_PFIP6TXMCOCTSLO_MAX_INDEX 127
6563 #define GLPES_PFIP6TXMCOCTSLO_IP6TXMCOCTSLO_S 0
6564 #define GLPES_PFIP6TXMCOCTSLO_IP6TXMCOCTSLO_M MAKEMASK(0xFFFFFFFF, 0)
6565 #define GLPES_PFIP6TXMCPKTSHI(_i) (0x0054AC04 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6566 #define GLPES_PFIP6TXMCPKTSHI_MAX_INDEX 127
6567 #define GLPES_PFIP6TXMCPKTSHI_IP6TXMCPKTSHI_S 0
6568 #define GLPES_PFIP6TXMCPKTSHI_IP6TXMCPKTSHI_M MAKEMASK(0xFFFF, 0)
6569 #define GLPES_PFIP6TXMCPKTSLO(_i) (0x0054AC00 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6570 #define GLPES_PFIP6TXMCPKTSLO_MAX_INDEX 127
6571 #define GLPES_PFIP6TXMCPKTSLO_IP6TXMCPKTSLO_S 0
6572 #define GLPES_PFIP6TXMCPKTSLO_IP6TXMCPKTSLO_M MAKEMASK(0xFFFFFFFF, 0)
6573 #define GLPES_PFIP6TXNOROUTE(_i) (0x0054B800 + ((_i) * 4)) /* _i=0...127 */ /* Reset Source: CORER */
6574 #define GLPES_PFIP6TXNOROUTE_MAX_INDEX 127
6575 #define GLPES_PFIP6TXNOROUTE_IP6TXNOROUTE_S 0
6576 #define GLPES_PFIP6TXNOROUTE_IP6TXNOROUTE_M MAKEMASK(0xFFFFFF, 0)
6577 #define GLPES_PFIP6TXOCTSHI(_i) (0x00548C04 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6578 #define GLPES_PFIP6TXOCTSHI_MAX_INDEX 127
6579 #define GLPES_PFIP6TXOCTSHI_IP6TXOCTSHI_S 0
6580 #define GLPES_PFIP6TXOCTSHI_IP6TXOCTSHI_M MAKEMASK(0xFFFF, 0)
6581 #define GLPES_PFIP6TXOCTSLO(_i) (0x00548C00 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6582 #define GLPES_PFIP6TXOCTSLO_MAX_INDEX 127
6583 #define GLPES_PFIP6TXOCTSLO_IP6TXOCTSLO_S 0
6584 #define GLPES_PFIP6TXOCTSLO_IP6TXOCTSLO_M MAKEMASK(0xFFFFFFFF, 0)
6585 #define GLPES_PFIP6TXPKTSHI(_i) (0x00549404 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6586 #define GLPES_PFIP6TXPKTSHI_MAX_INDEX 127
6587 #define GLPES_PFIP6TXPKTSHI_IP6TXPKTSHI_S 0
6588 #define GLPES_PFIP6TXPKTSHI_IP6TXPKTSHI_M MAKEMASK(0xFFFF, 0)
6589 #define GLPES_PFIP6TXPKTSLO(_i) (0x00549400 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6590 #define GLPES_PFIP6TXPKTSLO_MAX_INDEX 127
6591 #define GLPES_PFIP6TXPKTSLO_IP6TXPKTSLO_S 0
6592 #define GLPES_PFIP6TXPKTSLO_IP6TXPKTSLO_M MAKEMASK(0xFFFFFFFF, 0)
6593 #define GLPES_PFRDMARXRDSHI(_i) (0x0054EC04 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6594 #define GLPES_PFRDMARXRDSHI_MAX_INDEX 127
6595 #define GLPES_PFRDMARXRDSHI_RDMARXRDSHI_S 0
6596 #define GLPES_PFRDMARXRDSHI_RDMARXRDSHI_M MAKEMASK(0xFFFF, 0)
6597 #define GLPES_PFRDMARXRDSLO(_i) (0x0054EC00 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6598 #define GLPES_PFRDMARXRDSLO_MAX_INDEX 127
6599 #define GLPES_PFRDMARXRDSLO_RDMARXRDSLO_S 0
6600 #define GLPES_PFRDMARXRDSLO_RDMARXRDSLO_M MAKEMASK(0xFFFFFFFF, 0)
6601 #define GLPES_PFRDMARXSNDSHI(_i) (0x0054F404 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6602 #define GLPES_PFRDMARXSNDSHI_MAX_INDEX 127
6603 #define GLPES_PFRDMARXSNDSHI_RDMARXSNDSHI_S 0
6604 #define GLPES_PFRDMARXSNDSHI_RDMARXSNDSHI_M MAKEMASK(0xFFFF, 0)
6605 #define GLPES_PFRDMARXSNDSLO(_i) (0x0054F400 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6606 #define GLPES_PFRDMARXSNDSLO_MAX_INDEX 127
6607 #define GLPES_PFRDMARXSNDSLO_RDMARXSNDSLO_S 0
6608 #define GLPES_PFRDMARXSNDSLO_RDMARXSNDSLO_M MAKEMASK(0xFFFFFFFF, 0)
6609 #define GLPES_PFRDMARXWRSHI(_i) (0x0054E404 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6610 #define GLPES_PFRDMARXWRSHI_MAX_INDEX 127
6611 #define GLPES_PFRDMARXWRSHI_RDMARXWRSHI_S 0
6612 #define GLPES_PFRDMARXWRSHI_RDMARXWRSHI_M MAKEMASK(0xFFFF, 0)
6613 #define GLPES_PFRDMARXWRSLO(_i) (0x0054E400 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6614 #define GLPES_PFRDMARXWRSLO_MAX_INDEX 127
6615 #define GLPES_PFRDMARXWRSLO_RDMARXWRSLO_S 0
6616 #define GLPES_PFRDMARXWRSLO_RDMARXWRSLO_M MAKEMASK(0xFFFFFFFF, 0)
6617 #define GLPES_PFRDMATXRDSHI(_i) (0x00550404 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6618 #define GLPES_PFRDMATXRDSHI_MAX_INDEX 127
6619 #define GLPES_PFRDMATXRDSHI_RDMARXRDSHI_S 0
6620 #define GLPES_PFRDMATXRDSHI_RDMARXRDSHI_M MAKEMASK(0xFFFF, 0)
6621 #define GLPES_PFRDMATXRDSLO(_i) (0x00550400 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6622 #define GLPES_PFRDMATXRDSLO_MAX_INDEX 127
6623 #define GLPES_PFRDMATXRDSLO_RDMARXRDSLO_S 0
6624 #define GLPES_PFRDMATXRDSLO_RDMARXRDSLO_M MAKEMASK(0xFFFFFFFF, 0)
6625 #define GLPES_PFRDMATXSNDSHI(_i) (0x00550C04 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6626 #define GLPES_PFRDMATXSNDSHI_MAX_INDEX 127
6627 #define GLPES_PFRDMATXSNDSHI_RDMARXSNDSHI_S 0
6628 #define GLPES_PFRDMATXSNDSHI_RDMARXSNDSHI_M MAKEMASK(0xFFFF, 0)
6629 #define GLPES_PFRDMATXSNDSLO(_i) (0x00550C00 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6630 #define GLPES_PFRDMATXSNDSLO_MAX_INDEX 127
6631 #define GLPES_PFRDMATXSNDSLO_RDMARXSNDSLO_S 0
6632 #define GLPES_PFRDMATXSNDSLO_RDMARXSNDSLO_M MAKEMASK(0xFFFFFFFF, 0)
6633 #define GLPES_PFRDMATXWRSHI(_i) (0x0054FC04 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6634 #define GLPES_PFRDMATXWRSHI_MAX_INDEX 127
6635 #define GLPES_PFRDMATXWRSHI_RDMARXWRSHI_S 0
6636 #define GLPES_PFRDMATXWRSHI_RDMARXWRSHI_M MAKEMASK(0xFFFF, 0)
6637 #define GLPES_PFRDMATXWRSLO(_i) (0x0054FC00 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6638 #define GLPES_PFRDMATXWRSLO_MAX_INDEX 127
6639 #define GLPES_PFRDMATXWRSLO_RDMARXWRSLO_S 0
6640 #define GLPES_PFRDMATXWRSLO_RDMARXWRSLO_M MAKEMASK(0xFFFFFFFF, 0)
6641 #define GLPES_PFRDMAVBNDHI(_i) (0x00551404 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6642 #define GLPES_PFRDMAVBNDHI_MAX_INDEX 127
6643 #define GLPES_PFRDMAVBNDHI_RDMAVBNDHI_S 0
6644 #define GLPES_PFRDMAVBNDHI_RDMAVBNDHI_M MAKEMASK(0xFFFF, 0)
6645 #define GLPES_PFRDMAVBNDLO(_i) (0x00551400 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6646 #define GLPES_PFRDMAVBNDLO_MAX_INDEX 127
6647 #define GLPES_PFRDMAVBNDLO_RDMAVBNDLO_S 0
6648 #define GLPES_PFRDMAVBNDLO_RDMAVBNDLO_M MAKEMASK(0xFFFFFFFF, 0)
6649 #define GLPES_PFRDMAVINVHI(_i) (0x00551C04 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6650 #define GLPES_PFRDMAVINVHI_MAX_INDEX 127
6651 #define GLPES_PFRDMAVINVHI_RDMAVINVHI_S 0
6652 #define GLPES_PFRDMAVINVHI_RDMAVINVHI_M MAKEMASK(0xFFFF, 0)
6653 #define GLPES_PFRDMAVINVLO(_i) (0x00551C00 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6654 #define GLPES_PFRDMAVINVLO_MAX_INDEX 127
6655 #define GLPES_PFRDMAVINVLO_RDMAVINVLO_S 0
6656 #define GLPES_PFRDMAVINVLO_RDMAVINVLO_M MAKEMASK(0xFFFFFFFF, 0)
6657 #define GLPES_PFRXVLANERR(_i) (0x00540000 + ((_i) * 4)) /* _i=0...127 */ /* Reset Source: CORER */
6658 #define GLPES_PFRXVLANERR_MAX_INDEX 127
6659 #define GLPES_PFRXVLANERR_RXVLANERR_S 0
6660 #define GLPES_PFRXVLANERR_RXVLANERR_M MAKEMASK(0xFFFFFF, 0)
6661 #define GLPES_PFTCPRTXSEG(_i) (0x00552400 + ((_i) * 4)) /* _i=0...127 */ /* Reset Source: CORER */
6662 #define GLPES_PFTCPRTXSEG_MAX_INDEX 127
6663 #define GLPES_PFTCPRTXSEG_TCPRTXSEG_S 0
6664 #define GLPES_PFTCPRTXSEG_TCPRTXSEG_M MAKEMASK(0xFFFFFFFF, 0)
6665 #define GLPES_PFTCPRXOPTERR(_i) (0x0054C400 + ((_i) * 4)) /* _i=0...127 */ /* Reset Source: CORER */
6666 #define GLPES_PFTCPRXOPTERR_MAX_INDEX 127
6667 #define GLPES_PFTCPRXOPTERR_TCPRXOPTERR_S 0
6668 #define GLPES_PFTCPRXOPTERR_TCPRXOPTERR_M MAKEMASK(0xFFFFFF, 0)
6669 #define GLPES_PFTCPRXPROTOERR(_i) (0x0054C800 + ((_i) * 4)) /* _i=0...127 */ /* Reset Source: CORER */
6670 #define GLPES_PFTCPRXPROTOERR_MAX_INDEX 127
6671 #define GLPES_PFTCPRXPROTOERR_TCPRXPROTOERR_S 0
6672 #define GLPES_PFTCPRXPROTOERR_TCPRXPROTOERR_M MAKEMASK(0xFFFFFF, 0)
6673 #define GLPES_PFTCPRXSEGSHI(_i) (0x0054BC04 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6674 #define GLPES_PFTCPRXSEGSHI_MAX_INDEX 127
6675 #define GLPES_PFTCPRXSEGSHI_TCPRXSEGSHI_S 0
6676 #define GLPES_PFTCPRXSEGSHI_TCPRXSEGSHI_M MAKEMASK(0xFFFF, 0)
6677 #define GLPES_PFTCPRXSEGSLO(_i) (0x0054BC00 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6678 #define GLPES_PFTCPRXSEGSLO_MAX_INDEX 127
6679 #define GLPES_PFTCPRXSEGSLO_TCPRXSEGSLO_S 0
6680 #define GLPES_PFTCPRXSEGSLO_TCPRXSEGSLO_M MAKEMASK(0xFFFFFFFF, 0)
6681 #define GLPES_PFTCPTXSEGHI(_i) (0x0054CC04 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6682 #define GLPES_PFTCPTXSEGHI_MAX_INDEX 127
6683 #define GLPES_PFTCPTXSEGHI_TCPTXSEGHI_S 0
6684 #define GLPES_PFTCPTXSEGHI_TCPTXSEGHI_M MAKEMASK(0xFFFF, 0)
6685 #define GLPES_PFTCPTXSEGLO(_i) (0x0054CC00 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6686 #define GLPES_PFTCPTXSEGLO_MAX_INDEX 127
6687 #define GLPES_PFTCPTXSEGLO_TCPTXSEGLO_S 0
6688 #define GLPES_PFTCPTXSEGLO_TCPTXSEGLO_M MAKEMASK(0xFFFFFFFF, 0)
6689 #define GLPES_PFUDPRXPKTSHI(_i) (0x0054D404 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6690 #define GLPES_PFUDPRXPKTSHI_MAX_INDEX 127
6691 #define GLPES_PFUDPRXPKTSHI_UDPRXPKTSHI_S 0
6692 #define GLPES_PFUDPRXPKTSHI_UDPRXPKTSHI_M MAKEMASK(0xFFFF, 0)
6693 #define GLPES_PFUDPRXPKTSLO(_i) (0x0054D400 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6694 #define GLPES_PFUDPRXPKTSLO_MAX_INDEX 127
6695 #define GLPES_PFUDPRXPKTSLO_UDPRXPKTSLO_S 0
6696 #define GLPES_PFUDPRXPKTSLO_UDPRXPKTSLO_M MAKEMASK(0xFFFFFFFF, 0)
6697 #define GLPES_PFUDPTXPKTSHI(_i) (0x0054DC04 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6698 #define GLPES_PFUDPTXPKTSHI_MAX_INDEX 127
6699 #define GLPES_PFUDPTXPKTSHI_UDPTXPKTSHI_S 0
6700 #define GLPES_PFUDPTXPKTSHI_UDPTXPKTSHI_M MAKEMASK(0xFFFF, 0)
6701 #define GLPES_PFUDPTXPKTSLO(_i) (0x0054DC00 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6702 #define GLPES_PFUDPTXPKTSLO_MAX_INDEX 127
6703 #define GLPES_PFUDPTXPKTSLO_UDPTXPKTSLO_S 0
6704 #define GLPES_PFUDPTXPKTSLO_UDPTXPKTSLO_M MAKEMASK(0xFFFFFFFF, 0)
6705 #define GLPES_RDMARXMULTFPDUSHI 0x0055E00C /* Reset Source: CORER */
6706 #define GLPES_RDMARXMULTFPDUSHI_RDMARXMULTFPDUSHI_S 0
6707 #define GLPES_RDMARXMULTFPDUSHI_RDMARXMULTFPDUSHI_M MAKEMASK(0xFFFFFF, 0)
6708 #define GLPES_RDMARXMULTFPDUSLO 0x0055E008 /* Reset Source: CORER */
6709 #define GLPES_RDMARXMULTFPDUSLO_RDMARXMULTFPDUSLO_S 0
6710 #define GLPES_RDMARXMULTFPDUSLO_RDMARXMULTFPDUSLO_M MAKEMASK(0xFFFFFFFF, 0)
6711 #define GLPES_RDMARXOOODDPHI 0x0055E014 /* Reset Source: CORER */
6712 #define GLPES_RDMARXOOODDPHI_RDMARXOOODDPHI_S 0
6713 #define GLPES_RDMARXOOODDPHI_RDMARXOOODDPHI_M MAKEMASK(0xFFFFFF, 0)
6714 #define GLPES_RDMARXOOODDPLO 0x0055E010 /* Reset Source: CORER */
6715 #define GLPES_RDMARXOOODDPLO_RDMARXOOODDPLO_S 0
6716 #define GLPES_RDMARXOOODDPLO_RDMARXOOODDPLO_M MAKEMASK(0xFFFFFFFF, 0)
6717 #define GLPES_RDMARXOOONOMARK 0x0055E004 /* Reset Source: CORER */
6718 #define GLPES_RDMARXOOONOMARK_RDMAOOONOMARK_S 0
6719 #define GLPES_RDMARXOOONOMARK_RDMAOOONOMARK_M MAKEMASK(0xFFFFFFFF, 0)
6720 #define GLPES_RDMARXUNALIGN 0x0055E000 /* Reset Source: CORER */
6721 #define GLPES_RDMARXUNALIGN_RDMRXAUNALIGN_S 0
6722 #define GLPES_RDMARXUNALIGN_RDMRXAUNALIGN_M MAKEMASK(0xFFFFFFFF, 0)
6723 #define GLPES_TCPRXFOURHOLEHI 0x0055E03C /* Reset Source: CORER */
6724 #define GLPES_TCPRXFOURHOLEHI_TCPRXFOURHOLEHI_S 0
6725 #define GLPES_TCPRXFOURHOLEHI_TCPRXFOURHOLEHI_M MAKEMASK(0xFFFFFF, 0)
6726 #define GLPES_TCPRXFOURHOLELO 0x0055E038 /* Reset Source: CORER */
6727 #define GLPES_TCPRXFOURHOLELO_TCPRXFOURHOLELO_S 0
6728 #define GLPES_TCPRXFOURHOLELO_TCPRXFOURHOLELO_M MAKEMASK(0xFFFFFFFF, 0)
6729 #define GLPES_TCPRXONEHOLEHI 0x0055E024 /* Reset Source: CORER */
6730 #define GLPES_TCPRXONEHOLEHI_TCPRXONEHOLEHI_S 0
6731 #define GLPES_TCPRXONEHOLEHI_TCPRXONEHOLEHI_M MAKEMASK(0xFFFFFF, 0)
6732 #define GLPES_TCPRXONEHOLELO 0x0055E020 /* Reset Source: CORER */
6733 #define GLPES_TCPRXONEHOLELO_TCPRXONEHOLELO_S 0
6734 #define GLPES_TCPRXONEHOLELO_TCPRXONEHOLELO_M MAKEMASK(0xFFFFFFFF, 0)
6735 #define GLPES_TCPRXPUREACKHI 0x0055E01C /* Reset Source: CORER */
6736 #define GLPES_TCPRXPUREACKHI_TCPRXPUREACKSHI_S 0
6737 #define GLPES_TCPRXPUREACKHI_TCPRXPUREACKSHI_M MAKEMASK(0xFFFFFF, 0)
6738 #define GLPES_TCPRXPUREACKSLO 0x0055E018 /* Reset Source: CORER */
6739 #define GLPES_TCPRXPUREACKSLO_TCPRXPUREACKLO_S 0
6740 #define GLPES_TCPRXPUREACKSLO_TCPRXPUREACKLO_M MAKEMASK(0xFFFFFFFF, 0)
6741 #define GLPES_TCPRXTHREEHOLEHI 0x0055E034 /* Reset Source: CORER */
6742 #define GLPES_TCPRXTHREEHOLEHI_TCPRXTHREEHOLEHI_S 0
6743 #define GLPES_TCPRXTHREEHOLEHI_TCPRXTHREEHOLEHI_M MAKEMASK(0xFFFFFF, 0)
6744 #define GLPES_TCPRXTHREEHOLELO 0x0055E030 /* Reset Source: CORER */
6745 #define GLPES_TCPRXTHREEHOLELO_TCPRXTHREEHOLELO_S 0
6746 #define GLPES_TCPRXTHREEHOLELO_TCPRXTHREEHOLELO_M MAKEMASK(0xFFFFFFFF, 0)
6747 #define GLPES_TCPRXTWOHOLEHI 0x0055E02C /* Reset Source: CORER */
6748 #define GLPES_TCPRXTWOHOLEHI_TCPRXTWOHOLEHI_S 0
6749 #define GLPES_TCPRXTWOHOLEHI_TCPRXTWOHOLEHI_M MAKEMASK(0xFFFFFF, 0)
6750 #define GLPES_TCPRXTWOHOLELO 0x0055E028 /* Reset Source: CORER */
6751 #define GLPES_TCPRXTWOHOLELO_TCPRXTWOHOLELO_S 0
6752 #define GLPES_TCPRXTWOHOLELO_TCPRXTWOHOLELO_M MAKEMASK(0xFFFFFFFF, 0)
6753 #define GLPES_TCPTXRETRANSFASTHI 0x0055E044 /* Reset Source: CORER */
6754 #define GLPES_TCPTXRETRANSFASTHI_TCPTXRETRANSFASTHI_S 0
6755 #define GLPES_TCPTXRETRANSFASTHI_TCPTXRETRANSFASTHI_M MAKEMASK(0xFFFFFF, 0)
6756 #define GLPES_TCPTXRETRANSFASTLO 0x0055E040 /* Reset Source: CORER */
6757 #define GLPES_TCPTXRETRANSFASTLO_TCPTXRETRANSFASTLO_S 0
6758 #define GLPES_TCPTXRETRANSFASTLO_TCPTXRETRANSFASTLO_M MAKEMASK(0xFFFFFFFF, 0)
6759 #define GLPES_TCPTXTOUTSFASTHI 0x0055E04C /* Reset Source: CORER */
6760 #define GLPES_TCPTXTOUTSFASTHI_TCPTXTOUTSFASTHI_S 0
6761 #define GLPES_TCPTXTOUTSFASTHI_TCPTXTOUTSFASTHI_M MAKEMASK(0xFFFFFF, 0)
6762 #define GLPES_TCPTXTOUTSFASTLO 0x0055E048 /* Reset Source: CORER */
6763 #define GLPES_TCPTXTOUTSFASTLO_TCPTXTOUTSFASTLO_S 0
6764 #define GLPES_TCPTXTOUTSFASTLO_TCPTXTOUTSFASTLO_M MAKEMASK(0xFFFFFFFF, 0)
6765 #define GLPES_TCPTXTOUTSHI 0x0055E054 /* Reset Source: CORER */
6766 #define GLPES_TCPTXTOUTSHI_TCPTXTOUTSHI_S 0
6767 #define GLPES_TCPTXTOUTSHI_TCPTXTOUTSHI_M MAKEMASK(0xFFFFFF, 0)
6768 #define GLPES_TCPTXTOUTSLO 0x0055E050 /* Reset Source: CORER */
6769 #define GLPES_TCPTXTOUTSLO_TCPTXTOUTSLO_S 0
6770 #define GLPES_TCPTXTOUTSLO_TCPTXTOUTSLO_M MAKEMASK(0xFFFFFFFF, 0)
6771 #define GL_PWR_MODE_CTL 0x000B820C /* Reset Source: POR */
6772 #define GL_PWR_MODE_CTL_SWITCH_PWR_MODE_EN_S 0
6773 #define GL_PWR_MODE_CTL_SWITCH_PWR_MODE_EN_M BIT(0)
6774 #define GL_PWR_MODE_CTL_NIC_PWR_MODE_EN_S 1
6775 #define GL_PWR_MODE_CTL_NIC_PWR_MODE_EN_M BIT(1)
6776 #define GL_PWR_MODE_CTL_S5_PWR_MODE_EN_S 2
6777 #define GL_PWR_MODE_CTL_S5_PWR_MODE_EN_M BIT(2)
6778 #define GL_PWR_MODE_CTL_CAR_MAX_SW_CONFIG_S 3
6779 #define GL_PWR_MODE_CTL_CAR_MAX_SW_CONFIG_M MAKEMASK(0x3, 3)
6780 #define GL_PWR_MODE_CTL_CAR_MAX_BW_S 30
6781 #define GL_PWR_MODE_CTL_CAR_MAX_BW_M MAKEMASK(0x3, 30)
6782 #define GL_PWR_MODE_DIVIDE_CTRL_H_DEFAULT 0x000B825C /* Reset Source: POR */
6783 #define GL_PWR_MODE_DIVIDE_CTRL_H_DEFAULT_DEFAULT_DIV_VAL_PECLK_S 0
6784 #define GL_PWR_MODE_DIVIDE_CTRL_H_DEFAULT_DEFAULT_DIV_VAL_PECLK_M MAKEMASK(0x7, 0)
6785 #define GL_PWR_MODE_DIVIDE_CTRL_H_DEFAULT_DEFAULT_DIV_VAL_UCLK_S 3
6786 #define GL_PWR_MODE_DIVIDE_CTRL_H_DEFAULT_DEFAULT_DIV_VAL_UCLK_M MAKEMASK(0x7, 3)
6787 #define GL_PWR_MODE_DIVIDE_CTRL_H_DEFAULT_DEFAULT_DIV_VAL_LCLK_S 6
6788 #define GL_PWR_MODE_DIVIDE_CTRL_H_DEFAULT_DEFAULT_DIV_VAL_LCLK_M MAKEMASK(0x7, 6)
6789 #define GL_PWR_MODE_DIVIDE_CTRL_H_DEFAULT_DEFAULT_DIV_VAL_PSM_S 9
6790 #define GL_PWR_MODE_DIVIDE_CTRL_H_DEFAULT_DEFAULT_DIV_VAL_PSM_M MAKEMASK(0x7, 9)
6791 #define GL_PWR_MODE_DIVIDE_CTRL_H_DEFAULT_DEFAULT_DIV_VAL_RXCTL_S 12
6792 #define GL_PWR_MODE_DIVIDE_CTRL_H_DEFAULT_DEFAULT_DIV_VAL_RXCTL_M MAKEMASK(0x7, 12)
6793 #define GL_PWR_MODE_DIVIDE_CTRL_H_DEFAULT_DEFAULT_DIV_VAL_UANA_S 15
6794 #define GL_PWR_MODE_DIVIDE_CTRL_H_DEFAULT_DEFAULT_DIV_VAL_UANA_M MAKEMASK(0x7, 15)
6795 #define GL_PWR_MODE_DIVIDE_CTRL_H_DEFAULT_DEFAULT_DIV_VAL_S5_S 18
6796 #define GL_PWR_MODE_DIVIDE_CTRL_H_DEFAULT_DEFAULT_DIV_VAL_S5_M MAKEMASK(0x7, 18)
6797 #define GL_PWR_MODE_DIVIDE_CTRL_L_DEFAULT 0x000B8218 /* Reset Source: POR */
6798 #define GL_PWR_MODE_DIVIDE_CTRL_L_DEFAULT_DEFAULT_DIV_VAL_PECLK_S 0
6799 #define GL_PWR_MODE_DIVIDE_CTRL_L_DEFAULT_DEFAULT_DIV_VAL_PECLK_M MAKEMASK(0x7, 0)
6800 #define GL_PWR_MODE_DIVIDE_CTRL_L_DEFAULT_DEFAULT_DIV_VAL_UCLK_S 3
6801 #define GL_PWR_MODE_DIVIDE_CTRL_L_DEFAULT_DEFAULT_DIV_VAL_UCLK_M MAKEMASK(0x7, 3)
6802 #define GL_PWR_MODE_DIVIDE_CTRL_L_DEFAULT_DEFAULT_DIV_VAL_LCLK_S 6
6803 #define GL_PWR_MODE_DIVIDE_CTRL_L_DEFAULT_DEFAULT_DIV_VAL_LCLK_M MAKEMASK(0x7, 6)
6804 #define GL_PWR_MODE_DIVIDE_CTRL_L_DEFAULT_DEFAULT_DIV_VAL_PSM_S 9
6805 #define GL_PWR_MODE_DIVIDE_CTRL_L_DEFAULT_DEFAULT_DIV_VAL_PSM_M MAKEMASK(0x7, 9)
6806 #define GL_PWR_MODE_DIVIDE_CTRL_L_DEFAULT_DEFAULT_DIV_VAL_RXCTL_S 12
6807 #define GL_PWR_MODE_DIVIDE_CTRL_L_DEFAULT_DEFAULT_DIV_VAL_RXCTL_M MAKEMASK(0x7, 12)
6808 #define GL_PWR_MODE_DIVIDE_CTRL_L_DEFAULT_DEFAULT_DIV_VAL_UANA_S 15
6809 #define GL_PWR_MODE_DIVIDE_CTRL_L_DEFAULT_DEFAULT_DIV_VAL_UANA_M MAKEMASK(0x7, 15)
6810 #define GL_PWR_MODE_DIVIDE_CTRL_L_DEFAULT_DEFAULT_DIV_VAL_S5_S 18
6811 #define GL_PWR_MODE_DIVIDE_CTRL_L_DEFAULT_DEFAULT_DIV_VAL_S5_M MAKEMASK(0x7, 18)
6812 #define GL_PWR_MODE_DIVIDE_CTRL_M_DEFAULT 0x000B8260 /* Reset Source: POR */
6813 #define GL_PWR_MODE_DIVIDE_CTRL_M_DEFAULT_DEFAULT_DIV_VAL_PECLK_S 0
6814 #define GL_PWR_MODE_DIVIDE_CTRL_M_DEFAULT_DEFAULT_DIV_VAL_PECLK_M MAKEMASK(0x7, 0)
6815 #define GL_PWR_MODE_DIVIDE_CTRL_M_DEFAULT_DEFAULT_DIV_VAL_UCLK_S 3
6816 #define GL_PWR_MODE_DIVIDE_CTRL_M_DEFAULT_DEFAULT_DIV_VAL_UCLK_M MAKEMASK(0x7, 3)
6817 #define GL_PWR_MODE_DIVIDE_CTRL_M_DEFAULT_DEFAULT_DIV_VAL_LCLK_S 6
6818 #define GL_PWR_MODE_DIVIDE_CTRL_M_DEFAULT_DEFAULT_DIV_VAL_LCLK_M MAKEMASK(0x7, 6)
6819 #define GL_PWR_MODE_DIVIDE_CTRL_M_DEFAULT_DEFAULT_DIV_VAL_PSM_S 9
6820 #define GL_PWR_MODE_DIVIDE_CTRL_M_DEFAULT_DEFAULT_DIV_VAL_PSM_M MAKEMASK(0x7, 9)
6821 #define GL_PWR_MODE_DIVIDE_CTRL_M_DEFAULT_DEFAULT_DIV_VAL_RXCTL_S 12
6822 #define GL_PWR_MODE_DIVIDE_CTRL_M_DEFAULT_DEFAULT_DIV_VAL_RXCTL_M MAKEMASK(0x7, 12)
6823 #define GL_PWR_MODE_DIVIDE_CTRL_M_DEFAULT_DEFAULT_DIV_VAL_UANA_S 15
6824 #define GL_PWR_MODE_DIVIDE_CTRL_M_DEFAULT_DEFAULT_DIV_VAL_UANA_M MAKEMASK(0x7, 15)
6825 #define GL_PWR_MODE_DIVIDE_CTRL_M_DEFAULT_DEFAULT_DIV_VAL_S5_S 18
6826 #define GL_PWR_MODE_DIVIDE_CTRL_M_DEFAULT_DEFAULT_DIV_VAL_S5_M MAKEMASK(0x7, 18)
6827 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_LCLK 0x000B8200 /* Reset Source: POR */
6828 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_LCLK_DIV_VAL_TBW_50G_H_S 0
6829 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_LCLK_DIV_VAL_TBW_50G_H_M MAKEMASK(0x7, 0)
6830 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_LCLK_DIV_VAL_TBW_25G_H_S 3
6831 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_LCLK_DIV_VAL_TBW_25G_H_M MAKEMASK(0x7, 3)
6832 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_LCLK_DIV_VAL_TBW_10G_H_S 6
6833 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_LCLK_DIV_VAL_TBW_10G_H_M MAKEMASK(0x7, 6)
6834 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_LCLK_DIV_VAL_TBW_4G_H_S 9
6835 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_LCLK_DIV_VAL_TBW_4G_H_M MAKEMASK(0x7, 9)
6836 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_LCLK_DIV_VAL_TBW_A50G_H_S 12
6837 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_LCLK_DIV_VAL_TBW_A50G_H_M MAKEMASK(0xF, 12)
6838 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_PECLK 0x000B81F0 /* Reset Source: POR */
6839 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_PECLK_DIV_VAL_TBW_50G_H_S 0
6840 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_PECLK_DIV_VAL_TBW_50G_H_M MAKEMASK(0x7, 0)
6841 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_PECLK_DIV_VAL_TBW_25G_H_S 3
6842 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_PECLK_DIV_VAL_TBW_25G_H_M MAKEMASK(0x7, 3)
6843 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_PECLK_DIV_VAL_TBW_10G_H_S 6
6844 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_PECLK_DIV_VAL_TBW_10G_H_M MAKEMASK(0x7, 6)
6845 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_PECLK_DIV_VAL_TBW_4G_H_S 9
6846 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_PECLK_DIV_VAL_TBW_4G_H_M MAKEMASK(0x7, 9)
6847 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_PECLK_DIV_VAL_TBW_A50G_H_S 12
6848 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_PECLK_DIV_VAL_TBW_A50G_H_M MAKEMASK(0xF, 12)
6849 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_PSM 0x000B81FC /* Reset Source: POR */
6850 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_PSM_DIV_VAL_TBW_50G_H_S 0
6851 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_PSM_DIV_VAL_TBW_50G_H_M MAKEMASK(0x7, 0)
6852 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_PSM_DIV_VAL_TBW_25G_H_S 3
6853 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_PSM_DIV_VAL_TBW_25G_H_M MAKEMASK(0x7, 3)
6854 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_PSM_DIV_VAL_TBW_10G_H_S 6
6855 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_PSM_DIV_VAL_TBW_10G_H_M MAKEMASK(0x7, 6)
6856 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_PSM_DIV_VAL_TBW_4G_H_S 9
6857 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_PSM_DIV_VAL_TBW_4G_H_M MAKEMASK(0x7, 9)
6858 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_PSM_DIV_VAL_TBW_A50G_H_S 12
6859 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_PSM_DIV_VAL_TBW_A50G_H_M MAKEMASK(0xF, 12)
6860 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_RXCTL 0x000B81F8 /* Reset Source: POR */
6861 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_RXCTL_DIV_VAL_TBW_50G_H_S 0
6862 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_RXCTL_DIV_VAL_TBW_50G_H_M MAKEMASK(0x7, 0)
6863 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_RXCTL_DIV_VAL_TBW_25G_H_S 3
6864 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_RXCTL_DIV_VAL_TBW_25G_H_M MAKEMASK(0x7, 3)
6865 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_RXCTL_DIV_VAL_TBW_10G_H_S 6
6866 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_RXCTL_DIV_VAL_TBW_10G_H_M MAKEMASK(0x7, 6)
6867 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_RXCTL_DIV_VAL_TBW_4G_H_S 9
6868 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_RXCTL_DIV_VAL_TBW_4G_H_M MAKEMASK(0x7, 9)
6869 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_RXCTL_DIV_VAL_TBW_A50G_H_S 12
6870 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_RXCTL_DIV_VAL_TBW_A50G_H_M MAKEMASK(0xF, 12)
6871 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_UANA 0x000B8208 /* Reset Source: POR */
6872 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_UANA_DIV_VAL_TBW_50G_H_S 0
6873 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_UANA_DIV_VAL_TBW_50G_H_M MAKEMASK(0x7, 0)
6874 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_UANA_DIV_VAL_TBW_25G_H_S 3
6875 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_UANA_DIV_VAL_TBW_25G_H_M MAKEMASK(0x7, 3)
6876 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_UANA_DIV_VAL_TBW_10G_H_S 6
6877 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_UANA_DIV_VAL_TBW_10G_H_M MAKEMASK(0x7, 6)
6878 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_UANA_DIV_VAL_TBW_4G_H_S 9
6879 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_UANA_DIV_VAL_TBW_4G_H_M MAKEMASK(0x7, 9)
6880 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_UANA_DIV_VAL_TBW_A50G_H_S 12
6881 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_UANA_DIV_VAL_TBW_A50G_H_M MAKEMASK(0xF, 12)
6882 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_UCLK 0x000B81F4 /* Reset Source: POR */
6883 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_UCLK_DIV_VAL_TBW_50G_H_S 0
6884 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_UCLK_DIV_VAL_TBW_50G_H_M MAKEMASK(0x7, 0)
6885 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_UCLK_DIV_VAL_TBW_25G_H_S 3
6886 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_UCLK_DIV_VAL_TBW_25G_H_M MAKEMASK(0x7, 3)
6887 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_UCLK_DIV_VAL_TBW_10G_H_S 6
6888 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_UCLK_DIV_VAL_TBW_10G_H_M MAKEMASK(0x7, 6)
6889 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_UCLK_DIV_VAL_TBW_4G_H_S 9
6890 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_UCLK_DIV_VAL_TBW_4G_H_M MAKEMASK(0x7, 9)
6891 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_UCLK_DIV_VAL_TBW_A50G_H_S 12
6892 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_UCLK_DIV_VAL_TBW_A50G_H_M MAKEMASK(0xF, 12)
6893 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_LCLK 0x000B8244 /* Reset Source: POR */
6894 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_LCLK_DIV_VAL_TBW_50G_L_S 0
6895 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_LCLK_DIV_VAL_TBW_50G_L_M MAKEMASK(0x7, 0)
6896 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_LCLK_DIV_VAL_TBW_25G_L_S 3
6897 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_LCLK_DIV_VAL_TBW_25G_L_M MAKEMASK(0x7, 3)
6898 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_LCLK_DIV_VAL_TBW_10G_L_S 6
6899 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_LCLK_DIV_VAL_TBW_10G_L_M MAKEMASK(0x7, 6)
6900 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_LCLK_DIV_VAL_TBW_4G_L_S 9
6901 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_LCLK_DIV_VAL_TBW_4G_L_M MAKEMASK(0x7, 9)
6902 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_LCLK_DIV_VAL_TBW_A50G_L_S 12
6903 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_LCLK_DIV_VAL_TBW_A50G_L_M MAKEMASK(0x7, 12)
6904 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_PECLK 0x000B8220 /* Reset Source: POR */
6905 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_PECLK_DIV_VAL_TBW_50G_L_S 0
6906 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_PECLK_DIV_VAL_TBW_50G_L_M MAKEMASK(0x7, 0)
6907 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_PECLK_DIV_VAL_TBW_25G_L_S 3
6908 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_PECLK_DIV_VAL_TBW_25G_L_M MAKEMASK(0x7, 3)
6909 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_PECLK_DIV_VAL_TBW_10G_L_S 6
6910 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_PECLK_DIV_VAL_TBW_10G_L_M MAKEMASK(0x7, 6)
6911 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_PECLK_DIV_VAL_TBW_4G_L_S 9
6912 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_PECLK_DIV_VAL_TBW_4G_L_M MAKEMASK(0x7, 9)
6913 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_PECLK_DIV_VAL_TBW_A50G_L_S 12
6914 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_PECLK_DIV_VAL_TBW_A50G_L_M MAKEMASK(0x7, 12)
6915 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_PSM 0x000B8240 /* Reset Source: POR */
6916 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_PSM_DIV_VAL_TBW_50G_L_S 0
6917 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_PSM_DIV_VAL_TBW_50G_L_M MAKEMASK(0x7, 0)
6918 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_PSM_DIV_VAL_TBW_25G_L_S 3
6919 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_PSM_DIV_VAL_TBW_25G_L_M MAKEMASK(0x7, 3)
6920 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_PSM_DIV_VAL_TBW_10G_L_S 6
6921 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_PSM_DIV_VAL_TBW_10G_L_M MAKEMASK(0x7, 6)
6922 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_PSM_DIV_VAL_TBW_4G_L_S 9
6923 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_PSM_DIV_VAL_TBW_4G_L_M MAKEMASK(0x7, 9)
6924 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_PSM_DIV_VAL_TBW_A50G_L_S 12
6925 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_PSM_DIV_VAL_TBW_A50G_L_M MAKEMASK(0x7, 12)
6926 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_RXCTL 0x000B823C /* Reset Source: POR */
6927 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_RXCTL_DIV_VAL_TBW_50G_L_S 0
6928 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_RXCTL_DIV_VAL_TBW_50G_L_M MAKEMASK(0x7, 0)
6929 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_RXCTL_DIV_VAL_TBW_25G_L_S 3
6930 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_RXCTL_DIV_VAL_TBW_25G_L_M MAKEMASK(0x7, 3)
6931 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_RXCTL_DIV_VAL_TBW_10G_L_S 6
6932 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_RXCTL_DIV_VAL_TBW_10G_L_M MAKEMASK(0x7, 6)
6933 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_RXCTL_DIV_VAL_TBW_4G_L_S 9
6934 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_RXCTL_DIV_VAL_TBW_4G_L_M MAKEMASK(0x7, 9)
6935 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_RXCTL_DIV_VAL_TBW_A50G_L_S 12
6936 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_RXCTL_DIV_VAL_TBW_A50G_L_M MAKEMASK(0x7, 12)
6937 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_UANA 0x000B8248 /* Reset Source: POR */
6938 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_UANA_DIV_VAL_TBW_50G_L_S 0
6939 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_UANA_DIV_VAL_TBW_50G_L_M MAKEMASK(0x7, 0)
6940 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_UANA_DIV_VAL_TBW_25G_L_S 3
6941 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_UANA_DIV_VAL_TBW_25G_L_M MAKEMASK(0x7, 3)
6942 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_UANA_DIV_VAL_TBW_10G_L_S 6
6943 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_UANA_DIV_VAL_TBW_10G_L_M MAKEMASK(0x7, 6)
6944 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_UANA_DIV_VAL_TBW_4G_L_S 9
6945 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_UANA_DIV_VAL_TBW_4G_L_M MAKEMASK(0x7, 9)
6946 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_UANA_DIV_VAL_TBW_A50G_L_S 12
6947 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_UANA_DIV_VAL_TBW_A50G_L_M MAKEMASK(0x7, 12)
6948 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_UCLK 0x000B8238 /* Reset Source: POR */
6949 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_UCLK_DIV_VAL_TBW_50G_L_S 0
6950 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_UCLK_DIV_VAL_TBW_50G_L_M MAKEMASK(0x7, 0)
6951 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_UCLK_DIV_VAL_TBW_25G_L_S 3
6952 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_UCLK_DIV_VAL_TBW_25G_L_M MAKEMASK(0x7, 3)
6953 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_UCLK_DIV_VAL_TBW_10G_L_S 6
6954 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_UCLK_DIV_VAL_TBW_10G_L_M MAKEMASK(0x7, 6)
6955 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_UCLK_DIV_VAL_TBW_4G_L_S 9
6956 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_UCLK_DIV_VAL_TBW_4G_L_M MAKEMASK(0x7, 9)
6957 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_UCLK_DIV_VAL_TBW_A50G_L_S 12
6958 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_UCLK_DIV_VAL_TBW_A50G_L_M MAKEMASK(0x7, 12)
6959 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_LCLK 0x000B8230 /* Reset Source: POR */
6960 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_LCLK_DIV_VAL_TBW_50G_M_S 0
6961 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_LCLK_DIV_VAL_TBW_50G_M_M MAKEMASK(0x7, 0)
6962 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_LCLK_DIV_VAL_TBW_25G_M_S 3
6963 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_LCLK_DIV_VAL_TBW_25G_M_M MAKEMASK(0x7, 3)
6964 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_LCLK_DIV_VAL_TBW_10G_M_S 6
6965 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_LCLK_DIV_VAL_TBW_10G_M_M MAKEMASK(0x7, 6)
6966 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_LCLK_DIV_VAL_TBW_4G_M_S 9
6967 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_LCLK_DIV_VAL_TBW_4G_M_M MAKEMASK(0x7, 9)
6968 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_LCLK_DIV_VAL_TBW_A50G_M_S 12
6969 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_LCLK_DIV_VAL_TBW_A50G_M_M MAKEMASK(0x7, 12)
6970 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_PECLK 0x000B821C /* Reset Source: POR */
6971 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_PECLK_DIV_VAL_TBW_50G_M_S 0
6972 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_PECLK_DIV_VAL_TBW_50G_M_M MAKEMASK(0x7, 0)
6973 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_PECLK_DIV_VAL_TBW_25G_M_S 3
6974 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_PECLK_DIV_VAL_TBW_25G_M_M MAKEMASK(0x7, 3)
6975 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_PECLK_DIV_VAL_TBW_10G_M_S 6
6976 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_PECLK_DIV_VAL_TBW_10G_M_M MAKEMASK(0x7, 6)
6977 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_PECLK_DIV_VAL_TBW_4G_M_S 9
6978 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_PECLK_DIV_VAL_TBW_4G_M_M MAKEMASK(0x7, 9)
6979 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_PECLK_DIV_VAL_TBW_A50G_M_S 12
6980 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_PECLK_DIV_VAL_TBW_A50G_M_M MAKEMASK(0x7, 12)
6981 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_PSM 0x000B822C /* Reset Source: POR */
6982 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_PSM_DIV_VAL_TBW_50G_M_S 0
6983 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_PSM_DIV_VAL_TBW_50G_M_M MAKEMASK(0x7, 0)
6984 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_PSM_DIV_VAL_TBW_25G_M_S 3
6985 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_PSM_DIV_VAL_TBW_25G_M_M MAKEMASK(0x7, 3)
6986 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_PSM_DIV_VAL_TBW_10G_M_S 6
6987 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_PSM_DIV_VAL_TBW_10G_M_M MAKEMASK(0x7, 6)
6988 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_PSM_DIV_VAL_TBW_4G_M_S 9
6989 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_PSM_DIV_VAL_TBW_4G_M_M MAKEMASK(0x7, 9)
6990 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_PSM_DIV_VAL_TBW_A50G_M_S 12
6991 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_PSM_DIV_VAL_TBW_A50G_M_M MAKEMASK(0x7, 12)
6992 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_RXCTL 0x000B8228 /* Reset Source: POR */
6993 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_RXCTL_DIV_VAL_TBW_50G_M_S 0
6994 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_RXCTL_DIV_VAL_TBW_50G_M_M MAKEMASK(0x7, 0)
6995 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_RXCTL_DIV_VAL_TBW_25G_M_S 3
6996 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_RXCTL_DIV_VAL_TBW_25G_M_M MAKEMASK(0x7, 3)
6997 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_RXCTL_DIV_VAL_TBW_10G_M_S 6
6998 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_RXCTL_DIV_VAL_TBW_10G_M_M MAKEMASK(0x7, 6)
6999 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_RXCTL_DIV_VAL_TBW_4G_M_S 9
7000 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_RXCTL_DIV_VAL_TBW_4G_M_M MAKEMASK(0x7, 9)
7001 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_RXCTL_DIV_VAL_TBW_A50G_M_S 12
7002 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_RXCTL_DIV_VAL_TBW_A50G_M_M MAKEMASK(0x7, 12)
7003 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_UANA 0x000B8234 /* Reset Source: POR */
7004 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_UANA_DIV_VAL_TBW_50G_M_S 0
7005 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_UANA_DIV_VAL_TBW_50G_M_M MAKEMASK(0x7, 0)
7006 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_UANA_DIV_VAL_TBW_25G_M_S 3
7007 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_UANA_DIV_VAL_TBW_25G_M_M MAKEMASK(0x7, 3)
7008 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_UANA_DIV_VAL_TBW_10G_M_S 6
7009 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_UANA_DIV_VAL_TBW_10G_M_M MAKEMASK(0x7, 6)
7010 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_UANA_DIV_VAL_TBW_4G_M_S 9
7011 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_UANA_DIV_VAL_TBW_4G_M_M MAKEMASK(0x7, 9)
7012 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_UANA_DIV_VAL_TBW_A50G_M_S 12
7013 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_UANA_DIV_VAL_TBW_A50G_M_M MAKEMASK(0x7, 12)
7014 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_UCLK 0x000B8224 /* Reset Source: POR */
7015 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_UCLK_DIV_VAL_TBW_50G_M_S 0
7016 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_UCLK_DIV_VAL_TBW_50G_M_M MAKEMASK(0x7, 0)
7017 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_UCLK_DIV_VAL_TBW_25G_M_S 3
7018 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_UCLK_DIV_VAL_TBW_25G_M_M MAKEMASK(0x7, 3)
7019 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_UCLK_DIV_VAL_TBW_10G_M_S 6
7020 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_UCLK_DIV_VAL_TBW_10G_M_M MAKEMASK(0x7, 6)
7021 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_UCLK_DIV_VAL_TBW_4G_M_S 9
7022 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_UCLK_DIV_VAL_TBW_4G_M_M MAKEMASK(0x7, 9)
7023 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_UCLK_DIV_VAL_TBW_A50G_M_S 12
7024 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_UCLK_DIV_VAL_TBW_A50G_M_M MAKEMASK(0x7, 12)
7025 #define GL_PWR_MODE_DIVIDE_S5_H_CTRL 0x000B81EC /* Reset Source: POR */
7026 #define GL_PWR_MODE_DIVIDE_S5_H_CTRL_DIV_VAL_TBW_50G_H_S 0
7027 #define GL_PWR_MODE_DIVIDE_S5_H_CTRL_DIV_VAL_TBW_50G_H_M MAKEMASK(0x7, 0)
7028 #define GL_PWR_MODE_DIVIDE_S5_H_CTRL_DIV_VAL_TBW_25G_H_S 3
7029 #define GL_PWR_MODE_DIVIDE_S5_H_CTRL_DIV_VAL_TBW_25G_H_M MAKEMASK(0x7, 3)
7030 #define GL_PWR_MODE_DIVIDE_S5_H_CTRL_DIV_VAL_TBW_10G_H_S 6
7031 #define GL_PWR_MODE_DIVIDE_S5_H_CTRL_DIV_VAL_TBW_10G_H_M MAKEMASK(0x7, 6)
7032 #define GL_PWR_MODE_DIVIDE_S5_H_CTRL_DIV_VAL_TBW_4G_H_S 9
7033 #define GL_PWR_MODE_DIVIDE_S5_H_CTRL_DIV_VAL_TBW_4G_H_M MAKEMASK(0x7, 9)
7034 #define GL_PWR_MODE_DIVIDE_S5_H_CTRL_DIV_VAL_TBW_A50G_H_S 12
7035 #define GL_PWR_MODE_DIVIDE_S5_H_CTRL_DIV_VAL_TBW_A50G_H_M MAKEMASK(0xF, 12)
7036 #define GL_PWR_MODE_DIVIDE_S5_L_CTRL 0x000B824C /* Reset Source: POR */
7037 #define GL_PWR_MODE_DIVIDE_S5_L_CTRL_DIV_VAL_TBW_50G_L_S 0
7038 #define GL_PWR_MODE_DIVIDE_S5_L_CTRL_DIV_VAL_TBW_50G_L_M MAKEMASK(0x7, 0)
7039 #define GL_PWR_MODE_DIVIDE_S5_L_CTRL_DIV_VAL_TBW_25G_L_S 3
7040 #define GL_PWR_MODE_DIVIDE_S5_L_CTRL_DIV_VAL_TBW_25G_L_M MAKEMASK(0x7, 3)
7041 #define GL_PWR_MODE_DIVIDE_S5_L_CTRL_DIV_VAL_TBW_10G_L_S 6
7042 #define GL_PWR_MODE_DIVIDE_S5_L_CTRL_DIV_VAL_TBW_10G_L_M MAKEMASK(0x7, 6)
7043 #define GL_PWR_MODE_DIVIDE_S5_L_CTRL_DIV_VAL_TBW_4G_L_S 9
7044 #define GL_PWR_MODE_DIVIDE_S5_L_CTRL_DIV_VAL_TBW_4G_L_M MAKEMASK(0x7, 9)
7045 #define GL_PWR_MODE_DIVIDE_S5_L_CTRL_DIV_VAL_TBW_A50G_L_S 12
7046 #define GL_PWR_MODE_DIVIDE_S5_L_CTRL_DIV_VAL_TBW_A50G_L_M MAKEMASK(0x7, 12)
7047 #define GL_PWR_MODE_DIVIDE_S5_M_CTRL 0x000B8250 /* Reset Source: POR */
7048 #define GL_PWR_MODE_DIVIDE_S5_M_CTRL_DIV_VAL_TBW_50G_M_S 0
7049 #define GL_PWR_MODE_DIVIDE_S5_M_CTRL_DIV_VAL_TBW_50G_M_M MAKEMASK(0x7, 0)
7050 #define GL_PWR_MODE_DIVIDE_S5_M_CTRL_DIV_VAL_TBW_25G_M_S 3
7051 #define GL_PWR_MODE_DIVIDE_S5_M_CTRL_DIV_VAL_TBW_25G_M_M MAKEMASK(0x7, 3)
7052 #define GL_PWR_MODE_DIVIDE_S5_M_CTRL_DIV_VAL_TBW_10G_M_S 6
7053 #define GL_PWR_MODE_DIVIDE_S5_M_CTRL_DIV_VAL_TBW_10G_M_M MAKEMASK(0x7, 6)
7054 #define GL_PWR_MODE_DIVIDE_S5_M_CTRL_DIV_VAL_TBW_4G_M_S 9
7055 #define GL_PWR_MODE_DIVIDE_S5_M_CTRL_DIV_VAL_TBW_4G_M_M MAKEMASK(0x7, 9)
7056 #define GL_PWR_MODE_DIVIDE_S5_M_CTRL_DIV_VAL_TBW_A50G_M_S 12
7057 #define GL_PWR_MODE_DIVIDE_S5_M_CTRL_DIV_VAL_TBW_A50G_M_M MAKEMASK(0x7, 12)
7058 #define GL_S5_PWR_MODE_EXIT_CTL 0x000B8270 /* Reset Source: POR */
7059 #define GL_S5_PWR_MODE_EXIT_CTL_S5_PWR_MODE_AUTO_EXIT_S 0
7060 #define GL_S5_PWR_MODE_EXIT_CTL_S5_PWR_MODE_AUTO_EXIT_M BIT(0)
7061 #define GL_S5_PWR_MODE_EXIT_CTL_S5_PWR_MODE_FW_EXIT_S 1
7062 #define GL_S5_PWR_MODE_EXIT_CTL_S5_PWR_MODE_FW_EXIT_M BIT(1)
7063 #define GL_S5_PWR_MODE_EXIT_CTL_S5_PWR_MODE_PRST_FLOWS_ON_CORER_S 3
7064 #define GL_S5_PWR_MODE_EXIT_CTL_S5_PWR_MODE_PRST_FLOWS_ON_CORER_M BIT(3)
7065 #define GLGEN_PME_TO 0x000B81BC /* Reset Source: POR */
7066 #define GLGEN_PME_TO_PME_TO_FOR_PE_S 0
7067 #define GLGEN_PME_TO_PME_TO_FOR_PE_M BIT(0)
7068 #define PRTPM_EEE_STAT 0x001E4320 /* Reset Source: GLOBR */
7069 #define PRTPM_EEE_STAT_EEE_NEG_S 29
7070 #define PRTPM_EEE_STAT_EEE_NEG_M BIT(29)
7071 #define PRTPM_EEE_STAT_RX_LPI_STATUS_S 30
7072 #define PRTPM_EEE_STAT_RX_LPI_STATUS_M BIT(30)
7073 #define PRTPM_EEE_STAT_TX_LPI_STATUS_S 31
7074 #define PRTPM_EEE_STAT_TX_LPI_STATUS_M BIT(31)
7075 #define PRTPM_EEEC 0x001E4380 /* Reset Source: GLOBR */
7076 #define PRTPM_EEEC_TW_WAKE_MIN_S 16
7077 #define PRTPM_EEEC_TW_WAKE_MIN_M MAKEMASK(0x3F, 16)
7078 #define PRTPM_EEEC_TX_LU_LPI_DLY_S 24
7079 #define PRTPM_EEEC_TX_LU_LPI_DLY_M MAKEMASK(0x3, 24)
7080 #define PRTPM_EEEC_TEEE_DLY_S 26
7081 #define PRTPM_EEEC_TEEE_DLY_M MAKEMASK(0x3F, 26)
7082 #define PRTPM_EEEFWD 0x001E4400 /* Reset Source: GLOBR */
7083 #define PRTPM_EEEFWD_EEE_FW_CONFIG_DONE_S 31
7084 #define PRTPM_EEEFWD_EEE_FW_CONFIG_DONE_M BIT(31)
7085 #define PRTPM_EEER 0x001E4360 /* Reset Source: GLOBR */
7086 #define PRTPM_EEER_TW_SYSTEM_S 0
7087 #define PRTPM_EEER_TW_SYSTEM_M MAKEMASK(0xFFFF, 0)
7088 #define PRTPM_EEER_TX_LPI_EN_S 16
7089 #define PRTPM_EEER_TX_LPI_EN_M BIT(16)
7090 #define PRTPM_EEETXC 0x001E43E0 /* Reset Source: GLOBR */
7091 #define PRTPM_EEETXC_TW_PHY_S 0
7092 #define PRTPM_EEETXC_TW_PHY_M MAKEMASK(0xFFFF, 0)
7093 #define PRTPM_RLPIC 0x001E43A0 /* Reset Source: GLOBR */
7094 #define PRTPM_RLPIC_ERLPIC_S 0
7095 #define PRTPM_RLPIC_ERLPIC_M MAKEMASK(0xFFFFFFFF, 0)
7096 #define PRTPM_TLPIC 0x001E43C0 /* Reset Source: GLOBR */
7097 #define PRTPM_TLPIC_ETLPIC_S 0
7098 #define PRTPM_TLPIC_ETLPIC_M MAKEMASK(0xFFFFFFFF, 0)
7099 #define GLRPB_DHW(_i) (0x000AC000 + ((_i) * 4)) /* _i=0...15 */ /* Reset Source: CORER */
7100 #define GLRPB_DHW_MAX_INDEX 15
7101 #define GLRPB_DHW_DHW_TCN_S 0
7102 #define GLRPB_DHW_DHW_TCN_M MAKEMASK(0xFFFFF, 0)
7103 #define GLRPB_DLW(_i) (0x000AC044 + ((_i) * 4)) /* _i=0...15 */ /* Reset Source: CORER */
7104 #define GLRPB_DLW_MAX_INDEX 15
7105 #define GLRPB_DLW_DLW_TCN_S 0
7106 #define GLRPB_DLW_DLW_TCN_M MAKEMASK(0xFFFFF, 0)
7107 #define GLRPB_DPS(_i) (0x000AC084 + ((_i) * 4)) /* _i=0...15 */ /* Reset Source: CORER */
7108 #define GLRPB_DPS_MAX_INDEX 15
7109 #define GLRPB_DPS_DPS_TCN_S 0
7110 #define GLRPB_DPS_DPS_TCN_M MAKEMASK(0xFFFFF, 0)
7111 #define GLRPB_DSI_EN 0x000AC324 /* Reset Source: CORER */
7112 #define GLRPB_DSI_EN_DSI_EN_S 0
7113 #define GLRPB_DSI_EN_DSI_EN_M BIT(0)
7114 #define GLRPB_DSI_EN_DSI_L2_MAC_ERR_DROP_EN_S 1
7115 #define GLRPB_DSI_EN_DSI_L2_MAC_ERR_DROP_EN_M BIT(1)
7116 #define GLRPB_SHW(_i) (0x000AC120 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
7117 #define GLRPB_SHW_MAX_INDEX 7
7118 #define GLRPB_SHW_SHW_S 0
7119 #define GLRPB_SHW_SHW_M MAKEMASK(0xFFFFF, 0)
7120 #define GLRPB_SLW(_i) (0x000AC140 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
7121 #define GLRPB_SLW_MAX_INDEX 7
7122 #define GLRPB_SLW_SLW_S 0
7123 #define GLRPB_SLW_SLW_M MAKEMASK(0xFFFFF, 0)
7124 #define GLRPB_SPS(_i) (0x000AC0C4 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
7125 #define GLRPB_SPS_MAX_INDEX 7
7126 #define GLRPB_SPS_SPS_TCN_S 0
7127 #define GLRPB_SPS_SPS_TCN_M MAKEMASK(0xFFFFF, 0)
7128 #define GLRPB_TC_CFG(_i) (0x000AC2A4 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
7129 #define GLRPB_TC_CFG_MAX_INDEX 31
7130 #define GLRPB_TC_CFG_D_POOL_S 0
7131 #define GLRPB_TC_CFG_D_POOL_M MAKEMASK(0xFFFF, 0)
7132 #define GLRPB_TC_CFG_S_POOL_S 16
7133 #define GLRPB_TC_CFG_S_POOL_M MAKEMASK(0xFFFF, 16)
7134 #define GLRPB_TCHW(_i) (0x000AC330 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
7135 #define GLRPB_TCHW_MAX_INDEX 31
7136 #define GLRPB_TCHW_TCHW_S 0
7137 #define GLRPB_TCHW_TCHW_M MAKEMASK(0xFFFFF, 0)
7138 #define GLRPB_TCLW(_i) (0x000AC3B0 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
7139 #define GLRPB_TCLW_MAX_INDEX 31
7140 #define GLRPB_TCLW_TCLW_S 0
7141 #define GLRPB_TCLW_TCLW_M MAKEMASK(0xFFFFF, 0)
7142 #define GLQF_APBVT(_i) (0x00450000 + ((_i) * 4)) /* _i=0...2047 */ /* Reset Source: CORER */
7143 #define GLQF_APBVT_MAX_INDEX 2047
7144 #define GLQF_APBVT_APBVT_S 0
7145 #define GLQF_APBVT_APBVT_M MAKEMASK(0xFFFFFFFF, 0)
7146 #define GLQF_FD_CLSN_0 0x00460028 /* Reset Source: CORER */
7147 #define GLQF_FD_CLSN_0_HITSBCNT_S 0
7148 #define GLQF_FD_CLSN_0_HITSBCNT_M MAKEMASK(0xFFFFFFFF, 0)
7149 #define GLQF_FD_CLSN1 0x00460030 /* Reset Source: CORER */
7150 #define GLQF_FD_CLSN1_HITLBCNT_S 0
7151 #define GLQF_FD_CLSN1_HITLBCNT_M MAKEMASK(0xFFFFFFFF, 0)
7152 #define GLQF_FD_CNT 0x00460018 /* Reset Source: CORER */
7153 #define GLQF_FD_CNT_FD_GCNT_S 0
7154 #define GLQF_FD_CNT_FD_GCNT_M MAKEMASK(0x7FFF, 0)
7155 #define GLQF_FD_CNT_FD_BCNT_S 16
7156 #define GLQF_FD_CNT_FD_BCNT_M MAKEMASK(0x7FFF, 16)
7157 #define GLQF_FD_CTL 0x00460000 /* Reset Source: CORER */
7158 #define GLQF_FD_CTL_FDLONG_S 0
7159 #define GLQF_FD_CTL_FDLONG_M MAKEMASK(0xF, 0)
7160 #define GLQF_FD_CTL_HASH_REPORT_S 4
7161 #define GLQF_FD_CTL_HASH_REPORT_M BIT(4)
7162 #define GLQF_FD_CTL_FLT_ADDR_REPORT_S 5
7163 #define GLQF_FD_CTL_FLT_ADDR_REPORT_M BIT(5)
7164 #define GLQF_FD_SIZE 0x00460010 /* Reset Source: CORER */
7165 #define GLQF_FD_SIZE_FD_GSIZE_S 0
7166 #define GLQF_FD_SIZE_FD_GSIZE_M MAKEMASK(0x7FFF, 0)
7167 #define GLQF_FD_SIZE_FD_BSIZE_S 16
7168 #define GLQF_FD_SIZE_FD_BSIZE_M MAKEMASK(0x7FFF, 16)
7169 #define GLQF_FDCNT_0 0x00460020 /* Reset Source: CORER */
7170 #define GLQF_FDCNT_0_BUCKETCNT_S 0
7171 #define GLQF_FDCNT_0_BUCKETCNT_M MAKEMASK(0x7FFF, 0)
7172 #define GLQF_FDCNT_0_CNT_NOT_VLD_S 31
7173 #define GLQF_FDCNT_0_CNT_NOT_VLD_M BIT(31)
7174 #define GLQF_FDEVICTENA(_i) (0x00452000 + ((_i) * 4)) /* _i=0...3 */ /* Reset Source: CORER */
7175 #define GLQF_FDEVICTENA_MAX_INDEX 3
7176 #define GLQF_FDEVICTENA_FDEVICTENA_S 0
7177 #define GLQF_FDEVICTENA_FDEVICTENA_M MAKEMASK(0xFFFFFFFF, 0)
7178 #define GLQF_FDINSET(_i, _j) (0x00412000 + ((_i) * 4 + (_j) * 512)) /* _i=0...127, _j=0...5 */ /* Reset Source: CORER */
7179 #define GLQF_FDINSET_MAX_INDEX 127
7180 #define GLQF_FDINSET_FV_WORD_INDX0_S 0
7181 #define GLQF_FDINSET_FV_WORD_INDX0_M MAKEMASK(0x1F, 0)
7182 #define GLQF_FDINSET_FV_WORD_VAL0_S 7
7183 #define GLQF_FDINSET_FV_WORD_VAL0_M BIT(7)
7184 #define GLQF_FDINSET_FV_WORD_INDX1_S 8
7185 #define GLQF_FDINSET_FV_WORD_INDX1_M MAKEMASK(0x1F, 8)
7186 #define GLQF_FDINSET_FV_WORD_VAL1_S 15
7187 #define GLQF_FDINSET_FV_WORD_VAL1_M BIT(15)
7188 #define GLQF_FDINSET_FV_WORD_INDX2_S 16
7189 #define GLQF_FDINSET_FV_WORD_INDX2_M MAKEMASK(0x1F, 16)
7190 #define GLQF_FDINSET_FV_WORD_VAL2_S 23
7191 #define GLQF_FDINSET_FV_WORD_VAL2_M BIT(23)
7192 #define GLQF_FDINSET_FV_WORD_INDX3_S 24
7193 #define GLQF_FDINSET_FV_WORD_INDX3_M MAKEMASK(0x1F, 24)
7194 #define GLQF_FDINSET_FV_WORD_VAL3_S 31
7195 #define GLQF_FDINSET_FV_WORD_VAL3_M BIT(31)
7196 #define GLQF_FDMASK(_i) (0x00410800 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
7197 #define GLQF_FDMASK_MAX_INDEX 31
7198 #define GLQF_FDMASK_MSK_INDEX_S 0
7199 #define GLQF_FDMASK_MSK_INDEX_M MAKEMASK(0x1F, 0)
7200 #define GLQF_FDMASK_MASK_S 16
7201 #define GLQF_FDMASK_MASK_M MAKEMASK(0xFFFF, 16)
7202 #define GLQF_FDMASK_SEL(_i) (0x00410400 + ((_i) * 4)) /* _i=0...127 */ /* Reset Source: CORER */
7203 #define GLQF_FDMASK_SEL_MAX_INDEX 127
7204 #define GLQF_FDMASK_SEL_MASK_SEL_S 0
7205 #define GLQF_FDMASK_SEL_MASK_SEL_M MAKEMASK(0xFFFFFFFF, 0)
7206 #define GLQF_FDSWAP(_i, _j) (0x00413000 + ((_i) * 4 + (_j) * 512)) /* _i=0...127, _j=0...5 */ /* Reset Source: CORER */
7207 #define GLQF_FDSWAP_MAX_INDEX 127
7208 #define GLQF_FDSWAP_FV_WORD_INDX0_S 0
7209 #define GLQF_FDSWAP_FV_WORD_INDX0_M MAKEMASK(0x1F, 0)
7210 #define GLQF_FDSWAP_FV_WORD_VAL0_S 7
7211 #define GLQF_FDSWAP_FV_WORD_VAL0_M BIT(7)
7212 #define GLQF_FDSWAP_FV_WORD_INDX1_S 8
7213 #define GLQF_FDSWAP_FV_WORD_INDX1_M MAKEMASK(0x1F, 8)
7214 #define GLQF_FDSWAP_FV_WORD_VAL1_S 15
7215 #define GLQF_FDSWAP_FV_WORD_VAL1_M BIT(15)
7216 #define GLQF_FDSWAP_FV_WORD_INDX2_S 16
7217 #define GLQF_FDSWAP_FV_WORD_INDX2_M MAKEMASK(0x1F, 16)
7218 #define GLQF_FDSWAP_FV_WORD_VAL2_S 23
7219 #define GLQF_FDSWAP_FV_WORD_VAL2_M BIT(23)
7220 #define GLQF_FDSWAP_FV_WORD_INDX3_S 24
7221 #define GLQF_FDSWAP_FV_WORD_INDX3_M MAKEMASK(0x1F, 24)
7222 #define GLQF_FDSWAP_FV_WORD_VAL3_S 31
7223 #define GLQF_FDSWAP_FV_WORD_VAL3_M BIT(31)
7224 #define GLQF_HINSET(_i, _j) (0x0040E000 + ((_i) * 4 + (_j) * 512)) /* _i=0...127, _j=0...5 */ /* Reset Source: CORER */
7225 #define GLQF_HINSET_MAX_INDEX 127
7226 #define GLQF_HINSET_FV_WORD_INDX0_S 0
7227 #define GLQF_HINSET_FV_WORD_INDX0_M MAKEMASK(0x1F, 0)
7228 #define GLQF_HINSET_FV_WORD_VAL0_S 7
7229 #define GLQF_HINSET_FV_WORD_VAL0_M BIT(7)
7230 #define GLQF_HINSET_FV_WORD_INDX1_S 8
7231 #define GLQF_HINSET_FV_WORD_INDX1_M MAKEMASK(0x1F, 8)
7232 #define GLQF_HINSET_FV_WORD_VAL1_S 15
7233 #define GLQF_HINSET_FV_WORD_VAL1_M BIT(15)
7234 #define GLQF_HINSET_FV_WORD_INDX2_S 16
7235 #define GLQF_HINSET_FV_WORD_INDX2_M MAKEMASK(0x1F, 16)
7236 #define GLQF_HINSET_FV_WORD_VAL2_S 23
7237 #define GLQF_HINSET_FV_WORD_VAL2_M BIT(23)
7238 #define GLQF_HINSET_FV_WORD_INDX3_S 24
7239 #define GLQF_HINSET_FV_WORD_INDX3_M MAKEMASK(0x1F, 24)
7240 #define GLQF_HINSET_FV_WORD_VAL3_S 31
7241 #define GLQF_HINSET_FV_WORD_VAL3_M BIT(31)
7242 #define GLQF_HKEY(_i) (0x00456000 + ((_i) * 4)) /* _i=0...12 */ /* Reset Source: CORER */
7243 #define GLQF_HKEY_MAX_INDEX 12
7244 #define GLQF_HKEY_KEY_0_S 0
7245 #define GLQF_HKEY_KEY_0_M MAKEMASK(0xFF, 0)
7246 #define GLQF_HKEY_KEY_1_S 8
7247 #define GLQF_HKEY_KEY_1_M MAKEMASK(0xFF, 8)
7248 #define GLQF_HKEY_KEY_2_S 16
7249 #define GLQF_HKEY_KEY_2_M MAKEMASK(0xFF, 16)
7250 #define GLQF_HKEY_KEY_3_S 24
7251 #define GLQF_HKEY_KEY_3_M MAKEMASK(0xFF, 24)
7252 #define GLQF_HLUT(_i, _j) (0x00438000 + ((_i) * 4 + (_j) * 512)) /* _i=0...127, _j=0...15 */ /* Reset Source: CORER */
7253 #define GLQF_HLUT_MAX_INDEX 127
7254 #define GLQF_HLUT_LUT0_S 0
7255 #define GLQF_HLUT_LUT0_M MAKEMASK(0x3F, 0)
7256 #define GLQF_HLUT_LUT1_S 8
7257 #define GLQF_HLUT_LUT1_M MAKEMASK(0x3F, 8)
7258 #define GLQF_HLUT_LUT2_S 16
7259 #define GLQF_HLUT_LUT2_M MAKEMASK(0x3F, 16)
7260 #define GLQF_HLUT_LUT3_S 24
7261 #define GLQF_HLUT_LUT3_M MAKEMASK(0x3F, 24)
7262 #define GLQF_HLUT_SIZE(_i) (0x00455400 + ((_i) * 4)) /* _i=0...15 */ /* Reset Source: CORER */
7263 #define GLQF_HLUT_SIZE_MAX_INDEX 15
7264 #define GLQF_HLUT_SIZE_HSIZE_S 0
7265 #define GLQF_HLUT_SIZE_HSIZE_M BIT(0)
7266 #define GLQF_HMASK(_i) (0x0040FC00 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
7267 #define GLQF_HMASK_MAX_INDEX 31
7268 #define GLQF_HMASK_MSK_INDEX_S 0
7269 #define GLQF_HMASK_MSK_INDEX_M MAKEMASK(0x1F, 0)
7270 #define GLQF_HMASK_MASK_S 16
7271 #define GLQF_HMASK_MASK_M MAKEMASK(0xFFFF, 16)
7272 #define GLQF_HMASK_SEL(_i) (0x00410000 + ((_i) * 4)) /* _i=0...127 */ /* Reset Source: CORER */
7273 #define GLQF_HMASK_SEL_MAX_INDEX 127
7274 #define GLQF_HMASK_SEL_MASK_SEL_S 0
7275 #define GLQF_HMASK_SEL_MASK_SEL_M MAKEMASK(0xFFFFFFFF, 0)
7276 #define GLQF_HSYMM(_i, _j) (0x0040F000 + ((_i) * 4 + (_j) * 512)) /* _i=0...127, _j=0...5 */ /* Reset Source: CORER */
7277 #define GLQF_HSYMM_MAX_INDEX 127
7278 #define GLQF_HSYMM_FV_SYMM_INDX0_S 0
7279 #define GLQF_HSYMM_FV_SYMM_INDX0_M MAKEMASK(0x1F, 0)
7280 #define GLQF_HSYMM_SYMM0_ENA_S 7
7281 #define GLQF_HSYMM_SYMM0_ENA_M BIT(7)
7282 #define GLQF_HSYMM_FV_SYMM_INDX1_S 8
7283 #define GLQF_HSYMM_FV_SYMM_INDX1_M MAKEMASK(0x1F, 8)
7284 #define GLQF_HSYMM_SYMM1_ENA_S 15
7285 #define GLQF_HSYMM_SYMM1_ENA_M BIT(15)
7286 #define GLQF_HSYMM_FV_SYMM_INDX2_S 16
7287 #define GLQF_HSYMM_FV_SYMM_INDX2_M MAKEMASK(0x1F, 16)
7288 #define GLQF_HSYMM_SYMM2_ENA_S 23
7289 #define GLQF_HSYMM_SYMM2_ENA_M BIT(23)
7290 #define GLQF_HSYMM_FV_SYMM_INDX3_S 24
7291 #define GLQF_HSYMM_FV_SYMM_INDX3_M MAKEMASK(0x1F, 24)
7292 #define GLQF_HSYMM_SYMM3_ENA_S 31
7293 #define GLQF_HSYMM_SYMM3_ENA_M BIT(31)
7294 #define GLQF_PE_APBVT_CNT 0x00455500 /* Reset Source: CORER */
7295 #define GLQF_PE_APBVT_CNT_APBVT_LAN_S 0
7296 #define GLQF_PE_APBVT_CNT_APBVT_LAN_M MAKEMASK(0xFFFFFFFF, 0)
7297 #define GLQF_PE_CMD 0x00471080 /* Reset Source: CORER */
7298 #define GLQF_PE_CMD_ADDREM_STS_S 0
7299 #define GLQF_PE_CMD_ADDREM_STS_M MAKEMASK(0xFFFFFF, 0)
7300 #define GLQF_PE_CMD_ADDREM_ID_S 28
7301 #define GLQF_PE_CMD_ADDREM_ID_M MAKEMASK(0xF, 28)
7302 #define GLQF_PE_CTL 0x004710C0 /* Reset Source: CORER */
7303 #define GLQF_PE_CTL_PELONG_S 0
7304 #define GLQF_PE_CTL_PELONG_M MAKEMASK(0xF, 0)
7305 #define GLQF_PE_CTL2(_i) (0x00455200 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
7306 #define GLQF_PE_CTL2_MAX_INDEX 31
7307 #define GLQF_PE_CTL2_TO_QH_S 0
7308 #define GLQF_PE_CTL2_TO_QH_M MAKEMASK(0x3, 0)
7309 #define GLQF_PE_CTL2_APBVT_ENA_S 2
7310 #define GLQF_PE_CTL2_APBVT_ENA_M BIT(2)
7311 #define GLQF_PE_FVE 0x0020E514 /* Reset Source: CORER */
7312 #define GLQF_PE_FVE_W_ENA_S 0
7313 #define GLQF_PE_FVE_W_ENA_M MAKEMASK(0xFFFFFF, 0)
7314 #define GLQF_PE_OSR_STS 0x00471040 /* Reset Source: CORER */
7315 #define GLQF_PE_OSR_STS_QH_SRCH_MAXOSR_S 0
7316 #define GLQF_PE_OSR_STS_QH_SRCH_MAXOSR_M MAKEMASK(0x3FF, 0)
7317 #define GLQF_PE_OSR_STS_QH_CMD_MAXOSR_S 16
7318 #define GLQF_PE_OSR_STS_QH_CMD_MAXOSR_M MAKEMASK(0x3FF, 16)
7319 #define GLQF_PEINSET(_i, _j) (0x00415000 + ((_i) * 4 + (_j) * 128)) /* _i=0...31, _j=0...5 */ /* Reset Source: CORER */
7320 #define GLQF_PEINSET_MAX_INDEX 31
7321 #define GLQF_PEINSET_FV_WORD_INDX0_S 0
7322 #define GLQF_PEINSET_FV_WORD_INDX0_M MAKEMASK(0x1F, 0)
7323 #define GLQF_PEINSET_FV_WORD_VAL0_S 7
7324 #define GLQF_PEINSET_FV_WORD_VAL0_M BIT(7)
7325 #define GLQF_PEINSET_FV_WORD_INDX1_S 8
7326 #define GLQF_PEINSET_FV_WORD_INDX1_M MAKEMASK(0x1F, 8)
7327 #define GLQF_PEINSET_FV_WORD_VAL1_S 15
7328 #define GLQF_PEINSET_FV_WORD_VAL1_M BIT(15)
7329 #define GLQF_PEINSET_FV_WORD_INDX2_S 16
7330 #define GLQF_PEINSET_FV_WORD_INDX2_M MAKEMASK(0x1F, 16)
7331 #define GLQF_PEINSET_FV_WORD_VAL2_S 23
7332 #define GLQF_PEINSET_FV_WORD_VAL2_M BIT(23)
7333 #define GLQF_PEINSET_FV_WORD_INDX3_S 24
7334 #define GLQF_PEINSET_FV_WORD_INDX3_M MAKEMASK(0x1F, 24)
7335 #define GLQF_PEINSET_FV_WORD_VAL3_S 31
7336 #define GLQF_PEINSET_FV_WORD_VAL3_M BIT(31)
7337 #define GLQF_PEMASK(_i) (0x00415400 + ((_i) * 4)) /* _i=0...15 */ /* Reset Source: CORER */
7338 #define GLQF_PEMASK_MAX_INDEX 15
7339 #define GLQF_PEMASK_MSK_INDEX_S 0
7340 #define GLQF_PEMASK_MSK_INDEX_M MAKEMASK(0x1F, 0)
7341 #define GLQF_PEMASK_MASK_S 16
7342 #define GLQF_PEMASK_MASK_M MAKEMASK(0xFFFF, 16)
7343 #define GLQF_PEMASK_SEL(_i) (0x00415500 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
7344 #define GLQF_PEMASK_SEL_MAX_INDEX 31
7345 #define GLQF_PEMASK_SEL_MASK_SEL_S 0
7346 #define GLQF_PEMASK_SEL_MASK_SEL_M MAKEMASK(0xFFFF, 0)
7347 #define GLQF_PETABLE_CLR(_i) (0x000AA078 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */
7348 #define GLQF_PETABLE_CLR_MAX_INDEX 1
7349 #define GLQF_PETABLE_CLR_VM_VF_NUM_S 0
7350 #define GLQF_PETABLE_CLR_VM_VF_NUM_M MAKEMASK(0x3FF, 0)
7351 #define GLQF_PETABLE_CLR_VM_VF_TYPE_S 10
7352 #define GLQF_PETABLE_CLR_VM_VF_TYPE_M MAKEMASK(0x3, 10)
7353 #define GLQF_PETABLE_CLR_PF_NUM_S 12
7354 #define GLQF_PETABLE_CLR_PF_NUM_M MAKEMASK(0x7, 12)
7355 #define GLQF_PETABLE_CLR_PE_BUSY_S 16
7356 #define GLQF_PETABLE_CLR_PE_BUSY_M BIT(16)
7357 #define GLQF_PETABLE_CLR_PE_CLEAR_S 17
7358 #define GLQF_PETABLE_CLR_PE_CLEAR_M BIT(17)
7359 #define GLQF_PROF2TC(_i, _j) (0x0044D000 + ((_i) * 4 + (_j) * 512)) /* _i=0...127, _j=0...3 */ /* Reset Source: CORER */
7360 #define GLQF_PROF2TC_MAX_INDEX 127
7361 #define GLQF_PROF2TC_OVERRIDE_ENA_0_S 0
7362 #define GLQF_PROF2TC_OVERRIDE_ENA_0_M BIT(0)
7363 #define GLQF_PROF2TC_REGION_0_S 1
7364 #define GLQF_PROF2TC_REGION_0_M MAKEMASK(0x7, 1)
7365 #define GLQF_PROF2TC_OVERRIDE_ENA_1_S 4
7366 #define GLQF_PROF2TC_OVERRIDE_ENA_1_M BIT(4)
7367 #define GLQF_PROF2TC_REGION_1_S 5
7368 #define GLQF_PROF2TC_REGION_1_M MAKEMASK(0x7, 5)
7369 #define GLQF_PROF2TC_OVERRIDE_ENA_2_S 8
7370 #define GLQF_PROF2TC_OVERRIDE_ENA_2_M BIT(8)
7371 #define GLQF_PROF2TC_REGION_2_S 9
7372 #define GLQF_PROF2TC_REGION_2_M MAKEMASK(0x7, 9)
7373 #define GLQF_PROF2TC_OVERRIDE_ENA_3_S 12
7374 #define GLQF_PROF2TC_OVERRIDE_ENA_3_M BIT(12)
7375 #define GLQF_PROF2TC_REGION_3_S 13
7376 #define GLQF_PROF2TC_REGION_3_M MAKEMASK(0x7, 13)
7377 #define GLQF_PROF2TC_OVERRIDE_ENA_4_S 16
7378 #define GLQF_PROF2TC_OVERRIDE_ENA_4_M BIT(16)
7379 #define GLQF_PROF2TC_REGION_4_S 17
7380 #define GLQF_PROF2TC_REGION_4_M MAKEMASK(0x7, 17)
7381 #define GLQF_PROF2TC_OVERRIDE_ENA_5_S 20
7382 #define GLQF_PROF2TC_OVERRIDE_ENA_5_M BIT(20)
7383 #define GLQF_PROF2TC_REGION_5_S 21
7384 #define GLQF_PROF2TC_REGION_5_M MAKEMASK(0x7, 21)
7385 #define GLQF_PROF2TC_OVERRIDE_ENA_6_S 24
7386 #define GLQF_PROF2TC_OVERRIDE_ENA_6_M BIT(24)
7387 #define GLQF_PROF2TC_REGION_6_S 25
7388 #define GLQF_PROF2TC_REGION_6_M MAKEMASK(0x7, 25)
7389 #define GLQF_PROF2TC_OVERRIDE_ENA_7_S 28
7390 #define GLQF_PROF2TC_OVERRIDE_ENA_7_M BIT(28)
7391 #define GLQF_PROF2TC_REGION_7_S 29
7392 #define GLQF_PROF2TC_REGION_7_M MAKEMASK(0x7, 29)
7393 #define PFQF_FD_CNT 0x00460180 /* Reset Source: CORER */
7394 #define PFQF_FD_CNT_FD_GCNT_S 0
7395 #define PFQF_FD_CNT_FD_GCNT_M MAKEMASK(0x7FFF, 0)
7396 #define PFQF_FD_CNT_FD_BCNT_S 16
7397 #define PFQF_FD_CNT_FD_BCNT_M MAKEMASK(0x7FFF, 16)
7398 #define PFQF_FD_ENA 0x0043A000 /* Reset Source: CORER */
7399 #define PFQF_FD_ENA_FD_ENA_S 0
7400 #define PFQF_FD_ENA_FD_ENA_M BIT(0)
7401 #define PFQF_FD_SIZE 0x00460100 /* Reset Source: CORER */
7402 #define PFQF_FD_SIZE_FD_GSIZE_S 0
7403 #define PFQF_FD_SIZE_FD_GSIZE_M MAKEMASK(0x7FFF, 0)
7404 #define PFQF_FD_SIZE_FD_BSIZE_S 16
7405 #define PFQF_FD_SIZE_FD_BSIZE_M MAKEMASK(0x7FFF, 16)
7406 #define PFQF_FD_SUBTRACT 0x00460200 /* Reset Source: CORER */
7407 #define PFQF_FD_SUBTRACT_FD_GCNT_S 0
7408 #define PFQF_FD_SUBTRACT_FD_GCNT_M MAKEMASK(0x7FFF, 0)
7409 #define PFQF_FD_SUBTRACT_FD_BCNT_S 16
7410 #define PFQF_FD_SUBTRACT_FD_BCNT_M MAKEMASK(0x7FFF, 16)
7411 #define PFQF_HLUT(_i) (0x00430000 + ((_i) * 64)) /* _i=0...511 */ /* Reset Source: CORER */
7412 #define PFQF_HLUT_MAX_INDEX 511
7413 #define PFQF_HLUT_LUT0_S 0
7414 #define PFQF_HLUT_LUT0_M MAKEMASK(0xFF, 0)
7415 #define PFQF_HLUT_LUT1_S 8
7416 #define PFQF_HLUT_LUT1_M MAKEMASK(0xFF, 8)
7417 #define PFQF_HLUT_LUT2_S 16
7418 #define PFQF_HLUT_LUT2_M MAKEMASK(0xFF, 16)
7419 #define PFQF_HLUT_LUT3_S 24
7420 #define PFQF_HLUT_LUT3_M MAKEMASK(0xFF, 24)
7421 #define PFQF_HLUT_SIZE 0x00455480 /* Reset Source: CORER */
7422 #define PFQF_HLUT_SIZE_HSIZE_S 0
7423 #define PFQF_HLUT_SIZE_HSIZE_M MAKEMASK(0x3, 0)
7424 #define PFQF_PE_CLSN0 0x00470480 /* Reset Source: CORER */
7425 #define PFQF_PE_CLSN0_HITSBCNT_S 0
7426 #define PFQF_PE_CLSN0_HITSBCNT_M MAKEMASK(0xFFFFFFFF, 0)
7427 #define PFQF_PE_CLSN1 0x00470500 /* Reset Source: CORER */
7428 #define PFQF_PE_CLSN1_HITLBCNT_S 0
7429 #define PFQF_PE_CLSN1_HITLBCNT_M MAKEMASK(0xFFFFFFFF, 0)
7430 #define PFQF_PE_CTL1 0x00470000 /* Reset Source: CORER */
7431 #define PFQF_PE_CTL1_PEHSIZE_S 0
7432 #define PFQF_PE_CTL1_PEHSIZE_M MAKEMASK(0xF, 0)
7433 #define PFQF_PE_CTL2 0x00470040 /* Reset Source: CORER */
7434 #define PFQF_PE_CTL2_PEDSIZE_S 0
7435 #define PFQF_PE_CTL2_PEDSIZE_M MAKEMASK(0xF, 0)
7436 #define PFQF_PE_FILTERING_ENA 0x0043A080 /* Reset Source: CORER */
7437 #define PFQF_PE_FILTERING_ENA_PE_ENA_S 0
7438 #define PFQF_PE_FILTERING_ENA_PE_ENA_M BIT(0)
7439 #define PFQF_PE_FLHD 0x00470100 /* Reset Source: CORER */
7440 #define PFQF_PE_FLHD_FLHD_S 0
7441 #define PFQF_PE_FLHD_FLHD_M MAKEMASK(0xFFFFFF, 0)
7442 #define PFQF_PE_ST_CTL 0x00470400 /* Reset Source: CORER */
7443 #define PFQF_PE_ST_CTL_PF_CNT_EN_S 0
7444 #define PFQF_PE_ST_CTL_PF_CNT_EN_M BIT(0)
7445 #define PFQF_PE_ST_CTL_VFS_CNT_EN_S 1
7446 #define PFQF_PE_ST_CTL_VFS_CNT_EN_M BIT(1)
7447 #define PFQF_PE_ST_CTL_VF_CNT_EN_S 2
7448 #define PFQF_PE_ST_CTL_VF_CNT_EN_M BIT(2)
7449 #define PFQF_PE_ST_CTL_VF_NUM_S 16
7450 #define PFQF_PE_ST_CTL_VF_NUM_M MAKEMASK(0xFF, 16)
7451 #define PFQF_PE_TC_CTL 0x00452080 /* Reset Source: CORER */
7452 #define PFQF_PE_TC_CTL_TC_EN_PF_S 0
7453 #define PFQF_PE_TC_CTL_TC_EN_PF_M MAKEMASK(0xFF, 0)
7454 #define PFQF_PE_TC_CTL_TC_EN_VF_S 16
7455 #define PFQF_PE_TC_CTL_TC_EN_VF_M MAKEMASK(0xFF, 16)
7456 #define PFQF_PECNT_0 0x00470200 /* Reset Source: CORER */
7457 #define PFQF_PECNT_0_BUCKETCNT_S 0
7458 #define PFQF_PECNT_0_BUCKETCNT_M MAKEMASK(0x3FFFF, 0)
7459 #define PFQF_PECNT_1 0x00470300 /* Reset Source: CORER */
7460 #define PFQF_PECNT_1_FLTCNT_S 0
7461 #define PFQF_PECNT_1_FLTCNT_M MAKEMASK(0x3FFFF, 0)
7462 #define VPQF_PE_CTL1(_VF) (0x00474000 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: CORER */
7463 #define VPQF_PE_CTL1_MAX_INDEX 255
7464 #define VPQF_PE_CTL1_PEHSIZE_S 0
7465 #define VPQF_PE_CTL1_PEHSIZE_M MAKEMASK(0xF, 0)
7466 #define VPQF_PE_CTL2(_VF) (0x00474800 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: CORER */
7467 #define VPQF_PE_CTL2_MAX_INDEX 255
7468 #define VPQF_PE_CTL2_PEDSIZE_S 0
7469 #define VPQF_PE_CTL2_PEDSIZE_M MAKEMASK(0xF, 0)
7470 #define VPQF_PE_FILTERING_ENA(_VF) (0x00455800 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: CORER */
7471 #define VPQF_PE_FILTERING_ENA_MAX_INDEX 255
7472 #define VPQF_PE_FILTERING_ENA_PE_ENA_S 0
7473 #define VPQF_PE_FILTERING_ENA_PE_ENA_M BIT(0)
7474 #define VPQF_PE_FLHD(_VF) (0x00472000 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: CORER */
7475 #define VPQF_PE_FLHD_MAX_INDEX 255
7476 #define VPQF_PE_FLHD_FLHD_S 0
7477 #define VPQF_PE_FLHD_FLHD_M MAKEMASK(0xFFFFFF, 0)
7478 #define VPQF_PECNT_0(_VF) (0x00472800 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: CORER */
7479 #define VPQF_PECNT_0_MAX_INDEX 255
7480 #define VPQF_PECNT_0_BUCKETCNT_S 0
7481 #define VPQF_PECNT_0_BUCKETCNT_M MAKEMASK(0x3FFFF, 0)
7482 #define VPQF_PECNT_1(_VF) (0x00473000 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: CORER */
7483 #define VPQF_PECNT_1_MAX_INDEX 255
7484 #define VPQF_PECNT_1_FLTCNT_S 0
7485 #define VPQF_PECNT_1_FLTCNT_M MAKEMASK(0x3FFFF, 0)
7486 #define GLDCB_RMPMC 0x001223C8 /* Reset Source: CORER */
7487 #define GLDCB_RMPMC_RSPM_S 0
7488 #define GLDCB_RMPMC_RSPM_M MAKEMASK(0x3F, 0)
7489 #define GLDCB_RMPMC_MIQ_NODROP_MODE_S 6
7490 #define GLDCB_RMPMC_MIQ_NODROP_MODE_M MAKEMASK(0x1F, 6)
7491 #define GLDCB_RMPMC_RPM_DIS_S 31
7492 #define GLDCB_RMPMC_RPM_DIS_M BIT(31)
7493 #define GLDCB_RMPMS 0x001223CC /* Reset Source: CORER */
7494 #define GLDCB_RMPMS_RMPM_S 0
7495 #define GLDCB_RMPMS_RMPM_M MAKEMASK(0xFFFF, 0)
7496 #define GLDCB_RPCC 0x00122260 /* Reset Source: CORER */
7497 #define GLDCB_RPCC_EN_S 0
7498 #define GLDCB_RPCC_EN_M BIT(0)
7499 #define GLDCB_RPCC_SCL_FACT_S 4
7500 #define GLDCB_RPCC_SCL_FACT_M MAKEMASK(0x1F, 4)
7501 #define GLDCB_RPCC_THRSH_S 16
7502 #define GLDCB_RPCC_THRSH_M MAKEMASK(0xFFF, 16)
7503 #define GLDCB_RSPMC 0x001223C4 /* Reset Source: CORER */
7504 #define GLDCB_RSPMC_RSPM_S 0
7505 #define GLDCB_RSPMC_RSPM_M MAKEMASK(0xFF, 0)
7506 #define GLDCB_RSPMC_RPM_MODE_S 8
7507 #define GLDCB_RSPMC_RPM_MODE_M MAKEMASK(0x3, 8)
7508 #define GLDCB_RSPMC_PRR_MAX_EXP_S 10
7509 #define GLDCB_RSPMC_PRR_MAX_EXP_M MAKEMASK(0xF, 10)
7510 #define GLDCB_RSPMC_PFCTIMER_S 14
7511 #define GLDCB_RSPMC_PFCTIMER_M MAKEMASK(0x3FFF, 14)
7512 #define GLDCB_RSPMC_RPM_DIS_S 31
7513 #define GLDCB_RSPMC_RPM_DIS_M BIT(31)
7514 #define GLDCB_RSPMS 0x001223C0 /* Reset Source: CORER */
7515 #define GLDCB_RSPMS_RSPM_S 0
7516 #define GLDCB_RSPMS_RSPM_M MAKEMASK(0x3FFFF, 0)
7517 #define GLDCB_RTCTI 0x001223D0 /* Reset Source: CORER */
7518 #define GLDCB_RTCTI_PFCTIMEOUT_TC_S 0
7519 #define GLDCB_RTCTI_PFCTIMEOUT_TC_M MAKEMASK(0xFFFFFFFF, 0)
7520 #define GLDCB_RTCTQ(_i) (0x001222C0 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
7521 #define GLDCB_RTCTQ_MAX_INDEX 31
7522 #define GLDCB_RTCTQ_RXQNUM_S 0
7523 #define GLDCB_RTCTQ_RXQNUM_M MAKEMASK(0x7FF, 0)
7524 #define GLDCB_RTCTQ_IS_PF_Q_S 16
7525 #define GLDCB_RTCTQ_IS_PF_Q_M BIT(16)
7526 #define GLDCB_RTCTS(_i) (0x00122340 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
7527 #define GLDCB_RTCTS_MAX_INDEX 31
7528 #define GLDCB_RTCTS_PFCTIMER_S 0
7529 #define GLDCB_RTCTS_PFCTIMER_M MAKEMASK(0x3FFF, 0)
7530 #define GLRCB_CFG_COTF_CNT(_i) (0x001223D4 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
7531 #define GLRCB_CFG_COTF_CNT_MAX_INDEX 7
7532 #define GLRCB_CFG_COTF_CNT_MRKR_COTF_CNT_S 0
7533 #define GLRCB_CFG_COTF_CNT_MRKR_COTF_CNT_M MAKEMASK(0x3F, 0)
7534 #define GLRCB_CFG_COTF_ST 0x001223F4 /* Reset Source: CORER */
7535 #define GLRCB_CFG_COTF_ST_MRKR_COTF_ST_S 0
7536 #define GLRCB_CFG_COTF_ST_MRKR_COTF_ST_M MAKEMASK(0xFF, 0)
7537 #define GLRPRS_PMCFG_DHW(_i) (0x00200388 + ((_i) * 4)) /* _i=0...15 */ /* Reset Source: CORER */
7538 #define GLRPRS_PMCFG_DHW_MAX_INDEX 15
7539 #define GLRPRS_PMCFG_DHW_DHW_S 0
7540 #define GLRPRS_PMCFG_DHW_DHW_M MAKEMASK(0xFFFFF, 0)
7541 #define GLRPRS_PMCFG_DLW(_i) (0x002003C8 + ((_i) * 4)) /* _i=0...15 */ /* Reset Source: CORER */
7542 #define GLRPRS_PMCFG_DLW_MAX_INDEX 15
7543 #define GLRPRS_PMCFG_DLW_DLW_S 0
7544 #define GLRPRS_PMCFG_DLW_DLW_M MAKEMASK(0xFFFFF, 0)
7545 #define GLRPRS_PMCFG_DPS(_i) (0x00200308 + ((_i) * 4)) /* _i=0...15 */ /* Reset Source: CORER */
7546 #define GLRPRS_PMCFG_DPS_MAX_INDEX 15
7547 #define GLRPRS_PMCFG_DPS_DPS_S 0
7548 #define GLRPRS_PMCFG_DPS_DPS_M MAKEMASK(0xFFFFF, 0)
7549 #define GLRPRS_PMCFG_SHW(_i) (0x00200448 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
7550 #define GLRPRS_PMCFG_SHW_MAX_INDEX 7
7551 #define GLRPRS_PMCFG_SHW_SHW_S 0
7552 #define GLRPRS_PMCFG_SHW_SHW_M MAKEMASK(0xFFFFF, 0)
7553 #define GLRPRS_PMCFG_SLW(_i) (0x00200468 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
7554 #define GLRPRS_PMCFG_SLW_MAX_INDEX 7
7555 #define GLRPRS_PMCFG_SLW_SLW_S 0
7556 #define GLRPRS_PMCFG_SLW_SLW_M MAKEMASK(0xFFFFF, 0)
7557 #define GLRPRS_PMCFG_SPS(_i) (0x00200408 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
7558 #define GLRPRS_PMCFG_SPS_MAX_INDEX 7
7559 #define GLRPRS_PMCFG_SPS_SPS_S 0
7560 #define GLRPRS_PMCFG_SPS_SPS_M MAKEMASK(0xFFFFF, 0)
7561 #define GLRPRS_PMCFG_TC_CFG(_i) (0x00200488 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
7562 #define GLRPRS_PMCFG_TC_CFG_MAX_INDEX 31
7563 #define GLRPRS_PMCFG_TC_CFG_D_POOL_S 0
7564 #define GLRPRS_PMCFG_TC_CFG_D_POOL_M MAKEMASK(0xF, 0)
7565 #define GLRPRS_PMCFG_TC_CFG_S_POOL_S 16
7566 #define GLRPRS_PMCFG_TC_CFG_S_POOL_M MAKEMASK(0x7, 16)
7567 #define GLRPRS_PMCFG_TCHW(_i) (0x00200588 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
7568 #define GLRPRS_PMCFG_TCHW_MAX_INDEX 31
7569 #define GLRPRS_PMCFG_TCHW_TCHW_S 0
7570 #define GLRPRS_PMCFG_TCHW_TCHW_M MAKEMASK(0xFFFFF, 0)
7571 #define GLRPRS_PMCFG_TCLW(_i) (0x00200608 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
7572 #define GLRPRS_PMCFG_TCLW_MAX_INDEX 31
7573 #define GLRPRS_PMCFG_TCLW_TCLW_S 0
7574 #define GLRPRS_PMCFG_TCLW_TCLW_M MAKEMASK(0xFFFFF, 0)
7575 #define GLSWT_PMCFG_TC_CFG(_i) (0x00204900 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
7576 #define GLSWT_PMCFG_TC_CFG_MAX_INDEX 31
7577 #define GLSWT_PMCFG_TC_CFG_D_POOL_S 0
7578 #define GLSWT_PMCFG_TC_CFG_D_POOL_M MAKEMASK(0xF, 0)
7579 #define GLSWT_PMCFG_TC_CFG_S_POOL_S 16
7580 #define GLSWT_PMCFG_TC_CFG_S_POOL_M MAKEMASK(0x7, 16)
7581 #define PRTDCB_RLANPMS 0x00122280 /* Reset Source: CORER */
7582 #define PRTDCB_RLANPMS_LANRPPM_S 0
7583 #define PRTDCB_RLANPMS_LANRPPM_M MAKEMASK(0x3FFFF, 0)
7584 #define PRTDCB_RPPMC 0x00122240 /* Reset Source: CORER */
7585 #define PRTDCB_RPPMC_LANRPPM_S 0
7586 #define PRTDCB_RPPMC_LANRPPM_M MAKEMASK(0xFF, 0)
7587 #define PRTDCB_RPPMC_RDMARPPM_S 8
7588 #define PRTDCB_RPPMC_RDMARPPM_M MAKEMASK(0xFF, 8)
7589 #define PRTDCB_RRDMAPMS 0x00122120 /* Reset Source: CORER */
7590 #define PRTDCB_RRDMAPMS_RDMARPPM_S 0
7591 #define PRTDCB_RRDMAPMS_RDMARPPM_M MAKEMASK(0x3FFFF, 0)
7592 #define GL_STAT_SWR_BPCH(_i) (0x00347804 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
7593 #define GL_STAT_SWR_BPCH_MAX_INDEX 127
7594 #define GL_STAT_SWR_BPCH_VLBPCH_S 0
7595 #define GL_STAT_SWR_BPCH_VLBPCH_M MAKEMASK(0xFF, 0)
7596 #define GL_STAT_SWR_BPCL(_i) (0x00347800 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
7597 #define GL_STAT_SWR_BPCL_MAX_INDEX 127
7598 #define GL_STAT_SWR_BPCL_VLBPCL_S 0
7599 #define GL_STAT_SWR_BPCL_VLBPCL_M MAKEMASK(0xFFFFFFFF, 0)
7600 #define GL_STAT_SWR_GORCH(_i) (0x00342004 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
7601 #define GL_STAT_SWR_GORCH_MAX_INDEX 127
7602 #define GL_STAT_SWR_GORCH_VLBCH_S 0
7603 #define GL_STAT_SWR_GORCH_VLBCH_M MAKEMASK(0xFF, 0)
7604 #define GL_STAT_SWR_GORCL(_i) (0x00342000 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
7605 #define GL_STAT_SWR_GORCL_MAX_INDEX 127
7606 #define GL_STAT_SWR_GORCL_VLBCL_S 0
7607 #define GL_STAT_SWR_GORCL_VLBCL_M MAKEMASK(0xFFFFFFFF, 0)
7608 #define GL_STAT_SWR_GOTCH(_i) (0x00304004 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
7609 #define GL_STAT_SWR_GOTCH_MAX_INDEX 127
7610 #define GL_STAT_SWR_GOTCH_VLBCH_S 0
7611 #define GL_STAT_SWR_GOTCH_VLBCH_M MAKEMASK(0xFF, 0)
7612 #define GL_STAT_SWR_GOTCL(_i) (0x00304000 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
7613 #define GL_STAT_SWR_GOTCL_MAX_INDEX 127
7614 #define GL_STAT_SWR_GOTCL_VLBCL_S 0
7615 #define GL_STAT_SWR_GOTCL_VLBCL_M MAKEMASK(0xFFFFFFFF, 0)
7616 #define GL_STAT_SWR_MPCH(_i) (0x00347404 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
7617 #define GL_STAT_SWR_MPCH_MAX_INDEX 127
7618 #define GL_STAT_SWR_MPCH_VLMPCH_S 0
7619 #define GL_STAT_SWR_MPCH_VLMPCH_M MAKEMASK(0xFF, 0)
7620 #define GL_STAT_SWR_MPCL(_i) (0x00347400 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
7621 #define GL_STAT_SWR_MPCL_MAX_INDEX 127
7622 #define GL_STAT_SWR_MPCL_VLMPCL_S 0
7623 #define GL_STAT_SWR_MPCL_VLMPCL_M MAKEMASK(0xFFFFFFFF, 0)
7624 #define GL_STAT_SWR_UPCH(_i) (0x00347004 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
7625 #define GL_STAT_SWR_UPCH_MAX_INDEX 127
7626 #define GL_STAT_SWR_UPCH_VLUPCH_S 0
7627 #define GL_STAT_SWR_UPCH_VLUPCH_M MAKEMASK(0xFF, 0)
7628 #define GL_STAT_SWR_UPCL(_i) (0x00347000 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
7629 #define GL_STAT_SWR_UPCL_MAX_INDEX 127
7630 #define GL_STAT_SWR_UPCL_VLUPCL_S 0
7631 #define GL_STAT_SWR_UPCL_VLUPCL_M MAKEMASK(0xFFFFFFFF, 0)
7632 #define GLPRT_AORCL(_i) (0x003812C0 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7633 #define GLPRT_AORCL_MAX_INDEX 7
7634 #define GLPRT_AORCL_AORCL_S 0
7635 #define GLPRT_AORCL_AORCL_M MAKEMASK(0xFFFFFFFF, 0)
7636 #define GLPRT_BPRCH(_i) (0x00381384 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7637 #define GLPRT_BPRCH_MAX_INDEX 7
7638 #define GLPRT_BPRCH_UPRCH_S 0
7639 #define GLPRT_BPRCH_UPRCH_M MAKEMASK(0xFF, 0)
7640 #define GLPRT_BPRCL(_i) (0x00381380 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7641 #define GLPRT_BPRCL_MAX_INDEX 7
7642 #define GLPRT_BPRCL_UPRCH_S 0
7643 #define GLPRT_BPRCL_UPRCH_M MAKEMASK(0xFFFFFFFF, 0)
7644 #define GLPRT_BPTCH(_i) (0x00381244 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7645 #define GLPRT_BPTCH_MAX_INDEX 7
7646 #define GLPRT_BPTCH_UPRCH_S 0
7647 #define GLPRT_BPTCH_UPRCH_M MAKEMASK(0xFF, 0)
7648 #define GLPRT_BPTCL(_i) (0x00381240 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7649 #define GLPRT_BPTCL_MAX_INDEX 7
7650 #define GLPRT_BPTCL_UPRCH_S 0
7651 #define GLPRT_BPTCL_UPRCH_M MAKEMASK(0xFFFFFFFF, 0)
7652 #define GLPRT_CRCERRS(_i) (0x00380100 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7653 #define GLPRT_CRCERRS_MAX_INDEX 7
7654 #define GLPRT_CRCERRS_CRCERRS_S 0
7655 #define GLPRT_CRCERRS_CRCERRS_M MAKEMASK(0xFFFFFFFF, 0)
7656 #define GLPRT_CRCERRS_H(_i) (0x00380104 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7657 #define GLPRT_CRCERRS_H_MAX_INDEX 7
7658 #define GLPRT_CRCERRS_H_CRCERRS_S 0
7659 #define GLPRT_CRCERRS_H_CRCERRS_M MAKEMASK(0xFFFFFFFF, 0)
7660 #define GLPRT_GORCH(_i) (0x00380004 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7661 #define GLPRT_GORCH_MAX_INDEX 7
7662 #define GLPRT_GORCH_GORCH_S 0
7663 #define GLPRT_GORCH_GORCH_M MAKEMASK(0xFF, 0)
7664 #define GLPRT_GORCL(_i) (0x00380000 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7665 #define GLPRT_GORCL_MAX_INDEX 7
7666 #define GLPRT_GORCL_GORCL_S 0
7667 #define GLPRT_GORCL_GORCL_M MAKEMASK(0xFFFFFFFF, 0)
7668 #define GLPRT_GOTCH(_i) (0x00380B44 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7669 #define GLPRT_GOTCH_MAX_INDEX 7
7670 #define GLPRT_GOTCH_GOTCH_S 0
7671 #define GLPRT_GOTCH_GOTCH_M MAKEMASK(0xFF, 0)
7672 #define GLPRT_GOTCL(_i) (0x00380B40 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7673 #define GLPRT_GOTCL_MAX_INDEX 7
7674 #define GLPRT_GOTCL_GOTCL_S 0
7675 #define GLPRT_GOTCL_GOTCL_M MAKEMASK(0xFFFFFFFF, 0)
7676 #define GLPRT_ILLERRC(_i) (0x003801C0 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7677 #define GLPRT_ILLERRC_MAX_INDEX 7
7678 #define GLPRT_ILLERRC_ILLERRC_S 0
7679 #define GLPRT_ILLERRC_ILLERRC_M MAKEMASK(0xFFFFFFFF, 0)
7680 #define GLPRT_ILLERRC_H(_i) (0x003801C4 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7681 #define GLPRT_ILLERRC_H_MAX_INDEX 7
7682 #define GLPRT_ILLERRC_H_ILLERRC_S 0
7683 #define GLPRT_ILLERRC_H_ILLERRC_M MAKEMASK(0xFFFFFFFF, 0)
7684 #define GLPRT_LXOFFRXC(_i) (0x003802C0 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7685 #define GLPRT_LXOFFRXC_MAX_INDEX 7
7686 #define GLPRT_LXOFFRXC_LXOFFRXCNT_S 0
7687 #define GLPRT_LXOFFRXC_LXOFFRXCNT_M MAKEMASK(0xFFFFFFFF, 0)
7688 #define GLPRT_LXOFFRXC_H(_i) (0x003802C4 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7689 #define GLPRT_LXOFFRXC_H_MAX_INDEX 7
7690 #define GLPRT_LXOFFRXC_H_LXOFFRXCNT_S 0
7691 #define GLPRT_LXOFFRXC_H_LXOFFRXCNT_M MAKEMASK(0xFFFFFFFF, 0)
7692 #define GLPRT_LXOFFTXC(_i) (0x00381180 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7693 #define GLPRT_LXOFFTXC_MAX_INDEX 7
7694 #define GLPRT_LXOFFTXC_LXOFFTXC_S 0
7695 #define GLPRT_LXOFFTXC_LXOFFTXC_M MAKEMASK(0xFFFFFFFF, 0)
7696 #define GLPRT_LXOFFTXC_H(_i) (0x00381184 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7697 #define GLPRT_LXOFFTXC_H_MAX_INDEX 7
7698 #define GLPRT_LXOFFTXC_H_LXOFFTXC_S 0
7699 #define GLPRT_LXOFFTXC_H_LXOFFTXC_M MAKEMASK(0xFFFFFFFF, 0)
7700 #define GLPRT_LXONRXC(_i) (0x00380280 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7701 #define GLPRT_LXONRXC_MAX_INDEX 7
7702 #define GLPRT_LXONRXC_LXONRXCNT_S 0
7703 #define GLPRT_LXONRXC_LXONRXCNT_M MAKEMASK(0xFFFFFFFF, 0)
7704 #define GLPRT_LXONRXC_H(_i) (0x00380284 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7705 #define GLPRT_LXONRXC_H_MAX_INDEX 7
7706 #define GLPRT_LXONRXC_H_LXONRXCNT_S 0
7707 #define GLPRT_LXONRXC_H_LXONRXCNT_M MAKEMASK(0xFFFFFFFF, 0)
7708 #define GLPRT_LXONTXC(_i) (0x00381140 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7709 #define GLPRT_LXONTXC_MAX_INDEX 7
7710 #define GLPRT_LXONTXC_LXONTXC_S 0
7711 #define GLPRT_LXONTXC_LXONTXC_M MAKEMASK(0xFFFFFFFF, 0)
7712 #define GLPRT_LXONTXC_H(_i) (0x00381144 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7713 #define GLPRT_LXONTXC_H_MAX_INDEX 7
7714 #define GLPRT_LXONTXC_H_LXONTXC_S 0
7715 #define GLPRT_LXONTXC_H_LXONTXC_M MAKEMASK(0xFFFFFFFF, 0)
7716 #define GLPRT_MLFC(_i) (0x00380040 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7717 #define GLPRT_MLFC_MAX_INDEX 7
7718 #define GLPRT_MLFC_MLFC_S 0
7719 #define GLPRT_MLFC_MLFC_M MAKEMASK(0xFFFFFFFF, 0)
7720 #define GLPRT_MLFC_H(_i) (0x00380044 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7721 #define GLPRT_MLFC_H_MAX_INDEX 7
7722 #define GLPRT_MLFC_H_MLFC_S 0
7723 #define GLPRT_MLFC_H_MLFC_M MAKEMASK(0xFFFFFFFF, 0)
7724 #define GLPRT_MPRCH(_i) (0x00381344 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7725 #define GLPRT_MPRCH_MAX_INDEX 7
7726 #define GLPRT_MPRCH_MPRCH_S 0
7727 #define GLPRT_MPRCH_MPRCH_M MAKEMASK(0xFF, 0)
7728 #define GLPRT_MPRCL(_i) (0x00381340 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7729 #define GLPRT_MPRCL_MAX_INDEX 7
7730 #define GLPRT_MPRCL_MPRCL_S 0
7731 #define GLPRT_MPRCL_MPRCL_M MAKEMASK(0xFFFFFFFF, 0)
7732 #define GLPRT_MPTCH(_i) (0x00381204 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7733 #define GLPRT_MPTCH_MAX_INDEX 7
7734 #define GLPRT_MPTCH_MPTCH_S 0
7735 #define GLPRT_MPTCH_MPTCH_M MAKEMASK(0xFF, 0)
7736 #define GLPRT_MPTCL(_i) (0x00381200 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7737 #define GLPRT_MPTCL_MAX_INDEX 7
7738 #define GLPRT_MPTCL_MPTCL_S 0
7739 #define GLPRT_MPTCL_MPTCL_M MAKEMASK(0xFFFFFFFF, 0)
7740 #define GLPRT_MRFC(_i) (0x00380080 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7741 #define GLPRT_MRFC_MAX_INDEX 7
7742 #define GLPRT_MRFC_MRFC_S 0
7743 #define GLPRT_MRFC_MRFC_M MAKEMASK(0xFFFFFFFF, 0)
7744 #define GLPRT_MRFC_H(_i) (0x00380084 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7745 #define GLPRT_MRFC_H_MAX_INDEX 7
7746 #define GLPRT_MRFC_H_MRFC_S 0
7747 #define GLPRT_MRFC_H_MRFC_M MAKEMASK(0xFFFFFFFF, 0)
7748 #define GLPRT_PRC1023H(_i) (0x00380A04 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7749 #define GLPRT_PRC1023H_MAX_INDEX 7
7750 #define GLPRT_PRC1023H_PRC1023H_S 0
7751 #define GLPRT_PRC1023H_PRC1023H_M MAKEMASK(0xFF, 0)
7752 #define GLPRT_PRC1023L(_i) (0x00380A00 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7753 #define GLPRT_PRC1023L_MAX_INDEX 7
7754 #define GLPRT_PRC1023L_PRC1023L_S 0
7755 #define GLPRT_PRC1023L_PRC1023L_M MAKEMASK(0xFFFFFFFF, 0)
7756 #define GLPRT_PRC127H(_i) (0x00380944 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7757 #define GLPRT_PRC127H_MAX_INDEX 7
7758 #define GLPRT_PRC127H_PRC127H_S 0
7759 #define GLPRT_PRC127H_PRC127H_M MAKEMASK(0xFF, 0)
7760 #define GLPRT_PRC127L(_i) (0x00380940 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7761 #define GLPRT_PRC127L_MAX_INDEX 7
7762 #define GLPRT_PRC127L_PRC127L_S 0
7763 #define GLPRT_PRC127L_PRC127L_M MAKEMASK(0xFFFFFFFF, 0)
7764 #define GLPRT_PRC1522H(_i) (0x00380A44 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7765 #define GLPRT_PRC1522H_MAX_INDEX 7
7766 #define GLPRT_PRC1522H_PRC1522H_S 0
7767 #define GLPRT_PRC1522H_PRC1522H_M MAKEMASK(0xFF, 0)
7768 #define GLPRT_PRC1522L(_i) (0x00380A40 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7769 #define GLPRT_PRC1522L_MAX_INDEX 7
7770 #define GLPRT_PRC1522L_PRC1522L_S 0
7771 #define GLPRT_PRC1522L_PRC1522L_M MAKEMASK(0xFFFFFFFF, 0)
7772 #define GLPRT_PRC255H(_i) (0x00380984 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7773 #define GLPRT_PRC255H_MAX_INDEX 7
7774 #define GLPRT_PRC255H_PRTPRC255H_S 0
7775 #define GLPRT_PRC255H_PRTPRC255H_M MAKEMASK(0xFF, 0)
7776 #define GLPRT_PRC255L(_i) (0x00380980 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7777 #define GLPRT_PRC255L_MAX_INDEX 7
7778 #define GLPRT_PRC255L_PRC255L_S 0
7779 #define GLPRT_PRC255L_PRC255L_M MAKEMASK(0xFFFFFFFF, 0)
7780 #define GLPRT_PRC511H(_i) (0x003809C4 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7781 #define GLPRT_PRC511H_MAX_INDEX 7
7782 #define GLPRT_PRC511H_PRC511H_S 0
7783 #define GLPRT_PRC511H_PRC511H_M MAKEMASK(0xFF, 0)
7784 #define GLPRT_PRC511L(_i) (0x003809C0 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7785 #define GLPRT_PRC511L_MAX_INDEX 7
7786 #define GLPRT_PRC511L_PRC511L_S 0
7787 #define GLPRT_PRC511L_PRC511L_M MAKEMASK(0xFFFFFFFF, 0)
7788 #define GLPRT_PRC64H(_i) (0x00380904 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7789 #define GLPRT_PRC64H_MAX_INDEX 7
7790 #define GLPRT_PRC64H_PRC64H_S 0
7791 #define GLPRT_PRC64H_PRC64H_M MAKEMASK(0xFF, 0)
7792 #define GLPRT_PRC64L(_i) (0x00380900 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7793 #define GLPRT_PRC64L_MAX_INDEX 7
7794 #define GLPRT_PRC64L_PRC64L_S 0
7795 #define GLPRT_PRC64L_PRC64L_M MAKEMASK(0xFFFFFFFF, 0)
7796 #define GLPRT_PRC9522H(_i) (0x00380A84 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7797 #define GLPRT_PRC9522H_MAX_INDEX 7
7798 #define GLPRT_PRC9522H_PRC1522H_S 0
7799 #define GLPRT_PRC9522H_PRC1522H_M MAKEMASK(0xFF, 0)
7800 #define GLPRT_PRC9522L(_i) (0x00380A80 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7801 #define GLPRT_PRC9522L_MAX_INDEX 7
7802 #define GLPRT_PRC9522L_PRC1522L_S 0
7803 #define GLPRT_PRC9522L_PRC1522L_M MAKEMASK(0xFFFFFFFF, 0)
7804 #define GLPRT_PTC1023H(_i) (0x00380C84 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7805 #define GLPRT_PTC1023H_MAX_INDEX 7
7806 #define GLPRT_PTC1023H_PTC1023H_S 0
7807 #define GLPRT_PTC1023H_PTC1023H_M MAKEMASK(0xFF, 0)
7808 #define GLPRT_PTC1023L(_i) (0x00380C80 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7809 #define GLPRT_PTC1023L_MAX_INDEX 7
7810 #define GLPRT_PTC1023L_PTC1023L_S 0
7811 #define GLPRT_PTC1023L_PTC1023L_M MAKEMASK(0xFFFFFFFF, 0)
7812 #define GLPRT_PTC127H(_i) (0x00380BC4 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7813 #define GLPRT_PTC127H_MAX_INDEX 7
7814 #define GLPRT_PTC127H_PTC127H_S 0
7815 #define GLPRT_PTC127H_PTC127H_M MAKEMASK(0xFF, 0)
7816 #define GLPRT_PTC127L(_i) (0x00380BC0 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7817 #define GLPRT_PTC127L_MAX_INDEX 7
7818 #define GLPRT_PTC127L_PTC127L_S 0
7819 #define GLPRT_PTC127L_PTC127L_M MAKEMASK(0xFFFFFFFF, 0)
7820 #define GLPRT_PTC1522H(_i) (0x00380CC4 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7821 #define GLPRT_PTC1522H_MAX_INDEX 7
7822 #define GLPRT_PTC1522H_PTC1522H_S 0
7823 #define GLPRT_PTC1522H_PTC1522H_M MAKEMASK(0xFF, 0)
7824 #define GLPRT_PTC1522L(_i) (0x00380CC0 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7825 #define GLPRT_PTC1522L_MAX_INDEX 7
7826 #define GLPRT_PTC1522L_PTC1522L_S 0
7827 #define GLPRT_PTC1522L_PTC1522L_M MAKEMASK(0xFFFFFFFF, 0)
7828 #define GLPRT_PTC255H(_i) (0x00380C04 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7829 #define GLPRT_PTC255H_MAX_INDEX 7
7830 #define GLPRT_PTC255H_PTC255H_S 0
7831 #define GLPRT_PTC255H_PTC255H_M MAKEMASK(0xFF, 0)
7832 #define GLPRT_PTC255L(_i) (0x00380C00 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7833 #define GLPRT_PTC255L_MAX_INDEX 7
7834 #define GLPRT_PTC255L_PTC255L_S 0
7835 #define GLPRT_PTC255L_PTC255L_M MAKEMASK(0xFFFFFFFF, 0)
7836 #define GLPRT_PTC511H(_i) (0x00380C44 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7837 #define GLPRT_PTC511H_MAX_INDEX 7
7838 #define GLPRT_PTC511H_PTC511H_S 0
7839 #define GLPRT_PTC511H_PTC511H_M MAKEMASK(0xFF, 0)
7840 #define GLPRT_PTC511L(_i) (0x00380C40 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7841 #define GLPRT_PTC511L_MAX_INDEX 7
7842 #define GLPRT_PTC511L_PTC511L_S 0
7843 #define GLPRT_PTC511L_PTC511L_M MAKEMASK(0xFFFFFFFF, 0)
7844 #define GLPRT_PTC64H(_i) (0x00380B84 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7845 #define GLPRT_PTC64H_MAX_INDEX 7
7846 #define GLPRT_PTC64H_PTC64H_S 0
7847 #define GLPRT_PTC64H_PTC64H_M MAKEMASK(0xFF, 0)
7848 #define GLPRT_PTC64L(_i) (0x00380B80 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7849 #define GLPRT_PTC64L_MAX_INDEX 7
7850 #define GLPRT_PTC64L_PTC64L_S 0
7851 #define GLPRT_PTC64L_PTC64L_M MAKEMASK(0xFFFFFFFF, 0)
7852 #define GLPRT_PTC9522H(_i) (0x00380D04 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7853 #define GLPRT_PTC9522H_MAX_INDEX 7
7854 #define GLPRT_PTC9522H_PTC9522H_S 0
7855 #define GLPRT_PTC9522H_PTC9522H_M MAKEMASK(0xFF, 0)
7856 #define GLPRT_PTC9522L(_i) (0x00380D00 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7857 #define GLPRT_PTC9522L_MAX_INDEX 7
7858 #define GLPRT_PTC9522L_PTC9522L_S 0
7859 #define GLPRT_PTC9522L_PTC9522L_M MAKEMASK(0xFFFFFFFF, 0)
7860 #define GLPRT_PXOFFRXC(_i, _j) (0x00380500 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...7 */ /* Reset Source: CORER */
7861 #define GLPRT_PXOFFRXC_MAX_INDEX 7
7862 #define GLPRT_PXOFFRXC_PRPXOFFRXCNT_S 0
7863 #define GLPRT_PXOFFRXC_PRPXOFFRXCNT_M MAKEMASK(0xFFFFFFFF, 0)
7864 #define GLPRT_PXOFFRXC_H(_i, _j) (0x00380504 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...7 */ /* Reset Source: CORER */
7865 #define GLPRT_PXOFFRXC_H_MAX_INDEX 7
7866 #define GLPRT_PXOFFRXC_H_PRPXOFFRXCNT_S 0
7867 #define GLPRT_PXOFFRXC_H_PRPXOFFRXCNT_M MAKEMASK(0xFFFFFFFF, 0)
7868 #define GLPRT_PXOFFTXC(_i, _j) (0x00380F40 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...7 */ /* Reset Source: CORER */
7869 #define GLPRT_PXOFFTXC_MAX_INDEX 7
7870 #define GLPRT_PXOFFTXC_PRPXOFFTXCNT_S 0
7871 #define GLPRT_PXOFFTXC_PRPXOFFTXCNT_M MAKEMASK(0xFFFFFFFF, 0)
7872 #define GLPRT_PXOFFTXC_H(_i, _j) (0x00380F44 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...7 */ /* Reset Source: CORER */
7873 #define GLPRT_PXOFFTXC_H_MAX_INDEX 7
7874 #define GLPRT_PXOFFTXC_H_PRPXOFFTXCNT_S 0
7875 #define GLPRT_PXOFFTXC_H_PRPXOFFTXCNT_M MAKEMASK(0xFFFFFFFF, 0)
7876 #define GLPRT_PXONRXC(_i, _j) (0x00380300 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...7 */ /* Reset Source: CORER */
7877 #define GLPRT_PXONRXC_MAX_INDEX 7
7878 #define GLPRT_PXONRXC_PRPXONRXCNT_S 0
7879 #define GLPRT_PXONRXC_PRPXONRXCNT_M MAKEMASK(0xFFFFFFFF, 0)
7880 #define GLPRT_PXONRXC_H(_i, _j) (0x00380304 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...7 */ /* Reset Source: CORER */
7881 #define GLPRT_PXONRXC_H_MAX_INDEX 7
7882 #define GLPRT_PXONRXC_H_PRPXONRXCNT_S 0
7883 #define GLPRT_PXONRXC_H_PRPXONRXCNT_M MAKEMASK(0xFFFFFFFF, 0)
7884 #define GLPRT_PXONTXC(_i, _j) (0x00380D40 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...7 */ /* Reset Source: CORER */
7885 #define GLPRT_PXONTXC_MAX_INDEX 7
7886 #define GLPRT_PXONTXC_PRPXONTXC_S 0
7887 #define GLPRT_PXONTXC_PRPXONTXC_M MAKEMASK(0xFFFFFFFF, 0)
7888 #define GLPRT_PXONTXC_H(_i, _j) (0x00380D44 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...7 */ /* Reset Source: CORER */
7889 #define GLPRT_PXONTXC_H_MAX_INDEX 7
7890 #define GLPRT_PXONTXC_H_PRPXONTXC_S 0
7891 #define GLPRT_PXONTXC_H_PRPXONTXC_M MAKEMASK(0xFFFFFFFF, 0)
7892 #define GLPRT_RFC(_i) (0x00380AC0 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7893 #define GLPRT_RFC_MAX_INDEX 7
7894 #define GLPRT_RFC_RFC_S 0
7895 #define GLPRT_RFC_RFC_M MAKEMASK(0xFFFFFFFF, 0)
7896 #define GLPRT_RFC_H(_i) (0x00380AC4 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7897 #define GLPRT_RFC_H_MAX_INDEX 7
7898 #define GLPRT_RFC_H_RFC_S 0
7899 #define GLPRT_RFC_H_RFC_M MAKEMASK(0xFFFFFFFF, 0)
7900 #define GLPRT_RJC(_i) (0x00380B00 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7901 #define GLPRT_RJC_MAX_INDEX 7
7902 #define GLPRT_RJC_RJC_S 0
7903 #define GLPRT_RJC_RJC_M MAKEMASK(0xFFFFFFFF, 0)
7904 #define GLPRT_RJC_H(_i) (0x00380B04 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7905 #define GLPRT_RJC_H_MAX_INDEX 7
7906 #define GLPRT_RJC_H_RJC_S 0
7907 #define GLPRT_RJC_H_RJC_M MAKEMASK(0xFFFFFFFF, 0)
7908 #define GLPRT_RLEC(_i) (0x00380140 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7909 #define GLPRT_RLEC_MAX_INDEX 7
7910 #define GLPRT_RLEC_RLEC_S 0
7911 #define GLPRT_RLEC_RLEC_M MAKEMASK(0xFFFFFFFF, 0)
7912 #define GLPRT_RLEC_H(_i) (0x00380144 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7913 #define GLPRT_RLEC_H_MAX_INDEX 7
7914 #define GLPRT_RLEC_H_RLEC_S 0
7915 #define GLPRT_RLEC_H_RLEC_M MAKEMASK(0xFFFFFFFF, 0)
7916 #define GLPRT_ROC(_i) (0x00380240 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7917 #define GLPRT_ROC_MAX_INDEX 7
7918 #define GLPRT_ROC_ROC_S 0
7919 #define GLPRT_ROC_ROC_M MAKEMASK(0xFFFFFFFF, 0)
7920 #define GLPRT_ROC_H(_i) (0x00380244 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7921 #define GLPRT_ROC_H_MAX_INDEX 7
7922 #define GLPRT_ROC_H_ROC_S 0
7923 #define GLPRT_ROC_H_ROC_M MAKEMASK(0xFFFFFFFF, 0)
7924 #define GLPRT_RUC(_i) (0x00380200 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7925 #define GLPRT_RUC_MAX_INDEX 7
7926 #define GLPRT_RUC_RUC_S 0
7927 #define GLPRT_RUC_RUC_M MAKEMASK(0xFFFFFFFF, 0)
7928 #define GLPRT_RUC_H(_i) (0x00380204 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7929 #define GLPRT_RUC_H_MAX_INDEX 7
7930 #define GLPRT_RUC_H_RUC_S 0
7931 #define GLPRT_RUC_H_RUC_M MAKEMASK(0xFFFFFFFF, 0)
7932 #define GLPRT_RXON2OFFCNT(_i, _j) (0x00380700 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...7 */ /* Reset Source: CORER */
7933 #define GLPRT_RXON2OFFCNT_MAX_INDEX 7
7934 #define GLPRT_RXON2OFFCNT_PRRXON2OFFCNT_S 0
7935 #define GLPRT_RXON2OFFCNT_PRRXON2OFFCNT_M MAKEMASK(0xFFFFFFFF, 0)
7936 #define GLPRT_RXON2OFFCNT_H(_i, _j) (0x00380704 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...7 */ /* Reset Source: CORER */
7937 #define GLPRT_RXON2OFFCNT_H_MAX_INDEX 7
7938 #define GLPRT_RXON2OFFCNT_H_PRRXON2OFFCNT_S 0
7939 #define GLPRT_RXON2OFFCNT_H_PRRXON2OFFCNT_M MAKEMASK(0xFFFFFFFF, 0)
7940 #define GLPRT_STDC(_i) (0x00340000 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
7941 #define GLPRT_STDC_MAX_INDEX 7
7942 #define GLPRT_STDC_STDC_S 0
7943 #define GLPRT_STDC_STDC_M MAKEMASK(0xFFFFFFFF, 0)
7944 #define GLPRT_TDOLD(_i) (0x00381280 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7945 #define GLPRT_TDOLD_MAX_INDEX 7
7946 #define GLPRT_TDOLD_GLPRT_TDOLD_S 0
7947 #define GLPRT_TDOLD_GLPRT_TDOLD_M MAKEMASK(0xFFFFFFFF, 0)
7948 #define GLPRT_TDOLD_H(_i) (0x00381284 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7949 #define GLPRT_TDOLD_H_MAX_INDEX 7
7950 #define GLPRT_TDOLD_H_GLPRT_TDOLD_S 0
7951 #define GLPRT_TDOLD_H_GLPRT_TDOLD_M MAKEMASK(0xFFFFFFFF, 0)
7952 #define GLPRT_UPRCH(_i) (0x00381304 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7953 #define GLPRT_UPRCH_MAX_INDEX 7
7954 #define GLPRT_UPRCH_UPRCH_S 0
7955 #define GLPRT_UPRCH_UPRCH_M MAKEMASK(0xFF, 0)
7956 #define GLPRT_UPRCL(_i) (0x00381300 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7957 #define GLPRT_UPRCL_MAX_INDEX 7
7958 #define GLPRT_UPRCL_UPRCL_S 0
7959 #define GLPRT_UPRCL_UPRCL_M MAKEMASK(0xFFFFFFFF, 0)
7960 #define GLPRT_UPTCH(_i) (0x003811C4 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7961 #define GLPRT_UPTCH_MAX_INDEX 7
7962 #define GLPRT_UPTCH_UPTCH_S 0
7963 #define GLPRT_UPTCH_UPTCH_M MAKEMASK(0xFF, 0)
7964 #define GLPRT_UPTCL(_i) (0x003811C0 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7965 #define GLPRT_UPTCL_MAX_INDEX 7
7966 #define GLPRT_UPTCL_VUPTCH_S 0
7967 #define GLPRT_UPTCL_VUPTCH_M MAKEMASK(0xFFFFFFFF, 0)
7968 #define GLSTAT_ACL_CNT_0_H(_i) (0x00388004 + ((_i) * 8)) /* _i=0...511 */ /* Reset Source: CORER */
7969 #define GLSTAT_ACL_CNT_0_H_MAX_INDEX 511
7970 #define GLSTAT_ACL_CNT_0_H_CNT_MSB_S 0
7971 #define GLSTAT_ACL_CNT_0_H_CNT_MSB_M MAKEMASK(0xFF, 0)
7972 #define GLSTAT_ACL_CNT_0_L(_i) (0x00388000 + ((_i) * 8)) /* _i=0...511 */ /* Reset Source: CORER */
7973 #define GLSTAT_ACL_CNT_0_L_MAX_INDEX 511
7974 #define GLSTAT_ACL_CNT_0_L_CNT_LSB_S 0
7975 #define GLSTAT_ACL_CNT_0_L_CNT_LSB_M MAKEMASK(0xFFFFFFFF, 0)
7976 #define GLSTAT_ACL_CNT_1_H(_i) (0x00389004 + ((_i) * 8)) /* _i=0...511 */ /* Reset Source: CORER */
7977 #define GLSTAT_ACL_CNT_1_H_MAX_INDEX 511
7978 #define GLSTAT_ACL_CNT_1_H_CNT_MSB_S 0
7979 #define GLSTAT_ACL_CNT_1_H_CNT_MSB_M MAKEMASK(0xFF, 0)
7980 #define GLSTAT_ACL_CNT_1_L(_i) (0x00389000 + ((_i) * 8)) /* _i=0...511 */ /* Reset Source: CORER */
7981 #define GLSTAT_ACL_CNT_1_L_MAX_INDEX 511
7982 #define GLSTAT_ACL_CNT_1_L_CNT_LSB_S 0
7983 #define GLSTAT_ACL_CNT_1_L_CNT_LSB_M MAKEMASK(0xFFFFFFFF, 0)
7984 #define GLSTAT_ACL_CNT_2_H(_i) (0x0038A004 + ((_i) * 8)) /* _i=0...511 */ /* Reset Source: CORER */
7985 #define GLSTAT_ACL_CNT_2_H_MAX_INDEX 511
7986 #define GLSTAT_ACL_CNT_2_H_CNT_MSB_S 0
7987 #define GLSTAT_ACL_CNT_2_H_CNT_MSB_M MAKEMASK(0xFF, 0)
7988 #define GLSTAT_ACL_CNT_2_L(_i) (0x0038A000 + ((_i) * 8)) /* _i=0...511 */ /* Reset Source: CORER */
7989 #define GLSTAT_ACL_CNT_2_L_MAX_INDEX 511
7990 #define GLSTAT_ACL_CNT_2_L_CNT_LSB_S 0
7991 #define GLSTAT_ACL_CNT_2_L_CNT_LSB_M MAKEMASK(0xFFFFFFFF, 0)
7992 #define GLSTAT_ACL_CNT_3_H(_i) (0x0038B004 + ((_i) * 8)) /* _i=0...511 */ /* Reset Source: CORER */
7993 #define GLSTAT_ACL_CNT_3_H_MAX_INDEX 511
7994 #define GLSTAT_ACL_CNT_3_H_CNT_MSB_S 0
7995 #define GLSTAT_ACL_CNT_3_H_CNT_MSB_M MAKEMASK(0xFF, 0)
7996 #define GLSTAT_ACL_CNT_3_L(_i) (0x0038B000 + ((_i) * 8)) /* _i=0...511 */ /* Reset Source: CORER */
7997 #define GLSTAT_ACL_CNT_3_L_MAX_INDEX 511
7998 #define GLSTAT_ACL_CNT_3_L_CNT_LSB_S 0
7999 #define GLSTAT_ACL_CNT_3_L_CNT_LSB_M MAKEMASK(0xFFFFFFFF, 0)
8000 #define GLSTAT_FD_CNT0H(_i) (0x003A0004 + ((_i) * 8)) /* _i=0...4095 */ /* Reset Source: CORER */
8001 #define GLSTAT_FD_CNT0H_MAX_INDEX 4095
8002 #define GLSTAT_FD_CNT0H_FD0_CNT_H_S 0
8003 #define GLSTAT_FD_CNT0H_FD0_CNT_H_M MAKEMASK(0xFF, 0)
8004 #define GLSTAT_FD_CNT0L(_i) (0x003A0000 + ((_i) * 8)) /* _i=0...4095 */ /* Reset Source: CORER */
8005 #define GLSTAT_FD_CNT0L_MAX_INDEX 4095
8006 #define GLSTAT_FD_CNT0L_FD0_CNT_L_S 0
8007 #define GLSTAT_FD_CNT0L_FD0_CNT_L_M MAKEMASK(0xFFFFFFFF, 0)
8008 #define GLSTAT_FD_CNT1H(_i) (0x003A8004 + ((_i) * 8)) /* _i=0...4095 */ /* Reset Source: CORER */
8009 #define GLSTAT_FD_CNT1H_MAX_INDEX 4095
8010 #define GLSTAT_FD_CNT1H_FD0_CNT_H_S 0
8011 #define GLSTAT_FD_CNT1H_FD0_CNT_H_M MAKEMASK(0xFF, 0)
8012 #define GLSTAT_FD_CNT1L(_i) (0x003A8000 + ((_i) * 8)) /* _i=0...4095 */ /* Reset Source: CORER */
8013 #define GLSTAT_FD_CNT1L_MAX_INDEX 4095
8014 #define GLSTAT_FD_CNT1L_FD0_CNT_L_S 0
8015 #define GLSTAT_FD_CNT1L_FD0_CNT_L_M MAKEMASK(0xFFFFFFFF, 0)
8016 #define GLSW_BPRCH(_i) (0x00346204 + ((_i) * 8)) /* _i=0...31 */ /* Reset Source: CORER */
8017 #define GLSW_BPRCH_MAX_INDEX 31
8018 #define GLSW_BPRCH_BPRCH_S 0
8019 #define GLSW_BPRCH_BPRCH_M MAKEMASK(0xFF, 0)
8020 #define GLSW_BPRCL(_i) (0x00346200 + ((_i) * 8)) /* _i=0...31 */ /* Reset Source: CORER */
8021 #define GLSW_BPRCL_MAX_INDEX 31
8022 #define GLSW_BPRCL_BPRCL_S 0
8023 #define GLSW_BPRCL_BPRCL_M MAKEMASK(0xFFFFFFFF, 0)
8024 #define GLSW_BPTCH(_i) (0x00310204 + ((_i) * 8)) /* _i=0...31 */ /* Reset Source: CORER */
8025 #define GLSW_BPTCH_MAX_INDEX 31
8026 #define GLSW_BPTCH_BPTCH_S 0
8027 #define GLSW_BPTCH_BPTCH_M MAKEMASK(0xFF, 0)
8028 #define GLSW_BPTCL(_i) (0x00310200 + ((_i) * 8)) /* _i=0...31 */ /* Reset Source: CORER */
8029 #define GLSW_BPTCL_MAX_INDEX 31
8030 #define GLSW_BPTCL_BPTCL_S 0
8031 #define GLSW_BPTCL_BPTCL_M MAKEMASK(0xFFFFFFFF, 0)
8032 #define GLSW_GORCH(_i) (0x00341004 + ((_i) * 8)) /* _i=0...31 */ /* Reset Source: CORER */
8033 #define GLSW_GORCH_MAX_INDEX 31
8034 #define GLSW_GORCH_GORCH_S 0
8035 #define GLSW_GORCH_GORCH_M MAKEMASK(0xFF, 0)
8036 #define GLSW_GORCL(_i) (0x00341000 + ((_i) * 8)) /* _i=0...31 */ /* Reset Source: CORER */
8037 #define GLSW_GORCL_MAX_INDEX 31
8038 #define GLSW_GORCL_GORCL_S 0
8039 #define GLSW_GORCL_GORCL_M MAKEMASK(0xFFFFFFFF, 0)
8040 #define GLSW_GOTCH(_i) (0x00302004 + ((_i) * 8)) /* _i=0...31 */ /* Reset Source: CORER */
8041 #define GLSW_GOTCH_MAX_INDEX 31
8042 #define GLSW_GOTCH_GOTCH_S 0
8043 #define GLSW_GOTCH_GOTCH_M MAKEMASK(0xFF, 0)
8044 #define GLSW_GOTCL(_i) (0x00302000 + ((_i) * 8)) /* _i=0...31 */ /* Reset Source: CORER */
8045 #define GLSW_GOTCL_MAX_INDEX 31
8046 #define GLSW_GOTCL_GOTCL_S 0
8047 #define GLSW_GOTCL_GOTCL_M MAKEMASK(0xFFFFFFFF, 0)
8048 #define GLSW_MPRCH(_i) (0x00346104 + ((_i) * 8)) /* _i=0...31 */ /* Reset Source: CORER */
8049 #define GLSW_MPRCH_MAX_INDEX 31
8050 #define GLSW_MPRCH_MPRCH_S 0
8051 #define GLSW_MPRCH_MPRCH_M MAKEMASK(0xFF, 0)
8052 #define GLSW_MPRCL(_i) (0x00346100 + ((_i) * 8)) /* _i=0...31 */ /* Reset Source: CORER */
8053 #define GLSW_MPRCL_MAX_INDEX 31
8054 #define GLSW_MPRCL_MPRCL_S 0
8055 #define GLSW_MPRCL_MPRCL_M MAKEMASK(0xFFFFFFFF, 0)
8056 #define GLSW_MPTCH(_i) (0x00310104 + ((_i) * 8)) /* _i=0...31 */ /* Reset Source: CORER */
8057 #define GLSW_MPTCH_MAX_INDEX 31
8058 #define GLSW_MPTCH_MPTCH_S 0
8059 #define GLSW_MPTCH_MPTCH_M MAKEMASK(0xFF, 0)
8060 #define GLSW_MPTCL(_i) (0x00310100 + ((_i) * 8)) /* _i=0...31 */ /* Reset Source: CORER */
8061 #define GLSW_MPTCL_MAX_INDEX 31
8062 #define GLSW_MPTCL_MPTCL_S 0
8063 #define GLSW_MPTCL_MPTCL_M MAKEMASK(0xFFFFFFFF, 0)
8064 #define GLSW_UPRCH(_i) (0x00346004 + ((_i) * 8)) /* _i=0...31 */ /* Reset Source: CORER */
8065 #define GLSW_UPRCH_MAX_INDEX 31
8066 #define GLSW_UPRCH_UPRCH_S 0
8067 #define GLSW_UPRCH_UPRCH_M MAKEMASK(0xFF, 0)
8068 #define GLSW_UPRCL(_i) (0x00346000 + ((_i) * 8)) /* _i=0...31 */ /* Reset Source: CORER */
8069 #define GLSW_UPRCL_MAX_INDEX 31
8070 #define GLSW_UPRCL_UPRCL_S 0
8071 #define GLSW_UPRCL_UPRCL_M MAKEMASK(0xFFFFFFFF, 0)
8072 #define GLSW_UPTCH(_i) (0x00310004 + ((_i) * 8)) /* _i=0...31 */ /* Reset Source: CORER */
8073 #define GLSW_UPTCH_MAX_INDEX 31
8074 #define GLSW_UPTCH_UPTCH_S 0
8075 #define GLSW_UPTCH_UPTCH_M MAKEMASK(0xFF, 0)
8076 #define GLSW_UPTCL(_i) (0x00310000 + ((_i) * 8)) /* _i=0...31 */ /* Reset Source: CORER */
8077 #define GLSW_UPTCL_MAX_INDEX 31
8078 #define GLSW_UPTCL_UPTCL_S 0
8079 #define GLSW_UPTCL_UPTCL_M MAKEMASK(0xFFFFFFFF, 0)
8080 #define GLSWID_RUPP(_i) (0x00345000 + ((_i) * 4)) /* _i=0...255 */ /* Reset Source: CORER */
8081 #define GLSWID_RUPP_MAX_INDEX 255
8082 #define GLSWID_RUPP_RUPP_S 0
8083 #define GLSWID_RUPP_RUPP_M MAKEMASK(0xFFFFFFFF, 0)
8084 #define GLV_BPRCH(_i) (0x003B6004 + ((_i) * 8)) /* _i=0...767 */ /* Reset Source: CORER */
8085 #define GLV_BPRCH_MAX_INDEX 767
8086 #define GLV_BPRCH_BPRCH_S 0
8087 #define GLV_BPRCH_BPRCH_M MAKEMASK(0xFF, 0)
8088 #define GLV_BPRCL(_i) (0x003B6000 + ((_i) * 8)) /* _i=0...767 */ /* Reset Source: CORER */
8089 #define GLV_BPRCL_MAX_INDEX 767
8090 #define GLV_BPRCL_BPRCL_S 0
8091 #define GLV_BPRCL_BPRCL_M MAKEMASK(0xFFFFFFFF, 0)
8092 #define GLV_BPTCH(_i) (0x0030E004 + ((_i) * 8)) /* _i=0...767 */ /* Reset Source: CORER */
8093 #define GLV_BPTCH_MAX_INDEX 767
8094 #define GLV_BPTCH_BPTCH_S 0
8095 #define GLV_BPTCH_BPTCH_M MAKEMASK(0xFF, 0)
8096 #define GLV_BPTCL(_i) (0x0030E000 + ((_i) * 8)) /* _i=0...767 */ /* Reset Source: CORER */
8097 #define GLV_BPTCL_MAX_INDEX 767
8098 #define GLV_BPTCL_BPTCL_S 0
8099 #define GLV_BPTCL_BPTCL_M MAKEMASK(0xFFFFFFFF, 0)
8100 #define GLV_GORCH(_i) (0x003B0004 + ((_i) * 8)) /* _i=0...767 */ /* Reset Source: CORER */
8101 #define GLV_GORCH_MAX_INDEX 767
8102 #define GLV_GORCH_GORCH_S 0
8103 #define GLV_GORCH_GORCH_M MAKEMASK(0xFF, 0)
8104 #define GLV_GORCL(_i) (0x003B0000 + ((_i) * 8)) /* _i=0...767 */ /* Reset Source: CORER */
8105 #define GLV_GORCL_MAX_INDEX 767
8106 #define GLV_GORCL_GORCL_S 0
8107 #define GLV_GORCL_GORCL_M MAKEMASK(0xFFFFFFFF, 0)
8108 #define GLV_GOTCH(_i) (0x00300004 + ((_i) * 8)) /* _i=0...767 */ /* Reset Source: CORER */
8109 #define GLV_GOTCH_MAX_INDEX 767
8110 #define GLV_GOTCH_GOTCH_S 0
8111 #define GLV_GOTCH_GOTCH_M MAKEMASK(0xFF, 0)
8112 #define GLV_GOTCL(_i) (0x00300000 + ((_i) * 8)) /* _i=0...767 */ /* Reset Source: CORER */
8113 #define GLV_GOTCL_MAX_INDEX 767
8114 #define GLV_GOTCL_GOTCL_S 0
8115 #define GLV_GOTCL_GOTCL_M MAKEMASK(0xFFFFFFFF, 0)
8116 #define GLV_MPRCH(_i) (0x003B4004 + ((_i) * 8)) /* _i=0...767 */ /* Reset Source: CORER */
8117 #define GLV_MPRCH_MAX_INDEX 767
8118 #define GLV_MPRCH_MPRCH_S 0
8119 #define GLV_MPRCH_MPRCH_M MAKEMASK(0xFF, 0)
8120 #define GLV_MPRCL(_i) (0x003B4000 + ((_i) * 8)) /* _i=0...767 */ /* Reset Source: CORER */
8121 #define GLV_MPRCL_MAX_INDEX 767
8122 #define GLV_MPRCL_MPRCL_S 0
8123 #define GLV_MPRCL_MPRCL_M MAKEMASK(0xFFFFFFFF, 0)
8124 #define GLV_MPTCH(_i) (0x0030C004 + ((_i) * 8)) /* _i=0...767 */ /* Reset Source: CORER */
8125 #define GLV_MPTCH_MAX_INDEX 767
8126 #define GLV_MPTCH_MPTCH_S 0
8127 #define GLV_MPTCH_MPTCH_M MAKEMASK(0xFF, 0)
8128 #define GLV_MPTCL(_i) (0x0030C000 + ((_i) * 8)) /* _i=0...767 */ /* Reset Source: CORER */
8129 #define GLV_MPTCL_MAX_INDEX 767
8130 #define GLV_MPTCL_MPTCL_S 0
8131 #define GLV_MPTCL_MPTCL_M MAKEMASK(0xFFFFFFFF, 0)
8132 #define GLV_RDPC(_i) (0x00294C04 + ((_i) * 4)) /* _i=0...767 */ /* Reset Source: CORER */
8133 #define GLV_RDPC_MAX_INDEX 767
8134 #define GLV_RDPC_RDPC_S 0
8135 #define GLV_RDPC_RDPC_M MAKEMASK(0xFFFFFFFF, 0)
8136 #define GLV_REPC(_i) (0x00295804 + ((_i) * 4)) /* _i=0...767 */ /* Reset Source: CORER */
8137 #define GLV_REPC_MAX_INDEX 767
8138 #define GLV_REPC_NO_DESC_CNT_S 0
8139 #define GLV_REPC_NO_DESC_CNT_M MAKEMASK(0xFFFF, 0)
8140 #define GLV_REPC_ERROR_CNT_S 16
8141 #define GLV_REPC_ERROR_CNT_M MAKEMASK(0xFFFF, 16)
8142 #define GLV_TEPC(_VSI) (0x00312000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: CORER */
8143 #define GLV_TEPC_MAX_INDEX 767
8144 #define GLV_TEPC_TEPC_S 0
8145 #define GLV_TEPC_TEPC_M MAKEMASK(0xFFFFFFFF, 0)
8146 #define GLV_UPRCH(_i) (0x003B2004 + ((_i) * 8)) /* _i=0...767 */ /* Reset Source: CORER */
8147 #define GLV_UPRCH_MAX_INDEX 767
8148 #define GLV_UPRCH_UPRCH_S 0
8149 #define GLV_UPRCH_UPRCH_M MAKEMASK(0xFF, 0)
8150 #define GLV_UPRCL(_i) (0x003B2000 + ((_i) * 8)) /* _i=0...767 */ /* Reset Source: CORER */
8151 #define GLV_UPRCL_MAX_INDEX 767
8152 #define GLV_UPRCL_UPRCL_S 0
8153 #define GLV_UPRCL_UPRCL_M MAKEMASK(0xFFFFFFFF, 0)
8154 #define GLV_UPTCH(_i) (0x0030A004 + ((_i) * 8)) /* _i=0...767 */ /* Reset Source: CORER */
8155 #define GLV_UPTCH_MAX_INDEX 767
8156 #define GLV_UPTCH_GLVUPTCH_S 0
8157 #define GLV_UPTCH_GLVUPTCH_M MAKEMASK(0xFF, 0)
8158 #define GLV_UPTCL(_i) (0x0030A000 + ((_i) * 8)) /* _i=0...767 */ /* Reset Source: CORER */
8159 #define GLV_UPTCL_MAX_INDEX 767
8160 #define GLV_UPTCL_UPTCL_S 0
8161 #define GLV_UPTCL_UPTCL_M MAKEMASK(0xFFFFFFFF, 0)
8162 #define GLVEBUP_RBCH(_i, _j) (0x00343004 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...31 */ /* Reset Source: CORER */
8163 #define GLVEBUP_RBCH_MAX_INDEX 7
8164 #define GLVEBUP_RBCH_UPBCH_S 0
8165 #define GLVEBUP_RBCH_UPBCH_M MAKEMASK(0xFF, 0)
8166 #define GLVEBUP_RBCL(_i, _j) (0x00343000 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...31 */ /* Reset Source: CORER */
8167 #define GLVEBUP_RBCL_MAX_INDEX 7
8168 #define GLVEBUP_RBCL_UPBCL_S 0
8169 #define GLVEBUP_RBCL_UPBCL_M MAKEMASK(0xFFFFFFFF, 0)
8170 #define GLVEBUP_RPCH(_i, _j) (0x00344004 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...31 */ /* Reset Source: CORER */
8171 #define GLVEBUP_RPCH_MAX_INDEX 7
8172 #define GLVEBUP_RPCH_UPPCH_S 0
8173 #define GLVEBUP_RPCH_UPPCH_M MAKEMASK(0xFF, 0)
8174 #define GLVEBUP_RPCL(_i, _j) (0x00344000 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...31 */ /* Reset Source: CORER */
8175 #define GLVEBUP_RPCL_MAX_INDEX 7
8176 #define GLVEBUP_RPCL_UPPCL_S 0
8177 #define GLVEBUP_RPCL_UPPCL_M MAKEMASK(0xFFFFFFFF, 0)
8178 #define GLVEBUP_TBCH(_i, _j) (0x00306004 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...31 */ /* Reset Source: CORER */
8179 #define GLVEBUP_TBCH_MAX_INDEX 7
8180 #define GLVEBUP_TBCH_UPBCH_S 0
8181 #define GLVEBUP_TBCH_UPBCH_M MAKEMASK(0xFF, 0)
8182 #define GLVEBUP_TBCL(_i, _j) (0x00306000 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...31 */ /* Reset Source: CORER */
8183 #define GLVEBUP_TBCL_MAX_INDEX 7
8184 #define GLVEBUP_TBCL_UPBCL_S 0
8185 #define GLVEBUP_TBCL_UPBCL_M MAKEMASK(0xFFFFFFFF, 0)
8186 #define GLVEBUP_TPCH(_i, _j) (0x00308004 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...31 */ /* Reset Source: CORER */
8187 #define GLVEBUP_TPCH_MAX_INDEX 7
8188 #define GLVEBUP_TPCH_UPPCH_S 0
8189 #define GLVEBUP_TPCH_UPPCH_M MAKEMASK(0xFF, 0)
8190 #define GLVEBUP_TPCL(_i, _j) (0x00308000 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...31 */ /* Reset Source: CORER */
8191 #define GLVEBUP_TPCL_MAX_INDEX 7
8192 #define GLVEBUP_TPCL_UPPCL_S 0
8193 #define GLVEBUP_TPCL_UPPCL_M MAKEMASK(0xFFFFFFFF, 0)
8194 #define PRTRPB_LDPC 0x000AC280 /* Reset Source: CORER */
8195 #define PRTRPB_LDPC_CRCERRS_S 0
8196 #define PRTRPB_LDPC_CRCERRS_M MAKEMASK(0xFFFFFFFF, 0)
8197 #define PRTRPB_RDPC 0x000AC260 /* Reset Source: CORER */
8198 #define PRTRPB_RDPC_CRCERRS_S 0
8199 #define PRTRPB_RDPC_CRCERRS_M MAKEMASK(0xFFFFFFFF, 0)
8200 #define PRTTPB_STAT_TC_BYTES_SENTL(_i) (0x00098200 + ((_i) * 4)) /* _i=0...63 */ /* Reset Source: CORER */
8201 #define PRTTPB_STAT_TC_BYTES_SENTL_MAX_INDEX 63
8202 #define PRTTPB_STAT_TC_BYTES_SENTL_TCCNT_S 0
8203 #define PRTTPB_STAT_TC_BYTES_SENTL_TCCNT_M MAKEMASK(0xFFFFFFFF, 0)
8204 #define TPB_PRTTPB_STAT_PKT_SENT(_i) (0x00099470 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
8205 #define TPB_PRTTPB_STAT_PKT_SENT_MAX_INDEX 7
8206 #define TPB_PRTTPB_STAT_PKT_SENT_PKTCNT_S 0
8207 #define TPB_PRTTPB_STAT_PKT_SENT_PKTCNT_M MAKEMASK(0xFFFFFFFF, 0)
8208 #define TPB_PRTTPB_STAT_TC_BYTES_SENT(_i) (0x00099094 + ((_i) * 4)) /* _i=0...63 */ /* Reset Source: CORER */
8209 #define TPB_PRTTPB_STAT_TC_BYTES_SENT_MAX_INDEX 63
8210 #define TPB_PRTTPB_STAT_TC_BYTES_SENT_TCCNT_S 0
8211 #define TPB_PRTTPB_STAT_TC_BYTES_SENT_TCCNT_M MAKEMASK(0xFFFFFFFF, 0)
8212 #define EMP_SWT_PRUNIND 0x00204020 /* Reset Source: CORER */
8213 #define EMP_SWT_PRUNIND_OPCODE_S 0
8214 #define EMP_SWT_PRUNIND_OPCODE_M MAKEMASK(0xF, 0)
8215 #define EMP_SWT_PRUNIND_LIST_INDEX_NUM_S 4
8216 #define EMP_SWT_PRUNIND_LIST_INDEX_NUM_M MAKEMASK(0x3FF, 4)
8217 #define EMP_SWT_PRUNIND_VSI_NUM_S 16
8218 #define EMP_SWT_PRUNIND_VSI_NUM_M MAKEMASK(0x3FF, 16)
8219 #define EMP_SWT_PRUNIND_BIT_VALUE_S 31
8220 #define EMP_SWT_PRUNIND_BIT_VALUE_M BIT(31)
8221 #define EMP_SWT_REPIND 0x0020401C /* Reset Source: CORER */
8222 #define EMP_SWT_REPIND_OPCODE_S 0
8223 #define EMP_SWT_REPIND_OPCODE_M MAKEMASK(0xF, 0)
8224 #define EMP_SWT_REPIND_LIST_INDEX_NUMBER_S 4
8225 #define EMP_SWT_REPIND_LIST_INDEX_NUMBER_M MAKEMASK(0x3FF, 4)
8226 #define EMP_SWT_REPIND_VSI_NUM_S 16
8227 #define EMP_SWT_REPIND_VSI_NUM_M MAKEMASK(0x3FF, 16)
8228 #define EMP_SWT_REPIND_BIT_VALUE_S 31
8229 #define EMP_SWT_REPIND_BIT_VALUE_M BIT(31)
8230 #define GL_OVERRIDEC 0x002040A4 /* Reset Source: CORER */
8231 #define GL_OVERRIDEC_OVERRIDE_ATTEMPTC_S 0
8232 #define GL_OVERRIDEC_OVERRIDE_ATTEMPTC_M MAKEMASK(0xFFFF, 0)
8233 #define GL_OVERRIDEC_LAST_VSI_S 16
8234 #define GL_OVERRIDEC_LAST_VSI_M MAKEMASK(0x3FF, 16)
8235 #define GL_PLG_AVG_CALC_CFG 0x0020A5AC /* Reset Source: CORER */
8236 #define GL_PLG_AVG_CALC_CFG_CYCLE_LEN_S 0
8237 #define GL_PLG_AVG_CALC_CFG_CYCLE_LEN_M MAKEMASK(0x7FFFFFFF, 0)
8238 #define GL_PLG_AVG_CALC_CFG_MODE_S 31
8239 #define GL_PLG_AVG_CALC_CFG_MODE_M BIT(31)
8240 #define GL_PLG_AVG_CALC_ST 0x0020A5B0 /* Reset Source: CORER */
8241 #define GL_PLG_AVG_CALC_ST_IN_DATA_S 0
8242 #define GL_PLG_AVG_CALC_ST_IN_DATA_M MAKEMASK(0x7FFF, 0)
8243 #define GL_PLG_AVG_CALC_ST_OUT_DATA_S 16
8244 #define GL_PLG_AVG_CALC_ST_OUT_DATA_M MAKEMASK(0x7FFF, 16)
8245 #define GL_PLG_AVG_CALC_ST_VALID_S 31
8246 #define GL_PLG_AVG_CALC_ST_VALID_M BIT(31)
8247 #define GL_PRE_CFG_CMD 0x00214090 /* Reset Source: CORER */
8248 #define GL_PRE_CFG_CMD_ADDR_S 0
8249 #define GL_PRE_CFG_CMD_ADDR_M MAKEMASK(0x1FFF, 0)
8250 #define GL_PRE_CFG_CMD_TBLIDX_S 16
8251 #define GL_PRE_CFG_CMD_TBLIDX_M MAKEMASK(0x7, 16)
8252 #define GL_PRE_CFG_CMD_CMD_S 29
8253 #define GL_PRE_CFG_CMD_CMD_M BIT(29)
8254 #define GL_PRE_CFG_CMD_DONE_S 31
8255 #define GL_PRE_CFG_CMD_DONE_M BIT(31)
8256 #define GL_PRE_CFG_DATA(_i) (0x00214074 + ((_i) * 4)) /* _i=0...6 */ /* Reset Source: CORER */
8257 #define GL_PRE_CFG_DATA_MAX_INDEX 6
8258 #define GL_PRE_CFG_DATA_GL_PRE_RCP_DATA_S 0
8259 #define GL_PRE_CFG_DATA_GL_PRE_RCP_DATA_M MAKEMASK(0xFFFFFFFF, 0)
8260 #define GL_SWT_FUNCFILT 0x001D2698 /* Reset Source: CORER */
8261 #define GL_SWT_FUNCFILT_FUNCFILT_S 0
8262 #define GL_SWT_FUNCFILT_FUNCFILT_M BIT(0)
8263 #define GL_SWT_FW_STS(_i) (0x00216000 + ((_i) * 4)) /* _i=0...5 */ /* Reset Source: CORER */
8264 #define GL_SWT_FW_STS_MAX_INDEX 5
8265 #define GL_SWT_FW_STS_GL_SWT_FW_STS_S 0
8266 #define GL_SWT_FW_STS_GL_SWT_FW_STS_M MAKEMASK(0xFFFFFFFF, 0)
8267 #define GL_SWT_LAT_DOUBLE 0x00204004 /* Reset Source: CORER */
8268 #define GL_SWT_LAT_DOUBLE_BASE_S 0
8269 #define GL_SWT_LAT_DOUBLE_BASE_M MAKEMASK(0x7FF, 0)
8270 #define GL_SWT_LAT_DOUBLE_SIZE_S 16
8271 #define GL_SWT_LAT_DOUBLE_SIZE_M MAKEMASK(0x7FF, 16)
8272 #define GL_SWT_LAT_QUAD 0x00204008 /* Reset Source: CORER */
8273 #define GL_SWT_LAT_QUAD_BASE_S 0
8274 #define GL_SWT_LAT_QUAD_BASE_M MAKEMASK(0x7FF, 0)
8275 #define GL_SWT_LAT_QUAD_SIZE_S 16
8276 #define GL_SWT_LAT_QUAD_SIZE_M MAKEMASK(0x7FF, 16)
8277 #define GL_SWT_LAT_SINGLE 0x00204000 /* Reset Source: CORER */
8278 #define GL_SWT_LAT_SINGLE_BASE_S 0
8279 #define GL_SWT_LAT_SINGLE_BASE_M MAKEMASK(0x7FF, 0)
8280 #define GL_SWT_LAT_SINGLE_SIZE_S 16
8281 #define GL_SWT_LAT_SINGLE_SIZE_M MAKEMASK(0x7FF, 16)
8282 #define GL_SWT_MD_PRI 0x002040AC /* Reset Source: CORER */
8283 #define GL_SWT_MD_PRI_VSI_PRI_S 0
8284 #define GL_SWT_MD_PRI_VSI_PRI_M MAKEMASK(0x7, 0)
8285 #define GL_SWT_MD_PRI_LB_PRI_S 4
8286 #define GL_SWT_MD_PRI_LB_PRI_M MAKEMASK(0x7, 4)
8287 #define GL_SWT_MD_PRI_LAN_EN_PRI_S 8
8288 #define GL_SWT_MD_PRI_LAN_EN_PRI_M MAKEMASK(0x7, 8)
8289 #define GL_SWT_MD_PRI_QH_PRI_S 12
8290 #define GL_SWT_MD_PRI_QH_PRI_M MAKEMASK(0x7, 12)
8291 #define GL_SWT_MD_PRI_QL_PRI_S 16
8292 #define GL_SWT_MD_PRI_QL_PRI_M MAKEMASK(0x7, 16)
8293 #define GL_SWT_MIRTARVSI(_i) (0x00204500 + ((_i) * 4)) /* _i=0...63 */ /* Reset Source: CORER */
8294 #define GL_SWT_MIRTARVSI_MAX_INDEX 63
8295 #define GL_SWT_MIRTARVSI_VFVMNUMBER_S 0
8296 #define GL_SWT_MIRTARVSI_VFVMNUMBER_M MAKEMASK(0x3FF, 0)
8297 #define GL_SWT_MIRTARVSI_FUNCTIONTYPE_S 10
8298 #define GL_SWT_MIRTARVSI_FUNCTIONTYPE_M MAKEMASK(0x3, 10)
8299 #define GL_SWT_MIRTARVSI_PFNUMBER_S 12
8300 #define GL_SWT_MIRTARVSI_PFNUMBER_M MAKEMASK(0x7, 12)
8301 #define GL_SWT_MIRTARVSI_TARGETVSI_S 20
8302 #define GL_SWT_MIRTARVSI_TARGETVSI_M MAKEMASK(0x3FF, 20)
8303 #define GL_SWT_MIRTARVSI_RULEENABLE_S 31
8304 #define GL_SWT_MIRTARVSI_RULEENABLE_M BIT(31)
8305 #define GL_SWT_SWIDFVIDX 0x00214114 /* Reset Source: CORER */
8306 #define GL_SWT_SWIDFVIDX_SWIDFVIDX_S 0
8307 #define GL_SWT_SWIDFVIDX_SWIDFVIDX_M MAKEMASK(0x3F, 0)
8308 #define GL_SWT_SWIDFVIDX_PORT_TYPE_S 31
8309 #define GL_SWT_SWIDFVIDX_PORT_TYPE_M BIT(31)
8310 #define GL_VP_SWITCHID(_i) (0x00214094 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
8311 #define GL_VP_SWITCHID_MAX_INDEX 31
8312 #define GL_VP_SWITCHID_SWITCHID_S 0
8313 #define GL_VP_SWITCHID_SWITCHID_M MAKEMASK(0xFF, 0)
8314 #define GLSWID_STAT_BLOCK(_i) (0x0020A1A4 + ((_i) * 4)) /* _i=0...255 */ /* Reset Source: PFR */
8315 #define GLSWID_STAT_BLOCK_MAX_INDEX 255
8316 #define GLSWID_STAT_BLOCK_VEBID_S 0
8317 #define GLSWID_STAT_BLOCK_VEBID_M MAKEMASK(0x1F, 0)
8318 #define GLSWID_STAT_BLOCK_VEBID_VALID_S 31
8319 #define GLSWID_STAT_BLOCK_VEBID_VALID_M BIT(31)
8320 #define GLSWT_ACT_RESP_0 0x0020A5A4 /* Reset Source: CORER */
8321 #define GLSWT_ACT_RESP_0_GLSWT_ACT_RESP_S 0
8322 #define GLSWT_ACT_RESP_0_GLSWT_ACT_RESP_M MAKEMASK(0xFFFFFFFF, 0)
8323 #define GLSWT_ACT_RESP_1 0x0020A5A8 /* Reset Source: CORER */
8324 #define GLSWT_ACT_RESP_1_GLSWT_ACT_RESP_S 0
8325 #define GLSWT_ACT_RESP_1_GLSWT_ACT_RESP_M MAKEMASK(0xFFFFFFFF, 0)
8326 #define GLSWT_ARB_MODE 0x0020A674 /* Reset Source: CORER */
8327 #define GLSWT_ARB_MODE_FLU_PRI_SHM_S 0
8328 #define GLSWT_ARB_MODE_FLU_PRI_SHM_M BIT(0)
8329 #define GLSWT_ARB_MODE_TX_RX_FWD_PRI_S 1
8330 #define GLSWT_ARB_MODE_TX_RX_FWD_PRI_M BIT(1)
8331 #define PRT_SBPVSI 0x00204120 /* Reset Source: CORER */
8332 #define PRT_SBPVSI_BAD_FRAMES_VSI_S 0
8333 #define PRT_SBPVSI_BAD_FRAMES_VSI_M MAKEMASK(0x3FF, 0)
8334 #define PRT_SBPVSI_SBP_S 31
8335 #define PRT_SBPVSI_SBP_M BIT(31)
8336 #define PRT_SCSTS 0x00204140 /* Reset Source: CORER */
8337 #define PRT_SCSTS_BSCA_S 0
8338 #define PRT_SCSTS_BSCA_M BIT(0)
8339 #define PRT_SCSTS_BSCAP_S 1
8340 #define PRT_SCSTS_BSCAP_M BIT(1)
8341 #define PRT_SCSTS_MSCA_S 2
8342 #define PRT_SCSTS_MSCA_M BIT(2)
8343 #define PRT_SCSTS_MSCAP_S 3
8344 #define PRT_SCSTS_MSCAP_M BIT(3)
8345 #define PRT_SWT_BSCCNT 0x00204160 /* Reset Source: CORER */
8346 #define PRT_SWT_BSCCNT_CCOUNT_S 0
8347 #define PRT_SWT_BSCCNT_CCOUNT_M MAKEMASK(0x1FFFFFF, 0)
8348 #define PRT_SWT_BSCTRH 0x00204180 /* Reset Source: CORER */
8349 #define PRT_SWT_BSCTRH_UTRESH_S 0
8350 #define PRT_SWT_BSCTRH_UTRESH_M MAKEMASK(0x7FFFF, 0)
8351 #define PRT_SWT_MIREG 0x002042A0 /* Reset Source: CORER */
8352 #define PRT_SWT_MIREG_MIRRULE_S 0
8353 #define PRT_SWT_MIREG_MIRRULE_M MAKEMASK(0x3F, 0)
8354 #define PRT_SWT_MIREG_MIRENA_S 7
8355 #define PRT_SWT_MIREG_MIRENA_M BIT(7)
8356 #define PRT_SWT_MIRIG 0x00204280 /* Reset Source: CORER */
8357 #define PRT_SWT_MIRIG_MIRRULE_S 0
8358 #define PRT_SWT_MIRIG_MIRRULE_M MAKEMASK(0x3F, 0)
8359 #define PRT_SWT_MIRIG_MIRENA_S 7
8360 #define PRT_SWT_MIRIG_MIRENA_M BIT(7)
8361 #define PRT_SWT_MSCCNT 0x00204100 /* Reset Source: CORER */
8362 #define PRT_SWT_MSCCNT_CCOUNT_S 0
8363 #define PRT_SWT_MSCCNT_CCOUNT_M MAKEMASK(0x1FFFFFF, 0)
8364 #define PRT_SWT_MSCTRH 0x002041C0 /* Reset Source: CORER */
8365 #define PRT_SWT_MSCTRH_UTRESH_S 0
8366 #define PRT_SWT_MSCTRH_UTRESH_M MAKEMASK(0x7FFFF, 0)
8367 #define PRT_SWT_SCBI 0x002041E0 /* Reset Source: CORER */
8368 #define PRT_SWT_SCBI_BI_S 0
8369 #define PRT_SWT_SCBI_BI_M MAKEMASK(0x1FFFFFF, 0)
8370 #define PRT_SWT_SCCRL 0x00204200 /* Reset Source: CORER */
8371 #define PRT_SWT_SCCRL_MDIPW_S 0
8372 #define PRT_SWT_SCCRL_MDIPW_M BIT(0)
8373 #define PRT_SWT_SCCRL_MDICW_S 1
8374 #define PRT_SWT_SCCRL_MDICW_M BIT(1)
8375 #define PRT_SWT_SCCRL_BDIPW_S 2
8376 #define PRT_SWT_SCCRL_BDIPW_M BIT(2)
8377 #define PRT_SWT_SCCRL_BDICW_S 3
8378 #define PRT_SWT_SCCRL_BDICW_M BIT(3)
8379 #define PRT_SWT_SCCRL_INTERVAL_S 8
8380 #define PRT_SWT_SCCRL_INTERVAL_M MAKEMASK(0xFFFFF, 8)
8381 #define PRT_TCTUPR(_i) (0x00040840 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
8382 #define PRT_TCTUPR_MAX_INDEX 31
8383 #define PRT_TCTUPR_UP0_S 0
8384 #define PRT_TCTUPR_UP0_M MAKEMASK(0x7, 0)
8385 #define PRT_TCTUPR_UP1_S 4
8386 #define PRT_TCTUPR_UP1_M MAKEMASK(0x7, 4)
8387 #define PRT_TCTUPR_UP2_S 8
8388 #define PRT_TCTUPR_UP2_M MAKEMASK(0x7, 8)
8389 #define PRT_TCTUPR_UP3_S 12
8390 #define PRT_TCTUPR_UP3_M MAKEMASK(0x7, 12)
8391 #define PRT_TCTUPR_UP4_S 16
8392 #define PRT_TCTUPR_UP4_M MAKEMASK(0x7, 16)
8393 #define PRT_TCTUPR_UP5_S 20
8394 #define PRT_TCTUPR_UP5_M MAKEMASK(0x7, 20)
8395 #define PRT_TCTUPR_UP6_S 24
8396 #define PRT_TCTUPR_UP6_M MAKEMASK(0x7, 24)
8397 #define PRT_TCTUPR_UP7_S 28
8398 #define PRT_TCTUPR_UP7_M MAKEMASK(0x7, 28)
8399 #define GLHH_ART_CTL 0x000A41D4 /* Reset Source: POR */
8400 #define GLHH_ART_CTL_ACTIVE_S 0
8401 #define GLHH_ART_CTL_ACTIVE_M BIT(0)
8402 #define GLHH_ART_CTL_TIME_OUT1_S 1
8403 #define GLHH_ART_CTL_TIME_OUT1_M BIT(1)
8404 #define GLHH_ART_CTL_TIME_OUT2_S 2
8405 #define GLHH_ART_CTL_TIME_OUT2_M BIT(2)
8406 #define GLHH_ART_CTL_RESET_HH_S 31
8407 #define GLHH_ART_CTL_RESET_HH_M BIT(31)
8408 #define GLHH_ART_DATA 0x000A41E0 /* Reset Source: POR */
8409 #define GLHH_ART_DATA_AGENT_TYPE_S 0
8410 #define GLHH_ART_DATA_AGENT_TYPE_M MAKEMASK(0x7, 0)
8411 #define GLHH_ART_DATA_SYNC_TYPE_S 3
8412 #define GLHH_ART_DATA_SYNC_TYPE_M BIT(3)
8413 #define GLHH_ART_DATA_MAX_DELAY_S 4
8414 #define GLHH_ART_DATA_MAX_DELAY_M MAKEMASK(0xF, 4)
8415 #define GLHH_ART_DATA_TIME_BASE_S 8
8416 #define GLHH_ART_DATA_TIME_BASE_M MAKEMASK(0xF, 8)
8417 #define GLHH_ART_DATA_RSV_DATA_S 12
8418 #define GLHH_ART_DATA_RSV_DATA_M MAKEMASK(0xFFFFF, 12)
8419 #define GLHH_ART_TIME_H 0x000A41D8 /* Reset Source: POR */
8420 #define GLHH_ART_TIME_H_ART_TIME_H_S 0
8421 #define GLHH_ART_TIME_H_ART_TIME_H_M MAKEMASK(0xFFFFFFFF, 0)
8422 #define GLHH_ART_TIME_L 0x000A41DC /* Reset Source: POR */
8423 #define GLHH_ART_TIME_L_ART_TIME_L_S 0
8424 #define GLHH_ART_TIME_L_ART_TIME_L_M MAKEMASK(0xFFFFFFFF, 0)
8425 #define GLTSYN_AUX_IN_0(_i) (0x000889D8 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */
8426 #define GLTSYN_AUX_IN_0_MAX_INDEX 1
8427 #define GLTSYN_AUX_IN_0_EVNTLVL_S 0
8428 #define GLTSYN_AUX_IN_0_EVNTLVL_M MAKEMASK(0x3, 0)
8429 #define GLTSYN_AUX_IN_0_INT_ENA_S 4
8430 #define GLTSYN_AUX_IN_0_INT_ENA_M BIT(4)
8431 #define GLTSYN_AUX_IN_1(_i) (0x000889E0 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */
8432 #define GLTSYN_AUX_IN_1_MAX_INDEX 1
8433 #define GLTSYN_AUX_IN_1_EVNTLVL_S 0
8434 #define GLTSYN_AUX_IN_1_EVNTLVL_M MAKEMASK(0x3, 0)
8435 #define GLTSYN_AUX_IN_1_INT_ENA_S 4
8436 #define GLTSYN_AUX_IN_1_INT_ENA_M BIT(4)
8437 #define GLTSYN_AUX_IN_2(_i) (0x000889E8 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */
8438 #define GLTSYN_AUX_IN_2_MAX_INDEX 1
8439 #define GLTSYN_AUX_IN_2_EVNTLVL_S 0
8440 #define GLTSYN_AUX_IN_2_EVNTLVL_M MAKEMASK(0x3, 0)
8441 #define GLTSYN_AUX_IN_2_INT_ENA_S 4
8442 #define GLTSYN_AUX_IN_2_INT_ENA_M BIT(4)
8443 #define GLTSYN_AUX_OUT_0(_i) (0x00088998 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */
8444 #define GLTSYN_AUX_OUT_0_MAX_INDEX 1
8445 #define GLTSYN_AUX_OUT_0_OUT_ENA_S 0
8446 #define GLTSYN_AUX_OUT_0_OUT_ENA_M BIT(0)
8447 #define GLTSYN_AUX_OUT_0_OUTMOD_S 1
8448 #define GLTSYN_AUX_OUT_0_OUTMOD_M MAKEMASK(0x3, 1)
8449 #define GLTSYN_AUX_OUT_0_OUTLVL_S 3
8450 #define GLTSYN_AUX_OUT_0_OUTLVL_M BIT(3)
8451 #define GLTSYN_AUX_OUT_0_INT_ENA_S 4
8452 #define GLTSYN_AUX_OUT_0_INT_ENA_M BIT(4)
8453 #define GLTSYN_AUX_OUT_0_PULSEW_S 8
8454 #define GLTSYN_AUX_OUT_0_PULSEW_M MAKEMASK(0xF, 8)
8455 #define GLTSYN_AUX_OUT_1(_i) (0x000889A0 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */
8456 #define GLTSYN_AUX_OUT_1_MAX_INDEX 1
8457 #define GLTSYN_AUX_OUT_1_OUT_ENA_S 0
8458 #define GLTSYN_AUX_OUT_1_OUT_ENA_M BIT(0)
8459 #define GLTSYN_AUX_OUT_1_OUTMOD_S 1
8460 #define GLTSYN_AUX_OUT_1_OUTMOD_M MAKEMASK(0x3, 1)
8461 #define GLTSYN_AUX_OUT_1_OUTLVL_S 3
8462 #define GLTSYN_AUX_OUT_1_OUTLVL_M BIT(3)
8463 #define GLTSYN_AUX_OUT_1_INT_ENA_S 4
8464 #define GLTSYN_AUX_OUT_1_INT_ENA_M BIT(4)
8465 #define GLTSYN_AUX_OUT_1_PULSEW_S 8
8466 #define GLTSYN_AUX_OUT_1_PULSEW_M MAKEMASK(0xF, 8)
8467 #define GLTSYN_AUX_OUT_2(_i) (0x000889A8 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */
8468 #define GLTSYN_AUX_OUT_2_MAX_INDEX 1
8469 #define GLTSYN_AUX_OUT_2_OUT_ENA_S 0
8470 #define GLTSYN_AUX_OUT_2_OUT_ENA_M BIT(0)
8471 #define GLTSYN_AUX_OUT_2_OUTMOD_S 1
8472 #define GLTSYN_AUX_OUT_2_OUTMOD_M MAKEMASK(0x3, 1)
8473 #define GLTSYN_AUX_OUT_2_OUTLVL_S 3
8474 #define GLTSYN_AUX_OUT_2_OUTLVL_M BIT(3)
8475 #define GLTSYN_AUX_OUT_2_INT_ENA_S 4
8476 #define GLTSYN_AUX_OUT_2_INT_ENA_M BIT(4)
8477 #define GLTSYN_AUX_OUT_2_PULSEW_S 8
8478 #define GLTSYN_AUX_OUT_2_PULSEW_M MAKEMASK(0xF, 8)
8479 #define GLTSYN_AUX_OUT_3(_i) (0x000889B0 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */
8480 #define GLTSYN_AUX_OUT_3_MAX_INDEX 1
8481 #define GLTSYN_AUX_OUT_3_OUT_ENA_S 0
8482 #define GLTSYN_AUX_OUT_3_OUT_ENA_M BIT(0)
8483 #define GLTSYN_AUX_OUT_3_OUTMOD_S 1
8484 #define GLTSYN_AUX_OUT_3_OUTMOD_M MAKEMASK(0x3, 1)
8485 #define GLTSYN_AUX_OUT_3_OUTLVL_S 3
8486 #define GLTSYN_AUX_OUT_3_OUTLVL_M BIT(3)
8487 #define GLTSYN_AUX_OUT_3_INT_ENA_S 4
8488 #define GLTSYN_AUX_OUT_3_INT_ENA_M BIT(4)
8489 #define GLTSYN_AUX_OUT_3_PULSEW_S 8
8490 #define GLTSYN_AUX_OUT_3_PULSEW_M MAKEMASK(0xF, 8)
8491 #define GLTSYN_CLKO_0(_i) (0x000889B8 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */
8492 #define GLTSYN_CLKO_0_MAX_INDEX 1
8493 #define GLTSYN_CLKO_0_TSYNCLKO_S 0
8494 #define GLTSYN_CLKO_0_TSYNCLKO_M MAKEMASK(0xFFFFFFFF, 0)
8495 #define GLTSYN_CLKO_1(_i) (0x000889C0 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */
8496 #define GLTSYN_CLKO_1_MAX_INDEX 1
8497 #define GLTSYN_CLKO_1_TSYNCLKO_S 0
8498 #define GLTSYN_CLKO_1_TSYNCLKO_M MAKEMASK(0xFFFFFFFF, 0)
8499 #define GLTSYN_CLKO_2(_i) (0x000889C8 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */
8500 #define GLTSYN_CLKO_2_MAX_INDEX 1
8501 #define GLTSYN_CLKO_2_TSYNCLKO_S 0
8502 #define GLTSYN_CLKO_2_TSYNCLKO_M MAKEMASK(0xFFFFFFFF, 0)
8503 #define GLTSYN_CLKO_3(_i) (0x000889D0 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */
8504 #define GLTSYN_CLKO_3_MAX_INDEX 1
8505 #define GLTSYN_CLKO_3_TSYNCLKO_S 0
8506 #define GLTSYN_CLKO_3_TSYNCLKO_M MAKEMASK(0xFFFFFFFF, 0)
8507 #define GLTSYN_CMD 0x00088810 /* Reset Source: CORER */
8508 #define GLTSYN_CMD_CMD_S 0
8509 #define GLTSYN_CMD_CMD_M MAKEMASK(0xFF, 0)
8510 #define GLTSYN_CMD_SEL_MASTER_S 8
8511 #define GLTSYN_CMD_SEL_MASTER_M BIT(8)
8512 #define GLTSYN_CMD_SYNC 0x00088814 /* Reset Source: CORER */
8513 #define GLTSYN_CMD_SYNC_SYNC_S 0
8514 #define GLTSYN_CMD_SYNC_SYNC_M MAKEMASK(0x3, 0)
8515 #define GLTSYN_ENA(_i) (0x00088808 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */
8516 #define GLTSYN_ENA_MAX_INDEX 1
8517 #define GLTSYN_ENA_TSYN_ENA_S 0
8518 #define GLTSYN_ENA_TSYN_ENA_M BIT(0)
8519 #define GLTSYN_EVNT_H_0(_i) (0x00088970 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */
8520 #define GLTSYN_EVNT_H_0_MAX_INDEX 1
8521 #define GLTSYN_EVNT_H_0_TSYNEVNT_H_S 0
8522 #define GLTSYN_EVNT_H_0_TSYNEVNT_H_M MAKEMASK(0xFFFFFFFF, 0)
8523 #define GLTSYN_EVNT_H_1(_i) (0x00088980 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */
8524 #define GLTSYN_EVNT_H_1_MAX_INDEX 1
8525 #define GLTSYN_EVNT_H_1_TSYNEVNT_H_S 0
8526 #define GLTSYN_EVNT_H_1_TSYNEVNT_H_M MAKEMASK(0xFFFFFFFF, 0)
8527 #define GLTSYN_EVNT_H_2(_i) (0x00088990 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */
8528 #define GLTSYN_EVNT_H_2_MAX_INDEX 1
8529 #define GLTSYN_EVNT_H_2_TSYNEVNT_H_S 0
8530 #define GLTSYN_EVNT_H_2_TSYNEVNT_H_M MAKEMASK(0xFFFFFFFF, 0)
8531 #define GLTSYN_EVNT_L_0(_i) (0x00088968 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */
8532 #define GLTSYN_EVNT_L_0_MAX_INDEX 1
8533 #define GLTSYN_EVNT_L_0_TSYNEVNT_L_S 0
8534 #define GLTSYN_EVNT_L_0_TSYNEVNT_L_M MAKEMASK(0xFFFFFFFF, 0)
8535 #define GLTSYN_EVNT_L_1(_i) (0x00088978 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */
8536 #define GLTSYN_EVNT_L_1_MAX_INDEX 1
8537 #define GLTSYN_EVNT_L_1_TSYNEVNT_L_S 0
8538 #define GLTSYN_EVNT_L_1_TSYNEVNT_L_M MAKEMASK(0xFFFFFFFF, 0)
8539 #define GLTSYN_EVNT_L_2(_i) (0x00088988 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */
8540 #define GLTSYN_EVNT_L_2_MAX_INDEX 1
8541 #define GLTSYN_EVNT_L_2_TSYNEVNT_L_S 0
8542 #define GLTSYN_EVNT_L_2_TSYNEVNT_L_M MAKEMASK(0xFFFFFFFF, 0)
8543 #define GLTSYN_HHTIME_H(_i) (0x00088900 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */
8544 #define GLTSYN_HHTIME_H_MAX_INDEX 1
8545 #define GLTSYN_HHTIME_H_TSYNEVNT_H_S 0
8546 #define GLTSYN_HHTIME_H_TSYNEVNT_H_M MAKEMASK(0xFFFFFFFF, 0)
8547 #define GLTSYN_HHTIME_L(_i) (0x000888F8 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */
8548 #define GLTSYN_HHTIME_L_MAX_INDEX 1
8549 #define GLTSYN_HHTIME_L_TSYNEVNT_L_S 0
8550 #define GLTSYN_HHTIME_L_TSYNEVNT_L_M MAKEMASK(0xFFFFFFFF, 0)
8551 #define GLTSYN_INCVAL_H(_i) (0x00088920 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */
8552 #define GLTSYN_INCVAL_H_MAX_INDEX 1
8553 #define GLTSYN_INCVAL_H_INCVAL_H_S 0
8554 #define GLTSYN_INCVAL_H_INCVAL_H_M MAKEMASK(0xFF, 0)
8555 #define GLTSYN_INCVAL_L(_i) (0x00088918 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */
8556 #define GLTSYN_INCVAL_L_MAX_INDEX 1
8557 #define GLTSYN_INCVAL_L_INCVAL_L_S 0
8558 #define GLTSYN_INCVAL_L_INCVAL_L_M MAKEMASK(0xFFFFFFFF, 0)
8559 #define GLTSYN_SHADJ_H(_i) (0x00088910 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */
8560 #define GLTSYN_SHADJ_H_MAX_INDEX 1
8561 #define GLTSYN_SHADJ_H_ADJUST_H_S 0
8562 #define GLTSYN_SHADJ_H_ADJUST_H_M MAKEMASK(0xFFFFFFFF, 0)
8563 #define GLTSYN_SHADJ_L(_i) (0x00088908 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */
8564 #define GLTSYN_SHADJ_L_MAX_INDEX 1
8565 #define GLTSYN_SHADJ_L_ADJUST_L_S 0
8566 #define GLTSYN_SHADJ_L_ADJUST_L_M MAKEMASK(0xFFFFFFFF, 0)
8567 #define GLTSYN_SHTIME_0(_i) (0x000888E0 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */
8568 #define GLTSYN_SHTIME_0_MAX_INDEX 1
8569 #define GLTSYN_SHTIME_0_TSYNTIME_0_S 0
8570 #define GLTSYN_SHTIME_0_TSYNTIME_0_M MAKEMASK(0xFFFFFFFF, 0)
8571 #define GLTSYN_SHTIME_H(_i) (0x000888F0 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */
8572 #define GLTSYN_SHTIME_H_MAX_INDEX 1
8573 #define GLTSYN_SHTIME_H_TSYNTIME_H_S 0
8574 #define GLTSYN_SHTIME_H_TSYNTIME_H_M MAKEMASK(0xFFFFFFFF, 0)
8575 #define GLTSYN_SHTIME_L(_i) (0x000888E8 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */
8576 #define GLTSYN_SHTIME_L_MAX_INDEX 1
8577 #define GLTSYN_SHTIME_L_TSYNTIME_L_S 0
8578 #define GLTSYN_SHTIME_L_TSYNTIME_L_M MAKEMASK(0xFFFFFFFF, 0)
8579 #define GLTSYN_STAT(_i) (0x000888C0 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */
8580 #define GLTSYN_STAT_MAX_INDEX 1
8581 #define GLTSYN_STAT_EVENT0_S 0
8582 #define GLTSYN_STAT_EVENT0_M BIT(0)
8583 #define GLTSYN_STAT_EVENT1_S 1
8584 #define GLTSYN_STAT_EVENT1_M BIT(1)
8585 #define GLTSYN_STAT_EVENT2_S 2
8586 #define GLTSYN_STAT_EVENT2_M BIT(2)
8587 #define GLTSYN_STAT_TGT0_S 4
8588 #define GLTSYN_STAT_TGT0_M BIT(4)
8589 #define GLTSYN_STAT_TGT1_S 5
8590 #define GLTSYN_STAT_TGT1_M BIT(5)
8591 #define GLTSYN_STAT_TGT2_S 6
8592 #define GLTSYN_STAT_TGT2_M BIT(6)
8593 #define GLTSYN_STAT_TGT3_S 7
8594 #define GLTSYN_STAT_TGT3_M BIT(7)
8595 #define GLTSYN_SYNC_DLAY 0x00088818 /* Reset Source: CORER */
8596 #define GLTSYN_SYNC_DLAY_SYNC_DELAY_S 0
8597 #define GLTSYN_SYNC_DLAY_SYNC_DELAY_M MAKEMASK(0x1F, 0)
8598 #define GLTSYN_TGT_H_0(_i) (0x00088930 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */
8599 #define GLTSYN_TGT_H_0_MAX_INDEX 1
8600 #define GLTSYN_TGT_H_0_TSYNTGTT_H_S 0
8601 #define GLTSYN_TGT_H_0_TSYNTGTT_H_M MAKEMASK(0xFFFFFFFF, 0)
8602 #define GLTSYN_TGT_H_1(_i) (0x00088940 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */
8603 #define GLTSYN_TGT_H_1_MAX_INDEX 1
8604 #define GLTSYN_TGT_H_1_TSYNTGTT_H_S 0
8605 #define GLTSYN_TGT_H_1_TSYNTGTT_H_M MAKEMASK(0xFFFFFFFF, 0)
8606 #define GLTSYN_TGT_H_2(_i) (0x00088950 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */
8607 #define GLTSYN_TGT_H_2_MAX_INDEX 1
8608 #define GLTSYN_TGT_H_2_TSYNTGTT_H_S 0
8609 #define GLTSYN_TGT_H_2_TSYNTGTT_H_M MAKEMASK(0xFFFFFFFF, 0)
8610 #define GLTSYN_TGT_H_3(_i) (0x00088960 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */
8611 #define GLTSYN_TGT_H_3_MAX_INDEX 1
8612 #define GLTSYN_TGT_H_3_TSYNTGTT_H_S 0
8613 #define GLTSYN_TGT_H_3_TSYNTGTT_H_M MAKEMASK(0xFFFFFFFF, 0)
8614 #define GLTSYN_TGT_L_0(_i) (0x00088928 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */
8615 #define GLTSYN_TGT_L_0_MAX_INDEX 1
8616 #define GLTSYN_TGT_L_0_TSYNTGTT_L_S 0
8617 #define GLTSYN_TGT_L_0_TSYNTGTT_L_M MAKEMASK(0xFFFFFFFF, 0)
8618 #define GLTSYN_TGT_L_1(_i) (0x00088938 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */
8619 #define GLTSYN_TGT_L_1_MAX_INDEX 1
8620 #define GLTSYN_TGT_L_1_TSYNTGTT_L_S 0
8621 #define GLTSYN_TGT_L_1_TSYNTGTT_L_M MAKEMASK(0xFFFFFFFF, 0)
8622 #define GLTSYN_TGT_L_2(_i) (0x00088948 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */
8623 #define GLTSYN_TGT_L_2_MAX_INDEX 1
8624 #define GLTSYN_TGT_L_2_TSYNTGTT_L_S 0
8625 #define GLTSYN_TGT_L_2_TSYNTGTT_L_M MAKEMASK(0xFFFFFFFF, 0)
8626 #define GLTSYN_TGT_L_3(_i) (0x00088958 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */
8627 #define GLTSYN_TGT_L_3_MAX_INDEX 1
8628 #define GLTSYN_TGT_L_3_TSYNTGTT_L_S 0
8629 #define GLTSYN_TGT_L_3_TSYNTGTT_L_M MAKEMASK(0xFFFFFFFF, 0)
8630 #define GLTSYN_TIME_0(_i) (0x000888C8 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */
8631 #define GLTSYN_TIME_0_MAX_INDEX 1
8632 #define GLTSYN_TIME_0_TSYNTIME_0_S 0
8633 #define GLTSYN_TIME_0_TSYNTIME_0_M MAKEMASK(0xFFFFFFFF, 0)
8634 #define GLTSYN_TIME_H(_i) (0x000888D8 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */
8635 #define GLTSYN_TIME_H_MAX_INDEX 1
8636 #define GLTSYN_TIME_H_TSYNTIME_H_S 0
8637 #define GLTSYN_TIME_H_TSYNTIME_H_M MAKEMASK(0xFFFFFFFF, 0)
8638 #define GLTSYN_TIME_L(_i) (0x000888D0 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */
8639 #define GLTSYN_TIME_L_MAX_INDEX 1
8640 #define GLTSYN_TIME_L_TSYNTIME_L_S 0
8641 #define GLTSYN_TIME_L_TSYNTIME_L_M MAKEMASK(0xFFFFFFFF, 0)
8642 #define PFHH_SEM 0x000A4200 /* Reset Source: PFR */
8643 #define PFHH_SEM_BUSY_S 0
8644 #define PFHH_SEM_BUSY_M BIT(0)
8645 #define PFHH_SEM_PF_OWNER_S 4
8646 #define PFHH_SEM_PF_OWNER_M MAKEMASK(0x7, 4)
8647 #define PFTSYN_SEM 0x00088880 /* Reset Source: PFR */
8648 #define PFTSYN_SEM_BUSY_S 0
8649 #define PFTSYN_SEM_BUSY_M BIT(0)
8650 #define PFTSYN_SEM_PF_OWNER_S 4
8651 #define PFTSYN_SEM_PF_OWNER_M MAKEMASK(0x7, 4)
8652 #define GLPE_TSCD_FLR(_i) (0x0051E24C + ((_i) * 4)) /* _i=0...3 */ /* Reset Source: CORER */
8653 #define GLPE_TSCD_FLR_MAX_INDEX 3
8654 #define GLPE_TSCD_FLR_DRAIN_VCTR_ID_S 0
8655 #define GLPE_TSCD_FLR_DRAIN_VCTR_ID_M MAKEMASK(0x3, 0)
8656 #define GLPE_TSCD_FLR_PORT_S 2
8657 #define GLPE_TSCD_FLR_PORT_M MAKEMASK(0x7, 2)
8658 #define GLPE_TSCD_FLR_PF_NUM_S 5
8659 #define GLPE_TSCD_FLR_PF_NUM_M MAKEMASK(0x7, 5)
8660 #define GLPE_TSCD_FLR_VM_VF_TYPE_S 8
8661 #define GLPE_TSCD_FLR_VM_VF_TYPE_M MAKEMASK(0x3, 8)
8662 #define GLPE_TSCD_FLR_VM_VF_NUM_S 16
8663 #define GLPE_TSCD_FLR_VM_VF_NUM_M MAKEMASK(0x3FF, 16)
8664 #define GLPE_TSCD_FLR_VLD_S 31
8665 #define GLPE_TSCD_FLR_VLD_M BIT(31)
8666 #define GLPE_TSCD_PEPM 0x0051E228 /* Reset Source: CORER */
8667 #define GLPE_TSCD_PEPM_MDQ_CREDITS_S 0
8668 #define GLPE_TSCD_PEPM_MDQ_CREDITS_M MAKEMASK(0xFF, 0)
8669 #define PF_VIRT_VSTATUS 0x0009E680 /* Reset Source: PFR */
8670 #define PF_VIRT_VSTATUS_NUM_VFS_S 0
8671 #define PF_VIRT_VSTATUS_NUM_VFS_M MAKEMASK(0xFF, 0)
8672 #define PF_VIRT_VSTATUS_TOTAL_VFS_S 8
8673 #define PF_VIRT_VSTATUS_TOTAL_VFS_M MAKEMASK(0xFF, 8)
8674 #define PF_VIRT_VSTATUS_IOV_ACTIVE_S 16
8675 #define PF_VIRT_VSTATUS_IOV_ACTIVE_M BIT(16)
8676 #define PF_VT_PFALLOC 0x001D2480 /* Reset Source: CORER */
8677 #define PF_VT_PFALLOC_FIRSTVF_S 0
8678 #define PF_VT_PFALLOC_FIRSTVF_M MAKEMASK(0xFF, 0)
8679 #define PF_VT_PFALLOC_LASTVF_S 8
8680 #define PF_VT_PFALLOC_LASTVF_M MAKEMASK(0xFF, 8)
8681 #define PF_VT_PFALLOC_VALID_S 31
8682 #define PF_VT_PFALLOC_VALID_M BIT(31)
8683 #define PF_VT_PFALLOC_HIF 0x0009DD80 /* Reset Source: PCIR */
8684 #define PF_VT_PFALLOC_HIF_FIRSTVF_S 0
8685 #define PF_VT_PFALLOC_HIF_FIRSTVF_M MAKEMASK(0xFF, 0)
8686 #define PF_VT_PFALLOC_HIF_LASTVF_S 8
8687 #define PF_VT_PFALLOC_HIF_LASTVF_M MAKEMASK(0xFF, 8)
8688 #define PF_VT_PFALLOC_HIF_VALID_S 31
8689 #define PF_VT_PFALLOC_HIF_VALID_M BIT(31)
8690 #define PF_VT_PFALLOC_PCIE 0x000BE080 /* Reset Source: PCIR */
8691 #define PF_VT_PFALLOC_PCIE_FIRSTVF_S 0
8692 #define PF_VT_PFALLOC_PCIE_FIRSTVF_M MAKEMASK(0xFF, 0)
8693 #define PF_VT_PFALLOC_PCIE_LASTVF_S 8
8694 #define PF_VT_PFALLOC_PCIE_LASTVF_M MAKEMASK(0xFF, 8)
8695 #define PF_VT_PFALLOC_PCIE_VALID_S 31
8696 #define PF_VT_PFALLOC_PCIE_VALID_M BIT(31)
8697 #define VSI_L2TAGSTXVALID(_VSI) (0x00046000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: CORER */
8698 #define VSI_L2TAGSTXVALID_MAX_INDEX 767
8699 #define VSI_L2TAGSTXVALID_L2TAG1INSERTID_S 0
8700 #define VSI_L2TAGSTXVALID_L2TAG1INSERTID_M MAKEMASK(0x7, 0)
8701 #define VSI_L2TAGSTXVALID_L2TAG1INSERTID_VALID_S 3
8702 #define VSI_L2TAGSTXVALID_L2TAG1INSERTID_VALID_M BIT(3)
8703 #define VSI_L2TAGSTXVALID_L2TAG2INSERTID_S 4
8704 #define VSI_L2TAGSTXVALID_L2TAG2INSERTID_M MAKEMASK(0x7, 4)
8705 #define VSI_L2TAGSTXVALID_L2TAG2INSERTID_VALID_S 7
8706 #define VSI_L2TAGSTXVALID_L2TAG2INSERTID_VALID_M BIT(7)
8707 #define VSI_L2TAGSTXVALID_TIR0INSERTID_S 16
8708 #define VSI_L2TAGSTXVALID_TIR0INSERTID_M MAKEMASK(0x7, 16)
8709 #define VSI_L2TAGSTXVALID_TIR0_INSERT_S 19
8710 #define VSI_L2TAGSTXVALID_TIR0_INSERT_M BIT(19)
8711 #define VSI_L2TAGSTXVALID_TIR1INSERTID_S 20
8712 #define VSI_L2TAGSTXVALID_TIR1INSERTID_M MAKEMASK(0x7, 20)
8713 #define VSI_L2TAGSTXVALID_TIR1_INSERT_S 23
8714 #define VSI_L2TAGSTXVALID_TIR1_INSERT_M BIT(23)
8715 #define VSI_L2TAGSTXVALID_TIR2INSERTID_S 24
8716 #define VSI_L2TAGSTXVALID_TIR2INSERTID_M MAKEMASK(0x7, 24)
8717 #define VSI_L2TAGSTXVALID_TIR2_INSERT_S 27
8718 #define VSI_L2TAGSTXVALID_TIR2_INSERT_M BIT(27)
8719 #define VSI_PASID(_VSI) (0x0009C000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: PFR */
8720 #define VSI_PASID_MAX_INDEX 767
8721 #define VSI_PASID_PASID_S 0
8722 #define VSI_PASID_PASID_M MAKEMASK(0xFFFFF, 0)
8723 #define VSI_PASID_EN_S 31
8724 #define VSI_PASID_EN_M BIT(31)
8725 #define VSI_RUPR(_VSI) (0x00050000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: CORER */
8726 #define VSI_RUPR_MAX_INDEX 767
8727 #define VSI_RUPR_UP0_S 0
8728 #define VSI_RUPR_UP0_M MAKEMASK(0x7, 0)
8729 #define VSI_RUPR_UP1_S 3
8730 #define VSI_RUPR_UP1_M MAKEMASK(0x7, 3)
8731 #define VSI_RUPR_UP2_S 6
8732 #define VSI_RUPR_UP2_M MAKEMASK(0x7, 6)
8733 #define VSI_RUPR_UP3_S 9
8734 #define VSI_RUPR_UP3_M MAKEMASK(0x7, 9)
8735 #define VSI_RUPR_UP4_S 12
8736 #define VSI_RUPR_UP4_M MAKEMASK(0x7, 12)
8737 #define VSI_RUPR_UP5_S 15
8738 #define VSI_RUPR_UP5_M MAKEMASK(0x7, 15)
8739 #define VSI_RUPR_UP6_S 18
8740 #define VSI_RUPR_UP6_M MAKEMASK(0x7, 18)
8741 #define VSI_RUPR_UP7_S 21
8742 #define VSI_RUPR_UP7_M MAKEMASK(0x7, 21)
8743 #define VSI_RXSWCTRL(_VSI) (0x00205000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: CORER */
8744 #define VSI_RXSWCTRL_MAX_INDEX 767
8745 #define VSI_RXSWCTRL_MACVSIPRUNEENABLE_S 8
8746 #define VSI_RXSWCTRL_MACVSIPRUNEENABLE_M BIT(8)
8747 #define VSI_RXSWCTRL_PRUNEENABLE_S 9
8748 #define VSI_RXSWCTRL_PRUNEENABLE_M MAKEMASK(0xF, 9)
8749 #define VSI_RXSWCTRL_SRCPRUNEENABLE_S 13
8750 #define VSI_RXSWCTRL_SRCPRUNEENABLE_M BIT(13)
8751 #define VSI_SRCSWCTRL(_VSI) (0x00209000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: CORER */
8752 #define VSI_SRCSWCTRL_MAX_INDEX 767
8753 #define VSI_SRCSWCTRL_ALLOWDESTOVERRIDE_S 0
8754 #define VSI_SRCSWCTRL_ALLOWDESTOVERRIDE_M BIT(0)
8755 #define VSI_SRCSWCTRL_ALLOWLOOPBACK_S 1
8756 #define VSI_SRCSWCTRL_ALLOWLOOPBACK_M BIT(1)
8757 #define VSI_SRCSWCTRL_LANENABLE_S 2
8758 #define VSI_SRCSWCTRL_LANENABLE_M BIT(2)
8759 #define VSI_SRCSWCTRL_MACAS_S 3
8760 #define VSI_SRCSWCTRL_MACAS_M BIT(3)
8761 #define VSI_SRCSWCTRL_PRUNEENABLE_S 4
8762 #define VSI_SRCSWCTRL_PRUNEENABLE_M MAKEMASK(0xF, 4)
8763 #define VSI_SWITCHID(_VSI) (0x00215000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: CORER */
8764 #define VSI_SWITCHID_MAX_INDEX 767
8765 #define VSI_SWITCHID_SWITCHID_S 0
8766 #define VSI_SWITCHID_SWITCHID_M MAKEMASK(0xFF, 0)
8767 #define VSI_SWT_MIREG(_VSI) (0x00207000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: CORER */
8768 #define VSI_SWT_MIREG_MAX_INDEX 767
8769 #define VSI_SWT_MIREG_MIRRULE_S 0
8770 #define VSI_SWT_MIREG_MIRRULE_M MAKEMASK(0x3F, 0)
8771 #define VSI_SWT_MIREG_MIRENA_S 7
8772 #define VSI_SWT_MIREG_MIRENA_M BIT(7)
8773 #define VSI_SWT_MIRIG(_VSI) (0x00208000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: CORER */
8774 #define VSI_SWT_MIRIG_MAX_INDEX 767
8775 #define VSI_SWT_MIRIG_MIRRULE_S 0
8776 #define VSI_SWT_MIRIG_MIRRULE_M MAKEMASK(0x3F, 0)
8777 #define VSI_SWT_MIRIG_MIRENA_S 7
8778 #define VSI_SWT_MIRIG_MIRENA_M BIT(7)
8779 #define VSI_TAIR(_VSI) (0x00044000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: PFR */
8780 #define VSI_TAIR_MAX_INDEX 767
8781 #define VSI_TAIR_PORT_TAG_ID_S 0
8782 #define VSI_TAIR_PORT_TAG_ID_M MAKEMASK(0xFFFF, 0)
8783 #define VSI_TAR(_VSI) (0x00045000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: CORER */
8784 #define VSI_TAR_MAX_INDEX 767
8785 #define VSI_TAR_ACCEPTTAGGED_S 0
8786 #define VSI_TAR_ACCEPTTAGGED_M MAKEMASK(0x3FF, 0)
8787 #define VSI_TAR_ACCEPTUNTAGGED_S 16
8788 #define VSI_TAR_ACCEPTUNTAGGED_M MAKEMASK(0x3FF, 16)
8789 #define VSI_TIR_0(_VSI) (0x00041000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: CORER */
8790 #define VSI_TIR_0_MAX_INDEX 767
8791 #define VSI_TIR_0_PORT_TAG_ID_S 0
8792 #define VSI_TIR_0_PORT_TAG_ID_M MAKEMASK(0xFFFF, 0)
8793 #define VSI_TIR_1(_VSI) (0x00042000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: CORER */
8794 #define VSI_TIR_1_MAX_INDEX 767
8795 #define VSI_TIR_1_PORT_TAG_ID_S 0
8796 #define VSI_TIR_1_PORT_TAG_ID_M MAKEMASK(0xFFFFFFFF, 0)
8797 #define VSI_TIR_2(_VSI) (0x00043000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: CORER */
8798 #define VSI_TIR_2_MAX_INDEX 767
8799 #define VSI_TIR_2_PORT_TAG_ID_S 0
8800 #define VSI_TIR_2_PORT_TAG_ID_M MAKEMASK(0xFFFF, 0)
8801 #define VSI_TSR(_VSI) (0x00051000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: CORER */
8802 #define VSI_TSR_MAX_INDEX 767
8803 #define VSI_TSR_STRIPTAG_S 0
8804 #define VSI_TSR_STRIPTAG_M MAKEMASK(0x3FF, 0)
8805 #define VSI_TSR_SHOWTAG_S 10
8806 #define VSI_TSR_SHOWTAG_M MAKEMASK(0x3FF, 10)
8807 #define VSI_TSR_SHOWPRIONLY_S 20
8808 #define VSI_TSR_SHOWPRIONLY_M MAKEMASK(0x3FF, 20)
8809 #define VSI_TUPIOM(_VSI) (0x00048000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: CORER */
8810 #define VSI_TUPIOM_MAX_INDEX 767
8811 #define VSI_TUPIOM_UP0_S 0
8812 #define VSI_TUPIOM_UP0_M MAKEMASK(0x7, 0)
8813 #define VSI_TUPIOM_UP1_S 3
8814 #define VSI_TUPIOM_UP1_M MAKEMASK(0x7, 3)
8815 #define VSI_TUPIOM_UP2_S 6
8816 #define VSI_TUPIOM_UP2_M MAKEMASK(0x7, 6)
8817 #define VSI_TUPIOM_UP3_S 9
8818 #define VSI_TUPIOM_UP3_M MAKEMASK(0x7, 9)
8819 #define VSI_TUPIOM_UP4_S 12
8820 #define VSI_TUPIOM_UP4_M MAKEMASK(0x7, 12)
8821 #define VSI_TUPIOM_UP5_S 15
8822 #define VSI_TUPIOM_UP5_M MAKEMASK(0x7, 15)
8823 #define VSI_TUPIOM_UP6_S 18
8824 #define VSI_TUPIOM_UP6_M MAKEMASK(0x7, 18)
8825 #define VSI_TUPIOM_UP7_S 21
8826 #define VSI_TUPIOM_UP7_M MAKEMASK(0x7, 21)
8827 #define VSI_TUPR(_VSI) (0x00047000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: CORER */
8828 #define VSI_TUPR_MAX_INDEX 767
8829 #define VSI_TUPR_UP0_S 0
8830 #define VSI_TUPR_UP0_M MAKEMASK(0x7, 0)
8831 #define VSI_TUPR_UP1_S 3
8832 #define VSI_TUPR_UP1_M MAKEMASK(0x7, 3)
8833 #define VSI_TUPR_UP2_S 6
8834 #define VSI_TUPR_UP2_M MAKEMASK(0x7, 6)
8835 #define VSI_TUPR_UP3_S 9
8836 #define VSI_TUPR_UP3_M MAKEMASK(0x7, 9)
8837 #define VSI_TUPR_UP4_S 12
8838 #define VSI_TUPR_UP4_M MAKEMASK(0x7, 12)
8839 #define VSI_TUPR_UP5_S 15
8840 #define VSI_TUPR_UP5_M MAKEMASK(0x7, 15)
8841 #define VSI_TUPR_UP6_S 18
8842 #define VSI_TUPR_UP6_M MAKEMASK(0x7, 18)
8843 #define VSI_TUPR_UP7_S 21
8844 #define VSI_TUPR_UP7_M MAKEMASK(0x7, 21)
8845 #define VSI_VSI2F(_VSI) (0x001D0000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: PFR */
8846 #define VSI_VSI2F_MAX_INDEX 767
8847 #define VSI_VSI2F_VFVMNUMBER_S 0
8848 #define VSI_VSI2F_VFVMNUMBER_M MAKEMASK(0x3FF, 0)
8849 #define VSI_VSI2F_FUNCTIONTYPE_S 10
8850 #define VSI_VSI2F_FUNCTIONTYPE_M MAKEMASK(0x3, 10)
8851 #define VSI_VSI2F_PFNUMBER_S 12
8852 #define VSI_VSI2F_PFNUMBER_M MAKEMASK(0x7, 12)
8853 #define VSI_VSI2F_BUFFERNUMBER_S 16
8854 #define VSI_VSI2F_BUFFERNUMBER_M MAKEMASK(0x7, 16)
8855 #define VSI_VSI2F_VSI_NUMBER_S 20
8856 #define VSI_VSI2F_VSI_NUMBER_M MAKEMASK(0x3FF, 20)
8857 #define VSI_VSI2F_VSI_ENABLE_S 31
8858 #define VSI_VSI2F_VSI_ENABLE_M BIT(31)
8859 #define VSIQF_FD_CNT(_VSI) (0x00464000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: PFR */
8860 #define VSIQF_FD_CNT_MAX_INDEX 767
8861 #define VSIQF_FD_CNT_FD_GCNT_S 0
8862 #define VSIQF_FD_CNT_FD_GCNT_M MAKEMASK(0x3FFF, 0)
8863 #define VSIQF_FD_CNT_FD_BCNT_S 16
8864 #define VSIQF_FD_CNT_FD_BCNT_M MAKEMASK(0x3FFF, 16)
8865 #define VSIQF_FD_CTL1(_VSI) (0x00411000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: CORER */
8866 #define VSIQF_FD_CTL1_MAX_INDEX 767
8867 #define VSIQF_FD_CTL1_FLT_ENA_S 0
8868 #define VSIQF_FD_CTL1_FLT_ENA_M BIT(0)
8869 #define VSIQF_FD_CTL1_CFG_ENA_S 1
8870 #define VSIQF_FD_CTL1_CFG_ENA_M BIT(1)
8871 #define VSIQF_FD_CTL1_EVICT_ENA_S 2
8872 #define VSIQF_FD_CTL1_EVICT_ENA_M BIT(2)
8873 #define VSIQF_FD_DFLT(_VSI) (0x00457000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: CORER */
8874 #define VSIQF_FD_DFLT_MAX_INDEX 767
8875 #define VSIQF_FD_DFLT_DEFLT_QINDX_S 0
8876 #define VSIQF_FD_DFLT_DEFLT_QINDX_M MAKEMASK(0x7FF, 0)
8877 #define VSIQF_FD_DFLT_DEFLT_TOQUEUE_S 12
8878 #define VSIQF_FD_DFLT_DEFLT_TOQUEUE_M MAKEMASK(0x7, 12)
8879 #define VSIQF_FD_DFLT_COMP_QINDX_S 16
8880 #define VSIQF_FD_DFLT_COMP_QINDX_M MAKEMASK(0x7FF, 16)
8881 #define VSIQF_FD_DFLT_DEFLT_QINDX_PRIO_S 28
8882 #define VSIQF_FD_DFLT_DEFLT_QINDX_PRIO_M MAKEMASK(0x7, 28)
8883 #define VSIQF_FD_DFLT_DEFLT_DROP_S 31
8884 #define VSIQF_FD_DFLT_DEFLT_DROP_M BIT(31)
8885 #define VSIQF_FD_SIZE(_VSI) (0x00462000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: CORER */
8886 #define VSIQF_FD_SIZE_MAX_INDEX 767
8887 #define VSIQF_FD_SIZE_FD_GSIZE_S 0
8888 #define VSIQF_FD_SIZE_FD_GSIZE_M MAKEMASK(0x3FFF, 0)
8889 #define VSIQF_FD_SIZE_FD_BSIZE_S 16
8890 #define VSIQF_FD_SIZE_FD_BSIZE_M MAKEMASK(0x3FFF, 16)
8891 #define VSIQF_HASH_CTL(_VSI) (0x0040D000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: CORER */
8892 #define VSIQF_HASH_CTL_MAX_INDEX 767
8893 #define VSIQF_HASH_CTL_HASH_LUT_SEL_S 0
8894 #define VSIQF_HASH_CTL_HASH_LUT_SEL_M MAKEMASK(0x3, 0)
8895 #define VSIQF_HASH_CTL_GLOB_LUT_S 2
8896 #define VSIQF_HASH_CTL_GLOB_LUT_M MAKEMASK(0xF, 2)
8897 #define VSIQF_HASH_CTL_HASH_SCHEME_S 6
8898 #define VSIQF_HASH_CTL_HASH_SCHEME_M MAKEMASK(0x3, 6)
8899 #define VSIQF_HASH_CTL_TC_OVER_SEL_S 8
8900 #define VSIQF_HASH_CTL_TC_OVER_SEL_M MAKEMASK(0x1F, 8)
8901 #define VSIQF_HASH_CTL_TC_OVER_ENA_S 15
8902 #define VSIQF_HASH_CTL_TC_OVER_ENA_M BIT(15)
8903 #define VSIQF_HKEY(_i, _VSI) (0x00400000 + ((_i) * 4096 + (_VSI) * 4)) /* _i=0...12, _VSI=0...767 */ /* Reset Source: PFR */
8904 #define VSIQF_HKEY_MAX_INDEX 12
8905 #define VSIQF_HKEY_KEY_0_S 0
8906 #define VSIQF_HKEY_KEY_0_M MAKEMASK(0xFF, 0)
8907 #define VSIQF_HKEY_KEY_1_S 8
8908 #define VSIQF_HKEY_KEY_1_M MAKEMASK(0xFF, 8)
8909 #define VSIQF_HKEY_KEY_2_S 16
8910 #define VSIQF_HKEY_KEY_2_M MAKEMASK(0xFF, 16)
8911 #define VSIQF_HKEY_KEY_3_S 24
8912 #define VSIQF_HKEY_KEY_3_M MAKEMASK(0xFF, 24)
8913 #define VSIQF_HLUT(_i, _VSI) (0x00420000 + ((_i) * 4096 + (_VSI) * 4)) /* _i=0...15, _VSI=0...767 */ /* Reset Source: PFR */
8914 #define VSIQF_HLUT_MAX_INDEX 15
8915 #define VSIQF_HLUT_LUT0_S 0
8916 #define VSIQF_HLUT_LUT0_M MAKEMASK(0xF, 0)
8917 #define VSIQF_HLUT_LUT1_S 8
8918 #define VSIQF_HLUT_LUT1_M MAKEMASK(0xF, 8)
8919 #define VSIQF_HLUT_LUT2_S 16
8920 #define VSIQF_HLUT_LUT2_M MAKEMASK(0xF, 16)
8921 #define VSIQF_HLUT_LUT3_S 24
8922 #define VSIQF_HLUT_LUT3_M MAKEMASK(0xF, 24)
8923 #define VSIQF_PE_CTL1(_VSI) (0x00414000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: CORER */
8924 #define VSIQF_PE_CTL1_MAX_INDEX 767
8925 #define VSIQF_PE_CTL1_PE_FLTENA_S 0
8926 #define VSIQF_PE_CTL1_PE_FLTENA_M BIT(0)
8927 #define VSIQF_TC_REGION(_i, _VSI) (0x00448000 + ((_i) * 4096 + (_VSI) * 4)) /* _i=0...3, _VSI=0...767 */ /* Reset Source: CORER */
8928 #define VSIQF_TC_REGION_MAX_INDEX 3
8929 #define VSIQF_TC_REGION_TC_BASE0_S 0
8930 #define VSIQF_TC_REGION_TC_BASE0_M MAKEMASK(0x7FF, 0)
8931 #define VSIQF_TC_REGION_TC_SIZE0_S 11
8932 #define VSIQF_TC_REGION_TC_SIZE0_M MAKEMASK(0xF, 11)
8933 #define VSIQF_TC_REGION_TC_BASE1_S 16
8934 #define VSIQF_TC_REGION_TC_BASE1_M MAKEMASK(0x7FF, 16)
8935 #define VSIQF_TC_REGION_TC_SIZE1_S 27
8936 #define VSIQF_TC_REGION_TC_SIZE1_M MAKEMASK(0xF, 27)
8937 #define GLPM_WUMC 0x0009DEE4 /* Reset Source: POR */
8938 #define GLPM_WUMC_MNG_WU_PF_S 16
8939 #define GLPM_WUMC_MNG_WU_PF_M MAKEMASK(0xFF, 16)
8940 #define PFPM_APM 0x000B8080 /* Reset Source: POR */
8941 #define PFPM_APM_APME_S 0
8942 #define PFPM_APM_APME_M BIT(0)
8943 #define PFPM_WUC 0x0009DC80 /* Reset Source: POR */
8944 #define PFPM_WUC_EN_APM_D0_S 5
8945 #define PFPM_WUC_EN_APM_D0_M BIT(5)
8946 #define PFPM_WUFC 0x0009DC00 /* Reset Source: POR */
8947 #define PFPM_WUFC_LNKC_S 0
8948 #define PFPM_WUFC_LNKC_M BIT(0)
8949 #define PFPM_WUFC_MAG_S 1
8950 #define PFPM_WUFC_MAG_M BIT(1)
8951 #define PFPM_WUFC_MNG_S 3
8952 #define PFPM_WUFC_MNG_M BIT(3)
8953 #define PFPM_WUFC_FLX0_ACT_S 4
8954 #define PFPM_WUFC_FLX0_ACT_M BIT(4)
8955 #define PFPM_WUFC_FLX1_ACT_S 5
8956 #define PFPM_WUFC_FLX1_ACT_M BIT(5)
8957 #define PFPM_WUFC_FLX2_ACT_S 6
8958 #define PFPM_WUFC_FLX2_ACT_M BIT(6)
8959 #define PFPM_WUFC_FLX3_ACT_S 7
8960 #define PFPM_WUFC_FLX3_ACT_M BIT(7)
8961 #define PFPM_WUFC_FLX4_ACT_S 8
8962 #define PFPM_WUFC_FLX4_ACT_M BIT(8)
8963 #define PFPM_WUFC_FLX5_ACT_S 9
8964 #define PFPM_WUFC_FLX5_ACT_M BIT(9)
8965 #define PFPM_WUFC_FLX6_ACT_S 10
8966 #define PFPM_WUFC_FLX6_ACT_M BIT(10)
8967 #define PFPM_WUFC_FLX7_ACT_S 11
8968 #define PFPM_WUFC_FLX7_ACT_M BIT(11)
8969 #define PFPM_WUFC_FLX0_S 16
8970 #define PFPM_WUFC_FLX0_M BIT(16)
8971 #define PFPM_WUFC_FLX1_S 17
8972 #define PFPM_WUFC_FLX1_M BIT(17)
8973 #define PFPM_WUFC_FLX2_S 18
8974 #define PFPM_WUFC_FLX2_M BIT(18)
8975 #define PFPM_WUFC_FLX3_S 19
8976 #define PFPM_WUFC_FLX3_M BIT(19)
8977 #define PFPM_WUFC_FLX4_S 20
8978 #define PFPM_WUFC_FLX4_M BIT(20)
8979 #define PFPM_WUFC_FLX5_S 21
8980 #define PFPM_WUFC_FLX5_M BIT(21)
8981 #define PFPM_WUFC_FLX6_S 22
8982 #define PFPM_WUFC_FLX6_M BIT(22)
8983 #define PFPM_WUFC_FLX7_S 23
8984 #define PFPM_WUFC_FLX7_M BIT(23)
8985 #define PFPM_WUFC_FW_RST_WK_S 31
8986 #define PFPM_WUFC_FW_RST_WK_M BIT(31)
8987 #define PFPM_WUS 0x0009DB80 /* Reset Source: POR */
8988 #define PFPM_WUS_LNKC_S 0
8989 #define PFPM_WUS_LNKC_M BIT(0)
8990 #define PFPM_WUS_MAG_S 1
8991 #define PFPM_WUS_MAG_M BIT(1)
8992 #define PFPM_WUS_PME_STATUS_S 2
8993 #define PFPM_WUS_PME_STATUS_M BIT(2)
8994 #define PFPM_WUS_MNG_S 3
8995 #define PFPM_WUS_MNG_M BIT(3)
8996 #define PFPM_WUS_FLX0_S 16
8997 #define PFPM_WUS_FLX0_M BIT(16)
8998 #define PFPM_WUS_FLX1_S 17
8999 #define PFPM_WUS_FLX1_M BIT(17)
9000 #define PFPM_WUS_FLX2_S 18
9001 #define PFPM_WUS_FLX2_M BIT(18)
9002 #define PFPM_WUS_FLX3_S 19
9003 #define PFPM_WUS_FLX3_M BIT(19)
9004 #define PFPM_WUS_FLX4_S 20
9005 #define PFPM_WUS_FLX4_M BIT(20)
9006 #define PFPM_WUS_FLX5_S 21
9007 #define PFPM_WUS_FLX5_M BIT(21)
9008 #define PFPM_WUS_FLX6_S 22
9009 #define PFPM_WUS_FLX6_M BIT(22)
9010 #define PFPM_WUS_FLX7_S 23
9011 #define PFPM_WUS_FLX7_M BIT(23)
9012 #define PFPM_WUS_FW_RST_WK_S 31
9013 #define PFPM_WUS_FW_RST_WK_M BIT(31)
9014 #define PRTPM_SAH(_i) (0x001E3BA0 + ((_i) * 32)) /* _i=0...3 */ /* Reset Source: PFR */
9015 #define PRTPM_SAH_MAX_INDEX 3
9016 #define PRTPM_SAH_PFPM_SAH_S 0
9017 #define PRTPM_SAH_PFPM_SAH_M MAKEMASK(0xFFFF, 0)
9018 #define PRTPM_SAH_PF_NUM_S 26
9019 #define PRTPM_SAH_PF_NUM_M MAKEMASK(0xF, 26)
9020 #define PRTPM_SAH_MC_MAG_EN_S 30
9021 #define PRTPM_SAH_MC_MAG_EN_M BIT(30)
9022 #define PRTPM_SAH_AV_S 31
9023 #define PRTPM_SAH_AV_M BIT(31)
9024 #define PRTPM_SAL(_i) (0x001E3B20 + ((_i) * 32)) /* _i=0...3 */ /* Reset Source: PFR */
9025 #define PRTPM_SAL_MAX_INDEX 3
9026 #define PRTPM_SAL_PFPM_SAL_S 0
9027 #define PRTPM_SAL_PFPM_SAL_M MAKEMASK(0xFFFFFFFF, 0)
9028 #define GLPE_CQM_FUNC_INVALIDATE 0x00503300 /* Reset Source: CORER */
9029 #define GLPE_CQM_FUNC_INVALIDATE_PF_NUM_S 0
9030 #define GLPE_CQM_FUNC_INVALIDATE_PF_NUM_M MAKEMASK(0x7, 0)
9031 #define GLPE_CQM_FUNC_INVALIDATE_VM_VF_NUM_S 3
9032 #define GLPE_CQM_FUNC_INVALIDATE_VM_VF_NUM_M MAKEMASK(0x3FF, 3)
9033 #define GLPE_CQM_FUNC_INVALIDATE_VM_VF_TYPE_S 13
9034 #define GLPE_CQM_FUNC_INVALIDATE_VM_VF_TYPE_M MAKEMASK(0x3, 13)
9035 #define GLPE_CQM_FUNC_INVALIDATE_ENABLE_S 31
9036 #define GLPE_CQM_FUNC_INVALIDATE_ENABLE_M BIT(31)
9037 #define VFPE_MRTEIDXMASK 0x00009000 /* Reset Source: PFR */
9038 #define VFPE_MRTEIDXMASK_MRTEIDXMASKBITS_S 0
9039 #define VFPE_MRTEIDXMASK_MRTEIDXMASKBITS_M MAKEMASK(0x1F, 0)
9040 #define GLTSYN_HH_DLAY 0x0008881C /* Reset Source: CORER */
9041 #define GLTSYN_HH_DLAY_SYNC_DELAY_S 0
9042 #define GLTSYN_HH_DLAY_SYNC_DELAY_M MAKEMASK(0xF, 0)
9043 #define VF_MBX_ARQBAH1 0x00006000 /* Reset Source: CORER */
9044 #define VF_MBX_ARQBAH1_ARQBAH_S 0
9045 #define VF_MBX_ARQBAH1_ARQBAH_M MAKEMASK(0xFFFFFFFF, 0)
9046 #define VF_MBX_ARQBAL1 0x00006C00 /* Reset Source: CORER */
9047 #define VF_MBX_ARQBAL1_ARQBAL_LSB_S 0
9048 #define VF_MBX_ARQBAL1_ARQBAL_LSB_M MAKEMASK(0x3F, 0)
9049 #define VF_MBX_ARQBAL1_ARQBAL_S 6
9050 #define VF_MBX_ARQBAL1_ARQBAL_M MAKEMASK(0x3FFFFFF, 6)
9051 #define VF_MBX_ARQH1 0x00007400 /* Reset Source: CORER */
9052 #define VF_MBX_ARQH1_ARQH_S 0
9053 #define VF_MBX_ARQH1_ARQH_M MAKEMASK(0x3FF, 0)
9054 #define VF_MBX_ARQLEN1 0x00008000 /* Reset Source: PFR */
9055 #define VF_MBX_ARQLEN1_ARQLEN_S 0
9056 #define VF_MBX_ARQLEN1_ARQLEN_M MAKEMASK(0x3FF, 0)
9057 #define VF_MBX_ARQLEN1_ARQVFE_S 28
9058 #define VF_MBX_ARQLEN1_ARQVFE_M BIT(28)
9059 #define VF_MBX_ARQLEN1_ARQOVFL_S 29
9060 #define VF_MBX_ARQLEN1_ARQOVFL_M BIT(29)
9061 #define VF_MBX_ARQLEN1_ARQCRIT_S 30
9062 #define VF_MBX_ARQLEN1_ARQCRIT_M BIT(30)
9063 #define VF_MBX_ARQLEN1_ARQENABLE_S 31
9064 #define VF_MBX_ARQLEN1_ARQENABLE_M BIT(31)
9065 #define VF_MBX_ARQT1 0x00007000 /* Reset Source: CORER */
9066 #define VF_MBX_ARQT1_ARQT_S 0
9067 #define VF_MBX_ARQT1_ARQT_M MAKEMASK(0x3FF, 0)
9068 #define VF_MBX_ATQBAH1 0x00007800 /* Reset Source: CORER */
9069 #define VF_MBX_ATQBAH1_ATQBAH_S 0
9070 #define VF_MBX_ATQBAH1_ATQBAH_M MAKEMASK(0xFFFFFFFF, 0)
9071 #define VF_MBX_ATQBAL1 0x00007C00 /* Reset Source: CORER */
9072 #define VF_MBX_ATQBAL1_ATQBAL_S 6
9073 #define VF_MBX_ATQBAL1_ATQBAL_M MAKEMASK(0x3FFFFFF, 6)
9074 #define VF_MBX_ATQH1 0x00006400 /* Reset Source: CORER */
9075 #define VF_MBX_ATQH1_ATQH_S 0
9076 #define VF_MBX_ATQH1_ATQH_M MAKEMASK(0x3FF, 0)
9077 #define VF_MBX_ATQLEN1 0x00006800 /* Reset Source: PFR */
9078 #define VF_MBX_ATQLEN1_ATQLEN_S 0
9079 #define VF_MBX_ATQLEN1_ATQLEN_M MAKEMASK(0x3FF, 0)
9080 #define VF_MBX_ATQLEN1_ATQVFE_S 28
9081 #define VF_MBX_ATQLEN1_ATQVFE_M BIT(28)
9082 #define VF_MBX_ATQLEN1_ATQOVFL_S 29
9083 #define VF_MBX_ATQLEN1_ATQOVFL_M BIT(29)
9084 #define VF_MBX_ATQLEN1_ATQCRIT_S 30
9085 #define VF_MBX_ATQLEN1_ATQCRIT_M BIT(30)
9086 #define VF_MBX_ATQLEN1_ATQENABLE_S 31
9087 #define VF_MBX_ATQLEN1_ATQENABLE_M BIT(31)
9088 #define VF_MBX_ATQT1 0x00008400 /* Reset Source: CORER */
9089 #define VF_MBX_ATQT1_ATQT_S 0
9090 #define VF_MBX_ATQT1_ATQT_M MAKEMASK(0x3FF, 0)
9091 #define PFPCI_VF_FLUSH_DONE1 0x0000E400 /* Reset Source: PCIR */
9092 #define PFPCI_VF_FLUSH_DONE1_FLUSH_DONE_S 0
9093 #define PFPCI_VF_FLUSH_DONE1_FLUSH_DONE_M BIT(0)
9094 #define VFGEN_RSTAT1 0x00008800 /* Reset Source: VFR */
9095 #define VFGEN_RSTAT1_VFR_STATE_S 0
9096 #define VFGEN_RSTAT1_VFR_STATE_M MAKEMASK(0x3, 0)
9097 #define VFINT_DYN_CTL0 0x00005C00 /* Reset Source: CORER */
9098 #define VFINT_DYN_CTL0_INTENA_S 0
9099 #define VFINT_DYN_CTL0_INTENA_M BIT(0)
9100 #define VFINT_DYN_CTL0_CLEARPBA_S 1
9101 #define VFINT_DYN_CTL0_CLEARPBA_M BIT(1)
9102 #define VFINT_DYN_CTL0_SWINT_TRIG_S 2
9103 #define VFINT_DYN_CTL0_SWINT_TRIG_M BIT(2)
9104 #define VFINT_DYN_CTL0_ITR_INDX_S 3
9105 #define VFINT_DYN_CTL0_ITR_INDX_M MAKEMASK(0x3, 3)
9106 #define VFINT_DYN_CTL0_INTERVAL_S 5
9107 #define VFINT_DYN_CTL0_INTERVAL_M MAKEMASK(0xFFF, 5)
9108 #define VFINT_DYN_CTL0_SW_ITR_INDX_ENA_S 24
9109 #define VFINT_DYN_CTL0_SW_ITR_INDX_ENA_M BIT(24)
9110 #define VFINT_DYN_CTL0_SW_ITR_INDX_S 25
9111 #define VFINT_DYN_CTL0_SW_ITR_INDX_M MAKEMASK(0x3, 25)
9112 #define VFINT_DYN_CTL0_WB_ON_ITR_S 30
9113 #define VFINT_DYN_CTL0_WB_ON_ITR_M BIT(30)
9114 #define VFINT_DYN_CTL0_INTENA_MSK_S 31
9115 #define VFINT_DYN_CTL0_INTENA_MSK_M BIT(31)
9116 #define VFINT_DYN_CTLN(_i) (0x00003800 + ((_i) * 4)) /* _i=0...63 */ /* Reset Source: CORER */
9117 #define VFINT_DYN_CTLN_MAX_INDEX 63
9118 #define VFINT_DYN_CTLN_INTENA_S 0
9119 #define VFINT_DYN_CTLN_INTENA_M BIT(0)
9120 #define VFINT_DYN_CTLN_CLEARPBA_S 1
9121 #define VFINT_DYN_CTLN_CLEARPBA_M BIT(1)
9122 #define VFINT_DYN_CTLN_SWINT_TRIG_S 2
9123 #define VFINT_DYN_CTLN_SWINT_TRIG_M BIT(2)
9124 #define VFINT_DYN_CTLN_ITR_INDX_S 3
9125 #define VFINT_DYN_CTLN_ITR_INDX_M MAKEMASK(0x3, 3)
9126 #define VFINT_DYN_CTLN_INTERVAL_S 5
9127 #define VFINT_DYN_CTLN_INTERVAL_M MAKEMASK(0xFFF, 5)
9128 #define VFINT_DYN_CTLN_SW_ITR_INDX_ENA_S 24
9129 #define VFINT_DYN_CTLN_SW_ITR_INDX_ENA_M BIT(24)
9130 #define VFINT_DYN_CTLN_SW_ITR_INDX_S 25
9131 #define VFINT_DYN_CTLN_SW_ITR_INDX_M MAKEMASK(0x3, 25)
9132 #define VFINT_DYN_CTLN_WB_ON_ITR_S 30
9133 #define VFINT_DYN_CTLN_WB_ON_ITR_M BIT(30)
9134 #define VFINT_DYN_CTLN_INTENA_MSK_S 31
9135 #define VFINT_DYN_CTLN_INTENA_MSK_M BIT(31)
9136 #define VFINT_ITR0(_i) (0x00004C00 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
9137 #define VFINT_ITR0_MAX_INDEX 2
9138 #define VFINT_ITR0_INTERVAL_S 0
9139 #define VFINT_ITR0_INTERVAL_M MAKEMASK(0xFFF, 0)
9140 #define VFINT_ITRN(_i, _j) (0x00002800 + ((_i) * 4 + (_j) * 12)) /* _i=0...2, _j=0...63 */ /* Reset Source: CORER */
9141 #define VFINT_ITRN_MAX_INDEX 2
9142 #define VFINT_ITRN_INTERVAL_S 0
9143 #define VFINT_ITRN_INTERVAL_M MAKEMASK(0xFFF, 0)
9144 #define QRX_TAIL1(_QRX) (0x00002000 + ((_QRX) * 4)) /* _i=0...255 */ /* Reset Source: CORER */
9145 #define QRX_TAIL1_MAX_INDEX 255
9146 #define QRX_TAIL1_TAIL_S 0
9147 #define QRX_TAIL1_TAIL_M MAKEMASK(0x1FFF, 0)
9148 #define QTX_TAIL(_DBQM) (0x00000000 + ((_DBQM) * 4)) /* _i=0...255 */ /* Reset Source: CORER */
9149 #define QTX_TAIL_MAX_INDEX 255
9150 #define QTX_TAIL_QTX_COMM_DBELL_S 0
9151 #define QTX_TAIL_QTX_COMM_DBELL_M MAKEMASK(0xFFFFFFFF, 0)
9152 #define VF_MBX_CPM_ARQBAH1 0x0000F060 /* Reset Source: CORER */
9153 #define VF_MBX_CPM_ARQBAH1_ARQBAH_S 0
9154 #define VF_MBX_CPM_ARQBAH1_ARQBAH_M MAKEMASK(0xFFFFFFFF, 0)
9155 #define VF_MBX_CPM_ARQBAL1 0x0000F050 /* Reset Source: CORER */
9156 #define VF_MBX_CPM_ARQBAL1_ARQBAL_LSB_S 0
9157 #define VF_MBX_CPM_ARQBAL1_ARQBAL_LSB_M MAKEMASK(0x3F, 0)
9158 #define VF_MBX_CPM_ARQBAL1_ARQBAL_S 6
9159 #define VF_MBX_CPM_ARQBAL1_ARQBAL_M MAKEMASK(0x3FFFFFF, 6)
9160 #define VF_MBX_CPM_ARQH1 0x0000F080 /* Reset Source: CORER */
9161 #define VF_MBX_CPM_ARQH1_ARQH_S 0
9162 #define VF_MBX_CPM_ARQH1_ARQH_M MAKEMASK(0x3FF, 0)
9163 #define VF_MBX_CPM_ARQLEN1 0x0000F070 /* Reset Source: PFR */
9164 #define VF_MBX_CPM_ARQLEN1_ARQLEN_S 0
9165 #define VF_MBX_CPM_ARQLEN1_ARQLEN_M MAKEMASK(0x3FF, 0)
9166 #define VF_MBX_CPM_ARQLEN1_ARQVFE_S 28
9167 #define VF_MBX_CPM_ARQLEN1_ARQVFE_M BIT(28)
9168 #define VF_MBX_CPM_ARQLEN1_ARQOVFL_S 29
9169 #define VF_MBX_CPM_ARQLEN1_ARQOVFL_M BIT(29)
9170 #define VF_MBX_CPM_ARQLEN1_ARQCRIT_S 30
9171 #define VF_MBX_CPM_ARQLEN1_ARQCRIT_M BIT(30)
9172 #define VF_MBX_CPM_ARQLEN1_ARQENABLE_S 31
9173 #define VF_MBX_CPM_ARQLEN1_ARQENABLE_M BIT(31)
9174 #define VF_MBX_CPM_ARQT1 0x0000F090 /* Reset Source: CORER */
9175 #define VF_MBX_CPM_ARQT1_ARQT_S 0
9176 #define VF_MBX_CPM_ARQT1_ARQT_M MAKEMASK(0x3FF, 0)
9177 #define VF_MBX_CPM_ATQBAH1 0x0000F010 /* Reset Source: CORER */
9178 #define VF_MBX_CPM_ATQBAH1_ATQBAH_S 0
9179 #define VF_MBX_CPM_ATQBAH1_ATQBAH_M MAKEMASK(0xFFFFFFFF, 0)
9180 #define VF_MBX_CPM_ATQBAL1 0x0000F000 /* Reset Source: CORER */
9181 #define VF_MBX_CPM_ATQBAL1_ATQBAL_S 6
9182 #define VF_MBX_CPM_ATQBAL1_ATQBAL_M MAKEMASK(0x3FFFFFF, 6)
9183 #define VF_MBX_CPM_ATQH1 0x0000F030 /* Reset Source: CORER */
9184 #define VF_MBX_CPM_ATQH1_ATQH_S 0
9185 #define VF_MBX_CPM_ATQH1_ATQH_M MAKEMASK(0x3FF, 0)
9186 #define VF_MBX_CPM_ATQLEN1 0x0000F020 /* Reset Source: PFR */
9187 #define VF_MBX_CPM_ATQLEN1_ATQLEN_S 0
9188 #define VF_MBX_CPM_ATQLEN1_ATQLEN_M MAKEMASK(0x3FF, 0)
9189 #define VF_MBX_CPM_ATQLEN1_ATQVFE_S 28
9190 #define VF_MBX_CPM_ATQLEN1_ATQVFE_M BIT(28)
9191 #define VF_MBX_CPM_ATQLEN1_ATQOVFL_S 29
9192 #define VF_MBX_CPM_ATQLEN1_ATQOVFL_M BIT(29)
9193 #define VF_MBX_CPM_ATQLEN1_ATQCRIT_S 30
9194 #define VF_MBX_CPM_ATQLEN1_ATQCRIT_M BIT(30)
9195 #define VF_MBX_CPM_ATQLEN1_ATQENABLE_S 31
9196 #define VF_MBX_CPM_ATQLEN1_ATQENABLE_M BIT(31)
9197 #define VF_MBX_CPM_ATQT1 0x0000F040 /* Reset Source: CORER */
9198 #define VF_MBX_CPM_ATQT1_ATQT_S 0
9199 #define VF_MBX_CPM_ATQT1_ATQT_M MAKEMASK(0x3FF, 0)
9200 #define VF_MBX_HLP_ARQBAH1 0x00020060 /* Reset Source: CORER */
9201 #define VF_MBX_HLP_ARQBAH1_ARQBAH_S 0
9202 #define VF_MBX_HLP_ARQBAH1_ARQBAH_M MAKEMASK(0xFFFFFFFF, 0)
9203 #define VF_MBX_HLP_ARQBAL1 0x00020050 /* Reset Source: CORER */
9204 #define VF_MBX_HLP_ARQBAL1_ARQBAL_LSB_S 0
9205 #define VF_MBX_HLP_ARQBAL1_ARQBAL_LSB_M MAKEMASK(0x3F, 0)
9206 #define VF_MBX_HLP_ARQBAL1_ARQBAL_S 6
9207 #define VF_MBX_HLP_ARQBAL1_ARQBAL_M MAKEMASK(0x3FFFFFF, 6)
9208 #define VF_MBX_HLP_ARQH1 0x00020080 /* Reset Source: CORER */
9209 #define VF_MBX_HLP_ARQH1_ARQH_S 0
9210 #define VF_MBX_HLP_ARQH1_ARQH_M MAKEMASK(0x3FF, 0)
9211 #define VF_MBX_HLP_ARQLEN1 0x00020070 /* Reset Source: PFR */
9212 #define VF_MBX_HLP_ARQLEN1_ARQLEN_S 0
9213 #define VF_MBX_HLP_ARQLEN1_ARQLEN_M MAKEMASK(0x3FF, 0)
9214 #define VF_MBX_HLP_ARQLEN1_ARQVFE_S 28
9215 #define VF_MBX_HLP_ARQLEN1_ARQVFE_M BIT(28)
9216 #define VF_MBX_HLP_ARQLEN1_ARQOVFL_S 29
9217 #define VF_MBX_HLP_ARQLEN1_ARQOVFL_M BIT(29)
9218 #define VF_MBX_HLP_ARQLEN1_ARQCRIT_S 30
9219 #define VF_MBX_HLP_ARQLEN1_ARQCRIT_M BIT(30)
9220 #define VF_MBX_HLP_ARQLEN1_ARQENABLE_S 31
9221 #define VF_MBX_HLP_ARQLEN1_ARQENABLE_M BIT(31)
9222 #define VF_MBX_HLP_ARQT1 0x00020090 /* Reset Source: CORER */
9223 #define VF_MBX_HLP_ARQT1_ARQT_S 0
9224 #define VF_MBX_HLP_ARQT1_ARQT_M MAKEMASK(0x3FF, 0)
9225 #define VF_MBX_HLP_ATQBAH1 0x00020010 /* Reset Source: CORER */
9226 #define VF_MBX_HLP_ATQBAH1_ATQBAH_S 0
9227 #define VF_MBX_HLP_ATQBAH1_ATQBAH_M MAKEMASK(0xFFFFFFFF, 0)
9228 #define VF_MBX_HLP_ATQBAL1 0x00020000 /* Reset Source: CORER */
9229 #define VF_MBX_HLP_ATQBAL1_ATQBAL_S 6
9230 #define VF_MBX_HLP_ATQBAL1_ATQBAL_M MAKEMASK(0x3FFFFFF, 6)
9231 #define VF_MBX_HLP_ATQH1 0x00020030 /* Reset Source: CORER */
9232 #define VF_MBX_HLP_ATQH1_ATQH_S 0
9233 #define VF_MBX_HLP_ATQH1_ATQH_M MAKEMASK(0x3FF, 0)
9234 #define VF_MBX_HLP_ATQLEN1 0x00020020 /* Reset Source: PFR */
9235 #define VF_MBX_HLP_ATQLEN1_ATQLEN_S 0
9236 #define VF_MBX_HLP_ATQLEN1_ATQLEN_M MAKEMASK(0x3FF, 0)
9237 #define VF_MBX_HLP_ATQLEN1_ATQVFE_S 28
9238 #define VF_MBX_HLP_ATQLEN1_ATQVFE_M BIT(28)
9239 #define VF_MBX_HLP_ATQLEN1_ATQOVFL_S 29
9240 #define VF_MBX_HLP_ATQLEN1_ATQOVFL_M BIT(29)
9241 #define VF_MBX_HLP_ATQLEN1_ATQCRIT_S 30
9242 #define VF_MBX_HLP_ATQLEN1_ATQCRIT_M BIT(30)
9243 #define VF_MBX_HLP_ATQLEN1_ATQENABLE_S 31
9244 #define VF_MBX_HLP_ATQLEN1_ATQENABLE_M BIT(31)
9245 #define VF_MBX_HLP_ATQT1 0x00020040 /* Reset Source: CORER */
9246 #define VF_MBX_HLP_ATQT1_ATQT_S 0
9247 #define VF_MBX_HLP_ATQT1_ATQT_M MAKEMASK(0x3FF, 0)
9248 #define VF_MBX_PSM_ARQBAH1 0x00021060 /* Reset Source: CORER */
9249 #define VF_MBX_PSM_ARQBAH1_ARQBAH_S 0
9250 #define VF_MBX_PSM_ARQBAH1_ARQBAH_M MAKEMASK(0xFFFFFFFF, 0)
9251 #define VF_MBX_PSM_ARQBAL1 0x00021050 /* Reset Source: CORER */
9252 #define VF_MBX_PSM_ARQBAL1_ARQBAL_LSB_S 0
9253 #define VF_MBX_PSM_ARQBAL1_ARQBAL_LSB_M MAKEMASK(0x3F, 0)
9254 #define VF_MBX_PSM_ARQBAL1_ARQBAL_S 6
9255 #define VF_MBX_PSM_ARQBAL1_ARQBAL_M MAKEMASK(0x3FFFFFF, 6)
9256 #define VF_MBX_PSM_ARQH1 0x00021080 /* Reset Source: CORER */
9257 #define VF_MBX_PSM_ARQH1_ARQH_S 0
9258 #define VF_MBX_PSM_ARQH1_ARQH_M MAKEMASK(0x3FF, 0)
9259 #define VF_MBX_PSM_ARQLEN1 0x00021070 /* Reset Source: PFR */
9260 #define VF_MBX_PSM_ARQLEN1_ARQLEN_S 0
9261 #define VF_MBX_PSM_ARQLEN1_ARQLEN_M MAKEMASK(0x3FF, 0)
9262 #define VF_MBX_PSM_ARQLEN1_ARQVFE_S 28
9263 #define VF_MBX_PSM_ARQLEN1_ARQVFE_M BIT(28)
9264 #define VF_MBX_PSM_ARQLEN1_ARQOVFL_S 29
9265 #define VF_MBX_PSM_ARQLEN1_ARQOVFL_M BIT(29)
9266 #define VF_MBX_PSM_ARQLEN1_ARQCRIT_S 30
9267 #define VF_MBX_PSM_ARQLEN1_ARQCRIT_M BIT(30)
9268 #define VF_MBX_PSM_ARQLEN1_ARQENABLE_S 31
9269 #define VF_MBX_PSM_ARQLEN1_ARQENABLE_M BIT(31)
9270 #define VF_MBX_PSM_ARQT1 0x00021090 /* Reset Source: CORER */
9271 #define VF_MBX_PSM_ARQT1_ARQT_S 0
9272 #define VF_MBX_PSM_ARQT1_ARQT_M MAKEMASK(0x3FF, 0)
9273 #define VF_MBX_PSM_ATQBAH1 0x00021010 /* Reset Source: CORER */
9274 #define VF_MBX_PSM_ATQBAH1_ATQBAH_S 0
9275 #define VF_MBX_PSM_ATQBAH1_ATQBAH_M MAKEMASK(0xFFFFFFFF, 0)
9276 #define VF_MBX_PSM_ATQBAL1 0x00021000 /* Reset Source: CORER */
9277 #define VF_MBX_PSM_ATQBAL1_ATQBAL_S 6
9278 #define VF_MBX_PSM_ATQBAL1_ATQBAL_M MAKEMASK(0x3FFFFFF, 6)
9279 #define VF_MBX_PSM_ATQH1 0x00021030 /* Reset Source: CORER */
9280 #define VF_MBX_PSM_ATQH1_ATQH_S 0
9281 #define VF_MBX_PSM_ATQH1_ATQH_M MAKEMASK(0x3FF, 0)
9282 #define VF_MBX_PSM_ATQLEN1 0x00021020 /* Reset Source: PFR */
9283 #define VF_MBX_PSM_ATQLEN1_ATQLEN_S 0
9284 #define VF_MBX_PSM_ATQLEN1_ATQLEN_M MAKEMASK(0x3FF, 0)
9285 #define VF_MBX_PSM_ATQLEN1_ATQVFE_S 28
9286 #define VF_MBX_PSM_ATQLEN1_ATQVFE_M BIT(28)
9287 #define VF_MBX_PSM_ATQLEN1_ATQOVFL_S 29
9288 #define VF_MBX_PSM_ATQLEN1_ATQOVFL_M BIT(29)
9289 #define VF_MBX_PSM_ATQLEN1_ATQCRIT_S 30
9290 #define VF_MBX_PSM_ATQLEN1_ATQCRIT_M BIT(30)
9291 #define VF_MBX_PSM_ATQLEN1_ATQENABLE_S 31
9292 #define VF_MBX_PSM_ATQLEN1_ATQENABLE_M BIT(31)
9293 #define VF_MBX_PSM_ATQT1 0x00021040 /* Reset Source: CORER */
9294 #define VF_MBX_PSM_ATQT1_ATQT_S 0
9295 #define VF_MBX_PSM_ATQT1_ATQT_M MAKEMASK(0x3FF, 0)
9296 #define VF_SB_CPM_ARQBAH1 0x0000F160 /* Reset Source: CORER */
9297 #define VF_SB_CPM_ARQBAH1_ARQBAH_S 0
9298 #define VF_SB_CPM_ARQBAH1_ARQBAH_M MAKEMASK(0xFFFFFFFF, 0)
9299 #define VF_SB_CPM_ARQBAL1 0x0000F150 /* Reset Source: CORER */
9300 #define VF_SB_CPM_ARQBAL1_ARQBAL_LSB_S 0
9301 #define VF_SB_CPM_ARQBAL1_ARQBAL_LSB_M MAKEMASK(0x3F, 0)
9302 #define VF_SB_CPM_ARQBAL1_ARQBAL_S 6
9303 #define VF_SB_CPM_ARQBAL1_ARQBAL_M MAKEMASK(0x3FFFFFF, 6)
9304 #define VF_SB_CPM_ARQH1 0x0000F180 /* Reset Source: CORER */
9305 #define VF_SB_CPM_ARQH1_ARQH_S 0
9306 #define VF_SB_CPM_ARQH1_ARQH_M MAKEMASK(0x3FF, 0)
9307 #define VF_SB_CPM_ARQLEN1 0x0000F170 /* Reset Source: PFR */
9308 #define VF_SB_CPM_ARQLEN1_ARQLEN_S 0
9309 #define VF_SB_CPM_ARQLEN1_ARQLEN_M MAKEMASK(0x3FF, 0)
9310 #define VF_SB_CPM_ARQLEN1_ARQVFE_S 28
9311 #define VF_SB_CPM_ARQLEN1_ARQVFE_M BIT(28)
9312 #define VF_SB_CPM_ARQLEN1_ARQOVFL_S 29
9313 #define VF_SB_CPM_ARQLEN1_ARQOVFL_M BIT(29)
9314 #define VF_SB_CPM_ARQLEN1_ARQCRIT_S 30
9315 #define VF_SB_CPM_ARQLEN1_ARQCRIT_M BIT(30)
9316 #define VF_SB_CPM_ARQLEN1_ARQENABLE_S 31
9317 #define VF_SB_CPM_ARQLEN1_ARQENABLE_M BIT(31)
9318 #define VF_SB_CPM_ARQT1 0x0000F190 /* Reset Source: CORER */
9319 #define VF_SB_CPM_ARQT1_ARQT_S 0
9320 #define VF_SB_CPM_ARQT1_ARQT_M MAKEMASK(0x3FF, 0)
9321 #define VF_SB_CPM_ATQBAH1 0x0000F110 /* Reset Source: CORER */
9322 #define VF_SB_CPM_ATQBAH1_ATQBAH_S 0
9323 #define VF_SB_CPM_ATQBAH1_ATQBAH_M MAKEMASK(0xFFFFFFFF, 0)
9324 #define VF_SB_CPM_ATQBAL1 0x0000F100 /* Reset Source: CORER */
9325 #define VF_SB_CPM_ATQBAL1_ATQBAL_S 6
9326 #define VF_SB_CPM_ATQBAL1_ATQBAL_M MAKEMASK(0x3FFFFFF, 6)
9327 #define VF_SB_CPM_ATQH1 0x0000F130 /* Reset Source: CORER */
9328 #define VF_SB_CPM_ATQH1_ATQH_S 0
9329 #define VF_SB_CPM_ATQH1_ATQH_M MAKEMASK(0x3FF, 0)
9330 #define VF_SB_CPM_ATQLEN1 0x0000F120 /* Reset Source: PFR */
9331 #define VF_SB_CPM_ATQLEN1_ATQLEN_S 0
9332 #define VF_SB_CPM_ATQLEN1_ATQLEN_M MAKEMASK(0x3FF, 0)
9333 #define VF_SB_CPM_ATQLEN1_ATQVFE_S 28
9334 #define VF_SB_CPM_ATQLEN1_ATQVFE_M BIT(28)
9335 #define VF_SB_CPM_ATQLEN1_ATQOVFL_S 29
9336 #define VF_SB_CPM_ATQLEN1_ATQOVFL_M BIT(29)
9337 #define VF_SB_CPM_ATQLEN1_ATQCRIT_S 30
9338 #define VF_SB_CPM_ATQLEN1_ATQCRIT_M BIT(30)
9339 #define VF_SB_CPM_ATQLEN1_ATQENABLE_S 31
9340 #define VF_SB_CPM_ATQLEN1_ATQENABLE_M BIT(31)
9341 #define VF_SB_CPM_ATQT1 0x0000F140 /* Reset Source: CORER */
9342 #define VF_SB_CPM_ATQT1_ATQT_S 0
9343 #define VF_SB_CPM_ATQT1_ATQT_M MAKEMASK(0x3FF, 0)
9344 #define VFINT_DYN_CTL(_i) (0x00023000 + ((_i) * 4096)) /* _i=0...7 */ /* Reset Source: CORER */
9345 #define VFINT_DYN_CTL_MAX_INDEX 7
9346 #define VFINT_DYN_CTL_INTENA_S 0
9347 #define VFINT_DYN_CTL_INTENA_M BIT(0)
9348 #define VFINT_DYN_CTL_CLEARPBA_S 1
9349 #define VFINT_DYN_CTL_CLEARPBA_M BIT(1)
9350 #define VFINT_DYN_CTL_SWINT_TRIG_S 2
9351 #define VFINT_DYN_CTL_SWINT_TRIG_M BIT(2)
9352 #define VFINT_DYN_CTL_ITR_INDX_S 3
9353 #define VFINT_DYN_CTL_ITR_INDX_M MAKEMASK(0x3, 3)
9354 #define VFINT_DYN_CTL_INTERVAL_S 5
9355 #define VFINT_DYN_CTL_INTERVAL_M MAKEMASK(0xFFF, 5)
9356 #define VFINT_DYN_CTL_SW_ITR_INDX_ENA_S 24
9357 #define VFINT_DYN_CTL_SW_ITR_INDX_ENA_M BIT(24)
9358 #define VFINT_DYN_CTL_SW_ITR_INDX_S 25
9359 #define VFINT_DYN_CTL_SW_ITR_INDX_M MAKEMASK(0x3, 25)
9360 #define VFINT_DYN_CTL_WB_ON_ITR_S 30
9361 #define VFINT_DYN_CTL_WB_ON_ITR_M BIT(30)
9362 #define VFINT_DYN_CTL_INTENA_MSK_S 31
9363 #define VFINT_DYN_CTL_INTENA_MSK_M BIT(31)
9364 #define VFINT_ITR_0(_i) (0x00023004 + ((_i) * 4096)) /* _i=0...7 */ /* Reset Source: CORER */
9365 #define VFINT_ITR_0_MAX_INDEX 7
9366 #define VFINT_ITR_0_INTERVAL_S 0
9367 #define VFINT_ITR_0_INTERVAL_M MAKEMASK(0xFFF, 0)
9368 #define VFINT_ITR_1(_i) (0x00023008 + ((_i) * 4096)) /* _i=0...7 */ /* Reset Source: CORER */
9369 #define VFINT_ITR_1_MAX_INDEX 7
9370 #define VFINT_ITR_1_INTERVAL_S 0
9371 #define VFINT_ITR_1_INTERVAL_M MAKEMASK(0xFFF, 0)
9372 #define VFINT_ITR_2(_i) (0x0002300C + ((_i) * 4096)) /* _i=0...7 */ /* Reset Source: CORER */
9373 #define VFINT_ITR_2_MAX_INDEX 7
9374 #define VFINT_ITR_2_INTERVAL_S 0
9375 #define VFINT_ITR_2_INTERVAL_M MAKEMASK(0xFFF, 0)
9376 #define VFQRX_TAIL(_QRX) (0x0002E000 + ((_QRX) * 4)) /* _i=0...255 */ /* Reset Source: CORER */
9377 #define VFQRX_TAIL_MAX_INDEX 255
9378 #define VFQRX_TAIL_TAIL_S 0
9379 #define VFQRX_TAIL_TAIL_M MAKEMASK(0x1FFF, 0)
9380 #define VFQTX_COMM_DBELL(_DBQM) (0x00030000 + ((_DBQM) * 4)) /* _i=0...255 */ /* Reset Source: CORER */
9381 #define VFQTX_COMM_DBELL_MAX_INDEX 255
9382 #define VFQTX_COMM_DBELL_QTX_COMM_DBELL_S 0
9383 #define VFQTX_COMM_DBELL_QTX_COMM_DBELL_M MAKEMASK(0xFFFFFFFF, 0)
9384 #define VFQTX_COMM_DBLQ_DBELL(_DBLQ) (0x00022000 + ((_DBLQ) * 4)) /* _i=0...3 */ /* Reset Source: CORER */
9385 #define VFQTX_COMM_DBLQ_DBELL_MAX_INDEX 3
9386 #define VFQTX_COMM_DBLQ_DBELL_TAIL_S 0
9387 #define VFQTX_COMM_DBLQ_DBELL_TAIL_M MAKEMASK(0x1FFF, 0)
9388 #define MSIX_TMSG1(_i) (0x00000008 + ((_i) * 16)) /* _i=0...64 */ /* Reset Source: FLR */
9389 #define MSIX_TMSG1_MAX_INDEX 64
9390 #define MSIX_TMSG1_MSIXTMSG_S 0
9391 #define MSIX_TMSG1_MSIXTMSG_M MAKEMASK(0xFFFFFFFF, 0)
9392 #define VFPE_AEQALLOC1 0x0000A400 /* Reset Source: VFR */
9393 #define VFPE_AEQALLOC1_AECOUNT_S 0
9394 #define VFPE_AEQALLOC1_AECOUNT_M MAKEMASK(0xFFFFFFFF, 0)
9395 #define VFPE_CCQPHIGH1 0x00009800 /* Reset Source: VFR */
9396 #define VFPE_CCQPHIGH1_PECCQPHIGH_S 0
9397 #define VFPE_CCQPHIGH1_PECCQPHIGH_M MAKEMASK(0xFFFFFFFF, 0)
9398 #define VFPE_CCQPLOW1 0x0000AC00 /* Reset Source: VFR */
9399 #define VFPE_CCQPLOW1_PECCQPLOW_S 0
9400 #define VFPE_CCQPLOW1_PECCQPLOW_M MAKEMASK(0xFFFFFFFF, 0)
9401 #define VFPE_CCQPSTATUS1 0x0000B800 /* Reset Source: VFR */
9402 #define VFPE_CCQPSTATUS1_CCQP_DONE_S 0
9403 #define VFPE_CCQPSTATUS1_CCQP_DONE_M BIT(0)
9404 #define VFPE_CCQPSTATUS1_HMC_PROFILE_S 4
9405 #define VFPE_CCQPSTATUS1_HMC_PROFILE_M MAKEMASK(0x7, 4)
9406 #define VFPE_CCQPSTATUS1_RDMA_EN_VFS_S 16
9407 #define VFPE_CCQPSTATUS1_RDMA_EN_VFS_M MAKEMASK(0x3F, 16)
9408 #define VFPE_CCQPSTATUS1_CCQP_ERR_S 31
9409 #define VFPE_CCQPSTATUS1_CCQP_ERR_M BIT(31)
9410 #define VFPE_CQACK1 0x0000B000 /* Reset Source: VFR */
9411 #define VFPE_CQACK1_PECQID_S 0
9412 #define VFPE_CQACK1_PECQID_M MAKEMASK(0x7FFFF, 0)
9413 #define VFPE_CQARM1 0x0000B400 /* Reset Source: VFR */
9414 #define VFPE_CQARM1_PECQID_S 0
9415 #define VFPE_CQARM1_PECQID_M MAKEMASK(0x7FFFF, 0)
9416 #define VFPE_CQPDB1 0x0000BC00 /* Reset Source: VFR */
9417 #define VFPE_CQPDB1_WQHEAD_S 0
9418 #define VFPE_CQPDB1_WQHEAD_M MAKEMASK(0x7FF, 0)
9419 #define VFPE_CQPERRCODES1 0x00009C00 /* Reset Source: VFR */
9420 #define VFPE_CQPERRCODES1_CQP_MINOR_CODE_S 0
9421 #define VFPE_CQPERRCODES1_CQP_MINOR_CODE_M MAKEMASK(0xFFFF, 0)
9422 #define VFPE_CQPERRCODES1_CQP_MAJOR_CODE_S 16
9423 #define VFPE_CQPERRCODES1_CQP_MAJOR_CODE_M MAKEMASK(0xFFFF, 16)
9424 #define VFPE_CQPTAIL1 0x0000A000 /* Reset Source: VFR */
9425 #define VFPE_CQPTAIL1_WQTAIL_S 0
9426 #define VFPE_CQPTAIL1_WQTAIL_M MAKEMASK(0x7FF, 0)
9427 #define VFPE_CQPTAIL1_CQP_OP_ERR_S 31
9428 #define VFPE_CQPTAIL1_CQP_OP_ERR_M BIT(31)
9429 #define VFPE_IPCONFIG01 0x00008C00 /* Reset Source: VFR */
9430 #define VFPE_IPCONFIG01_PEIPID_S 0
9431 #define VFPE_IPCONFIG01_PEIPID_M MAKEMASK(0xFFFF, 0)
9432 #define VFPE_IPCONFIG01_USEENTIREIDRANGE_S 16
9433 #define VFPE_IPCONFIG01_USEENTIREIDRANGE_M BIT(16)
9434 #define VFPE_IPCONFIG01_UDP_SRC_PORT_MASK_EN_S 17
9435 #define VFPE_IPCONFIG01_UDP_SRC_PORT_MASK_EN_M BIT(17)
9436 #define VFPE_MRTEIDXMASK1(_VF) (0x00509800 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: PFR */
9437 #define VFPE_MRTEIDXMASK1_MAX_INDEX 255
9438 #define VFPE_MRTEIDXMASK1_MRTEIDXMASKBITS_S 0
9439 #define VFPE_MRTEIDXMASK1_MRTEIDXMASKBITS_M MAKEMASK(0x1F, 0)
9440 #define VFPE_RCVUNEXPECTEDERROR1 0x00009400 /* Reset Source: VFR */
9441 #define VFPE_RCVUNEXPECTEDERROR1_TCP_RX_UNEXP_ERR_S 0
9442 #define VFPE_RCVUNEXPECTEDERROR1_TCP_RX_UNEXP_ERR_M MAKEMASK(0xFFFFFF, 0)
9443 #define VFPE_TCPNOWTIMER1 0x0000A800 /* Reset Source: VFR */
9444 #define VFPE_TCPNOWTIMER1_TCP_NOW_S 0
9445 #define VFPE_TCPNOWTIMER1_TCP_NOW_M MAKEMASK(0xFFFFFFFF, 0)
9446 #define VFPE_WQEALLOC1 0x0000C000 /* Reset Source: VFR */
9447 #define VFPE_WQEALLOC1_PEQPID_S 0
9448 #define VFPE_WQEALLOC1_PEQPID_M MAKEMASK(0x3FFFF, 0)
9449 #define VFPE_WQEALLOC1_WQE_DESC_INDEX_S 20
9450 #define VFPE_WQEALLOC1_WQE_DESC_INDEX_M MAKEMASK(0xFFF, 20)