1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2001-2020 Intel Corporation
5 #include "ice_common.h"
9 * @hw: pointer to the HW struct
10 * @module_typeid: module pointer location in words from the NVM beginning
11 * @offset: byte offset from the module beginning
12 * @length: length of the section to be read (in bytes from the offset)
13 * @data: command buffer (size [bytes] = length)
14 * @last_command: tells if this is the last command in a series
15 * @read_shadow_ram: tell if this is a shadow RAM read
16 * @cd: pointer to command details structure or NULL
18 * Read the NVM using the admin queue commands (0x0701)
21 ice_aq_read_nvm(struct ice_hw *hw, u16 module_typeid, u32 offset, u16 length,
22 void *data, bool last_command, bool read_shadow_ram,
25 struct ice_aq_desc desc;
26 struct ice_aqc_nvm *cmd;
28 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
30 cmd = &desc.params.nvm;
32 if (offset > ICE_AQC_NVM_MAX_OFFSET)
35 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_nvm_read);
37 if (!read_shadow_ram && module_typeid == ICE_AQC_NVM_START_POINT)
38 cmd->cmd_flags |= ICE_AQC_NVM_FLASH_ONLY;
40 /* If this is the last command in a series, set the proper flag. */
42 cmd->cmd_flags |= ICE_AQC_NVM_LAST_CMD;
43 cmd->module_typeid = CPU_TO_LE16(module_typeid);
44 cmd->offset_low = CPU_TO_LE16(offset & 0xFFFF);
45 cmd->offset_high = (offset >> 16) & 0xFF;
46 cmd->length = CPU_TO_LE16(length);
48 return ice_aq_send_cmd(hw, &desc, data, length, cd);
52 * ice_read_flat_nvm - Read portion of NVM by flat offset
53 * @hw: pointer to the HW struct
54 * @offset: offset from beginning of NVM
55 * @length: (in) number of bytes to read; (out) number of bytes actually read
56 * @data: buffer to return data in (sized to fit the specified length)
57 * @read_shadow_ram: if true, read from shadow RAM instead of NVM
59 * Reads a portion of the NVM, as a flat memory space. This function correctly
60 * breaks read requests across Shadow RAM sectors and ensures that no single
61 * read request exceeds the maximum 4KB read for a single AdminQ command.
63 * Returns a status code on failure. Note that the data pointer may be
64 * partially updated if some reads succeed before a failure.
67 ice_read_flat_nvm(struct ice_hw *hw, u32 offset, u32 *length, u8 *data,
70 enum ice_status status;
75 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
79 /* Verify the length of the read if this is for the Shadow RAM */
80 if (read_shadow_ram && ((offset + inlen) > (hw->flash.sr_words * 2u))) {
81 ice_debug(hw, ICE_DBG_NVM, "NVM error: requested data is beyond Shadow RAM limit\n");
86 u32 read_size, sector_offset;
88 /* ice_aq_read_nvm cannot read more than 4KB at a time.
89 * Additionally, a read from the Shadow RAM may not cross over
90 * a sector boundary. Conveniently, the sector size is also
93 sector_offset = offset % ICE_AQ_MAX_BUF_LEN;
94 read_size = MIN_T(u32, ICE_AQ_MAX_BUF_LEN - sector_offset,
97 last_cmd = !(bytes_read + read_size < inlen);
99 /* ice_aq_read_nvm takes the length as a u16. Our read_size is
100 * calculated using a u32, but the ICE_AQ_MAX_BUF_LEN maximum
101 * size guarantees that it will fit within the 2 bytes.
103 status = ice_aq_read_nvm(hw, ICE_AQC_NVM_START_POINT,
104 offset, (u16)read_size,
105 data + bytes_read, last_cmd,
106 read_shadow_ram, NULL);
110 bytes_read += read_size;
114 *length = bytes_read;
119 * ice_read_sr_word_aq - Reads Shadow RAM via AQ
120 * @hw: pointer to the HW structure
121 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF)
122 * @data: word read from the Shadow RAM
124 * Reads one 16 bit word from the Shadow RAM using ice_read_flat_nvm.
126 static enum ice_status
127 ice_read_sr_word_aq(struct ice_hw *hw, u16 offset, u16 *data)
129 u32 bytes = sizeof(u16);
130 enum ice_status status;
133 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
135 /* Note that ice_read_flat_nvm checks if the read is past the Shadow
136 * RAM size, and ensures we don't read across a Shadow RAM sector
139 status = ice_read_flat_nvm(hw, offset * sizeof(u16), &bytes,
140 (_FORCE_ u8 *)&data_local, true);
144 *data = LE16_TO_CPU(data_local);
149 * ice_read_sr_buf_aq - Reads Shadow RAM buf via AQ
150 * @hw: pointer to the HW structure
151 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF)
152 * @words: (in) number of words to read; (out) number of words actually read
153 * @data: words read from the Shadow RAM
155 * Reads 16 bit words (data buf) from the Shadow RAM. Ownership of the NVM is
156 * taken before reading the buffer and later released.
158 static enum ice_status
159 ice_read_sr_buf_aq(struct ice_hw *hw, u16 offset, u16 *words, u16 *data)
161 u32 bytes = *words * 2, i;
162 enum ice_status status;
164 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
166 /* ice_read_flat_nvm takes into account the 4KB AdminQ and Shadow RAM
167 * sector restrictions necessary when reading from the NVM.
169 status = ice_read_flat_nvm(hw, offset * 2, &bytes, (u8 *)data, true);
171 /* Report the number of words successfully read */
174 /* Byte swap the words up to the amount we actually read */
175 for (i = 0; i < *words; i++)
176 data[i] = LE16_TO_CPU(((_FORCE_ __le16 *)data)[i]);
182 * ice_acquire_nvm - Generic request for acquiring the NVM ownership
183 * @hw: pointer to the HW structure
184 * @access: NVM access type (read or write)
186 * This function will request NVM ownership.
189 ice_acquire_nvm(struct ice_hw *hw, enum ice_aq_res_access_type access)
191 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
193 if (hw->flash.blank_nvm_mode)
196 return ice_acquire_res(hw, ICE_NVM_RES_ID, access, ICE_NVM_TIMEOUT);
200 * ice_release_nvm - Generic request for releasing the NVM ownership
201 * @hw: pointer to the HW structure
203 * This function will release NVM ownership.
205 void ice_release_nvm(struct ice_hw *hw)
207 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
209 if (hw->flash.blank_nvm_mode)
212 ice_release_res(hw, ICE_NVM_RES_ID);
216 * ice_get_flash_bank_offset - Get offset into requested flash bank
217 * @hw: pointer to the HW structure
218 * @bank: whether to read from the active or inactive flash bank
219 * @module: the module to read from
221 * Based on the module, lookup the module offset from the beginning of the
224 * Returns the flash offset. Note that a value of zero is invalid and must be
225 * treated as an error.
227 static u32 ice_get_flash_bank_offset(struct ice_hw *hw, enum ice_bank_select bank, u16 module)
229 struct ice_bank_info *banks = &hw->flash.banks;
230 enum ice_flash_bank active_bank;
231 bool second_bank_active;
235 case ICE_SR_1ST_NVM_BANK_PTR:
236 offset = banks->nvm_ptr;
237 size = banks->nvm_size;
238 active_bank = banks->nvm_bank;
240 case ICE_SR_1ST_OROM_BANK_PTR:
241 offset = banks->orom_ptr;
242 size = banks->orom_size;
243 active_bank = banks->orom_bank;
245 case ICE_SR_NETLIST_BANK_PTR:
246 offset = banks->netlist_ptr;
247 size = banks->netlist_size;
248 active_bank = banks->netlist_bank;
251 ice_debug(hw, ICE_DBG_NVM, "Unexpected value for flash module: 0x%04x\n", module);
255 switch (active_bank) {
256 case ICE_1ST_FLASH_BANK:
257 second_bank_active = false;
259 case ICE_2ND_FLASH_BANK:
260 second_bank_active = true;
263 ice_debug(hw, ICE_DBG_NVM, "Unexpected value for active flash bank: %u\n",
268 /* The second flash bank is stored immediately following the first
269 * bank. Based on whether the 1st or 2nd bank is active, and whether
270 * we want the active or inactive bank, calculate the desired offset.
273 case ICE_ACTIVE_FLASH_BANK:
274 return offset + (second_bank_active ? size : 0);
275 case ICE_INACTIVE_FLASH_BANK:
276 return offset + (second_bank_active ? 0 : size);
279 ice_debug(hw, ICE_DBG_NVM, "Unexpected value for flash bank selection: %u\n", bank);
284 * ice_read_flash_module - Read a word from one of the main NVM modules
285 * @hw: pointer to the HW structure
286 * @bank: which bank of the module to read
287 * @module: the module to read
288 * @offset: the offset into the module in bytes
289 * @data: storage for the word read from the flash
290 * @length: bytes of data to read
292 * Read data from the specified flash module. The bank parameter indicates
293 * whether or not to read from the active bank or the inactive bank of that
296 * The word will be read using flat NVM access, and relies on the
297 * hw->flash.banks data being setup by ice_determine_active_flash_banks()
298 * during initialization.
300 static enum ice_status
301 ice_read_flash_module(struct ice_hw *hw, enum ice_bank_select bank, u16 module,
302 u32 offset, u8 *data, u32 length)
304 enum ice_status status;
307 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
309 start = ice_get_flash_bank_offset(hw, bank, module);
311 ice_debug(hw, ICE_DBG_NVM, "Unable to calculate flash bank offset for module 0x%04x\n",
313 return ICE_ERR_PARAM;
316 status = ice_acquire_nvm(hw, ICE_RES_READ);
320 status = ice_read_flat_nvm(hw, start + offset, &length, data, false);
328 * ice_read_nvm_module - Read from the active main NVM module
329 * @hw: pointer to the HW structure
330 * @bank: whether to read from active or inactive NVM module
331 * @offset: offset into the NVM module to read, in words
332 * @data: storage for returned word value
334 * Read the specified word from the active NVM module. This includes the CSS
335 * header at the start of the NVM module.
337 static enum ice_status
338 ice_read_nvm_module(struct ice_hw *hw, enum ice_bank_select bank, u32 offset, u16 *data)
340 enum ice_status status;
343 status = ice_read_flash_module(hw, bank, ICE_SR_1ST_NVM_BANK_PTR, offset * sizeof(u16),
344 (_FORCE_ u8 *)&data_local, sizeof(u16));
346 *data = LE16_TO_CPU(data_local);
352 * ice_read_nvm_sr_copy - Read a word from the Shadow RAM copy in the NVM bank
353 * @hw: pointer to the HW structure
354 * @bank: whether to read from the active or inactive NVM module
355 * @offset: offset into the Shadow RAM copy to read, in words
356 * @data: storage for returned word value
358 * Read the specified word from the copy of the Shadow RAM found in the
359 * specified NVM module.
361 static enum ice_status
362 ice_read_nvm_sr_copy(struct ice_hw *hw, enum ice_bank_select bank, u32 offset, u16 *data)
364 return ice_read_nvm_module(hw, bank, ICE_NVM_SR_COPY_WORD_OFFSET + offset, data);
368 * ice_read_orom_module - Read from the active Option ROM module
369 * @hw: pointer to the HW structure
370 * @bank: whether to read from active or inactive OROM module
371 * @offset: offset into the OROM module to read, in words
372 * @data: storage for returned word value
374 * Read the specified word from the active Option ROM module of the flash.
375 * Note that unlike the NVM module, the CSS data is stored at the end of the
376 * module instead of at the beginning.
378 static enum ice_status
379 ice_read_orom_module(struct ice_hw *hw, enum ice_bank_select bank, u32 offset, u16 *data)
381 enum ice_status status;
384 status = ice_read_flash_module(hw, bank, ICE_SR_1ST_OROM_BANK_PTR, offset * sizeof(u16),
385 (_FORCE_ u8 *)&data_local, sizeof(u16));
387 *data = LE16_TO_CPU(data_local);
393 * ice_read_sr_word - Reads Shadow RAM word and acquire NVM if necessary
394 * @hw: pointer to the HW structure
395 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF)
396 * @data: word read from the Shadow RAM
398 * Reads one 16 bit word from the Shadow RAM using the ice_read_sr_word_aq.
400 enum ice_status ice_read_sr_word(struct ice_hw *hw, u16 offset, u16 *data)
402 enum ice_status status;
404 status = ice_acquire_nvm(hw, ICE_RES_READ);
406 status = ice_read_sr_word_aq(hw, offset, data);
414 * ice_get_pfa_module_tlv - Reads sub module TLV from NVM PFA
415 * @hw: pointer to hardware structure
416 * @module_tlv: pointer to module TLV to return
417 * @module_tlv_len: pointer to module TLV length to return
418 * @module_type: module type requested
420 * Finds the requested sub module TLV type from the Preserved Field
421 * Area (PFA) and returns the TLV pointer and length. The caller can
422 * use these to read the variable length TLV value.
425 ice_get_pfa_module_tlv(struct ice_hw *hw, u16 *module_tlv, u16 *module_tlv_len,
428 enum ice_status status;
429 u16 pfa_len, pfa_ptr;
432 status = ice_read_sr_word(hw, ICE_SR_PFA_PTR, &pfa_ptr);
433 if (status != ICE_SUCCESS) {
434 ice_debug(hw, ICE_DBG_INIT, "Preserved Field Array pointer.\n");
437 status = ice_read_sr_word(hw, pfa_ptr, &pfa_len);
438 if (status != ICE_SUCCESS) {
439 ice_debug(hw, ICE_DBG_INIT, "Failed to read PFA length.\n");
442 /* Starting with first TLV after PFA length, iterate through the list
443 * of TLVs to find the requested one.
445 next_tlv = pfa_ptr + 1;
446 while (next_tlv < pfa_ptr + pfa_len) {
447 u16 tlv_sub_module_type;
451 status = ice_read_sr_word(hw, next_tlv, &tlv_sub_module_type);
452 if (status != ICE_SUCCESS) {
453 ice_debug(hw, ICE_DBG_INIT, "Failed to read TLV type.\n");
456 /* Read TLV length */
457 status = ice_read_sr_word(hw, next_tlv + 1, &tlv_len);
458 if (status != ICE_SUCCESS) {
459 ice_debug(hw, ICE_DBG_INIT, "Failed to read TLV length.\n");
462 if (tlv_sub_module_type == module_type) {
464 *module_tlv = next_tlv;
465 *module_tlv_len = tlv_len;
468 return ICE_ERR_INVAL_SIZE;
470 /* Check next TLV, i.e. current TLV pointer + length + 2 words
471 * (for current TLV's type and length)
473 next_tlv = next_tlv + tlv_len + 2;
475 /* Module does not exist */
476 return ICE_ERR_DOES_NOT_EXIST;
480 * ice_read_pba_string - Reads part number string from NVM
481 * @hw: pointer to hardware structure
482 * @pba_num: stores the part number string from the NVM
483 * @pba_num_size: part number string buffer length
485 * Reads the part number string from the NVM.
488 ice_read_pba_string(struct ice_hw *hw, u8 *pba_num, u32 pba_num_size)
490 u16 pba_tlv, pba_tlv_len;
491 enum ice_status status;
492 u16 pba_word, pba_size;
495 status = ice_get_pfa_module_tlv(hw, &pba_tlv, &pba_tlv_len,
496 ICE_SR_PBA_BLOCK_PTR);
497 if (status != ICE_SUCCESS) {
498 ice_debug(hw, ICE_DBG_INIT, "Failed to read PBA Block TLV.\n");
502 /* pba_size is the next word */
503 status = ice_read_sr_word(hw, (pba_tlv + 2), &pba_size);
504 if (status != ICE_SUCCESS) {
505 ice_debug(hw, ICE_DBG_INIT, "Failed to read PBA Section size.\n");
509 if (pba_tlv_len < pba_size) {
510 ice_debug(hw, ICE_DBG_INIT, "Invalid PBA Block TLV size.\n");
511 return ICE_ERR_INVAL_SIZE;
514 /* Subtract one to get PBA word count (PBA Size word is included in
518 if (pba_num_size < (((u32)pba_size * 2) + 1)) {
519 ice_debug(hw, ICE_DBG_INIT, "Buffer too small for PBA data.\n");
520 return ICE_ERR_PARAM;
523 for (i = 0; i < pba_size; i++) {
524 status = ice_read_sr_word(hw, (pba_tlv + 2 + 1) + i, &pba_word);
525 if (status != ICE_SUCCESS) {
526 ice_debug(hw, ICE_DBG_INIT, "Failed to read PBA Block word %d.\n", i);
530 pba_num[(i * 2)] = (pba_word >> 8) & 0xFF;
531 pba_num[(i * 2) + 1] = pba_word & 0xFF;
533 pba_num[(pba_size * 2)] = '\0';
539 * ice_get_nvm_srev - Read the security revision from the NVM CSS header
540 * @hw: pointer to the HW struct
541 * @bank: whether to read from the active or inactive flash bank
542 * @srev: storage for security revision
544 * Read the security revision out of the CSS header of the active NVM module
547 static enum ice_status ice_get_nvm_srev(struct ice_hw *hw, enum ice_bank_select bank, u32 *srev)
549 enum ice_status status;
552 status = ice_read_nvm_module(hw, bank, ICE_NVM_CSS_SREV_L, &srev_l);
556 status = ice_read_nvm_module(hw, bank, ICE_NVM_CSS_SREV_H, &srev_h);
560 *srev = srev_h << 16 | srev_l;
566 * ice_get_nvm_ver_info - Read NVM version information
567 * @hw: pointer to the HW struct
568 * @bank: whether to read from the active or inactive flash bank
569 * @nvm: pointer to NVM info structure
571 * Read the NVM EETRACK ID and map version of the main NVM image bank, filling
572 * in the nvm info structure.
574 static enum ice_status
575 ice_get_nvm_ver_info(struct ice_hw *hw, enum ice_bank_select bank, struct ice_nvm_info *nvm)
577 u16 eetrack_lo, eetrack_hi, ver;
578 enum ice_status status;
580 status = ice_read_nvm_sr_copy(hw, bank, ICE_SR_NVM_DEV_STARTER_VER, &ver);
582 ice_debug(hw, ICE_DBG_NVM, "Failed to read DEV starter version.\n");
586 nvm->major = (ver & ICE_NVM_VER_HI_MASK) >> ICE_NVM_VER_HI_SHIFT;
587 nvm->minor = (ver & ICE_NVM_VER_LO_MASK) >> ICE_NVM_VER_LO_SHIFT;
589 status = ice_read_nvm_sr_copy(hw, bank, ICE_SR_NVM_EETRACK_LO, &eetrack_lo);
591 ice_debug(hw, ICE_DBG_NVM, "Failed to read EETRACK lo.\n");
594 status = ice_read_nvm_sr_copy(hw, bank, ICE_SR_NVM_EETRACK_HI, &eetrack_hi);
596 ice_debug(hw, ICE_DBG_NVM, "Failed to read EETRACK hi.\n");
600 nvm->eetrack = (eetrack_hi << 16) | eetrack_lo;
602 status = ice_get_nvm_srev(hw, bank, &nvm->srev);
604 ice_debug(hw, ICE_DBG_NVM, "Failed to read NVM security revision.\n");
610 * ice_get_inactive_nvm_ver - Read Option ROM version from the inactive bank
611 * @hw: pointer to the HW structure
612 * @nvm: storage for Option ROM version information
614 * Reads the NVM EETRACK ID, Map version, and security revision of the
615 * inactive NVM bank. Used to access version data for a pending update that
616 * has not yet been activated.
618 enum ice_status ice_get_inactive_nvm_ver(struct ice_hw *hw, struct ice_nvm_info *nvm)
620 return ice_get_nvm_ver_info(hw, ICE_INACTIVE_FLASH_BANK, nvm);
624 * ice_get_orom_srev - Read the security revision from the OROM CSS header
625 * @hw: pointer to the HW struct
626 * @bank: whether to read from active or inactive flash module
627 * @srev: storage for security revision
629 * Read the security revision out of the CSS header of the active OROM module
632 static enum ice_status ice_get_orom_srev(struct ice_hw *hw, enum ice_bank_select bank, u32 *srev)
634 enum ice_status status;
638 if (hw->flash.banks.orom_size < ICE_NVM_OROM_TRAILER_LENGTH) {
639 ice_debug(hw, ICE_DBG_NVM, "Unexpected Option ROM Size of %u\n",
640 hw->flash.banks.orom_size);
644 /* calculate how far into the Option ROM the CSS header starts. Note
645 * that ice_read_orom_module takes a word offset so we need to
648 css_start = (hw->flash.banks.orom_size - ICE_NVM_OROM_TRAILER_LENGTH) / 2;
650 status = ice_read_orom_module(hw, bank, css_start + ICE_NVM_CSS_SREV_L, &srev_l);
654 status = ice_read_orom_module(hw, bank, css_start + ICE_NVM_CSS_SREV_H, &srev_h);
658 *srev = srev_h << 16 | srev_l;
664 * ice_get_orom_civd_data - Get the combo version information from Option ROM
665 * @hw: pointer to the HW struct
666 * @bank: whether to read from the active or inactive flash module
667 * @civd: storage for the Option ROM CIVD data.
669 * Searches through the Option ROM flash contents to locate the CIVD data for
672 static enum ice_status
673 ice_get_orom_civd_data(struct ice_hw *hw, enum ice_bank_select bank,
674 struct ice_orom_civd_info *civd)
676 struct ice_orom_civd_info tmp;
677 enum ice_status status;
680 /* The CIVD section is located in the Option ROM aligned to 512 bytes.
681 * The first 4 bytes must contain the ASCII characters "$CIV".
682 * A simple modulo 256 sum of all of the bytes of the structure must
685 for (offset = 0; (offset + 512) <= hw->flash.banks.orom_size; offset += 512) {
688 status = ice_read_flash_module(hw, bank, ICE_SR_1ST_OROM_BANK_PTR,
689 offset, (u8 *)&tmp, sizeof(tmp));
691 ice_debug(hw, ICE_DBG_NVM, "Unable to read Option ROM CIVD data\n");
695 /* Skip forward until we find a matching signature */
696 if (memcmp("$CIV", tmp.signature, sizeof(tmp.signature)) != 0)
699 /* Verify that the simple checksum is zero */
700 for (i = 0; i < sizeof(tmp); i++)
701 sum += ((u8 *)&tmp)[i];
704 ice_debug(hw, ICE_DBG_NVM, "Found CIVD data with invalid checksum of %u\n",
717 * ice_get_orom_ver_info - Read Option ROM version information
718 * @hw: pointer to the HW struct
719 * @bank: whether to read from the active or inactive flash module
720 * @orom: pointer to Option ROM info structure
722 * Read Option ROM version and security revision from the Option ROM flash
725 static enum ice_status
726 ice_get_orom_ver_info(struct ice_hw *hw, enum ice_bank_select bank, struct ice_orom_info *orom)
728 struct ice_orom_civd_info civd;
729 enum ice_status status;
732 status = ice_get_orom_civd_data(hw, bank, &civd);
734 ice_debug(hw, ICE_DBG_NVM, "Failed to locate valid Option ROM CIVD data\n");
738 combo_ver = LE32_TO_CPU(civd.combo_ver);
740 orom->major = (u8)((combo_ver & ICE_OROM_VER_MASK) >> ICE_OROM_VER_SHIFT);
741 orom->patch = (u8)(combo_ver & ICE_OROM_VER_PATCH_MASK);
742 orom->build = (u16)((combo_ver & ICE_OROM_VER_BUILD_MASK) >> ICE_OROM_VER_BUILD_SHIFT);
744 status = ice_get_orom_srev(hw, bank, &orom->srev);
746 ice_debug(hw, ICE_DBG_NVM, "Failed to read Option ROM security revision.\n");
754 * ice_get_inactive_orom_ver - Read Option ROM version from the inactive bank
755 * @hw: pointer to the HW structure
756 * @orom: storage for Option ROM version information
758 * Reads the Option ROM version and security revision data for the inactive
759 * section of flash. Used to access version data for a pending update that has
760 * not yet been activated.
762 enum ice_status ice_get_inactive_orom_ver(struct ice_hw *hw, struct ice_orom_info *orom)
764 return ice_get_orom_ver_info(hw, ICE_INACTIVE_FLASH_BANK, orom);
768 * ice_discover_flash_size - Discover the available flash size.
769 * @hw: pointer to the HW struct
771 * The device flash could be up to 16MB in size. However, it is possible that
772 * the actual size is smaller. Use bisection to determine the accessible size
775 static enum ice_status ice_discover_flash_size(struct ice_hw *hw)
777 u32 min_size = 0, max_size = ICE_AQC_NVM_MAX_OFFSET + 1;
778 enum ice_status status;
780 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
782 status = ice_acquire_nvm(hw, ICE_RES_READ);
786 while ((max_size - min_size) > 1) {
787 u32 offset = (max_size + min_size) / 2;
791 status = ice_read_flat_nvm(hw, offset, &len, &data, false);
792 if (status == ICE_ERR_AQ_ERROR &&
793 hw->adminq.sq_last_status == ICE_AQ_RC_EINVAL) {
794 ice_debug(hw, ICE_DBG_NVM, "%s: New upper bound of %u bytes\n",
796 status = ICE_SUCCESS;
798 } else if (!status) {
799 ice_debug(hw, ICE_DBG_NVM, "%s: New lower bound of %u bytes\n",
803 /* an unexpected error occurred */
804 goto err_read_flat_nvm;
808 ice_debug(hw, ICE_DBG_NVM, "Predicted flash size is %u bytes\n", max_size);
810 hw->flash.flash_size = max_size;
819 * ice_read_sr_pointer - Read the value of a Shadow RAM pointer word
820 * @hw: pointer to the HW structure
821 * @offset: the word offset of the Shadow RAM word to read
822 * @pointer: pointer value read from Shadow RAM
824 * Read the given Shadow RAM word, and convert it to a pointer value specified
825 * in bytes. This function assumes the specified offset is a valid pointer
828 * Each pointer word specifies whether it is stored in word size or 4KB
829 * sector size by using the highest bit. The reported pointer value will be in
830 * bytes, intended for flat NVM reads.
832 static enum ice_status
833 ice_read_sr_pointer(struct ice_hw *hw, u16 offset, u32 *pointer)
835 enum ice_status status;
838 status = ice_read_sr_word(hw, offset, &value);
842 /* Determine if the pointer is in 4KB or word units */
843 if (value & ICE_SR_NVM_PTR_4KB_UNITS)
844 *pointer = (value & ~ICE_SR_NVM_PTR_4KB_UNITS) * 4 * 1024;
846 *pointer = value * 2;
852 * ice_read_sr_area_size - Read an area size from a Shadow RAM word
853 * @hw: pointer to the HW structure
854 * @offset: the word offset of the Shadow RAM to read
855 * @size: size value read from the Shadow RAM
857 * Read the given Shadow RAM word, and convert it to an area size value
858 * specified in bytes. This function assumes the specified offset is a valid
861 * Each area size word is specified in 4KB sector units. This function reports
862 * the size in bytes, intended for flat NVM reads.
864 static enum ice_status
865 ice_read_sr_area_size(struct ice_hw *hw, u16 offset, u32 *size)
867 enum ice_status status;
870 status = ice_read_sr_word(hw, offset, &value);
874 /* Area sizes are always specified in 4KB units */
875 *size = value * 4 * 1024;
881 * ice_determine_active_flash_banks - Discover active bank for each module
882 * @hw: pointer to the HW struct
884 * Read the Shadow RAM control word and determine which banks are active for
885 * the NVM, OROM, and Netlist modules. Also read and calculate the associated
886 * pointer and size. These values are then cached into the ice_flash_info
887 * structure for later use in order to calculate the correct offset to read
888 * from the active module.
890 static enum ice_status
891 ice_determine_active_flash_banks(struct ice_hw *hw)
893 struct ice_bank_info *banks = &hw->flash.banks;
894 enum ice_status status;
897 status = ice_read_sr_word(hw, ICE_SR_NVM_CTRL_WORD, &ctrl_word);
899 ice_debug(hw, ICE_DBG_NVM, "Failed to read the Shadow RAM control word\n");
903 /* Check that the control word indicates validity */
904 if ((ctrl_word & ICE_SR_CTRL_WORD_1_M) >> ICE_SR_CTRL_WORD_1_S != ICE_SR_CTRL_WORD_VALID) {
905 ice_debug(hw, ICE_DBG_NVM, "Shadow RAM control word is invalid\n");
909 if (!(ctrl_word & ICE_SR_CTRL_WORD_NVM_BANK))
910 banks->nvm_bank = ICE_1ST_FLASH_BANK;
912 banks->nvm_bank = ICE_2ND_FLASH_BANK;
914 if (!(ctrl_word & ICE_SR_CTRL_WORD_OROM_BANK))
915 banks->orom_bank = ICE_1ST_FLASH_BANK;
917 banks->orom_bank = ICE_2ND_FLASH_BANK;
919 if (!(ctrl_word & ICE_SR_CTRL_WORD_NETLIST_BANK))
920 banks->netlist_bank = ICE_1ST_FLASH_BANK;
922 banks->netlist_bank = ICE_2ND_FLASH_BANK;
924 status = ice_read_sr_pointer(hw, ICE_SR_1ST_NVM_BANK_PTR, &banks->nvm_ptr);
926 ice_debug(hw, ICE_DBG_NVM, "Failed to read NVM bank pointer\n");
930 status = ice_read_sr_area_size(hw, ICE_SR_NVM_BANK_SIZE, &banks->nvm_size);
932 ice_debug(hw, ICE_DBG_NVM, "Failed to read NVM bank area size\n");
936 status = ice_read_sr_pointer(hw, ICE_SR_1ST_OROM_BANK_PTR, &banks->orom_ptr);
938 ice_debug(hw, ICE_DBG_NVM, "Failed to read OROM bank pointer\n");
942 status = ice_read_sr_area_size(hw, ICE_SR_OROM_BANK_SIZE, &banks->orom_size);
944 ice_debug(hw, ICE_DBG_NVM, "Failed to read OROM bank area size\n");
948 status = ice_read_sr_pointer(hw, ICE_SR_NETLIST_BANK_PTR, &banks->netlist_ptr);
950 ice_debug(hw, ICE_DBG_NVM, "Failed to read Netlist bank pointer\n");
954 status = ice_read_sr_area_size(hw, ICE_SR_NETLIST_BANK_SIZE, &banks->netlist_size);
956 ice_debug(hw, ICE_DBG_NVM, "Failed to read Netlist bank area size\n");
964 * ice_init_nvm - initializes NVM setting
965 * @hw: pointer to the HW struct
967 * This function reads and populates NVM settings such as Shadow RAM size,
968 * max_timeout, and blank_nvm_mode
970 enum ice_status ice_init_nvm(struct ice_hw *hw)
972 struct ice_flash_info *flash = &hw->flash;
973 enum ice_status status;
977 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
979 /* The SR size is stored regardless of the NVM programming mode
980 * as the blank mode may be used in the factory line.
982 gens_stat = rd32(hw, GLNVM_GENS);
983 sr_size = (gens_stat & GLNVM_GENS_SR_SIZE_M) >> GLNVM_GENS_SR_SIZE_S;
985 /* Switching to words (sr_size contains power of 2) */
986 flash->sr_words = BIT(sr_size) * ICE_SR_WORDS_IN_1KB;
988 /* Check if we are in the normal or blank NVM programming mode */
989 fla = rd32(hw, GLNVM_FLA);
990 if (fla & GLNVM_FLA_LOCKED_M) { /* Normal programming mode */
991 flash->blank_nvm_mode = false;
993 /* Blank programming mode */
994 flash->blank_nvm_mode = true;
995 ice_debug(hw, ICE_DBG_NVM, "NVM init error: unsupported blank mode.\n");
996 return ICE_ERR_NVM_BLANK_MODE;
999 status = ice_discover_flash_size(hw);
1001 ice_debug(hw, ICE_DBG_NVM, "NVM init error: failed to discover flash size.\n");
1005 status = ice_determine_active_flash_banks(hw);
1007 ice_debug(hw, ICE_DBG_NVM, "Failed to determine active flash banks.\n");
1011 status = ice_get_nvm_ver_info(hw, ICE_ACTIVE_FLASH_BANK, &flash->nvm);
1013 ice_debug(hw, ICE_DBG_INIT, "Failed to read NVM info.\n");
1017 status = ice_get_orom_ver_info(hw, ICE_ACTIVE_FLASH_BANK, &flash->orom);
1019 ice_debug(hw, ICE_DBG_INIT, "Failed to read Option ROM info.\n");
1025 * ice_read_sr_buf - Reads Shadow RAM buf and acquire lock if necessary
1026 * @hw: pointer to the HW structure
1027 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF)
1028 * @words: (in) number of words to read; (out) number of words actually read
1029 * @data: words read from the Shadow RAM
1031 * Reads 16 bit words (data buf) from the SR using the ice_read_nvm_buf_aq
1032 * method. The buf read is preceded by the NVM ownership take
1033 * and followed by the release.
1036 ice_read_sr_buf(struct ice_hw *hw, u16 offset, u16 *words, u16 *data)
1038 enum ice_status status;
1040 status = ice_acquire_nvm(hw, ICE_RES_READ);
1042 status = ice_read_sr_buf_aq(hw, offset, words, data);
1043 ice_release_nvm(hw);
1050 * ice_nvm_validate_checksum
1051 * @hw: pointer to the HW struct
1053 * Verify NVM PFA checksum validity (0x0706)
1055 enum ice_status ice_nvm_validate_checksum(struct ice_hw *hw)
1057 struct ice_aqc_nvm_checksum *cmd;
1058 struct ice_aq_desc desc;
1059 enum ice_status status;
1061 status = ice_acquire_nvm(hw, ICE_RES_READ);
1065 cmd = &desc.params.nvm_checksum;
1067 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_nvm_checksum);
1068 cmd->flags = ICE_AQC_NVM_CHECKSUM_VERIFY;
1070 status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
1071 ice_release_nvm(hw);
1074 if (LE16_TO_CPU(cmd->checksum) != ICE_AQC_NVM_CHECKSUM_CORRECT)
1075 status = ICE_ERR_NVM_CHECKSUM;
1081 * ice_nvm_recalculate_checksum
1082 * @hw: pointer to the HW struct
1084 * Recalculate NVM PFA checksum (0x0706)
1086 enum ice_status ice_nvm_recalculate_checksum(struct ice_hw *hw)
1088 struct ice_aqc_nvm_checksum *cmd;
1089 struct ice_aq_desc desc;
1090 enum ice_status status;
1092 status = ice_acquire_nvm(hw, ICE_RES_READ);
1096 cmd = &desc.params.nvm_checksum;
1098 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_nvm_checksum);
1099 cmd->flags = ICE_AQC_NVM_CHECKSUM_RECALC;
1101 status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
1103 ice_release_nvm(hw);
1109 * ice_nvm_access_get_features - Return the NVM access features structure
1110 * @cmd: NVM access command to process
1111 * @data: storage for the driver NVM features
1113 * Fill in the data section of the NVM access request with a copy of the NVM
1114 * features structure.
1117 ice_nvm_access_get_features(struct ice_nvm_access_cmd *cmd,
1118 union ice_nvm_access_data *data)
1120 /* The provided data_size must be at least as large as our NVM
1121 * features structure. A larger size should not be treated as an
1122 * error, to allow future extensions to the features structure to
1123 * work on older drivers.
1125 if (cmd->data_size < sizeof(struct ice_nvm_features))
1126 return ICE_ERR_NO_MEMORY;
1128 /* Initialize the data buffer to zeros */
1129 ice_memset(data, 0, cmd->data_size, ICE_NONDMA_MEM);
1131 /* Fill in the features data */
1132 data->drv_features.major = ICE_NVM_ACCESS_MAJOR_VER;
1133 data->drv_features.minor = ICE_NVM_ACCESS_MINOR_VER;
1134 data->drv_features.size = sizeof(struct ice_nvm_features);
1135 data->drv_features.features[0] = ICE_NVM_FEATURES_0_REG_ACCESS;
1141 * ice_nvm_access_get_module - Helper function to read module value
1142 * @cmd: NVM access command structure
1144 * Reads the module value out of the NVM access config field.
1146 u32 ice_nvm_access_get_module(struct ice_nvm_access_cmd *cmd)
1148 return ((cmd->config & ICE_NVM_CFG_MODULE_M) >> ICE_NVM_CFG_MODULE_S);
1152 * ice_nvm_access_get_flags - Helper function to read flags value
1153 * @cmd: NVM access command structure
1155 * Reads the flags value out of the NVM access config field.
1157 u32 ice_nvm_access_get_flags(struct ice_nvm_access_cmd *cmd)
1159 return ((cmd->config & ICE_NVM_CFG_FLAGS_M) >> ICE_NVM_CFG_FLAGS_S);
1163 * ice_nvm_access_get_adapter - Helper function to read adapter info
1164 * @cmd: NVM access command structure
1166 * Read the adapter info value out of the NVM access config field.
1168 u32 ice_nvm_access_get_adapter(struct ice_nvm_access_cmd *cmd)
1170 return ((cmd->config & ICE_NVM_CFG_ADAPTER_INFO_M) >>
1171 ICE_NVM_CFG_ADAPTER_INFO_S);
1175 * ice_validate_nvm_rw_reg - Check than an NVM access request is valid
1176 * @cmd: NVM access command structure
1178 * Validates that an NVM access structure is request to read or write a valid
1179 * register offset. First validates that the module and flags are correct, and
1180 * then ensures that the register offset is one of the accepted registers.
1182 static enum ice_status
1183 ice_validate_nvm_rw_reg(struct ice_nvm_access_cmd *cmd)
1185 u32 module, flags, offset;
1188 module = ice_nvm_access_get_module(cmd);
1189 flags = ice_nvm_access_get_flags(cmd);
1190 offset = cmd->offset;
1192 /* Make sure the module and flags indicate a read/write request */
1193 if (module != ICE_NVM_REG_RW_MODULE ||
1194 flags != ICE_NVM_REG_RW_FLAGS ||
1195 cmd->data_size != FIELD_SIZEOF(union ice_nvm_access_data, regval))
1196 return ICE_ERR_PARAM;
1200 case GL_HICR_EN: /* Note, this register is read only */
1203 case GLGEN_CSR_DEBUG_C:
1205 case GLPCI_LBARCTRL:
1214 for (i = 0; i <= ICE_NVM_ACCESS_GL_HIDA_MAX; i++)
1215 if (offset == (u32)GL_HIDA(i))
1218 for (i = 0; i <= ICE_NVM_ACCESS_GL_HIBA_MAX; i++)
1219 if (offset == (u32)GL_HIBA(i))
1222 /* All other register offsets are not valid */
1223 return ICE_ERR_OUT_OF_RANGE;
1227 * ice_nvm_access_read - Handle an NVM read request
1228 * @hw: pointer to the HW struct
1229 * @cmd: NVM access command to process
1230 * @data: storage for the register value read
1232 * Process an NVM access request to read a register.
1235 ice_nvm_access_read(struct ice_hw *hw, struct ice_nvm_access_cmd *cmd,
1236 union ice_nvm_access_data *data)
1238 enum ice_status status;
1240 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
1242 /* Always initialize the output data, even on failure */
1243 ice_memset(data, 0, cmd->data_size, ICE_NONDMA_MEM);
1245 /* Make sure this is a valid read/write access request */
1246 status = ice_validate_nvm_rw_reg(cmd);
1250 ice_debug(hw, ICE_DBG_NVM, "NVM access: reading register %08x\n",
1253 /* Read the register and store the contents in the data field */
1254 data->regval = rd32(hw, cmd->offset);
1260 * ice_nvm_access_write - Handle an NVM write request
1261 * @hw: pointer to the HW struct
1262 * @cmd: NVM access command to process
1263 * @data: NVM access data to write
1265 * Process an NVM access request to write a register.
1268 ice_nvm_access_write(struct ice_hw *hw, struct ice_nvm_access_cmd *cmd,
1269 union ice_nvm_access_data *data)
1271 enum ice_status status;
1273 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
1275 /* Make sure this is a valid read/write access request */
1276 status = ice_validate_nvm_rw_reg(cmd);
1280 /* Reject requests to write to read-only registers */
1281 switch (cmd->offset) {
1284 return ICE_ERR_OUT_OF_RANGE;
1289 ice_debug(hw, ICE_DBG_NVM, "NVM access: writing register %08x with value %08x\n",
1290 cmd->offset, data->regval);
1292 /* Write the data field to the specified register */
1293 wr32(hw, cmd->offset, data->regval);
1299 * ice_handle_nvm_access - Handle an NVM access request
1300 * @hw: pointer to the HW struct
1301 * @cmd: NVM access command info
1302 * @data: pointer to read or return data
1304 * Process an NVM access request. Read the command structure information and
1305 * determine if it is valid. If not, report an error indicating the command
1308 * For valid commands, perform the necessary function, copying the data into
1309 * the provided data buffer.
1312 ice_handle_nvm_access(struct ice_hw *hw, struct ice_nvm_access_cmd *cmd,
1313 union ice_nvm_access_data *data)
1315 u32 module, flags, adapter_info;
1317 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
1319 /* Extended flags are currently reserved and must be zero */
1320 if ((cmd->config & ICE_NVM_CFG_EXT_FLAGS_M) != 0)
1321 return ICE_ERR_PARAM;
1323 /* Adapter info must match the HW device ID */
1324 adapter_info = ice_nvm_access_get_adapter(cmd);
1325 if (adapter_info != hw->device_id)
1326 return ICE_ERR_PARAM;
1328 switch (cmd->command) {
1329 case ICE_NVM_CMD_READ:
1330 module = ice_nvm_access_get_module(cmd);
1331 flags = ice_nvm_access_get_flags(cmd);
1333 /* Getting the driver's NVM features structure shares the same
1334 * command type as reading a register. Read the config field
1335 * to determine if this is a request to get features.
1337 if (module == ICE_NVM_GET_FEATURES_MODULE &&
1338 flags == ICE_NVM_GET_FEATURES_FLAGS &&
1340 return ice_nvm_access_get_features(cmd, data);
1342 return ice_nvm_access_read(hw, cmd, data);
1343 case ICE_NVM_CMD_WRITE:
1344 return ice_nvm_access_write(hw, cmd, data);
1346 return ICE_ERR_PARAM;